2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
56 enum modifier_priority
{
57 MODIFIER_PRIORITY_INVALID
= 0,
58 MODIFIER_PRIORITY_LINEAR
,
61 MODIFIER_PRIORITY_Y_CCS
,
64 static const uint64_t priority_to_modifier
[] = {
65 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
66 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
67 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
68 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
69 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
73 modifier_is_supported(const struct gen_device_info
*devinfo
,
74 enum pipe_format pfmt
, uint64_t modifier
)
76 /* XXX: do something real */
78 case I915_FORMAT_MOD_Y_TILED_CCS
: {
79 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
82 enum isl_format rt_format
=
83 iris_format_for_usage(devinfo
, pfmt
,
84 ISL_SURF_USAGE_RENDER_TARGET_BIT
).fmt
;
86 enum isl_format linear_format
= isl_format_srgb_to_linear(rt_format
);
88 if (!isl_format_supports_ccs_e(devinfo
, linear_format
))
91 return devinfo
->gen
>= 9 && devinfo
->gen
<= 11;
93 case I915_FORMAT_MOD_Y_TILED
:
94 case I915_FORMAT_MOD_X_TILED
:
95 case DRM_FORMAT_MOD_LINEAR
:
97 case DRM_FORMAT_MOD_INVALID
:
104 select_best_modifier(struct gen_device_info
*devinfo
, enum pipe_format pfmt
,
105 const uint64_t *modifiers
,
108 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
110 for (int i
= 0; i
< count
; i
++) {
111 if (!modifier_is_supported(devinfo
, pfmt
, modifiers
[i
]))
114 switch (modifiers
[i
]) {
115 case I915_FORMAT_MOD_Y_TILED_CCS
:
116 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
118 case I915_FORMAT_MOD_Y_TILED
:
119 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
121 case I915_FORMAT_MOD_X_TILED
:
122 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
124 case DRM_FORMAT_MOD_LINEAR
:
125 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
127 case DRM_FORMAT_MOD_INVALID
:
133 return priority_to_modifier
[prio
];
137 target_to_isl_surf_dim(enum pipe_texture_target target
)
141 case PIPE_TEXTURE_1D
:
142 case PIPE_TEXTURE_1D_ARRAY
:
143 return ISL_SURF_DIM_1D
;
144 case PIPE_TEXTURE_2D
:
145 case PIPE_TEXTURE_CUBE
:
146 case PIPE_TEXTURE_RECT
:
147 case PIPE_TEXTURE_2D_ARRAY
:
148 case PIPE_TEXTURE_CUBE_ARRAY
:
149 return ISL_SURF_DIM_2D
;
150 case PIPE_TEXTURE_3D
:
151 return ISL_SURF_DIM_3D
;
152 case PIPE_MAX_TEXTURE_TYPES
:
155 unreachable("invalid texture type");
159 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
160 enum pipe_format pfmt
,
163 unsigned int *external_only
,
166 struct iris_screen
*screen
= (void *) pscreen
;
167 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
169 uint64_t all_modifiers
[] = {
170 DRM_FORMAT_MOD_LINEAR
,
171 I915_FORMAT_MOD_X_TILED
,
172 I915_FORMAT_MOD_Y_TILED
,
173 I915_FORMAT_MOD_Y_TILED_CCS
,
176 int supported_mods
= 0;
178 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
179 if (!modifier_is_supported(devinfo
, pfmt
, all_modifiers
[i
]))
182 if (supported_mods
< max
) {
184 modifiers
[supported_mods
] = all_modifiers
[i
];
187 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
193 *count
= supported_mods
;
196 static isl_surf_usage_flags_t
197 pipe_bind_to_isl_usage(unsigned bindings
)
199 isl_surf_usage_flags_t usage
= 0;
201 if (bindings
& PIPE_BIND_RENDER_TARGET
)
202 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
204 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
205 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
207 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
208 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
210 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
211 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
216 struct pipe_resource
*
217 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
219 /* For packed depth-stencil, we treat depth as the primary resource
220 * and store S8 as the "second plane" resource.
222 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
230 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
231 struct pipe_resource
*stencil
)
233 assert(util_format_has_depth(util_format_description(p_res
->format
)));
234 pipe_resource_reference(&p_res
->next
, stencil
);
238 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
239 struct iris_resource
**out_z
,
240 struct iris_resource
**out_s
)
248 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
249 *out_z
= (void *) res
;
250 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
253 *out_s
= (void *) res
;
258 iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
259 enum isl_tiling tiling
,
260 enum pipe_texture_target target
)
263 case PIPE_TEXTURE_1D
:
264 case PIPE_TEXTURE_1D_ARRAY
:
265 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
266 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
268 case PIPE_TEXTURE_2D
:
269 case PIPE_TEXTURE_2D_ARRAY
:
270 case PIPE_TEXTURE_RECT
:
271 case PIPE_TEXTURE_CUBE
:
272 case PIPE_TEXTURE_CUBE_ARRAY
:
273 return ISL_DIM_LAYOUT_GEN4_2D
;
275 case PIPE_TEXTURE_3D
:
276 return (devinfo
->gen
>= 9 ?
277 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
279 case PIPE_MAX_TEXTURE_TYPES
:
283 unreachable("invalid texture type");
287 iris_resource_disable_aux(struct iris_resource
*res
)
289 iris_bo_unreference(res
->aux
.bo
);
290 iris_bo_unreference(res
->aux
.extra_aux
.bo
);
291 iris_bo_unreference(res
->aux
.clear_color_bo
);
292 free(res
->aux
.state
);
294 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
295 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
296 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
297 res
->aux
.has_hiz
= 0;
298 res
->aux
.surf
.size_B
= 0;
300 res
->aux
.extra_aux
.surf
.size_B
= 0;
301 res
->aux
.extra_aux
.bo
= NULL
;
302 res
->aux
.clear_color_bo
= NULL
;
303 res
->aux
.state
= NULL
;
307 iris_resource_destroy(struct pipe_screen
*screen
,
308 struct pipe_resource
*resource
)
310 struct iris_resource
*res
= (struct iris_resource
*)resource
;
312 if (resource
->target
== PIPE_BUFFER
)
313 util_range_destroy(&res
->valid_buffer_range
);
315 iris_resource_disable_aux(res
);
317 iris_bo_unreference(res
->bo
);
321 static struct iris_resource
*
322 iris_alloc_resource(struct pipe_screen
*pscreen
,
323 const struct pipe_resource
*templ
)
325 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
330 res
->base
.screen
= pscreen
;
331 pipe_reference_init(&res
->base
.reference
, 1);
333 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
334 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
336 if (templ
->target
== PIPE_BUFFER
)
337 util_range_init(&res
->valid_buffer_range
);
343 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
345 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
346 return minify(res
->surf
.logical_level0_px
.depth
, level
);
348 return res
->surf
.logical_level0_px
.array_len
;
351 static enum isl_aux_state
**
352 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
354 uint32_t total_slices
= 0;
355 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
356 total_slices
+= iris_get_num_logical_layers(res
, level
);
358 const size_t per_level_array_size
=
359 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
361 /* We're going to allocate a single chunk of data for both the per-level
362 * reference array and the arrays of aux_state. This makes cleanup
363 * significantly easier.
365 const size_t total_size
=
366 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
368 void *data
= malloc(total_size
);
372 enum isl_aux_state
**per_level_arr
= data
;
373 enum isl_aux_state
*s
= data
+ per_level_array_size
;
374 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
375 per_level_arr
[level
] = s
;
376 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
377 for (uint32_t a
= 0; a
< level_layers
; a
++)
380 assert((void *)s
== data
+ total_size
);
382 return per_level_arr
;
386 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
388 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
389 return devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
: 0;
393 map_aux_addresses(struct iris_screen
*screen
, struct iris_resource
*res
)
395 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
396 if (devinfo
->gen
>= 12 && isl_aux_usage_has_ccs(res
->aux
.usage
)) {
397 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
399 const bool has_extra_ccs
= res
->aux
.extra_aux
.surf
.size_B
> 0;
400 struct iris_bo
*aux_bo
= has_extra_ccs
?
401 res
->aux
.extra_aux
.bo
: res
->aux
.bo
;
402 const unsigned aux_offset
= has_extra_ccs
?
403 res
->aux
.extra_aux
.offset
: res
->aux
.offset
;
404 gen_aux_map_add_image(aux_map_ctx
, &res
->surf
, res
->bo
->gtt_offset
,
405 aux_bo
->gtt_offset
+ aux_offset
);
406 res
->bo
->aux_map_address
= aux_bo
->gtt_offset
;
411 want_ccs_e_for_format(const struct gen_device_info
*devinfo
,
412 enum isl_format format
)
414 if (!isl_format_supports_ccs_e(devinfo
, format
))
417 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
419 /* CCS_E seems to significantly hurt performance with 32-bit floating
420 * point formats. For example, Paraview's "Wavelet Volume" case uses
421 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
422 * formats causes a 62% FPS drop.
424 * However, many benchmarks seem to use 16-bit float with no issues.
426 if (fmtl
->channels
.r
.bits
== 32 && fmtl
->channels
.r
.type
== ISL_SFLOAT
)
433 * Configure aux for the resource, but don't allocate it. For images which
434 * might be shared with modifiers, we must allocate the image and aux data in
438 iris_resource_configure_aux(struct iris_screen
*screen
,
439 struct iris_resource
*res
, bool imported
,
440 uint64_t *aux_size_B
,
441 uint32_t *alloc_flags
)
443 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
445 /* Try to create the auxiliary surfaces allowed by the modifier or by
446 * the user if no modifier is specified.
448 assert(!res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
||
449 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
451 const bool has_mcs
= !res
->mod_info
&&
452 isl_surf_get_mcs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
454 const bool has_hiz
= !res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_HIZ
) &&
455 isl_surf_get_hiz_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
458 ((!res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_RBC
)) ||
459 (res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)) &&
460 isl_surf_get_ccs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
,
461 &res
->aux
.extra_aux
.surf
, 0);
463 /* Having both HIZ and MCS is impossible. */
464 assert(!has_mcs
|| !has_hiz
);
466 /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
467 if (has_ccs
&& (has_mcs
|| has_hiz
)) {
468 assert(res
->aux
.extra_aux
.surf
.size_B
> 0 &&
469 res
->aux
.extra_aux
.surf
.usage
& ISL_SURF_USAGE_CCS_BIT
);
470 assert(res
->aux
.surf
.size_B
> 0 &&
471 res
->aux
.surf
.usage
&
472 (ISL_SURF_USAGE_HIZ_BIT
| ISL_SURF_USAGE_MCS_BIT
));
475 if (res
->mod_info
&& has_ccs
) {
476 /* Only allow a CCS modifier if the aux was created successfully. */
477 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
478 } else if (has_mcs
) {
479 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_MCS
;
480 } else if (has_hiz
) {
481 res
->aux
.possible_usages
|=
482 1 << (has_ccs
? ISL_AUX_USAGE_HIZ_CCS
: ISL_AUX_USAGE_HIZ
);
483 } else if (has_ccs
) {
484 if (want_ccs_e_for_format(devinfo
, res
->surf
.format
))
485 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
487 if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
488 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
491 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
493 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
495 /* We don't always support sampling with hiz. But when we do, it must be
498 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1)
499 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
501 /* We don't always support sampling with HIZ_CCS. But when we do, treat it
503 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ_CCS
);
504 if (isl_surf_supports_hiz_ccs_wt(devinfo
, &res
->surf
, res
->aux
.usage
))
505 res
->aux
.sampler_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
507 enum isl_aux_state initial_state
;
510 assert(!res
->aux
.bo
);
512 switch (res
->aux
.usage
) {
513 case ISL_AUX_USAGE_NONE
:
514 /* Having no aux buffer is only okay if there's no modifier with aux. */
515 return !res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
;
516 case ISL_AUX_USAGE_HIZ
:
517 case ISL_AUX_USAGE_HIZ_CCS
:
518 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
520 case ISL_AUX_USAGE_MCS
:
521 case ISL_AUX_USAGE_MCS_CCS
:
522 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
524 * "When MCS buffer is enabled and bound to MSRT, it is required
525 * that it is cleared prior to any rendering."
527 * Since we only use the MCS buffer for rendering, we just clear it
528 * immediately on allocation. The clear value for MCS buffers is all
529 * 1's, so we simply memset it to 0xff.
531 initial_state
= ISL_AUX_STATE_CLEAR
;
533 case ISL_AUX_USAGE_CCS_D
:
534 case ISL_AUX_USAGE_CCS_E
:
535 /* When CCS_E is used, we need to ensure that the CCS starts off in
536 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
539 * "If Software wants to enable Color Compression without Fast
540 * clear, Software needs to initialize MCS with zeros."
542 * A CCS value of 0 indicates that the corresponding block is in the
543 * pass-through state which is what we want.
545 * For CCS_D, do the same thing. On Gen9+, this avoids having any
546 * undefined bits in the aux buffer.
550 isl_drm_modifier_get_default_aux_state(res
->mod_info
->modifier
);
552 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
553 *alloc_flags
|= BO_ALLOC_ZEROED
;
557 if (!res
->aux
.state
) {
558 /* Create the aux_state for the auxiliary buffer. */
559 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
564 uint64_t size
= res
->aux
.surf
.size_B
;
566 /* Allocate space in the buffer for storing the CCS. */
567 if (res
->aux
.extra_aux
.surf
.size_B
> 0) {
568 res
->aux
.extra_aux
.offset
=
569 ALIGN(size
, res
->aux
.extra_aux
.surf
.alignment_B
);
570 size
= res
->aux
.extra_aux
.offset
+ res
->aux
.extra_aux
.surf
.size_B
;
573 /* Allocate space in the buffer for storing the clear color. On modern
574 * platforms (gen > 9), we can read it directly from such buffer.
576 * On gen <= 9, we are going to store the clear color on the buffer
577 * anyways, and copy it back to the surface state during state emission.
579 res
->aux
.clear_color_offset
= size
;
580 size
+= iris_get_aux_clear_color_state_size(screen
);
583 if (isl_aux_usage_has_hiz(res
->aux
.usage
)) {
584 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
585 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
586 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
588 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
589 * For LOD == 0, we can grow the dimensions to make it work.
591 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
592 res
->aux
.has_hiz
|= 1 << level
;
600 * Initialize the aux buffer contents.
603 iris_resource_init_aux_buf(struct iris_resource
*res
, uint32_t alloc_flags
,
604 unsigned clear_color_state_size
)
606 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
607 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
610 iris_resource_disable_aux(res
);
614 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
615 uint8_t memset_value
= isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0;
616 memset((char*)map
+ res
->aux
.offset
, memset_value
,
617 res
->aux
.surf
.size_B
);
620 /* Bspec section titled : MCS/CCS Buffers for Render Target(s) states:
621 * - If Software wants to enable Color Compression without Fast clear,
622 * Software needs to initialize MCS with zeros.
623 * - Lossless compression and CCS initialized to all F (using HW Fast
624 * Clear or SW direct Clear)
626 * We think, the first bullet point above is referring to CCS aux
627 * surface. Since we initialize the MCS in the clear state, we also
628 * initialize the CCS in the clear state (via SW direct clear) to keep
631 memset((char*)map
+ res
->aux
.extra_aux
.offset
,
632 isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0,
633 res
->aux
.extra_aux
.surf
.size_B
);
635 /* Zero the indirect clear color to match ::fast_clear_color. */
636 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
637 clear_color_state_size
);
639 iris_bo_unmap(res
->aux
.bo
);
642 if (res
->aux
.extra_aux
.surf
.size_B
> 0) {
643 res
->aux
.extra_aux
.bo
= res
->aux
.bo
;
644 iris_bo_reference(res
->aux
.extra_aux
.bo
);
647 if (clear_color_state_size
> 0) {
648 res
->aux
.clear_color_bo
= res
->aux
.bo
;
649 iris_bo_reference(res
->aux
.clear_color_bo
);
656 * Allocate the initial aux surface for a resource based on aux.usage
659 iris_resource_alloc_separate_aux(struct iris_screen
*screen
,
660 struct iris_resource
*res
)
662 uint32_t alloc_flags
;
664 if (!iris_resource_configure_aux(screen
, res
, false, &size
, &alloc_flags
))
670 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
671 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
672 * of bytes instead of trying to recalculate based on different format
675 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
, 4096,
677 isl_tiling_to_i915_tiling(res
->aux
.surf
.tiling
),
678 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
683 if (!iris_resource_init_aux_buf(res
, alloc_flags
,
684 iris_get_aux_clear_color_state_size(screen
)))
687 map_aux_addresses(screen
, res
);
693 iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
694 struct iris_resource
*res
)
696 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
697 assert(iris_resource_unfinished_aux_import(res
));
698 assert(!res
->mod_info
->supports_clear_color
);
700 struct iris_resource
*aux_res
= (void *) res
->base
.next
;
701 assert(aux_res
->aux
.surf
.row_pitch_B
&& aux_res
->aux
.offset
&&
704 assert(res
->bo
== aux_res
->aux
.bo
);
705 iris_bo_reference(aux_res
->aux
.bo
);
706 res
->aux
.bo
= aux_res
->aux
.bo
;
708 res
->aux
.offset
= aux_res
->aux
.offset
;
710 assert(res
->bo
->size
>= (res
->aux
.offset
+ res
->aux
.surf
.size_B
));
711 assert(res
->aux
.clear_color_bo
== NULL
);
712 res
->aux
.clear_color_offset
= 0;
714 assert(aux_res
->aux
.surf
.row_pitch_B
== res
->aux
.surf
.row_pitch_B
);
716 unsigned clear_color_state_size
=
717 iris_get_aux_clear_color_state_size(screen
);
719 if (clear_color_state_size
> 0) {
720 res
->aux
.clear_color_bo
=
721 iris_bo_alloc(screen
->bufmgr
, "clear color buffer",
722 clear_color_state_size
, IRIS_MEMZONE_OTHER
);
723 res
->aux
.clear_color_offset
= 0;
726 iris_resource_destroy(&screen
->base
, res
->base
.next
);
727 res
->base
.next
= NULL
;
730 static struct pipe_resource
*
731 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
732 const struct pipe_resource
*templ
)
734 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
735 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
737 assert(templ
->target
== PIPE_BUFFER
);
738 assert(templ
->height0
<= 1);
739 assert(templ
->depth0
<= 1);
740 assert(templ
->format
== PIPE_FORMAT_NONE
||
741 util_format_get_blocksize(templ
->format
) == 1);
743 res
->internal_format
= templ
->format
;
744 res
->surf
.tiling
= ISL_TILING_LINEAR
;
746 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
747 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
748 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
749 memzone
= IRIS_MEMZONE_SHADER
;
750 name
= "shader kernels";
751 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
752 memzone
= IRIS_MEMZONE_SURFACE
;
753 name
= "surface state";
754 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
755 memzone
= IRIS_MEMZONE_DYNAMIC
;
756 name
= "dynamic state";
759 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
761 iris_resource_destroy(pscreen
, &res
->base
);
768 static struct pipe_resource
*
769 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
770 const struct pipe_resource
*templ
,
771 const uint64_t *modifiers
,
774 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
775 struct gen_device_info
*devinfo
= &screen
->devinfo
;
776 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
781 const struct util_format_description
*format_desc
=
782 util_format_description(templ
->format
);
783 const bool has_depth
= util_format_has_depth(format_desc
);
785 select_best_modifier(devinfo
, templ
->format
, modifiers
, modifiers_count
);
787 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
789 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
790 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
792 tiling_flags
= 1 << res
->mod_info
->tiling
;
794 if (modifiers_count
> 0) {
795 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
799 /* Use linear for staging buffers */
800 if (templ
->usage
== PIPE_USAGE_STAGING
||
801 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
802 tiling_flags
= ISL_TILING_LINEAR_BIT
;
805 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
807 if (templ
->target
== PIPE_TEXTURE_CUBE
||
808 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
809 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
811 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
812 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
813 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
815 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
818 enum pipe_format pfmt
= templ
->format
;
819 res
->internal_format
= pfmt
;
821 /* Should be handled by u_transfer_helper */
822 assert(!util_format_is_depth_and_stencil(pfmt
));
824 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
825 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
827 UNUSED
const bool isl_surf_created_successfully
=
828 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
829 .dim
= target_to_isl_surf_dim(templ
->target
),
831 .width
= templ
->width0
,
832 .height
= templ
->height0
,
833 .depth
= templ
->depth0
,
834 .levels
= templ
->last_level
+ 1,
835 .array_len
= templ
->array_size
,
836 .samples
= MAX2(templ
->nr_samples
, 1),
837 .min_alignment_B
= 0,
840 .tiling_flags
= tiling_flags
);
841 assert(isl_surf_created_successfully
);
843 const char *name
= "miptree";
844 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
846 unsigned int flags
= 0;
847 if (templ
->usage
== PIPE_USAGE_STAGING
)
848 flags
|= BO_ALLOC_COHERENT
;
850 /* These are for u_upload_mgr buffers only */
851 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
852 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
853 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
855 uint32_t aux_preferred_alloc_flags
;
856 uint64_t aux_size
= 0;
858 iris_resource_configure_aux(screen
, res
, false, &aux_size
,
859 &aux_preferred_alloc_flags
);
860 aux_enabled
= aux_enabled
&& res
->aux
.surf
.size_B
> 0;
861 const bool separate_aux
= aux_enabled
&& !res
->mod_info
;
865 if (aux_enabled
&& !separate_aux
) {
866 /* Allocate aux data with main surface. This is required for modifiers
867 * with aux data (ccs).
869 aux_offset
= ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
);
870 bo_size
= aux_offset
+ aux_size
;
873 bo_size
= res
->surf
.size_B
;
876 uint32_t alignment
= MAX2(4096, res
->surf
.alignment_B
);
877 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, alignment
,
879 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
880 res
->surf
.row_pitch_B
, flags
);
887 if (!iris_resource_alloc_separate_aux(screen
, res
))
890 res
->aux
.bo
= res
->bo
;
891 iris_bo_reference(res
->aux
.bo
);
892 res
->aux
.offset
+= aux_offset
;
893 unsigned clear_color_state_size
=
894 iris_get_aux_clear_color_state_size(screen
);
895 if (clear_color_state_size
> 0)
896 res
->aux
.clear_color_offset
+= aux_offset
;
897 if (!iris_resource_init_aux_buf(res
, flags
, clear_color_state_size
))
899 map_aux_addresses(screen
, res
);
904 if (res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
907 iris_resource_disable_aux(res
);
913 fprintf(stderr
, "XXX: resource creation failed\n");
914 iris_resource_destroy(pscreen
, &res
->base
);
919 static struct pipe_resource
*
920 iris_resource_create(struct pipe_screen
*pscreen
,
921 const struct pipe_resource
*templ
)
923 if (templ
->target
== PIPE_BUFFER
)
924 return iris_resource_create_for_buffer(pscreen
, templ
);
926 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
930 tiling_to_modifier(uint32_t tiling
)
932 static const uint64_t map
[] = {
933 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
934 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
935 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
938 assert(tiling
< ARRAY_SIZE(map
));
943 static struct pipe_resource
*
944 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
945 const struct pipe_resource
*templ
,
948 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
949 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
950 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
954 assert(templ
->target
== PIPE_BUFFER
);
956 res
->internal_format
= templ
->format
;
957 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
958 user_memory
, templ
->width0
,
965 util_range_add(&res
->base
, &res
->valid_buffer_range
, 0, templ
->width0
);
970 static struct pipe_resource
*
971 iris_resource_from_handle(struct pipe_screen
*pscreen
,
972 const struct pipe_resource
*templ
,
973 struct winsys_handle
*whandle
,
976 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
977 struct gen_device_info
*devinfo
= &screen
->devinfo
;
978 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
979 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
983 switch (whandle
->type
) {
984 case WINSYS_HANDLE_TYPE_FD
:
985 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
);
987 case WINSYS_HANDLE_TYPE_SHARED
:
988 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
992 unreachable("invalid winsys handle type");
997 res
->offset
= whandle
->offset
;
999 uint64_t modifier
= whandle
->modifier
;
1000 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
1001 modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
1003 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
1004 assert(res
->mod_info
);
1006 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
1008 const struct iris_format_info fmt
=
1009 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
1010 res
->internal_format
= templ
->format
;
1012 if (templ
->target
== PIPE_BUFFER
) {
1013 res
->surf
.tiling
= ISL_TILING_LINEAR
;
1015 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
|| whandle
->plane
== 0) {
1016 UNUSED
const bool isl_surf_created_successfully
=
1017 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
1018 .dim
= target_to_isl_surf_dim(templ
->target
),
1020 .width
= templ
->width0
,
1021 .height
= templ
->height0
,
1022 .depth
= templ
->depth0
,
1023 .levels
= templ
->last_level
+ 1,
1024 .array_len
= templ
->array_size
,
1025 .samples
= MAX2(templ
->nr_samples
, 1),
1026 .min_alignment_B
= 0,
1027 .row_pitch_B
= whandle
->stride
,
1029 .tiling_flags
= 1 << res
->mod_info
->tiling
);
1030 assert(isl_surf_created_successfully
);
1031 assert(res
->bo
->tiling_mode
==
1032 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
1034 // XXX: create_ccs_buf_for_image?
1035 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
) {
1036 if (!iris_resource_alloc_separate_aux(screen
, res
))
1039 if (res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1040 uint32_t alloc_flags
;
1042 bool ok
= iris_resource_configure_aux(screen
, res
, true, &size
,
1045 /* The gallium dri layer will create a separate plane resource
1046 * for the aux image. iris_resource_finish_aux_import will
1047 * merge the separate aux parameters back into a single
1053 /* Save modifier import information to reconstruct later. After
1054 * import, this will be available under a second image accessible
1055 * from the main image with res->base.next. See
1056 * iris_resource_finish_aux_import.
1058 res
->aux
.surf
.row_pitch_B
= whandle
->stride
;
1059 res
->aux
.offset
= whandle
->offset
;
1060 res
->aux
.bo
= res
->bo
;
1068 iris_resource_destroy(pscreen
, &res
->base
);
1073 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
1075 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1076 struct iris_batch
*render_batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1077 struct iris_resource
*res
= (void *) resource
;
1078 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
1080 iris_resource_prepare_access(ice
, render_batch
, res
,
1081 0, INTEL_REMAINING_LEVELS
,
1082 0, INTEL_REMAINING_LAYERS
,
1083 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
1084 mod
? mod
->supports_clear_color
: false);
1088 iris_resource_disable_aux_on_first_query(struct pipe_resource
*resource
,
1091 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1093 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1095 /* Disable aux usage if explicit flush not set and this is the first time
1096 * we are dealing with this resource and the resource was not created with
1097 * a modifier with aux.
1099 if (!mod_with_aux
&&
1100 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0) &&
1101 p_atomic_read(&resource
->reference
.count
) == 1) {
1102 iris_resource_disable_aux(res
);
1107 iris_resource_get_param(struct pipe_screen
*screen
,
1108 struct pipe_context
*context
,
1109 struct pipe_resource
*resource
,
1112 enum pipe_resource_param param
,
1113 unsigned handle_usage
,
1116 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1118 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1119 bool wants_aux
= mod_with_aux
&& plane
> 0;
1123 if (iris_resource_unfinished_aux_import(res
))
1124 iris_resource_finish_aux_import(screen
, res
);
1126 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
1128 iris_resource_disable_aux_on_first_query(resource
, handle_usage
);
1131 case PIPE_RESOURCE_PARAM_NPLANES
:
1136 for (struct pipe_resource
*cur
= resource
; cur
; cur
= cur
->next
)
1141 case PIPE_RESOURCE_PARAM_STRIDE
:
1142 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
1144 case PIPE_RESOURCE_PARAM_OFFSET
:
1145 *value
= wants_aux
? res
->aux
.offset
: 0;
1147 case PIPE_RESOURCE_PARAM_MODIFIER
:
1148 *value
= res
->mod_info
? res
->mod_info
->modifier
:
1149 tiling_to_modifier(res
->bo
->tiling_mode
);
1151 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
1152 result
= iris_bo_flink(bo
, &handle
) == 0;
1156 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
1157 *value
= iris_bo_export_gem_handle(bo
);
1159 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
1160 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
1170 iris_resource_get_handle(struct pipe_screen
*pscreen
,
1171 struct pipe_context
*ctx
,
1172 struct pipe_resource
*resource
,
1173 struct winsys_handle
*whandle
,
1176 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1178 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1180 iris_resource_disable_aux_on_first_query(resource
, usage
);
1183 if (mod_with_aux
&& whandle
->plane
> 0) {
1184 assert(res
->aux
.bo
);
1186 whandle
->stride
= res
->aux
.surf
.row_pitch_B
;
1187 whandle
->offset
= res
->aux
.offset
;
1189 /* If this is a buffer, stride should be 0 - no need to special case */
1190 whandle
->stride
= res
->surf
.row_pitch_B
;
1194 res
->mod_info
? res
->mod_info
->modifier
1195 : tiling_to_modifier(res
->bo
->tiling_mode
);
1198 enum isl_aux_usage allowed_usage
=
1199 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1201 if (res
->aux
.usage
!= allowed_usage
) {
1202 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
1203 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
1204 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
1208 switch (whandle
->type
) {
1209 case WINSYS_HANDLE_TYPE_SHARED
:
1210 return iris_bo_flink(bo
, &whandle
->handle
) == 0;
1211 case WINSYS_HANDLE_TYPE_KMS
:
1212 whandle
->handle
= iris_bo_export_gem_handle(bo
);
1214 case WINSYS_HANDLE_TYPE_FD
:
1215 return iris_bo_export_dmabuf(bo
, (int *) &whandle
->handle
) == 0;
1222 resource_is_busy(struct iris_context
*ice
,
1223 struct iris_resource
*res
)
1225 bool busy
= iris_bo_busy(res
->bo
);
1227 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1228 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1234 iris_invalidate_resource(struct pipe_context
*ctx
,
1235 struct pipe_resource
*resource
)
1237 struct iris_screen
*screen
= (void *) ctx
->screen
;
1238 struct iris_context
*ice
= (void *) ctx
;
1239 struct iris_resource
*res
= (void *) resource
;
1241 if (resource
->target
!= PIPE_BUFFER
)
1244 if (!resource_is_busy(ice
, res
)) {
1245 /* The resource is idle, so just mark that it contains no data and
1246 * keep using the same underlying buffer object.
1248 util_range_set_empty(&res
->valid_buffer_range
);
1252 /* Otherwise, try and replace the backing storage with a new BO. */
1254 /* We can't reallocate memory we didn't allocate in the first place. */
1255 if (res
->bo
->userptr
)
1258 // XXX: We should support this.
1259 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1262 struct iris_bo
*old_bo
= res
->bo
;
1263 struct iris_bo
*new_bo
=
1264 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1265 iris_memzone_for_address(old_bo
->gtt_offset
));
1269 /* Swap out the backing storage */
1272 /* Rebind the buffer, replacing any state referring to the old BO's
1273 * address, and marking state dirty so it's reemitted.
1275 ice
->vtbl
.rebind_buffer(ice
, res
, old_bo
->gtt_offset
);
1277 util_range_set_empty(&res
->valid_buffer_range
);
1279 iris_bo_unreference(old_bo
);
1283 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1284 const struct pipe_box
*flush_box
)
1286 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1289 struct iris_transfer
*map
= (void *) xfer
;
1291 struct pipe_box src_box
= *flush_box
;
1293 /* Account for extra alignment padding in staging buffer */
1294 if (xfer
->resource
->target
== PIPE_BUFFER
)
1295 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1297 struct pipe_box dst_box
= (struct pipe_box
) {
1298 .x
= xfer
->box
.x
+ flush_box
->x
,
1299 .y
= xfer
->box
.y
+ flush_box
->y
,
1300 .z
= xfer
->box
.z
+ flush_box
->z
,
1301 .width
= flush_box
->width
,
1302 .height
= flush_box
->height
,
1303 .depth
= flush_box
->depth
,
1306 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1307 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1312 iris_unmap_copy_region(struct iris_transfer
*map
)
1314 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1320 iris_map_copy_region(struct iris_transfer
*map
)
1322 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1323 struct pipe_transfer
*xfer
= &map
->base
;
1324 struct pipe_box
*box
= &xfer
->box
;
1325 struct iris_resource
*res
= (void *) xfer
->resource
;
1327 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1328 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1330 struct pipe_resource templ
= (struct pipe_resource
) {
1331 .usage
= PIPE_USAGE_STAGING
,
1332 .width0
= box
->width
+ extra
,
1333 .height0
= box
->height
,
1335 .nr_samples
= xfer
->resource
->nr_samples
,
1336 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1337 .array_size
= box
->depth
,
1338 .format
= res
->internal_format
,
1341 if (xfer
->resource
->target
== PIPE_BUFFER
)
1342 templ
.target
= PIPE_BUFFER
;
1343 else if (templ
.array_size
> 1)
1344 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1346 templ
.target
= PIPE_TEXTURE_2D
;
1348 map
->staging
= iris_resource_create(pscreen
, &templ
);
1349 assert(map
->staging
);
1351 if (templ
.target
!= PIPE_BUFFER
) {
1352 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1353 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1354 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1357 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1358 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1359 xfer
->resource
, xfer
->level
, box
);
1360 /* Ensure writes to the staging BO land before we map it below. */
1361 iris_emit_pipe_control_flush(map
->batch
,
1362 "transfer read: flush before mapping",
1363 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1364 PIPE_CONTROL_CS_STALL
);
1367 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1369 if (iris_batch_references(map
->batch
, staging_bo
))
1370 iris_batch_flush(map
->batch
);
1373 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1375 map
->unmap
= iris_unmap_copy_region
;
1379 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1380 unsigned *out_x0_el
, unsigned *out_y0_el
)
1382 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1383 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1385 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1390 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1391 * different tiling patterns.
1394 iris_resource_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1395 uint32_t *tile_w
, uint32_t *tile_h
)
1406 case ISL_TILING_LINEAR
:
1411 unreachable("not reached");
1417 * This function computes masks that may be used to select the bits of the X
1418 * and Y coordinates that indicate the offset within a tile. If the BO is
1419 * untiled, the masks are set to 0.
1422 iris_resource_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1423 uint32_t *mask_x
, uint32_t *mask_y
)
1425 uint32_t tile_w_bytes
, tile_h
;
1427 iris_resource_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1429 *mask_x
= tile_w_bytes
/ cpp
- 1;
1430 *mask_y
= tile_h
- 1;
1434 * Compute the offset (in bytes) from the start of the BO to the given x
1435 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1436 * multiples of the tile size.
1439 iris_resource_get_aligned_offset(const struct iris_resource
*res
,
1440 uint32_t x
, uint32_t y
)
1442 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1443 unsigned cpp
= fmtl
->bpb
/ 8;
1444 uint32_t pitch
= res
->surf
.row_pitch_B
;
1446 switch (res
->surf
.tiling
) {
1448 unreachable("not reached");
1449 case ISL_TILING_LINEAR
:
1450 return y
* pitch
+ x
* cpp
;
1452 assert((x
% (512 / cpp
)) == 0);
1453 assert((y
% 8) == 0);
1454 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1456 assert((x
% (128 / cpp
)) == 0);
1457 assert((y
% 32) == 0);
1458 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1463 * Rendering with tiled buffers requires that the base address of the buffer
1464 * be aligned to a page boundary. For renderbuffers, and sometimes with
1465 * textures, we may want the surface to point at a texture image level that
1466 * isn't at a page boundary.
1468 * This function returns an appropriately-aligned base offset
1469 * according to the tiling restrictions, plus any required x/y offset
1473 iris_resource_get_tile_offsets(const struct iris_resource
*res
,
1474 uint32_t level
, uint32_t z
,
1475 uint32_t *tile_x
, uint32_t *tile_y
)
1478 uint32_t mask_x
, mask_y
;
1480 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1481 const unsigned cpp
= fmtl
->bpb
/ 8;
1483 iris_resource_get_tile_masks(res
->surf
.tiling
, cpp
, &mask_x
, &mask_y
);
1484 get_image_offset_el(&res
->surf
, level
, z
, &x
, &y
);
1486 *tile_x
= x
& mask_x
;
1487 *tile_y
= y
& mask_y
;
1489 return iris_resource_get_aligned_offset(res
, x
& ~mask_x
, y
& ~mask_y
);
1493 * Get pointer offset into stencil buffer.
1495 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1496 * must decode the tile's layout in software.
1499 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1501 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1503 * Even though the returned offset is always positive, the return type is
1505 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1506 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1509 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
)
1511 uint32_t tile_size
= 4096;
1512 uint32_t tile_width
= 64;
1513 uint32_t tile_height
= 64;
1514 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1516 uint32_t tile_x
= x
/ tile_width
;
1517 uint32_t tile_y
= y
/ tile_height
;
1519 /* The byte's address relative to the tile's base addres. */
1520 uint32_t byte_x
= x
% tile_width
;
1521 uint32_t byte_y
= y
% tile_height
;
1523 uintptr_t u
= tile_y
* row_size
1524 + tile_x
* tile_size
1525 + 512 * (byte_x
/ 8)
1527 + 32 * ((byte_y
/ 4) % 2)
1528 + 16 * ((byte_x
/ 4) % 2)
1529 + 8 * ((byte_y
/ 2) % 2)
1530 + 4 * ((byte_x
/ 2) % 2)
1538 iris_unmap_s8(struct iris_transfer
*map
)
1540 struct pipe_transfer
*xfer
= &map
->base
;
1541 const struct pipe_box
*box
= &xfer
->box
;
1542 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1543 struct isl_surf
*surf
= &res
->surf
;
1545 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1546 uint8_t *untiled_s8_map
= map
->ptr
;
1547 uint8_t *tiled_s8_map
=
1548 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1550 for (int s
= 0; s
< box
->depth
; s
++) {
1551 unsigned x0_el
, y0_el
;
1552 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1554 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1555 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1556 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1558 y0_el
+ box
->y
+ y
);
1559 tiled_s8_map
[offset
] =
1560 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1570 iris_map_s8(struct iris_transfer
*map
)
1572 struct pipe_transfer
*xfer
= &map
->base
;
1573 const struct pipe_box
*box
= &xfer
->box
;
1574 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1575 struct isl_surf
*surf
= &res
->surf
;
1577 xfer
->stride
= surf
->row_pitch_B
;
1578 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1580 /* The tiling and detiling functions require that the linear buffer has
1581 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1582 * over-allocate the linear buffer to get the proper alignment.
1584 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1585 assert(map
->buffer
);
1587 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1588 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1589 * invalidate is set, since we'll be writing the whole rectangle from our
1590 * temporary buffer back out.
1592 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1593 uint8_t *untiled_s8_map
= map
->ptr
;
1594 uint8_t *tiled_s8_map
=
1595 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1597 for (int s
= 0; s
< box
->depth
; s
++) {
1598 unsigned x0_el
, y0_el
;
1599 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1601 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1602 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1603 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1605 y0_el
+ box
->y
+ y
);
1606 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1607 tiled_s8_map
[offset
];
1613 map
->unmap
= iris_unmap_s8
;
1616 /* Compute extent parameters for use with tiled_memcpy functions.
1617 * xs are in units of bytes and ys are in units of strides.
1620 tile_extents(const struct isl_surf
*surf
,
1621 const struct pipe_box
*box
,
1622 unsigned level
, int z
,
1623 unsigned *x1_B
, unsigned *x2_B
,
1624 unsigned *y1_el
, unsigned *y2_el
)
1626 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1627 const unsigned cpp
= fmtl
->bpb
/ 8;
1629 assert(box
->x
% fmtl
->bw
== 0);
1630 assert(box
->y
% fmtl
->bh
== 0);
1632 unsigned x0_el
, y0_el
;
1633 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1635 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1636 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1637 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1638 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1642 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1644 struct pipe_transfer
*xfer
= &map
->base
;
1645 const struct pipe_box
*box
= &xfer
->box
;
1646 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1647 struct isl_surf
*surf
= &res
->surf
;
1649 const bool has_swizzling
= false;
1651 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1653 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1655 for (int s
= 0; s
< box
->depth
; s
++) {
1656 unsigned x1
, x2
, y1
, y2
;
1657 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1659 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1661 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1662 surf
->row_pitch_B
, xfer
->stride
,
1663 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1666 os_free_aligned(map
->buffer
);
1667 map
->buffer
= map
->ptr
= NULL
;
1671 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1673 struct pipe_transfer
*xfer
= &map
->base
;
1674 const struct pipe_box
*box
= &xfer
->box
;
1675 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1676 struct isl_surf
*surf
= &res
->surf
;
1678 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1679 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1681 unsigned x1
, x2
, y1
, y2
;
1682 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1684 /* The tiling and detiling functions require that the linear buffer has
1685 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1686 * over-allocate the linear buffer to get the proper alignment.
1689 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1690 assert(map
->buffer
);
1691 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1693 const bool has_swizzling
= false;
1695 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1697 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1699 for (int s
= 0; s
< box
->depth
; s
++) {
1700 unsigned x1
, x2
, y1
, y2
;
1701 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1703 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1704 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1706 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1707 surf
->row_pitch_B
, has_swizzling
,
1708 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1712 map
->unmap
= iris_unmap_tiled_memcpy
;
1716 iris_map_direct(struct iris_transfer
*map
)
1718 struct pipe_transfer
*xfer
= &map
->base
;
1719 struct pipe_box
*box
= &xfer
->box
;
1720 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1722 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1724 if (res
->base
.target
== PIPE_BUFFER
) {
1726 xfer
->layer_stride
= 0;
1728 map
->ptr
= ptr
+ box
->x
;
1730 struct isl_surf
*surf
= &res
->surf
;
1731 const struct isl_format_layout
*fmtl
=
1732 isl_format_get_layout(surf
->format
);
1733 const unsigned cpp
= fmtl
->bpb
/ 8;
1734 unsigned x0_el
, y0_el
;
1736 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1738 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1739 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1741 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1746 can_promote_to_async(const struct iris_resource
*res
,
1747 const struct pipe_box
*box
,
1748 enum pipe_transfer_usage usage
)
1750 /* If we're writing to a section of the buffer that hasn't even been
1751 * initialized with useful data, then we can safely promote this write
1752 * to be unsynchronized. This helps the common pattern of appending data.
1754 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1755 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1756 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1757 box
->x
+ box
->width
);
1761 iris_transfer_map(struct pipe_context
*ctx
,
1762 struct pipe_resource
*resource
,
1764 enum pipe_transfer_usage usage
,
1765 const struct pipe_box
*box
,
1766 struct pipe_transfer
**ptransfer
)
1768 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1769 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1770 struct isl_surf
*surf
= &res
->surf
;
1772 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1773 /* Replace the backing storage with a fresh buffer for non-async maps */
1774 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1775 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1776 iris_invalidate_resource(ctx
, resource
);
1778 /* If we can discard the whole resource, we can discard the range. */
1779 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1782 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1783 can_promote_to_async(res
, box
, usage
)) {
1784 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1787 bool need_resolve
= false;
1788 bool need_color_resolve
= false;
1790 if (resource
->target
!= PIPE_BUFFER
) {
1791 bool need_hiz_resolve
= iris_resource_level_has_hiz(res
, level
);
1793 need_color_resolve
=
1794 (res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
||
1795 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) &&
1796 iris_has_color_unresolved(res
, level
, 1, box
->z
, box
->depth
);
1798 need_resolve
= need_color_resolve
|| need_hiz_resolve
;
1801 bool map_would_stall
= false;
1803 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1804 map_would_stall
= need_resolve
|| resource_is_busy(ice
, res
);
1806 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1807 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1811 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1812 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1815 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1816 struct pipe_transfer
*xfer
= &map
->base
;
1821 memset(map
, 0, sizeof(*map
));
1822 map
->dbg
= &ice
->dbg
;
1824 pipe_resource_reference(&xfer
->resource
, resource
);
1825 xfer
->level
= level
;
1826 xfer
->usage
= usage
;
1830 map
->dest_had_defined_contents
=
1831 util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1832 box
->x
+ box
->width
);
1834 if (usage
& PIPE_TRANSFER_WRITE
)
1835 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1837 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1838 * there is to access them simultaneously on the CPU & GPU. This also
1839 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1840 * contain state we're constructing for a GPU draw call, which would
1841 * kill us with infinite stack recursion.
1843 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1844 PIPE_TRANSFER_COHERENT
|
1845 PIPE_TRANSFER_MAP_DIRECTLY
);
1847 /* GPU copies are not useful for buffer reads. Instead of stalling to
1848 * read from the original buffer, we'd simply copy it to a temporary...
1849 * then stall (a bit longer) to read from that buffer.
1851 * Images are less clear-cut. Color resolves are destructive, removing
1852 * the underlying compression, so we'd rather blit the data to a linear
1853 * temporary and map that, to avoid the resolve. (It might be better to
1854 * a tiled temporary and use the tiled_memcpy paths...)
1856 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) && !need_color_resolve
)
1859 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1860 if (fmtl
->txc
== ISL_TXC_ASTC
)
1863 if ((map_would_stall
|| res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) && !no_gpu
) {
1864 /* If we need a synchronous mapping and the resource is busy, or needs
1865 * resolving, we copy to/from a linear temporary buffer using the GPU.
1867 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1868 map
->blorp
= &ice
->blorp
;
1869 iris_map_copy_region(map
);
1871 /* Otherwise we're free to map on the CPU. */
1874 iris_resource_access_raw(ice
, &ice
->batches
[IRIS_BATCH_RENDER
], res
,
1875 level
, box
->z
, box
->depth
,
1876 usage
& PIPE_TRANSFER_WRITE
);
1879 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1880 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1881 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1882 iris_batch_flush(&ice
->batches
[i
]);
1886 if (surf
->tiling
== ISL_TILING_W
) {
1887 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1889 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1890 iris_map_tiled_memcpy(map
);
1892 iris_map_direct(map
);
1900 iris_transfer_flush_region(struct pipe_context
*ctx
,
1901 struct pipe_transfer
*xfer
,
1902 const struct pipe_box
*box
)
1904 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1905 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1906 struct iris_transfer
*map
= (void *) xfer
;
1909 iris_flush_staging_region(xfer
, box
);
1911 uint32_t history_flush
= 0;
1913 if (res
->base
.target
== PIPE_BUFFER
) {
1915 history_flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
1917 if (map
->dest_had_defined_contents
)
1918 history_flush
|= iris_flush_bits_for_history(res
);
1920 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1923 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
1924 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1925 struct iris_batch
*batch
= &ice
->batches
[i
];
1926 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
1927 iris_batch_maybe_flush(batch
, 24);
1928 iris_emit_pipe_control_flush(batch
,
1929 "cache history: transfer flush",
1935 /* Make sure we flag constants dirty even if there's no need to emit
1936 * any PIPE_CONTROLs to a batch.
1938 iris_dirty_for_history(ice
, res
);
1942 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1944 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1945 struct iris_transfer
*map
= (void *) xfer
;
1947 if (!(xfer
->usage
& (PIPE_TRANSFER_FLUSH_EXPLICIT
|
1948 PIPE_TRANSFER_COHERENT
))) {
1949 struct pipe_box flush_box
= {
1950 .x
= 0, .y
= 0, .z
= 0,
1951 .width
= xfer
->box
.width
,
1952 .height
= xfer
->box
.height
,
1953 .depth
= xfer
->box
.depth
,
1955 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
1961 pipe_resource_reference(&xfer
->resource
, NULL
);
1962 slab_free(&ice
->transfer_pool
, map
);
1966 * Mark state dirty that needs to be re-emitted when a resource is written.
1969 iris_dirty_for_history(struct iris_context
*ice
,
1970 struct iris_resource
*res
)
1972 uint64_t dirty
= 0ull;
1974 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1975 dirty
|= ((uint64_t)res
->bind_stages
) << IRIS_SHIFT_FOR_DIRTY_CONSTANTS
;
1978 ice
->state
.dirty
|= dirty
;
1982 * Produce a set of PIPE_CONTROL bits which ensure data written to a
1983 * resource becomes visible, and any stale read cache data is invalidated.
1986 iris_flush_bits_for_history(struct iris_resource
*res
)
1988 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
1990 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1991 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
1992 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1995 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
1996 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1998 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
1999 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
2001 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
2002 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
2008 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
2009 struct iris_batch
*batch
,
2010 struct iris_resource
*res
,
2011 uint32_t extra_flags
,
2014 if (res
->base
.target
!= PIPE_BUFFER
)
2017 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
2019 iris_emit_pipe_control_flush(batch
, reason
, flush
);
2021 iris_dirty_for_history(ice
, res
);
2025 iris_resource_set_clear_color(struct iris_context
*ice
,
2026 struct iris_resource
*res
,
2027 union isl_color_value color
)
2029 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
2030 res
->aux
.clear_color
= color
;
2037 union isl_color_value
2038 iris_resource_get_clear_color(const struct iris_resource
*res
,
2039 struct iris_bo
**clear_color_bo
,
2040 uint64_t *clear_color_offset
)
2042 assert(res
->aux
.bo
);
2045 *clear_color_bo
= res
->aux
.clear_color_bo
;
2046 if (clear_color_offset
)
2047 *clear_color_offset
= res
->aux
.clear_color_offset
;
2048 return res
->aux
.clear_color
;
2051 static enum pipe_format
2052 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
2054 struct iris_resource
*res
= (void *) p_res
;
2055 return res
->internal_format
;
2058 static const struct u_transfer_vtbl transfer_vtbl
= {
2059 .resource_create
= iris_resource_create
,
2060 .resource_destroy
= iris_resource_destroy
,
2061 .transfer_map
= iris_transfer_map
,
2062 .transfer_unmap
= iris_transfer_unmap
,
2063 .transfer_flush_region
= iris_transfer_flush_region
,
2064 .get_internal_format
= iris_resource_get_internal_format
,
2065 .set_stencil
= iris_resource_set_separate_stencil
,
2066 .get_stencil
= iris_resource_get_separate_stencil
,
2070 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
2072 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
2073 pscreen
->resource_create_with_modifiers
=
2074 iris_resource_create_with_modifiers
;
2075 pscreen
->resource_create
= u_transfer_helper_resource_create
;
2076 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
2077 pscreen
->resource_from_handle
= iris_resource_from_handle
;
2078 pscreen
->resource_get_handle
= iris_resource_get_handle
;
2079 pscreen
->resource_get_param
= iris_resource_get_param
;
2080 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
2081 pscreen
->transfer_helper
=
2082 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
2086 iris_init_resource_functions(struct pipe_context
*ctx
)
2088 ctx
->flush_resource
= iris_flush_resource
;
2089 ctx
->invalidate_resource
= iris_invalidate_resource
;
2090 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
2091 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
2092 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
2093 ctx
->buffer_subdata
= u_default_buffer_subdata
;
2094 ctx
->texture_subdata
= u_default_texture_subdata
;