2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * @file iris_resource.c
27 * Resources are images, buffers, and other objects used by the GPU.
29 * XXX: explain resources
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/os_memory.h"
39 #include "util/u_cpu_detect.h"
40 #include "util/u_inlines.h"
41 #include "util/u_format.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_debug.h"
52 #include "drm-uapi/drm_fourcc.h"
53 #include "drm-uapi/i915_drm.h"
55 // XXX: u_transfer_helper...for separate stencil...
57 enum modifier_priority
{
58 MODIFIER_PRIORITY_INVALID
= 0,
59 MODIFIER_PRIORITY_LINEAR
,
62 MODIFIER_PRIORITY_Y_CCS
,
65 static const uint64_t priority_to_modifier
[] = {
66 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
67 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
68 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
69 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
70 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
74 modifier_is_supported(const struct gen_device_info
*devinfo
,
77 /* XXX: do something real */
79 case I915_FORMAT_MOD_Y_TILED
:
80 case I915_FORMAT_MOD_X_TILED
:
81 case DRM_FORMAT_MOD_LINEAR
:
83 case I915_FORMAT_MOD_Y_TILED_CCS
:
84 case DRM_FORMAT_MOD_INVALID
:
91 select_best_modifier(struct gen_device_info
*devinfo
,
92 const uint64_t *modifiers
,
95 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
97 for (int i
= 0; i
< count
; i
++) {
98 if (!modifier_is_supported(devinfo
, modifiers
[i
]))
101 switch (modifiers
[i
]) {
102 case I915_FORMAT_MOD_Y_TILED_CCS
:
103 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
105 case I915_FORMAT_MOD_Y_TILED
:
106 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
108 case I915_FORMAT_MOD_X_TILED
:
109 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
111 case DRM_FORMAT_MOD_LINEAR
:
112 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
114 case DRM_FORMAT_MOD_INVALID
:
120 return priority_to_modifier
[prio
];
123 static enum isl_surf_dim
124 target_to_isl_surf_dim(enum pipe_texture_target target
)
128 case PIPE_TEXTURE_1D
:
129 case PIPE_TEXTURE_1D_ARRAY
:
130 return ISL_SURF_DIM_1D
;
131 case PIPE_TEXTURE_2D
:
132 case PIPE_TEXTURE_CUBE
:
133 case PIPE_TEXTURE_RECT
:
134 case PIPE_TEXTURE_2D_ARRAY
:
135 case PIPE_TEXTURE_CUBE_ARRAY
:
136 return ISL_SURF_DIM_2D
;
137 case PIPE_TEXTURE_3D
:
138 return ISL_SURF_DIM_3D
;
139 case PIPE_MAX_TEXTURE_TYPES
:
142 unreachable("invalid texture type");
145 static isl_surf_usage_flags_t
146 pipe_bind_to_isl_usage(unsigned bindings
)
148 isl_surf_usage_flags_t usage
= 0;
150 if (bindings
& PIPE_BIND_RENDER_TARGET
)
151 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
153 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
154 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
156 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
157 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
159 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
160 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
165 struct pipe_resource
*
166 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
168 /* For packed depth-stencil, we treat depth as the primary resource
169 * and store S8 as the "second plane" resource.
175 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
176 struct pipe_resource
*stencil
)
178 assert(util_format_has_depth(util_format_description(p_res
->format
)));
179 p_res
->next
= stencil
;
183 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
184 struct iris_resource
**out_z
,
185 struct iris_resource
**out_s
)
193 const struct util_format_description
*desc
=
194 util_format_description(res
->format
);
196 if (util_format_has_depth(desc
)) {
197 *out_z
= (void *) res
;
198 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
200 assert(util_format_has_stencil(desc
));
202 *out_s
= (void *) res
;
207 iris_resource_destroy(struct pipe_screen
*screen
,
208 struct pipe_resource
*resource
)
210 struct iris_resource
*res
= (struct iris_resource
*)resource
;
212 iris_bo_unreference(res
->bo
);
216 static struct iris_resource
*
217 iris_alloc_resource(struct pipe_screen
*pscreen
,
218 const struct pipe_resource
*templ
)
220 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
225 res
->base
.screen
= pscreen
;
226 pipe_reference_init(&res
->base
.reference
, 1);
231 static struct pipe_resource
*
232 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
233 const struct pipe_resource
*templ
,
234 const uint64_t *modifiers
,
237 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
238 struct gen_device_info
*devinfo
= &screen
->devinfo
;
239 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
240 const struct util_format_description
*format_desc
=
241 util_format_description(templ
->format
);
246 const bool has_depth
= util_format_has_depth(format_desc
);
247 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
249 if (modifiers_count
== 0 || !modifiers
) {
251 modifier
= I915_FORMAT_MOD_Y_TILED
;
252 } else if (templ
->bind
& PIPE_BIND_DISPLAY_TARGET
) {
253 /* Display is X-tiled for historical reasons. */
254 modifier
= I915_FORMAT_MOD_X_TILED
;
256 modifier
= I915_FORMAT_MOD_Y_TILED
;
258 /* XXX: make sure this doesn't do stupid things for internal textures */
261 if (templ
->target
== PIPE_BUFFER
|| templ
->usage
== PIPE_USAGE_STAGING
)
262 modifier
= DRM_FORMAT_MOD_LINEAR
;
264 if (templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
))
265 modifier
= DRM_FORMAT_MOD_LINEAR
;
267 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
268 /* User requested specific modifiers */
269 modifier
= select_best_modifier(devinfo
, modifiers
, modifiers_count
);
270 if (modifier
== DRM_FORMAT_MOD_INVALID
)
274 const struct isl_drm_modifier_info
*mod_info
=
275 isl_drm_modifier_get_info(modifier
);
277 enum isl_tiling tiling
= templ
->format
== PIPE_FORMAT_S8_UINT
?
278 ISL_TILING_W
: mod_info
->tiling
;
280 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
282 if (templ
->target
== PIPE_TEXTURE_CUBE
||
283 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
284 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
286 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
287 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
288 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
290 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
293 enum pipe_format pfmt
= templ
->format
;
294 res
->internal_format
= pfmt
;
296 /* Should be handled by u_transfer_helper */
297 assert(!util_format_is_depth_and_stencil(pfmt
));
299 enum isl_format isl_format
= iris_isl_format_for_pipe_format(pfmt
);
300 assert(isl_format
!= ISL_FORMAT_UNSUPPORTED
);
302 UNUSED
const bool isl_surf_created_successfully
=
303 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
304 .dim
= target_to_isl_surf_dim(templ
->target
),
305 .format
= isl_format
,
306 .width
= templ
->width0
,
307 .height
= templ
->height0
,
308 .depth
= templ
->depth0
,
309 .levels
= templ
->last_level
+ 1,
310 .array_len
= templ
->array_size
,
311 .samples
= MAX2(templ
->nr_samples
, 1),
312 .min_alignment_B
= 0,
315 .tiling_flags
= 1 << tiling
);
316 assert(isl_surf_created_successfully
);
318 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
319 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
320 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
321 memzone
= IRIS_MEMZONE_SHADER
;
322 name
= "shader kernels";
323 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
324 memzone
= IRIS_MEMZONE_SURFACE
;
325 name
= "surface state";
326 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
327 memzone
= IRIS_MEMZONE_DYNAMIC
;
328 name
= "dynamic state";
331 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, res
->surf
.size_B
,
333 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
334 res
->surf
.row_pitch_B
, 0);
341 iris_resource_destroy(pscreen
, &res
->base
);
345 static struct pipe_resource
*
346 iris_resource_create(struct pipe_screen
*pscreen
,
347 const struct pipe_resource
*templ
)
349 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
353 tiling_to_modifier(uint32_t tiling
)
355 static const uint64_t map
[] = {
356 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
357 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
358 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
361 assert(tiling
< ARRAY_SIZE(map
));
366 static struct pipe_resource
*
367 iris_resource_from_handle(struct pipe_screen
*pscreen
,
368 const struct pipe_resource
*templ
,
369 struct winsys_handle
*whandle
,
372 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
373 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
374 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
378 if (whandle
->offset
!= 0) {
379 dbg_printf("Attempt to import unsupported winsys offset %u\n",
384 switch (whandle
->type
) {
385 case WINSYS_HANDLE_TYPE_FD
:
386 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
);
388 case WINSYS_HANDLE_TYPE_SHARED
:
389 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
393 unreachable("invalid winsys handle type");
398 uint64_t modifier
= whandle
->modifier
;
399 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
400 modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
402 const struct isl_drm_modifier_info
*mod_info
=
403 isl_drm_modifier_get_info(modifier
);
407 isl_surf_usage_flags_t isl_usage
= ISL_SURF_USAGE_DISPLAY_BIT
;
409 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
410 .dim
= target_to_isl_surf_dim(templ
->target
),
411 .format
= iris_isl_format_for_pipe_format(templ
->format
),
412 .width
= templ
->width0
,
413 .height
= templ
->height0
,
414 .depth
= templ
->depth0
,
415 .levels
= templ
->last_level
+ 1,
416 .array_len
= templ
->array_size
,
417 .samples
= MAX2(templ
->nr_samples
, 1),
418 .min_alignment_B
= 0,
421 .tiling_flags
= 1 << mod_info
->tiling
);
423 assert(res
->bo
->tiling_mode
== isl_tiling_to_i915_tiling(res
->surf
.tiling
));
428 iris_resource_destroy(pscreen
, &res
->base
);
433 iris_resource_get_handle(struct pipe_screen
*pscreen
,
434 struct pipe_context
*ctx
,
435 struct pipe_resource
*resource
,
436 struct winsys_handle
*whandle
,
439 struct iris_resource
*res
= (struct iris_resource
*)resource
;
441 whandle
->stride
= res
->surf
.row_pitch_B
;
442 whandle
->modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
444 switch (whandle
->type
) {
445 case WINSYS_HANDLE_TYPE_SHARED
:
446 return iris_bo_flink(res
->bo
, &whandle
->handle
) == 0;
447 case WINSYS_HANDLE_TYPE_KMS
:
448 return iris_bo_export_gem_handle(res
->bo
) != 0;
449 case WINSYS_HANDLE_TYPE_FD
:
450 return iris_bo_export_dmabuf(res
->bo
, (int *) &whandle
->handle
) == 0;
457 get_image_offset_el(struct isl_surf
*surf
, unsigned level
, unsigned z
,
458 unsigned *out_x0_el
, unsigned *out_y0_el
)
460 if (surf
->dim
== ISL_SURF_DIM_3D
) {
461 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
463 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
468 * Get pointer offset into stencil buffer.
470 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
471 * must decode the tile's layout in software.
474 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
476 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
478 * Even though the returned offset is always positive, the return type is
480 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
481 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
484 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
486 uint32_t tile_size
= 4096;
487 uint32_t tile_width
= 64;
488 uint32_t tile_height
= 64;
489 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
491 uint32_t tile_x
= x
/ tile_width
;
492 uint32_t tile_y
= y
/ tile_height
;
494 /* The byte's address relative to the tile's base addres. */
495 uint32_t byte_x
= x
% tile_width
;
496 uint32_t byte_y
= y
% tile_height
;
498 uintptr_t u
= tile_y
* row_size
502 + 32 * ((byte_y
/ 4) % 2)
503 + 16 * ((byte_x
/ 4) % 2)
504 + 8 * ((byte_y
/ 2) % 2)
505 + 4 * ((byte_x
/ 2) % 2)
510 /* adjust for bit6 swizzling */
511 if (((byte_x
/ 8) % 2) == 1) {
512 if (((byte_y
/ 8) % 2) == 0) {
524 iris_unmap_s8(struct iris_transfer
*map
)
526 struct pipe_transfer
*xfer
= &map
->base
;
527 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
528 struct isl_surf
*surf
= &res
->surf
;
529 const bool has_swizzling
= false; // XXX: swizzling?
531 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
532 uint8_t *untiled_s8_map
= map
->ptr
;
533 uint8_t *tiled_s8_map
=
534 iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
536 struct pipe_box box
= xfer
->box
;
538 for (int s
= 0; s
< box
.depth
; s
++) {
539 unsigned x0_el
, y0_el
;
540 get_image_offset_el(surf
, xfer
->level
, box
.z
, &x0_el
, &y0_el
);
542 for (uint32_t y
= 0; y
< box
.height
; y
++) {
543 for (uint32_t x
= 0; x
< box
.width
; x
++) {
544 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
548 tiled_s8_map
[offset
] =
549 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
561 iris_map_s8(struct iris_transfer
*map
)
563 struct pipe_transfer
*xfer
= &map
->base
;
564 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
565 struct isl_surf
*surf
= &res
->surf
;
567 xfer
->stride
= surf
->row_pitch_B
;
568 xfer
->layer_stride
= xfer
->stride
* xfer
->box
.height
;
570 /* The tiling and detiling functions require that the linear buffer has
571 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
572 * over-allocate the linear buffer to get the proper alignment.
574 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* xfer
->box
.depth
);
577 const bool has_swizzling
= false; // XXX: swizzling?
579 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
580 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
581 * invalidate is set, since we'll be writing the whole rectangle from our
582 * temporary buffer back out.
584 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
585 uint8_t *untiled_s8_map
= map
->ptr
;
586 uint8_t *tiled_s8_map
=
587 iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
589 struct pipe_box box
= xfer
->box
;
591 for (int s
= 0; s
< box
.depth
; s
++) {
592 unsigned x0_el
, y0_el
;
593 get_image_offset_el(surf
, xfer
->level
, box
.z
, &x0_el
, &y0_el
);
595 for (uint32_t y
= 0; y
< box
.height
; y
++) {
596 for (uint32_t x
= 0; x
< box
.width
; x
++) {
597 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
601 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
602 tiled_s8_map
[offset
];
610 map
->unmap
= iris_unmap_s8
;
613 /* Compute extent parameters for use with tiled_memcpy functions.
614 * xs are in units of bytes and ys are in units of strides.
617 tile_extents(struct isl_surf
*surf
,
618 const struct pipe_box
*box
,
620 unsigned *x1_B
, unsigned *x2_B
,
621 unsigned *y1_el
, unsigned *y2_el
)
623 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
624 const unsigned cpp
= fmtl
->bpb
/ 8;
626 assert(box
->x
% fmtl
->bw
== 0);
627 assert(box
->y
% fmtl
->bh
== 0);
629 unsigned x0_el
, y0_el
;
630 get_image_offset_el(surf
, level
, box
->z
, &x0_el
, &y0_el
);
632 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
633 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
634 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
635 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
639 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
641 struct pipe_transfer
*xfer
= &map
->base
;
642 struct pipe_box box
= xfer
->box
;
643 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
644 struct isl_surf
*surf
= &res
->surf
;
646 const bool has_swizzling
= false; // XXX: swizzling?
648 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
649 char *dst
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
651 for (int s
= 0; s
< box
.depth
; s
++) {
652 unsigned x1
, x2
, y1
, y2
;
653 tile_extents(surf
, &box
, xfer
->level
, &x1
, &x2
, &y1
, &y2
);
655 void *ptr
= map
->ptr
+ box
.z
* xfer
->layer_stride
;
657 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
658 surf
->row_pitch_B
, xfer
->stride
,
659 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
663 os_free_aligned(map
->buffer
);
664 map
->buffer
= map
->ptr
= NULL
;
668 iris_map_tiled_memcpy(struct iris_transfer
*map
)
670 struct pipe_transfer
*xfer
= &map
->base
;
671 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
672 struct isl_surf
*surf
= &res
->surf
;
674 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
675 xfer
->layer_stride
= xfer
->stride
* xfer
->box
.height
;
677 unsigned x1
, x2
, y1
, y2
;
678 tile_extents(surf
, &xfer
->box
, xfer
->level
, &x1
, &x2
, &y1
, &y2
);
680 /* The tiling and detiling functions require that the linear buffer has
681 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
682 * over-allocate the linear buffer to get the proper alignment.
685 os_malloc_aligned(xfer
->layer_stride
* xfer
->box
.depth
, 16);
687 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
689 const bool has_swizzling
= false; // XXX: swizzling?
691 // XXX: PIPE_TRANSFER_READ?
692 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
693 char *src
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
695 struct pipe_box box
= xfer
->box
;
697 for (int s
= 0; s
< box
.depth
; s
++) {
698 unsigned x1
, x2
, y1
, y2
;
699 tile_extents(surf
, &box
, xfer
->level
, &x1
, &x2
, &y1
, &y2
);
701 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, map
->ptr
, src
,
702 xfer
->stride
, surf
->row_pitch_B
,
703 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
708 map
->unmap
= iris_unmap_tiled_memcpy
;
712 iris_map_direct(struct iris_transfer
*map
)
714 struct pipe_transfer
*xfer
= &map
->base
;
715 struct pipe_box
*box
= &xfer
->box
;
716 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
717 struct isl_surf
*surf
= &res
->surf
;
718 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
719 const unsigned cpp
= fmtl
->bpb
/ 8;
721 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
722 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
724 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
);
726 // XXX: level, layer, etc
727 assert(xfer
->level
== 0);
730 map
->ptr
= ptr
+ box
->y
* xfer
->stride
+ box
->x
* cpp
;
734 iris_transfer_map(struct pipe_context
*ctx
,
735 struct pipe_resource
*resource
,
737 enum pipe_transfer_usage usage
,
738 const struct pipe_box
*box
,
739 struct pipe_transfer
**ptransfer
)
741 struct iris_context
*ice
= (struct iris_context
*)ctx
;
742 struct iris_resource
*res
= (struct iris_resource
*)resource
;
743 struct isl_surf
*surf
= &res
->surf
;
745 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
746 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
749 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
750 iris_batch_references(&ice
->render_batch
, res
->bo
)) {
751 iris_batch_flush(&ice
->render_batch
);
754 if ((usage
& PIPE_TRANSFER_DONTBLOCK
) && iris_bo_busy(res
->bo
))
757 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
758 struct pipe_transfer
*xfer
= &map
->base
;
760 // PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
761 // PIPE_TRANSFER_DISCARD_RANGE
766 memset(map
, 0, sizeof(*map
));
767 map
->dbg
= &ice
->dbg
;
769 pipe_resource_reference(&xfer
->resource
, resource
);
775 xfer
->usage
&= (PIPE_TRANSFER_READ
|
776 PIPE_TRANSFER_WRITE
|
777 PIPE_TRANSFER_UNSYNCHRONIZED
|
778 PIPE_TRANSFER_PERSISTENT
|
779 PIPE_TRANSFER_COHERENT
|
780 PIPE_TRANSFER_DISCARD_RANGE
);
782 if (surf
->tiling
== ISL_TILING_W
) {
783 // XXX: just teach iris_map_tiled_memcpy about W tiling...
785 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
786 iris_map_tiled_memcpy(map
);
788 iris_map_direct(map
);
795 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
797 struct iris_context
*ice
= (struct iris_context
*)ctx
;
798 struct iris_transfer
*map
= (void *) xfer
;
799 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
800 struct isl_surf
*surf
= &res
->surf
;
805 /* XXX: big ol' hack! need to re-emit UBOs. want bind_history? */
806 if (surf
->tiling
== ISL_TILING_LINEAR
) {
807 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
| IRIS_DIRTY_BINDINGS_VS
808 | IRIS_DIRTY_CONSTANTS_TCS
| IRIS_DIRTY_BINDINGS_TCS
809 | IRIS_DIRTY_CONSTANTS_TES
| IRIS_DIRTY_BINDINGS_TES
810 | IRIS_DIRTY_CONSTANTS_GS
| IRIS_DIRTY_BINDINGS_GS
811 | IRIS_DIRTY_CONSTANTS_FS
| IRIS_DIRTY_BINDINGS_FS
;
814 pipe_resource_reference(&xfer
->resource
, NULL
);
815 slab_free(&ice
->transfer_pool
, map
);
819 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
823 static enum pipe_format
824 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
826 struct iris_resource
*res
= (void *) p_res
;
827 return res
->internal_format
;
830 static const struct u_transfer_vtbl transfer_vtbl
= {
831 .resource_create
= iris_resource_create
,
832 .resource_destroy
= iris_resource_destroy
,
833 .transfer_map
= iris_transfer_map
,
834 .transfer_unmap
= iris_transfer_unmap
,
835 .transfer_flush_region
= u_default_transfer_flush_region
,
836 .get_internal_format
= iris_resource_get_internal_format
,
837 .set_stencil
= iris_resource_set_separate_stencil
,
838 .get_stencil
= iris_resource_get_separate_stencil
,
842 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
844 pscreen
->resource_create_with_modifiers
=
845 iris_resource_create_with_modifiers
;
846 pscreen
->resource_create
= u_transfer_helper_resource_create
;
847 pscreen
->resource_from_handle
= iris_resource_from_handle
;
848 pscreen
->resource_get_handle
= iris_resource_get_handle
;
849 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
850 pscreen
->transfer_helper
=
851 u_transfer_helper_create(&transfer_vtbl
, true, true, false, false);
855 iris_init_resource_functions(struct pipe_context
*ctx
)
857 ctx
->flush_resource
= iris_flush_resource
;
858 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
859 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
860 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
861 ctx
->buffer_subdata
= u_default_buffer_subdata
;
862 ctx
->texture_subdata
= u_default_texture_subdata
;