2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/format/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
56 enum modifier_priority
{
57 MODIFIER_PRIORITY_INVALID
= 0,
58 MODIFIER_PRIORITY_LINEAR
,
61 MODIFIER_PRIORITY_Y_CCS
,
62 MODIFIER_PRIORITY_Y_GEN12_RC_CCS
,
65 static const uint64_t priority_to_modifier
[] = {
66 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
67 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
68 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
69 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
70 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
71 [MODIFIER_PRIORITY_Y_GEN12_RC_CCS
] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
,
75 modifier_is_supported(const struct gen_device_info
*devinfo
,
76 enum pipe_format pfmt
, uint64_t modifier
)
78 /* Check for basic device support. */
80 case DRM_FORMAT_MOD_LINEAR
:
81 case I915_FORMAT_MOD_X_TILED
:
82 case I915_FORMAT_MOD_Y_TILED
:
84 case I915_FORMAT_MOD_Y_TILED_CCS
:
85 if (devinfo
->gen
<= 8 || devinfo
->gen
>= 12)
88 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
:
89 if (devinfo
->gen
!= 12)
92 case DRM_FORMAT_MOD_INVALID
:
97 /* Check remaining requirements. */
99 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
:
100 case I915_FORMAT_MOD_Y_TILED_CCS
: {
101 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
104 enum isl_format rt_format
=
105 iris_format_for_usage(devinfo
, pfmt
,
106 ISL_SURF_USAGE_RENDER_TARGET_BIT
).fmt
;
108 if (rt_format
== ISL_FORMAT_UNSUPPORTED
||
109 !isl_format_supports_ccs_e(devinfo
, rt_format
))
121 select_best_modifier(struct gen_device_info
*devinfo
, enum pipe_format pfmt
,
122 const uint64_t *modifiers
,
125 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
127 for (int i
= 0; i
< count
; i
++) {
128 if (!modifier_is_supported(devinfo
, pfmt
, modifiers
[i
]))
131 switch (modifiers
[i
]) {
132 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
:
133 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_GEN12_RC_CCS
);
135 case I915_FORMAT_MOD_Y_TILED_CCS
:
136 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
138 case I915_FORMAT_MOD_Y_TILED
:
139 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
141 case I915_FORMAT_MOD_X_TILED
:
142 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
144 case DRM_FORMAT_MOD_LINEAR
:
145 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
147 case DRM_FORMAT_MOD_INVALID
:
153 return priority_to_modifier
[prio
];
157 target_to_isl_surf_dim(enum pipe_texture_target target
)
161 case PIPE_TEXTURE_1D
:
162 case PIPE_TEXTURE_1D_ARRAY
:
163 return ISL_SURF_DIM_1D
;
164 case PIPE_TEXTURE_2D
:
165 case PIPE_TEXTURE_CUBE
:
166 case PIPE_TEXTURE_RECT
:
167 case PIPE_TEXTURE_2D_ARRAY
:
168 case PIPE_TEXTURE_CUBE_ARRAY
:
169 return ISL_SURF_DIM_2D
;
170 case PIPE_TEXTURE_3D
:
171 return ISL_SURF_DIM_3D
;
172 case PIPE_MAX_TEXTURE_TYPES
:
175 unreachable("invalid texture type");
179 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
180 enum pipe_format pfmt
,
183 unsigned int *external_only
,
186 struct iris_screen
*screen
= (void *) pscreen
;
187 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
189 uint64_t all_modifiers
[] = {
190 DRM_FORMAT_MOD_LINEAR
,
191 I915_FORMAT_MOD_X_TILED
,
192 I915_FORMAT_MOD_Y_TILED
,
193 I915_FORMAT_MOD_Y_TILED_CCS
,
194 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
,
197 int supported_mods
= 0;
199 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
200 if (!modifier_is_supported(devinfo
, pfmt
, all_modifiers
[i
]))
203 if (supported_mods
< max
) {
205 modifiers
[supported_mods
] = all_modifiers
[i
];
208 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
214 *count
= supported_mods
;
217 static isl_surf_usage_flags_t
218 pipe_bind_to_isl_usage(unsigned bindings
)
220 isl_surf_usage_flags_t usage
= 0;
222 if (bindings
& PIPE_BIND_RENDER_TARGET
)
223 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
225 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
226 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
228 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
229 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
231 if (bindings
& PIPE_BIND_SCANOUT
)
232 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
238 iris_image_view_get_format(struct iris_context
*ice
,
239 const struct pipe_image_view
*img
)
241 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
242 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
244 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
245 enum isl_format isl_fmt
=
246 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
248 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
249 /* On Gen8, try to use typed surfaces reads (which support a
250 * limited number of formats), and if not possible, fall back
253 if (devinfo
->gen
== 8 &&
254 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
))
255 return ISL_FORMAT_RAW
;
257 return isl_lower_storage_image_format(devinfo
, isl_fmt
);
263 struct pipe_resource
*
264 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
266 /* For packed depth-stencil, we treat depth as the primary resource
267 * and store S8 as the "second plane" resource.
269 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
277 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
278 struct pipe_resource
*stencil
)
280 assert(util_format_has_depth(util_format_description(p_res
->format
)));
281 pipe_resource_reference(&p_res
->next
, stencil
);
285 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
286 struct iris_resource
**out_z
,
287 struct iris_resource
**out_s
)
295 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
296 *out_z
= (void *) res
;
297 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
300 *out_s
= (void *) res
;
305 iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
306 enum isl_tiling tiling
,
307 enum pipe_texture_target target
)
310 case PIPE_TEXTURE_1D
:
311 case PIPE_TEXTURE_1D_ARRAY
:
312 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
313 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
315 case PIPE_TEXTURE_2D
:
316 case PIPE_TEXTURE_2D_ARRAY
:
317 case PIPE_TEXTURE_RECT
:
318 case PIPE_TEXTURE_CUBE
:
319 case PIPE_TEXTURE_CUBE_ARRAY
:
320 return ISL_DIM_LAYOUT_GEN4_2D
;
322 case PIPE_TEXTURE_3D
:
323 return (devinfo
->gen
>= 9 ?
324 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
326 case PIPE_MAX_TEXTURE_TYPES
:
330 unreachable("invalid texture type");
334 iris_resource_disable_aux(struct iris_resource
*res
)
336 iris_bo_unreference(res
->aux
.bo
);
337 iris_bo_unreference(res
->aux
.clear_color_bo
);
338 free(res
->aux
.state
);
340 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
341 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
342 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
343 res
->aux
.has_hiz
= 0;
344 res
->aux
.surf
.size_B
= 0;
346 res
->aux
.extra_aux
.surf
.size_B
= 0;
347 res
->aux
.clear_color_bo
= NULL
;
348 res
->aux
.state
= NULL
;
352 iris_resource_destroy(struct pipe_screen
*screen
,
353 struct pipe_resource
*resource
)
355 struct iris_resource
*res
= (struct iris_resource
*)resource
;
357 if (resource
->target
== PIPE_BUFFER
)
358 util_range_destroy(&res
->valid_buffer_range
);
360 iris_resource_disable_aux(res
);
362 iris_bo_unreference(res
->bo
);
363 iris_pscreen_unref(res
->base
.screen
);
368 static struct iris_resource
*
369 iris_alloc_resource(struct pipe_screen
*pscreen
,
370 const struct pipe_resource
*templ
)
372 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
377 res
->base
.screen
= iris_pscreen_ref(pscreen
);
378 pipe_reference_init(&res
->base
.reference
, 1);
380 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
381 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
383 if (templ
->target
== PIPE_BUFFER
)
384 util_range_init(&res
->valid_buffer_range
);
390 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
392 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
393 return minify(res
->surf
.logical_level0_px
.depth
, level
);
395 return res
->surf
.logical_level0_px
.array_len
;
398 static enum isl_aux_state
**
399 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
401 assert(res
->aux
.state
== NULL
);
403 uint32_t total_slices
= 0;
404 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
405 total_slices
+= iris_get_num_logical_layers(res
, level
);
407 const size_t per_level_array_size
=
408 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
410 /* We're going to allocate a single chunk of data for both the per-level
411 * reference array and the arrays of aux_state. This makes cleanup
412 * significantly easier.
414 const size_t total_size
=
415 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
417 void *data
= malloc(total_size
);
421 enum isl_aux_state
**per_level_arr
= data
;
422 enum isl_aux_state
*s
= data
+ per_level_array_size
;
423 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
424 per_level_arr
[level
] = s
;
425 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
426 for (uint32_t a
= 0; a
< level_layers
; a
++)
429 assert((void *)s
== data
+ total_size
);
431 return per_level_arr
;
435 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
437 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
438 return devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
: 0;
442 map_aux_addresses(struct iris_screen
*screen
, struct iris_resource
*res
)
444 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
445 if (devinfo
->gen
>= 12 && isl_aux_usage_has_ccs(res
->aux
.usage
)) {
446 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
448 const unsigned aux_offset
= res
->aux
.extra_aux
.surf
.size_B
> 0 ?
449 res
->aux
.extra_aux
.offset
: res
->aux
.offset
;
450 gen_aux_map_add_image(aux_map_ctx
, &res
->surf
, res
->bo
->gtt_offset
,
451 res
->aux
.bo
->gtt_offset
+ aux_offset
);
452 res
->bo
->aux_map_address
= res
->aux
.bo
->gtt_offset
;
457 want_ccs_e_for_format(const struct gen_device_info
*devinfo
,
458 enum isl_format format
)
460 if (!isl_format_supports_ccs_e(devinfo
, format
))
463 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
465 /* CCS_E seems to significantly hurt performance with 32-bit floating
466 * point formats. For example, Paraview's "Wavelet Volume" case uses
467 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
468 * formats causes a 62% FPS drop.
470 * However, many benchmarks seem to use 16-bit float with no issues.
472 if (fmtl
->channels
.r
.bits
== 32 && fmtl
->channels
.r
.type
== ISL_SFLOAT
)
479 * Configure aux for the resource, but don't allocate it. For images which
480 * might be shared with modifiers, we must allocate the image and aux data in
483 * Returns false on unexpected error (e.g. allocation failed, or invalid
484 * configuration result).
487 iris_resource_configure_aux(struct iris_screen
*screen
,
488 struct iris_resource
*res
, bool imported
,
489 uint64_t *aux_size_B
,
490 uint32_t *alloc_flags
)
492 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
494 /* Try to create the auxiliary surfaces allowed by the modifier or by
495 * the user if no modifier is specified.
497 assert(!res
->mod_info
||
498 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
||
499 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
500 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_GEN12_CCS_E
);
502 const bool has_mcs
= !res
->mod_info
&&
503 isl_surf_get_mcs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
505 const bool has_hiz
= !res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_HIZ
) &&
506 isl_surf_get_hiz_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
509 ((!res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_RBC
)) ||
510 (res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)) &&
511 isl_surf_get_ccs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
,
512 &res
->aux
.extra_aux
.surf
, 0);
514 /* Having both HIZ and MCS is impossible. */
515 assert(!has_mcs
|| !has_hiz
);
517 /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
518 if (has_ccs
&& (has_mcs
|| has_hiz
)) {
519 assert(res
->aux
.extra_aux
.surf
.size_B
> 0 &&
520 res
->aux
.extra_aux
.surf
.usage
& ISL_SURF_USAGE_CCS_BIT
);
521 assert(res
->aux
.surf
.size_B
> 0 &&
522 res
->aux
.surf
.usage
&
523 (ISL_SURF_USAGE_HIZ_BIT
| ISL_SURF_USAGE_MCS_BIT
));
526 if (res
->mod_info
&& has_ccs
) {
527 /* Only allow a CCS modifier if the aux was created successfully. */
528 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
529 } else if (has_mcs
) {
530 res
->aux
.possible_usages
|=
531 1 << (has_ccs
? ISL_AUX_USAGE_MCS_CCS
: ISL_AUX_USAGE_MCS
);
532 } else if (has_hiz
) {
534 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
535 } else if (res
->surf
.samples
== 1 &&
536 (res
->surf
.usage
& ISL_SURF_USAGE_TEXTURE_BIT
)) {
537 /* If this resource is single-sampled and will be used as a texture,
538 * put the HiZ surface in write-through mode so that we can sample
541 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS_WT
;
543 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS
;
545 } else if (has_ccs
&& isl_surf_usage_is_stencil(res
->surf
.usage
)) {
546 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_STC_CCS
;
547 } else if (has_ccs
) {
548 if (want_ccs_e_for_format(devinfo
, res
->surf
.format
)) {
549 res
->aux
.possible_usages
|= devinfo
->gen
< 12 ?
550 1 << ISL_AUX_USAGE_CCS_E
: 1 << ISL_AUX_USAGE_GEN12_CCS_E
;
551 } else if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
)) {
552 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
556 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
558 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
560 /* We don't always support sampling with hiz. But when we do, it must be
563 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1)
564 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
566 /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
567 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ_CCS
);
569 enum isl_aux_state initial_state
;
572 assert(!res
->aux
.bo
);
574 switch (res
->aux
.usage
) {
575 case ISL_AUX_USAGE_NONE
:
576 /* Having no aux buffer is only okay if there's no modifier with aux. */
577 return !res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
;
578 case ISL_AUX_USAGE_HIZ
:
579 case ISL_AUX_USAGE_HIZ_CCS
:
580 case ISL_AUX_USAGE_HIZ_CCS_WT
:
581 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
583 case ISL_AUX_USAGE_MCS
:
584 case ISL_AUX_USAGE_MCS_CCS
:
585 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
587 * "When MCS buffer is enabled and bound to MSRT, it is required
588 * that it is cleared prior to any rendering."
590 * Since we only use the MCS buffer for rendering, we just clear it
591 * immediately on allocation. The clear value for MCS buffers is all
592 * 1's, so we simply memset it to 0xff.
594 initial_state
= ISL_AUX_STATE_CLEAR
;
596 case ISL_AUX_USAGE_CCS_D
:
597 case ISL_AUX_USAGE_CCS_E
:
598 case ISL_AUX_USAGE_GEN12_CCS_E
:
599 case ISL_AUX_USAGE_STC_CCS
:
600 /* When CCS_E is used, we need to ensure that the CCS starts off in
601 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
604 * "If Software wants to enable Color Compression without Fast
605 * clear, Software needs to initialize MCS with zeros."
607 * A CCS value of 0 indicates that the corresponding block is in the
608 * pass-through state which is what we want.
610 * For CCS_D, do the same thing. On Gen9+, this avoids having any
611 * undefined bits in the aux buffer.
614 assert(res
->aux
.usage
!= ISL_AUX_USAGE_STC_CCS
);
616 isl_drm_modifier_get_default_aux_state(res
->mod_info
->modifier
);
618 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
620 *alloc_flags
|= BO_ALLOC_ZEROED
;
622 case ISL_AUX_USAGE_MC
:
624 unreachable("Unsupported aux mode");
627 /* Create the aux_state for the auxiliary buffer. */
628 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
632 /* Increase the aux offset if the main and aux surfaces will share a BO. */
634 !res
->mod_info
|| res
->mod_info
->aux_usage
== res
->aux
.usage
?
635 ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
) : 0;
636 uint64_t size
= res
->aux
.surf
.size_B
;
638 /* Allocate space in the buffer for storing the CCS. */
639 if (res
->aux
.extra_aux
.surf
.size_B
> 0) {
640 const uint64_t padded_aux_size
=
641 ALIGN(size
, res
->aux
.extra_aux
.surf
.alignment_B
);
642 res
->aux
.extra_aux
.offset
= res
->aux
.offset
+ padded_aux_size
;
643 size
= padded_aux_size
+ res
->aux
.extra_aux
.surf
.size_B
;
646 /* Allocate space in the buffer for storing the clear color. On modern
647 * platforms (gen > 9), we can read it directly from such buffer.
649 * On gen <= 9, we are going to store the clear color on the buffer
650 * anyways, and copy it back to the surface state during state emission.
652 * Also add some padding to make sure the fast clear color state buffer
653 * starts at a 4K alignment. We believe that 256B might be enough, but due
654 * to lack of testing we will leave this as 4K for now.
656 size
= ALIGN(size
, 4096);
657 res
->aux
.clear_color_offset
= res
->aux
.offset
+ size
;
658 size
+= iris_get_aux_clear_color_state_size(screen
);
661 if (isl_aux_usage_has_hiz(res
->aux
.usage
)) {
662 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
663 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
664 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
666 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
667 * For LOD == 0, we can grow the dimensions to make it work.
669 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
670 res
->aux
.has_hiz
|= 1 << level
;
678 * Initialize the aux buffer contents.
680 * Returns false on unexpected error (e.g. mapping a BO failed).
683 iris_resource_init_aux_buf(struct iris_resource
*res
, uint32_t alloc_flags
,
684 unsigned clear_color_state_size
)
686 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
687 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
692 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
693 uint8_t memset_value
= isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0;
694 memset((char*)map
+ res
->aux
.offset
, memset_value
,
695 res
->aux
.surf
.size_B
);
698 memset((char*)map
+ res
->aux
.extra_aux
.offset
,
699 0, res
->aux
.extra_aux
.surf
.size_B
);
701 /* Zero the indirect clear color to match ::fast_clear_color. */
702 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
703 clear_color_state_size
);
705 iris_bo_unmap(res
->aux
.bo
);
708 if (clear_color_state_size
> 0) {
709 res
->aux
.clear_color_bo
= res
->aux
.bo
;
710 iris_bo_reference(res
->aux
.clear_color_bo
);
717 * Allocate the initial aux surface for a resource based on aux.usage
719 * Returns false on unexpected error (e.g. allocation failed, or invalid
720 * configuration result).
723 iris_resource_alloc_separate_aux(struct iris_screen
*screen
,
724 struct iris_resource
*res
)
726 uint32_t alloc_flags
;
728 if (!iris_resource_configure_aux(screen
, res
, false, &size
, &alloc_flags
))
734 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
735 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
736 * of bytes instead of trying to recalculate based on different format
739 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
, 4096,
741 isl_tiling_to_i915_tiling(res
->aux
.surf
.tiling
),
742 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
747 if (!iris_resource_init_aux_buf(res
, alloc_flags
,
748 iris_get_aux_clear_color_state_size(screen
)))
751 map_aux_addresses(screen
, res
);
757 iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
758 struct iris_resource
*res
)
760 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
761 assert(iris_resource_unfinished_aux_import(res
));
762 assert(!res
->mod_info
->supports_clear_color
);
764 struct iris_resource
*aux_res
= (void *) res
->base
.next
;
765 assert(aux_res
->aux
.surf
.row_pitch_B
&& aux_res
->aux
.offset
&&
768 assert(res
->bo
== aux_res
->aux
.bo
);
769 iris_bo_reference(aux_res
->aux
.bo
);
770 res
->aux
.bo
= aux_res
->aux
.bo
;
772 res
->aux
.offset
= aux_res
->aux
.offset
;
774 assert(res
->bo
->size
>= (res
->aux
.offset
+ res
->aux
.surf
.size_B
));
775 assert(res
->aux
.clear_color_bo
== NULL
);
776 res
->aux
.clear_color_offset
= 0;
778 assert(aux_res
->aux
.surf
.row_pitch_B
== res
->aux
.surf
.row_pitch_B
);
780 unsigned clear_color_state_size
=
781 iris_get_aux_clear_color_state_size(screen
);
783 if (clear_color_state_size
> 0) {
784 res
->aux
.clear_color_bo
=
785 iris_bo_alloc_tiled(screen
->bufmgr
, "clear color_buffer",
786 clear_color_state_size
, 1, IRIS_MEMZONE_OTHER
,
787 I915_TILING_NONE
, 0, BO_ALLOC_ZEROED
);
788 res
->aux
.clear_color_offset
= 0;
791 iris_resource_destroy(&screen
->base
, res
->base
.next
);
792 res
->base
.next
= NULL
;
794 map_aux_addresses(screen
, res
);
797 static struct pipe_resource
*
798 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
799 const struct pipe_resource
*templ
)
801 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
802 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
804 assert(templ
->target
== PIPE_BUFFER
);
805 assert(templ
->height0
<= 1);
806 assert(templ
->depth0
<= 1);
807 assert(templ
->format
== PIPE_FORMAT_NONE
||
808 util_format_get_blocksize(templ
->format
) == 1);
810 res
->internal_format
= templ
->format
;
811 res
->surf
.tiling
= ISL_TILING_LINEAR
;
813 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
814 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
815 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
816 memzone
= IRIS_MEMZONE_SHADER
;
817 name
= "shader kernels";
818 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
819 memzone
= IRIS_MEMZONE_SURFACE
;
820 name
= "surface state";
821 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
822 memzone
= IRIS_MEMZONE_DYNAMIC
;
823 name
= "dynamic state";
826 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
828 iris_resource_destroy(pscreen
, &res
->base
);
832 if (templ
->bind
& PIPE_BIND_SHARED
)
833 iris_bo_make_external(res
->bo
);
838 static struct pipe_resource
*
839 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
840 const struct pipe_resource
*templ
,
841 const uint64_t *modifiers
,
844 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
845 struct gen_device_info
*devinfo
= &screen
->devinfo
;
846 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
851 const struct util_format_description
*format_desc
=
852 util_format_description(templ
->format
);
853 const bool has_depth
= util_format_has_depth(format_desc
);
855 select_best_modifier(devinfo
, templ
->format
, modifiers
, modifiers_count
);
857 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
859 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
860 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
862 tiling_flags
= 1 << res
->mod_info
->tiling
;
864 if (modifiers_count
> 0) {
865 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
869 /* Use linear for staging buffers */
870 if (templ
->usage
== PIPE_USAGE_STAGING
||
871 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) ) {
872 tiling_flags
= ISL_TILING_LINEAR_BIT
;
873 } else if (templ
->bind
& PIPE_BIND_SCANOUT
) {
874 if (devinfo
->has_tiling_uapi
)
875 tiling_flags
= ISL_TILING_X_BIT
;
877 tiling_flags
= ISL_TILING_LINEAR_BIT
;
881 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
883 if (templ
->target
== PIPE_TEXTURE_CUBE
||
884 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
885 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
887 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
888 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
889 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
891 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
894 enum pipe_format pfmt
= templ
->format
;
895 res
->internal_format
= pfmt
;
897 /* Should be handled by u_transfer_helper */
898 assert(!util_format_is_depth_and_stencil(pfmt
));
900 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
901 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
903 UNUSED
const bool isl_surf_created_successfully
=
904 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
905 .dim
= target_to_isl_surf_dim(templ
->target
),
907 .width
= templ
->width0
,
908 .height
= templ
->height0
,
909 .depth
= templ
->depth0
,
910 .levels
= templ
->last_level
+ 1,
911 .array_len
= templ
->array_size
,
912 .samples
= MAX2(templ
->nr_samples
, 1),
913 .min_alignment_B
= 0,
916 .tiling_flags
= tiling_flags
);
917 assert(isl_surf_created_successfully
);
919 const char *name
= "miptree";
920 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
922 unsigned int flags
= 0;
923 if (templ
->usage
== PIPE_USAGE_STAGING
)
924 flags
|= BO_ALLOC_COHERENT
;
926 /* These are for u_upload_mgr buffers only */
927 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
928 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
929 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
931 uint32_t aux_preferred_alloc_flags
;
932 uint64_t aux_size
= 0;
933 if (!iris_resource_configure_aux(screen
, res
, false, &aux_size
,
934 &aux_preferred_alloc_flags
)) {
938 /* Modifiers require the aux data to be in the same buffer as the main
939 * surface, but we combine them even when a modifiers is not being used.
941 const uint64_t bo_size
=
942 MAX2(res
->surf
.size_B
, res
->aux
.offset
+ aux_size
);
943 uint32_t alignment
= MAX2(4096, res
->surf
.alignment_B
);
944 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, alignment
,
946 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
947 res
->surf
.row_pitch_B
, flags
);
953 res
->aux
.bo
= res
->bo
;
954 iris_bo_reference(res
->aux
.bo
);
955 unsigned clear_color_state_size
=
956 iris_get_aux_clear_color_state_size(screen
);
957 if (!iris_resource_init_aux_buf(res
, flags
, clear_color_state_size
))
959 map_aux_addresses(screen
, res
);
962 if (templ
->bind
& PIPE_BIND_SHARED
)
963 iris_bo_make_external(res
->bo
);
968 fprintf(stderr
, "XXX: resource creation failed\n");
969 iris_resource_destroy(pscreen
, &res
->base
);
974 static struct pipe_resource
*
975 iris_resource_create(struct pipe_screen
*pscreen
,
976 const struct pipe_resource
*templ
)
978 if (templ
->target
== PIPE_BUFFER
)
979 return iris_resource_create_for_buffer(pscreen
, templ
);
981 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
985 tiling_to_modifier(uint32_t tiling
)
987 static const uint64_t map
[] = {
988 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
989 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
990 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
993 assert(tiling
< ARRAY_SIZE(map
));
998 static struct pipe_resource
*
999 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
1000 const struct pipe_resource
*templ
,
1003 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
1004 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1005 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
1009 assert(templ
->target
== PIPE_BUFFER
);
1011 res
->internal_format
= templ
->format
;
1012 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
1013 user_memory
, templ
->width0
,
1014 IRIS_MEMZONE_OTHER
);
1016 iris_resource_destroy(pscreen
, &res
->base
);
1020 util_range_add(&res
->base
, &res
->valid_buffer_range
, 0, templ
->width0
);
1025 static struct pipe_resource
*
1026 iris_resource_from_handle(struct pipe_screen
*pscreen
,
1027 const struct pipe_resource
*templ
,
1028 struct winsys_handle
*whandle
,
1031 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
1032 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1033 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1034 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
1035 const struct isl_drm_modifier_info
*mod_inf
=
1036 isl_drm_modifier_get_info(whandle
->modifier
);
1042 switch (whandle
->type
) {
1043 case WINSYS_HANDLE_TYPE_FD
:
1045 tiling
= isl_tiling_to_i915_tiling(mod_inf
->tiling
);
1048 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
,
1049 tiling
, whandle
->stride
);
1051 case WINSYS_HANDLE_TYPE_SHARED
:
1052 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
1056 unreachable("invalid winsys handle type");
1061 res
->offset
= whandle
->offset
;
1063 if (mod_inf
== NULL
) {
1065 isl_drm_modifier_get_info(tiling_to_modifier(res
->bo
->tiling_mode
));
1069 res
->external_format
= whandle
->format
;
1070 res
->mod_info
= mod_inf
;
1072 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
1074 const struct iris_format_info fmt
=
1075 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
1076 res
->internal_format
= templ
->format
;
1078 if (templ
->target
== PIPE_BUFFER
) {
1079 res
->surf
.tiling
= ISL_TILING_LINEAR
;
1081 /* Create a surface for each plane specified by the external format. */
1082 if (whandle
->plane
< util_format_get_num_planes(whandle
->format
)) {
1083 UNUSED
const bool isl_surf_created_successfully
=
1084 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
1085 .dim
= target_to_isl_surf_dim(templ
->target
),
1087 .width
= templ
->width0
,
1088 .height
= templ
->height0
,
1089 .depth
= templ
->depth0
,
1090 .levels
= templ
->last_level
+ 1,
1091 .array_len
= templ
->array_size
,
1092 .samples
= MAX2(templ
->nr_samples
, 1),
1093 .min_alignment_B
= 0,
1094 .row_pitch_B
= whandle
->stride
,
1096 .tiling_flags
= 1 << res
->mod_info
->tiling
);
1097 assert(isl_surf_created_successfully
);
1098 assert(res
->bo
->tiling_mode
==
1099 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
1101 // XXX: create_ccs_buf_for_image?
1102 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
) {
1103 if (!iris_resource_alloc_separate_aux(screen
, res
))
1106 if (res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1107 uint32_t alloc_flags
;
1109 bool ok
= iris_resource_configure_aux(screen
, res
, true, &size
,
1112 /* The gallium dri layer will create a separate plane resource
1113 * for the aux image. iris_resource_finish_aux_import will
1114 * merge the separate aux parameters back into a single
1120 /* Save modifier import information to reconstruct later. After
1121 * import, this will be available under a second image accessible
1122 * from the main image with res->base.next. See
1123 * iris_resource_finish_aux_import.
1125 res
->aux
.surf
.row_pitch_B
= whandle
->stride
;
1126 res
->aux
.offset
= whandle
->offset
;
1127 res
->aux
.bo
= res
->bo
;
1135 iris_resource_destroy(pscreen
, &res
->base
);
1140 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
1142 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1143 struct iris_resource
*res
= (void *) resource
;
1144 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
1146 iris_resource_prepare_access(ice
, res
,
1147 0, INTEL_REMAINING_LEVELS
,
1148 0, INTEL_REMAINING_LAYERS
,
1149 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
1150 mod
? mod
->supports_clear_color
: false);
1154 iris_resource_disable_aux_on_first_query(struct pipe_resource
*resource
,
1157 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1159 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1161 /* Disable aux usage if explicit flush not set and this is the first time
1162 * we are dealing with this resource and the resource was not created with
1163 * a modifier with aux.
1165 if (!mod_with_aux
&&
1166 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0) &&
1167 p_atomic_read(&resource
->reference
.count
) == 1) {
1168 iris_resource_disable_aux(res
);
1173 iris_resource_get_param(struct pipe_screen
*pscreen
,
1174 struct pipe_context
*context
,
1175 struct pipe_resource
*resource
,
1178 enum pipe_resource_param param
,
1179 unsigned handle_usage
,
1182 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
1183 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1185 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1186 bool wants_aux
= mod_with_aux
&& plane
> 0;
1190 if (iris_resource_unfinished_aux_import(res
))
1191 iris_resource_finish_aux_import(pscreen
, res
);
1193 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
1195 iris_resource_disable_aux_on_first_query(resource
, handle_usage
);
1198 case PIPE_RESOURCE_PARAM_NPLANES
:
1203 for (struct pipe_resource
*cur
= resource
; cur
; cur
= cur
->next
)
1208 case PIPE_RESOURCE_PARAM_STRIDE
:
1209 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
1211 case PIPE_RESOURCE_PARAM_OFFSET
:
1212 *value
= wants_aux
? res
->aux
.offset
: 0;
1214 case PIPE_RESOURCE_PARAM_MODIFIER
:
1215 *value
= res
->mod_info
? res
->mod_info
->modifier
:
1216 tiling_to_modifier(res
->bo
->tiling_mode
);
1218 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
1219 result
= iris_bo_flink(bo
, &handle
) == 0;
1223 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
: {
1224 /* Because we share the same drm file across multiple iris_screen, when
1225 * we export a GEM handle we must make sure it is valid in the DRM file
1226 * descriptor the caller is using (this is the FD given at screen
1230 if (iris_bo_export_gem_handle_for_device(bo
, screen
->winsys_fd
, &handle
))
1236 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
1237 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
1247 iris_resource_get_handle(struct pipe_screen
*pscreen
,
1248 struct pipe_context
*ctx
,
1249 struct pipe_resource
*resource
,
1250 struct winsys_handle
*whandle
,
1253 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
1254 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1256 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1258 iris_resource_disable_aux_on_first_query(resource
, usage
);
1261 if (mod_with_aux
&& whandle
->plane
> 0) {
1262 assert(res
->aux
.bo
);
1264 whandle
->stride
= res
->aux
.surf
.row_pitch_B
;
1265 whandle
->offset
= res
->aux
.offset
;
1267 /* If this is a buffer, stride should be 0 - no need to special case */
1268 whandle
->stride
= res
->surf
.row_pitch_B
;
1272 whandle
->format
= res
->external_format
;
1274 res
->mod_info
? res
->mod_info
->modifier
1275 : tiling_to_modifier(res
->bo
->tiling_mode
);
1278 enum isl_aux_usage allowed_usage
=
1279 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1281 if (res
->aux
.usage
!= allowed_usage
) {
1282 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
1283 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
1284 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
1288 switch (whandle
->type
) {
1289 case WINSYS_HANDLE_TYPE_SHARED
:
1290 return iris_bo_flink(bo
, &whandle
->handle
) == 0;
1291 case WINSYS_HANDLE_TYPE_KMS
: {
1292 /* Because we share the same drm file across multiple iris_screen, when
1293 * we export a GEM handle we must make sure it is valid in the DRM file
1294 * descriptor the caller is using (this is the FD given at screen
1298 if (iris_bo_export_gem_handle_for_device(bo
, screen
->winsys_fd
, &handle
))
1300 whandle
->handle
= handle
;
1303 case WINSYS_HANDLE_TYPE_FD
:
1304 return iris_bo_export_dmabuf(bo
, (int *) &whandle
->handle
) == 0;
1311 resource_is_busy(struct iris_context
*ice
,
1312 struct iris_resource
*res
)
1314 bool busy
= iris_bo_busy(res
->bo
);
1316 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1317 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1323 iris_invalidate_resource(struct pipe_context
*ctx
,
1324 struct pipe_resource
*resource
)
1326 struct iris_screen
*screen
= (void *) ctx
->screen
;
1327 struct iris_context
*ice
= (void *) ctx
;
1328 struct iris_resource
*res
= (void *) resource
;
1330 if (resource
->target
!= PIPE_BUFFER
)
1333 /* If it's already invalidated, don't bother doing anything. */
1334 if (res
->valid_buffer_range
.start
> res
->valid_buffer_range
.end
)
1337 if (!resource_is_busy(ice
, res
)) {
1338 /* The resource is idle, so just mark that it contains no data and
1339 * keep using the same underlying buffer object.
1341 util_range_set_empty(&res
->valid_buffer_range
);
1345 /* Otherwise, try and replace the backing storage with a new BO. */
1347 /* We can't reallocate memory we didn't allocate in the first place. */
1348 if (res
->bo
->userptr
)
1351 // XXX: We should support this.
1352 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1355 struct iris_bo
*old_bo
= res
->bo
;
1356 struct iris_bo
*new_bo
=
1357 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1358 iris_memzone_for_address(old_bo
->gtt_offset
));
1362 /* Swap out the backing storage */
1365 /* Rebind the buffer, replacing any state referring to the old BO's
1366 * address, and marking state dirty so it's reemitted.
1368 screen
->vtbl
.rebind_buffer(ice
, res
);
1370 util_range_set_empty(&res
->valid_buffer_range
);
1372 iris_bo_unreference(old_bo
);
1376 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1377 const struct pipe_box
*flush_box
)
1379 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1382 struct iris_transfer
*map
= (void *) xfer
;
1384 struct pipe_box src_box
= *flush_box
;
1386 /* Account for extra alignment padding in staging buffer */
1387 if (xfer
->resource
->target
== PIPE_BUFFER
)
1388 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1390 struct pipe_box dst_box
= (struct pipe_box
) {
1391 .x
= xfer
->box
.x
+ flush_box
->x
,
1392 .y
= xfer
->box
.y
+ flush_box
->y
,
1393 .z
= xfer
->box
.z
+ flush_box
->z
,
1394 .width
= flush_box
->width
,
1395 .height
= flush_box
->height
,
1396 .depth
= flush_box
->depth
,
1399 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1400 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1405 iris_unmap_copy_region(struct iris_transfer
*map
)
1407 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1413 iris_map_copy_region(struct iris_transfer
*map
)
1415 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1416 struct pipe_transfer
*xfer
= &map
->base
;
1417 struct pipe_box
*box
= &xfer
->box
;
1418 struct iris_resource
*res
= (void *) xfer
->resource
;
1420 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1421 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1423 struct pipe_resource templ
= (struct pipe_resource
) {
1424 .usage
= PIPE_USAGE_STAGING
,
1425 .width0
= box
->width
+ extra
,
1426 .height0
= box
->height
,
1428 .nr_samples
= xfer
->resource
->nr_samples
,
1429 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1430 .array_size
= box
->depth
,
1431 .format
= res
->internal_format
,
1434 if (xfer
->resource
->target
== PIPE_BUFFER
)
1435 templ
.target
= PIPE_BUFFER
;
1436 else if (templ
.array_size
> 1)
1437 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1439 templ
.target
= PIPE_TEXTURE_2D
;
1441 map
->staging
= iris_resource_create(pscreen
, &templ
);
1442 assert(map
->staging
);
1444 if (templ
.target
!= PIPE_BUFFER
) {
1445 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1446 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1447 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1450 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1451 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1452 xfer
->resource
, xfer
->level
, box
);
1453 /* Ensure writes to the staging BO land before we map it below. */
1454 iris_emit_pipe_control_flush(map
->batch
,
1455 "transfer read: flush before mapping",
1456 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1457 PIPE_CONTROL_CS_STALL
);
1460 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1462 if (iris_batch_references(map
->batch
, staging_bo
))
1463 iris_batch_flush(map
->batch
);
1466 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1468 map
->unmap
= iris_unmap_copy_region
;
1472 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1473 unsigned *out_x0_el
, unsigned *out_y0_el
)
1475 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1476 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1478 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1483 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1484 * different tiling patterns.
1487 iris_resource_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1488 uint32_t *tile_w
, uint32_t *tile_h
)
1499 case ISL_TILING_LINEAR
:
1504 unreachable("not reached");
1510 * This function computes masks that may be used to select the bits of the X
1511 * and Y coordinates that indicate the offset within a tile. If the BO is
1512 * untiled, the masks are set to 0.
1515 iris_resource_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1516 uint32_t *mask_x
, uint32_t *mask_y
)
1518 uint32_t tile_w_bytes
, tile_h
;
1520 iris_resource_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1522 *mask_x
= tile_w_bytes
/ cpp
- 1;
1523 *mask_y
= tile_h
- 1;
1527 * Compute the offset (in bytes) from the start of the BO to the given x
1528 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1529 * multiples of the tile size.
1532 iris_resource_get_aligned_offset(const struct iris_resource
*res
,
1533 uint32_t x
, uint32_t y
)
1535 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1536 unsigned cpp
= fmtl
->bpb
/ 8;
1537 uint32_t pitch
= res
->surf
.row_pitch_B
;
1539 switch (res
->surf
.tiling
) {
1541 unreachable("not reached");
1542 case ISL_TILING_LINEAR
:
1543 return y
* pitch
+ x
* cpp
;
1545 assert((x
% (512 / cpp
)) == 0);
1546 assert((y
% 8) == 0);
1547 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1549 assert((x
% (128 / cpp
)) == 0);
1550 assert((y
% 32) == 0);
1551 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1556 * Rendering with tiled buffers requires that the base address of the buffer
1557 * be aligned to a page boundary. For renderbuffers, and sometimes with
1558 * textures, we may want the surface to point at a texture image level that
1559 * isn't at a page boundary.
1561 * This function returns an appropriately-aligned base offset
1562 * according to the tiling restrictions, plus any required x/y offset
1566 iris_resource_get_tile_offsets(const struct iris_resource
*res
,
1567 uint32_t level
, uint32_t z
,
1568 uint32_t *tile_x
, uint32_t *tile_y
)
1571 uint32_t mask_x
, mask_y
;
1573 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1574 const unsigned cpp
= fmtl
->bpb
/ 8;
1576 iris_resource_get_tile_masks(res
->surf
.tiling
, cpp
, &mask_x
, &mask_y
);
1577 get_image_offset_el(&res
->surf
, level
, z
, &x
, &y
);
1579 *tile_x
= x
& mask_x
;
1580 *tile_y
= y
& mask_y
;
1582 return iris_resource_get_aligned_offset(res
, x
& ~mask_x
, y
& ~mask_y
);
1586 * Get pointer offset into stencil buffer.
1588 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1589 * must decode the tile's layout in software.
1592 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1594 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1596 * Even though the returned offset is always positive, the return type is
1598 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1599 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1602 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
)
1604 uint32_t tile_size
= 4096;
1605 uint32_t tile_width
= 64;
1606 uint32_t tile_height
= 64;
1607 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1609 uint32_t tile_x
= x
/ tile_width
;
1610 uint32_t tile_y
= y
/ tile_height
;
1612 /* The byte's address relative to the tile's base addres. */
1613 uint32_t byte_x
= x
% tile_width
;
1614 uint32_t byte_y
= y
% tile_height
;
1616 uintptr_t u
= tile_y
* row_size
1617 + tile_x
* tile_size
1618 + 512 * (byte_x
/ 8)
1620 + 32 * ((byte_y
/ 4) % 2)
1621 + 16 * ((byte_x
/ 4) % 2)
1622 + 8 * ((byte_y
/ 2) % 2)
1623 + 4 * ((byte_x
/ 2) % 2)
1631 iris_unmap_s8(struct iris_transfer
*map
)
1633 struct pipe_transfer
*xfer
= &map
->base
;
1634 const struct pipe_box
*box
= &xfer
->box
;
1635 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1636 struct isl_surf
*surf
= &res
->surf
;
1638 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1639 uint8_t *untiled_s8_map
= map
->ptr
;
1640 uint8_t *tiled_s8_map
=
1641 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1643 for (int s
= 0; s
< box
->depth
; s
++) {
1644 unsigned x0_el
, y0_el
;
1645 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1647 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1648 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1649 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1651 y0_el
+ box
->y
+ y
);
1652 tiled_s8_map
[offset
] =
1653 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1663 iris_map_s8(struct iris_transfer
*map
)
1665 struct pipe_transfer
*xfer
= &map
->base
;
1666 const struct pipe_box
*box
= &xfer
->box
;
1667 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1668 struct isl_surf
*surf
= &res
->surf
;
1670 xfer
->stride
= surf
->row_pitch_B
;
1671 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1673 /* The tiling and detiling functions require that the linear buffer has
1674 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1675 * over-allocate the linear buffer to get the proper alignment.
1677 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1678 assert(map
->buffer
);
1680 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1681 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1682 * invalidate is set, since we'll be writing the whole rectangle from our
1683 * temporary buffer back out.
1685 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1686 uint8_t *untiled_s8_map
= map
->ptr
;
1687 uint8_t *tiled_s8_map
=
1688 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1690 for (int s
= 0; s
< box
->depth
; s
++) {
1691 unsigned x0_el
, y0_el
;
1692 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1694 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1695 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1696 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1698 y0_el
+ box
->y
+ y
);
1699 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1700 tiled_s8_map
[offset
];
1706 map
->unmap
= iris_unmap_s8
;
1709 /* Compute extent parameters for use with tiled_memcpy functions.
1710 * xs are in units of bytes and ys are in units of strides.
1713 tile_extents(const struct isl_surf
*surf
,
1714 const struct pipe_box
*box
,
1715 unsigned level
, int z
,
1716 unsigned *x1_B
, unsigned *x2_B
,
1717 unsigned *y1_el
, unsigned *y2_el
)
1719 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1720 const unsigned cpp
= fmtl
->bpb
/ 8;
1722 assert(box
->x
% fmtl
->bw
== 0);
1723 assert(box
->y
% fmtl
->bh
== 0);
1725 unsigned x0_el
, y0_el
;
1726 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1728 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1729 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1730 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1731 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1735 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1737 struct pipe_transfer
*xfer
= &map
->base
;
1738 const struct pipe_box
*box
= &xfer
->box
;
1739 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1740 struct isl_surf
*surf
= &res
->surf
;
1742 const bool has_swizzling
= false;
1744 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1746 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1748 for (int s
= 0; s
< box
->depth
; s
++) {
1749 unsigned x1
, x2
, y1
, y2
;
1750 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1752 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1754 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1755 surf
->row_pitch_B
, xfer
->stride
,
1756 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1759 os_free_aligned(map
->buffer
);
1760 map
->buffer
= map
->ptr
= NULL
;
1764 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1766 struct pipe_transfer
*xfer
= &map
->base
;
1767 const struct pipe_box
*box
= &xfer
->box
;
1768 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1769 struct isl_surf
*surf
= &res
->surf
;
1771 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1772 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1774 unsigned x1
, x2
, y1
, y2
;
1775 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1777 /* The tiling and detiling functions require that the linear buffer has
1778 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1779 * over-allocate the linear buffer to get the proper alignment.
1782 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1783 assert(map
->buffer
);
1784 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1786 const bool has_swizzling
= false;
1788 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1790 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1792 for (int s
= 0; s
< box
->depth
; s
++) {
1793 unsigned x1
, x2
, y1
, y2
;
1794 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1796 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1797 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1799 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1800 surf
->row_pitch_B
, has_swizzling
,
1801 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1805 map
->unmap
= iris_unmap_tiled_memcpy
;
1809 iris_map_direct(struct iris_transfer
*map
)
1811 struct pipe_transfer
*xfer
= &map
->base
;
1812 struct pipe_box
*box
= &xfer
->box
;
1813 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1815 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1817 if (res
->base
.target
== PIPE_BUFFER
) {
1819 xfer
->layer_stride
= 0;
1821 map
->ptr
= ptr
+ box
->x
;
1823 struct isl_surf
*surf
= &res
->surf
;
1824 const struct isl_format_layout
*fmtl
=
1825 isl_format_get_layout(surf
->format
);
1826 const unsigned cpp
= fmtl
->bpb
/ 8;
1827 unsigned x0_el
, y0_el
;
1829 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1831 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1832 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1834 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1839 can_promote_to_async(const struct iris_resource
*res
,
1840 const struct pipe_box
*box
,
1841 enum pipe_transfer_usage usage
)
1843 /* If we're writing to a section of the buffer that hasn't even been
1844 * initialized with useful data, then we can safely promote this write
1845 * to be unsynchronized. This helps the common pattern of appending data.
1847 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1848 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1849 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1850 box
->x
+ box
->width
);
1854 iris_transfer_map(struct pipe_context
*ctx
,
1855 struct pipe_resource
*resource
,
1857 enum pipe_transfer_usage usage
,
1858 const struct pipe_box
*box
,
1859 struct pipe_transfer
**ptransfer
)
1861 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1862 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1863 struct isl_surf
*surf
= &res
->surf
;
1865 if (iris_resource_unfinished_aux_import(res
))
1866 iris_resource_finish_aux_import(ctx
->screen
, res
);
1868 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1869 /* Replace the backing storage with a fresh buffer for non-async maps */
1870 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1871 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1872 iris_invalidate_resource(ctx
, resource
);
1874 /* If we can discard the whole resource, we can discard the range. */
1875 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1878 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1879 can_promote_to_async(res
, box
, usage
)) {
1880 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1883 bool need_resolve
= false;
1884 bool need_color_resolve
= false;
1886 if (resource
->target
!= PIPE_BUFFER
) {
1887 bool need_hiz_resolve
= iris_resource_level_has_hiz(res
, level
);
1888 bool need_stencil_resolve
= res
->aux
.usage
== ISL_AUX_USAGE_STC_CCS
;
1890 need_color_resolve
=
1891 (res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
||
1892 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
||
1893 res
->aux
.usage
== ISL_AUX_USAGE_GEN12_CCS_E
) &&
1894 iris_has_color_unresolved(res
, level
, 1, box
->z
, box
->depth
);
1896 need_resolve
= need_color_resolve
||
1898 need_stencil_resolve
;
1901 bool map_would_stall
= false;
1903 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1904 map_would_stall
= need_resolve
|| resource_is_busy(ice
, res
);
1906 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1907 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1911 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1912 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1915 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1916 struct pipe_transfer
*xfer
= &map
->base
;
1921 memset(map
, 0, sizeof(*map
));
1922 map
->dbg
= &ice
->dbg
;
1924 pipe_resource_reference(&xfer
->resource
, resource
);
1925 xfer
->level
= level
;
1926 xfer
->usage
= usage
;
1930 map
->dest_had_defined_contents
=
1931 util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1932 box
->x
+ box
->width
);
1934 if (usage
& PIPE_TRANSFER_WRITE
)
1935 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1937 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1938 * there is to access them simultaneously on the CPU & GPU. This also
1939 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1940 * contain state we're constructing for a GPU draw call, which would
1941 * kill us with infinite stack recursion.
1943 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1944 PIPE_TRANSFER_COHERENT
|
1945 PIPE_TRANSFER_MAP_DIRECTLY
);
1947 /* GPU copies are not useful for buffer reads. Instead of stalling to
1948 * read from the original buffer, we'd simply copy it to a temporary...
1949 * then stall (a bit longer) to read from that buffer.
1951 * Images are less clear-cut. Color resolves are destructive, removing
1952 * the underlying compression, so we'd rather blit the data to a linear
1953 * temporary and map that, to avoid the resolve. (It might be better to
1954 * a tiled temporary and use the tiled_memcpy paths...)
1956 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) && !need_color_resolve
)
1959 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1960 if (fmtl
->txc
== ISL_TXC_ASTC
)
1963 if ((map_would_stall
||
1964 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
||
1965 res
->aux
.usage
== ISL_AUX_USAGE_GEN12_CCS_E
) && !no_gpu
) {
1966 /* If we need a synchronous mapping and the resource is busy, or needs
1967 * resolving, we copy to/from a linear temporary buffer using the GPU.
1969 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1970 map
->blorp
= &ice
->blorp
;
1971 iris_map_copy_region(map
);
1973 /* Otherwise we're free to map on the CPU. */
1976 iris_resource_access_raw(ice
, res
, level
, box
->z
, box
->depth
,
1977 usage
& PIPE_TRANSFER_WRITE
);
1980 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1981 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1982 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1983 iris_batch_flush(&ice
->batches
[i
]);
1987 if (surf
->tiling
== ISL_TILING_W
) {
1988 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1990 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1991 iris_map_tiled_memcpy(map
);
1993 iris_map_direct(map
);
2001 iris_transfer_flush_region(struct pipe_context
*ctx
,
2002 struct pipe_transfer
*xfer
,
2003 const struct pipe_box
*box
)
2005 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2006 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
2007 struct iris_transfer
*map
= (void *) xfer
;
2010 iris_flush_staging_region(xfer
, box
);
2012 uint32_t history_flush
= 0;
2014 if (res
->base
.target
== PIPE_BUFFER
) {
2016 history_flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
2018 if (map
->dest_had_defined_contents
)
2019 history_flush
|= iris_flush_bits_for_history(res
);
2021 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
2024 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
2025 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
2026 struct iris_batch
*batch
= &ice
->batches
[i
];
2027 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
2028 iris_batch_maybe_flush(batch
, 24);
2029 iris_emit_pipe_control_flush(batch
,
2030 "cache history: transfer flush",
2036 /* Make sure we flag constants dirty even if there's no need to emit
2037 * any PIPE_CONTROLs to a batch.
2039 iris_dirty_for_history(ice
, res
);
2043 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
2045 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2046 struct iris_transfer
*map
= (void *) xfer
;
2048 if (!(xfer
->usage
& (PIPE_TRANSFER_FLUSH_EXPLICIT
|
2049 PIPE_TRANSFER_COHERENT
))) {
2050 struct pipe_box flush_box
= {
2051 .x
= 0, .y
= 0, .z
= 0,
2052 .width
= xfer
->box
.width
,
2053 .height
= xfer
->box
.height
,
2054 .depth
= xfer
->box
.depth
,
2056 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
2062 pipe_resource_reference(&xfer
->resource
, NULL
);
2063 slab_free(&ice
->transfer_pool
, map
);
2067 * The pipe->texture_subdata() driver hook.
2069 * Mesa's state tracker takes this path whenever possible, even with
2070 * PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER set.
2073 iris_texture_subdata(struct pipe_context
*ctx
,
2074 struct pipe_resource
*resource
,
2077 const struct pipe_box
*box
,
2080 unsigned layer_stride
)
2082 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2083 struct iris_resource
*res
= (struct iris_resource
*)resource
;
2084 const struct isl_surf
*surf
= &res
->surf
;
2086 assert(resource
->target
!= PIPE_BUFFER
);
2088 if (iris_resource_unfinished_aux_import(res
))
2089 iris_resource_finish_aux_import(ctx
->screen
, res
);
2091 /* Just use the transfer-based path for linear buffers - it will already
2092 * do a direct mapping, or a simple linear staging buffer.
2094 * Linear staging buffers appear to be better than tiled ones, too, so
2095 * take that path if we need the GPU to perform color compression, or
2096 * stall-avoidance blits.
2098 if (surf
->tiling
== ISL_TILING_LINEAR
||
2099 (isl_aux_usage_has_ccs(res
->aux
.usage
) &&
2100 res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
) ||
2101 resource_is_busy(ice
, res
)) {
2102 return u_default_texture_subdata(ctx
, resource
, level
, usage
, box
,
2103 data
, stride
, layer_stride
);
2106 /* No state trackers pass any flags other than PIPE_TRANSFER_WRITE */
2108 iris_resource_access_raw(ice
, res
, level
, box
->z
, box
->depth
, true);
2110 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
2111 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
2112 iris_batch_flush(&ice
->batches
[i
]);
2115 uint8_t *dst
= iris_bo_map(&ice
->dbg
, res
->bo
, MAP_WRITE
| MAP_RAW
);
2117 for (int s
= 0; s
< box
->depth
; s
++) {
2118 const uint8_t *src
= data
+ s
* layer_stride
;
2120 if (surf
->tiling
== ISL_TILING_W
) {
2121 unsigned x0_el
, y0_el
;
2122 get_image_offset_el(surf
, level
, box
->z
+ s
, &x0_el
, &y0_el
);
2124 for (unsigned y
= 0; y
< box
->height
; y
++) {
2125 for (unsigned x
= 0; x
< box
->width
; x
++) {
2126 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
2128 y0_el
+ box
->y
+ y
);
2129 dst
[offset
] = src
[y
* stride
+ x
];
2133 unsigned x1
, x2
, y1
, y2
;
2135 tile_extents(surf
, box
, level
, s
, &x1
, &x2
, &y1
, &y2
);
2137 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
,
2138 (void *)dst
, (void *)src
,
2139 surf
->row_pitch_B
, stride
,
2140 false, surf
->tiling
, ISL_MEMCPY
);
2146 * Mark state dirty that needs to be re-emitted when a resource is written.
2149 iris_dirty_for_history(struct iris_context
*ice
,
2150 struct iris_resource
*res
)
2152 uint64_t stage_dirty
= 0ull;
2154 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2155 stage_dirty
|= ((uint64_t)res
->bind_stages
)
2156 << IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS
;
2159 ice
->state
.stage_dirty
|= stage_dirty
;
2163 * Produce a set of PIPE_CONTROL bits which ensure data written to a
2164 * resource becomes visible, and any stale read cache data is invalidated.
2167 iris_flush_bits_for_history(struct iris_resource
*res
)
2169 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
2171 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2172 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
2173 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2176 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
2177 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2179 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
2180 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
2182 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
2183 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
2189 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
2190 struct iris_batch
*batch
,
2191 struct iris_resource
*res
,
2192 uint32_t extra_flags
,
2195 if (res
->base
.target
!= PIPE_BUFFER
)
2198 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
2200 iris_emit_pipe_control_flush(batch
, reason
, flush
);
2202 iris_dirty_for_history(ice
, res
);
2206 iris_resource_set_clear_color(struct iris_context
*ice
,
2207 struct iris_resource
*res
,
2208 union isl_color_value color
)
2210 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
2211 res
->aux
.clear_color
= color
;
2218 union isl_color_value
2219 iris_resource_get_clear_color(const struct iris_resource
*res
,
2220 struct iris_bo
**clear_color_bo
,
2221 uint64_t *clear_color_offset
)
2223 assert(res
->aux
.bo
);
2226 *clear_color_bo
= res
->aux
.clear_color_bo
;
2227 if (clear_color_offset
)
2228 *clear_color_offset
= res
->aux
.clear_color_offset
;
2229 return res
->aux
.clear_color
;
2232 static enum pipe_format
2233 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
2235 struct iris_resource
*res
= (void *) p_res
;
2236 return res
->internal_format
;
2239 static const struct u_transfer_vtbl transfer_vtbl
= {
2240 .resource_create
= iris_resource_create
,
2241 .resource_destroy
= iris_resource_destroy
,
2242 .transfer_map
= iris_transfer_map
,
2243 .transfer_unmap
= iris_transfer_unmap
,
2244 .transfer_flush_region
= iris_transfer_flush_region
,
2245 .get_internal_format
= iris_resource_get_internal_format
,
2246 .set_stencil
= iris_resource_set_separate_stencil
,
2247 .get_stencil
= iris_resource_get_separate_stencil
,
2251 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
2253 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
2254 pscreen
->resource_create_with_modifiers
=
2255 iris_resource_create_with_modifiers
;
2256 pscreen
->resource_create
= u_transfer_helper_resource_create
;
2257 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
2258 pscreen
->resource_from_handle
= iris_resource_from_handle
;
2259 pscreen
->resource_get_handle
= iris_resource_get_handle
;
2260 pscreen
->resource_get_param
= iris_resource_get_param
;
2261 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
2262 pscreen
->transfer_helper
=
2263 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
2267 iris_init_resource_functions(struct pipe_context
*ctx
)
2269 ctx
->flush_resource
= iris_flush_resource
;
2270 ctx
->invalidate_resource
= iris_invalidate_resource
;
2271 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
2272 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
2273 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
2274 ctx
->buffer_subdata
= u_default_buffer_subdata
;
2275 ctx
->texture_subdata
= iris_texture_subdata
;