2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_transfer.h"
42 #include "util/u_transfer_helper.h"
43 #include "util/u_upload_mgr.h"
44 #include "util/ralloc.h"
45 #include "iris_batch.h"
46 #include "iris_context.h"
47 #include "iris_resource.h"
48 #include "iris_screen.h"
49 #include "intel/common/gen_debug.h"
51 #include "drm-uapi/drm_fourcc.h"
52 #include "drm-uapi/i915_drm.h"
54 enum modifier_priority
{
55 MODIFIER_PRIORITY_INVALID
= 0,
56 MODIFIER_PRIORITY_LINEAR
,
59 MODIFIER_PRIORITY_Y_CCS
,
62 static const uint64_t priority_to_modifier
[] = {
63 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
64 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
65 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
66 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
67 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
71 modifier_is_supported(const struct gen_device_info
*devinfo
,
74 /* XXX: do something real */
76 case I915_FORMAT_MOD_Y_TILED
:
77 case I915_FORMAT_MOD_X_TILED
:
78 case DRM_FORMAT_MOD_LINEAR
:
80 case I915_FORMAT_MOD_Y_TILED_CCS
:
81 case DRM_FORMAT_MOD_INVALID
:
88 select_best_modifier(struct gen_device_info
*devinfo
,
89 const uint64_t *modifiers
,
92 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
94 for (int i
= 0; i
< count
; i
++) {
95 if (!modifier_is_supported(devinfo
, modifiers
[i
]))
98 switch (modifiers
[i
]) {
99 case I915_FORMAT_MOD_Y_TILED_CCS
:
100 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
102 case I915_FORMAT_MOD_Y_TILED
:
103 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
105 case I915_FORMAT_MOD_X_TILED
:
106 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
108 case DRM_FORMAT_MOD_LINEAR
:
109 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
111 case DRM_FORMAT_MOD_INVALID
:
117 return priority_to_modifier
[prio
];
120 static enum isl_surf_dim
121 target_to_isl_surf_dim(enum pipe_texture_target target
)
125 case PIPE_TEXTURE_1D
:
126 case PIPE_TEXTURE_1D_ARRAY
:
127 return ISL_SURF_DIM_1D
;
128 case PIPE_TEXTURE_2D
:
129 case PIPE_TEXTURE_CUBE
:
130 case PIPE_TEXTURE_RECT
:
131 case PIPE_TEXTURE_2D_ARRAY
:
132 case PIPE_TEXTURE_CUBE_ARRAY
:
133 return ISL_SURF_DIM_2D
;
134 case PIPE_TEXTURE_3D
:
135 return ISL_SURF_DIM_3D
;
136 case PIPE_MAX_TEXTURE_TYPES
:
139 unreachable("invalid texture type");
142 static isl_surf_usage_flags_t
143 pipe_bind_to_isl_usage(unsigned bindings
)
145 isl_surf_usage_flags_t usage
= 0;
147 if (bindings
& PIPE_BIND_RENDER_TARGET
)
148 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
150 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
151 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
153 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
154 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
156 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
157 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
162 struct pipe_resource
*
163 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
165 /* For packed depth-stencil, we treat depth as the primary resource
166 * and store S8 as the "second plane" resource.
172 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
173 struct pipe_resource
*stencil
)
175 assert(util_format_has_depth(util_format_description(p_res
->format
)));
176 pipe_resource_reference(&p_res
->next
, stencil
);
180 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
181 struct iris_resource
**out_z
,
182 struct iris_resource
**out_s
)
190 const struct util_format_description
*desc
=
191 util_format_description(res
->format
);
193 if (util_format_has_depth(desc
)) {
194 *out_z
= (void *) res
;
195 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
197 assert(util_format_has_stencil(desc
));
199 *out_s
= (void *) res
;
204 iris_resource_destroy(struct pipe_screen
*screen
,
205 struct pipe_resource
*resource
)
207 struct iris_resource
*res
= (struct iris_resource
*)resource
;
209 iris_bo_unreference(res
->bo
);
213 static struct iris_resource
*
214 iris_alloc_resource(struct pipe_screen
*pscreen
,
215 const struct pipe_resource
*templ
)
217 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
222 res
->base
.screen
= pscreen
;
223 pipe_reference_init(&res
->base
.reference
, 1);
228 static struct pipe_resource
*
229 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
230 const struct pipe_resource
*templ
,
231 const uint64_t *modifiers
,
234 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
235 struct gen_device_info
*devinfo
= &screen
->devinfo
;
236 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
237 const struct util_format_description
*format_desc
=
238 util_format_description(templ
->format
);
243 const bool has_depth
= util_format_has_depth(format_desc
);
244 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
246 if (modifiers_count
== 0 || !modifiers
) {
248 modifier
= I915_FORMAT_MOD_Y_TILED
;
249 } else if (templ
->target
== PIPE_TEXTURE_1D
||
250 templ
->target
== PIPE_TEXTURE_1D_ARRAY
) {
251 modifier
= DRM_FORMAT_MOD_LINEAR
;
252 } else if (templ
->bind
& PIPE_BIND_DISPLAY_TARGET
) {
253 /* Display is X-tiled for historical reasons. */
254 modifier
= I915_FORMAT_MOD_X_TILED
;
256 modifier
= I915_FORMAT_MOD_Y_TILED
;
258 /* XXX: make sure this doesn't do stupid things for internal textures */
261 if (templ
->target
== PIPE_BUFFER
|| templ
->usage
== PIPE_USAGE_STAGING
)
262 modifier
= DRM_FORMAT_MOD_LINEAR
;
264 if (templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
))
265 modifier
= DRM_FORMAT_MOD_LINEAR
;
267 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
268 /* User requested specific modifiers */
269 modifier
= select_best_modifier(devinfo
, modifiers
, modifiers_count
);
270 if (modifier
== DRM_FORMAT_MOD_INVALID
)
274 const struct isl_drm_modifier_info
*mod_info
=
275 isl_drm_modifier_get_info(modifier
);
277 enum isl_tiling tiling
= templ
->format
== PIPE_FORMAT_S8_UINT
?
278 ISL_TILING_W
: mod_info
->tiling
;
280 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
282 if (templ
->target
== PIPE_TEXTURE_CUBE
||
283 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
284 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
286 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
287 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
288 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
290 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
293 enum pipe_format pfmt
= templ
->format
;
294 res
->internal_format
= pfmt
;
296 /* Should be handled by u_transfer_helper */
297 assert(!util_format_is_depth_and_stencil(pfmt
));
299 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
300 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
302 UNUSED
const bool isl_surf_created_successfully
=
303 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
304 .dim
= target_to_isl_surf_dim(templ
->target
),
306 .width
= templ
->width0
,
307 .height
= templ
->height0
,
308 .depth
= templ
->depth0
,
309 .levels
= templ
->last_level
+ 1,
310 .array_len
= templ
->array_size
,
311 .samples
= MAX2(templ
->nr_samples
, 1),
312 .min_alignment_B
= 0,
315 .tiling_flags
= 1 << tiling
);
316 assert(isl_surf_created_successfully
);
318 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
319 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
320 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
321 memzone
= IRIS_MEMZONE_SHADER
;
322 name
= "shader kernels";
323 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
324 memzone
= IRIS_MEMZONE_SURFACE
;
325 name
= "surface state";
326 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
327 memzone
= IRIS_MEMZONE_DYNAMIC
;
328 name
= "dynamic state";
331 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, res
->surf
.size_B
,
333 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
334 res
->surf
.row_pitch_B
, 0);
341 iris_resource_destroy(pscreen
, &res
->base
);
345 static struct pipe_resource
*
346 iris_resource_create(struct pipe_screen
*pscreen
,
347 const struct pipe_resource
*templ
)
349 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
353 tiling_to_modifier(uint32_t tiling
)
355 static const uint64_t map
[] = {
356 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
357 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
358 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
361 assert(tiling
< ARRAY_SIZE(map
));
366 static struct pipe_resource
*
367 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
368 const struct pipe_resource
*templ
,
371 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
372 struct gen_device_info
*devinfo
= &screen
->devinfo
;
373 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
374 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
378 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
379 user_memory
, templ
->width0
,
386 res
->internal_format
= templ
->format
;
389 isl_surf_usage_flags_t isl_usage
= 0;
391 const struct iris_format_info fmt
=
392 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
394 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
395 .dim
= target_to_isl_surf_dim(templ
->target
),
397 .width
= templ
->width0
,
398 .height
= templ
->height0
,
399 .depth
= templ
->depth0
,
400 .levels
= templ
->last_level
+ 1,
401 .array_len
= templ
->array_size
,
402 .samples
= MAX2(templ
->nr_samples
, 1),
403 .min_alignment_B
= 0,
406 .tiling_flags
= 1 << ISL_TILING_LINEAR
);
408 assert(res
->bo
->tiling_mode
== isl_tiling_to_i915_tiling(res
->surf
.tiling
));
413 static struct pipe_resource
*
414 iris_resource_from_handle(struct pipe_screen
*pscreen
,
415 const struct pipe_resource
*templ
,
416 struct winsys_handle
*whandle
,
419 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
420 struct gen_device_info
*devinfo
= &screen
->devinfo
;
421 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
422 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
426 if (whandle
->offset
!= 0) {
427 dbg_printf("Attempt to import unsupported winsys offset %u\n",
432 switch (whandle
->type
) {
433 case WINSYS_HANDLE_TYPE_FD
:
434 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
);
436 case WINSYS_HANDLE_TYPE_SHARED
:
437 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
441 unreachable("invalid winsys handle type");
446 uint64_t modifier
= whandle
->modifier
;
447 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
448 modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
450 const struct isl_drm_modifier_info
*mod_info
=
451 isl_drm_modifier_get_info(modifier
);
455 isl_surf_usage_flags_t isl_usage
= ISL_SURF_USAGE_DISPLAY_BIT
;
457 const struct iris_format_info fmt
=
458 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
460 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
461 .dim
= target_to_isl_surf_dim(templ
->target
),
463 .width
= templ
->width0
,
464 .height
= templ
->height0
,
465 .depth
= templ
->depth0
,
466 .levels
= templ
->last_level
+ 1,
467 .array_len
= templ
->array_size
,
468 .samples
= MAX2(templ
->nr_samples
, 1),
469 .min_alignment_B
= 0,
472 .tiling_flags
= 1 << mod_info
->tiling
);
474 assert(res
->bo
->tiling_mode
== isl_tiling_to_i915_tiling(res
->surf
.tiling
));
479 iris_resource_destroy(pscreen
, &res
->base
);
484 iris_resource_get_handle(struct pipe_screen
*pscreen
,
485 struct pipe_context
*ctx
,
486 struct pipe_resource
*resource
,
487 struct winsys_handle
*whandle
,
490 struct iris_resource
*res
= (struct iris_resource
*)resource
;
492 whandle
->stride
= res
->surf
.row_pitch_B
;
493 whandle
->modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
495 switch (whandle
->type
) {
496 case WINSYS_HANDLE_TYPE_SHARED
:
497 return iris_bo_flink(res
->bo
, &whandle
->handle
) == 0;
498 case WINSYS_HANDLE_TYPE_KMS
:
499 whandle
->handle
= iris_bo_export_gem_handle(res
->bo
);
501 case WINSYS_HANDLE_TYPE_FD
:
502 return iris_bo_export_dmabuf(res
->bo
, (int *) &whandle
->handle
) == 0;
509 get_image_offset_el(struct isl_surf
*surf
, unsigned level
, unsigned z
,
510 unsigned *out_x0_el
, unsigned *out_y0_el
)
512 if (surf
->dim
== ISL_SURF_DIM_3D
) {
513 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
515 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
520 * Get pointer offset into stencil buffer.
522 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
523 * must decode the tile's layout in software.
526 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
528 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
530 * Even though the returned offset is always positive, the return type is
532 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
533 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
536 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
538 uint32_t tile_size
= 4096;
539 uint32_t tile_width
= 64;
540 uint32_t tile_height
= 64;
541 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
543 uint32_t tile_x
= x
/ tile_width
;
544 uint32_t tile_y
= y
/ tile_height
;
546 /* The byte's address relative to the tile's base addres. */
547 uint32_t byte_x
= x
% tile_width
;
548 uint32_t byte_y
= y
% tile_height
;
550 uintptr_t u
= tile_y
* row_size
554 + 32 * ((byte_y
/ 4) % 2)
555 + 16 * ((byte_x
/ 4) % 2)
556 + 8 * ((byte_y
/ 2) % 2)
557 + 4 * ((byte_x
/ 2) % 2)
562 /* adjust for bit6 swizzling */
563 if (((byte_x
/ 8) % 2) == 1) {
564 if (((byte_y
/ 8) % 2) == 0) {
576 iris_unmap_s8(struct iris_transfer
*map
)
578 struct pipe_transfer
*xfer
= &map
->base
;
579 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
580 struct isl_surf
*surf
= &res
->surf
;
581 const bool has_swizzling
= false;
583 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
584 uint8_t *untiled_s8_map
= map
->ptr
;
585 uint8_t *tiled_s8_map
=
586 iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
588 struct pipe_box box
= xfer
->box
;
590 for (int s
= 0; s
< box
.depth
; s
++) {
591 unsigned x0_el
, y0_el
;
592 get_image_offset_el(surf
, xfer
->level
, box
.z
, &x0_el
, &y0_el
);
594 for (uint32_t y
= 0; y
< box
.height
; y
++) {
595 for (uint32_t x
= 0; x
< box
.width
; x
++) {
596 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
600 tiled_s8_map
[offset
] =
601 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
613 iris_map_s8(struct iris_transfer
*map
)
615 struct pipe_transfer
*xfer
= &map
->base
;
616 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
617 struct isl_surf
*surf
= &res
->surf
;
619 xfer
->stride
= surf
->row_pitch_B
;
620 xfer
->layer_stride
= xfer
->stride
* xfer
->box
.height
;
622 /* The tiling and detiling functions require that the linear buffer has
623 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
624 * over-allocate the linear buffer to get the proper alignment.
626 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* xfer
->box
.depth
);
629 const bool has_swizzling
= false;
631 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
632 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
633 * invalidate is set, since we'll be writing the whole rectangle from our
634 * temporary buffer back out.
636 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
637 uint8_t *untiled_s8_map
= map
->ptr
;
638 uint8_t *tiled_s8_map
=
639 iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
641 struct pipe_box box
= xfer
->box
;
643 for (int s
= 0; s
< box
.depth
; s
++) {
644 unsigned x0_el
, y0_el
;
645 get_image_offset_el(surf
, xfer
->level
, box
.z
, &x0_el
, &y0_el
);
647 for (uint32_t y
= 0; y
< box
.height
; y
++) {
648 for (uint32_t x
= 0; x
< box
.width
; x
++) {
649 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
653 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
654 tiled_s8_map
[offset
];
662 map
->unmap
= iris_unmap_s8
;
665 /* Compute extent parameters for use with tiled_memcpy functions.
666 * xs are in units of bytes and ys are in units of strides.
669 tile_extents(struct isl_surf
*surf
,
670 const struct pipe_box
*box
,
672 unsigned *x1_B
, unsigned *x2_B
,
673 unsigned *y1_el
, unsigned *y2_el
)
675 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
676 const unsigned cpp
= fmtl
->bpb
/ 8;
678 assert(box
->x
% fmtl
->bw
== 0);
679 assert(box
->y
% fmtl
->bh
== 0);
681 unsigned x0_el
, y0_el
;
682 get_image_offset_el(surf
, level
, box
->z
, &x0_el
, &y0_el
);
684 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
685 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
686 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
687 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
691 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
693 struct pipe_transfer
*xfer
= &map
->base
;
694 struct pipe_box box
= xfer
->box
;
695 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
696 struct isl_surf
*surf
= &res
->surf
;
698 const bool has_swizzling
= false;
700 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
701 char *dst
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
703 for (int s
= 0; s
< box
.depth
; s
++) {
704 unsigned x1
, x2
, y1
, y2
;
705 tile_extents(surf
, &box
, xfer
->level
, &x1
, &x2
, &y1
, &y2
);
707 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
709 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
710 surf
->row_pitch_B
, xfer
->stride
,
711 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
715 os_free_aligned(map
->buffer
);
716 map
->buffer
= map
->ptr
= NULL
;
720 iris_map_tiled_memcpy(struct iris_transfer
*map
)
722 struct pipe_transfer
*xfer
= &map
->base
;
723 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
724 struct isl_surf
*surf
= &res
->surf
;
726 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
727 xfer
->layer_stride
= xfer
->stride
* xfer
->box
.height
;
729 unsigned x1
, x2
, y1
, y2
;
730 tile_extents(surf
, &xfer
->box
, xfer
->level
, &x1
, &x2
, &y1
, &y2
);
732 /* The tiling and detiling functions require that the linear buffer has
733 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
734 * over-allocate the linear buffer to get the proper alignment.
737 os_malloc_aligned(xfer
->layer_stride
* xfer
->box
.depth
, 16);
739 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
741 const bool has_swizzling
= false;
743 // XXX: PIPE_TRANSFER_READ?
744 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
745 char *src
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
747 struct pipe_box box
= xfer
->box
;
749 for (int s
= 0; s
< box
.depth
; s
++) {
750 unsigned x1
, x2
, y1
, y2
;
751 tile_extents(surf
, &box
, xfer
->level
, &x1
, &x2
, &y1
, &y2
);
753 /* When transferring cubes, box.depth is counted in cubes, but
754 * box.z is counted in faces. We want to transfer only the
755 * specified face, but for all array elements. So, use 's'
756 * (the zero-based slice count) rather than box.z.
758 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
760 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
761 surf
->row_pitch_B
, has_swizzling
,
762 surf
->tiling
, ISL_MEMCPY
);
767 map
->unmap
= iris_unmap_tiled_memcpy
;
771 iris_map_direct(struct iris_transfer
*map
)
773 struct pipe_transfer
*xfer
= &map
->base
;
774 struct pipe_box
*box
= &xfer
->box
;
775 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
776 struct isl_surf
*surf
= &res
->surf
;
777 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
778 const unsigned cpp
= fmtl
->bpb
/ 8;
779 unsigned x0_el
, y0_el
;
781 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
);
783 if (res
->base
.target
== PIPE_BUFFER
) {
785 xfer
->layer_stride
= 0;
787 map
->ptr
= ptr
+ box
->x
;
789 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
791 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
792 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
794 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
799 iris_transfer_map(struct pipe_context
*ctx
,
800 struct pipe_resource
*resource
,
802 enum pipe_transfer_usage usage
,
803 const struct pipe_box
*box
,
804 struct pipe_transfer
**ptransfer
)
806 struct iris_context
*ice
= (struct iris_context
*)ctx
;
807 struct iris_resource
*res
= (struct iris_resource
*)resource
;
808 struct isl_surf
*surf
= &res
->surf
;
810 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
811 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
814 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
815 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
816 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
817 iris_batch_flush(&ice
->batches
[i
]);
821 if ((usage
& PIPE_TRANSFER_DONTBLOCK
) && iris_bo_busy(res
->bo
))
824 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
825 struct pipe_transfer
*xfer
= &map
->base
;
827 // PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
828 // PIPE_TRANSFER_DISCARD_RANGE
833 memset(map
, 0, sizeof(*map
));
834 map
->dbg
= &ice
->dbg
;
836 pipe_resource_reference(&xfer
->resource
, resource
);
842 xfer
->usage
&= (PIPE_TRANSFER_READ
|
843 PIPE_TRANSFER_WRITE
|
844 PIPE_TRANSFER_UNSYNCHRONIZED
|
845 PIPE_TRANSFER_PERSISTENT
|
846 PIPE_TRANSFER_COHERENT
|
847 PIPE_TRANSFER_DISCARD_RANGE
);
849 if (surf
->tiling
== ISL_TILING_W
) {
850 // XXX: just teach iris_map_tiled_memcpy about W tiling...
852 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
853 iris_map_tiled_memcpy(map
);
855 iris_map_direct(map
);
862 iris_transfer_flush_region(struct pipe_context
*ctx
,
863 struct pipe_transfer
*xfer
,
864 const struct pipe_box
*box
)
866 struct iris_context
*ice
= (struct iris_context
*)ctx
;
867 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
870 // XXX: don't emit flushes in both engines...? we may also need to flush
871 // even if there isn't a draw yet - may still be stale data in caches...
872 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
873 if (ice
->batches
[i
].contains_draw
) {
874 iris_batch_maybe_flush(&ice
->batches
[i
], 24);
875 iris_flush_and_dirty_for_history(ice
, &ice
->batches
[i
], res
);
881 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
883 struct iris_context
*ice
= (struct iris_context
*)ctx
;
884 struct iris_transfer
*map
= (void *) xfer
;
885 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
890 // XXX: don't emit flushes in both engines...?
891 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
892 if (ice
->batches
[i
].contains_draw
) {
893 iris_batch_maybe_flush(&ice
->batches
[i
], 24);
894 iris_flush_and_dirty_for_history(ice
, &ice
->batches
[i
], res
);
898 pipe_resource_reference(&xfer
->resource
, NULL
);
899 slab_free(&ice
->transfer_pool
, map
);
903 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
908 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
909 struct iris_batch
*batch
,
910 struct iris_resource
*res
)
912 if (res
->base
.target
!= PIPE_BUFFER
)
915 unsigned flush
= PIPE_CONTROL_CS_STALL
;
916 uint64_t dirty
= 0ull;
918 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
919 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
920 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
921 dirty
|= IRIS_DIRTY_CONSTANTS_VS
|
922 IRIS_DIRTY_CONSTANTS_TCS
|
923 IRIS_DIRTY_CONSTANTS_TES
|
924 IRIS_DIRTY_CONSTANTS_GS
|
925 IRIS_DIRTY_CONSTANTS_FS
|
926 IRIS_DIRTY_CONSTANTS_CS
|
927 IRIS_ALL_DIRTY_BINDINGS
;
930 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
931 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
933 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
934 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
936 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
937 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
939 iris_emit_pipe_control_flush(batch
, flush
);
941 ice
->state
.dirty
|= dirty
;
944 static enum pipe_format
945 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
947 struct iris_resource
*res
= (void *) p_res
;
948 return res
->internal_format
;
951 static const struct u_transfer_vtbl transfer_vtbl
= {
952 .resource_create
= iris_resource_create
,
953 .resource_destroy
= iris_resource_destroy
,
954 .transfer_map
= iris_transfer_map
,
955 .transfer_unmap
= iris_transfer_unmap
,
956 .transfer_flush_region
= iris_transfer_flush_region
,
957 .get_internal_format
= iris_resource_get_internal_format
,
958 .set_stencil
= iris_resource_set_separate_stencil
,
959 .get_stencil
= iris_resource_get_separate_stencil
,
963 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
965 pscreen
->resource_create_with_modifiers
=
966 iris_resource_create_with_modifiers
;
967 pscreen
->resource_create
= u_transfer_helper_resource_create
;
968 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
969 pscreen
->resource_from_handle
= iris_resource_from_handle
;
970 pscreen
->resource_get_handle
= iris_resource_get_handle
;
971 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
972 pscreen
->transfer_helper
=
973 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
977 iris_init_resource_functions(struct pipe_context
*ctx
)
979 ctx
->flush_resource
= iris_flush_resource
;
980 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
981 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
982 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
983 ctx
->buffer_subdata
= u_default_buffer_subdata
;
984 ctx
->texture_subdata
= u_default_texture_subdata
;