2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/dev/gen_debug.h"
52 #include "drm-uapi/drm_fourcc.h"
53 #include "drm-uapi/i915_drm.h"
55 enum modifier_priority
{
56 MODIFIER_PRIORITY_INVALID
= 0,
57 MODIFIER_PRIORITY_LINEAR
,
60 MODIFIER_PRIORITY_Y_CCS
,
63 static const uint64_t priority_to_modifier
[] = {
64 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
65 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
66 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
67 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
68 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
72 modifier_is_supported(const struct gen_device_info
*devinfo
,
75 /* XXX: do something real */
77 case I915_FORMAT_MOD_Y_TILED
:
78 case I915_FORMAT_MOD_X_TILED
:
79 case DRM_FORMAT_MOD_LINEAR
:
81 case I915_FORMAT_MOD_Y_TILED_CCS
:
82 case DRM_FORMAT_MOD_INVALID
:
89 select_best_modifier(struct gen_device_info
*devinfo
,
90 const uint64_t *modifiers
,
93 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
95 for (int i
= 0; i
< count
; i
++) {
96 if (!modifier_is_supported(devinfo
, modifiers
[i
]))
99 switch (modifiers
[i
]) {
100 case I915_FORMAT_MOD_Y_TILED_CCS
:
101 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
103 case I915_FORMAT_MOD_Y_TILED
:
104 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
106 case I915_FORMAT_MOD_X_TILED
:
107 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
109 case DRM_FORMAT_MOD_LINEAR
:
110 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
112 case DRM_FORMAT_MOD_INVALID
:
118 return priority_to_modifier
[prio
];
121 static enum isl_surf_dim
122 target_to_isl_surf_dim(enum pipe_texture_target target
)
126 case PIPE_TEXTURE_1D
:
127 case PIPE_TEXTURE_1D_ARRAY
:
128 return ISL_SURF_DIM_1D
;
129 case PIPE_TEXTURE_2D
:
130 case PIPE_TEXTURE_CUBE
:
131 case PIPE_TEXTURE_RECT
:
132 case PIPE_TEXTURE_2D_ARRAY
:
133 case PIPE_TEXTURE_CUBE_ARRAY
:
134 return ISL_SURF_DIM_2D
;
135 case PIPE_TEXTURE_3D
:
136 return ISL_SURF_DIM_3D
;
137 case PIPE_MAX_TEXTURE_TYPES
:
140 unreachable("invalid texture type");
144 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
145 enum pipe_format pfmt
,
148 unsigned int *external_only
,
151 struct iris_screen
*screen
= (void *) pscreen
;
152 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
154 uint64_t all_modifiers
[] = {
155 DRM_FORMAT_MOD_LINEAR
,
156 I915_FORMAT_MOD_X_TILED
,
157 I915_FORMAT_MOD_Y_TILED
,
158 // XXX: (broken) I915_FORMAT_MOD_Y_TILED_CCS,
161 int supported_mods
= 0;
163 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
164 if (!modifier_is_supported(devinfo
, all_modifiers
[i
]))
167 if (supported_mods
< max
) {
169 modifiers
[supported_mods
] = all_modifiers
[i
];
172 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
178 *count
= supported_mods
;
181 static isl_surf_usage_flags_t
182 pipe_bind_to_isl_usage(unsigned bindings
)
184 isl_surf_usage_flags_t usage
= 0;
186 if (bindings
& PIPE_BIND_RENDER_TARGET
)
187 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
189 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
190 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
192 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
193 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
195 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
196 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
201 struct pipe_resource
*
202 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
204 /* For packed depth-stencil, we treat depth as the primary resource
205 * and store S8 as the "second plane" resource.
207 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
215 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
216 struct pipe_resource
*stencil
)
218 assert(util_format_has_depth(util_format_description(p_res
->format
)));
219 pipe_resource_reference(&p_res
->next
, stencil
);
223 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
224 struct iris_resource
**out_z
,
225 struct iris_resource
**out_s
)
233 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
234 *out_z
= (void *) res
;
235 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
238 *out_s
= (void *) res
;
243 iris_resource_disable_aux(struct iris_resource
*res
)
245 iris_bo_unreference(res
->aux
.bo
);
246 iris_bo_unreference(res
->aux
.clear_color_bo
);
247 free(res
->aux
.state
);
249 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
250 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
251 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
252 res
->aux
.surf
.size_B
= 0;
254 res
->aux
.clear_color_bo
= NULL
;
255 res
->aux
.state
= NULL
;
259 iris_resource_destroy(struct pipe_screen
*screen
,
260 struct pipe_resource
*resource
)
262 struct iris_resource
*res
= (struct iris_resource
*)resource
;
264 if (resource
->target
== PIPE_BUFFER
)
265 util_range_destroy(&res
->valid_buffer_range
);
267 iris_resource_disable_aux(res
);
269 iris_bo_unreference(res
->bo
);
273 static struct iris_resource
*
274 iris_alloc_resource(struct pipe_screen
*pscreen
,
275 const struct pipe_resource
*templ
)
277 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
282 res
->base
.screen
= pscreen
;
283 pipe_reference_init(&res
->base
.reference
, 1);
285 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
286 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
288 if (templ
->target
== PIPE_BUFFER
)
289 util_range_init(&res
->valid_buffer_range
);
295 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
297 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
298 return minify(res
->surf
.logical_level0_px
.depth
, level
);
300 return res
->surf
.logical_level0_px
.array_len
;
303 static enum isl_aux_state
**
304 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
306 uint32_t total_slices
= 0;
307 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
308 total_slices
+= iris_get_num_logical_layers(res
, level
);
310 const size_t per_level_array_size
=
311 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
313 /* We're going to allocate a single chunk of data for both the per-level
314 * reference array and the arrays of aux_state. This makes cleanup
315 * significantly easier.
317 const size_t total_size
=
318 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
320 void *data
= malloc(total_size
);
324 enum isl_aux_state
**per_level_arr
= data
;
325 enum isl_aux_state
*s
= data
+ per_level_array_size
;
326 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
327 per_level_arr
[level
] = s
;
328 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
329 for (uint32_t a
= 0; a
< level_layers
; a
++)
332 assert((void *)s
== data
+ total_size
);
334 return per_level_arr
;
338 * Allocate the initial aux surface for a resource based on aux.usage
341 iris_resource_alloc_aux(struct iris_screen
*screen
, struct iris_resource
*res
)
343 struct isl_device
*isl_dev
= &screen
->isl_dev
;
344 enum isl_aux_state initial_state
;
345 UNUSED
bool ok
= false;
346 uint8_t memset_value
= 0;
347 uint32_t alloc_flags
= 0;
348 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
349 const unsigned clear_color_state_size
= devinfo
->gen
>= 10 ?
350 screen
->isl_dev
.ss
.clear_color_state_size
:
351 (devinfo
->gen
>= 9 ? screen
->isl_dev
.ss
.clear_value_size
: 0);
353 assert(!res
->aux
.bo
);
355 switch (res
->aux
.usage
) {
356 case ISL_AUX_USAGE_NONE
:
357 res
->aux
.surf
.size_B
= 0;
360 case ISL_AUX_USAGE_HIZ
:
361 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
363 ok
= isl_surf_get_hiz_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
365 case ISL_AUX_USAGE_MCS
:
366 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
368 * "When MCS buffer is enabled and bound to MSRT, it is required
369 * that it is cleared prior to any rendering."
371 * Since we only use the MCS buffer for rendering, we just clear it
372 * immediately on allocation. The clear value for MCS buffers is all
373 * 1's, so we simply memset it to 0xff.
375 initial_state
= ISL_AUX_STATE_CLEAR
;
377 ok
= isl_surf_get_mcs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
379 case ISL_AUX_USAGE_CCS_D
:
380 case ISL_AUX_USAGE_CCS_E
:
381 /* When CCS_E is used, we need to ensure that the CCS starts off in
382 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
385 * "If Software wants to enable Color Compression without Fast
386 * clear, Software needs to initialize MCS with zeros."
388 * A CCS value of 0 indicates that the corresponding block is in the
389 * pass-through state which is what we want.
391 * For CCS_D, do the same thing. On Gen9+, this avoids having any
392 * undefined bits in the aux buffer.
394 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
395 alloc_flags
|= BO_ALLOC_ZEROED
;
396 ok
= isl_surf_get_ccs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
, 0);
400 /* We should have a valid aux_surf. */
404 /* No work is needed for a zero-sized auxiliary buffer. */
405 if (res
->aux
.surf
.size_B
== 0)
408 /* Create the aux_state for the auxiliary buffer. */
409 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
413 uint64_t size
= res
->aux
.surf
.size_B
;
415 /* Allocate space in the buffer for storing the clear color. On modern
416 * platforms (gen > 9), we can read it directly from such buffer.
418 * On gen <= 9, we are going to store the clear color on the buffer
419 * anyways, and copy it back to the surface state during state emission.
421 res
->aux
.clear_color_offset
= size
;
422 size
+= clear_color_state_size
;
424 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
425 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
426 * of bytes instead of trying to recalculate based on different format
429 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
,
430 IRIS_MEMZONE_OTHER
, I915_TILING_Y
,
431 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
436 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
437 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
440 iris_resource_disable_aux(res
);
444 if (memset_value
!= 0)
445 memset(map
, memset_value
, res
->aux
.surf
.size_B
);
447 /* Zero the indirect clear color to match ::fast_clear_color. */
448 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
449 clear_color_state_size
);
451 iris_bo_unmap(res
->aux
.bo
);
454 if (clear_color_state_size
> 0) {
455 res
->aux
.clear_color_bo
= res
->aux
.bo
;
456 iris_bo_reference(res
->aux
.clear_color_bo
);
459 if (res
->aux
.usage
== ISL_AUX_USAGE_HIZ
) {
460 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
461 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
462 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
464 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
465 * For LOD == 0, we can grow the dimensions to make it work.
467 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
468 res
->aux
.has_hiz
|= 1 << level
;
476 supports_mcs(const struct isl_surf
*surf
)
478 /* MCS compression only applies to multisampled resources. */
479 if (surf
->samples
<= 1)
482 /* Depth and stencil buffers use the IMS (interleaved) layout. */
483 if (isl_surf_usage_is_depth_or_stencil(surf
->usage
))
490 supports_ccs(const struct gen_device_info
*devinfo
,
491 const struct isl_surf
*surf
)
493 /* CCS only supports singlesampled resources. */
494 if (surf
->samples
> 1)
497 /* Note: still need to check the format! */
502 static struct pipe_resource
*
503 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
504 const struct pipe_resource
*templ
)
506 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
507 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
509 assert(templ
->target
== PIPE_BUFFER
);
510 assert(templ
->height0
<= 1);
511 assert(templ
->depth0
<= 1);
512 assert(templ
->format
== PIPE_FORMAT_NONE
||
513 util_format_get_blocksize(templ
->format
) == 1);
515 res
->internal_format
= templ
->format
;
516 res
->surf
.tiling
= ISL_TILING_LINEAR
;
518 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
519 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
520 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
521 memzone
= IRIS_MEMZONE_SHADER
;
522 name
= "shader kernels";
523 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
524 memzone
= IRIS_MEMZONE_SURFACE
;
525 name
= "surface state";
526 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
527 memzone
= IRIS_MEMZONE_DYNAMIC
;
528 name
= "dynamic state";
531 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
533 iris_resource_destroy(pscreen
, &res
->base
);
540 static struct pipe_resource
*
541 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
542 const struct pipe_resource
*templ
,
543 const uint64_t *modifiers
,
546 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
547 struct gen_device_info
*devinfo
= &screen
->devinfo
;
548 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
553 const struct util_format_description
*format_desc
=
554 util_format_description(templ
->format
);
555 const bool has_depth
= util_format_has_depth(format_desc
);
557 select_best_modifier(devinfo
, modifiers
, modifiers_count
);
559 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
561 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
562 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
564 tiling_flags
= 1 << res
->mod_info
->tiling
;
566 if (modifiers_count
> 0) {
567 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
571 /* No modifiers - we can select our own tiling. */
574 /* Depth must be Y-tiled */
575 tiling_flags
= ISL_TILING_Y0_BIT
;
576 } else if (templ
->format
== PIPE_FORMAT_S8_UINT
) {
577 /* Stencil must be W-tiled */
578 tiling_flags
= ISL_TILING_W_BIT
;
579 } else if (templ
->target
== PIPE_BUFFER
||
580 templ
->target
== PIPE_TEXTURE_1D
||
581 templ
->target
== PIPE_TEXTURE_1D_ARRAY
) {
582 /* Use linear for buffers and 1D textures */
583 tiling_flags
= ISL_TILING_LINEAR_BIT
;
586 /* Use linear for staging buffers */
587 if (templ
->usage
== PIPE_USAGE_STAGING
||
588 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
589 tiling_flags
= ISL_TILING_LINEAR_BIT
;
592 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
594 if (templ
->target
== PIPE_TEXTURE_CUBE
||
595 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
596 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
598 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
599 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
600 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
602 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
605 enum pipe_format pfmt
= templ
->format
;
606 res
->internal_format
= pfmt
;
608 /* Should be handled by u_transfer_helper */
609 assert(!util_format_is_depth_and_stencil(pfmt
));
611 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
612 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
614 UNUSED
const bool isl_surf_created_successfully
=
615 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
616 .dim
= target_to_isl_surf_dim(templ
->target
),
618 .width
= templ
->width0
,
619 .height
= templ
->height0
,
620 .depth
= templ
->depth0
,
621 .levels
= templ
->last_level
+ 1,
622 .array_len
= templ
->array_size
,
623 .samples
= MAX2(templ
->nr_samples
, 1),
624 .min_alignment_B
= 0,
627 .tiling_flags
= tiling_flags
);
628 assert(isl_surf_created_successfully
);
631 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
632 } else if (supports_mcs(&res
->surf
)) {
633 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_MCS
;
634 } else if (has_depth
) {
635 if (likely(!(INTEL_DEBUG
& DEBUG_NO_HIZ
)))
636 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
637 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO_RBC
)) &&
638 supports_ccs(devinfo
, &res
->surf
)) {
639 if (isl_format_supports_ccs_e(devinfo
, res
->surf
.format
))
640 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
642 if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
643 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
646 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
648 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
650 /* We don't always support sampling with hiz. But when we do, it must be
653 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1) {
654 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
657 const char *name
= "miptree";
658 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
660 unsigned int flags
= 0;
661 if (templ
->usage
== PIPE_USAGE_STAGING
)
662 flags
|= BO_ALLOC_COHERENT
;
664 /* These are for u_upload_mgr buffers only */
665 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
666 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
667 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
669 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, res
->surf
.size_B
,
671 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
672 res
->surf
.row_pitch_B
, flags
);
677 if (!iris_resource_alloc_aux(screen
, res
))
678 iris_resource_disable_aux(res
);
683 fprintf(stderr
, "XXX: resource creation failed\n");
684 iris_resource_destroy(pscreen
, &res
->base
);
689 static struct pipe_resource
*
690 iris_resource_create(struct pipe_screen
*pscreen
,
691 const struct pipe_resource
*templ
)
693 if (templ
->target
== PIPE_BUFFER
)
694 return iris_resource_create_for_buffer(pscreen
, templ
);
696 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
700 tiling_to_modifier(uint32_t tiling
)
702 static const uint64_t map
[] = {
703 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
704 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
705 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
708 assert(tiling
< ARRAY_SIZE(map
));
713 static struct pipe_resource
*
714 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
715 const struct pipe_resource
*templ
,
718 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
719 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
720 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
724 assert(templ
->target
== PIPE_BUFFER
);
726 res
->internal_format
= templ
->format
;
727 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
728 user_memory
, templ
->width0
,
735 util_range_add(&res
->valid_buffer_range
, 0, templ
->width0
);
740 static struct pipe_resource
*
741 iris_resource_from_handle(struct pipe_screen
*pscreen
,
742 const struct pipe_resource
*templ
,
743 struct winsys_handle
*whandle
,
746 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
747 struct gen_device_info
*devinfo
= &screen
->devinfo
;
748 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
749 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
753 switch (whandle
->type
) {
754 case WINSYS_HANDLE_TYPE_FD
:
755 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
);
757 case WINSYS_HANDLE_TYPE_SHARED
:
758 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
762 unreachable("invalid winsys handle type");
767 res
->offset
= whandle
->offset
;
769 uint64_t modifier
= whandle
->modifier
;
770 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
771 modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
773 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
774 assert(res
->mod_info
);
776 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
778 const struct iris_format_info fmt
=
779 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
780 res
->internal_format
= templ
->format
;
782 if (templ
->target
== PIPE_BUFFER
) {
783 res
->surf
.tiling
= ISL_TILING_LINEAR
;
785 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
786 .dim
= target_to_isl_surf_dim(templ
->target
),
788 .width
= templ
->width0
,
789 .height
= templ
->height0
,
790 .depth
= templ
->depth0
,
791 .levels
= templ
->last_level
+ 1,
792 .array_len
= templ
->array_size
,
793 .samples
= MAX2(templ
->nr_samples
, 1),
794 .min_alignment_B
= 0,
795 .row_pitch_B
= whandle
->stride
,
797 .tiling_flags
= 1 << res
->mod_info
->tiling
);
799 assert(res
->bo
->tiling_mode
==
800 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
802 // XXX: create_ccs_buf_for_image?
803 if (!iris_resource_alloc_aux(screen
, res
))
810 iris_resource_destroy(pscreen
, &res
->base
);
815 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
817 struct iris_context
*ice
= (struct iris_context
*)ctx
;
818 struct iris_batch
*render_batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
819 struct iris_resource
*res
= (void *) resource
;
820 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
822 iris_resource_prepare_access(ice
, render_batch
, res
,
823 0, INTEL_REMAINING_LEVELS
,
824 0, INTEL_REMAINING_LAYERS
,
825 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
826 mod
? mod
->supports_clear_color
: false);
830 iris_resource_get_handle(struct pipe_screen
*pscreen
,
831 struct pipe_context
*ctx
,
832 struct pipe_resource
*resource
,
833 struct winsys_handle
*whandle
,
836 struct iris_resource
*res
= (struct iris_resource
*)resource
;
838 /* Disable aux usage if explicit flush not set and this is the
839 * first time we are dealing with this resource.
841 if ((!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0)) {
842 if (p_atomic_read(&resource
->reference
.count
) == 1)
843 iris_resource_disable_aux(res
);
846 /* If this is a buffer, stride should be 0 - no need to special case */
847 whandle
->stride
= res
->surf
.row_pitch_B
;
849 res
->mod_info
? res
->mod_info
->modifier
850 : tiling_to_modifier(res
->bo
->tiling_mode
);
853 enum isl_aux_usage allowed_usage
=
854 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
856 if (res
->aux
.usage
!= allowed_usage
) {
857 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
858 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
859 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
863 switch (whandle
->type
) {
864 case WINSYS_HANDLE_TYPE_SHARED
:
865 return iris_bo_flink(res
->bo
, &whandle
->handle
) == 0;
866 case WINSYS_HANDLE_TYPE_KMS
:
867 whandle
->handle
= iris_bo_export_gem_handle(res
->bo
);
869 case WINSYS_HANDLE_TYPE_FD
:
870 return iris_bo_export_dmabuf(res
->bo
, (int *) &whandle
->handle
) == 0;
877 resource_is_busy(struct iris_context
*ice
,
878 struct iris_resource
*res
)
880 bool busy
= iris_bo_busy(res
->bo
);
882 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
883 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
889 iris_invalidate_resource(struct pipe_context
*ctx
,
890 struct pipe_resource
*resource
)
892 struct iris_screen
*screen
= (void *) ctx
->screen
;
893 struct iris_context
*ice
= (void *) ctx
;
894 struct iris_resource
*res
= (void *) resource
;
896 if (resource
->target
!= PIPE_BUFFER
)
899 if (!resource_is_busy(ice
, res
)) {
900 /* The resource is idle, so just mark that it contains no data and
901 * keep using the same underlying buffer object.
903 util_range_set_empty(&res
->valid_buffer_range
);
907 /* Otherwise, try and replace the backing storage with a new BO. */
909 /* We can't reallocate memory we didn't allocate in the first place. */
910 if (res
->bo
->userptr
)
913 // XXX: We should support this.
914 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
917 struct iris_bo
*old_bo
= res
->bo
;
918 struct iris_bo
*new_bo
=
919 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
920 iris_memzone_for_address(old_bo
->gtt_offset
));
924 /* Swap out the backing storage */
927 /* Rebind the buffer, replacing any state referring to the old BO's
928 * address, and marking state dirty so it's reemitted.
930 ice
->vtbl
.rebind_buffer(ice
, res
, old_bo
->gtt_offset
);
932 util_range_set_empty(&res
->valid_buffer_range
);
934 iris_bo_unreference(old_bo
);
938 iris_flush_staging_region(struct pipe_transfer
*xfer
,
939 const struct pipe_box
*flush_box
)
941 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
944 struct iris_transfer
*map
= (void *) xfer
;
946 struct pipe_box src_box
= *flush_box
;
948 /* Account for extra alignment padding in staging buffer */
949 if (xfer
->resource
->target
== PIPE_BUFFER
)
950 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
952 struct pipe_box dst_box
= (struct pipe_box
) {
953 .x
= xfer
->box
.x
+ flush_box
->x
,
954 .y
= xfer
->box
.y
+ flush_box
->y
,
955 .z
= xfer
->box
.z
+ flush_box
->z
,
956 .width
= flush_box
->width
,
957 .height
= flush_box
->height
,
958 .depth
= flush_box
->depth
,
961 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
962 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
967 iris_unmap_copy_region(struct iris_transfer
*map
)
969 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
975 iris_map_copy_region(struct iris_transfer
*map
)
977 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
978 struct pipe_transfer
*xfer
= &map
->base
;
979 struct pipe_box
*box
= &xfer
->box
;
980 struct iris_resource
*res
= (void *) xfer
->resource
;
982 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
983 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
985 struct pipe_resource templ
= (struct pipe_resource
) {
986 .usage
= PIPE_USAGE_STAGING
,
987 .width0
= box
->width
+ extra
,
988 .height0
= box
->height
,
990 .nr_samples
= xfer
->resource
->nr_samples
,
991 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
992 .array_size
= box
->depth
,
995 if (xfer
->resource
->target
== PIPE_BUFFER
)
996 templ
.target
= PIPE_BUFFER
;
997 else if (templ
.array_size
> 1)
998 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1000 templ
.target
= PIPE_TEXTURE_2D
;
1002 /* Depth, stencil, and ASTC can't be linear surfaces, so we can't use
1003 * xfer->resource->format directly. Pick a bpb compatible format so
1004 * resource creation will succeed; blorp_copy will override it anyway.
1006 switch (util_format_get_blocksizebits(res
->internal_format
)) {
1007 case 8: templ
.format
= PIPE_FORMAT_R8_UINT
; break;
1008 case 16: templ
.format
= PIPE_FORMAT_R8G8_UINT
; break;
1009 case 24: templ
.format
= PIPE_FORMAT_R8G8B8_UINT
; break;
1010 case 32: templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
; break;
1011 case 48: templ
.format
= PIPE_FORMAT_R16G16B16_UINT
; break;
1012 case 64: templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
; break;
1013 case 96: templ
.format
= PIPE_FORMAT_R32G32B32_UINT
; break;
1014 case 128: templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
; break;
1015 default: unreachable("Invalid bpb");
1018 map
->staging
= iris_resource_create(pscreen
, &templ
);
1019 assert(map
->staging
);
1021 if (templ
.target
!= PIPE_BUFFER
) {
1022 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1023 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1024 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1027 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1028 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1029 xfer
->resource
, xfer
->level
, box
);
1030 /* Ensure writes to the staging BO land before we map it below. */
1031 iris_emit_pipe_control_flush(map
->batch
,
1032 "transfer read: flush before mapping",
1033 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1034 PIPE_CONTROL_CS_STALL
);
1037 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1039 if (iris_batch_references(map
->batch
, staging_bo
))
1040 iris_batch_flush(map
->batch
);
1043 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1045 map
->unmap
= iris_unmap_copy_region
;
1049 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1050 unsigned *out_x0_el
, unsigned *out_y0_el
)
1052 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1053 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1055 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1060 * Get pointer offset into stencil buffer.
1062 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1063 * must decode the tile's layout in software.
1066 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1068 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1070 * Even though the returned offset is always positive, the return type is
1072 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1073 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1076 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1078 uint32_t tile_size
= 4096;
1079 uint32_t tile_width
= 64;
1080 uint32_t tile_height
= 64;
1081 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1083 uint32_t tile_x
= x
/ tile_width
;
1084 uint32_t tile_y
= y
/ tile_height
;
1086 /* The byte's address relative to the tile's base addres. */
1087 uint32_t byte_x
= x
% tile_width
;
1088 uint32_t byte_y
= y
% tile_height
;
1090 uintptr_t u
= tile_y
* row_size
1091 + tile_x
* tile_size
1092 + 512 * (byte_x
/ 8)
1094 + 32 * ((byte_y
/ 4) % 2)
1095 + 16 * ((byte_x
/ 4) % 2)
1096 + 8 * ((byte_y
/ 2) % 2)
1097 + 4 * ((byte_x
/ 2) % 2)
1102 /* adjust for bit6 swizzling */
1103 if (((byte_x
/ 8) % 2) == 1) {
1104 if (((byte_y
/ 8) % 2) == 0) {
1116 iris_unmap_s8(struct iris_transfer
*map
)
1118 struct pipe_transfer
*xfer
= &map
->base
;
1119 const struct pipe_box
*box
= &xfer
->box
;
1120 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1121 struct isl_surf
*surf
= &res
->surf
;
1122 const bool has_swizzling
= false;
1124 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1125 uint8_t *untiled_s8_map
= map
->ptr
;
1126 uint8_t *tiled_s8_map
=
1127 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1129 for (int s
= 0; s
< box
->depth
; s
++) {
1130 unsigned x0_el
, y0_el
;
1131 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1133 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1134 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1135 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1139 tiled_s8_map
[offset
] =
1140 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1150 iris_map_s8(struct iris_transfer
*map
)
1152 struct pipe_transfer
*xfer
= &map
->base
;
1153 const struct pipe_box
*box
= &xfer
->box
;
1154 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1155 struct isl_surf
*surf
= &res
->surf
;
1157 xfer
->stride
= surf
->row_pitch_B
;
1158 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1160 /* The tiling and detiling functions require that the linear buffer has
1161 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1162 * over-allocate the linear buffer to get the proper alignment.
1164 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1165 assert(map
->buffer
);
1167 const bool has_swizzling
= false;
1169 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1170 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1171 * invalidate is set, since we'll be writing the whole rectangle from our
1172 * temporary buffer back out.
1174 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1175 uint8_t *untiled_s8_map
= map
->ptr
;
1176 uint8_t *tiled_s8_map
=
1177 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1179 for (int s
= 0; s
< box
->depth
; s
++) {
1180 unsigned x0_el
, y0_el
;
1181 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1183 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1184 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1185 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1189 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1190 tiled_s8_map
[offset
];
1196 map
->unmap
= iris_unmap_s8
;
1199 /* Compute extent parameters for use with tiled_memcpy functions.
1200 * xs are in units of bytes and ys are in units of strides.
1203 tile_extents(const struct isl_surf
*surf
,
1204 const struct pipe_box
*box
,
1205 unsigned level
, int z
,
1206 unsigned *x1_B
, unsigned *x2_B
,
1207 unsigned *y1_el
, unsigned *y2_el
)
1209 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1210 const unsigned cpp
= fmtl
->bpb
/ 8;
1212 assert(box
->x
% fmtl
->bw
== 0);
1213 assert(box
->y
% fmtl
->bh
== 0);
1215 unsigned x0_el
, y0_el
;
1216 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1218 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1219 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1220 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1221 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1225 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1227 struct pipe_transfer
*xfer
= &map
->base
;
1228 const struct pipe_box
*box
= &xfer
->box
;
1229 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1230 struct isl_surf
*surf
= &res
->surf
;
1232 const bool has_swizzling
= false;
1234 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1236 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1238 for (int s
= 0; s
< box
->depth
; s
++) {
1239 unsigned x1
, x2
, y1
, y2
;
1240 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1242 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1244 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1245 surf
->row_pitch_B
, xfer
->stride
,
1246 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1249 os_free_aligned(map
->buffer
);
1250 map
->buffer
= map
->ptr
= NULL
;
1254 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1256 struct pipe_transfer
*xfer
= &map
->base
;
1257 const struct pipe_box
*box
= &xfer
->box
;
1258 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1259 struct isl_surf
*surf
= &res
->surf
;
1261 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1262 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1264 unsigned x1
, x2
, y1
, y2
;
1265 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1267 /* The tiling and detiling functions require that the linear buffer has
1268 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1269 * over-allocate the linear buffer to get the proper alignment.
1272 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1273 assert(map
->buffer
);
1274 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1276 const bool has_swizzling
= false;
1278 // XXX: PIPE_TRANSFER_READ?
1279 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1281 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1283 for (int s
= 0; s
< box
->depth
; s
++) {
1284 unsigned x1
, x2
, y1
, y2
;
1285 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1287 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1288 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1290 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1291 surf
->row_pitch_B
, has_swizzling
,
1292 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1296 map
->unmap
= iris_unmap_tiled_memcpy
;
1300 iris_map_direct(struct iris_transfer
*map
)
1302 struct pipe_transfer
*xfer
= &map
->base
;
1303 struct pipe_box
*box
= &xfer
->box
;
1304 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1306 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1308 if (res
->base
.target
== PIPE_BUFFER
) {
1310 xfer
->layer_stride
= 0;
1312 map
->ptr
= ptr
+ box
->x
;
1314 struct isl_surf
*surf
= &res
->surf
;
1315 const struct isl_format_layout
*fmtl
=
1316 isl_format_get_layout(surf
->format
);
1317 const unsigned cpp
= fmtl
->bpb
/ 8;
1318 unsigned x0_el
, y0_el
;
1320 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1322 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1323 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1325 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1330 can_promote_to_async(const struct iris_resource
*res
,
1331 const struct pipe_box
*box
,
1332 enum pipe_transfer_usage usage
)
1334 /* If we're writing to a section of the buffer that hasn't even been
1335 * initialized with useful data, then we can safely promote this write
1336 * to be unsynchronized. This helps the common pattern of appending data.
1338 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1339 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1340 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1341 box
->x
+ box
->width
);
1345 iris_transfer_map(struct pipe_context
*ctx
,
1346 struct pipe_resource
*resource
,
1348 enum pipe_transfer_usage usage
,
1349 const struct pipe_box
*box
,
1350 struct pipe_transfer
**ptransfer
)
1352 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1353 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1354 struct isl_surf
*surf
= &res
->surf
;
1356 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1357 /* Replace the backing storage with a fresh buffer for non-async maps */
1358 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1359 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1360 iris_invalidate_resource(ctx
, resource
);
1362 /* If we can discard the whole resource, we can discard the range. */
1363 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1366 bool map_would_stall
= false;
1368 if (resource
->target
!= PIPE_BUFFER
) {
1369 iris_resource_access_raw(ice
, &ice
->batches
[IRIS_BATCH_RENDER
], res
,
1370 level
, box
->z
, box
->depth
,
1371 usage
& PIPE_TRANSFER_WRITE
);
1374 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1375 can_promote_to_async(res
, box
, usage
)) {
1376 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1379 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1380 map_would_stall
= resource_is_busy(ice
, res
);
1382 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1383 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1387 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1388 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1391 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1392 struct pipe_transfer
*xfer
= &map
->base
;
1397 memset(map
, 0, sizeof(*map
));
1398 map
->dbg
= &ice
->dbg
;
1400 pipe_resource_reference(&xfer
->resource
, resource
);
1401 xfer
->level
= level
;
1402 xfer
->usage
= usage
;
1406 if (usage
& PIPE_TRANSFER_WRITE
)
1407 util_range_add(&res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1409 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1410 * there is to access them simultaneously on the CPU & GPU. This also
1411 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1412 * contain state we're constructing for a GPU draw call, which would
1413 * kill us with infinite stack recursion.
1415 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1416 PIPE_TRANSFER_COHERENT
|
1417 PIPE_TRANSFER_MAP_DIRECTLY
);
1419 /* GPU copies are not useful for buffer reads. Instead of stalling to
1420 * read from the original buffer, we'd simply copy it to a temporary...
1421 * then stall (a bit longer) to read from that buffer.
1423 * Images are less clear-cut. Color resolves are destructive, removing
1424 * the underlying compression, so we'd rather blit the data to a linear
1425 * temporary and map that, to avoid the resolve. (It might be better to
1426 * a tiled temporary and use the tiled_memcpy paths...)
1428 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) &&
1429 res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
&&
1430 res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
) {
1434 if ((map_would_stall
|| res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) && !no_gpu
) {
1435 /* If we need a synchronous mapping and the resource is busy,
1436 * we copy to/from a linear temporary buffer using the GPU.
1438 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1439 map
->blorp
= &ice
->blorp
;
1440 iris_map_copy_region(map
);
1442 /* Otherwise we're free to map on the CPU. Flush if needed. */
1443 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1444 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1445 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1446 iris_batch_flush(&ice
->batches
[i
]);
1450 if (surf
->tiling
== ISL_TILING_W
) {
1451 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1453 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1454 iris_map_tiled_memcpy(map
);
1456 iris_map_direct(map
);
1464 iris_transfer_flush_region(struct pipe_context
*ctx
,
1465 struct pipe_transfer
*xfer
,
1466 const struct pipe_box
*box
)
1468 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1469 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1470 struct iris_transfer
*map
= (void *) xfer
;
1473 iris_flush_staging_region(xfer
, box
);
1475 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1476 if (ice
->batches
[i
].contains_draw
||
1477 ice
->batches
[i
].cache
.render
->entries
) {
1478 iris_batch_maybe_flush(&ice
->batches
[i
], 24);
1479 iris_flush_and_dirty_for_history(ice
, &ice
->batches
[i
], res
,
1480 "cache history: transfer flush");
1484 /* Make sure we flag constants dirty even if there's no need to emit
1485 * any PIPE_CONTROLs to a batch.
1487 iris_dirty_for_history(ice
, res
);
1491 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1493 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1494 struct iris_transfer
*map
= (void *) xfer
;
1496 if (!(xfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
)) {
1497 struct pipe_box flush_box
= {
1498 .x
= 0, .y
= 0, .z
= 0,
1499 .width
= xfer
->box
.width
,
1500 .height
= xfer
->box
.height
,
1501 .depth
= xfer
->box
.depth
,
1503 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
1509 pipe_resource_reference(&xfer
->resource
, NULL
);
1510 slab_free(&ice
->transfer_pool
, map
);
1514 * Mark state dirty that needs to be re-emitted when a resource is written.
1517 iris_dirty_for_history(struct iris_context
*ice
,
1518 struct iris_resource
*res
)
1520 uint64_t dirty
= 0ull;
1522 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1523 dirty
|= IRIS_DIRTY_CONSTANTS_VS
|
1524 IRIS_DIRTY_CONSTANTS_TCS
|
1525 IRIS_DIRTY_CONSTANTS_TES
|
1526 IRIS_DIRTY_CONSTANTS_GS
|
1527 IRIS_DIRTY_CONSTANTS_FS
|
1528 IRIS_DIRTY_CONSTANTS_CS
|
1529 IRIS_ALL_DIRTY_BINDINGS
;
1532 ice
->state
.dirty
|= dirty
;
1536 * Produce a set of PIPE_CONTROL bits which ensure data written to a
1537 * resource becomes visible, and any stale read cache data is invalidated.
1540 iris_flush_bits_for_history(struct iris_resource
*res
)
1542 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
1544 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1545 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
1546 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1549 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
1550 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1552 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
1553 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1555 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
1556 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
1562 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
1563 struct iris_batch
*batch
,
1564 struct iris_resource
*res
,
1567 if (res
->base
.target
!= PIPE_BUFFER
)
1570 uint32_t flush
= iris_flush_bits_for_history(res
);
1572 /* We've likely used the rendering engine (i.e. BLORP) to write to this
1573 * surface. Flush the render cache so the data actually lands.
1575 if (batch
->name
!= IRIS_BATCH_COMPUTE
)
1576 flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
1578 iris_emit_pipe_control_flush(batch
, reason
, flush
);
1582 iris_resource_set_clear_color(struct iris_context
*ice
,
1583 struct iris_resource
*res
,
1584 union isl_color_value color
)
1586 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
1587 res
->aux
.clear_color
= color
;
1594 union isl_color_value
1595 iris_resource_get_clear_color(const struct iris_resource
*res
,
1596 struct iris_bo
**clear_color_bo
,
1597 uint64_t *clear_color_offset
)
1599 assert(res
->aux
.bo
);
1602 *clear_color_bo
= res
->aux
.clear_color_bo
;
1603 if (clear_color_offset
)
1604 *clear_color_offset
= res
->aux
.clear_color_offset
;
1605 return res
->aux
.clear_color
;
1608 static enum pipe_format
1609 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
1611 struct iris_resource
*res
= (void *) p_res
;
1612 return res
->internal_format
;
1615 static const struct u_transfer_vtbl transfer_vtbl
= {
1616 .resource_create
= iris_resource_create
,
1617 .resource_destroy
= iris_resource_destroy
,
1618 .transfer_map
= iris_transfer_map
,
1619 .transfer_unmap
= iris_transfer_unmap
,
1620 .transfer_flush_region
= iris_transfer_flush_region
,
1621 .get_internal_format
= iris_resource_get_internal_format
,
1622 .set_stencil
= iris_resource_set_separate_stencil
,
1623 .get_stencil
= iris_resource_get_separate_stencil
,
1627 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
1629 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
1630 pscreen
->resource_create_with_modifiers
=
1631 iris_resource_create_with_modifiers
;
1632 pscreen
->resource_create
= u_transfer_helper_resource_create
;
1633 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
1634 pscreen
->resource_from_handle
= iris_resource_from_handle
;
1635 pscreen
->resource_get_handle
= iris_resource_get_handle
;
1636 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
1637 pscreen
->transfer_helper
=
1638 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
1642 iris_init_resource_functions(struct pipe_context
*ctx
)
1644 ctx
->flush_resource
= iris_flush_resource
;
1645 ctx
->invalidate_resource
= iris_invalidate_resource
;
1646 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
1647 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
1648 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
1649 ctx
->buffer_subdata
= u_default_buffer_subdata
;
1650 ctx
->texture_subdata
= u_default_texture_subdata
;