2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_transfer.h"
42 #include "util/u_transfer_helper.h"
43 #include "util/u_upload_mgr.h"
44 #include "util/ralloc.h"
45 #include "iris_batch.h"
46 #include "iris_context.h"
47 #include "iris_resource.h"
48 #include "iris_screen.h"
49 #include "intel/common/gen_debug.h"
51 #include "drm-uapi/drm_fourcc.h"
52 #include "drm-uapi/i915_drm.h"
54 enum modifier_priority
{
55 MODIFIER_PRIORITY_INVALID
= 0,
56 MODIFIER_PRIORITY_LINEAR
,
59 MODIFIER_PRIORITY_Y_CCS
,
62 static const uint64_t priority_to_modifier
[] = {
63 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
64 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
65 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
66 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
67 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
71 modifier_is_supported(const struct gen_device_info
*devinfo
,
74 /* XXX: do something real */
76 case I915_FORMAT_MOD_Y_TILED
:
77 case I915_FORMAT_MOD_X_TILED
:
78 case DRM_FORMAT_MOD_LINEAR
:
80 case I915_FORMAT_MOD_Y_TILED_CCS
:
81 case DRM_FORMAT_MOD_INVALID
:
88 select_best_modifier(struct gen_device_info
*devinfo
,
89 const uint64_t *modifiers
,
92 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
94 for (int i
= 0; i
< count
; i
++) {
95 if (!modifier_is_supported(devinfo
, modifiers
[i
]))
98 switch (modifiers
[i
]) {
99 case I915_FORMAT_MOD_Y_TILED_CCS
:
100 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
102 case I915_FORMAT_MOD_Y_TILED
:
103 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
105 case I915_FORMAT_MOD_X_TILED
:
106 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
108 case DRM_FORMAT_MOD_LINEAR
:
109 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
111 case DRM_FORMAT_MOD_INVALID
:
117 return priority_to_modifier
[prio
];
120 static enum isl_surf_dim
121 target_to_isl_surf_dim(enum pipe_texture_target target
)
125 case PIPE_TEXTURE_1D
:
126 case PIPE_TEXTURE_1D_ARRAY
:
127 return ISL_SURF_DIM_1D
;
128 case PIPE_TEXTURE_2D
:
129 case PIPE_TEXTURE_CUBE
:
130 case PIPE_TEXTURE_RECT
:
131 case PIPE_TEXTURE_2D_ARRAY
:
132 case PIPE_TEXTURE_CUBE_ARRAY
:
133 return ISL_SURF_DIM_2D
;
134 case PIPE_TEXTURE_3D
:
135 return ISL_SURF_DIM_3D
;
136 case PIPE_MAX_TEXTURE_TYPES
:
139 unreachable("invalid texture type");
142 static isl_surf_usage_flags_t
143 pipe_bind_to_isl_usage(unsigned bindings
)
145 isl_surf_usage_flags_t usage
= 0;
147 if (bindings
& PIPE_BIND_RENDER_TARGET
)
148 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
150 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
151 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
153 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
154 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
156 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
157 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
162 struct pipe_resource
*
163 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
165 /* For packed depth-stencil, we treat depth as the primary resource
166 * and store S8 as the "second plane" resource.
172 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
173 struct pipe_resource
*stencil
)
175 assert(util_format_has_depth(util_format_description(p_res
->format
)));
176 pipe_resource_reference(&p_res
->next
, stencil
);
180 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
181 struct iris_resource
**out_z
,
182 struct iris_resource
**out_s
)
190 const struct util_format_description
*desc
=
191 util_format_description(res
->format
);
193 if (util_format_has_depth(desc
)) {
194 *out_z
= (void *) res
;
195 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
197 assert(util_format_has_stencil(desc
));
199 *out_s
= (void *) res
;
204 iris_resource_destroy(struct pipe_screen
*screen
,
205 struct pipe_resource
*resource
)
207 struct iris_resource
*res
= (struct iris_resource
*)resource
;
209 iris_bo_unreference(res
->bo
);
213 static struct iris_resource
*
214 iris_alloc_resource(struct pipe_screen
*pscreen
,
215 const struct pipe_resource
*templ
)
217 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
222 res
->base
.screen
= pscreen
;
223 pipe_reference_init(&res
->base
.reference
, 1);
228 static struct pipe_resource
*
229 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
230 const struct pipe_resource
*templ
)
232 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
233 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
235 assert(templ
->target
== PIPE_BUFFER
);
236 assert(templ
->height0
<= 1);
237 assert(templ
->depth0
<= 1);
238 assert(templ
->format
== PIPE_FORMAT_NONE
||
239 util_format_get_blocksize(templ
->format
) == 1);
241 res
->internal_format
= templ
->format
;
242 res
->surf
.tiling
= ISL_TILING_LINEAR
;
244 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
245 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
246 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
247 memzone
= IRIS_MEMZONE_SHADER
;
248 name
= "shader kernels";
249 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
250 memzone
= IRIS_MEMZONE_SURFACE
;
251 name
= "surface state";
252 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
253 memzone
= IRIS_MEMZONE_DYNAMIC
;
254 name
= "dynamic state";
257 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
259 iris_resource_destroy(pscreen
, &res
->base
);
266 static struct pipe_resource
*
267 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
268 const struct pipe_resource
*templ
,
269 const uint64_t *modifiers
,
272 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
273 struct gen_device_info
*devinfo
= &screen
->devinfo
;
274 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
275 const struct util_format_description
*format_desc
=
276 util_format_description(templ
->format
);
281 const bool has_depth
= util_format_has_depth(format_desc
);
283 select_best_modifier(devinfo
, modifiers
, modifiers_count
);
285 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
287 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
288 const struct isl_drm_modifier_info
*mod_info
=
289 isl_drm_modifier_get_info(modifier
);
291 tiling_flags
= 1 << mod_info
->tiling
;
293 if (modifiers_count
> 0) {
294 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
298 /* No modifiers - we can select our own tiling. */
301 /* Depth must be Y-tiled */
302 tiling_flags
= ISL_TILING_Y0_BIT
;
303 } else if (templ
->format
== PIPE_FORMAT_S8_UINT
) {
304 /* Stencil must be W-tiled */
305 tiling_flags
= ISL_TILING_W_BIT
;
306 } else if (templ
->target
== PIPE_BUFFER
||
307 templ
->target
== PIPE_TEXTURE_1D
||
308 templ
->target
== PIPE_TEXTURE_1D_ARRAY
) {
309 /* Use linear for buffers and 1D textures */
310 tiling_flags
= ISL_TILING_LINEAR_BIT
;
313 /* Use linear for staging buffers */
314 if (templ
->usage
== PIPE_USAGE_STAGING
||
315 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
316 tiling_flags
= ISL_TILING_LINEAR_BIT
;
319 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
321 if (templ
->target
== PIPE_TEXTURE_CUBE
||
322 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
323 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
325 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
326 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
327 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
329 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
332 enum pipe_format pfmt
= templ
->format
;
333 res
->internal_format
= pfmt
;
335 /* Should be handled by u_transfer_helper */
336 assert(!util_format_is_depth_and_stencil(pfmt
));
338 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
339 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
341 UNUSED
const bool isl_surf_created_successfully
=
342 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
343 .dim
= target_to_isl_surf_dim(templ
->target
),
345 .width
= templ
->width0
,
346 .height
= templ
->height0
,
347 .depth
= templ
->depth0
,
348 .levels
= templ
->last_level
+ 1,
349 .array_len
= templ
->array_size
,
350 .samples
= MAX2(templ
->nr_samples
, 1),
351 .min_alignment_B
= 0,
354 .tiling_flags
= tiling_flags
);
355 assert(isl_surf_created_successfully
);
357 const char *name
= "miptree";
359 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
361 /* These are for u_upload_mgr buffers only */
362 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
363 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
364 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
366 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, res
->surf
.size_B
,
368 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
369 res
->surf
.row_pitch_B
, 0);
371 iris_resource_destroy(pscreen
, &res
->base
);
378 static struct pipe_resource
*
379 iris_resource_create(struct pipe_screen
*pscreen
,
380 const struct pipe_resource
*templ
)
382 if (templ
->target
== PIPE_BUFFER
)
383 return iris_resource_create_for_buffer(pscreen
, templ
);
385 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
389 tiling_to_modifier(uint32_t tiling
)
391 static const uint64_t map
[] = {
392 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
393 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
394 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
397 assert(tiling
< ARRAY_SIZE(map
));
402 static struct pipe_resource
*
403 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
404 const struct pipe_resource
*templ
,
407 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
408 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
409 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
413 assert(templ
->target
== PIPE_BUFFER
);
415 res
->internal_format
= templ
->format
;
416 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
417 user_memory
, templ
->width0
,
427 static struct pipe_resource
*
428 iris_resource_from_handle(struct pipe_screen
*pscreen
,
429 const struct pipe_resource
*templ
,
430 struct winsys_handle
*whandle
,
433 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
434 struct gen_device_info
*devinfo
= &screen
->devinfo
;
435 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
436 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
440 if (whandle
->offset
!= 0) {
441 dbg_printf("Attempt to import unsupported winsys offset %u\n",
446 switch (whandle
->type
) {
447 case WINSYS_HANDLE_TYPE_FD
:
448 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
);
450 case WINSYS_HANDLE_TYPE_SHARED
:
451 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
455 unreachable("invalid winsys handle type");
460 uint64_t modifier
= whandle
->modifier
;
461 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
462 modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
464 const struct isl_drm_modifier_info
*mod_info
=
465 isl_drm_modifier_get_info(modifier
);
468 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
470 const struct iris_format_info fmt
=
471 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
473 if (templ
->target
== PIPE_BUFFER
) {
474 res
->surf
.tiling
= ISL_TILING_LINEAR
;
476 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
477 .dim
= target_to_isl_surf_dim(templ
->target
),
479 .width
= templ
->width0
,
480 .height
= templ
->height0
,
481 .depth
= templ
->depth0
,
482 .levels
= templ
->last_level
+ 1,
483 .array_len
= templ
->array_size
,
484 .samples
= MAX2(templ
->nr_samples
, 1),
485 .min_alignment_B
= 0,
486 .row_pitch_B
= whandle
->stride
,
488 .tiling_flags
= 1 << mod_info
->tiling
);
490 assert(res
->bo
->tiling_mode
==
491 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
497 iris_resource_destroy(pscreen
, &res
->base
);
502 iris_resource_get_handle(struct pipe_screen
*pscreen
,
503 struct pipe_context
*ctx
,
504 struct pipe_resource
*resource
,
505 struct winsys_handle
*whandle
,
508 struct iris_resource
*res
= (struct iris_resource
*)resource
;
510 /* If this is a buffer, stride should be 0 - no need to special case */
511 whandle
->stride
= res
->surf
.row_pitch_B
;
512 whandle
->modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
514 switch (whandle
->type
) {
515 case WINSYS_HANDLE_TYPE_SHARED
:
516 return iris_bo_flink(res
->bo
, &whandle
->handle
) == 0;
517 case WINSYS_HANDLE_TYPE_KMS
:
518 whandle
->handle
= iris_bo_export_gem_handle(res
->bo
);
520 case WINSYS_HANDLE_TYPE_FD
:
521 return iris_bo_export_dmabuf(res
->bo
, (int *) &whandle
->handle
) == 0;
528 get_image_offset_el(struct isl_surf
*surf
, unsigned level
, unsigned z
,
529 unsigned *out_x0_el
, unsigned *out_y0_el
)
531 if (surf
->dim
== ISL_SURF_DIM_3D
) {
532 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
534 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
539 * Get pointer offset into stencil buffer.
541 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
542 * must decode the tile's layout in software.
545 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
547 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
549 * Even though the returned offset is always positive, the return type is
551 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
552 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
555 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
557 uint32_t tile_size
= 4096;
558 uint32_t tile_width
= 64;
559 uint32_t tile_height
= 64;
560 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
562 uint32_t tile_x
= x
/ tile_width
;
563 uint32_t tile_y
= y
/ tile_height
;
565 /* The byte's address relative to the tile's base addres. */
566 uint32_t byte_x
= x
% tile_width
;
567 uint32_t byte_y
= y
% tile_height
;
569 uintptr_t u
= tile_y
* row_size
573 + 32 * ((byte_y
/ 4) % 2)
574 + 16 * ((byte_x
/ 4) % 2)
575 + 8 * ((byte_y
/ 2) % 2)
576 + 4 * ((byte_x
/ 2) % 2)
581 /* adjust for bit6 swizzling */
582 if (((byte_x
/ 8) % 2) == 1) {
583 if (((byte_y
/ 8) % 2) == 0) {
595 iris_unmap_s8(struct iris_transfer
*map
)
597 struct pipe_transfer
*xfer
= &map
->base
;
598 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
599 struct isl_surf
*surf
= &res
->surf
;
600 const bool has_swizzling
= false;
602 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
603 uint8_t *untiled_s8_map
= map
->ptr
;
604 uint8_t *tiled_s8_map
=
605 iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
607 struct pipe_box box
= xfer
->box
;
609 for (int s
= 0; s
< box
.depth
; s
++) {
610 unsigned x0_el
, y0_el
;
611 get_image_offset_el(surf
, xfer
->level
, box
.z
, &x0_el
, &y0_el
);
613 for (uint32_t y
= 0; y
< box
.height
; y
++) {
614 for (uint32_t x
= 0; x
< box
.width
; x
++) {
615 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
619 tiled_s8_map
[offset
] =
620 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
632 iris_map_s8(struct iris_transfer
*map
)
634 struct pipe_transfer
*xfer
= &map
->base
;
635 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
636 struct isl_surf
*surf
= &res
->surf
;
638 xfer
->stride
= surf
->row_pitch_B
;
639 xfer
->layer_stride
= xfer
->stride
* xfer
->box
.height
;
641 /* The tiling and detiling functions require that the linear buffer has
642 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
643 * over-allocate the linear buffer to get the proper alignment.
645 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* xfer
->box
.depth
);
648 const bool has_swizzling
= false;
650 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
651 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
652 * invalidate is set, since we'll be writing the whole rectangle from our
653 * temporary buffer back out.
655 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
656 uint8_t *untiled_s8_map
= map
->ptr
;
657 uint8_t *tiled_s8_map
=
658 iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
660 struct pipe_box box
= xfer
->box
;
662 for (int s
= 0; s
< box
.depth
; s
++) {
663 unsigned x0_el
, y0_el
;
664 get_image_offset_el(surf
, xfer
->level
, box
.z
, &x0_el
, &y0_el
);
666 for (uint32_t y
= 0; y
< box
.height
; y
++) {
667 for (uint32_t x
= 0; x
< box
.width
; x
++) {
668 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
672 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
673 tiled_s8_map
[offset
];
681 map
->unmap
= iris_unmap_s8
;
684 /* Compute extent parameters for use with tiled_memcpy functions.
685 * xs are in units of bytes and ys are in units of strides.
688 tile_extents(struct isl_surf
*surf
,
689 const struct pipe_box
*box
,
691 unsigned *x1_B
, unsigned *x2_B
,
692 unsigned *y1_el
, unsigned *y2_el
)
694 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
695 const unsigned cpp
= fmtl
->bpb
/ 8;
697 assert(box
->x
% fmtl
->bw
== 0);
698 assert(box
->y
% fmtl
->bh
== 0);
700 unsigned x0_el
, y0_el
;
701 get_image_offset_el(surf
, level
, box
->z
, &x0_el
, &y0_el
);
703 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
704 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
705 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
706 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
710 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
712 struct pipe_transfer
*xfer
= &map
->base
;
713 struct pipe_box box
= xfer
->box
;
714 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
715 struct isl_surf
*surf
= &res
->surf
;
717 const bool has_swizzling
= false;
719 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
720 char *dst
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
722 for (int s
= 0; s
< box
.depth
; s
++) {
723 unsigned x1
, x2
, y1
, y2
;
724 tile_extents(surf
, &box
, xfer
->level
, &x1
, &x2
, &y1
, &y2
);
726 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
728 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
729 surf
->row_pitch_B
, xfer
->stride
,
730 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
734 os_free_aligned(map
->buffer
);
735 map
->buffer
= map
->ptr
= NULL
;
739 iris_map_tiled_memcpy(struct iris_transfer
*map
)
741 struct pipe_transfer
*xfer
= &map
->base
;
742 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
743 struct isl_surf
*surf
= &res
->surf
;
745 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
746 xfer
->layer_stride
= xfer
->stride
* xfer
->box
.height
;
748 unsigned x1
, x2
, y1
, y2
;
749 tile_extents(surf
, &xfer
->box
, xfer
->level
, &x1
, &x2
, &y1
, &y2
);
751 /* The tiling and detiling functions require that the linear buffer has
752 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
753 * over-allocate the linear buffer to get the proper alignment.
756 os_malloc_aligned(xfer
->layer_stride
* xfer
->box
.depth
, 16);
758 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
760 const bool has_swizzling
= false;
762 // XXX: PIPE_TRANSFER_READ?
763 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
764 char *src
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
766 struct pipe_box box
= xfer
->box
;
768 for (int s
= 0; s
< box
.depth
; s
++) {
769 unsigned x1
, x2
, y1
, y2
;
770 tile_extents(surf
, &box
, xfer
->level
, &x1
, &x2
, &y1
, &y2
);
772 /* Use 's' rather than 'box.z' to rebase the first slice to 0. */
773 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
775 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
776 surf
->row_pitch_B
, has_swizzling
,
777 surf
->tiling
, ISL_MEMCPY
);
782 map
->unmap
= iris_unmap_tiled_memcpy
;
786 iris_map_direct(struct iris_transfer
*map
)
788 struct pipe_transfer
*xfer
= &map
->base
;
789 struct pipe_box
*box
= &xfer
->box
;
790 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
792 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
);
794 if (res
->base
.target
== PIPE_BUFFER
) {
796 xfer
->layer_stride
= 0;
798 map
->ptr
= ptr
+ box
->x
;
800 struct isl_surf
*surf
= &res
->surf
;
801 const struct isl_format_layout
*fmtl
=
802 isl_format_get_layout(surf
->format
);
803 const unsigned cpp
= fmtl
->bpb
/ 8;
804 unsigned x0_el
, y0_el
;
806 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
808 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
809 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
811 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
816 iris_transfer_map(struct pipe_context
*ctx
,
817 struct pipe_resource
*resource
,
819 enum pipe_transfer_usage usage
,
820 const struct pipe_box
*box
,
821 struct pipe_transfer
**ptransfer
)
823 struct iris_context
*ice
= (struct iris_context
*)ctx
;
824 struct iris_resource
*res
= (struct iris_resource
*)resource
;
825 struct isl_surf
*surf
= &res
->surf
;
827 /* If we can discard the whole resource, we can also discard the
828 * subrange being accessed.
830 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
)
831 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
833 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
834 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
837 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
838 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
839 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
840 iris_batch_flush(&ice
->batches
[i
]);
844 if ((usage
& PIPE_TRANSFER_DONTBLOCK
) && iris_bo_busy(res
->bo
))
847 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
848 struct pipe_transfer
*xfer
= &map
->base
;
853 memset(map
, 0, sizeof(*map
));
854 map
->dbg
= &ice
->dbg
;
856 pipe_resource_reference(&xfer
->resource
, resource
);
862 xfer
->usage
&= (PIPE_TRANSFER_READ
|
863 PIPE_TRANSFER_WRITE
|
864 PIPE_TRANSFER_UNSYNCHRONIZED
|
865 PIPE_TRANSFER_PERSISTENT
|
866 PIPE_TRANSFER_COHERENT
|
867 PIPE_TRANSFER_DISCARD_RANGE
);
869 if (surf
->tiling
== ISL_TILING_W
) {
870 // XXX: just teach iris_map_tiled_memcpy about W tiling...
872 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
873 iris_map_tiled_memcpy(map
);
875 iris_map_direct(map
);
882 iris_transfer_flush_region(struct pipe_context
*ctx
,
883 struct pipe_transfer
*xfer
,
884 const struct pipe_box
*box
)
886 struct iris_context
*ice
= (struct iris_context
*)ctx
;
887 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
890 // XXX: don't emit flushes in both engines...? we may also need to flush
891 // even if there isn't a draw yet - may still be stale data in caches...
892 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
893 if (ice
->batches
[i
].contains_draw
) {
894 iris_batch_maybe_flush(&ice
->batches
[i
], 24);
895 iris_flush_and_dirty_for_history(ice
, &ice
->batches
[i
], res
);
901 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
903 struct iris_context
*ice
= (struct iris_context
*)ctx
;
904 struct iris_transfer
*map
= (void *) xfer
;
905 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
910 // XXX: don't emit flushes in both engines...?
911 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
912 if (ice
->batches
[i
].contains_draw
) {
913 iris_batch_maybe_flush(&ice
->batches
[i
], 24);
914 iris_flush_and_dirty_for_history(ice
, &ice
->batches
[i
], res
);
918 pipe_resource_reference(&xfer
->resource
, NULL
);
919 slab_free(&ice
->transfer_pool
, map
);
923 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
928 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
929 struct iris_batch
*batch
,
930 struct iris_resource
*res
)
932 if (res
->base
.target
!= PIPE_BUFFER
)
935 unsigned flush
= PIPE_CONTROL_CS_STALL
;
937 /* We've likely used the rendering engine (i.e. BLORP) to write to this
938 * surface. Flush the render cache so the data actually lands.
940 if (batch
->name
!= IRIS_BATCH_COMPUTE
)
941 flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
943 uint64_t dirty
= 0ull;
945 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
946 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
947 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
948 dirty
|= IRIS_DIRTY_CONSTANTS_VS
|
949 IRIS_DIRTY_CONSTANTS_TCS
|
950 IRIS_DIRTY_CONSTANTS_TES
|
951 IRIS_DIRTY_CONSTANTS_GS
|
952 IRIS_DIRTY_CONSTANTS_FS
|
953 IRIS_DIRTY_CONSTANTS_CS
|
954 IRIS_ALL_DIRTY_BINDINGS
;
957 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
958 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
960 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
961 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
963 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
964 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
966 iris_emit_pipe_control_flush(batch
, flush
);
968 ice
->state
.dirty
|= dirty
;
971 static enum pipe_format
972 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
974 struct iris_resource
*res
= (void *) p_res
;
975 return res
->internal_format
;
978 static const struct u_transfer_vtbl transfer_vtbl
= {
979 .resource_create
= iris_resource_create
,
980 .resource_destroy
= iris_resource_destroy
,
981 .transfer_map
= iris_transfer_map
,
982 .transfer_unmap
= iris_transfer_unmap
,
983 .transfer_flush_region
= iris_transfer_flush_region
,
984 .get_internal_format
= iris_resource_get_internal_format
,
985 .set_stencil
= iris_resource_set_separate_stencil
,
986 .get_stencil
= iris_resource_get_separate_stencil
,
990 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
992 pscreen
->resource_create_with_modifiers
=
993 iris_resource_create_with_modifiers
;
994 pscreen
->resource_create
= u_transfer_helper_resource_create
;
995 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
996 pscreen
->resource_from_handle
= iris_resource_from_handle
;
997 pscreen
->resource_get_handle
= iris_resource_get_handle
;
998 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
999 pscreen
->transfer_helper
=
1000 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
1004 iris_init_resource_functions(struct pipe_context
*ctx
)
1006 ctx
->flush_resource
= iris_flush_resource
;
1007 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
1008 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
1009 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
1010 ctx
->buffer_subdata
= u_default_buffer_subdata
;
1011 ctx
->texture_subdata
= u_default_texture_subdata
;