2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/format/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
56 enum modifier_priority
{
57 MODIFIER_PRIORITY_INVALID
= 0,
58 MODIFIER_PRIORITY_LINEAR
,
61 MODIFIER_PRIORITY_Y_CCS
,
64 static const uint64_t priority_to_modifier
[] = {
65 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
66 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
67 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
68 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
69 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
73 modifier_is_supported(const struct gen_device_info
*devinfo
,
74 enum pipe_format pfmt
, uint64_t modifier
)
76 /* XXX: do something real */
78 case I915_FORMAT_MOD_Y_TILED_CCS
: {
79 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
82 enum isl_format rt_format
=
83 iris_format_for_usage(devinfo
, pfmt
,
84 ISL_SURF_USAGE_RENDER_TARGET_BIT
).fmt
;
86 enum isl_format linear_format
= isl_format_srgb_to_linear(rt_format
);
88 if (linear_format
== ISL_FORMAT_UNSUPPORTED
||
89 !isl_format_supports_ccs_e(devinfo
, linear_format
))
92 return devinfo
->gen
>= 9 && devinfo
->gen
<= 11;
94 case I915_FORMAT_MOD_Y_TILED
:
95 case I915_FORMAT_MOD_X_TILED
:
96 case DRM_FORMAT_MOD_LINEAR
:
98 case DRM_FORMAT_MOD_INVALID
:
105 select_best_modifier(struct gen_device_info
*devinfo
, enum pipe_format pfmt
,
106 const uint64_t *modifiers
,
109 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
111 for (int i
= 0; i
< count
; i
++) {
112 if (!modifier_is_supported(devinfo
, pfmt
, modifiers
[i
]))
115 switch (modifiers
[i
]) {
116 case I915_FORMAT_MOD_Y_TILED_CCS
:
117 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
119 case I915_FORMAT_MOD_Y_TILED
:
120 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
122 case I915_FORMAT_MOD_X_TILED
:
123 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
125 case DRM_FORMAT_MOD_LINEAR
:
126 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
128 case DRM_FORMAT_MOD_INVALID
:
134 return priority_to_modifier
[prio
];
138 target_to_isl_surf_dim(enum pipe_texture_target target
)
142 case PIPE_TEXTURE_1D
:
143 case PIPE_TEXTURE_1D_ARRAY
:
144 return ISL_SURF_DIM_1D
;
145 case PIPE_TEXTURE_2D
:
146 case PIPE_TEXTURE_CUBE
:
147 case PIPE_TEXTURE_RECT
:
148 case PIPE_TEXTURE_2D_ARRAY
:
149 case PIPE_TEXTURE_CUBE_ARRAY
:
150 return ISL_SURF_DIM_2D
;
151 case PIPE_TEXTURE_3D
:
152 return ISL_SURF_DIM_3D
;
153 case PIPE_MAX_TEXTURE_TYPES
:
156 unreachable("invalid texture type");
160 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
161 enum pipe_format pfmt
,
164 unsigned int *external_only
,
167 struct iris_screen
*screen
= (void *) pscreen
;
168 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
170 uint64_t all_modifiers
[] = {
171 DRM_FORMAT_MOD_LINEAR
,
172 I915_FORMAT_MOD_X_TILED
,
173 I915_FORMAT_MOD_Y_TILED
,
174 I915_FORMAT_MOD_Y_TILED_CCS
,
177 int supported_mods
= 0;
179 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
180 if (!modifier_is_supported(devinfo
, pfmt
, all_modifiers
[i
]))
183 if (supported_mods
< max
) {
185 modifiers
[supported_mods
] = all_modifiers
[i
];
188 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
194 *count
= supported_mods
;
197 static isl_surf_usage_flags_t
198 pipe_bind_to_isl_usage(unsigned bindings
)
200 isl_surf_usage_flags_t usage
= 0;
202 if (bindings
& PIPE_BIND_RENDER_TARGET
)
203 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
205 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
206 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
208 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
209 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
211 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
212 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
217 struct pipe_resource
*
218 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
220 /* For packed depth-stencil, we treat depth as the primary resource
221 * and store S8 as the "second plane" resource.
223 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
231 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
232 struct pipe_resource
*stencil
)
234 assert(util_format_has_depth(util_format_description(p_res
->format
)));
235 pipe_resource_reference(&p_res
->next
, stencil
);
239 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
240 struct iris_resource
**out_z
,
241 struct iris_resource
**out_s
)
249 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
250 *out_z
= (void *) res
;
251 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
254 *out_s
= (void *) res
;
259 iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
260 enum isl_tiling tiling
,
261 enum pipe_texture_target target
)
264 case PIPE_TEXTURE_1D
:
265 case PIPE_TEXTURE_1D_ARRAY
:
266 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
267 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
269 case PIPE_TEXTURE_2D
:
270 case PIPE_TEXTURE_2D_ARRAY
:
271 case PIPE_TEXTURE_RECT
:
272 case PIPE_TEXTURE_CUBE
:
273 case PIPE_TEXTURE_CUBE_ARRAY
:
274 return ISL_DIM_LAYOUT_GEN4_2D
;
276 case PIPE_TEXTURE_3D
:
277 return (devinfo
->gen
>= 9 ?
278 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
280 case PIPE_MAX_TEXTURE_TYPES
:
284 unreachable("invalid texture type");
288 iris_resource_disable_aux(struct iris_resource
*res
)
290 iris_bo_unreference(res
->aux
.bo
);
291 iris_bo_unreference(res
->aux
.clear_color_bo
);
292 free(res
->aux
.state
);
294 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
295 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
296 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
297 res
->aux
.has_hiz
= 0;
298 res
->aux
.surf
.size_B
= 0;
300 res
->aux
.extra_aux
.surf
.size_B
= 0;
301 res
->aux
.clear_color_bo
= NULL
;
302 res
->aux
.state
= NULL
;
306 iris_resource_destroy(struct pipe_screen
*screen
,
307 struct pipe_resource
*resource
)
309 struct iris_resource
*res
= (struct iris_resource
*)resource
;
311 if (resource
->target
== PIPE_BUFFER
)
312 util_range_destroy(&res
->valid_buffer_range
);
314 iris_resource_disable_aux(res
);
316 iris_bo_unreference(res
->bo
);
320 static struct iris_resource
*
321 iris_alloc_resource(struct pipe_screen
*pscreen
,
322 const struct pipe_resource
*templ
)
324 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
329 res
->base
.screen
= pscreen
;
330 pipe_reference_init(&res
->base
.reference
, 1);
332 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
333 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
335 if (templ
->target
== PIPE_BUFFER
)
336 util_range_init(&res
->valid_buffer_range
);
342 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
344 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
345 return minify(res
->surf
.logical_level0_px
.depth
, level
);
347 return res
->surf
.logical_level0_px
.array_len
;
350 static enum isl_aux_state
**
351 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
353 assert(res
->aux
.state
== NULL
);
355 uint32_t total_slices
= 0;
356 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
357 total_slices
+= iris_get_num_logical_layers(res
, level
);
359 const size_t per_level_array_size
=
360 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
362 /* We're going to allocate a single chunk of data for both the per-level
363 * reference array and the arrays of aux_state. This makes cleanup
364 * significantly easier.
366 const size_t total_size
=
367 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
369 void *data
= malloc(total_size
);
373 enum isl_aux_state
**per_level_arr
= data
;
374 enum isl_aux_state
*s
= data
+ per_level_array_size
;
375 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
376 per_level_arr
[level
] = s
;
377 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
378 for (uint32_t a
= 0; a
< level_layers
; a
++)
381 assert((void *)s
== data
+ total_size
);
383 return per_level_arr
;
387 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
389 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
390 return devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
: 0;
394 map_aux_addresses(struct iris_screen
*screen
, struct iris_resource
*res
)
396 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
397 if (devinfo
->gen
>= 12 && isl_aux_usage_has_ccs(res
->aux
.usage
)) {
398 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
400 const unsigned aux_offset
= res
->aux
.extra_aux
.surf
.size_B
> 0 ?
401 res
->aux
.extra_aux
.offset
: res
->aux
.offset
;
402 gen_aux_map_add_image(aux_map_ctx
, &res
->surf
, res
->bo
->gtt_offset
,
403 res
->aux
.bo
->gtt_offset
+ aux_offset
);
404 res
->bo
->aux_map_address
= res
->aux
.bo
->gtt_offset
;
409 want_ccs_e_for_format(const struct gen_device_info
*devinfo
,
410 enum isl_format format
)
412 if (!isl_format_supports_ccs_e(devinfo
, format
))
415 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
417 /* CCS_E seems to significantly hurt performance with 32-bit floating
418 * point formats. For example, Paraview's "Wavelet Volume" case uses
419 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
420 * formats causes a 62% FPS drop.
422 * However, many benchmarks seem to use 16-bit float with no issues.
424 if (fmtl
->channels
.r
.bits
== 32 && fmtl
->channels
.r
.type
== ISL_SFLOAT
)
431 * Configure aux for the resource, but don't allocate it. For images which
432 * might be shared with modifiers, we must allocate the image and aux data in
435 * Returns false on unexpected error (e.g. allocation failed, or invalid
436 * configuration result).
439 iris_resource_configure_aux(struct iris_screen
*screen
,
440 struct iris_resource
*res
, bool imported
,
441 uint64_t *aux_size_B
,
442 uint32_t *alloc_flags
)
444 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
446 /* Try to create the auxiliary surfaces allowed by the modifier or by
447 * the user if no modifier is specified.
449 assert(!res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
||
450 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
452 const bool has_mcs
= !res
->mod_info
&&
453 isl_surf_get_mcs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
455 const bool has_hiz
= !res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_HIZ
) &&
456 isl_surf_get_hiz_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
459 ((!res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_RBC
)) ||
460 (res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)) &&
461 isl_surf_get_ccs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
,
462 &res
->aux
.extra_aux
.surf
, 0);
464 /* Having both HIZ and MCS is impossible. */
465 assert(!has_mcs
|| !has_hiz
);
467 /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
468 if (has_ccs
&& (has_mcs
|| has_hiz
)) {
469 assert(res
->aux
.extra_aux
.surf
.size_B
> 0 &&
470 res
->aux
.extra_aux
.surf
.usage
& ISL_SURF_USAGE_CCS_BIT
);
471 assert(res
->aux
.surf
.size_B
> 0 &&
472 res
->aux
.surf
.usage
&
473 (ISL_SURF_USAGE_HIZ_BIT
| ISL_SURF_USAGE_MCS_BIT
));
476 if (res
->mod_info
&& has_ccs
) {
477 /* Only allow a CCS modifier if the aux was created successfully. */
478 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
479 } else if (has_mcs
) {
480 res
->aux
.possible_usages
|=
481 1 << (has_ccs
? ISL_AUX_USAGE_MCS_CCS
: ISL_AUX_USAGE_MCS
);
482 } else if (has_hiz
) {
484 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
485 } else if (res
->surf
.samples
== 1 &&
486 (res
->surf
.usage
& ISL_SURF_USAGE_TEXTURE_BIT
)) {
487 /* If this resource is single-sampled and will be used as a texture,
488 * put the HiZ surface in write-through mode so that we can sample
491 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS_WT
;
493 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS
;
495 } else if (has_ccs
&& isl_surf_usage_is_stencil(res
->surf
.usage
)) {
496 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_STC_CCS
;
497 } else if (has_ccs
) {
498 if (want_ccs_e_for_format(devinfo
, res
->surf
.format
))
499 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
501 if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
502 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
505 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
507 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
509 /* We don't always support sampling with hiz. But when we do, it must be
512 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1)
513 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
515 /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
516 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ_CCS
);
518 enum isl_aux_state initial_state
;
521 assert(!res
->aux
.bo
);
523 switch (res
->aux
.usage
) {
524 case ISL_AUX_USAGE_NONE
:
525 /* Having no aux buffer is only okay if there's no modifier with aux. */
526 return !res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
;
527 case ISL_AUX_USAGE_HIZ
:
528 case ISL_AUX_USAGE_HIZ_CCS
:
529 case ISL_AUX_USAGE_HIZ_CCS_WT
:
530 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
532 case ISL_AUX_USAGE_MCS
:
533 case ISL_AUX_USAGE_MCS_CCS
:
534 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
536 * "When MCS buffer is enabled and bound to MSRT, it is required
537 * that it is cleared prior to any rendering."
539 * Since we only use the MCS buffer for rendering, we just clear it
540 * immediately on allocation. The clear value for MCS buffers is all
541 * 1's, so we simply memset it to 0xff.
543 initial_state
= ISL_AUX_STATE_CLEAR
;
545 case ISL_AUX_USAGE_CCS_D
:
546 case ISL_AUX_USAGE_CCS_E
:
547 case ISL_AUX_USAGE_STC_CCS
:
548 /* When CCS_E is used, we need to ensure that the CCS starts off in
549 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
552 * "If Software wants to enable Color Compression without Fast
553 * clear, Software needs to initialize MCS with zeros."
555 * A CCS value of 0 indicates that the corresponding block is in the
556 * pass-through state which is what we want.
558 * For CCS_D, do the same thing. On Gen9+, this avoids having any
559 * undefined bits in the aux buffer.
562 assert(res
->aux
.usage
!= ISL_AUX_USAGE_STC_CCS
);
564 isl_drm_modifier_get_default_aux_state(res
->mod_info
->modifier
);
566 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
568 *alloc_flags
|= BO_ALLOC_ZEROED
;
570 case ISL_AUX_USAGE_MC
:
571 unreachable("Unsupported aux mode");
574 /* Create the aux_state for the auxiliary buffer. */
575 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
579 /* Increase the aux offset if the main and aux surfaces will share a BO. */
581 !res
->mod_info
|| res
->mod_info
->aux_usage
== res
->aux
.usage
?
582 ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
) : 0;
583 uint64_t size
= res
->aux
.surf
.size_B
;
585 /* Allocate space in the buffer for storing the CCS. */
586 if (res
->aux
.extra_aux
.surf
.size_B
> 0) {
587 const uint64_t padded_aux_size
=
588 ALIGN(size
, res
->aux
.extra_aux
.surf
.alignment_B
);
589 res
->aux
.extra_aux
.offset
= res
->aux
.offset
+ padded_aux_size
;
590 size
= padded_aux_size
+ res
->aux
.extra_aux
.surf
.size_B
;
593 /* Allocate space in the buffer for storing the clear color. On modern
594 * platforms (gen > 9), we can read it directly from such buffer.
596 * On gen <= 9, we are going to store the clear color on the buffer
597 * anyways, and copy it back to the surface state during state emission.
599 * Also add some padding to make sure the fast clear color state buffer
600 * starts at a 4K alignment. We believe that 256B might be enough, but due
601 * to lack of testing we will leave this as 4K for now.
603 size
= ALIGN(size
, 4096);
604 res
->aux
.clear_color_offset
= res
->aux
.offset
+ size
;
605 size
+= iris_get_aux_clear_color_state_size(screen
);
608 if (isl_aux_usage_has_hiz(res
->aux
.usage
)) {
609 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
610 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
611 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
613 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
614 * For LOD == 0, we can grow the dimensions to make it work.
616 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
617 res
->aux
.has_hiz
|= 1 << level
;
625 * Initialize the aux buffer contents.
627 * Returns false on unexpected error (e.g. mapping a BO failed).
630 iris_resource_init_aux_buf(struct iris_resource
*res
, uint32_t alloc_flags
,
631 unsigned clear_color_state_size
)
633 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
634 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
639 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
640 uint8_t memset_value
= isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0;
641 memset((char*)map
+ res
->aux
.offset
, memset_value
,
642 res
->aux
.surf
.size_B
);
645 /* Bspec section titled : MCS/CCS Buffers for Render Target(s) states:
646 * - If Software wants to enable Color Compression without Fast clear,
647 * Software needs to initialize MCS with zeros.
648 * - Lossless compression and CCS initialized to all F (using HW Fast
649 * Clear or SW direct Clear)
651 * We think, the first bullet point above is referring to CCS aux
652 * surface. Since we initialize the MCS in the clear state, we also
653 * initialize the CCS in the clear state (via SW direct clear) to keep
656 memset((char*)map
+ res
->aux
.extra_aux
.offset
,
657 isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0,
658 res
->aux
.extra_aux
.surf
.size_B
);
660 /* Zero the indirect clear color to match ::fast_clear_color. */
661 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
662 clear_color_state_size
);
664 iris_bo_unmap(res
->aux
.bo
);
667 if (clear_color_state_size
> 0) {
668 res
->aux
.clear_color_bo
= res
->aux
.bo
;
669 iris_bo_reference(res
->aux
.clear_color_bo
);
676 * Allocate the initial aux surface for a resource based on aux.usage
678 * Returns false on unexpected error (e.g. allocation failed, or invalid
679 * configuration result).
682 iris_resource_alloc_separate_aux(struct iris_screen
*screen
,
683 struct iris_resource
*res
)
685 uint32_t alloc_flags
;
687 if (!iris_resource_configure_aux(screen
, res
, false, &size
, &alloc_flags
))
693 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
694 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
695 * of bytes instead of trying to recalculate based on different format
698 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
, 4096,
700 isl_tiling_to_i915_tiling(res
->aux
.surf
.tiling
),
701 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
706 if (!iris_resource_init_aux_buf(res
, alloc_flags
,
707 iris_get_aux_clear_color_state_size(screen
)))
710 map_aux_addresses(screen
, res
);
716 iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
717 struct iris_resource
*res
)
719 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
720 assert(iris_resource_unfinished_aux_import(res
));
721 assert(!res
->mod_info
->supports_clear_color
);
723 struct iris_resource
*aux_res
= (void *) res
->base
.next
;
724 assert(aux_res
->aux
.surf
.row_pitch_B
&& aux_res
->aux
.offset
&&
727 assert(res
->bo
== aux_res
->aux
.bo
);
728 iris_bo_reference(aux_res
->aux
.bo
);
729 res
->aux
.bo
= aux_res
->aux
.bo
;
731 res
->aux
.offset
= aux_res
->aux
.offset
;
733 assert(res
->bo
->size
>= (res
->aux
.offset
+ res
->aux
.surf
.size_B
));
734 assert(res
->aux
.clear_color_bo
== NULL
);
735 res
->aux
.clear_color_offset
= 0;
737 assert(aux_res
->aux
.surf
.row_pitch_B
== res
->aux
.surf
.row_pitch_B
);
739 unsigned clear_color_state_size
=
740 iris_get_aux_clear_color_state_size(screen
);
742 if (clear_color_state_size
> 0) {
743 res
->aux
.clear_color_bo
=
744 iris_bo_alloc(screen
->bufmgr
, "clear color buffer",
745 clear_color_state_size
, IRIS_MEMZONE_OTHER
);
746 res
->aux
.clear_color_offset
= 0;
749 iris_resource_destroy(&screen
->base
, res
->base
.next
);
750 res
->base
.next
= NULL
;
753 static struct pipe_resource
*
754 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
755 const struct pipe_resource
*templ
)
757 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
758 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
760 assert(templ
->target
== PIPE_BUFFER
);
761 assert(templ
->height0
<= 1);
762 assert(templ
->depth0
<= 1);
763 assert(templ
->format
== PIPE_FORMAT_NONE
||
764 util_format_get_blocksize(templ
->format
) == 1);
766 res
->internal_format
= templ
->format
;
767 res
->surf
.tiling
= ISL_TILING_LINEAR
;
769 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
770 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
771 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
772 memzone
= IRIS_MEMZONE_SHADER
;
773 name
= "shader kernels";
774 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
775 memzone
= IRIS_MEMZONE_SURFACE
;
776 name
= "surface state";
777 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
778 memzone
= IRIS_MEMZONE_DYNAMIC
;
779 name
= "dynamic state";
782 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
784 iris_resource_destroy(pscreen
, &res
->base
);
791 static struct pipe_resource
*
792 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
793 const struct pipe_resource
*templ
,
794 const uint64_t *modifiers
,
797 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
798 struct gen_device_info
*devinfo
= &screen
->devinfo
;
799 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
804 const struct util_format_description
*format_desc
=
805 util_format_description(templ
->format
);
806 const bool has_depth
= util_format_has_depth(format_desc
);
808 select_best_modifier(devinfo
, templ
->format
, modifiers
, modifiers_count
);
810 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
812 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
813 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
815 tiling_flags
= 1 << res
->mod_info
->tiling
;
817 if (modifiers_count
> 0) {
818 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
822 /* Use linear for staging buffers */
823 if (templ
->usage
== PIPE_USAGE_STAGING
||
824 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
825 tiling_flags
= ISL_TILING_LINEAR_BIT
;
826 else if (templ
->bind
& PIPE_BIND_SCANOUT
)
827 tiling_flags
= ISL_TILING_X_BIT
;
830 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
832 if (templ
->target
== PIPE_TEXTURE_CUBE
||
833 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
834 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
836 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
837 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
838 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
840 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
843 enum pipe_format pfmt
= templ
->format
;
844 res
->internal_format
= pfmt
;
846 /* Should be handled by u_transfer_helper */
847 assert(!util_format_is_depth_and_stencil(pfmt
));
849 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
850 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
852 UNUSED
const bool isl_surf_created_successfully
=
853 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
854 .dim
= target_to_isl_surf_dim(templ
->target
),
856 .width
= templ
->width0
,
857 .height
= templ
->height0
,
858 .depth
= templ
->depth0
,
859 .levels
= templ
->last_level
+ 1,
860 .array_len
= templ
->array_size
,
861 .samples
= MAX2(templ
->nr_samples
, 1),
862 .min_alignment_B
= 0,
865 .tiling_flags
= tiling_flags
);
866 assert(isl_surf_created_successfully
);
868 const char *name
= "miptree";
869 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
871 unsigned int flags
= 0;
872 if (templ
->usage
== PIPE_USAGE_STAGING
)
873 flags
|= BO_ALLOC_COHERENT
;
875 /* These are for u_upload_mgr buffers only */
876 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
877 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
878 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
880 uint32_t aux_preferred_alloc_flags
;
881 uint64_t aux_size
= 0;
882 if (!iris_resource_configure_aux(screen
, res
, false, &aux_size
,
883 &aux_preferred_alloc_flags
)) {
887 /* Modifiers require the aux data to be in the same buffer as the main
888 * surface, but we combine them even when a modifiers is not being used.
890 const uint64_t bo_size
=
891 MAX2(res
->surf
.size_B
, res
->aux
.offset
+ aux_size
);
892 uint32_t alignment
= MAX2(4096, res
->surf
.alignment_B
);
893 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, alignment
,
895 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
896 res
->surf
.row_pitch_B
, flags
);
902 res
->aux
.bo
= res
->bo
;
903 iris_bo_reference(res
->aux
.bo
);
904 unsigned clear_color_state_size
=
905 iris_get_aux_clear_color_state_size(screen
);
906 if (!iris_resource_init_aux_buf(res
, flags
, clear_color_state_size
))
908 map_aux_addresses(screen
, res
);
914 fprintf(stderr
, "XXX: resource creation failed\n");
915 iris_resource_destroy(pscreen
, &res
->base
);
920 static struct pipe_resource
*
921 iris_resource_create(struct pipe_screen
*pscreen
,
922 const struct pipe_resource
*templ
)
924 if (templ
->target
== PIPE_BUFFER
)
925 return iris_resource_create_for_buffer(pscreen
, templ
);
927 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
931 tiling_to_modifier(uint32_t tiling
)
933 static const uint64_t map
[] = {
934 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
935 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
936 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
939 assert(tiling
< ARRAY_SIZE(map
));
944 static struct pipe_resource
*
945 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
946 const struct pipe_resource
*templ
,
949 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
950 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
951 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
955 assert(templ
->target
== PIPE_BUFFER
);
957 res
->internal_format
= templ
->format
;
958 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
959 user_memory
, templ
->width0
,
966 util_range_add(&res
->base
, &res
->valid_buffer_range
, 0, templ
->width0
);
971 static struct pipe_resource
*
972 iris_resource_from_handle(struct pipe_screen
*pscreen
,
973 const struct pipe_resource
*templ
,
974 struct winsys_handle
*whandle
,
977 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
978 struct gen_device_info
*devinfo
= &screen
->devinfo
;
979 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
980 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
981 const struct isl_drm_modifier_info
*mod_inf
=
982 isl_drm_modifier_get_info(whandle
->modifier
);
988 switch (whandle
->type
) {
989 case WINSYS_HANDLE_TYPE_FD
:
991 tiling
= isl_tiling_to_i915_tiling(mod_inf
->tiling
);
993 tiling
= I915_TILING_LAST
+ 1;
994 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
,
995 tiling
, whandle
->stride
);
997 case WINSYS_HANDLE_TYPE_SHARED
:
998 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
1002 unreachable("invalid winsys handle type");
1007 res
->offset
= whandle
->offset
;
1009 if (mod_inf
== NULL
) {
1011 isl_drm_modifier_get_info(tiling_to_modifier(res
->bo
->tiling_mode
));
1015 res
->external_format
= whandle
->format
;
1016 res
->mod_info
= mod_inf
;
1018 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
1020 const struct iris_format_info fmt
=
1021 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
1022 res
->internal_format
= templ
->format
;
1024 if (templ
->target
== PIPE_BUFFER
) {
1025 res
->surf
.tiling
= ISL_TILING_LINEAR
;
1027 /* Create a surface for each plane specified by the external format. */
1028 if (whandle
->plane
< util_format_get_num_planes(whandle
->format
)) {
1029 UNUSED
const bool isl_surf_created_successfully
=
1030 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
1031 .dim
= target_to_isl_surf_dim(templ
->target
),
1033 .width
= templ
->width0
,
1034 .height
= templ
->height0
,
1035 .depth
= templ
->depth0
,
1036 .levels
= templ
->last_level
+ 1,
1037 .array_len
= templ
->array_size
,
1038 .samples
= MAX2(templ
->nr_samples
, 1),
1039 .min_alignment_B
= 0,
1040 .row_pitch_B
= whandle
->stride
,
1042 .tiling_flags
= 1 << res
->mod_info
->tiling
);
1043 assert(isl_surf_created_successfully
);
1044 assert(res
->bo
->tiling_mode
==
1045 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
1047 // XXX: create_ccs_buf_for_image?
1048 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
) {
1049 if (!iris_resource_alloc_separate_aux(screen
, res
))
1052 if (res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1053 uint32_t alloc_flags
;
1055 bool ok
= iris_resource_configure_aux(screen
, res
, true, &size
,
1058 /* The gallium dri layer will create a separate plane resource
1059 * for the aux image. iris_resource_finish_aux_import will
1060 * merge the separate aux parameters back into a single
1066 /* Save modifier import information to reconstruct later. After
1067 * import, this will be available under a second image accessible
1068 * from the main image with res->base.next. See
1069 * iris_resource_finish_aux_import.
1071 res
->aux
.surf
.row_pitch_B
= whandle
->stride
;
1072 res
->aux
.offset
= whandle
->offset
;
1073 res
->aux
.bo
= res
->bo
;
1081 iris_resource_destroy(pscreen
, &res
->base
);
1086 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
1088 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1089 struct iris_batch
*render_batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1090 struct iris_resource
*res
= (void *) resource
;
1091 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
1093 iris_resource_prepare_access(ice
, render_batch
, res
,
1094 0, INTEL_REMAINING_LEVELS
,
1095 0, INTEL_REMAINING_LAYERS
,
1096 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
1097 mod
? mod
->supports_clear_color
: false);
1101 iris_resource_disable_aux_on_first_query(struct pipe_resource
*resource
,
1104 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1106 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1108 /* Disable aux usage if explicit flush not set and this is the first time
1109 * we are dealing with this resource and the resource was not created with
1110 * a modifier with aux.
1112 if (!mod_with_aux
&&
1113 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0) &&
1114 p_atomic_read(&resource
->reference
.count
) == 1) {
1115 iris_resource_disable_aux(res
);
1120 iris_resource_get_param(struct pipe_screen
*screen
,
1121 struct pipe_context
*context
,
1122 struct pipe_resource
*resource
,
1125 enum pipe_resource_param param
,
1126 unsigned handle_usage
,
1129 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1131 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1132 bool wants_aux
= mod_with_aux
&& plane
> 0;
1136 if (iris_resource_unfinished_aux_import(res
))
1137 iris_resource_finish_aux_import(screen
, res
);
1139 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
1141 iris_resource_disable_aux_on_first_query(resource
, handle_usage
);
1144 case PIPE_RESOURCE_PARAM_NPLANES
:
1149 for (struct pipe_resource
*cur
= resource
; cur
; cur
= cur
->next
)
1154 case PIPE_RESOURCE_PARAM_STRIDE
:
1155 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
1157 case PIPE_RESOURCE_PARAM_OFFSET
:
1158 *value
= wants_aux
? res
->aux
.offset
: 0;
1160 case PIPE_RESOURCE_PARAM_MODIFIER
:
1161 *value
= res
->mod_info
? res
->mod_info
->modifier
:
1162 tiling_to_modifier(res
->bo
->tiling_mode
);
1164 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
1165 result
= iris_bo_flink(bo
, &handle
) == 0;
1169 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
1170 *value
= iris_bo_export_gem_handle(bo
);
1172 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
1173 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
1183 iris_resource_get_handle(struct pipe_screen
*pscreen
,
1184 struct pipe_context
*ctx
,
1185 struct pipe_resource
*resource
,
1186 struct winsys_handle
*whandle
,
1189 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1191 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1193 iris_resource_disable_aux_on_first_query(resource
, usage
);
1196 if (mod_with_aux
&& whandle
->plane
> 0) {
1197 assert(res
->aux
.bo
);
1199 whandle
->stride
= res
->aux
.surf
.row_pitch_B
;
1200 whandle
->offset
= res
->aux
.offset
;
1202 /* If this is a buffer, stride should be 0 - no need to special case */
1203 whandle
->stride
= res
->surf
.row_pitch_B
;
1207 whandle
->format
= res
->external_format
;
1209 res
->mod_info
? res
->mod_info
->modifier
1210 : tiling_to_modifier(res
->bo
->tiling_mode
);
1213 enum isl_aux_usage allowed_usage
=
1214 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1216 if (res
->aux
.usage
!= allowed_usage
) {
1217 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
1218 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
1219 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
1223 switch (whandle
->type
) {
1224 case WINSYS_HANDLE_TYPE_SHARED
:
1225 return iris_bo_flink(bo
, &whandle
->handle
) == 0;
1226 case WINSYS_HANDLE_TYPE_KMS
:
1227 whandle
->handle
= iris_bo_export_gem_handle(bo
);
1229 case WINSYS_HANDLE_TYPE_FD
:
1230 return iris_bo_export_dmabuf(bo
, (int *) &whandle
->handle
) == 0;
1237 resource_is_busy(struct iris_context
*ice
,
1238 struct iris_resource
*res
)
1240 bool busy
= iris_bo_busy(res
->bo
);
1242 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1243 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1249 iris_invalidate_resource(struct pipe_context
*ctx
,
1250 struct pipe_resource
*resource
)
1252 struct iris_screen
*screen
= (void *) ctx
->screen
;
1253 struct iris_context
*ice
= (void *) ctx
;
1254 struct iris_resource
*res
= (void *) resource
;
1256 if (resource
->target
!= PIPE_BUFFER
)
1259 /* If it's already invalidated, don't bother doing anything. */
1260 if (res
->valid_buffer_range
.start
> res
->valid_buffer_range
.end
)
1263 if (!resource_is_busy(ice
, res
)) {
1264 /* The resource is idle, so just mark that it contains no data and
1265 * keep using the same underlying buffer object.
1267 util_range_set_empty(&res
->valid_buffer_range
);
1271 /* Otherwise, try and replace the backing storage with a new BO. */
1273 /* We can't reallocate memory we didn't allocate in the first place. */
1274 if (res
->bo
->userptr
)
1277 // XXX: We should support this.
1278 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1281 struct iris_bo
*old_bo
= res
->bo
;
1282 struct iris_bo
*new_bo
=
1283 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1284 iris_memzone_for_address(old_bo
->gtt_offset
));
1288 /* Swap out the backing storage */
1291 /* Rebind the buffer, replacing any state referring to the old BO's
1292 * address, and marking state dirty so it's reemitted.
1294 ice
->vtbl
.rebind_buffer(ice
, res
);
1296 util_range_set_empty(&res
->valid_buffer_range
);
1298 iris_bo_unreference(old_bo
);
1302 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1303 const struct pipe_box
*flush_box
)
1305 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1308 struct iris_transfer
*map
= (void *) xfer
;
1310 struct pipe_box src_box
= *flush_box
;
1312 /* Account for extra alignment padding in staging buffer */
1313 if (xfer
->resource
->target
== PIPE_BUFFER
)
1314 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1316 struct pipe_box dst_box
= (struct pipe_box
) {
1317 .x
= xfer
->box
.x
+ flush_box
->x
,
1318 .y
= xfer
->box
.y
+ flush_box
->y
,
1319 .z
= xfer
->box
.z
+ flush_box
->z
,
1320 .width
= flush_box
->width
,
1321 .height
= flush_box
->height
,
1322 .depth
= flush_box
->depth
,
1325 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1326 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1331 iris_unmap_copy_region(struct iris_transfer
*map
)
1333 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1339 iris_map_copy_region(struct iris_transfer
*map
)
1341 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1342 struct pipe_transfer
*xfer
= &map
->base
;
1343 struct pipe_box
*box
= &xfer
->box
;
1344 struct iris_resource
*res
= (void *) xfer
->resource
;
1346 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1347 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1349 struct pipe_resource templ
= (struct pipe_resource
) {
1350 .usage
= PIPE_USAGE_STAGING
,
1351 .width0
= box
->width
+ extra
,
1352 .height0
= box
->height
,
1354 .nr_samples
= xfer
->resource
->nr_samples
,
1355 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1356 .array_size
= box
->depth
,
1357 .format
= res
->internal_format
,
1360 if (xfer
->resource
->target
== PIPE_BUFFER
)
1361 templ
.target
= PIPE_BUFFER
;
1362 else if (templ
.array_size
> 1)
1363 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1365 templ
.target
= PIPE_TEXTURE_2D
;
1367 map
->staging
= iris_resource_create(pscreen
, &templ
);
1368 assert(map
->staging
);
1370 if (templ
.target
!= PIPE_BUFFER
) {
1371 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1372 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1373 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1376 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1377 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1378 xfer
->resource
, xfer
->level
, box
);
1379 /* Ensure writes to the staging BO land before we map it below. */
1380 iris_emit_pipe_control_flush(map
->batch
,
1381 "transfer read: flush before mapping",
1382 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1383 PIPE_CONTROL_CS_STALL
);
1386 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1388 if (iris_batch_references(map
->batch
, staging_bo
))
1389 iris_batch_flush(map
->batch
);
1392 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1394 map
->unmap
= iris_unmap_copy_region
;
1398 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1399 unsigned *out_x0_el
, unsigned *out_y0_el
)
1401 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1402 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1404 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1409 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1410 * different tiling patterns.
1413 iris_resource_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1414 uint32_t *tile_w
, uint32_t *tile_h
)
1425 case ISL_TILING_LINEAR
:
1430 unreachable("not reached");
1436 * This function computes masks that may be used to select the bits of the X
1437 * and Y coordinates that indicate the offset within a tile. If the BO is
1438 * untiled, the masks are set to 0.
1441 iris_resource_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1442 uint32_t *mask_x
, uint32_t *mask_y
)
1444 uint32_t tile_w_bytes
, tile_h
;
1446 iris_resource_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1448 *mask_x
= tile_w_bytes
/ cpp
- 1;
1449 *mask_y
= tile_h
- 1;
1453 * Compute the offset (in bytes) from the start of the BO to the given x
1454 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1455 * multiples of the tile size.
1458 iris_resource_get_aligned_offset(const struct iris_resource
*res
,
1459 uint32_t x
, uint32_t y
)
1461 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1462 unsigned cpp
= fmtl
->bpb
/ 8;
1463 uint32_t pitch
= res
->surf
.row_pitch_B
;
1465 switch (res
->surf
.tiling
) {
1467 unreachable("not reached");
1468 case ISL_TILING_LINEAR
:
1469 return y
* pitch
+ x
* cpp
;
1471 assert((x
% (512 / cpp
)) == 0);
1472 assert((y
% 8) == 0);
1473 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1475 assert((x
% (128 / cpp
)) == 0);
1476 assert((y
% 32) == 0);
1477 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1482 * Rendering with tiled buffers requires that the base address of the buffer
1483 * be aligned to a page boundary. For renderbuffers, and sometimes with
1484 * textures, we may want the surface to point at a texture image level that
1485 * isn't at a page boundary.
1487 * This function returns an appropriately-aligned base offset
1488 * according to the tiling restrictions, plus any required x/y offset
1492 iris_resource_get_tile_offsets(const struct iris_resource
*res
,
1493 uint32_t level
, uint32_t z
,
1494 uint32_t *tile_x
, uint32_t *tile_y
)
1497 uint32_t mask_x
, mask_y
;
1499 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1500 const unsigned cpp
= fmtl
->bpb
/ 8;
1502 iris_resource_get_tile_masks(res
->surf
.tiling
, cpp
, &mask_x
, &mask_y
);
1503 get_image_offset_el(&res
->surf
, level
, z
, &x
, &y
);
1505 *tile_x
= x
& mask_x
;
1506 *tile_y
= y
& mask_y
;
1508 return iris_resource_get_aligned_offset(res
, x
& ~mask_x
, y
& ~mask_y
);
1512 * Get pointer offset into stencil buffer.
1514 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1515 * must decode the tile's layout in software.
1518 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1520 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1522 * Even though the returned offset is always positive, the return type is
1524 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1525 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1528 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
)
1530 uint32_t tile_size
= 4096;
1531 uint32_t tile_width
= 64;
1532 uint32_t tile_height
= 64;
1533 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1535 uint32_t tile_x
= x
/ tile_width
;
1536 uint32_t tile_y
= y
/ tile_height
;
1538 /* The byte's address relative to the tile's base addres. */
1539 uint32_t byte_x
= x
% tile_width
;
1540 uint32_t byte_y
= y
% tile_height
;
1542 uintptr_t u
= tile_y
* row_size
1543 + tile_x
* tile_size
1544 + 512 * (byte_x
/ 8)
1546 + 32 * ((byte_y
/ 4) % 2)
1547 + 16 * ((byte_x
/ 4) % 2)
1548 + 8 * ((byte_y
/ 2) % 2)
1549 + 4 * ((byte_x
/ 2) % 2)
1557 iris_unmap_s8(struct iris_transfer
*map
)
1559 struct pipe_transfer
*xfer
= &map
->base
;
1560 const struct pipe_box
*box
= &xfer
->box
;
1561 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1562 struct isl_surf
*surf
= &res
->surf
;
1564 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1565 uint8_t *untiled_s8_map
= map
->ptr
;
1566 uint8_t *tiled_s8_map
=
1567 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1569 for (int s
= 0; s
< box
->depth
; s
++) {
1570 unsigned x0_el
, y0_el
;
1571 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1573 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1574 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1575 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1577 y0_el
+ box
->y
+ y
);
1578 tiled_s8_map
[offset
] =
1579 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1589 iris_map_s8(struct iris_transfer
*map
)
1591 struct pipe_transfer
*xfer
= &map
->base
;
1592 const struct pipe_box
*box
= &xfer
->box
;
1593 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1594 struct isl_surf
*surf
= &res
->surf
;
1596 xfer
->stride
= surf
->row_pitch_B
;
1597 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1599 /* The tiling and detiling functions require that the linear buffer has
1600 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1601 * over-allocate the linear buffer to get the proper alignment.
1603 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1604 assert(map
->buffer
);
1606 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1607 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1608 * invalidate is set, since we'll be writing the whole rectangle from our
1609 * temporary buffer back out.
1611 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1612 uint8_t *untiled_s8_map
= map
->ptr
;
1613 uint8_t *tiled_s8_map
=
1614 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1616 for (int s
= 0; s
< box
->depth
; s
++) {
1617 unsigned x0_el
, y0_el
;
1618 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1620 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1621 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1622 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1624 y0_el
+ box
->y
+ y
);
1625 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1626 tiled_s8_map
[offset
];
1632 map
->unmap
= iris_unmap_s8
;
1635 /* Compute extent parameters for use with tiled_memcpy functions.
1636 * xs are in units of bytes and ys are in units of strides.
1639 tile_extents(const struct isl_surf
*surf
,
1640 const struct pipe_box
*box
,
1641 unsigned level
, int z
,
1642 unsigned *x1_B
, unsigned *x2_B
,
1643 unsigned *y1_el
, unsigned *y2_el
)
1645 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1646 const unsigned cpp
= fmtl
->bpb
/ 8;
1648 assert(box
->x
% fmtl
->bw
== 0);
1649 assert(box
->y
% fmtl
->bh
== 0);
1651 unsigned x0_el
, y0_el
;
1652 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1654 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1655 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1656 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1657 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1661 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1663 struct pipe_transfer
*xfer
= &map
->base
;
1664 const struct pipe_box
*box
= &xfer
->box
;
1665 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1666 struct isl_surf
*surf
= &res
->surf
;
1668 const bool has_swizzling
= false;
1670 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1672 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1674 for (int s
= 0; s
< box
->depth
; s
++) {
1675 unsigned x1
, x2
, y1
, y2
;
1676 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1678 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1680 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1681 surf
->row_pitch_B
, xfer
->stride
,
1682 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1685 os_free_aligned(map
->buffer
);
1686 map
->buffer
= map
->ptr
= NULL
;
1690 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1692 struct pipe_transfer
*xfer
= &map
->base
;
1693 const struct pipe_box
*box
= &xfer
->box
;
1694 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1695 struct isl_surf
*surf
= &res
->surf
;
1697 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1698 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1700 unsigned x1
, x2
, y1
, y2
;
1701 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1703 /* The tiling and detiling functions require that the linear buffer has
1704 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1705 * over-allocate the linear buffer to get the proper alignment.
1708 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1709 assert(map
->buffer
);
1710 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1712 const bool has_swizzling
= false;
1714 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1716 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1718 for (int s
= 0; s
< box
->depth
; s
++) {
1719 unsigned x1
, x2
, y1
, y2
;
1720 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1722 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1723 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1725 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1726 surf
->row_pitch_B
, has_swizzling
,
1727 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1731 map
->unmap
= iris_unmap_tiled_memcpy
;
1735 iris_map_direct(struct iris_transfer
*map
)
1737 struct pipe_transfer
*xfer
= &map
->base
;
1738 struct pipe_box
*box
= &xfer
->box
;
1739 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1741 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1743 if (res
->base
.target
== PIPE_BUFFER
) {
1745 xfer
->layer_stride
= 0;
1747 map
->ptr
= ptr
+ box
->x
;
1749 struct isl_surf
*surf
= &res
->surf
;
1750 const struct isl_format_layout
*fmtl
=
1751 isl_format_get_layout(surf
->format
);
1752 const unsigned cpp
= fmtl
->bpb
/ 8;
1753 unsigned x0_el
, y0_el
;
1755 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1757 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1758 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1760 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1765 can_promote_to_async(const struct iris_resource
*res
,
1766 const struct pipe_box
*box
,
1767 enum pipe_transfer_usage usage
)
1769 /* If we're writing to a section of the buffer that hasn't even been
1770 * initialized with useful data, then we can safely promote this write
1771 * to be unsynchronized. This helps the common pattern of appending data.
1773 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1774 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1775 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1776 box
->x
+ box
->width
);
1780 iris_transfer_map(struct pipe_context
*ctx
,
1781 struct pipe_resource
*resource
,
1783 enum pipe_transfer_usage usage
,
1784 const struct pipe_box
*box
,
1785 struct pipe_transfer
**ptransfer
)
1787 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1788 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1789 struct isl_surf
*surf
= &res
->surf
;
1791 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1792 /* Replace the backing storage with a fresh buffer for non-async maps */
1793 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1794 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1795 iris_invalidate_resource(ctx
, resource
);
1797 /* If we can discard the whole resource, we can discard the range. */
1798 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1801 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1802 can_promote_to_async(res
, box
, usage
)) {
1803 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1806 bool need_resolve
= false;
1807 bool need_color_resolve
= false;
1809 if (resource
->target
!= PIPE_BUFFER
) {
1810 bool need_hiz_resolve
= iris_resource_level_has_hiz(res
, level
);
1811 bool need_stencil_resolve
= res
->aux
.usage
== ISL_AUX_USAGE_STC_CCS
;
1813 need_color_resolve
=
1814 (res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
||
1815 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) &&
1816 iris_has_color_unresolved(res
, level
, 1, box
->z
, box
->depth
);
1818 need_resolve
= need_color_resolve
||
1820 need_stencil_resolve
;
1823 bool map_would_stall
= false;
1825 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1826 map_would_stall
= need_resolve
|| resource_is_busy(ice
, res
);
1828 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1829 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1833 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1834 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1837 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1838 struct pipe_transfer
*xfer
= &map
->base
;
1843 memset(map
, 0, sizeof(*map
));
1844 map
->dbg
= &ice
->dbg
;
1846 pipe_resource_reference(&xfer
->resource
, resource
);
1847 xfer
->level
= level
;
1848 xfer
->usage
= usage
;
1852 map
->dest_had_defined_contents
=
1853 util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1854 box
->x
+ box
->width
);
1856 if (usage
& PIPE_TRANSFER_WRITE
)
1857 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1859 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1860 * there is to access them simultaneously on the CPU & GPU. This also
1861 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1862 * contain state we're constructing for a GPU draw call, which would
1863 * kill us with infinite stack recursion.
1865 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1866 PIPE_TRANSFER_COHERENT
|
1867 PIPE_TRANSFER_MAP_DIRECTLY
);
1869 /* GPU copies are not useful for buffer reads. Instead of stalling to
1870 * read from the original buffer, we'd simply copy it to a temporary...
1871 * then stall (a bit longer) to read from that buffer.
1873 * Images are less clear-cut. Color resolves are destructive, removing
1874 * the underlying compression, so we'd rather blit the data to a linear
1875 * temporary and map that, to avoid the resolve. (It might be better to
1876 * a tiled temporary and use the tiled_memcpy paths...)
1878 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) && !need_color_resolve
)
1881 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1882 if (fmtl
->txc
== ISL_TXC_ASTC
)
1885 if ((map_would_stall
|| res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) && !no_gpu
) {
1886 /* If we need a synchronous mapping and the resource is busy, or needs
1887 * resolving, we copy to/from a linear temporary buffer using the GPU.
1889 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1890 map
->blorp
= &ice
->blorp
;
1891 iris_map_copy_region(map
);
1893 /* Otherwise we're free to map on the CPU. */
1896 iris_resource_access_raw(ice
, &ice
->batches
[IRIS_BATCH_RENDER
], res
,
1897 level
, box
->z
, box
->depth
,
1898 usage
& PIPE_TRANSFER_WRITE
);
1901 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1902 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1903 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1904 iris_batch_flush(&ice
->batches
[i
]);
1908 if (surf
->tiling
== ISL_TILING_W
) {
1909 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1911 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1912 iris_map_tiled_memcpy(map
);
1914 iris_map_direct(map
);
1922 iris_transfer_flush_region(struct pipe_context
*ctx
,
1923 struct pipe_transfer
*xfer
,
1924 const struct pipe_box
*box
)
1926 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1927 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1928 struct iris_transfer
*map
= (void *) xfer
;
1931 iris_flush_staging_region(xfer
, box
);
1933 uint32_t history_flush
= 0;
1935 if (res
->base
.target
== PIPE_BUFFER
) {
1937 history_flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
1939 if (map
->dest_had_defined_contents
)
1940 history_flush
|= iris_flush_bits_for_history(res
);
1942 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1945 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
1946 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1947 struct iris_batch
*batch
= &ice
->batches
[i
];
1948 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
1949 iris_batch_maybe_flush(batch
, 24);
1950 iris_emit_pipe_control_flush(batch
,
1951 "cache history: transfer flush",
1957 /* Make sure we flag constants dirty even if there's no need to emit
1958 * any PIPE_CONTROLs to a batch.
1960 iris_dirty_for_history(ice
, res
);
1964 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1966 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1967 struct iris_transfer
*map
= (void *) xfer
;
1969 if (!(xfer
->usage
& (PIPE_TRANSFER_FLUSH_EXPLICIT
|
1970 PIPE_TRANSFER_COHERENT
))) {
1971 struct pipe_box flush_box
= {
1972 .x
= 0, .y
= 0, .z
= 0,
1973 .width
= xfer
->box
.width
,
1974 .height
= xfer
->box
.height
,
1975 .depth
= xfer
->box
.depth
,
1977 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
1983 pipe_resource_reference(&xfer
->resource
, NULL
);
1984 slab_free(&ice
->transfer_pool
, map
);
1988 * Mark state dirty that needs to be re-emitted when a resource is written.
1991 iris_dirty_for_history(struct iris_context
*ice
,
1992 struct iris_resource
*res
)
1994 uint64_t dirty
= 0ull;
1996 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1997 dirty
|= ((uint64_t)res
->bind_stages
) << IRIS_SHIFT_FOR_DIRTY_CONSTANTS
;
2000 ice
->state
.dirty
|= dirty
;
2004 * Produce a set of PIPE_CONTROL bits which ensure data written to a
2005 * resource becomes visible, and any stale read cache data is invalidated.
2008 iris_flush_bits_for_history(struct iris_resource
*res
)
2010 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
2012 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2013 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
2014 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2017 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
2018 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2020 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
2021 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
2023 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
2024 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
2030 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
2031 struct iris_batch
*batch
,
2032 struct iris_resource
*res
,
2033 uint32_t extra_flags
,
2036 if (res
->base
.target
!= PIPE_BUFFER
)
2039 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
2041 iris_emit_pipe_control_flush(batch
, reason
, flush
);
2043 iris_dirty_for_history(ice
, res
);
2047 iris_resource_set_clear_color(struct iris_context
*ice
,
2048 struct iris_resource
*res
,
2049 union isl_color_value color
)
2051 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
2052 res
->aux
.clear_color
= color
;
2059 union isl_color_value
2060 iris_resource_get_clear_color(const struct iris_resource
*res
,
2061 struct iris_bo
**clear_color_bo
,
2062 uint64_t *clear_color_offset
)
2064 assert(res
->aux
.bo
);
2067 *clear_color_bo
= res
->aux
.clear_color_bo
;
2068 if (clear_color_offset
)
2069 *clear_color_offset
= res
->aux
.clear_color_offset
;
2070 return res
->aux
.clear_color
;
2073 static enum pipe_format
2074 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
2076 struct iris_resource
*res
= (void *) p_res
;
2077 return res
->internal_format
;
2080 static const struct u_transfer_vtbl transfer_vtbl
= {
2081 .resource_create
= iris_resource_create
,
2082 .resource_destroy
= iris_resource_destroy
,
2083 .transfer_map
= iris_transfer_map
,
2084 .transfer_unmap
= iris_transfer_unmap
,
2085 .transfer_flush_region
= iris_transfer_flush_region
,
2086 .get_internal_format
= iris_resource_get_internal_format
,
2087 .set_stencil
= iris_resource_set_separate_stencil
,
2088 .get_stencil
= iris_resource_get_separate_stencil
,
2092 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
2094 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
2095 pscreen
->resource_create_with_modifiers
=
2096 iris_resource_create_with_modifiers
;
2097 pscreen
->resource_create
= u_transfer_helper_resource_create
;
2098 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
2099 pscreen
->resource_from_handle
= iris_resource_from_handle
;
2100 pscreen
->resource_get_handle
= iris_resource_get_handle
;
2101 pscreen
->resource_get_param
= iris_resource_get_param
;
2102 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
2103 pscreen
->transfer_helper
=
2104 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
2108 iris_init_resource_functions(struct pipe_context
*ctx
)
2110 ctx
->flush_resource
= iris_flush_resource
;
2111 ctx
->invalidate_resource
= iris_invalidate_resource
;
2112 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
2113 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
2114 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
2115 ctx
->buffer_subdata
= u_default_buffer_subdata
;
2116 ctx
->texture_subdata
= u_default_texture_subdata
;