2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/dev/gen_debug.h"
52 #include "drm-uapi/drm_fourcc.h"
53 #include "drm-uapi/i915_drm.h"
55 enum modifier_priority
{
56 MODIFIER_PRIORITY_INVALID
= 0,
57 MODIFIER_PRIORITY_LINEAR
,
60 MODIFIER_PRIORITY_Y_CCS
,
63 static const uint64_t priority_to_modifier
[] = {
64 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
65 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
66 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
67 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
68 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
72 modifier_is_supported(const struct gen_device_info
*devinfo
,
75 /* XXX: do something real */
77 case I915_FORMAT_MOD_Y_TILED
:
78 case I915_FORMAT_MOD_X_TILED
:
79 case DRM_FORMAT_MOD_LINEAR
:
81 case I915_FORMAT_MOD_Y_TILED_CCS
:
82 case DRM_FORMAT_MOD_INVALID
:
89 select_best_modifier(struct gen_device_info
*devinfo
,
90 const uint64_t *modifiers
,
93 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
95 for (int i
= 0; i
< count
; i
++) {
96 if (!modifier_is_supported(devinfo
, modifiers
[i
]))
99 switch (modifiers
[i
]) {
100 case I915_FORMAT_MOD_Y_TILED_CCS
:
101 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
103 case I915_FORMAT_MOD_Y_TILED
:
104 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
106 case I915_FORMAT_MOD_X_TILED
:
107 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
109 case DRM_FORMAT_MOD_LINEAR
:
110 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
112 case DRM_FORMAT_MOD_INVALID
:
118 return priority_to_modifier
[prio
];
121 static enum isl_surf_dim
122 target_to_isl_surf_dim(enum pipe_texture_target target
)
126 case PIPE_TEXTURE_1D
:
127 case PIPE_TEXTURE_1D_ARRAY
:
128 return ISL_SURF_DIM_1D
;
129 case PIPE_TEXTURE_2D
:
130 case PIPE_TEXTURE_CUBE
:
131 case PIPE_TEXTURE_RECT
:
132 case PIPE_TEXTURE_2D_ARRAY
:
133 case PIPE_TEXTURE_CUBE_ARRAY
:
134 return ISL_SURF_DIM_2D
;
135 case PIPE_TEXTURE_3D
:
136 return ISL_SURF_DIM_3D
;
137 case PIPE_MAX_TEXTURE_TYPES
:
140 unreachable("invalid texture type");
144 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
145 enum pipe_format pfmt
,
148 unsigned int *external_only
,
151 struct iris_screen
*screen
= (void *) pscreen
;
152 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
154 uint64_t all_modifiers
[] = {
155 DRM_FORMAT_MOD_LINEAR
,
156 I915_FORMAT_MOD_X_TILED
,
157 I915_FORMAT_MOD_Y_TILED
,
158 // XXX: (broken) I915_FORMAT_MOD_Y_TILED_CCS,
161 int supported_mods
= 0;
163 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
164 if (!modifier_is_supported(devinfo
, all_modifiers
[i
]))
167 if (supported_mods
< max
) {
169 modifiers
[supported_mods
] = all_modifiers
[i
];
172 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
178 *count
= supported_mods
;
181 static isl_surf_usage_flags_t
182 pipe_bind_to_isl_usage(unsigned bindings
)
184 isl_surf_usage_flags_t usage
= 0;
186 if (bindings
& PIPE_BIND_RENDER_TARGET
)
187 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
189 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
190 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
192 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
193 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
195 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
196 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
201 struct pipe_resource
*
202 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
204 /* For packed depth-stencil, we treat depth as the primary resource
205 * and store S8 as the "second plane" resource.
207 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
215 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
216 struct pipe_resource
*stencil
)
218 assert(util_format_has_depth(util_format_description(p_res
->format
)));
219 pipe_resource_reference(&p_res
->next
, stencil
);
223 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
224 struct iris_resource
**out_z
,
225 struct iris_resource
**out_s
)
233 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
234 *out_z
= (void *) res
;
235 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
238 *out_s
= (void *) res
;
243 iris_resource_disable_aux(struct iris_resource
*res
)
245 iris_bo_unreference(res
->aux
.bo
);
246 iris_bo_unreference(res
->aux
.clear_color_bo
);
247 free(res
->aux
.state
);
249 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
250 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
251 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
252 res
->aux
.surf
.size_B
= 0;
254 res
->aux
.clear_color_bo
= NULL
;
255 res
->aux
.state
= NULL
;
259 iris_resource_destroy(struct pipe_screen
*screen
,
260 struct pipe_resource
*resource
)
262 struct iris_resource
*res
= (struct iris_resource
*)resource
;
264 if (resource
->target
== PIPE_BUFFER
)
265 util_range_destroy(&res
->valid_buffer_range
);
267 iris_resource_disable_aux(res
);
269 iris_bo_unreference(res
->bo
);
273 static struct iris_resource
*
274 iris_alloc_resource(struct pipe_screen
*pscreen
,
275 const struct pipe_resource
*templ
)
277 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
282 res
->base
.screen
= pscreen
;
283 pipe_reference_init(&res
->base
.reference
, 1);
285 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
286 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
288 if (templ
->target
== PIPE_BUFFER
)
289 util_range_init(&res
->valid_buffer_range
);
295 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
297 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
298 return minify(res
->surf
.logical_level0_px
.depth
, level
);
300 return res
->surf
.logical_level0_px
.array_len
;
303 static enum isl_aux_state
**
304 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
306 uint32_t total_slices
= 0;
307 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
308 total_slices
+= iris_get_num_logical_layers(res
, level
);
310 const size_t per_level_array_size
=
311 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
313 /* We're going to allocate a single chunk of data for both the per-level
314 * reference array and the arrays of aux_state. This makes cleanup
315 * significantly easier.
317 const size_t total_size
=
318 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
320 void *data
= malloc(total_size
);
324 enum isl_aux_state
**per_level_arr
= data
;
325 enum isl_aux_state
*s
= data
+ per_level_array_size
;
326 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
327 per_level_arr
[level
] = s
;
328 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
329 for (uint32_t a
= 0; a
< level_layers
; a
++)
332 assert((void *)s
== data
+ total_size
);
334 return per_level_arr
;
338 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
340 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
342 (devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
:
343 (devinfo
->gen
>= 9 ? screen
->isl_dev
.ss
.clear_value_size
: 0));
347 * Configure aux for the resource, but don't allocate it. For images which
348 * might be shared with modifiers, we must allocate the image and aux data in
352 iris_resource_configure_aux(struct iris_screen
*screen
,
353 struct iris_resource
*res
, uint64_t *aux_size_B
,
354 uint32_t *alloc_flags
)
356 struct isl_device
*isl_dev
= &screen
->isl_dev
;
357 enum isl_aux_state initial_state
;
358 UNUSED
bool ok
= false;
362 assert(!res
->aux
.bo
);
364 switch (res
->aux
.usage
) {
365 case ISL_AUX_USAGE_NONE
:
366 res
->aux
.surf
.size_B
= 0;
369 case ISL_AUX_USAGE_HIZ
:
370 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
371 ok
= isl_surf_get_hiz_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
373 case ISL_AUX_USAGE_MCS
:
374 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
376 * "When MCS buffer is enabled and bound to MSRT, it is required
377 * that it is cleared prior to any rendering."
379 * Since we only use the MCS buffer for rendering, we just clear it
380 * immediately on allocation. The clear value for MCS buffers is all
381 * 1's, so we simply memset it to 0xff.
383 initial_state
= ISL_AUX_STATE_CLEAR
;
384 ok
= isl_surf_get_mcs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
386 case ISL_AUX_USAGE_CCS_D
:
387 case ISL_AUX_USAGE_CCS_E
:
388 /* When CCS_E is used, we need to ensure that the CCS starts off in
389 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
392 * "If Software wants to enable Color Compression without Fast
393 * clear, Software needs to initialize MCS with zeros."
395 * A CCS value of 0 indicates that the corresponding block is in the
396 * pass-through state which is what we want.
398 * For CCS_D, do the same thing. On Gen9+, this avoids having any
399 * undefined bits in the aux buffer.
401 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
402 *alloc_flags
|= BO_ALLOC_ZEROED
;
403 ok
= isl_surf_get_ccs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
, 0);
407 /* We should have a valid aux_surf. */
411 /* No work is needed for a zero-sized auxiliary buffer. */
412 if (res
->aux
.surf
.size_B
== 0)
415 if (!res
->aux
.state
) {
416 /* Create the aux_state for the auxiliary buffer. */
417 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
422 uint64_t size
= res
->aux
.surf
.size_B
;
424 /* Allocate space in the buffer for storing the clear color. On modern
425 * platforms (gen > 9), we can read it directly from such buffer.
427 * On gen <= 9, we are going to store the clear color on the buffer
428 * anyways, and copy it back to the surface state during state emission.
430 res
->aux
.clear_color_offset
= size
;
431 size
+= iris_get_aux_clear_color_state_size(screen
);
434 if (res
->aux
.usage
== ISL_AUX_USAGE_HIZ
) {
435 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
436 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
437 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
439 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
440 * For LOD == 0, we can grow the dimensions to make it work.
442 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
443 res
->aux
.has_hiz
|= 1 << level
;
451 * Initialize the aux buffer contents.
454 iris_resource_init_aux_buf(struct iris_resource
*res
, uint32_t alloc_flags
,
455 unsigned clear_color_state_size
)
457 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
458 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
461 iris_resource_disable_aux(res
);
465 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
466 uint8_t memset_value
= res
->aux
.usage
== ISL_AUX_USAGE_MCS
? 0xFF : 0;
467 memset((char*)map
+ res
->aux
.offset
, memset_value
,
468 res
->aux
.surf
.size_B
);
471 /* Zero the indirect clear color to match ::fast_clear_color. */
472 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
473 clear_color_state_size
);
475 iris_bo_unmap(res
->aux
.bo
);
478 if (clear_color_state_size
> 0) {
479 res
->aux
.clear_color_bo
= res
->aux
.bo
;
480 iris_bo_reference(res
->aux
.clear_color_bo
);
487 * Allocate the initial aux surface for a resource based on aux.usage
490 iris_resource_alloc_separate_aux(struct iris_screen
*screen
,
491 struct iris_resource
*res
)
493 uint32_t alloc_flags
;
495 if (!iris_resource_configure_aux(screen
, res
, &size
, &alloc_flags
))
501 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
502 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
503 * of bytes instead of trying to recalculate based on different format
506 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
, 4096,
507 IRIS_MEMZONE_OTHER
, I915_TILING_Y
,
508 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
513 if (!iris_resource_init_aux_buf(res
, alloc_flags
,
514 iris_get_aux_clear_color_state_size(screen
)))
521 supports_mcs(const struct isl_surf
*surf
)
523 /* MCS compression only applies to multisampled resources. */
524 if (surf
->samples
<= 1)
527 /* Depth and stencil buffers use the IMS (interleaved) layout. */
528 if (isl_surf_usage_is_depth_or_stencil(surf
->usage
))
535 supports_ccs(const struct gen_device_info
*devinfo
,
536 const struct isl_surf
*surf
)
538 /* CCS only supports singlesampled resources. */
539 if (surf
->samples
> 1)
542 /* Note: still need to check the format! */
547 static struct pipe_resource
*
548 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
549 const struct pipe_resource
*templ
)
551 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
552 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
554 assert(templ
->target
== PIPE_BUFFER
);
555 assert(templ
->height0
<= 1);
556 assert(templ
->depth0
<= 1);
557 assert(templ
->format
== PIPE_FORMAT_NONE
||
558 util_format_get_blocksize(templ
->format
) == 1);
560 res
->internal_format
= templ
->format
;
561 res
->surf
.tiling
= ISL_TILING_LINEAR
;
563 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
564 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
565 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
566 memzone
= IRIS_MEMZONE_SHADER
;
567 name
= "shader kernels";
568 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
569 memzone
= IRIS_MEMZONE_SURFACE
;
570 name
= "surface state";
571 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
572 memzone
= IRIS_MEMZONE_DYNAMIC
;
573 name
= "dynamic state";
576 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
578 iris_resource_destroy(pscreen
, &res
->base
);
585 static struct pipe_resource
*
586 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
587 const struct pipe_resource
*templ
,
588 const uint64_t *modifiers
,
591 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
592 struct gen_device_info
*devinfo
= &screen
->devinfo
;
593 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
598 const struct util_format_description
*format_desc
=
599 util_format_description(templ
->format
);
600 const bool has_depth
= util_format_has_depth(format_desc
);
602 select_best_modifier(devinfo
, modifiers
, modifiers_count
);
604 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
606 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
607 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
609 tiling_flags
= 1 << res
->mod_info
->tiling
;
611 if (modifiers_count
> 0) {
612 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
616 /* No modifiers - we can select our own tiling. */
619 /* Depth must be Y-tiled */
620 tiling_flags
= ISL_TILING_Y0_BIT
;
621 } else if (templ
->format
== PIPE_FORMAT_S8_UINT
) {
622 /* Stencil must be W-tiled */
623 tiling_flags
= ISL_TILING_W_BIT
;
624 } else if (templ
->target
== PIPE_BUFFER
||
625 templ
->target
== PIPE_TEXTURE_1D
||
626 templ
->target
== PIPE_TEXTURE_1D_ARRAY
) {
627 /* Use linear for buffers and 1D textures */
628 tiling_flags
= ISL_TILING_LINEAR_BIT
;
631 /* Use linear for staging buffers */
632 if (templ
->usage
== PIPE_USAGE_STAGING
||
633 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
634 tiling_flags
= ISL_TILING_LINEAR_BIT
;
637 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
639 if (templ
->target
== PIPE_TEXTURE_CUBE
||
640 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
641 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
643 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
644 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
645 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
647 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
650 enum pipe_format pfmt
= templ
->format
;
651 res
->internal_format
= pfmt
;
653 /* Should be handled by u_transfer_helper */
654 assert(!util_format_is_depth_and_stencil(pfmt
));
656 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
657 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
659 UNUSED
const bool isl_surf_created_successfully
=
660 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
661 .dim
= target_to_isl_surf_dim(templ
->target
),
663 .width
= templ
->width0
,
664 .height
= templ
->height0
,
665 .depth
= templ
->depth0
,
666 .levels
= templ
->last_level
+ 1,
667 .array_len
= templ
->array_size
,
668 .samples
= MAX2(templ
->nr_samples
, 1),
669 .min_alignment_B
= 0,
672 .tiling_flags
= tiling_flags
);
673 assert(isl_surf_created_successfully
);
676 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
677 } else if (supports_mcs(&res
->surf
)) {
678 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_MCS
;
679 } else if (has_depth
) {
680 if (likely(!(INTEL_DEBUG
& DEBUG_NO_HIZ
)))
681 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
682 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO_RBC
)) &&
683 supports_ccs(devinfo
, &res
->surf
)) {
684 if (isl_format_supports_ccs_e(devinfo
, res
->surf
.format
))
685 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
687 if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
688 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
691 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
693 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
695 /* We don't always support sampling with hiz. But when we do, it must be
698 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1) {
699 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
702 const char *name
= "miptree";
703 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
705 unsigned int flags
= 0;
706 if (templ
->usage
== PIPE_USAGE_STAGING
)
707 flags
|= BO_ALLOC_COHERENT
;
709 /* These are for u_upload_mgr buffers only */
710 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
711 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
712 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
714 uint32_t aux_preferred_alloc_flags
;
715 uint64_t aux_size
= 0;
717 iris_resource_configure_aux(screen
, res
, &aux_size
,
718 &aux_preferred_alloc_flags
);
719 aux_enabled
= aux_enabled
&& res
->aux
.surf
.size_B
> 0;
720 const bool separate_aux
= aux_enabled
&& !res
->mod_info
;
724 if (aux_enabled
&& !separate_aux
) {
725 /* Allocate aux data with main surface. This is required for modifiers
726 * with aux data (ccs).
728 aux_offset
= ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
);
729 bo_size
= aux_offset
+ aux_size
;
732 bo_size
= res
->surf
.size_B
;
735 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, 4096, memzone
,
736 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
737 res
->surf
.row_pitch_B
, flags
);
744 if (!iris_resource_alloc_separate_aux(screen
, res
))
747 res
->aux
.bo
= res
->bo
;
748 iris_bo_reference(res
->aux
.bo
);
749 res
->aux
.offset
+= aux_offset
;
750 unsigned clear_color_state_size
=
751 iris_get_aux_clear_color_state_size(screen
);
752 if (clear_color_state_size
> 0)
753 res
->aux
.clear_color_offset
+= aux_offset
;
754 if (!iris_resource_init_aux_buf(res
, flags
, clear_color_state_size
))
760 iris_resource_disable_aux(res
);
765 fprintf(stderr
, "XXX: resource creation failed\n");
766 iris_resource_destroy(pscreen
, &res
->base
);
771 static struct pipe_resource
*
772 iris_resource_create(struct pipe_screen
*pscreen
,
773 const struct pipe_resource
*templ
)
775 if (templ
->target
== PIPE_BUFFER
)
776 return iris_resource_create_for_buffer(pscreen
, templ
);
778 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
782 tiling_to_modifier(uint32_t tiling
)
784 static const uint64_t map
[] = {
785 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
786 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
787 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
790 assert(tiling
< ARRAY_SIZE(map
));
795 static struct pipe_resource
*
796 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
797 const struct pipe_resource
*templ
,
800 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
801 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
802 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
806 assert(templ
->target
== PIPE_BUFFER
);
808 res
->internal_format
= templ
->format
;
809 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
810 user_memory
, templ
->width0
,
817 util_range_add(&res
->valid_buffer_range
, 0, templ
->width0
);
822 static struct pipe_resource
*
823 iris_resource_from_handle(struct pipe_screen
*pscreen
,
824 const struct pipe_resource
*templ
,
825 struct winsys_handle
*whandle
,
828 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
829 struct gen_device_info
*devinfo
= &screen
->devinfo
;
830 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
831 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
835 switch (whandle
->type
) {
836 case WINSYS_HANDLE_TYPE_FD
:
837 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
);
839 case WINSYS_HANDLE_TYPE_SHARED
:
840 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
844 unreachable("invalid winsys handle type");
849 res
->offset
= whandle
->offset
;
851 uint64_t modifier
= whandle
->modifier
;
852 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
853 modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
855 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
856 assert(res
->mod_info
);
858 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
860 const struct iris_format_info fmt
=
861 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
862 res
->internal_format
= templ
->format
;
864 if (templ
->target
== PIPE_BUFFER
) {
865 res
->surf
.tiling
= ISL_TILING_LINEAR
;
867 UNUSED
const bool isl_surf_created_successfully
=
868 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
869 .dim
= target_to_isl_surf_dim(templ
->target
),
871 .width
= templ
->width0
,
872 .height
= templ
->height0
,
873 .depth
= templ
->depth0
,
874 .levels
= templ
->last_level
+ 1,
875 .array_len
= templ
->array_size
,
876 .samples
= MAX2(templ
->nr_samples
, 1),
877 .min_alignment_B
= 0,
878 .row_pitch_B
= whandle
->stride
,
880 .tiling_flags
= 1 << res
->mod_info
->tiling
);
881 assert(isl_surf_created_successfully
);
882 assert(res
->bo
->tiling_mode
==
883 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
885 // XXX: create_ccs_buf_for_image?
886 if (!iris_resource_alloc_separate_aux(screen
, res
))
893 iris_resource_destroy(pscreen
, &res
->base
);
898 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
900 struct iris_context
*ice
= (struct iris_context
*)ctx
;
901 struct iris_batch
*render_batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
902 struct iris_resource
*res
= (void *) resource
;
903 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
905 iris_resource_prepare_access(ice
, render_batch
, res
,
906 0, INTEL_REMAINING_LEVELS
,
907 0, INTEL_REMAINING_LAYERS
,
908 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
909 mod
? mod
->supports_clear_color
: false);
913 iris_resource_get_param(struct pipe_screen
*screen
,
914 struct pipe_resource
*resource
,
916 enum pipe_resource_param param
,
919 struct iris_resource
*res
= (struct iris_resource
*)resource
;
921 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
922 bool wants_aux
= mod_with_aux
&& plane
> 0;
923 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
928 case PIPE_RESOURCE_PARAM_NPLANES
:
929 *value
= mod_with_aux
? 2 : 1;
931 case PIPE_RESOURCE_PARAM_STRIDE
:
932 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
934 case PIPE_RESOURCE_PARAM_OFFSET
:
935 *value
= wants_aux
? res
->aux
.offset
: 0;
937 case PIPE_RESOURCE_PARAM_MODIFIER
:
938 *value
= res
->mod_info
? res
->mod_info
->modifier
:
939 tiling_to_modifier(res
->bo
->tiling_mode
);
941 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
942 result
= iris_bo_flink(bo
, &handle
) == 0;
946 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
947 *value
= iris_bo_export_gem_handle(bo
);
949 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
950 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
960 iris_resource_get_handle(struct pipe_screen
*pscreen
,
961 struct pipe_context
*ctx
,
962 struct pipe_resource
*resource
,
963 struct winsys_handle
*whandle
,
966 struct iris_resource
*res
= (struct iris_resource
*)resource
;
968 /* Disable aux usage if explicit flush not set and this is the
969 * first time we are dealing with this resource.
971 if ((!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0)) {
972 if (p_atomic_read(&resource
->reference
.count
) == 1)
973 iris_resource_disable_aux(res
);
976 /* If this is a buffer, stride should be 0 - no need to special case */
977 whandle
->stride
= res
->surf
.row_pitch_B
;
979 res
->mod_info
? res
->mod_info
->modifier
980 : tiling_to_modifier(res
->bo
->tiling_mode
);
983 enum isl_aux_usage allowed_usage
=
984 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
986 if (res
->aux
.usage
!= allowed_usage
) {
987 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
988 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
989 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
993 switch (whandle
->type
) {
994 case WINSYS_HANDLE_TYPE_SHARED
:
995 return iris_bo_flink(res
->bo
, &whandle
->handle
) == 0;
996 case WINSYS_HANDLE_TYPE_KMS
:
997 whandle
->handle
= iris_bo_export_gem_handle(res
->bo
);
999 case WINSYS_HANDLE_TYPE_FD
:
1000 return iris_bo_export_dmabuf(res
->bo
, (int *) &whandle
->handle
) == 0;
1007 resource_is_busy(struct iris_context
*ice
,
1008 struct iris_resource
*res
)
1010 bool busy
= iris_bo_busy(res
->bo
);
1012 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1013 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1019 iris_invalidate_resource(struct pipe_context
*ctx
,
1020 struct pipe_resource
*resource
)
1022 struct iris_screen
*screen
= (void *) ctx
->screen
;
1023 struct iris_context
*ice
= (void *) ctx
;
1024 struct iris_resource
*res
= (void *) resource
;
1026 if (resource
->target
!= PIPE_BUFFER
)
1029 if (!resource_is_busy(ice
, res
)) {
1030 /* The resource is idle, so just mark that it contains no data and
1031 * keep using the same underlying buffer object.
1033 util_range_set_empty(&res
->valid_buffer_range
);
1037 /* Otherwise, try and replace the backing storage with a new BO. */
1039 /* We can't reallocate memory we didn't allocate in the first place. */
1040 if (res
->bo
->userptr
)
1043 // XXX: We should support this.
1044 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1047 struct iris_bo
*old_bo
= res
->bo
;
1048 struct iris_bo
*new_bo
=
1049 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1050 iris_memzone_for_address(old_bo
->gtt_offset
));
1054 /* Swap out the backing storage */
1057 /* Rebind the buffer, replacing any state referring to the old BO's
1058 * address, and marking state dirty so it's reemitted.
1060 ice
->vtbl
.rebind_buffer(ice
, res
, old_bo
->gtt_offset
);
1062 util_range_set_empty(&res
->valid_buffer_range
);
1064 iris_bo_unreference(old_bo
);
1068 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1069 const struct pipe_box
*flush_box
)
1071 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1074 struct iris_transfer
*map
= (void *) xfer
;
1076 struct pipe_box src_box
= *flush_box
;
1078 /* Account for extra alignment padding in staging buffer */
1079 if (xfer
->resource
->target
== PIPE_BUFFER
)
1080 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1082 struct pipe_box dst_box
= (struct pipe_box
) {
1083 .x
= xfer
->box
.x
+ flush_box
->x
,
1084 .y
= xfer
->box
.y
+ flush_box
->y
,
1085 .z
= xfer
->box
.z
+ flush_box
->z
,
1086 .width
= flush_box
->width
,
1087 .height
= flush_box
->height
,
1088 .depth
= flush_box
->depth
,
1091 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1092 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1097 iris_unmap_copy_region(struct iris_transfer
*map
)
1099 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1105 iris_map_copy_region(struct iris_transfer
*map
)
1107 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1108 struct pipe_transfer
*xfer
= &map
->base
;
1109 struct pipe_box
*box
= &xfer
->box
;
1110 struct iris_resource
*res
= (void *) xfer
->resource
;
1112 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1113 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1115 struct pipe_resource templ
= (struct pipe_resource
) {
1116 .usage
= PIPE_USAGE_STAGING
,
1117 .width0
= box
->width
+ extra
,
1118 .height0
= box
->height
,
1120 .nr_samples
= xfer
->resource
->nr_samples
,
1121 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1122 .array_size
= box
->depth
,
1125 if (xfer
->resource
->target
== PIPE_BUFFER
)
1126 templ
.target
= PIPE_BUFFER
;
1127 else if (templ
.array_size
> 1)
1128 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1130 templ
.target
= PIPE_TEXTURE_2D
;
1132 /* Depth, stencil, and ASTC can't be linear surfaces, so we can't use
1133 * xfer->resource->format directly. Pick a bpb compatible format so
1134 * resource creation will succeed; blorp_copy will override it anyway.
1136 switch (util_format_get_blocksizebits(res
->internal_format
)) {
1137 case 8: templ
.format
= PIPE_FORMAT_R8_UINT
; break;
1138 case 16: templ
.format
= PIPE_FORMAT_R8G8_UINT
; break;
1139 case 24: templ
.format
= PIPE_FORMAT_R8G8B8_UINT
; break;
1140 case 32: templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
; break;
1141 case 48: templ
.format
= PIPE_FORMAT_R16G16B16_UINT
; break;
1142 case 64: templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
; break;
1143 case 96: templ
.format
= PIPE_FORMAT_R32G32B32_UINT
; break;
1144 case 128: templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
; break;
1145 default: unreachable("Invalid bpb");
1148 map
->staging
= iris_resource_create(pscreen
, &templ
);
1149 assert(map
->staging
);
1151 if (templ
.target
!= PIPE_BUFFER
) {
1152 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1153 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1154 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1157 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1158 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1159 xfer
->resource
, xfer
->level
, box
);
1160 /* Ensure writes to the staging BO land before we map it below. */
1161 iris_emit_pipe_control_flush(map
->batch
,
1162 "transfer read: flush before mapping",
1163 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1164 PIPE_CONTROL_CS_STALL
);
1167 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1169 if (iris_batch_references(map
->batch
, staging_bo
))
1170 iris_batch_flush(map
->batch
);
1173 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1175 map
->unmap
= iris_unmap_copy_region
;
1179 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1180 unsigned *out_x0_el
, unsigned *out_y0_el
)
1182 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1183 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1185 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1190 * Get pointer offset into stencil buffer.
1192 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1193 * must decode the tile's layout in software.
1196 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1198 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1200 * Even though the returned offset is always positive, the return type is
1202 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1203 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1206 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1208 uint32_t tile_size
= 4096;
1209 uint32_t tile_width
= 64;
1210 uint32_t tile_height
= 64;
1211 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1213 uint32_t tile_x
= x
/ tile_width
;
1214 uint32_t tile_y
= y
/ tile_height
;
1216 /* The byte's address relative to the tile's base addres. */
1217 uint32_t byte_x
= x
% tile_width
;
1218 uint32_t byte_y
= y
% tile_height
;
1220 uintptr_t u
= tile_y
* row_size
1221 + tile_x
* tile_size
1222 + 512 * (byte_x
/ 8)
1224 + 32 * ((byte_y
/ 4) % 2)
1225 + 16 * ((byte_x
/ 4) % 2)
1226 + 8 * ((byte_y
/ 2) % 2)
1227 + 4 * ((byte_x
/ 2) % 2)
1232 /* adjust for bit6 swizzling */
1233 if (((byte_x
/ 8) % 2) == 1) {
1234 if (((byte_y
/ 8) % 2) == 0) {
1246 iris_unmap_s8(struct iris_transfer
*map
)
1248 struct pipe_transfer
*xfer
= &map
->base
;
1249 const struct pipe_box
*box
= &xfer
->box
;
1250 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1251 struct isl_surf
*surf
= &res
->surf
;
1252 const bool has_swizzling
= false;
1254 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1255 uint8_t *untiled_s8_map
= map
->ptr
;
1256 uint8_t *tiled_s8_map
=
1257 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1259 for (int s
= 0; s
< box
->depth
; s
++) {
1260 unsigned x0_el
, y0_el
;
1261 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1263 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1264 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1265 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1269 tiled_s8_map
[offset
] =
1270 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1280 iris_map_s8(struct iris_transfer
*map
)
1282 struct pipe_transfer
*xfer
= &map
->base
;
1283 const struct pipe_box
*box
= &xfer
->box
;
1284 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1285 struct isl_surf
*surf
= &res
->surf
;
1287 xfer
->stride
= surf
->row_pitch_B
;
1288 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1290 /* The tiling and detiling functions require that the linear buffer has
1291 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1292 * over-allocate the linear buffer to get the proper alignment.
1294 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1295 assert(map
->buffer
);
1297 const bool has_swizzling
= false;
1299 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1300 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1301 * invalidate is set, since we'll be writing the whole rectangle from our
1302 * temporary buffer back out.
1304 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1305 uint8_t *untiled_s8_map
= map
->ptr
;
1306 uint8_t *tiled_s8_map
=
1307 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1309 for (int s
= 0; s
< box
->depth
; s
++) {
1310 unsigned x0_el
, y0_el
;
1311 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1313 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1314 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1315 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1319 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1320 tiled_s8_map
[offset
];
1326 map
->unmap
= iris_unmap_s8
;
1329 /* Compute extent parameters for use with tiled_memcpy functions.
1330 * xs are in units of bytes and ys are in units of strides.
1333 tile_extents(const struct isl_surf
*surf
,
1334 const struct pipe_box
*box
,
1335 unsigned level
, int z
,
1336 unsigned *x1_B
, unsigned *x2_B
,
1337 unsigned *y1_el
, unsigned *y2_el
)
1339 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1340 const unsigned cpp
= fmtl
->bpb
/ 8;
1342 assert(box
->x
% fmtl
->bw
== 0);
1343 assert(box
->y
% fmtl
->bh
== 0);
1345 unsigned x0_el
, y0_el
;
1346 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1348 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1349 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1350 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1351 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1355 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1357 struct pipe_transfer
*xfer
= &map
->base
;
1358 const struct pipe_box
*box
= &xfer
->box
;
1359 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1360 struct isl_surf
*surf
= &res
->surf
;
1362 const bool has_swizzling
= false;
1364 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1366 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1368 for (int s
= 0; s
< box
->depth
; s
++) {
1369 unsigned x1
, x2
, y1
, y2
;
1370 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1372 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1374 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1375 surf
->row_pitch_B
, xfer
->stride
,
1376 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1379 os_free_aligned(map
->buffer
);
1380 map
->buffer
= map
->ptr
= NULL
;
1384 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1386 struct pipe_transfer
*xfer
= &map
->base
;
1387 const struct pipe_box
*box
= &xfer
->box
;
1388 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1389 struct isl_surf
*surf
= &res
->surf
;
1391 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1392 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1394 unsigned x1
, x2
, y1
, y2
;
1395 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1397 /* The tiling and detiling functions require that the linear buffer has
1398 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1399 * over-allocate the linear buffer to get the proper alignment.
1402 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1403 assert(map
->buffer
);
1404 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1406 const bool has_swizzling
= false;
1408 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1410 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1412 for (int s
= 0; s
< box
->depth
; s
++) {
1413 unsigned x1
, x2
, y1
, y2
;
1414 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1416 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1417 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1419 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1420 surf
->row_pitch_B
, has_swizzling
,
1421 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1425 map
->unmap
= iris_unmap_tiled_memcpy
;
1429 iris_map_direct(struct iris_transfer
*map
)
1431 struct pipe_transfer
*xfer
= &map
->base
;
1432 struct pipe_box
*box
= &xfer
->box
;
1433 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1435 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1437 if (res
->base
.target
== PIPE_BUFFER
) {
1439 xfer
->layer_stride
= 0;
1441 map
->ptr
= ptr
+ box
->x
;
1443 struct isl_surf
*surf
= &res
->surf
;
1444 const struct isl_format_layout
*fmtl
=
1445 isl_format_get_layout(surf
->format
);
1446 const unsigned cpp
= fmtl
->bpb
/ 8;
1447 unsigned x0_el
, y0_el
;
1449 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1451 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1452 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1454 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1459 can_promote_to_async(const struct iris_resource
*res
,
1460 const struct pipe_box
*box
,
1461 enum pipe_transfer_usage usage
)
1463 /* If we're writing to a section of the buffer that hasn't even been
1464 * initialized with useful data, then we can safely promote this write
1465 * to be unsynchronized. This helps the common pattern of appending data.
1467 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1468 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1469 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1470 box
->x
+ box
->width
);
1474 iris_transfer_map(struct pipe_context
*ctx
,
1475 struct pipe_resource
*resource
,
1477 enum pipe_transfer_usage usage
,
1478 const struct pipe_box
*box
,
1479 struct pipe_transfer
**ptransfer
)
1481 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1482 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1483 struct isl_surf
*surf
= &res
->surf
;
1485 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1486 /* Replace the backing storage with a fresh buffer for non-async maps */
1487 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1488 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1489 iris_invalidate_resource(ctx
, resource
);
1491 /* If we can discard the whole resource, we can discard the range. */
1492 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1495 bool map_would_stall
= false;
1497 if (resource
->target
!= PIPE_BUFFER
) {
1498 iris_resource_access_raw(ice
, &ice
->batches
[IRIS_BATCH_RENDER
], res
,
1499 level
, box
->z
, box
->depth
,
1500 usage
& PIPE_TRANSFER_WRITE
);
1503 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1504 can_promote_to_async(res
, box
, usage
)) {
1505 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1508 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1509 map_would_stall
= resource_is_busy(ice
, res
);
1511 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1512 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1516 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1517 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1520 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1521 struct pipe_transfer
*xfer
= &map
->base
;
1526 memset(map
, 0, sizeof(*map
));
1527 map
->dbg
= &ice
->dbg
;
1529 pipe_resource_reference(&xfer
->resource
, resource
);
1530 xfer
->level
= level
;
1531 xfer
->usage
= usage
;
1535 if (usage
& PIPE_TRANSFER_WRITE
)
1536 util_range_add(&res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1538 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1539 * there is to access them simultaneously on the CPU & GPU. This also
1540 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1541 * contain state we're constructing for a GPU draw call, which would
1542 * kill us with infinite stack recursion.
1544 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1545 PIPE_TRANSFER_COHERENT
|
1546 PIPE_TRANSFER_MAP_DIRECTLY
);
1548 /* GPU copies are not useful for buffer reads. Instead of stalling to
1549 * read from the original buffer, we'd simply copy it to a temporary...
1550 * then stall (a bit longer) to read from that buffer.
1552 * Images are less clear-cut. Color resolves are destructive, removing
1553 * the underlying compression, so we'd rather blit the data to a linear
1554 * temporary and map that, to avoid the resolve. (It might be better to
1555 * a tiled temporary and use the tiled_memcpy paths...)
1557 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) &&
1558 res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
&&
1559 res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
) {
1563 if ((map_would_stall
|| res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) && !no_gpu
) {
1564 /* If we need a synchronous mapping and the resource is busy,
1565 * we copy to/from a linear temporary buffer using the GPU.
1567 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1568 map
->blorp
= &ice
->blorp
;
1569 iris_map_copy_region(map
);
1571 /* Otherwise we're free to map on the CPU. Flush if needed. */
1572 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1573 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1574 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1575 iris_batch_flush(&ice
->batches
[i
]);
1579 if (surf
->tiling
== ISL_TILING_W
) {
1580 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1582 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1583 iris_map_tiled_memcpy(map
);
1585 iris_map_direct(map
);
1593 iris_transfer_flush_region(struct pipe_context
*ctx
,
1594 struct pipe_transfer
*xfer
,
1595 const struct pipe_box
*box
)
1597 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1598 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1599 struct iris_transfer
*map
= (void *) xfer
;
1602 iris_flush_staging_region(xfer
, box
);
1604 uint32_t history_flush
= 0;
1606 if (res
->base
.target
== PIPE_BUFFER
) {
1607 history_flush
|= iris_flush_bits_for_history(res
) |
1608 (map
->staging
? PIPE_CONTROL_RENDER_TARGET_FLUSH
: 0);
1611 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
1612 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1613 struct iris_batch
*batch
= &ice
->batches
[i
];
1614 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
1615 iris_batch_maybe_flush(batch
, 24);
1616 iris_emit_pipe_control_flush(batch
,
1617 "cache history: transfer flush",
1623 /* Make sure we flag constants dirty even if there's no need to emit
1624 * any PIPE_CONTROLs to a batch.
1626 iris_dirty_for_history(ice
, res
);
1630 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1632 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1633 struct iris_transfer
*map
= (void *) xfer
;
1635 if (!(xfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
)) {
1636 struct pipe_box flush_box
= {
1637 .x
= 0, .y
= 0, .z
= 0,
1638 .width
= xfer
->box
.width
,
1639 .height
= xfer
->box
.height
,
1640 .depth
= xfer
->box
.depth
,
1642 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
1648 pipe_resource_reference(&xfer
->resource
, NULL
);
1649 slab_free(&ice
->transfer_pool
, map
);
1653 * Mark state dirty that needs to be re-emitted when a resource is written.
1656 iris_dirty_for_history(struct iris_context
*ice
,
1657 struct iris_resource
*res
)
1659 uint64_t dirty
= 0ull;
1661 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1662 dirty
|= IRIS_DIRTY_CONSTANTS_VS
|
1663 IRIS_DIRTY_CONSTANTS_TCS
|
1664 IRIS_DIRTY_CONSTANTS_TES
|
1665 IRIS_DIRTY_CONSTANTS_GS
|
1666 IRIS_DIRTY_CONSTANTS_FS
|
1667 IRIS_DIRTY_CONSTANTS_CS
|
1668 IRIS_ALL_DIRTY_BINDINGS
;
1671 ice
->state
.dirty
|= dirty
;
1675 * Produce a set of PIPE_CONTROL bits which ensure data written to a
1676 * resource becomes visible, and any stale read cache data is invalidated.
1679 iris_flush_bits_for_history(struct iris_resource
*res
)
1681 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
1683 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1684 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
1685 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1688 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
1689 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1691 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
1692 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1694 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
1695 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
1701 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
1702 struct iris_batch
*batch
,
1703 struct iris_resource
*res
,
1704 uint32_t extra_flags
,
1707 if (res
->base
.target
!= PIPE_BUFFER
)
1710 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
1712 iris_emit_pipe_control_flush(batch
, reason
, flush
);
1714 iris_dirty_for_history(ice
, res
);
1718 iris_resource_set_clear_color(struct iris_context
*ice
,
1719 struct iris_resource
*res
,
1720 union isl_color_value color
)
1722 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
1723 res
->aux
.clear_color
= color
;
1730 union isl_color_value
1731 iris_resource_get_clear_color(const struct iris_resource
*res
,
1732 struct iris_bo
**clear_color_bo
,
1733 uint64_t *clear_color_offset
)
1735 assert(res
->aux
.bo
);
1738 *clear_color_bo
= res
->aux
.clear_color_bo
;
1739 if (clear_color_offset
)
1740 *clear_color_offset
= res
->aux
.clear_color_offset
;
1741 return res
->aux
.clear_color
;
1744 static enum pipe_format
1745 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
1747 struct iris_resource
*res
= (void *) p_res
;
1748 return res
->internal_format
;
1751 static const struct u_transfer_vtbl transfer_vtbl
= {
1752 .resource_create
= iris_resource_create
,
1753 .resource_destroy
= iris_resource_destroy
,
1754 .transfer_map
= iris_transfer_map
,
1755 .transfer_unmap
= iris_transfer_unmap
,
1756 .transfer_flush_region
= iris_transfer_flush_region
,
1757 .get_internal_format
= iris_resource_get_internal_format
,
1758 .set_stencil
= iris_resource_set_separate_stencil
,
1759 .get_stencil
= iris_resource_get_separate_stencil
,
1763 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
1765 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
1766 pscreen
->resource_create_with_modifiers
=
1767 iris_resource_create_with_modifiers
;
1768 pscreen
->resource_create
= u_transfer_helper_resource_create
;
1769 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
1770 pscreen
->resource_from_handle
= iris_resource_from_handle
;
1771 pscreen
->resource_get_handle
= iris_resource_get_handle
;
1772 pscreen
->resource_get_param
= iris_resource_get_param
;
1773 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
1774 pscreen
->transfer_helper
=
1775 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
1779 iris_init_resource_functions(struct pipe_context
*ctx
)
1781 ctx
->flush_resource
= iris_flush_resource
;
1782 ctx
->invalidate_resource
= iris_invalidate_resource
;
1783 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
1784 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
1785 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
1786 ctx
->buffer_subdata
= u_default_buffer_subdata
;
1787 ctx
->texture_subdata
= u_default_texture_subdata
;