2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/dev/gen_debug.h"
52 #include "drm-uapi/drm_fourcc.h"
53 #include "drm-uapi/i915_drm.h"
55 enum modifier_priority
{
56 MODIFIER_PRIORITY_INVALID
= 0,
57 MODIFIER_PRIORITY_LINEAR
,
60 MODIFIER_PRIORITY_Y_CCS
,
63 static const uint64_t priority_to_modifier
[] = {
64 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
65 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
66 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
67 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
68 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
72 modifier_is_supported(const struct gen_device_info
*devinfo
,
75 /* XXX: do something real */
77 case I915_FORMAT_MOD_Y_TILED
:
78 case I915_FORMAT_MOD_X_TILED
:
79 case DRM_FORMAT_MOD_LINEAR
:
81 case I915_FORMAT_MOD_Y_TILED_CCS
:
82 case DRM_FORMAT_MOD_INVALID
:
89 select_best_modifier(struct gen_device_info
*devinfo
,
90 const uint64_t *modifiers
,
93 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
95 for (int i
= 0; i
< count
; i
++) {
96 if (!modifier_is_supported(devinfo
, modifiers
[i
]))
99 switch (modifiers
[i
]) {
100 case I915_FORMAT_MOD_Y_TILED_CCS
:
101 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
103 case I915_FORMAT_MOD_Y_TILED
:
104 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
106 case I915_FORMAT_MOD_X_TILED
:
107 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
109 case DRM_FORMAT_MOD_LINEAR
:
110 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
112 case DRM_FORMAT_MOD_INVALID
:
118 return priority_to_modifier
[prio
];
121 static enum isl_surf_dim
122 target_to_isl_surf_dim(enum pipe_texture_target target
)
126 case PIPE_TEXTURE_1D
:
127 case PIPE_TEXTURE_1D_ARRAY
:
128 return ISL_SURF_DIM_1D
;
129 case PIPE_TEXTURE_2D
:
130 case PIPE_TEXTURE_CUBE
:
131 case PIPE_TEXTURE_RECT
:
132 case PIPE_TEXTURE_2D_ARRAY
:
133 case PIPE_TEXTURE_CUBE_ARRAY
:
134 return ISL_SURF_DIM_2D
;
135 case PIPE_TEXTURE_3D
:
136 return ISL_SURF_DIM_3D
;
137 case PIPE_MAX_TEXTURE_TYPES
:
140 unreachable("invalid texture type");
144 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
145 enum pipe_format pfmt
,
148 unsigned int *external_only
,
151 struct iris_screen
*screen
= (void *) pscreen
;
152 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
154 uint64_t all_modifiers
[] = {
155 DRM_FORMAT_MOD_LINEAR
,
156 I915_FORMAT_MOD_X_TILED
,
157 I915_FORMAT_MOD_Y_TILED
,
158 // XXX: (broken) I915_FORMAT_MOD_Y_TILED_CCS,
161 int supported_mods
= 0;
163 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
164 if (!modifier_is_supported(devinfo
, all_modifiers
[i
]))
167 if (supported_mods
< max
) {
169 modifiers
[supported_mods
] = all_modifiers
[i
];
172 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
178 *count
= supported_mods
;
181 static isl_surf_usage_flags_t
182 pipe_bind_to_isl_usage(unsigned bindings
)
184 isl_surf_usage_flags_t usage
= 0;
186 if (bindings
& PIPE_BIND_RENDER_TARGET
)
187 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
189 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
190 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
192 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
193 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
195 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
196 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
201 struct pipe_resource
*
202 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
204 /* For packed depth-stencil, we treat depth as the primary resource
205 * and store S8 as the "second plane" resource.
211 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
212 struct pipe_resource
*stencil
)
214 assert(util_format_has_depth(util_format_description(p_res
->format
)));
215 pipe_resource_reference(&p_res
->next
, stencil
);
219 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
220 struct iris_resource
**out_z
,
221 struct iris_resource
**out_s
)
229 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
230 *out_z
= (void *) res
;
231 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
234 *out_s
= (void *) res
;
239 iris_resource_disable_aux(struct iris_resource
*res
)
241 iris_bo_unreference(res
->aux
.bo
);
242 iris_bo_unreference(res
->aux
.clear_color_bo
);
243 free(res
->aux
.state
);
245 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
246 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
247 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
248 res
->aux
.surf
.size_B
= 0;
250 res
->aux
.clear_color_bo
= NULL
;
251 res
->aux
.state
= NULL
;
255 iris_resource_destroy(struct pipe_screen
*screen
,
256 struct pipe_resource
*resource
)
258 struct iris_resource
*res
= (struct iris_resource
*)resource
;
260 iris_resource_disable_aux(res
);
262 iris_bo_unreference(res
->bo
);
266 static struct iris_resource
*
267 iris_alloc_resource(struct pipe_screen
*pscreen
,
268 const struct pipe_resource
*templ
)
270 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
275 res
->base
.screen
= pscreen
;
276 pipe_reference_init(&res
->base
.reference
, 1);
278 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
279 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
285 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
287 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
288 return minify(res
->surf
.logical_level0_px
.depth
, level
);
290 return res
->surf
.logical_level0_px
.array_len
;
293 static enum isl_aux_state
**
294 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
296 uint32_t total_slices
= 0;
297 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
298 total_slices
+= iris_get_num_logical_layers(res
, level
);
300 const size_t per_level_array_size
=
301 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
303 /* We're going to allocate a single chunk of data for both the per-level
304 * reference array and the arrays of aux_state. This makes cleanup
305 * significantly easier.
307 const size_t total_size
=
308 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
310 void *data
= malloc(total_size
);
314 enum isl_aux_state
**per_level_arr
= data
;
315 enum isl_aux_state
*s
= data
+ per_level_array_size
;
316 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
317 per_level_arr
[level
] = s
;
318 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
319 for (uint32_t a
= 0; a
< level_layers
; a
++)
322 assert((void *)s
== data
+ total_size
);
324 return per_level_arr
;
328 * Allocate the initial aux surface for a resource based on aux.usage
331 iris_resource_alloc_aux(struct iris_screen
*screen
, struct iris_resource
*res
)
333 struct isl_device
*isl_dev
= &screen
->isl_dev
;
334 enum isl_aux_state initial_state
;
335 UNUSED
bool ok
= false;
336 uint8_t memset_value
= 0;
337 uint32_t alloc_flags
= 0;
338 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
339 const unsigned clear_color_state_size
= devinfo
->gen
>= 10 ?
340 screen
->isl_dev
.ss
.clear_color_state_size
:
341 (devinfo
->gen
>= 9 ? screen
->isl_dev
.ss
.clear_value_size
: 0);
343 assert(!res
->aux
.bo
);
345 switch (res
->aux
.usage
) {
346 case ISL_AUX_USAGE_NONE
:
347 res
->aux
.surf
.size_B
= 0;
349 case ISL_AUX_USAGE_HIZ
:
350 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
352 ok
= isl_surf_get_hiz_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
354 case ISL_AUX_USAGE_MCS
:
355 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
357 * "When MCS buffer is enabled and bound to MSRT, it is required
358 * that it is cleared prior to any rendering."
360 * Since we only use the MCS buffer for rendering, we just clear it
361 * immediately on allocation. The clear value for MCS buffers is all
362 * 1's, so we simply memset it to 0xff.
364 initial_state
= ISL_AUX_STATE_CLEAR
;
366 ok
= isl_surf_get_mcs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
368 case ISL_AUX_USAGE_CCS_D
:
369 case ISL_AUX_USAGE_CCS_E
:
370 /* When CCS_E is used, we need to ensure that the CCS starts off in
371 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
374 * "If Software wants to enable Color Compression without Fast
375 * clear, Software needs to initialize MCS with zeros."
377 * A CCS value of 0 indicates that the corresponding block is in the
378 * pass-through state which is what we want.
380 * For CCS_D, do the same thing. On Gen9+, this avoids having any
381 * undefined bits in the aux buffer.
383 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
384 alloc_flags
|= BO_ALLOC_ZEROED
;
385 ok
= isl_surf_get_ccs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
, 0);
389 /* No work is needed for a zero-sized auxiliary buffer. */
390 if (res
->aux
.surf
.size_B
== 0)
393 /* Assert that ISL gave us a valid aux surf */
396 /* Create the aux_state for the auxiliary buffer. */
397 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
401 uint64_t size
= res
->aux
.surf
.size_B
;
403 /* Allocate space in the buffer for storing the clear color. On modern
404 * platforms (gen > 9), we can read it directly from such buffer.
406 * On gen <= 9, we are going to store the clear color on the buffer
407 * anyways, and copy it back to the surface state during state emission.
409 res
->aux
.clear_color_offset
= size
;
410 size
+= clear_color_state_size
;
412 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
413 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
414 * of bytes instead of trying to recalculate based on different format
417 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
,
418 IRIS_MEMZONE_OTHER
, I915_TILING_Y
,
419 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
424 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
425 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
428 iris_resource_disable_aux(res
);
432 if (memset_value
!= 0)
433 memset(map
, memset_value
, res
->aux
.surf
.size_B
);
435 /* Zero the indirect clear color to match ::fast_clear_color. */
436 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
437 clear_color_state_size
);
439 iris_bo_unmap(res
->aux
.bo
);
442 if (clear_color_state_size
> 0) {
443 res
->aux
.clear_color_bo
= res
->aux
.bo
;
444 iris_bo_reference(res
->aux
.clear_color_bo
);
447 if (res
->aux
.usage
== ISL_AUX_USAGE_HIZ
) {
448 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
449 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
450 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
452 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
453 * For LOD == 0, we can grow the dimensions to make it work.
455 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
456 res
->aux
.has_hiz
|= 1 << level
;
464 supports_mcs(const struct isl_surf
*surf
)
466 /* MCS compression only applies to multisampled resources. */
467 if (surf
->samples
<= 1)
470 /* See isl_surf_get_mcs_surf for details. */
471 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
474 /* Depth and stencil buffers use the IMS (interleaved) layout. */
475 if (isl_surf_usage_is_depth_or_stencil(surf
->usage
))
482 supports_ccs(const struct gen_device_info
*devinfo
,
483 const struct isl_surf
*surf
)
485 /* Gen9+ only supports CCS for Y-tiled buffers. */
486 if (surf
->tiling
!= ISL_TILING_Y0
)
489 /* CCS only supports singlesampled resources. */
490 if (surf
->samples
> 1)
493 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
494 * work for 3D textures until Gen9 where the layout of 3D textures changes
495 * to match 2D array textures.
497 if (devinfo
->gen
< 9 && surf
->dim
!= ISL_SURF_DIM_2D
)
500 /* Note: still need to check the format! */
505 static struct pipe_resource
*
506 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
507 const struct pipe_resource
*templ
)
509 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
510 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
512 assert(templ
->target
== PIPE_BUFFER
);
513 assert(templ
->height0
<= 1);
514 assert(templ
->depth0
<= 1);
515 assert(templ
->format
== PIPE_FORMAT_NONE
||
516 util_format_get_blocksize(templ
->format
) == 1);
518 res
->internal_format
= templ
->format
;
519 res
->surf
.tiling
= ISL_TILING_LINEAR
;
521 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
522 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
523 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
524 memzone
= IRIS_MEMZONE_SHADER
;
525 name
= "shader kernels";
526 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
527 memzone
= IRIS_MEMZONE_SURFACE
;
528 name
= "surface state";
529 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
530 memzone
= IRIS_MEMZONE_DYNAMIC
;
531 name
= "dynamic state";
534 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
536 iris_resource_destroy(pscreen
, &res
->base
);
543 static struct pipe_resource
*
544 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
545 const struct pipe_resource
*templ
,
546 const uint64_t *modifiers
,
549 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
550 struct gen_device_info
*devinfo
= &screen
->devinfo
;
551 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
556 const struct util_format_description
*format_desc
=
557 util_format_description(templ
->format
);
558 const bool has_depth
= util_format_has_depth(format_desc
);
560 select_best_modifier(devinfo
, modifiers
, modifiers_count
);
562 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
564 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
565 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
567 tiling_flags
= 1 << res
->mod_info
->tiling
;
569 if (modifiers_count
> 0) {
570 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
574 /* No modifiers - we can select our own tiling. */
577 /* Depth must be Y-tiled */
578 tiling_flags
= ISL_TILING_Y0_BIT
;
579 } else if (templ
->format
== PIPE_FORMAT_S8_UINT
) {
580 /* Stencil must be W-tiled */
581 tiling_flags
= ISL_TILING_W_BIT
;
582 } else if (templ
->target
== PIPE_BUFFER
||
583 templ
->target
== PIPE_TEXTURE_1D
||
584 templ
->target
== PIPE_TEXTURE_1D_ARRAY
) {
585 /* Use linear for buffers and 1D textures */
586 tiling_flags
= ISL_TILING_LINEAR_BIT
;
589 /* Use linear for staging buffers */
590 if (templ
->usage
== PIPE_USAGE_STAGING
||
591 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
592 tiling_flags
= ISL_TILING_LINEAR_BIT
;
595 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
597 if (templ
->target
== PIPE_TEXTURE_CUBE
||
598 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
599 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
601 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
602 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
603 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
605 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
608 enum pipe_format pfmt
= templ
->format
;
609 res
->internal_format
= pfmt
;
611 /* Should be handled by u_transfer_helper */
612 assert(!util_format_is_depth_and_stencil(pfmt
));
614 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
615 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
617 UNUSED
const bool isl_surf_created_successfully
=
618 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
619 .dim
= target_to_isl_surf_dim(templ
->target
),
621 .width
= templ
->width0
,
622 .height
= templ
->height0
,
623 .depth
= templ
->depth0
,
624 .levels
= templ
->last_level
+ 1,
625 .array_len
= templ
->array_size
,
626 .samples
= MAX2(templ
->nr_samples
, 1),
627 .min_alignment_B
= 0,
630 .tiling_flags
= tiling_flags
);
631 assert(isl_surf_created_successfully
);
634 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
635 } else if (supports_mcs(&res
->surf
)) {
636 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_MCS
;
637 } else if (has_depth
) {
638 if (likely(!(INTEL_DEBUG
& DEBUG_NO_HIZ
)))
639 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
640 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO_RBC
)) &&
641 supports_ccs(devinfo
, &res
->surf
)) {
642 if (isl_format_supports_ccs_e(devinfo
, res
->surf
.format
))
643 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
645 if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
646 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
649 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
651 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
653 /* We don't always support sampling with hiz. But when we do, it must be
656 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1) {
657 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
660 const char *name
= "miptree";
661 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
663 unsigned int flags
= 0;
664 if (templ
->usage
== PIPE_USAGE_STAGING
)
665 flags
|= BO_ALLOC_COHERENT
;
667 /* These are for u_upload_mgr buffers only */
668 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
669 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
670 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
672 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, res
->surf
.size_B
,
674 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
675 res
->surf
.row_pitch_B
, flags
);
680 if (!iris_resource_alloc_aux(screen
, res
))
686 fprintf(stderr
, "XXX: resource creation failed\n");
687 iris_resource_destroy(pscreen
, &res
->base
);
692 static struct pipe_resource
*
693 iris_resource_create(struct pipe_screen
*pscreen
,
694 const struct pipe_resource
*templ
)
696 if (templ
->target
== PIPE_BUFFER
)
697 return iris_resource_create_for_buffer(pscreen
, templ
);
699 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
703 tiling_to_modifier(uint32_t tiling
)
705 static const uint64_t map
[] = {
706 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
707 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
708 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
711 assert(tiling
< ARRAY_SIZE(map
));
716 static struct pipe_resource
*
717 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
718 const struct pipe_resource
*templ
,
721 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
722 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
723 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
727 assert(templ
->target
== PIPE_BUFFER
);
729 res
->internal_format
= templ
->format
;
730 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
731 user_memory
, templ
->width0
,
741 static struct pipe_resource
*
742 iris_resource_from_handle(struct pipe_screen
*pscreen
,
743 const struct pipe_resource
*templ
,
744 struct winsys_handle
*whandle
,
747 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
748 struct gen_device_info
*devinfo
= &screen
->devinfo
;
749 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
750 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
754 if (whandle
->offset
!= 0) {
755 dbg_printf("Attempt to import unsupported winsys offset %u\n",
760 switch (whandle
->type
) {
761 case WINSYS_HANDLE_TYPE_FD
:
762 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
);
764 case WINSYS_HANDLE_TYPE_SHARED
:
765 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
769 unreachable("invalid winsys handle type");
774 uint64_t modifier
= whandle
->modifier
;
775 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
776 modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
778 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
779 assert(res
->mod_info
);
781 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
783 const struct iris_format_info fmt
=
784 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
785 res
->internal_format
= templ
->format
;
787 if (templ
->target
== PIPE_BUFFER
) {
788 res
->surf
.tiling
= ISL_TILING_LINEAR
;
790 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
791 .dim
= target_to_isl_surf_dim(templ
->target
),
793 .width
= templ
->width0
,
794 .height
= templ
->height0
,
795 .depth
= templ
->depth0
,
796 .levels
= templ
->last_level
+ 1,
797 .array_len
= templ
->array_size
,
798 .samples
= MAX2(templ
->nr_samples
, 1),
799 .min_alignment_B
= 0,
800 .row_pitch_B
= whandle
->stride
,
802 .tiling_flags
= 1 << res
->mod_info
->tiling
);
804 assert(res
->bo
->tiling_mode
==
805 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
807 // XXX: create_ccs_buf_for_image?
808 if (!iris_resource_alloc_aux(screen
, res
))
815 iris_resource_destroy(pscreen
, &res
->base
);
820 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
822 struct iris_context
*ice
= (struct iris_context
*)ctx
;
823 struct iris_batch
*render_batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
824 struct iris_resource
*res
= (void *) resource
;
825 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
827 iris_resource_prepare_access(ice
, render_batch
, res
,
828 0, INTEL_REMAINING_LEVELS
,
829 0, INTEL_REMAINING_LAYERS
,
830 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
831 mod
? mod
->supports_clear_color
: false);
835 iris_resource_get_handle(struct pipe_screen
*pscreen
,
836 struct pipe_context
*ctx
,
837 struct pipe_resource
*resource
,
838 struct winsys_handle
*whandle
,
841 struct iris_resource
*res
= (struct iris_resource
*)resource
;
843 /* Disable aux usage if explicit flush not set and this is the
844 * first time we are dealing with this resource.
846 if ((!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0)) {
847 if (p_atomic_read(&resource
->reference
.count
) == 1)
848 iris_resource_disable_aux(res
);
851 /* If this is a buffer, stride should be 0 - no need to special case */
852 whandle
->stride
= res
->surf
.row_pitch_B
;
854 res
->mod_info
? res
->mod_info
->modifier
855 : tiling_to_modifier(res
->bo
->tiling_mode
);
858 enum isl_aux_usage allowed_usage
=
859 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
861 if (res
->aux
.usage
!= allowed_usage
) {
862 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
863 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
864 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
868 switch (whandle
->type
) {
869 case WINSYS_HANDLE_TYPE_SHARED
:
870 return iris_bo_flink(res
->bo
, &whandle
->handle
) == 0;
871 case WINSYS_HANDLE_TYPE_KMS
:
872 whandle
->handle
= iris_bo_export_gem_handle(res
->bo
);
874 case WINSYS_HANDLE_TYPE_FD
:
875 return iris_bo_export_dmabuf(res
->bo
, (int *) &whandle
->handle
) == 0;
882 iris_invalidate_resource(struct pipe_context
*ctx
,
883 struct pipe_resource
*resource
)
885 struct iris_screen
*screen
= (void *) ctx
->screen
;
886 struct iris_context
*ice
= (void *) ctx
;
887 struct iris_resource
*res
= (void *) resource
;
889 if (resource
->target
!= PIPE_BUFFER
)
892 /* We can't reallocate memory we didn't allocate in the first place. */
893 if (res
->bo
->userptr
)
896 // XXX: We should support this.
897 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
900 struct iris_bo
*old_bo
= res
->bo
;
901 struct iris_bo
*new_bo
=
902 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
903 iris_memzone_for_address(old_bo
->gtt_offset
));
908 ice
->vtbl
.rebind_buffer(ice
, res
, old_bo
->gtt_offset
);
909 iris_bo_unreference(old_bo
);
913 iris_flush_staging_region(struct pipe_transfer
*xfer
,
914 const struct pipe_box
*flush_box
)
916 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
919 struct iris_transfer
*map
= (void *) xfer
;
921 struct pipe_box src_box
= *flush_box
;
923 /* Account for extra alignment padding in staging buffer */
924 if (xfer
->resource
->target
== PIPE_BUFFER
)
925 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
927 struct pipe_box dst_box
= (struct pipe_box
) {
928 .x
= xfer
->box
.x
+ flush_box
->x
,
929 .y
= xfer
->box
.y
+ flush_box
->y
,
930 .z
= xfer
->box
.z
+ flush_box
->z
,
931 .width
= flush_box
->width
,
932 .height
= flush_box
->height
,
933 .depth
= flush_box
->depth
,
936 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
937 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
942 iris_unmap_copy_region(struct iris_transfer
*map
)
944 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
950 iris_map_copy_region(struct iris_transfer
*map
)
952 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
953 struct pipe_transfer
*xfer
= &map
->base
;
954 struct pipe_box
*box
= &xfer
->box
;
955 struct iris_resource
*res
= (void *) xfer
->resource
;
957 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
958 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
960 struct pipe_resource templ
= (struct pipe_resource
) {
961 .usage
= PIPE_USAGE_STAGING
,
962 .width0
= box
->width
+ extra
,
963 .height0
= box
->height
,
965 .nr_samples
= xfer
->resource
->nr_samples
,
966 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
967 .array_size
= box
->depth
,
970 if (xfer
->resource
->target
== PIPE_BUFFER
)
971 templ
.target
= PIPE_BUFFER
;
972 else if (templ
.array_size
> 1)
973 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
975 templ
.target
= PIPE_TEXTURE_2D
;
977 /* Depth, stencil, and ASTC can't be linear surfaces, so we can't use
978 * xfer->resource->format directly. Pick a bpb compatible format so
979 * resource creation will succeed; blorp_copy will override it anyway.
981 switch (util_format_get_blocksizebits(res
->internal_format
)) {
982 case 8: templ
.format
= PIPE_FORMAT_R8_UINT
; break;
983 case 16: templ
.format
= PIPE_FORMAT_R8G8_UINT
; break;
984 case 24: templ
.format
= PIPE_FORMAT_R8G8B8_UINT
; break;
985 case 32: templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
; break;
986 case 48: templ
.format
= PIPE_FORMAT_R16G16B16_UINT
; break;
987 case 64: templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
; break;
988 case 96: templ
.format
= PIPE_FORMAT_R32G32B32_UINT
; break;
989 case 128: templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
; break;
990 default: unreachable("Invalid bpb");
993 map
->staging
= iris_resource_create(pscreen
, &templ
);
994 assert(map
->staging
);
996 if (templ
.target
!= PIPE_BUFFER
) {
997 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
998 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
999 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1002 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1003 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1004 xfer
->resource
, xfer
->level
, box
);
1005 /* Ensure writes to the staging BO land before we map it below. */
1006 iris_emit_pipe_control_flush(map
->batch
,
1007 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1008 PIPE_CONTROL_CS_STALL
);
1011 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1013 if (iris_batch_references(map
->batch
, staging_bo
))
1014 iris_batch_flush(map
->batch
);
1017 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1019 map
->unmap
= iris_unmap_copy_region
;
1023 get_image_offset_el(struct isl_surf
*surf
, unsigned level
, unsigned z
,
1024 unsigned *out_x0_el
, unsigned *out_y0_el
)
1026 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1027 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1029 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1034 * Get pointer offset into stencil buffer.
1036 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1037 * must decode the tile's layout in software.
1040 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1042 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1044 * Even though the returned offset is always positive, the return type is
1046 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1047 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1050 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1052 uint32_t tile_size
= 4096;
1053 uint32_t tile_width
= 64;
1054 uint32_t tile_height
= 64;
1055 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1057 uint32_t tile_x
= x
/ tile_width
;
1058 uint32_t tile_y
= y
/ tile_height
;
1060 /* The byte's address relative to the tile's base addres. */
1061 uint32_t byte_x
= x
% tile_width
;
1062 uint32_t byte_y
= y
% tile_height
;
1064 uintptr_t u
= tile_y
* row_size
1065 + tile_x
* tile_size
1066 + 512 * (byte_x
/ 8)
1068 + 32 * ((byte_y
/ 4) % 2)
1069 + 16 * ((byte_x
/ 4) % 2)
1070 + 8 * ((byte_y
/ 2) % 2)
1071 + 4 * ((byte_x
/ 2) % 2)
1076 /* adjust for bit6 swizzling */
1077 if (((byte_x
/ 8) % 2) == 1) {
1078 if (((byte_y
/ 8) % 2) == 0) {
1090 iris_unmap_s8(struct iris_transfer
*map
)
1092 struct pipe_transfer
*xfer
= &map
->base
;
1093 const struct pipe_box
*box
= &xfer
->box
;
1094 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1095 struct isl_surf
*surf
= &res
->surf
;
1096 const bool has_swizzling
= false;
1098 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1099 uint8_t *untiled_s8_map
= map
->ptr
;
1100 uint8_t *tiled_s8_map
=
1101 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1103 for (int s
= 0; s
< box
->depth
; s
++) {
1104 unsigned x0_el
, y0_el
;
1105 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1107 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1108 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1109 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1113 tiled_s8_map
[offset
] =
1114 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1124 iris_map_s8(struct iris_transfer
*map
)
1126 struct pipe_transfer
*xfer
= &map
->base
;
1127 const struct pipe_box
*box
= &xfer
->box
;
1128 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1129 struct isl_surf
*surf
= &res
->surf
;
1131 xfer
->stride
= surf
->row_pitch_B
;
1132 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1134 /* The tiling and detiling functions require that the linear buffer has
1135 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1136 * over-allocate the linear buffer to get the proper alignment.
1138 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1139 assert(map
->buffer
);
1141 const bool has_swizzling
= false;
1143 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1144 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1145 * invalidate is set, since we'll be writing the whole rectangle from our
1146 * temporary buffer back out.
1148 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1149 uint8_t *untiled_s8_map
= map
->ptr
;
1150 uint8_t *tiled_s8_map
=
1151 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1153 for (int s
= 0; s
< box
->depth
; s
++) {
1154 unsigned x0_el
, y0_el
;
1155 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1157 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1158 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1159 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1163 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1164 tiled_s8_map
[offset
];
1170 map
->unmap
= iris_unmap_s8
;
1173 /* Compute extent parameters for use with tiled_memcpy functions.
1174 * xs are in units of bytes and ys are in units of strides.
1177 tile_extents(struct isl_surf
*surf
,
1178 const struct pipe_box
*box
,
1179 unsigned level
, int z
,
1180 unsigned *x1_B
, unsigned *x2_B
,
1181 unsigned *y1_el
, unsigned *y2_el
)
1183 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1184 const unsigned cpp
= fmtl
->bpb
/ 8;
1186 assert(box
->x
% fmtl
->bw
== 0);
1187 assert(box
->y
% fmtl
->bh
== 0);
1189 unsigned x0_el
, y0_el
;
1190 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1192 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1193 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1194 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1195 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1199 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1201 struct pipe_transfer
*xfer
= &map
->base
;
1202 const struct pipe_box
*box
= &xfer
->box
;
1203 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1204 struct isl_surf
*surf
= &res
->surf
;
1206 const bool has_swizzling
= false;
1208 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1210 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1212 for (int s
= 0; s
< box
->depth
; s
++) {
1213 unsigned x1
, x2
, y1
, y2
;
1214 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1216 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1218 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1219 surf
->row_pitch_B
, xfer
->stride
,
1220 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1223 os_free_aligned(map
->buffer
);
1224 map
->buffer
= map
->ptr
= NULL
;
1228 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1230 struct pipe_transfer
*xfer
= &map
->base
;
1231 const struct pipe_box
*box
= &xfer
->box
;
1232 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1233 struct isl_surf
*surf
= &res
->surf
;
1235 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1236 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1238 unsigned x1
, x2
, y1
, y2
;
1239 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1241 /* The tiling and detiling functions require that the linear buffer has
1242 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1243 * over-allocate the linear buffer to get the proper alignment.
1246 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1247 assert(map
->buffer
);
1248 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1250 const bool has_swizzling
= false;
1252 // XXX: PIPE_TRANSFER_READ?
1253 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1255 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1257 for (int s
= 0; s
< box
->depth
; s
++) {
1258 unsigned x1
, x2
, y1
, y2
;
1259 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1261 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1262 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1264 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1265 surf
->row_pitch_B
, has_swizzling
,
1266 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1270 map
->unmap
= iris_unmap_tiled_memcpy
;
1274 iris_map_direct(struct iris_transfer
*map
)
1276 struct pipe_transfer
*xfer
= &map
->base
;
1277 struct pipe_box
*box
= &xfer
->box
;
1278 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1280 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1282 if (res
->base
.target
== PIPE_BUFFER
) {
1284 xfer
->layer_stride
= 0;
1286 map
->ptr
= ptr
+ box
->x
;
1288 struct isl_surf
*surf
= &res
->surf
;
1289 const struct isl_format_layout
*fmtl
=
1290 isl_format_get_layout(surf
->format
);
1291 const unsigned cpp
= fmtl
->bpb
/ 8;
1292 unsigned x0_el
, y0_el
;
1294 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1296 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1297 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1299 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1304 iris_transfer_map(struct pipe_context
*ctx
,
1305 struct pipe_resource
*resource
,
1307 enum pipe_transfer_usage usage
,
1308 const struct pipe_box
*box
,
1309 struct pipe_transfer
**ptransfer
)
1311 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1312 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1313 struct isl_surf
*surf
= &res
->surf
;
1315 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1316 /* Replace the backing storage with a fresh buffer for non-async maps */
1317 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1318 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1319 iris_invalidate_resource(ctx
, resource
);
1321 /* If we can discard the whole resource, we can discard the range. */
1322 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1325 bool map_would_stall
= false;
1327 if (resource
->target
!= PIPE_BUFFER
) {
1328 iris_resource_access_raw(ice
, &ice
->batches
[IRIS_BATCH_RENDER
], res
,
1329 level
, box
->z
, box
->depth
,
1330 usage
& PIPE_TRANSFER_WRITE
);
1333 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1334 map_would_stall
= iris_bo_busy(res
->bo
);
1336 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1337 map_would_stall
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1339 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1340 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1344 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1345 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1348 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1349 struct pipe_transfer
*xfer
= &map
->base
;
1354 memset(map
, 0, sizeof(*map
));
1355 map
->dbg
= &ice
->dbg
;
1357 pipe_resource_reference(&xfer
->resource
, resource
);
1358 xfer
->level
= level
;
1359 xfer
->usage
= usage
;
1363 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1364 * there is to access them simultaneously on the CPU & GPU. This also
1365 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1366 * contain state we're constructing for a GPU draw call, which would
1367 * kill us with infinite stack recursion.
1369 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1370 PIPE_TRANSFER_COHERENT
|
1371 PIPE_TRANSFER_MAP_DIRECTLY
);
1373 /* GPU copies are not useful for buffer reads. Instead of stalling to
1374 * read from the original buffer, we'd simply copy it to a temporary...
1375 * then stall (a bit longer) to read from that buffer.
1377 * Images are less clear-cut. Color resolves are destructive, removing
1378 * the underlying compression, so we'd rather blit the data to a linear
1379 * temporary and map that, to avoid the resolve. (It might be better to
1380 * a tiled temporary and use the tiled_memcpy paths...)
1382 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) &&
1383 res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
&&
1384 res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
) {
1388 if (map_would_stall
&& !no_gpu
) {
1389 /* If we need a synchronous mapping and the resource is busy,
1390 * we copy to/from a linear temporary buffer using the GPU.
1392 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1393 map
->blorp
= &ice
->blorp
;
1394 iris_map_copy_region(map
);
1396 /* Otherwise we're free to map on the CPU. Flush if needed. */
1397 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1398 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1399 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1400 iris_batch_flush(&ice
->batches
[i
]);
1404 if (surf
->tiling
== ISL_TILING_W
) {
1405 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1407 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1408 iris_map_tiled_memcpy(map
);
1410 iris_map_direct(map
);
1418 iris_transfer_flush_region(struct pipe_context
*ctx
,
1419 struct pipe_transfer
*xfer
,
1420 const struct pipe_box
*box
)
1422 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1423 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1424 struct iris_transfer
*map
= (void *) xfer
;
1427 iris_flush_staging_region(xfer
, box
);
1429 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1430 if (ice
->batches
[i
].contains_draw
||
1431 ice
->batches
[i
].cache
.render
->entries
) {
1432 iris_batch_maybe_flush(&ice
->batches
[i
], 24);
1433 iris_flush_and_dirty_for_history(ice
, &ice
->batches
[i
], res
);
1437 /* Make sure we flag constants dirty even if there's no need to emit
1438 * any PIPE_CONTROLs to a batch.
1440 iris_flush_and_dirty_for_history(ice
, NULL
, res
);
1444 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1446 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1447 struct iris_transfer
*map
= (void *) xfer
;
1449 if (!(xfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
)) {
1450 struct pipe_box flush_box
= {
1451 .x
= 0, .y
= 0, .z
= 0,
1452 .width
= xfer
->box
.width
,
1453 .height
= xfer
->box
.height
,
1454 .depth
= xfer
->box
.depth
,
1456 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
1462 pipe_resource_reference(&xfer
->resource
, NULL
);
1463 slab_free(&ice
->transfer_pool
, map
);
1467 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
1468 struct iris_batch
*batch
,
1469 struct iris_resource
*res
)
1471 if (res
->base
.target
!= PIPE_BUFFER
)
1474 unsigned flush
= PIPE_CONTROL_CS_STALL
;
1476 /* We've likely used the rendering engine (i.e. BLORP) to write to this
1477 * surface. Flush the render cache so the data actually lands.
1479 if (batch
&& batch
->name
!= IRIS_BATCH_COMPUTE
)
1480 flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
1482 uint64_t dirty
= 0ull;
1484 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1485 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
1486 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1487 dirty
|= IRIS_DIRTY_CONSTANTS_VS
|
1488 IRIS_DIRTY_CONSTANTS_TCS
|
1489 IRIS_DIRTY_CONSTANTS_TES
|
1490 IRIS_DIRTY_CONSTANTS_GS
|
1491 IRIS_DIRTY_CONSTANTS_FS
|
1492 IRIS_DIRTY_CONSTANTS_CS
|
1493 IRIS_ALL_DIRTY_BINDINGS
;
1496 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
1497 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1499 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
1500 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1502 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
1503 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
1506 iris_emit_pipe_control_flush(batch
, flush
);
1508 ice
->state
.dirty
|= dirty
;
1512 iris_resource_set_clear_color(struct iris_context
*ice
,
1513 struct iris_resource
*res
,
1514 union isl_color_value color
)
1516 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
1517 res
->aux
.clear_color
= color
;
1524 union isl_color_value
1525 iris_resource_get_clear_color(const struct iris_resource
*res
,
1526 struct iris_bo
**clear_color_bo
,
1527 uint64_t *clear_color_offset
)
1529 assert(res
->aux
.bo
);
1532 *clear_color_bo
= res
->aux
.clear_color_bo
;
1533 if (clear_color_offset
)
1534 *clear_color_offset
= res
->aux
.clear_color_offset
;
1535 return res
->aux
.clear_color
;
1538 static enum pipe_format
1539 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
1541 struct iris_resource
*res
= (void *) p_res
;
1542 return res
->internal_format
;
1545 static const struct u_transfer_vtbl transfer_vtbl
= {
1546 .resource_create
= iris_resource_create
,
1547 .resource_destroy
= iris_resource_destroy
,
1548 .transfer_map
= iris_transfer_map
,
1549 .transfer_unmap
= iris_transfer_unmap
,
1550 .transfer_flush_region
= iris_transfer_flush_region
,
1551 .get_internal_format
= iris_resource_get_internal_format
,
1552 .set_stencil
= iris_resource_set_separate_stencil
,
1553 .get_stencil
= iris_resource_get_separate_stencil
,
1557 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
1559 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
1560 pscreen
->resource_create_with_modifiers
=
1561 iris_resource_create_with_modifiers
;
1562 pscreen
->resource_create
= u_transfer_helper_resource_create
;
1563 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
1564 pscreen
->resource_from_handle
= iris_resource_from_handle
;
1565 pscreen
->resource_get_handle
= iris_resource_get_handle
;
1566 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
1567 pscreen
->transfer_helper
=
1568 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
1572 iris_init_resource_functions(struct pipe_context
*ctx
)
1574 ctx
->flush_resource
= iris_flush_resource
;
1575 ctx
->invalidate_resource
= iris_invalidate_resource
;
1576 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
1577 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
1578 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
1579 ctx
->buffer_subdata
= u_default_buffer_subdata
;
1580 ctx
->texture_subdata
= u_default_texture_subdata
;