2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/dev/gen_debug.h"
52 #include "drm-uapi/drm_fourcc.h"
53 #include "drm-uapi/i915_drm.h"
55 enum modifier_priority
{
56 MODIFIER_PRIORITY_INVALID
= 0,
57 MODIFIER_PRIORITY_LINEAR
,
60 MODIFIER_PRIORITY_Y_CCS
,
63 static const uint64_t priority_to_modifier
[] = {
64 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
65 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
66 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
67 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
68 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
72 modifier_is_supported(const struct gen_device_info
*devinfo
,
73 enum pipe_format pfmt
, uint64_t modifier
)
75 /* XXX: do something real */
77 case I915_FORMAT_MOD_Y_TILED_CCS
: {
78 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
81 enum isl_format rt_format
=
82 iris_format_for_usage(devinfo
, pfmt
,
83 ISL_SURF_USAGE_RENDER_TARGET_BIT
).fmt
;
85 enum isl_format linear_format
= isl_format_srgb_to_linear(rt_format
);
87 if (!isl_format_supports_ccs_e(devinfo
, linear_format
))
92 case I915_FORMAT_MOD_Y_TILED
:
93 case I915_FORMAT_MOD_X_TILED
:
94 case DRM_FORMAT_MOD_LINEAR
:
96 case DRM_FORMAT_MOD_INVALID
:
103 select_best_modifier(struct gen_device_info
*devinfo
, enum pipe_format pfmt
,
104 const uint64_t *modifiers
,
107 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
109 for (int i
= 0; i
< count
; i
++) {
110 if (!modifier_is_supported(devinfo
, pfmt
, modifiers
[i
]))
113 switch (modifiers
[i
]) {
114 case I915_FORMAT_MOD_Y_TILED_CCS
:
115 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
117 case I915_FORMAT_MOD_Y_TILED
:
118 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
120 case I915_FORMAT_MOD_X_TILED
:
121 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
123 case DRM_FORMAT_MOD_LINEAR
:
124 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
126 case DRM_FORMAT_MOD_INVALID
:
132 return priority_to_modifier
[prio
];
136 target_to_isl_surf_dim(enum pipe_texture_target target
)
140 case PIPE_TEXTURE_1D
:
141 case PIPE_TEXTURE_1D_ARRAY
:
142 return ISL_SURF_DIM_1D
;
143 case PIPE_TEXTURE_2D
:
144 case PIPE_TEXTURE_CUBE
:
145 case PIPE_TEXTURE_RECT
:
146 case PIPE_TEXTURE_2D_ARRAY
:
147 case PIPE_TEXTURE_CUBE_ARRAY
:
148 return ISL_SURF_DIM_2D
;
149 case PIPE_TEXTURE_3D
:
150 return ISL_SURF_DIM_3D
;
151 case PIPE_MAX_TEXTURE_TYPES
:
154 unreachable("invalid texture type");
158 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
159 enum pipe_format pfmt
,
162 unsigned int *external_only
,
165 struct iris_screen
*screen
= (void *) pscreen
;
166 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
168 uint64_t all_modifiers
[] = {
169 DRM_FORMAT_MOD_LINEAR
,
170 I915_FORMAT_MOD_X_TILED
,
171 I915_FORMAT_MOD_Y_TILED
,
172 I915_FORMAT_MOD_Y_TILED_CCS
,
175 int supported_mods
= 0;
177 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
178 if (!modifier_is_supported(devinfo
, pfmt
, all_modifiers
[i
]))
181 if (supported_mods
< max
) {
183 modifiers
[supported_mods
] = all_modifiers
[i
];
186 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
192 *count
= supported_mods
;
195 static isl_surf_usage_flags_t
196 pipe_bind_to_isl_usage(unsigned bindings
)
198 isl_surf_usage_flags_t usage
= 0;
200 if (bindings
& PIPE_BIND_RENDER_TARGET
)
201 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
203 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
204 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
206 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
207 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
209 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
210 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
215 struct pipe_resource
*
216 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
218 /* For packed depth-stencil, we treat depth as the primary resource
219 * and store S8 as the "second plane" resource.
221 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
229 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
230 struct pipe_resource
*stencil
)
232 assert(util_format_has_depth(util_format_description(p_res
->format
)));
233 pipe_resource_reference(&p_res
->next
, stencil
);
237 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
238 struct iris_resource
**out_z
,
239 struct iris_resource
**out_s
)
247 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
248 *out_z
= (void *) res
;
249 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
252 *out_s
= (void *) res
;
257 iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
258 enum isl_tiling tiling
,
259 enum pipe_texture_target target
)
262 case PIPE_TEXTURE_1D
:
263 case PIPE_TEXTURE_1D_ARRAY
:
264 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
265 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
267 case PIPE_TEXTURE_2D
:
268 case PIPE_TEXTURE_2D_ARRAY
:
269 case PIPE_TEXTURE_RECT
:
270 case PIPE_TEXTURE_CUBE
:
271 case PIPE_TEXTURE_CUBE_ARRAY
:
272 return ISL_DIM_LAYOUT_GEN4_2D
;
274 case PIPE_TEXTURE_3D
:
275 return (devinfo
->gen
>= 9 ?
276 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
278 case PIPE_MAX_TEXTURE_TYPES
:
282 unreachable("invalid texture type");
286 iris_resource_disable_aux(struct iris_resource
*res
)
288 iris_bo_unreference(res
->aux
.bo
);
289 iris_bo_unreference(res
->aux
.clear_color_bo
);
290 free(res
->aux
.state
);
292 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
293 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
294 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
295 res
->aux
.surf
.size_B
= 0;
297 res
->aux
.clear_color_bo
= NULL
;
298 res
->aux
.state
= NULL
;
302 iris_resource_destroy(struct pipe_screen
*screen
,
303 struct pipe_resource
*resource
)
305 struct iris_resource
*res
= (struct iris_resource
*)resource
;
307 if (resource
->target
== PIPE_BUFFER
)
308 util_range_destroy(&res
->valid_buffer_range
);
310 iris_resource_disable_aux(res
);
312 iris_bo_unreference(res
->bo
);
316 static struct iris_resource
*
317 iris_alloc_resource(struct pipe_screen
*pscreen
,
318 const struct pipe_resource
*templ
)
320 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
325 res
->base
.screen
= pscreen
;
326 pipe_reference_init(&res
->base
.reference
, 1);
328 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
329 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
331 if (templ
->target
== PIPE_BUFFER
)
332 util_range_init(&res
->valid_buffer_range
);
338 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
340 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
341 return minify(res
->surf
.logical_level0_px
.depth
, level
);
343 return res
->surf
.logical_level0_px
.array_len
;
346 static enum isl_aux_state
**
347 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
349 uint32_t total_slices
= 0;
350 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
351 total_slices
+= iris_get_num_logical_layers(res
, level
);
353 const size_t per_level_array_size
=
354 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
356 /* We're going to allocate a single chunk of data for both the per-level
357 * reference array and the arrays of aux_state. This makes cleanup
358 * significantly easier.
360 const size_t total_size
=
361 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
363 void *data
= malloc(total_size
);
367 enum isl_aux_state
**per_level_arr
= data
;
368 enum isl_aux_state
*s
= data
+ per_level_array_size
;
369 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
370 per_level_arr
[level
] = s
;
371 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
372 for (uint32_t a
= 0; a
< level_layers
; a
++)
375 assert((void *)s
== data
+ total_size
);
377 return per_level_arr
;
381 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
383 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
384 return devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
: 0;
388 * Configure aux for the resource, but don't allocate it. For images which
389 * might be shared with modifiers, we must allocate the image and aux data in
393 iris_resource_configure_aux(struct iris_screen
*screen
,
394 struct iris_resource
*res
, bool imported
,
395 uint64_t *aux_size_B
,
396 uint32_t *alloc_flags
)
398 struct isl_device
*isl_dev
= &screen
->isl_dev
;
399 enum isl_aux_state initial_state
;
400 UNUSED
bool ok
= false;
404 assert(!res
->aux
.bo
);
406 switch (res
->aux
.usage
) {
407 case ISL_AUX_USAGE_NONE
:
408 res
->aux
.surf
.size_B
= 0;
411 case ISL_AUX_USAGE_HIZ
:
412 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
413 ok
= isl_surf_get_hiz_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
415 case ISL_AUX_USAGE_MCS
:
416 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
418 * "When MCS buffer is enabled and bound to MSRT, it is required
419 * that it is cleared prior to any rendering."
421 * Since we only use the MCS buffer for rendering, we just clear it
422 * immediately on allocation. The clear value for MCS buffers is all
423 * 1's, so we simply memset it to 0xff.
425 initial_state
= ISL_AUX_STATE_CLEAR
;
426 ok
= isl_surf_get_mcs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
428 case ISL_AUX_USAGE_CCS_D
:
429 case ISL_AUX_USAGE_CCS_E
:
430 /* When CCS_E is used, we need to ensure that the CCS starts off in
431 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
434 * "If Software wants to enable Color Compression without Fast
435 * clear, Software needs to initialize MCS with zeros."
437 * A CCS value of 0 indicates that the corresponding block is in the
438 * pass-through state which is what we want.
440 * For CCS_D, do the same thing. On Gen9+, this avoids having any
441 * undefined bits in the aux buffer.
445 isl_drm_modifier_get_default_aux_state(res
->mod_info
->modifier
);
447 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
448 *alloc_flags
|= BO_ALLOC_ZEROED
;
449 ok
= isl_surf_get_ccs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
, 0);
453 /* We should have a valid aux_surf. */
457 /* No work is needed for a zero-sized auxiliary buffer. */
458 if (res
->aux
.surf
.size_B
== 0)
461 if (!res
->aux
.state
) {
462 /* Create the aux_state for the auxiliary buffer. */
463 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
468 uint64_t size
= res
->aux
.surf
.size_B
;
470 /* Allocate space in the buffer for storing the clear color. On modern
471 * platforms (gen > 9), we can read it directly from such buffer.
473 * On gen <= 9, we are going to store the clear color on the buffer
474 * anyways, and copy it back to the surface state during state emission.
476 res
->aux
.clear_color_offset
= size
;
477 size
+= iris_get_aux_clear_color_state_size(screen
);
480 if (res
->aux
.usage
== ISL_AUX_USAGE_HIZ
) {
481 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
482 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
483 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
485 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
486 * For LOD == 0, we can grow the dimensions to make it work.
488 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
489 res
->aux
.has_hiz
|= 1 << level
;
497 * Initialize the aux buffer contents.
500 iris_resource_init_aux_buf(struct iris_resource
*res
, uint32_t alloc_flags
,
501 unsigned clear_color_state_size
)
503 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
504 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
507 iris_resource_disable_aux(res
);
511 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
512 uint8_t memset_value
= res
->aux
.usage
== ISL_AUX_USAGE_MCS
? 0xFF : 0;
513 memset((char*)map
+ res
->aux
.offset
, memset_value
,
514 res
->aux
.surf
.size_B
);
517 /* Zero the indirect clear color to match ::fast_clear_color. */
518 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
519 clear_color_state_size
);
521 iris_bo_unmap(res
->aux
.bo
);
524 if (clear_color_state_size
> 0) {
525 res
->aux
.clear_color_bo
= res
->aux
.bo
;
526 iris_bo_reference(res
->aux
.clear_color_bo
);
533 * Allocate the initial aux surface for a resource based on aux.usage
536 iris_resource_alloc_separate_aux(struct iris_screen
*screen
,
537 struct iris_resource
*res
)
539 uint32_t alloc_flags
;
541 if (!iris_resource_configure_aux(screen
, res
, false, &size
, &alloc_flags
))
547 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
548 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
549 * of bytes instead of trying to recalculate based on different format
552 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
, 4096,
553 IRIS_MEMZONE_OTHER
, I915_TILING_Y
,
554 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
559 if (!iris_resource_init_aux_buf(res
, alloc_flags
,
560 iris_get_aux_clear_color_state_size(screen
)))
567 iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
568 struct iris_resource
*res
)
570 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
571 assert(iris_resource_unfinished_aux_import(res
));
572 assert(!res
->mod_info
->supports_clear_color
);
574 struct iris_resource
*aux_res
= (void *) res
->base
.next
;
575 assert(aux_res
->aux
.surf
.row_pitch_B
&& aux_res
->aux
.offset
&&
578 assert(res
->bo
== aux_res
->aux
.bo
);
579 iris_bo_reference(aux_res
->aux
.bo
);
580 res
->aux
.bo
= aux_res
->aux
.bo
;
582 res
->aux
.offset
= aux_res
->aux
.offset
;
584 assert(res
->bo
->size
>= (res
->aux
.offset
+ res
->aux
.surf
.size_B
));
585 assert(res
->aux
.clear_color_bo
== NULL
);
586 res
->aux
.clear_color_offset
= 0;
588 assert(aux_res
->aux
.surf
.row_pitch_B
== res
->aux
.surf
.row_pitch_B
);
590 unsigned clear_color_state_size
=
591 iris_get_aux_clear_color_state_size(screen
);
593 if (clear_color_state_size
> 0) {
594 res
->aux
.clear_color_bo
=
595 iris_bo_alloc(screen
->bufmgr
, "clear color buffer",
596 clear_color_state_size
, IRIS_MEMZONE_OTHER
);
597 res
->aux
.clear_color_offset
= 0;
600 iris_resource_destroy(&screen
->base
, res
->base
.next
);
601 res
->base
.next
= NULL
;
605 supports_mcs(const struct isl_surf
*surf
)
607 /* MCS compression only applies to multisampled resources. */
608 if (surf
->samples
<= 1)
611 /* Depth and stencil buffers use the IMS (interleaved) layout. */
612 if (isl_surf_usage_is_depth_or_stencil(surf
->usage
))
619 supports_ccs(const struct gen_device_info
*devinfo
,
620 const struct isl_surf
*surf
)
622 /* CCS only supports singlesampled resources. */
623 if (surf
->samples
> 1)
626 /* Note: still need to check the format! */
631 static struct pipe_resource
*
632 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
633 const struct pipe_resource
*templ
)
635 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
636 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
638 assert(templ
->target
== PIPE_BUFFER
);
639 assert(templ
->height0
<= 1);
640 assert(templ
->depth0
<= 1);
641 assert(templ
->format
== PIPE_FORMAT_NONE
||
642 util_format_get_blocksize(templ
->format
) == 1);
644 res
->internal_format
= templ
->format
;
645 res
->surf
.tiling
= ISL_TILING_LINEAR
;
647 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
648 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
649 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
650 memzone
= IRIS_MEMZONE_SHADER
;
651 name
= "shader kernels";
652 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
653 memzone
= IRIS_MEMZONE_SURFACE
;
654 name
= "surface state";
655 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
656 memzone
= IRIS_MEMZONE_DYNAMIC
;
657 name
= "dynamic state";
660 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
662 iris_resource_destroy(pscreen
, &res
->base
);
669 static struct pipe_resource
*
670 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
671 const struct pipe_resource
*templ
,
672 const uint64_t *modifiers
,
675 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
676 struct gen_device_info
*devinfo
= &screen
->devinfo
;
677 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
682 const struct util_format_description
*format_desc
=
683 util_format_description(templ
->format
);
684 const bool has_depth
= util_format_has_depth(format_desc
);
686 select_best_modifier(devinfo
, templ
->format
, modifiers
, modifiers_count
);
688 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
690 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
691 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
693 tiling_flags
= 1 << res
->mod_info
->tiling
;
695 if (modifiers_count
> 0) {
696 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
700 /* No modifiers - we can select our own tiling. */
703 /* Depth must be Y-tiled */
704 tiling_flags
= ISL_TILING_Y0_BIT
;
705 } else if (templ
->format
== PIPE_FORMAT_S8_UINT
) {
706 /* Stencil must be W-tiled */
707 tiling_flags
= ISL_TILING_W_BIT
;
708 } else if (templ
->target
== PIPE_BUFFER
||
709 templ
->target
== PIPE_TEXTURE_1D
||
710 templ
->target
== PIPE_TEXTURE_1D_ARRAY
) {
711 /* Use linear for buffers and 1D textures */
712 tiling_flags
= ISL_TILING_LINEAR_BIT
;
715 /* Use linear for staging buffers */
716 if (templ
->usage
== PIPE_USAGE_STAGING
||
717 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
718 tiling_flags
= ISL_TILING_LINEAR_BIT
;
721 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
723 if (templ
->target
== PIPE_TEXTURE_CUBE
||
724 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
725 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
727 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
728 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
729 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
731 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
734 enum pipe_format pfmt
= templ
->format
;
735 res
->internal_format
= pfmt
;
737 /* Should be handled by u_transfer_helper */
738 assert(!util_format_is_depth_and_stencil(pfmt
));
740 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
741 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
743 UNUSED
const bool isl_surf_created_successfully
=
744 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
745 .dim
= target_to_isl_surf_dim(templ
->target
),
747 .width
= templ
->width0
,
748 .height
= templ
->height0
,
749 .depth
= templ
->depth0
,
750 .levels
= templ
->last_level
+ 1,
751 .array_len
= templ
->array_size
,
752 .samples
= MAX2(templ
->nr_samples
, 1),
753 .min_alignment_B
= 0,
756 .tiling_flags
= tiling_flags
);
757 assert(isl_surf_created_successfully
);
760 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
761 } else if (supports_mcs(&res
->surf
)) {
762 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_MCS
;
763 } else if (has_depth
) {
764 if (likely(!(INTEL_DEBUG
& DEBUG_NO_HIZ
)))
765 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
766 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO_RBC
)) &&
767 supports_ccs(devinfo
, &res
->surf
)) {
768 if (isl_format_supports_ccs_e(devinfo
, res
->surf
.format
))
769 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
771 if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
772 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
775 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
777 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
779 /* We don't always support sampling with hiz. But when we do, it must be
782 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1) {
783 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
786 const char *name
= "miptree";
787 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
789 unsigned int flags
= 0;
790 if (templ
->usage
== PIPE_USAGE_STAGING
)
791 flags
|= BO_ALLOC_COHERENT
;
793 /* These are for u_upload_mgr buffers only */
794 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
795 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
796 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
798 uint32_t aux_preferred_alloc_flags
;
799 uint64_t aux_size
= 0;
801 iris_resource_configure_aux(screen
, res
, false, &aux_size
,
802 &aux_preferred_alloc_flags
);
803 aux_enabled
= aux_enabled
&& res
->aux
.surf
.size_B
> 0;
804 const bool separate_aux
= aux_enabled
&& !res
->mod_info
;
808 if (aux_enabled
&& !separate_aux
) {
809 /* Allocate aux data with main surface. This is required for modifiers
810 * with aux data (ccs).
812 aux_offset
= ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
);
813 bo_size
= aux_offset
+ aux_size
;
816 bo_size
= res
->surf
.size_B
;
819 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, 4096, memzone
,
820 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
821 res
->surf
.row_pitch_B
, flags
);
828 if (!iris_resource_alloc_separate_aux(screen
, res
))
831 res
->aux
.bo
= res
->bo
;
832 iris_bo_reference(res
->aux
.bo
);
833 res
->aux
.offset
+= aux_offset
;
834 unsigned clear_color_state_size
=
835 iris_get_aux_clear_color_state_size(screen
);
836 if (clear_color_state_size
> 0)
837 res
->aux
.clear_color_offset
+= aux_offset
;
838 if (!iris_resource_init_aux_buf(res
, flags
, clear_color_state_size
))
844 iris_resource_disable_aux(res
);
849 fprintf(stderr
, "XXX: resource creation failed\n");
850 iris_resource_destroy(pscreen
, &res
->base
);
855 static struct pipe_resource
*
856 iris_resource_create(struct pipe_screen
*pscreen
,
857 const struct pipe_resource
*templ
)
859 if (templ
->target
== PIPE_BUFFER
)
860 return iris_resource_create_for_buffer(pscreen
, templ
);
862 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
866 tiling_to_modifier(uint32_t tiling
)
868 static const uint64_t map
[] = {
869 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
870 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
871 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
874 assert(tiling
< ARRAY_SIZE(map
));
879 static struct pipe_resource
*
880 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
881 const struct pipe_resource
*templ
,
884 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
885 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
886 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
890 assert(templ
->target
== PIPE_BUFFER
);
892 res
->internal_format
= templ
->format
;
893 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
894 user_memory
, templ
->width0
,
901 util_range_add(&res
->valid_buffer_range
, 0, templ
->width0
);
906 static struct pipe_resource
*
907 iris_resource_from_handle(struct pipe_screen
*pscreen
,
908 const struct pipe_resource
*templ
,
909 struct winsys_handle
*whandle
,
912 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
913 struct gen_device_info
*devinfo
= &screen
->devinfo
;
914 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
915 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
919 switch (whandle
->type
) {
920 case WINSYS_HANDLE_TYPE_FD
:
921 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
);
923 case WINSYS_HANDLE_TYPE_SHARED
:
924 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
928 unreachable("invalid winsys handle type");
933 res
->offset
= whandle
->offset
;
935 uint64_t modifier
= whandle
->modifier
;
936 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
937 modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
939 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
940 assert(res
->mod_info
);
942 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
944 const struct iris_format_info fmt
=
945 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
946 res
->internal_format
= templ
->format
;
948 if (templ
->target
== PIPE_BUFFER
) {
949 res
->surf
.tiling
= ISL_TILING_LINEAR
;
951 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
|| whandle
->plane
== 0) {
952 UNUSED
const bool isl_surf_created_successfully
=
953 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
954 .dim
= target_to_isl_surf_dim(templ
->target
),
956 .width
= templ
->width0
,
957 .height
= templ
->height0
,
958 .depth
= templ
->depth0
,
959 .levels
= templ
->last_level
+ 1,
960 .array_len
= templ
->array_size
,
961 .samples
= MAX2(templ
->nr_samples
, 1),
962 .min_alignment_B
= 0,
963 .row_pitch_B
= whandle
->stride
,
965 .tiling_flags
= 1 << res
->mod_info
->tiling
);
966 assert(isl_surf_created_successfully
);
967 assert(res
->bo
->tiling_mode
==
968 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
970 // XXX: create_ccs_buf_for_image?
971 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
) {
972 if (!iris_resource_alloc_separate_aux(screen
, res
))
975 if (res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
976 uint32_t alloc_flags
;
978 res
->aux
.usage
= res
->mod_info
->aux_usage
;
979 res
->aux
.possible_usages
= 1 << res
->mod_info
->aux_usage
;
980 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
981 bool ok
= iris_resource_configure_aux(screen
, res
, true, &size
,
984 /* The gallium dri layer will create a separate plane resource
985 * for the aux image. iris_resource_finish_aux_import will
986 * merge the separate aux parameters back into a single
992 /* Save modifier import information to reconstruct later. After
993 * import, this will be available under a second image accessible
994 * from the main image with res->base.next. See
995 * iris_resource_finish_aux_import.
997 res
->aux
.surf
.row_pitch_B
= whandle
->stride
;
998 res
->aux
.offset
= whandle
->offset
;
999 res
->aux
.bo
= res
->bo
;
1007 iris_resource_destroy(pscreen
, &res
->base
);
1012 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
1014 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1015 struct iris_batch
*render_batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1016 struct iris_resource
*res
= (void *) resource
;
1017 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
1019 iris_resource_prepare_access(ice
, render_batch
, res
,
1020 0, INTEL_REMAINING_LEVELS
,
1021 0, INTEL_REMAINING_LAYERS
,
1022 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
1023 mod
? mod
->supports_clear_color
: false);
1027 iris_resource_get_param(struct pipe_screen
*screen
,
1028 struct pipe_resource
*resource
,
1030 enum pipe_resource_param param
,
1033 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1035 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1036 bool wants_aux
= mod_with_aux
&& plane
> 0;
1037 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
1042 case PIPE_RESOURCE_PARAM_NPLANES
:
1043 *value
= mod_with_aux
? 2 : 1;
1045 case PIPE_RESOURCE_PARAM_STRIDE
:
1046 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
1048 case PIPE_RESOURCE_PARAM_OFFSET
:
1049 *value
= wants_aux
? res
->aux
.offset
: 0;
1051 case PIPE_RESOURCE_PARAM_MODIFIER
:
1052 *value
= res
->mod_info
? res
->mod_info
->modifier
:
1053 tiling_to_modifier(res
->bo
->tiling_mode
);
1055 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
1056 result
= iris_bo_flink(bo
, &handle
) == 0;
1060 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
1061 *value
= iris_bo_export_gem_handle(bo
);
1063 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
1064 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
1074 iris_resource_get_handle(struct pipe_screen
*pscreen
,
1075 struct pipe_context
*ctx
,
1076 struct pipe_resource
*resource
,
1077 struct winsys_handle
*whandle
,
1080 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1082 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1084 /* Disable aux usage if explicit flush not set and this is the first time
1085 * we are dealing with this resource and the resource was not created with
1086 * a modifier with aux.
1088 if (!mod_with_aux
&&
1089 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0) &&
1090 p_atomic_read(&resource
->reference
.count
) == 1) {
1091 iris_resource_disable_aux(res
);
1095 if (mod_with_aux
&& whandle
->plane
> 0) {
1096 assert(res
->aux
.bo
);
1098 whandle
->stride
= res
->aux
.surf
.row_pitch_B
;
1099 whandle
->offset
= res
->aux
.offset
;
1101 /* If this is a buffer, stride should be 0 - no need to special case */
1102 whandle
->stride
= res
->surf
.row_pitch_B
;
1106 res
->mod_info
? res
->mod_info
->modifier
1107 : tiling_to_modifier(res
->bo
->tiling_mode
);
1110 enum isl_aux_usage allowed_usage
=
1111 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1113 if (res
->aux
.usage
!= allowed_usage
) {
1114 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
1115 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
1116 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
1120 switch (whandle
->type
) {
1121 case WINSYS_HANDLE_TYPE_SHARED
:
1122 return iris_bo_flink(bo
, &whandle
->handle
) == 0;
1123 case WINSYS_HANDLE_TYPE_KMS
:
1124 whandle
->handle
= iris_bo_export_gem_handle(bo
);
1126 case WINSYS_HANDLE_TYPE_FD
:
1127 return iris_bo_export_dmabuf(bo
, (int *) &whandle
->handle
) == 0;
1134 resource_is_busy(struct iris_context
*ice
,
1135 struct iris_resource
*res
)
1137 bool busy
= iris_bo_busy(res
->bo
);
1139 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1140 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1146 iris_invalidate_resource(struct pipe_context
*ctx
,
1147 struct pipe_resource
*resource
)
1149 struct iris_screen
*screen
= (void *) ctx
->screen
;
1150 struct iris_context
*ice
= (void *) ctx
;
1151 struct iris_resource
*res
= (void *) resource
;
1153 if (resource
->target
!= PIPE_BUFFER
)
1156 if (!resource_is_busy(ice
, res
)) {
1157 /* The resource is idle, so just mark that it contains no data and
1158 * keep using the same underlying buffer object.
1160 util_range_set_empty(&res
->valid_buffer_range
);
1164 /* Otherwise, try and replace the backing storage with a new BO. */
1166 /* We can't reallocate memory we didn't allocate in the first place. */
1167 if (res
->bo
->userptr
)
1170 // XXX: We should support this.
1171 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1174 struct iris_bo
*old_bo
= res
->bo
;
1175 struct iris_bo
*new_bo
=
1176 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1177 iris_memzone_for_address(old_bo
->gtt_offset
));
1181 /* Swap out the backing storage */
1184 /* Rebind the buffer, replacing any state referring to the old BO's
1185 * address, and marking state dirty so it's reemitted.
1187 ice
->vtbl
.rebind_buffer(ice
, res
, old_bo
->gtt_offset
);
1189 util_range_set_empty(&res
->valid_buffer_range
);
1191 iris_bo_unreference(old_bo
);
1195 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1196 const struct pipe_box
*flush_box
)
1198 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1201 struct iris_transfer
*map
= (void *) xfer
;
1203 struct pipe_box src_box
= *flush_box
;
1205 /* Account for extra alignment padding in staging buffer */
1206 if (xfer
->resource
->target
== PIPE_BUFFER
)
1207 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1209 struct pipe_box dst_box
= (struct pipe_box
) {
1210 .x
= xfer
->box
.x
+ flush_box
->x
,
1211 .y
= xfer
->box
.y
+ flush_box
->y
,
1212 .z
= xfer
->box
.z
+ flush_box
->z
,
1213 .width
= flush_box
->width
,
1214 .height
= flush_box
->height
,
1215 .depth
= flush_box
->depth
,
1218 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1219 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1224 iris_unmap_copy_region(struct iris_transfer
*map
)
1226 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1232 iris_map_copy_region(struct iris_transfer
*map
)
1234 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1235 struct pipe_transfer
*xfer
= &map
->base
;
1236 struct pipe_box
*box
= &xfer
->box
;
1237 struct iris_resource
*res
= (void *) xfer
->resource
;
1239 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1240 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1242 struct pipe_resource templ
= (struct pipe_resource
) {
1243 .usage
= PIPE_USAGE_STAGING
,
1244 .width0
= box
->width
+ extra
,
1245 .height0
= box
->height
,
1247 .nr_samples
= xfer
->resource
->nr_samples
,
1248 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1249 .array_size
= box
->depth
,
1250 .format
= res
->internal_format
,
1253 if (xfer
->resource
->target
== PIPE_BUFFER
)
1254 templ
.target
= PIPE_BUFFER
;
1255 else if (templ
.array_size
> 1)
1256 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1258 templ
.target
= PIPE_TEXTURE_2D
;
1260 map
->staging
= iris_resource_create(pscreen
, &templ
);
1261 assert(map
->staging
);
1263 if (templ
.target
!= PIPE_BUFFER
) {
1264 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1265 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1266 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1269 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1270 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1271 xfer
->resource
, xfer
->level
, box
);
1272 /* Ensure writes to the staging BO land before we map it below. */
1273 iris_emit_pipe_control_flush(map
->batch
,
1274 "transfer read: flush before mapping",
1275 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1276 PIPE_CONTROL_CS_STALL
);
1279 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1281 if (iris_batch_references(map
->batch
, staging_bo
))
1282 iris_batch_flush(map
->batch
);
1285 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1287 map
->unmap
= iris_unmap_copy_region
;
1291 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1292 unsigned *out_x0_el
, unsigned *out_y0_el
)
1294 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1295 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1297 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1302 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1303 * different tiling patterns.
1306 iris_resource_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1307 uint32_t *tile_w
, uint32_t *tile_h
)
1318 case ISL_TILING_LINEAR
:
1323 unreachable("not reached");
1329 * This function computes masks that may be used to select the bits of the X
1330 * and Y coordinates that indicate the offset within a tile. If the BO is
1331 * untiled, the masks are set to 0.
1334 iris_resource_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1335 uint32_t *mask_x
, uint32_t *mask_y
)
1337 uint32_t tile_w_bytes
, tile_h
;
1339 iris_resource_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1341 *mask_x
= tile_w_bytes
/ cpp
- 1;
1342 *mask_y
= tile_h
- 1;
1346 * Compute the offset (in bytes) from the start of the BO to the given x
1347 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1348 * multiples of the tile size.
1351 iris_resource_get_aligned_offset(const struct iris_resource
*res
,
1352 uint32_t x
, uint32_t y
)
1354 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1355 unsigned cpp
= fmtl
->bpb
/ 8;
1356 uint32_t pitch
= res
->surf
.row_pitch_B
;
1358 switch (res
->surf
.tiling
) {
1360 unreachable("not reached");
1361 case ISL_TILING_LINEAR
:
1362 return y
* pitch
+ x
* cpp
;
1364 assert((x
% (512 / cpp
)) == 0);
1365 assert((y
% 8) == 0);
1366 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1368 assert((x
% (128 / cpp
)) == 0);
1369 assert((y
% 32) == 0);
1370 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1375 * Rendering with tiled buffers requires that the base address of the buffer
1376 * be aligned to a page boundary. For renderbuffers, and sometimes with
1377 * textures, we may want the surface to point at a texture image level that
1378 * isn't at a page boundary.
1380 * This function returns an appropriately-aligned base offset
1381 * according to the tiling restrictions, plus any required x/y offset
1385 iris_resource_get_tile_offsets(const struct iris_resource
*res
,
1386 uint32_t level
, uint32_t z
,
1387 uint32_t *tile_x
, uint32_t *tile_y
)
1390 uint32_t mask_x
, mask_y
;
1392 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1393 const unsigned cpp
= fmtl
->bpb
/ 8;
1395 iris_resource_get_tile_masks(res
->surf
.tiling
, cpp
, &mask_x
, &mask_y
);
1396 get_image_offset_el(&res
->surf
, level
, z
, &x
, &y
);
1398 *tile_x
= x
& mask_x
;
1399 *tile_y
= y
& mask_y
;
1401 return iris_resource_get_aligned_offset(res
, x
& ~mask_x
, y
& ~mask_y
);
1405 * Get pointer offset into stencil buffer.
1407 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1408 * must decode the tile's layout in software.
1411 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1413 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1415 * Even though the returned offset is always positive, the return type is
1417 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1418 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1421 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
)
1423 uint32_t tile_size
= 4096;
1424 uint32_t tile_width
= 64;
1425 uint32_t tile_height
= 64;
1426 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1428 uint32_t tile_x
= x
/ tile_width
;
1429 uint32_t tile_y
= y
/ tile_height
;
1431 /* The byte's address relative to the tile's base addres. */
1432 uint32_t byte_x
= x
% tile_width
;
1433 uint32_t byte_y
= y
% tile_height
;
1435 uintptr_t u
= tile_y
* row_size
1436 + tile_x
* tile_size
1437 + 512 * (byte_x
/ 8)
1439 + 32 * ((byte_y
/ 4) % 2)
1440 + 16 * ((byte_x
/ 4) % 2)
1441 + 8 * ((byte_y
/ 2) % 2)
1442 + 4 * ((byte_x
/ 2) % 2)
1450 iris_unmap_s8(struct iris_transfer
*map
)
1452 struct pipe_transfer
*xfer
= &map
->base
;
1453 const struct pipe_box
*box
= &xfer
->box
;
1454 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1455 struct isl_surf
*surf
= &res
->surf
;
1457 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1458 uint8_t *untiled_s8_map
= map
->ptr
;
1459 uint8_t *tiled_s8_map
=
1460 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1462 for (int s
= 0; s
< box
->depth
; s
++) {
1463 unsigned x0_el
, y0_el
;
1464 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1466 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1467 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1468 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1470 y0_el
+ box
->y
+ y
);
1471 tiled_s8_map
[offset
] =
1472 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1482 iris_map_s8(struct iris_transfer
*map
)
1484 struct pipe_transfer
*xfer
= &map
->base
;
1485 const struct pipe_box
*box
= &xfer
->box
;
1486 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1487 struct isl_surf
*surf
= &res
->surf
;
1489 xfer
->stride
= surf
->row_pitch_B
;
1490 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1492 /* The tiling and detiling functions require that the linear buffer has
1493 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1494 * over-allocate the linear buffer to get the proper alignment.
1496 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1497 assert(map
->buffer
);
1499 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1500 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1501 * invalidate is set, since we'll be writing the whole rectangle from our
1502 * temporary buffer back out.
1504 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1505 uint8_t *untiled_s8_map
= map
->ptr
;
1506 uint8_t *tiled_s8_map
=
1507 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1509 for (int s
= 0; s
< box
->depth
; s
++) {
1510 unsigned x0_el
, y0_el
;
1511 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1513 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1514 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1515 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1517 y0_el
+ box
->y
+ y
);
1518 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1519 tiled_s8_map
[offset
];
1525 map
->unmap
= iris_unmap_s8
;
1528 /* Compute extent parameters for use with tiled_memcpy functions.
1529 * xs are in units of bytes and ys are in units of strides.
1532 tile_extents(const struct isl_surf
*surf
,
1533 const struct pipe_box
*box
,
1534 unsigned level
, int z
,
1535 unsigned *x1_B
, unsigned *x2_B
,
1536 unsigned *y1_el
, unsigned *y2_el
)
1538 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1539 const unsigned cpp
= fmtl
->bpb
/ 8;
1541 assert(box
->x
% fmtl
->bw
== 0);
1542 assert(box
->y
% fmtl
->bh
== 0);
1544 unsigned x0_el
, y0_el
;
1545 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1547 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1548 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1549 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1550 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1554 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1556 struct pipe_transfer
*xfer
= &map
->base
;
1557 const struct pipe_box
*box
= &xfer
->box
;
1558 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1559 struct isl_surf
*surf
= &res
->surf
;
1561 const bool has_swizzling
= false;
1563 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1565 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1567 for (int s
= 0; s
< box
->depth
; s
++) {
1568 unsigned x1
, x2
, y1
, y2
;
1569 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1571 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1573 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1574 surf
->row_pitch_B
, xfer
->stride
,
1575 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1578 os_free_aligned(map
->buffer
);
1579 map
->buffer
= map
->ptr
= NULL
;
1583 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1585 struct pipe_transfer
*xfer
= &map
->base
;
1586 const struct pipe_box
*box
= &xfer
->box
;
1587 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1588 struct isl_surf
*surf
= &res
->surf
;
1590 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1591 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1593 unsigned x1
, x2
, y1
, y2
;
1594 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1596 /* The tiling and detiling functions require that the linear buffer has
1597 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1598 * over-allocate the linear buffer to get the proper alignment.
1601 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1602 assert(map
->buffer
);
1603 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1605 const bool has_swizzling
= false;
1607 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1609 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1611 for (int s
= 0; s
< box
->depth
; s
++) {
1612 unsigned x1
, x2
, y1
, y2
;
1613 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1615 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1616 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1618 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1619 surf
->row_pitch_B
, has_swizzling
,
1620 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1624 map
->unmap
= iris_unmap_tiled_memcpy
;
1628 iris_map_direct(struct iris_transfer
*map
)
1630 struct pipe_transfer
*xfer
= &map
->base
;
1631 struct pipe_box
*box
= &xfer
->box
;
1632 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1634 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1636 if (res
->base
.target
== PIPE_BUFFER
) {
1638 xfer
->layer_stride
= 0;
1640 map
->ptr
= ptr
+ box
->x
;
1642 struct isl_surf
*surf
= &res
->surf
;
1643 const struct isl_format_layout
*fmtl
=
1644 isl_format_get_layout(surf
->format
);
1645 const unsigned cpp
= fmtl
->bpb
/ 8;
1646 unsigned x0_el
, y0_el
;
1648 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1650 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1651 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1653 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1658 can_promote_to_async(const struct iris_resource
*res
,
1659 const struct pipe_box
*box
,
1660 enum pipe_transfer_usage usage
)
1662 /* If we're writing to a section of the buffer that hasn't even been
1663 * initialized with useful data, then we can safely promote this write
1664 * to be unsynchronized. This helps the common pattern of appending data.
1666 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1667 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1668 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1669 box
->x
+ box
->width
);
1673 iris_transfer_map(struct pipe_context
*ctx
,
1674 struct pipe_resource
*resource
,
1676 enum pipe_transfer_usage usage
,
1677 const struct pipe_box
*box
,
1678 struct pipe_transfer
**ptransfer
)
1680 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1681 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1682 struct isl_surf
*surf
= &res
->surf
;
1684 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1685 /* Replace the backing storage with a fresh buffer for non-async maps */
1686 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1687 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1688 iris_invalidate_resource(ctx
, resource
);
1690 /* If we can discard the whole resource, we can discard the range. */
1691 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1694 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1695 can_promote_to_async(res
, box
, usage
)) {
1696 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1699 bool need_resolve
= false;
1700 bool need_color_resolve
= false;
1702 if (resource
->target
!= PIPE_BUFFER
) {
1703 bool need_hiz_resolve
= iris_resource_level_has_hiz(res
, level
);
1705 need_color_resolve
=
1706 (res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
||
1707 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) &&
1708 iris_has_color_unresolved(res
, level
, 1, box
->z
, box
->depth
);
1710 need_resolve
= need_color_resolve
|| need_hiz_resolve
;
1713 bool map_would_stall
= false;
1715 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1716 map_would_stall
= need_resolve
|| resource_is_busy(ice
, res
);
1718 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1719 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1723 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1724 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1727 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1728 struct pipe_transfer
*xfer
= &map
->base
;
1733 memset(map
, 0, sizeof(*map
));
1734 map
->dbg
= &ice
->dbg
;
1736 pipe_resource_reference(&xfer
->resource
, resource
);
1737 xfer
->level
= level
;
1738 xfer
->usage
= usage
;
1742 if (usage
& PIPE_TRANSFER_WRITE
)
1743 util_range_add(&res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1745 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1746 * there is to access them simultaneously on the CPU & GPU. This also
1747 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1748 * contain state we're constructing for a GPU draw call, which would
1749 * kill us with infinite stack recursion.
1751 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1752 PIPE_TRANSFER_COHERENT
|
1753 PIPE_TRANSFER_MAP_DIRECTLY
);
1755 /* GPU copies are not useful for buffer reads. Instead of stalling to
1756 * read from the original buffer, we'd simply copy it to a temporary...
1757 * then stall (a bit longer) to read from that buffer.
1759 * Images are less clear-cut. Color resolves are destructive, removing
1760 * the underlying compression, so we'd rather blit the data to a linear
1761 * temporary and map that, to avoid the resolve. (It might be better to
1762 * a tiled temporary and use the tiled_memcpy paths...)
1764 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) && !need_color_resolve
)
1767 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1768 if (fmtl
->txc
== ISL_TXC_ASTC
)
1771 if ((map_would_stall
|| res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) && !no_gpu
) {
1772 /* If we need a synchronous mapping and the resource is busy, or needs
1773 * resolving, we copy to/from a linear temporary buffer using the GPU.
1775 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1776 map
->blorp
= &ice
->blorp
;
1777 iris_map_copy_region(map
);
1779 /* Otherwise we're free to map on the CPU. */
1782 iris_resource_access_raw(ice
, &ice
->batches
[IRIS_BATCH_RENDER
], res
,
1783 level
, box
->z
, box
->depth
,
1784 usage
& PIPE_TRANSFER_WRITE
);
1787 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1788 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1789 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1790 iris_batch_flush(&ice
->batches
[i
]);
1794 if (surf
->tiling
== ISL_TILING_W
) {
1795 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1797 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1798 iris_map_tiled_memcpy(map
);
1800 iris_map_direct(map
);
1808 iris_transfer_flush_region(struct pipe_context
*ctx
,
1809 struct pipe_transfer
*xfer
,
1810 const struct pipe_box
*box
)
1812 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1813 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1814 struct iris_transfer
*map
= (void *) xfer
;
1817 iris_flush_staging_region(xfer
, box
);
1819 uint32_t history_flush
= 0;
1821 if (res
->base
.target
== PIPE_BUFFER
) {
1822 history_flush
|= iris_flush_bits_for_history(res
) |
1823 (map
->staging
? PIPE_CONTROL_RENDER_TARGET_FLUSH
: 0);
1826 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
1827 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1828 struct iris_batch
*batch
= &ice
->batches
[i
];
1829 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
1830 iris_batch_maybe_flush(batch
, 24);
1831 iris_emit_pipe_control_flush(batch
,
1832 "cache history: transfer flush",
1838 /* Make sure we flag constants dirty even if there's no need to emit
1839 * any PIPE_CONTROLs to a batch.
1841 iris_dirty_for_history(ice
, res
);
1845 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1847 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1848 struct iris_transfer
*map
= (void *) xfer
;
1850 if (!(xfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
)) {
1851 struct pipe_box flush_box
= {
1852 .x
= 0, .y
= 0, .z
= 0,
1853 .width
= xfer
->box
.width
,
1854 .height
= xfer
->box
.height
,
1855 .depth
= xfer
->box
.depth
,
1857 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
1863 pipe_resource_reference(&xfer
->resource
, NULL
);
1864 slab_free(&ice
->transfer_pool
, map
);
1868 * Mark state dirty that needs to be re-emitted when a resource is written.
1871 iris_dirty_for_history(struct iris_context
*ice
,
1872 struct iris_resource
*res
)
1874 uint64_t dirty
= 0ull;
1876 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1877 dirty
|= IRIS_DIRTY_CONSTANTS_VS
|
1878 IRIS_DIRTY_CONSTANTS_TCS
|
1879 IRIS_DIRTY_CONSTANTS_TES
|
1880 IRIS_DIRTY_CONSTANTS_GS
|
1881 IRIS_DIRTY_CONSTANTS_FS
|
1882 IRIS_DIRTY_CONSTANTS_CS
|
1883 IRIS_ALL_DIRTY_BINDINGS
;
1886 ice
->state
.dirty
|= dirty
;
1890 * Produce a set of PIPE_CONTROL bits which ensure data written to a
1891 * resource becomes visible, and any stale read cache data is invalidated.
1894 iris_flush_bits_for_history(struct iris_resource
*res
)
1896 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
1898 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1899 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
1900 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1903 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
1904 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1906 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
1907 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1909 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
1910 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
1916 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
1917 struct iris_batch
*batch
,
1918 struct iris_resource
*res
,
1919 uint32_t extra_flags
,
1922 if (res
->base
.target
!= PIPE_BUFFER
)
1925 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
1927 iris_emit_pipe_control_flush(batch
, reason
, flush
);
1929 iris_dirty_for_history(ice
, res
);
1933 iris_resource_set_clear_color(struct iris_context
*ice
,
1934 struct iris_resource
*res
,
1935 union isl_color_value color
)
1937 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
1938 res
->aux
.clear_color
= color
;
1945 union isl_color_value
1946 iris_resource_get_clear_color(const struct iris_resource
*res
,
1947 struct iris_bo
**clear_color_bo
,
1948 uint64_t *clear_color_offset
)
1950 assert(res
->aux
.bo
);
1953 *clear_color_bo
= res
->aux
.clear_color_bo
;
1954 if (clear_color_offset
)
1955 *clear_color_offset
= res
->aux
.clear_color_offset
;
1956 return res
->aux
.clear_color
;
1959 static enum pipe_format
1960 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
1962 struct iris_resource
*res
= (void *) p_res
;
1963 return res
->internal_format
;
1966 static const struct u_transfer_vtbl transfer_vtbl
= {
1967 .resource_create
= iris_resource_create
,
1968 .resource_destroy
= iris_resource_destroy
,
1969 .transfer_map
= iris_transfer_map
,
1970 .transfer_unmap
= iris_transfer_unmap
,
1971 .transfer_flush_region
= iris_transfer_flush_region
,
1972 .get_internal_format
= iris_resource_get_internal_format
,
1973 .set_stencil
= iris_resource_set_separate_stencil
,
1974 .get_stencil
= iris_resource_get_separate_stencil
,
1978 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
1980 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
1981 pscreen
->resource_create_with_modifiers
=
1982 iris_resource_create_with_modifiers
;
1983 pscreen
->resource_create
= u_transfer_helper_resource_create
;
1984 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
1985 pscreen
->resource_from_handle
= iris_resource_from_handle
;
1986 pscreen
->resource_get_handle
= iris_resource_get_handle
;
1987 pscreen
->resource_get_param
= iris_resource_get_param
;
1988 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
1989 pscreen
->transfer_helper
=
1990 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
1994 iris_init_resource_functions(struct pipe_context
*ctx
)
1996 ctx
->flush_resource
= iris_flush_resource
;
1997 ctx
->invalidate_resource
= iris_invalidate_resource
;
1998 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
1999 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
2000 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
2001 ctx
->buffer_subdata
= u_default_buffer_subdata
;
2002 ctx
->texture_subdata
= u_default_texture_subdata
;