2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
56 enum modifier_priority
{
57 MODIFIER_PRIORITY_INVALID
= 0,
58 MODIFIER_PRIORITY_LINEAR
,
61 MODIFIER_PRIORITY_Y_CCS
,
64 static const uint64_t priority_to_modifier
[] = {
65 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
66 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
67 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
68 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
69 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
73 modifier_is_supported(const struct gen_device_info
*devinfo
,
74 enum pipe_format pfmt
, uint64_t modifier
)
76 /* XXX: do something real */
78 case I915_FORMAT_MOD_Y_TILED_CCS
: {
79 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
82 enum isl_format rt_format
=
83 iris_format_for_usage(devinfo
, pfmt
,
84 ISL_SURF_USAGE_RENDER_TARGET_BIT
).fmt
;
86 enum isl_format linear_format
= isl_format_srgb_to_linear(rt_format
);
88 if (!isl_format_supports_ccs_e(devinfo
, linear_format
))
91 return devinfo
->gen
>= 9 && devinfo
->gen
<= 11;
93 case I915_FORMAT_MOD_Y_TILED
:
94 case I915_FORMAT_MOD_X_TILED
:
95 case DRM_FORMAT_MOD_LINEAR
:
97 case DRM_FORMAT_MOD_INVALID
:
104 select_best_modifier(struct gen_device_info
*devinfo
, enum pipe_format pfmt
,
105 const uint64_t *modifiers
,
108 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
110 for (int i
= 0; i
< count
; i
++) {
111 if (!modifier_is_supported(devinfo
, pfmt
, modifiers
[i
]))
114 switch (modifiers
[i
]) {
115 case I915_FORMAT_MOD_Y_TILED_CCS
:
116 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
118 case I915_FORMAT_MOD_Y_TILED
:
119 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
121 case I915_FORMAT_MOD_X_TILED
:
122 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
124 case DRM_FORMAT_MOD_LINEAR
:
125 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
127 case DRM_FORMAT_MOD_INVALID
:
133 return priority_to_modifier
[prio
];
137 target_to_isl_surf_dim(enum pipe_texture_target target
)
141 case PIPE_TEXTURE_1D
:
142 case PIPE_TEXTURE_1D_ARRAY
:
143 return ISL_SURF_DIM_1D
;
144 case PIPE_TEXTURE_2D
:
145 case PIPE_TEXTURE_CUBE
:
146 case PIPE_TEXTURE_RECT
:
147 case PIPE_TEXTURE_2D_ARRAY
:
148 case PIPE_TEXTURE_CUBE_ARRAY
:
149 return ISL_SURF_DIM_2D
;
150 case PIPE_TEXTURE_3D
:
151 return ISL_SURF_DIM_3D
;
152 case PIPE_MAX_TEXTURE_TYPES
:
155 unreachable("invalid texture type");
159 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
160 enum pipe_format pfmt
,
163 unsigned int *external_only
,
166 struct iris_screen
*screen
= (void *) pscreen
;
167 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
169 uint64_t all_modifiers
[] = {
170 DRM_FORMAT_MOD_LINEAR
,
171 I915_FORMAT_MOD_X_TILED
,
172 I915_FORMAT_MOD_Y_TILED
,
173 I915_FORMAT_MOD_Y_TILED_CCS
,
176 int supported_mods
= 0;
178 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
179 if (!modifier_is_supported(devinfo
, pfmt
, all_modifiers
[i
]))
182 if (supported_mods
< max
) {
184 modifiers
[supported_mods
] = all_modifiers
[i
];
187 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
193 *count
= supported_mods
;
196 static isl_surf_usage_flags_t
197 pipe_bind_to_isl_usage(unsigned bindings
)
199 isl_surf_usage_flags_t usage
= 0;
201 if (bindings
& PIPE_BIND_RENDER_TARGET
)
202 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
204 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
205 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
207 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
208 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
210 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
211 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
216 struct pipe_resource
*
217 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
219 /* For packed depth-stencil, we treat depth as the primary resource
220 * and store S8 as the "second plane" resource.
222 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
230 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
231 struct pipe_resource
*stencil
)
233 assert(util_format_has_depth(util_format_description(p_res
->format
)));
234 pipe_resource_reference(&p_res
->next
, stencil
);
238 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
239 struct iris_resource
**out_z
,
240 struct iris_resource
**out_s
)
248 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
249 *out_z
= (void *) res
;
250 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
253 *out_s
= (void *) res
;
258 iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
259 enum isl_tiling tiling
,
260 enum pipe_texture_target target
)
263 case PIPE_TEXTURE_1D
:
264 case PIPE_TEXTURE_1D_ARRAY
:
265 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
266 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
268 case PIPE_TEXTURE_2D
:
269 case PIPE_TEXTURE_2D_ARRAY
:
270 case PIPE_TEXTURE_RECT
:
271 case PIPE_TEXTURE_CUBE
:
272 case PIPE_TEXTURE_CUBE_ARRAY
:
273 return ISL_DIM_LAYOUT_GEN4_2D
;
275 case PIPE_TEXTURE_3D
:
276 return (devinfo
->gen
>= 9 ?
277 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
279 case PIPE_MAX_TEXTURE_TYPES
:
283 unreachable("invalid texture type");
287 iris_resource_disable_aux(struct iris_resource
*res
)
289 iris_bo_unreference(res
->aux
.bo
);
290 iris_bo_unreference(res
->aux
.clear_color_bo
);
291 free(res
->aux
.state
);
293 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
294 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
295 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
296 res
->aux
.surf
.size_B
= 0;
298 res
->aux
.clear_color_bo
= NULL
;
299 res
->aux
.state
= NULL
;
303 iris_resource_destroy(struct pipe_screen
*screen
,
304 struct pipe_resource
*resource
)
306 struct iris_resource
*res
= (struct iris_resource
*)resource
;
308 if (resource
->target
== PIPE_BUFFER
)
309 util_range_destroy(&res
->valid_buffer_range
);
311 iris_resource_disable_aux(res
);
313 iris_bo_unreference(res
->bo
);
317 static struct iris_resource
*
318 iris_alloc_resource(struct pipe_screen
*pscreen
,
319 const struct pipe_resource
*templ
)
321 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
326 res
->base
.screen
= pscreen
;
327 pipe_reference_init(&res
->base
.reference
, 1);
329 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
330 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
332 if (templ
->target
== PIPE_BUFFER
)
333 util_range_init(&res
->valid_buffer_range
);
339 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
341 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
342 return minify(res
->surf
.logical_level0_px
.depth
, level
);
344 return res
->surf
.logical_level0_px
.array_len
;
347 static enum isl_aux_state
**
348 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
350 uint32_t total_slices
= 0;
351 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
352 total_slices
+= iris_get_num_logical_layers(res
, level
);
354 const size_t per_level_array_size
=
355 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
357 /* We're going to allocate a single chunk of data for both the per-level
358 * reference array and the arrays of aux_state. This makes cleanup
359 * significantly easier.
361 const size_t total_size
=
362 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
364 void *data
= malloc(total_size
);
368 enum isl_aux_state
**per_level_arr
= data
;
369 enum isl_aux_state
*s
= data
+ per_level_array_size
;
370 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
371 per_level_arr
[level
] = s
;
372 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
373 for (uint32_t a
= 0; a
< level_layers
; a
++)
376 assert((void *)s
== data
+ total_size
);
378 return per_level_arr
;
382 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
384 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
385 return devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
: 0;
389 map_aux_addresses(struct iris_screen
*screen
, struct iris_resource
*res
)
391 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
392 if (devinfo
->gen
>= 12 && isl_aux_usage_has_ccs(res
->aux
.usage
)) {
393 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
395 gen_aux_map_add_image(aux_map_ctx
, &res
->surf
, res
->bo
->gtt_offset
,
396 res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
);
397 res
->bo
->aux_map_address
= res
->aux
.bo
->gtt_offset
;
402 * Configure aux for the resource, but don't allocate it. For images which
403 * might be shared with modifiers, we must allocate the image and aux data in
407 iris_resource_configure_aux(struct iris_screen
*screen
,
408 struct iris_resource
*res
, bool imported
,
409 uint64_t *aux_size_B
,
410 uint32_t *alloc_flags
)
412 struct isl_device
*isl_dev
= &screen
->isl_dev
;
413 enum isl_aux_state initial_state
;
414 UNUSED
bool ok
= false;
418 assert(!res
->aux
.bo
);
420 switch (res
->aux
.usage
) {
421 case ISL_AUX_USAGE_NONE
:
422 res
->aux
.surf
.size_B
= 0;
425 case ISL_AUX_USAGE_HIZ
:
426 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
427 ok
= isl_surf_get_hiz_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
429 case ISL_AUX_USAGE_MCS
:
430 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
432 * "When MCS buffer is enabled and bound to MSRT, it is required
433 * that it is cleared prior to any rendering."
435 * Since we only use the MCS buffer for rendering, we just clear it
436 * immediately on allocation. The clear value for MCS buffers is all
437 * 1's, so we simply memset it to 0xff.
439 initial_state
= ISL_AUX_STATE_CLEAR
;
440 ok
= isl_surf_get_mcs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
442 case ISL_AUX_USAGE_CCS_D
:
443 case ISL_AUX_USAGE_CCS_E
:
444 /* When CCS_E is used, we need to ensure that the CCS starts off in
445 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
448 * "If Software wants to enable Color Compression without Fast
449 * clear, Software needs to initialize MCS with zeros."
451 * A CCS value of 0 indicates that the corresponding block is in the
452 * pass-through state which is what we want.
454 * For CCS_D, do the same thing. On Gen9+, this avoids having any
455 * undefined bits in the aux buffer.
459 isl_drm_modifier_get_default_aux_state(res
->mod_info
->modifier
);
461 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
462 *alloc_flags
|= BO_ALLOC_ZEROED
;
463 ok
= isl_surf_get_ccs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
, 0);
467 /* We should have a valid aux_surf. */
471 /* No work is needed for a zero-sized auxiliary buffer. */
472 if (res
->aux
.surf
.size_B
== 0)
475 if (!res
->aux
.state
) {
476 /* Create the aux_state for the auxiliary buffer. */
477 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
482 uint64_t size
= res
->aux
.surf
.size_B
;
484 /* Allocate space in the buffer for storing the clear color. On modern
485 * platforms (gen > 9), we can read it directly from such buffer.
487 * On gen <= 9, we are going to store the clear color on the buffer
488 * anyways, and copy it back to the surface state during state emission.
490 res
->aux
.clear_color_offset
= size
;
491 size
+= iris_get_aux_clear_color_state_size(screen
);
494 if (res
->aux
.usage
== ISL_AUX_USAGE_HIZ
) {
495 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
496 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
497 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
499 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
500 * For LOD == 0, we can grow the dimensions to make it work.
502 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
503 res
->aux
.has_hiz
|= 1 << level
;
511 * Initialize the aux buffer contents.
514 iris_resource_init_aux_buf(struct iris_resource
*res
, uint32_t alloc_flags
,
515 unsigned clear_color_state_size
)
517 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
518 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
521 iris_resource_disable_aux(res
);
525 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
526 uint8_t memset_value
= res
->aux
.usage
== ISL_AUX_USAGE_MCS
? 0xFF : 0;
527 memset((char*)map
+ res
->aux
.offset
, memset_value
,
528 res
->aux
.surf
.size_B
);
531 /* Zero the indirect clear color to match ::fast_clear_color. */
532 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
533 clear_color_state_size
);
535 iris_bo_unmap(res
->aux
.bo
);
538 if (clear_color_state_size
> 0) {
539 res
->aux
.clear_color_bo
= res
->aux
.bo
;
540 iris_bo_reference(res
->aux
.clear_color_bo
);
547 * Allocate the initial aux surface for a resource based on aux.usage
550 iris_resource_alloc_separate_aux(struct iris_screen
*screen
,
551 struct iris_resource
*res
)
553 uint32_t alloc_flags
;
555 if (!iris_resource_configure_aux(screen
, res
, false, &size
, &alloc_flags
))
561 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
562 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
563 * of bytes instead of trying to recalculate based on different format
566 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
, 4096,
568 isl_tiling_to_i915_tiling(res
->aux
.surf
.tiling
),
569 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
574 if (!iris_resource_init_aux_buf(res
, alloc_flags
,
575 iris_get_aux_clear_color_state_size(screen
)))
578 map_aux_addresses(screen
, res
);
584 iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
585 struct iris_resource
*res
)
587 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
588 assert(iris_resource_unfinished_aux_import(res
));
589 assert(!res
->mod_info
->supports_clear_color
);
591 struct iris_resource
*aux_res
= (void *) res
->base
.next
;
592 assert(aux_res
->aux
.surf
.row_pitch_B
&& aux_res
->aux
.offset
&&
595 assert(res
->bo
== aux_res
->aux
.bo
);
596 iris_bo_reference(aux_res
->aux
.bo
);
597 res
->aux
.bo
= aux_res
->aux
.bo
;
599 res
->aux
.offset
= aux_res
->aux
.offset
;
601 assert(res
->bo
->size
>= (res
->aux
.offset
+ res
->aux
.surf
.size_B
));
602 assert(res
->aux
.clear_color_bo
== NULL
);
603 res
->aux
.clear_color_offset
= 0;
605 assert(aux_res
->aux
.surf
.row_pitch_B
== res
->aux
.surf
.row_pitch_B
);
607 unsigned clear_color_state_size
=
608 iris_get_aux_clear_color_state_size(screen
);
610 if (clear_color_state_size
> 0) {
611 res
->aux
.clear_color_bo
=
612 iris_bo_alloc(screen
->bufmgr
, "clear color buffer",
613 clear_color_state_size
, IRIS_MEMZONE_OTHER
);
614 res
->aux
.clear_color_offset
= 0;
617 iris_resource_destroy(&screen
->base
, res
->base
.next
);
618 res
->base
.next
= NULL
;
622 supports_mcs(const struct isl_surf
*surf
)
624 /* MCS compression only applies to multisampled resources. */
625 if (surf
->samples
<= 1)
628 /* Depth and stencil buffers use the IMS (interleaved) layout. */
629 if (isl_surf_usage_is_depth_or_stencil(surf
->usage
))
636 supports_ccs(const struct gen_device_info
*devinfo
,
637 const struct isl_surf
*surf
)
639 /* CCS only supports singlesampled resources. */
640 if (surf
->samples
> 1)
643 /* Note: still need to check the format! */
649 want_ccs_e_for_format(const struct gen_device_info
*devinfo
,
650 enum isl_format format
)
652 if (!isl_format_supports_ccs_e(devinfo
, format
))
655 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
657 /* CCS_E seems to significantly hurt performance with 32-bit floating
658 * point formats. For example, Paraview's "Wavelet Volume" case uses
659 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
660 * formats causes a 62% FPS drop.
662 * However, many benchmarks seem to use 16-bit float with no issues.
664 if (fmtl
->channels
.r
.bits
== 32 && fmtl
->channels
.r
.type
== ISL_SFLOAT
)
670 static struct pipe_resource
*
671 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
672 const struct pipe_resource
*templ
)
674 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
675 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
677 assert(templ
->target
== PIPE_BUFFER
);
678 assert(templ
->height0
<= 1);
679 assert(templ
->depth0
<= 1);
680 assert(templ
->format
== PIPE_FORMAT_NONE
||
681 util_format_get_blocksize(templ
->format
) == 1);
683 res
->internal_format
= templ
->format
;
684 res
->surf
.tiling
= ISL_TILING_LINEAR
;
686 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
687 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
688 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
689 memzone
= IRIS_MEMZONE_SHADER
;
690 name
= "shader kernels";
691 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
692 memzone
= IRIS_MEMZONE_SURFACE
;
693 name
= "surface state";
694 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
695 memzone
= IRIS_MEMZONE_DYNAMIC
;
696 name
= "dynamic state";
699 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
701 iris_resource_destroy(pscreen
, &res
->base
);
708 static struct pipe_resource
*
709 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
710 const struct pipe_resource
*templ
,
711 const uint64_t *modifiers
,
714 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
715 struct gen_device_info
*devinfo
= &screen
->devinfo
;
716 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
721 const struct util_format_description
*format_desc
=
722 util_format_description(templ
->format
);
723 const bool has_depth
= util_format_has_depth(format_desc
);
725 select_best_modifier(devinfo
, templ
->format
, modifiers
, modifiers_count
);
727 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
729 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
730 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
732 tiling_flags
= 1 << res
->mod_info
->tiling
;
734 if (modifiers_count
> 0) {
735 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
739 /* Use linear for staging buffers */
740 if (templ
->usage
== PIPE_USAGE_STAGING
||
741 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
742 tiling_flags
= ISL_TILING_LINEAR_BIT
;
745 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
747 if (templ
->target
== PIPE_TEXTURE_CUBE
||
748 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
749 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
751 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
752 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
753 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
755 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
758 enum pipe_format pfmt
= templ
->format
;
759 res
->internal_format
= pfmt
;
761 /* Should be handled by u_transfer_helper */
762 assert(!util_format_is_depth_and_stencil(pfmt
));
764 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
765 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
767 UNUSED
const bool isl_surf_created_successfully
=
768 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
769 .dim
= target_to_isl_surf_dim(templ
->target
),
771 .width
= templ
->width0
,
772 .height
= templ
->height0
,
773 .depth
= templ
->depth0
,
774 .levels
= templ
->last_level
+ 1,
775 .array_len
= templ
->array_size
,
776 .samples
= MAX2(templ
->nr_samples
, 1),
777 .min_alignment_B
= 0,
780 .tiling_flags
= tiling_flags
);
781 assert(isl_surf_created_successfully
);
784 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
785 } else if (supports_mcs(&res
->surf
)) {
786 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_MCS
;
787 } else if (has_depth
) {
788 if (likely(!(INTEL_DEBUG
& DEBUG_NO_HIZ
)))
789 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
790 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO_RBC
)) &&
791 supports_ccs(devinfo
, &res
->surf
)) {
792 if (want_ccs_e_for_format(devinfo
, res
->surf
.format
))
793 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
795 if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
796 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
799 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
801 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
803 /* We don't always support sampling with hiz. But when we do, it must be
806 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1) {
807 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
810 const char *name
= "miptree";
811 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
813 unsigned int flags
= 0;
814 if (templ
->usage
== PIPE_USAGE_STAGING
)
815 flags
|= BO_ALLOC_COHERENT
;
817 /* These are for u_upload_mgr buffers only */
818 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
819 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
820 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
822 uint32_t aux_preferred_alloc_flags
;
823 uint64_t aux_size
= 0;
825 iris_resource_configure_aux(screen
, res
, false, &aux_size
,
826 &aux_preferred_alloc_flags
);
827 aux_enabled
= aux_enabled
&& res
->aux
.surf
.size_B
> 0;
828 const bool separate_aux
= aux_enabled
&& !res
->mod_info
;
832 if (aux_enabled
&& !separate_aux
) {
833 /* Allocate aux data with main surface. This is required for modifiers
834 * with aux data (ccs).
836 aux_offset
= ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
);
837 bo_size
= aux_offset
+ aux_size
;
840 bo_size
= res
->surf
.size_B
;
843 uint32_t alignment
= MAX2(4096, res
->surf
.alignment_B
);
844 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, alignment
,
846 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
847 res
->surf
.row_pitch_B
, flags
);
854 if (!iris_resource_alloc_separate_aux(screen
, res
))
857 res
->aux
.bo
= res
->bo
;
858 iris_bo_reference(res
->aux
.bo
);
859 res
->aux
.offset
+= aux_offset
;
860 unsigned clear_color_state_size
=
861 iris_get_aux_clear_color_state_size(screen
);
862 if (clear_color_state_size
> 0)
863 res
->aux
.clear_color_offset
+= aux_offset
;
864 if (!iris_resource_init_aux_buf(res
, flags
, clear_color_state_size
))
866 map_aux_addresses(screen
, res
);
871 iris_resource_disable_aux(res
);
876 fprintf(stderr
, "XXX: resource creation failed\n");
877 iris_resource_destroy(pscreen
, &res
->base
);
882 static struct pipe_resource
*
883 iris_resource_create(struct pipe_screen
*pscreen
,
884 const struct pipe_resource
*templ
)
886 if (templ
->target
== PIPE_BUFFER
)
887 return iris_resource_create_for_buffer(pscreen
, templ
);
889 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
893 tiling_to_modifier(uint32_t tiling
)
895 static const uint64_t map
[] = {
896 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
897 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
898 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
901 assert(tiling
< ARRAY_SIZE(map
));
906 static struct pipe_resource
*
907 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
908 const struct pipe_resource
*templ
,
911 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
912 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
913 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
917 assert(templ
->target
== PIPE_BUFFER
);
919 res
->internal_format
= templ
->format
;
920 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
921 user_memory
, templ
->width0
,
928 util_range_add(&res
->base
, &res
->valid_buffer_range
, 0, templ
->width0
);
933 static struct pipe_resource
*
934 iris_resource_from_handle(struct pipe_screen
*pscreen
,
935 const struct pipe_resource
*templ
,
936 struct winsys_handle
*whandle
,
939 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
940 struct gen_device_info
*devinfo
= &screen
->devinfo
;
941 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
942 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
946 switch (whandle
->type
) {
947 case WINSYS_HANDLE_TYPE_FD
:
948 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
);
950 case WINSYS_HANDLE_TYPE_SHARED
:
951 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
955 unreachable("invalid winsys handle type");
960 res
->offset
= whandle
->offset
;
962 uint64_t modifier
= whandle
->modifier
;
963 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
964 modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
966 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
967 assert(res
->mod_info
);
969 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
971 const struct iris_format_info fmt
=
972 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
973 res
->internal_format
= templ
->format
;
975 if (templ
->target
== PIPE_BUFFER
) {
976 res
->surf
.tiling
= ISL_TILING_LINEAR
;
978 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
|| whandle
->plane
== 0) {
979 UNUSED
const bool isl_surf_created_successfully
=
980 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
981 .dim
= target_to_isl_surf_dim(templ
->target
),
983 .width
= templ
->width0
,
984 .height
= templ
->height0
,
985 .depth
= templ
->depth0
,
986 .levels
= templ
->last_level
+ 1,
987 .array_len
= templ
->array_size
,
988 .samples
= MAX2(templ
->nr_samples
, 1),
989 .min_alignment_B
= 0,
990 .row_pitch_B
= whandle
->stride
,
992 .tiling_flags
= 1 << res
->mod_info
->tiling
);
993 assert(isl_surf_created_successfully
);
994 assert(res
->bo
->tiling_mode
==
995 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
997 // XXX: create_ccs_buf_for_image?
998 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
) {
999 if (!iris_resource_alloc_separate_aux(screen
, res
))
1002 if (res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1003 uint32_t alloc_flags
;
1005 res
->aux
.usage
= res
->mod_info
->aux_usage
;
1006 res
->aux
.possible_usages
= 1 << res
->mod_info
->aux_usage
;
1007 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
1008 bool ok
= iris_resource_configure_aux(screen
, res
, true, &size
,
1011 /* The gallium dri layer will create a separate plane resource
1012 * for the aux image. iris_resource_finish_aux_import will
1013 * merge the separate aux parameters back into a single
1019 /* Save modifier import information to reconstruct later. After
1020 * import, this will be available under a second image accessible
1021 * from the main image with res->base.next. See
1022 * iris_resource_finish_aux_import.
1024 res
->aux
.surf
.row_pitch_B
= whandle
->stride
;
1025 res
->aux
.offset
= whandle
->offset
;
1026 res
->aux
.bo
= res
->bo
;
1034 iris_resource_destroy(pscreen
, &res
->base
);
1039 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
1041 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1042 struct iris_batch
*render_batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1043 struct iris_resource
*res
= (void *) resource
;
1044 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
1046 iris_resource_prepare_access(ice
, render_batch
, res
,
1047 0, INTEL_REMAINING_LEVELS
,
1048 0, INTEL_REMAINING_LAYERS
,
1049 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
1050 mod
? mod
->supports_clear_color
: false);
1054 iris_resource_disable_aux_on_first_query(struct pipe_resource
*resource
,
1057 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1059 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1061 /* Disable aux usage if explicit flush not set and this is the first time
1062 * we are dealing with this resource and the resource was not created with
1063 * a modifier with aux.
1065 if (!mod_with_aux
&&
1066 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0) &&
1067 p_atomic_read(&resource
->reference
.count
) == 1) {
1068 iris_resource_disable_aux(res
);
1073 iris_resource_get_param(struct pipe_screen
*screen
,
1074 struct pipe_context
*context
,
1075 struct pipe_resource
*resource
,
1078 enum pipe_resource_param param
,
1079 unsigned handle_usage
,
1082 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1084 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1085 bool wants_aux
= mod_with_aux
&& plane
> 0;
1089 if (iris_resource_unfinished_aux_import(res
))
1090 iris_resource_finish_aux_import(screen
, res
);
1092 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
1094 iris_resource_disable_aux_on_first_query(resource
, handle_usage
);
1097 case PIPE_RESOURCE_PARAM_NPLANES
:
1102 for (struct pipe_resource
*cur
= resource
; cur
; cur
= cur
->next
)
1107 case PIPE_RESOURCE_PARAM_STRIDE
:
1108 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
1110 case PIPE_RESOURCE_PARAM_OFFSET
:
1111 *value
= wants_aux
? res
->aux
.offset
: 0;
1113 case PIPE_RESOURCE_PARAM_MODIFIER
:
1114 *value
= res
->mod_info
? res
->mod_info
->modifier
:
1115 tiling_to_modifier(res
->bo
->tiling_mode
);
1117 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
1118 result
= iris_bo_flink(bo
, &handle
) == 0;
1122 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
1123 *value
= iris_bo_export_gem_handle(bo
);
1125 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
1126 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
1136 iris_resource_get_handle(struct pipe_screen
*pscreen
,
1137 struct pipe_context
*ctx
,
1138 struct pipe_resource
*resource
,
1139 struct winsys_handle
*whandle
,
1142 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1144 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1146 iris_resource_disable_aux_on_first_query(resource
, usage
);
1149 if (mod_with_aux
&& whandle
->plane
> 0) {
1150 assert(res
->aux
.bo
);
1152 whandle
->stride
= res
->aux
.surf
.row_pitch_B
;
1153 whandle
->offset
= res
->aux
.offset
;
1155 /* If this is a buffer, stride should be 0 - no need to special case */
1156 whandle
->stride
= res
->surf
.row_pitch_B
;
1160 res
->mod_info
? res
->mod_info
->modifier
1161 : tiling_to_modifier(res
->bo
->tiling_mode
);
1164 enum isl_aux_usage allowed_usage
=
1165 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1167 if (res
->aux
.usage
!= allowed_usage
) {
1168 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
1169 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
1170 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
1174 switch (whandle
->type
) {
1175 case WINSYS_HANDLE_TYPE_SHARED
:
1176 return iris_bo_flink(bo
, &whandle
->handle
) == 0;
1177 case WINSYS_HANDLE_TYPE_KMS
:
1178 whandle
->handle
= iris_bo_export_gem_handle(bo
);
1180 case WINSYS_HANDLE_TYPE_FD
:
1181 return iris_bo_export_dmabuf(bo
, (int *) &whandle
->handle
) == 0;
1188 resource_is_busy(struct iris_context
*ice
,
1189 struct iris_resource
*res
)
1191 bool busy
= iris_bo_busy(res
->bo
);
1193 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1194 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1200 iris_invalidate_resource(struct pipe_context
*ctx
,
1201 struct pipe_resource
*resource
)
1203 struct iris_screen
*screen
= (void *) ctx
->screen
;
1204 struct iris_context
*ice
= (void *) ctx
;
1205 struct iris_resource
*res
= (void *) resource
;
1207 if (resource
->target
!= PIPE_BUFFER
)
1210 if (!resource_is_busy(ice
, res
)) {
1211 /* The resource is idle, so just mark that it contains no data and
1212 * keep using the same underlying buffer object.
1214 util_range_set_empty(&res
->valid_buffer_range
);
1218 /* Otherwise, try and replace the backing storage with a new BO. */
1220 /* We can't reallocate memory we didn't allocate in the first place. */
1221 if (res
->bo
->userptr
)
1224 // XXX: We should support this.
1225 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1228 struct iris_bo
*old_bo
= res
->bo
;
1229 struct iris_bo
*new_bo
=
1230 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1231 iris_memzone_for_address(old_bo
->gtt_offset
));
1235 /* Swap out the backing storage */
1238 /* Rebind the buffer, replacing any state referring to the old BO's
1239 * address, and marking state dirty so it's reemitted.
1241 ice
->vtbl
.rebind_buffer(ice
, res
, old_bo
->gtt_offset
);
1243 util_range_set_empty(&res
->valid_buffer_range
);
1245 iris_bo_unreference(old_bo
);
1249 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1250 const struct pipe_box
*flush_box
)
1252 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1255 struct iris_transfer
*map
= (void *) xfer
;
1257 struct pipe_box src_box
= *flush_box
;
1259 /* Account for extra alignment padding in staging buffer */
1260 if (xfer
->resource
->target
== PIPE_BUFFER
)
1261 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1263 struct pipe_box dst_box
= (struct pipe_box
) {
1264 .x
= xfer
->box
.x
+ flush_box
->x
,
1265 .y
= xfer
->box
.y
+ flush_box
->y
,
1266 .z
= xfer
->box
.z
+ flush_box
->z
,
1267 .width
= flush_box
->width
,
1268 .height
= flush_box
->height
,
1269 .depth
= flush_box
->depth
,
1272 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1273 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1278 iris_unmap_copy_region(struct iris_transfer
*map
)
1280 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1286 iris_map_copy_region(struct iris_transfer
*map
)
1288 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1289 struct pipe_transfer
*xfer
= &map
->base
;
1290 struct pipe_box
*box
= &xfer
->box
;
1291 struct iris_resource
*res
= (void *) xfer
->resource
;
1293 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1294 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1296 struct pipe_resource templ
= (struct pipe_resource
) {
1297 .usage
= PIPE_USAGE_STAGING
,
1298 .width0
= box
->width
+ extra
,
1299 .height0
= box
->height
,
1301 .nr_samples
= xfer
->resource
->nr_samples
,
1302 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1303 .array_size
= box
->depth
,
1304 .format
= res
->internal_format
,
1307 if (xfer
->resource
->target
== PIPE_BUFFER
)
1308 templ
.target
= PIPE_BUFFER
;
1309 else if (templ
.array_size
> 1)
1310 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1312 templ
.target
= PIPE_TEXTURE_2D
;
1314 map
->staging
= iris_resource_create(pscreen
, &templ
);
1315 assert(map
->staging
);
1317 if (templ
.target
!= PIPE_BUFFER
) {
1318 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1319 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1320 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1323 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1324 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1325 xfer
->resource
, xfer
->level
, box
);
1326 /* Ensure writes to the staging BO land before we map it below. */
1327 iris_emit_pipe_control_flush(map
->batch
,
1328 "transfer read: flush before mapping",
1329 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1330 PIPE_CONTROL_CS_STALL
);
1333 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1335 if (iris_batch_references(map
->batch
, staging_bo
))
1336 iris_batch_flush(map
->batch
);
1339 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1341 map
->unmap
= iris_unmap_copy_region
;
1345 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1346 unsigned *out_x0_el
, unsigned *out_y0_el
)
1348 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1349 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1351 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1356 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1357 * different tiling patterns.
1360 iris_resource_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1361 uint32_t *tile_w
, uint32_t *tile_h
)
1372 case ISL_TILING_LINEAR
:
1377 unreachable("not reached");
1383 * This function computes masks that may be used to select the bits of the X
1384 * and Y coordinates that indicate the offset within a tile. If the BO is
1385 * untiled, the masks are set to 0.
1388 iris_resource_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1389 uint32_t *mask_x
, uint32_t *mask_y
)
1391 uint32_t tile_w_bytes
, tile_h
;
1393 iris_resource_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1395 *mask_x
= tile_w_bytes
/ cpp
- 1;
1396 *mask_y
= tile_h
- 1;
1400 * Compute the offset (in bytes) from the start of the BO to the given x
1401 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1402 * multiples of the tile size.
1405 iris_resource_get_aligned_offset(const struct iris_resource
*res
,
1406 uint32_t x
, uint32_t y
)
1408 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1409 unsigned cpp
= fmtl
->bpb
/ 8;
1410 uint32_t pitch
= res
->surf
.row_pitch_B
;
1412 switch (res
->surf
.tiling
) {
1414 unreachable("not reached");
1415 case ISL_TILING_LINEAR
:
1416 return y
* pitch
+ x
* cpp
;
1418 assert((x
% (512 / cpp
)) == 0);
1419 assert((y
% 8) == 0);
1420 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1422 assert((x
% (128 / cpp
)) == 0);
1423 assert((y
% 32) == 0);
1424 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1429 * Rendering with tiled buffers requires that the base address of the buffer
1430 * be aligned to a page boundary. For renderbuffers, and sometimes with
1431 * textures, we may want the surface to point at a texture image level that
1432 * isn't at a page boundary.
1434 * This function returns an appropriately-aligned base offset
1435 * according to the tiling restrictions, plus any required x/y offset
1439 iris_resource_get_tile_offsets(const struct iris_resource
*res
,
1440 uint32_t level
, uint32_t z
,
1441 uint32_t *tile_x
, uint32_t *tile_y
)
1444 uint32_t mask_x
, mask_y
;
1446 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1447 const unsigned cpp
= fmtl
->bpb
/ 8;
1449 iris_resource_get_tile_masks(res
->surf
.tiling
, cpp
, &mask_x
, &mask_y
);
1450 get_image_offset_el(&res
->surf
, level
, z
, &x
, &y
);
1452 *tile_x
= x
& mask_x
;
1453 *tile_y
= y
& mask_y
;
1455 return iris_resource_get_aligned_offset(res
, x
& ~mask_x
, y
& ~mask_y
);
1459 * Get pointer offset into stencil buffer.
1461 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1462 * must decode the tile's layout in software.
1465 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1467 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1469 * Even though the returned offset is always positive, the return type is
1471 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1472 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1475 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
)
1477 uint32_t tile_size
= 4096;
1478 uint32_t tile_width
= 64;
1479 uint32_t tile_height
= 64;
1480 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1482 uint32_t tile_x
= x
/ tile_width
;
1483 uint32_t tile_y
= y
/ tile_height
;
1485 /* The byte's address relative to the tile's base addres. */
1486 uint32_t byte_x
= x
% tile_width
;
1487 uint32_t byte_y
= y
% tile_height
;
1489 uintptr_t u
= tile_y
* row_size
1490 + tile_x
* tile_size
1491 + 512 * (byte_x
/ 8)
1493 + 32 * ((byte_y
/ 4) % 2)
1494 + 16 * ((byte_x
/ 4) % 2)
1495 + 8 * ((byte_y
/ 2) % 2)
1496 + 4 * ((byte_x
/ 2) % 2)
1504 iris_unmap_s8(struct iris_transfer
*map
)
1506 struct pipe_transfer
*xfer
= &map
->base
;
1507 const struct pipe_box
*box
= &xfer
->box
;
1508 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1509 struct isl_surf
*surf
= &res
->surf
;
1511 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1512 uint8_t *untiled_s8_map
= map
->ptr
;
1513 uint8_t *tiled_s8_map
=
1514 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1516 for (int s
= 0; s
< box
->depth
; s
++) {
1517 unsigned x0_el
, y0_el
;
1518 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1520 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1521 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1522 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1524 y0_el
+ box
->y
+ y
);
1525 tiled_s8_map
[offset
] =
1526 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1536 iris_map_s8(struct iris_transfer
*map
)
1538 struct pipe_transfer
*xfer
= &map
->base
;
1539 const struct pipe_box
*box
= &xfer
->box
;
1540 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1541 struct isl_surf
*surf
= &res
->surf
;
1543 xfer
->stride
= surf
->row_pitch_B
;
1544 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1546 /* The tiling and detiling functions require that the linear buffer has
1547 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1548 * over-allocate the linear buffer to get the proper alignment.
1550 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1551 assert(map
->buffer
);
1553 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1554 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1555 * invalidate is set, since we'll be writing the whole rectangle from our
1556 * temporary buffer back out.
1558 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1559 uint8_t *untiled_s8_map
= map
->ptr
;
1560 uint8_t *tiled_s8_map
=
1561 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1563 for (int s
= 0; s
< box
->depth
; s
++) {
1564 unsigned x0_el
, y0_el
;
1565 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1567 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1568 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1569 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1571 y0_el
+ box
->y
+ y
);
1572 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1573 tiled_s8_map
[offset
];
1579 map
->unmap
= iris_unmap_s8
;
1582 /* Compute extent parameters for use with tiled_memcpy functions.
1583 * xs are in units of bytes and ys are in units of strides.
1586 tile_extents(const struct isl_surf
*surf
,
1587 const struct pipe_box
*box
,
1588 unsigned level
, int z
,
1589 unsigned *x1_B
, unsigned *x2_B
,
1590 unsigned *y1_el
, unsigned *y2_el
)
1592 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1593 const unsigned cpp
= fmtl
->bpb
/ 8;
1595 assert(box
->x
% fmtl
->bw
== 0);
1596 assert(box
->y
% fmtl
->bh
== 0);
1598 unsigned x0_el
, y0_el
;
1599 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1601 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1602 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1603 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1604 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1608 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1610 struct pipe_transfer
*xfer
= &map
->base
;
1611 const struct pipe_box
*box
= &xfer
->box
;
1612 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1613 struct isl_surf
*surf
= &res
->surf
;
1615 const bool has_swizzling
= false;
1617 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1619 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1621 for (int s
= 0; s
< box
->depth
; s
++) {
1622 unsigned x1
, x2
, y1
, y2
;
1623 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1625 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1627 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1628 surf
->row_pitch_B
, xfer
->stride
,
1629 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1632 os_free_aligned(map
->buffer
);
1633 map
->buffer
= map
->ptr
= NULL
;
1637 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1639 struct pipe_transfer
*xfer
= &map
->base
;
1640 const struct pipe_box
*box
= &xfer
->box
;
1641 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1642 struct isl_surf
*surf
= &res
->surf
;
1644 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1645 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1647 unsigned x1
, x2
, y1
, y2
;
1648 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1650 /* The tiling and detiling functions require that the linear buffer has
1651 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1652 * over-allocate the linear buffer to get the proper alignment.
1655 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1656 assert(map
->buffer
);
1657 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1659 const bool has_swizzling
= false;
1661 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1663 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1665 for (int s
= 0; s
< box
->depth
; s
++) {
1666 unsigned x1
, x2
, y1
, y2
;
1667 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1669 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1670 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1672 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1673 surf
->row_pitch_B
, has_swizzling
,
1674 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1678 map
->unmap
= iris_unmap_tiled_memcpy
;
1682 iris_map_direct(struct iris_transfer
*map
)
1684 struct pipe_transfer
*xfer
= &map
->base
;
1685 struct pipe_box
*box
= &xfer
->box
;
1686 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1688 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1690 if (res
->base
.target
== PIPE_BUFFER
) {
1692 xfer
->layer_stride
= 0;
1694 map
->ptr
= ptr
+ box
->x
;
1696 struct isl_surf
*surf
= &res
->surf
;
1697 const struct isl_format_layout
*fmtl
=
1698 isl_format_get_layout(surf
->format
);
1699 const unsigned cpp
= fmtl
->bpb
/ 8;
1700 unsigned x0_el
, y0_el
;
1702 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1704 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1705 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1707 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1712 can_promote_to_async(const struct iris_resource
*res
,
1713 const struct pipe_box
*box
,
1714 enum pipe_transfer_usage usage
)
1716 /* If we're writing to a section of the buffer that hasn't even been
1717 * initialized with useful data, then we can safely promote this write
1718 * to be unsynchronized. This helps the common pattern of appending data.
1720 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1721 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1722 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1723 box
->x
+ box
->width
);
1727 iris_transfer_map(struct pipe_context
*ctx
,
1728 struct pipe_resource
*resource
,
1730 enum pipe_transfer_usage usage
,
1731 const struct pipe_box
*box
,
1732 struct pipe_transfer
**ptransfer
)
1734 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1735 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1736 struct isl_surf
*surf
= &res
->surf
;
1738 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1739 /* Replace the backing storage with a fresh buffer for non-async maps */
1740 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1741 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1742 iris_invalidate_resource(ctx
, resource
);
1744 /* If we can discard the whole resource, we can discard the range. */
1745 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1748 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1749 can_promote_to_async(res
, box
, usage
)) {
1750 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1753 bool need_resolve
= false;
1754 bool need_color_resolve
= false;
1756 if (resource
->target
!= PIPE_BUFFER
) {
1757 bool need_hiz_resolve
= iris_resource_level_has_hiz(res
, level
);
1759 need_color_resolve
=
1760 (res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
||
1761 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) &&
1762 iris_has_color_unresolved(res
, level
, 1, box
->z
, box
->depth
);
1764 need_resolve
= need_color_resolve
|| need_hiz_resolve
;
1767 bool map_would_stall
= false;
1769 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1770 map_would_stall
= need_resolve
|| resource_is_busy(ice
, res
);
1772 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1773 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1777 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1778 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1781 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1782 struct pipe_transfer
*xfer
= &map
->base
;
1787 memset(map
, 0, sizeof(*map
));
1788 map
->dbg
= &ice
->dbg
;
1790 pipe_resource_reference(&xfer
->resource
, resource
);
1791 xfer
->level
= level
;
1792 xfer
->usage
= usage
;
1796 map
->dest_had_defined_contents
=
1797 util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1798 box
->x
+ box
->width
);
1800 if (usage
& PIPE_TRANSFER_WRITE
)
1801 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1803 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1804 * there is to access them simultaneously on the CPU & GPU. This also
1805 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1806 * contain state we're constructing for a GPU draw call, which would
1807 * kill us with infinite stack recursion.
1809 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1810 PIPE_TRANSFER_COHERENT
|
1811 PIPE_TRANSFER_MAP_DIRECTLY
);
1813 /* GPU copies are not useful for buffer reads. Instead of stalling to
1814 * read from the original buffer, we'd simply copy it to a temporary...
1815 * then stall (a bit longer) to read from that buffer.
1817 * Images are less clear-cut. Color resolves are destructive, removing
1818 * the underlying compression, so we'd rather blit the data to a linear
1819 * temporary and map that, to avoid the resolve. (It might be better to
1820 * a tiled temporary and use the tiled_memcpy paths...)
1822 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) && !need_color_resolve
)
1825 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1826 if (fmtl
->txc
== ISL_TXC_ASTC
)
1829 if ((map_would_stall
|| res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) && !no_gpu
) {
1830 /* If we need a synchronous mapping and the resource is busy, or needs
1831 * resolving, we copy to/from a linear temporary buffer using the GPU.
1833 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1834 map
->blorp
= &ice
->blorp
;
1835 iris_map_copy_region(map
);
1837 /* Otherwise we're free to map on the CPU. */
1840 iris_resource_access_raw(ice
, &ice
->batches
[IRIS_BATCH_RENDER
], res
,
1841 level
, box
->z
, box
->depth
,
1842 usage
& PIPE_TRANSFER_WRITE
);
1845 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1846 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1847 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1848 iris_batch_flush(&ice
->batches
[i
]);
1852 if (surf
->tiling
== ISL_TILING_W
) {
1853 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1855 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1856 iris_map_tiled_memcpy(map
);
1858 iris_map_direct(map
);
1866 iris_transfer_flush_region(struct pipe_context
*ctx
,
1867 struct pipe_transfer
*xfer
,
1868 const struct pipe_box
*box
)
1870 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1871 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1872 struct iris_transfer
*map
= (void *) xfer
;
1875 iris_flush_staging_region(xfer
, box
);
1877 uint32_t history_flush
= 0;
1879 if (res
->base
.target
== PIPE_BUFFER
) {
1881 history_flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
1883 if (map
->dest_had_defined_contents
)
1884 history_flush
|= iris_flush_bits_for_history(res
);
1886 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1889 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
1890 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1891 struct iris_batch
*batch
= &ice
->batches
[i
];
1892 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
1893 iris_batch_maybe_flush(batch
, 24);
1894 iris_emit_pipe_control_flush(batch
,
1895 "cache history: transfer flush",
1901 /* Make sure we flag constants dirty even if there's no need to emit
1902 * any PIPE_CONTROLs to a batch.
1904 iris_dirty_for_history(ice
, res
);
1908 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1910 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1911 struct iris_transfer
*map
= (void *) xfer
;
1913 if (!(xfer
->usage
& (PIPE_TRANSFER_FLUSH_EXPLICIT
|
1914 PIPE_TRANSFER_COHERENT
))) {
1915 struct pipe_box flush_box
= {
1916 .x
= 0, .y
= 0, .z
= 0,
1917 .width
= xfer
->box
.width
,
1918 .height
= xfer
->box
.height
,
1919 .depth
= xfer
->box
.depth
,
1921 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
1927 pipe_resource_reference(&xfer
->resource
, NULL
);
1928 slab_free(&ice
->transfer_pool
, map
);
1932 * Mark state dirty that needs to be re-emitted when a resource is written.
1935 iris_dirty_for_history(struct iris_context
*ice
,
1936 struct iris_resource
*res
)
1938 uint64_t dirty
= 0ull;
1940 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1941 dirty
|= ((uint64_t)res
->bind_stages
) << IRIS_SHIFT_FOR_DIRTY_CONSTANTS
;
1944 ice
->state
.dirty
|= dirty
;
1948 * Produce a set of PIPE_CONTROL bits which ensure data written to a
1949 * resource becomes visible, and any stale read cache data is invalidated.
1952 iris_flush_bits_for_history(struct iris_resource
*res
)
1954 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
1956 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1957 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
1958 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1961 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
1962 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1964 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
1965 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1967 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
1968 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
1974 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
1975 struct iris_batch
*batch
,
1976 struct iris_resource
*res
,
1977 uint32_t extra_flags
,
1980 if (res
->base
.target
!= PIPE_BUFFER
)
1983 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
1985 iris_emit_pipe_control_flush(batch
, reason
, flush
);
1987 iris_dirty_for_history(ice
, res
);
1991 iris_resource_set_clear_color(struct iris_context
*ice
,
1992 struct iris_resource
*res
,
1993 union isl_color_value color
)
1995 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
1996 res
->aux
.clear_color
= color
;
2003 union isl_color_value
2004 iris_resource_get_clear_color(const struct iris_resource
*res
,
2005 struct iris_bo
**clear_color_bo
,
2006 uint64_t *clear_color_offset
)
2008 assert(res
->aux
.bo
);
2011 *clear_color_bo
= res
->aux
.clear_color_bo
;
2012 if (clear_color_offset
)
2013 *clear_color_offset
= res
->aux
.clear_color_offset
;
2014 return res
->aux
.clear_color
;
2017 static enum pipe_format
2018 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
2020 struct iris_resource
*res
= (void *) p_res
;
2021 return res
->internal_format
;
2024 static const struct u_transfer_vtbl transfer_vtbl
= {
2025 .resource_create
= iris_resource_create
,
2026 .resource_destroy
= iris_resource_destroy
,
2027 .transfer_map
= iris_transfer_map
,
2028 .transfer_unmap
= iris_transfer_unmap
,
2029 .transfer_flush_region
= iris_transfer_flush_region
,
2030 .get_internal_format
= iris_resource_get_internal_format
,
2031 .set_stencil
= iris_resource_set_separate_stencil
,
2032 .get_stencil
= iris_resource_get_separate_stencil
,
2036 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
2038 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
2039 pscreen
->resource_create_with_modifiers
=
2040 iris_resource_create_with_modifiers
;
2041 pscreen
->resource_create
= u_transfer_helper_resource_create
;
2042 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
2043 pscreen
->resource_from_handle
= iris_resource_from_handle
;
2044 pscreen
->resource_get_handle
= iris_resource_get_handle
;
2045 pscreen
->resource_get_param
= iris_resource_get_param
;
2046 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
2047 pscreen
->transfer_helper
=
2048 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
2052 iris_init_resource_functions(struct pipe_context
*ctx
)
2054 ctx
->flush_resource
= iris_flush_resource
;
2055 ctx
->invalidate_resource
= iris_invalidate_resource
;
2056 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
2057 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
2058 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
2059 ctx
->buffer_subdata
= u_default_buffer_subdata
;
2060 ctx
->texture_subdata
= u_default_texture_subdata
;