2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/dev/gen_debug.h"
52 #include "drm-uapi/drm_fourcc.h"
53 #include "drm-uapi/i915_drm.h"
55 enum modifier_priority
{
56 MODIFIER_PRIORITY_INVALID
= 0,
57 MODIFIER_PRIORITY_LINEAR
,
60 MODIFIER_PRIORITY_Y_CCS
,
63 static const uint64_t priority_to_modifier
[] = {
64 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
65 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
66 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
67 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
68 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
72 modifier_is_supported(const struct gen_device_info
*devinfo
,
75 /* XXX: do something real */
77 case I915_FORMAT_MOD_Y_TILED
:
78 case I915_FORMAT_MOD_X_TILED
:
79 case DRM_FORMAT_MOD_LINEAR
:
81 case I915_FORMAT_MOD_Y_TILED_CCS
:
82 case DRM_FORMAT_MOD_INVALID
:
89 select_best_modifier(struct gen_device_info
*devinfo
,
90 const uint64_t *modifiers
,
93 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
95 for (int i
= 0; i
< count
; i
++) {
96 if (!modifier_is_supported(devinfo
, modifiers
[i
]))
99 switch (modifiers
[i
]) {
100 case I915_FORMAT_MOD_Y_TILED_CCS
:
101 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
103 case I915_FORMAT_MOD_Y_TILED
:
104 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
106 case I915_FORMAT_MOD_X_TILED
:
107 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
109 case DRM_FORMAT_MOD_LINEAR
:
110 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
112 case DRM_FORMAT_MOD_INVALID
:
118 return priority_to_modifier
[prio
];
121 static enum isl_surf_dim
122 target_to_isl_surf_dim(enum pipe_texture_target target
)
126 case PIPE_TEXTURE_1D
:
127 case PIPE_TEXTURE_1D_ARRAY
:
128 return ISL_SURF_DIM_1D
;
129 case PIPE_TEXTURE_2D
:
130 case PIPE_TEXTURE_CUBE
:
131 case PIPE_TEXTURE_RECT
:
132 case PIPE_TEXTURE_2D_ARRAY
:
133 case PIPE_TEXTURE_CUBE_ARRAY
:
134 return ISL_SURF_DIM_2D
;
135 case PIPE_TEXTURE_3D
:
136 return ISL_SURF_DIM_3D
;
137 case PIPE_MAX_TEXTURE_TYPES
:
140 unreachable("invalid texture type");
144 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
145 enum pipe_format pfmt
,
148 unsigned int *external_only
,
151 struct iris_screen
*screen
= (void *) pscreen
;
152 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
154 uint64_t all_modifiers
[] = {
155 DRM_FORMAT_MOD_LINEAR
,
156 I915_FORMAT_MOD_X_TILED
,
157 I915_FORMAT_MOD_Y_TILED
,
158 // XXX: (broken) I915_FORMAT_MOD_Y_TILED_CCS,
161 int supported_mods
= 0;
163 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
164 if (!modifier_is_supported(devinfo
, all_modifiers
[i
]))
167 if (supported_mods
< max
) {
169 modifiers
[supported_mods
] = all_modifiers
[i
];
172 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
178 *count
= supported_mods
;
181 static isl_surf_usage_flags_t
182 pipe_bind_to_isl_usage(unsigned bindings
)
184 isl_surf_usage_flags_t usage
= 0;
186 if (bindings
& PIPE_BIND_RENDER_TARGET
)
187 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
189 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
190 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
192 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
193 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
195 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
196 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
201 struct pipe_resource
*
202 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
204 /* For packed depth-stencil, we treat depth as the primary resource
205 * and store S8 as the "second plane" resource.
211 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
212 struct pipe_resource
*stencil
)
214 assert(util_format_has_depth(util_format_description(p_res
->format
)));
215 pipe_resource_reference(&p_res
->next
, stencil
);
219 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
220 struct iris_resource
**out_z
,
221 struct iris_resource
**out_s
)
229 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
230 *out_z
= (void *) res
;
231 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
234 *out_s
= (void *) res
;
239 iris_resource_disable_aux(struct iris_resource
*res
)
241 iris_bo_unreference(res
->aux
.bo
);
242 iris_bo_unreference(res
->aux
.clear_color_bo
);
243 free(res
->aux
.state
);
245 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
246 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
247 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
248 res
->aux
.surf
.size_B
= 0;
250 res
->aux
.clear_color_bo
= NULL
;
251 res
->aux
.state
= NULL
;
255 iris_resource_destroy(struct pipe_screen
*screen
,
256 struct pipe_resource
*resource
)
258 struct iris_resource
*res
= (struct iris_resource
*)resource
;
260 if (resource
->target
== PIPE_BUFFER
)
261 util_range_destroy(&res
->valid_buffer_range
);
263 iris_resource_disable_aux(res
);
265 iris_bo_unreference(res
->bo
);
269 static struct iris_resource
*
270 iris_alloc_resource(struct pipe_screen
*pscreen
,
271 const struct pipe_resource
*templ
)
273 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
278 res
->base
.screen
= pscreen
;
279 pipe_reference_init(&res
->base
.reference
, 1);
281 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
282 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
284 if (templ
->target
== PIPE_BUFFER
)
285 util_range_init(&res
->valid_buffer_range
);
291 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
293 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
294 return minify(res
->surf
.logical_level0_px
.depth
, level
);
296 return res
->surf
.logical_level0_px
.array_len
;
299 static enum isl_aux_state
**
300 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
302 uint32_t total_slices
= 0;
303 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
304 total_slices
+= iris_get_num_logical_layers(res
, level
);
306 const size_t per_level_array_size
=
307 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
309 /* We're going to allocate a single chunk of data for both the per-level
310 * reference array and the arrays of aux_state. This makes cleanup
311 * significantly easier.
313 const size_t total_size
=
314 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
316 void *data
= malloc(total_size
);
320 enum isl_aux_state
**per_level_arr
= data
;
321 enum isl_aux_state
*s
= data
+ per_level_array_size
;
322 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
323 per_level_arr
[level
] = s
;
324 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
325 for (uint32_t a
= 0; a
< level_layers
; a
++)
328 assert((void *)s
== data
+ total_size
);
330 return per_level_arr
;
334 * Allocate the initial aux surface for a resource based on aux.usage
337 iris_resource_alloc_aux(struct iris_screen
*screen
, struct iris_resource
*res
)
339 struct isl_device
*isl_dev
= &screen
->isl_dev
;
340 enum isl_aux_state initial_state
;
341 UNUSED
bool ok
= false;
342 uint8_t memset_value
= 0;
343 uint32_t alloc_flags
= 0;
344 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
345 const unsigned clear_color_state_size
= devinfo
->gen
>= 10 ?
346 screen
->isl_dev
.ss
.clear_color_state_size
:
347 (devinfo
->gen
>= 9 ? screen
->isl_dev
.ss
.clear_value_size
: 0);
349 assert(!res
->aux
.bo
);
351 switch (res
->aux
.usage
) {
352 case ISL_AUX_USAGE_NONE
:
353 res
->aux
.surf
.size_B
= 0;
355 case ISL_AUX_USAGE_HIZ
:
356 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
358 ok
= isl_surf_get_hiz_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
360 case ISL_AUX_USAGE_MCS
:
361 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
363 * "When MCS buffer is enabled and bound to MSRT, it is required
364 * that it is cleared prior to any rendering."
366 * Since we only use the MCS buffer for rendering, we just clear it
367 * immediately on allocation. The clear value for MCS buffers is all
368 * 1's, so we simply memset it to 0xff.
370 initial_state
= ISL_AUX_STATE_CLEAR
;
372 ok
= isl_surf_get_mcs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
374 case ISL_AUX_USAGE_CCS_D
:
375 case ISL_AUX_USAGE_CCS_E
:
376 /* When CCS_E is used, we need to ensure that the CCS starts off in
377 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
380 * "If Software wants to enable Color Compression without Fast
381 * clear, Software needs to initialize MCS with zeros."
383 * A CCS value of 0 indicates that the corresponding block is in the
384 * pass-through state which is what we want.
386 * For CCS_D, do the same thing. On Gen9+, this avoids having any
387 * undefined bits in the aux buffer.
389 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
390 alloc_flags
|= BO_ALLOC_ZEROED
;
391 ok
= isl_surf_get_ccs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
, 0);
395 /* No work is needed for a zero-sized auxiliary buffer. */
396 if (res
->aux
.surf
.size_B
== 0)
399 /* Assert that ISL gave us a valid aux surf */
402 /* Create the aux_state for the auxiliary buffer. */
403 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
407 uint64_t size
= res
->aux
.surf
.size_B
;
409 /* Allocate space in the buffer for storing the clear color. On modern
410 * platforms (gen > 9), we can read it directly from such buffer.
412 * On gen <= 9, we are going to store the clear color on the buffer
413 * anyways, and copy it back to the surface state during state emission.
415 res
->aux
.clear_color_offset
= size
;
416 size
+= clear_color_state_size
;
418 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
419 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
420 * of bytes instead of trying to recalculate based on different format
423 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
,
424 IRIS_MEMZONE_OTHER
, I915_TILING_Y
,
425 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
430 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
431 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
434 iris_resource_disable_aux(res
);
438 if (memset_value
!= 0)
439 memset(map
, memset_value
, res
->aux
.surf
.size_B
);
441 /* Zero the indirect clear color to match ::fast_clear_color. */
442 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
443 clear_color_state_size
);
445 iris_bo_unmap(res
->aux
.bo
);
448 if (clear_color_state_size
> 0) {
449 res
->aux
.clear_color_bo
= res
->aux
.bo
;
450 iris_bo_reference(res
->aux
.clear_color_bo
);
453 if (res
->aux
.usage
== ISL_AUX_USAGE_HIZ
) {
454 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
455 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
456 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
458 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
459 * For LOD == 0, we can grow the dimensions to make it work.
461 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
462 res
->aux
.has_hiz
|= 1 << level
;
470 supports_mcs(const struct isl_surf
*surf
)
472 /* MCS compression only applies to multisampled resources. */
473 if (surf
->samples
<= 1)
476 /* See isl_surf_get_mcs_surf for details. */
477 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
480 /* Depth and stencil buffers use the IMS (interleaved) layout. */
481 if (isl_surf_usage_is_depth_or_stencil(surf
->usage
))
488 supports_ccs(const struct gen_device_info
*devinfo
,
489 const struct isl_surf
*surf
)
491 /* Gen9+ only supports CCS for Y-tiled buffers. */
492 if (surf
->tiling
!= ISL_TILING_Y0
)
495 /* CCS only supports singlesampled resources. */
496 if (surf
->samples
> 1)
499 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
500 * work for 3D textures until Gen9 where the layout of 3D textures changes
501 * to match 2D array textures.
503 if (devinfo
->gen
< 9 && surf
->dim
!= ISL_SURF_DIM_2D
)
506 /* Note: still need to check the format! */
511 static struct pipe_resource
*
512 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
513 const struct pipe_resource
*templ
)
515 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
516 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
518 assert(templ
->target
== PIPE_BUFFER
);
519 assert(templ
->height0
<= 1);
520 assert(templ
->depth0
<= 1);
521 assert(templ
->format
== PIPE_FORMAT_NONE
||
522 util_format_get_blocksize(templ
->format
) == 1);
524 res
->internal_format
= templ
->format
;
525 res
->surf
.tiling
= ISL_TILING_LINEAR
;
527 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
528 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
529 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
530 memzone
= IRIS_MEMZONE_SHADER
;
531 name
= "shader kernels";
532 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
533 memzone
= IRIS_MEMZONE_SURFACE
;
534 name
= "surface state";
535 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
536 memzone
= IRIS_MEMZONE_DYNAMIC
;
537 name
= "dynamic state";
540 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
542 iris_resource_destroy(pscreen
, &res
->base
);
549 static struct pipe_resource
*
550 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
551 const struct pipe_resource
*templ
,
552 const uint64_t *modifiers
,
555 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
556 struct gen_device_info
*devinfo
= &screen
->devinfo
;
557 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
562 const struct util_format_description
*format_desc
=
563 util_format_description(templ
->format
);
564 const bool has_depth
= util_format_has_depth(format_desc
);
566 select_best_modifier(devinfo
, modifiers
, modifiers_count
);
568 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
570 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
571 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
573 tiling_flags
= 1 << res
->mod_info
->tiling
;
575 if (modifiers_count
> 0) {
576 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
580 /* No modifiers - we can select our own tiling. */
583 /* Depth must be Y-tiled */
584 tiling_flags
= ISL_TILING_Y0_BIT
;
585 } else if (templ
->format
== PIPE_FORMAT_S8_UINT
) {
586 /* Stencil must be W-tiled */
587 tiling_flags
= ISL_TILING_W_BIT
;
588 } else if (templ
->target
== PIPE_BUFFER
||
589 templ
->target
== PIPE_TEXTURE_1D
||
590 templ
->target
== PIPE_TEXTURE_1D_ARRAY
) {
591 /* Use linear for buffers and 1D textures */
592 tiling_flags
= ISL_TILING_LINEAR_BIT
;
595 /* Use linear for staging buffers */
596 if (templ
->usage
== PIPE_USAGE_STAGING
||
597 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
598 tiling_flags
= ISL_TILING_LINEAR_BIT
;
601 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
603 if (templ
->target
== PIPE_TEXTURE_CUBE
||
604 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
605 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
607 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
608 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
609 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
611 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
614 enum pipe_format pfmt
= templ
->format
;
615 res
->internal_format
= pfmt
;
617 /* Should be handled by u_transfer_helper */
618 assert(!util_format_is_depth_and_stencil(pfmt
));
620 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
621 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
623 UNUSED
const bool isl_surf_created_successfully
=
624 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
625 .dim
= target_to_isl_surf_dim(templ
->target
),
627 .width
= templ
->width0
,
628 .height
= templ
->height0
,
629 .depth
= templ
->depth0
,
630 .levels
= templ
->last_level
+ 1,
631 .array_len
= templ
->array_size
,
632 .samples
= MAX2(templ
->nr_samples
, 1),
633 .min_alignment_B
= 0,
636 .tiling_flags
= tiling_flags
);
637 assert(isl_surf_created_successfully
);
640 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
641 } else if (supports_mcs(&res
->surf
)) {
642 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_MCS
;
643 } else if (has_depth
) {
644 if (likely(!(INTEL_DEBUG
& DEBUG_NO_HIZ
)))
645 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
646 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO_RBC
)) &&
647 supports_ccs(devinfo
, &res
->surf
)) {
648 if (isl_format_supports_ccs_e(devinfo
, res
->surf
.format
))
649 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
651 if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
652 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
655 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
657 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
659 /* We don't always support sampling with hiz. But when we do, it must be
662 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1) {
663 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
666 const char *name
= "miptree";
667 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
669 unsigned int flags
= 0;
670 if (templ
->usage
== PIPE_USAGE_STAGING
)
671 flags
|= BO_ALLOC_COHERENT
;
673 /* These are for u_upload_mgr buffers only */
674 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
675 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
676 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
678 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, res
->surf
.size_B
,
680 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
681 res
->surf
.row_pitch_B
, flags
);
686 if (!iris_resource_alloc_aux(screen
, res
))
692 fprintf(stderr
, "XXX: resource creation failed\n");
693 iris_resource_destroy(pscreen
, &res
->base
);
698 static struct pipe_resource
*
699 iris_resource_create(struct pipe_screen
*pscreen
,
700 const struct pipe_resource
*templ
)
702 if (templ
->target
== PIPE_BUFFER
)
703 return iris_resource_create_for_buffer(pscreen
, templ
);
705 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
709 tiling_to_modifier(uint32_t tiling
)
711 static const uint64_t map
[] = {
712 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
713 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
714 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
717 assert(tiling
< ARRAY_SIZE(map
));
722 static struct pipe_resource
*
723 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
724 const struct pipe_resource
*templ
,
727 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
728 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
729 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
733 assert(templ
->target
== PIPE_BUFFER
);
735 res
->internal_format
= templ
->format
;
736 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
737 user_memory
, templ
->width0
,
744 util_range_add(&res
->valid_buffer_range
, 0, templ
->width0
);
749 static struct pipe_resource
*
750 iris_resource_from_handle(struct pipe_screen
*pscreen
,
751 const struct pipe_resource
*templ
,
752 struct winsys_handle
*whandle
,
755 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
756 struct gen_device_info
*devinfo
= &screen
->devinfo
;
757 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
758 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
762 if (whandle
->offset
!= 0) {
763 dbg_printf("Attempt to import unsupported winsys offset %u\n",
768 switch (whandle
->type
) {
769 case WINSYS_HANDLE_TYPE_FD
:
770 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
);
772 case WINSYS_HANDLE_TYPE_SHARED
:
773 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
777 unreachable("invalid winsys handle type");
782 uint64_t modifier
= whandle
->modifier
;
783 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
784 modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
786 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
787 assert(res
->mod_info
);
789 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
791 const struct iris_format_info fmt
=
792 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
793 res
->internal_format
= templ
->format
;
795 if (templ
->target
== PIPE_BUFFER
) {
796 res
->surf
.tiling
= ISL_TILING_LINEAR
;
798 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
799 .dim
= target_to_isl_surf_dim(templ
->target
),
801 .width
= templ
->width0
,
802 .height
= templ
->height0
,
803 .depth
= templ
->depth0
,
804 .levels
= templ
->last_level
+ 1,
805 .array_len
= templ
->array_size
,
806 .samples
= MAX2(templ
->nr_samples
, 1),
807 .min_alignment_B
= 0,
808 .row_pitch_B
= whandle
->stride
,
810 .tiling_flags
= 1 << res
->mod_info
->tiling
);
812 assert(res
->bo
->tiling_mode
==
813 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
815 // XXX: create_ccs_buf_for_image?
816 if (!iris_resource_alloc_aux(screen
, res
))
823 iris_resource_destroy(pscreen
, &res
->base
);
828 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
830 struct iris_context
*ice
= (struct iris_context
*)ctx
;
831 struct iris_batch
*render_batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
832 struct iris_resource
*res
= (void *) resource
;
833 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
835 iris_resource_prepare_access(ice
, render_batch
, res
,
836 0, INTEL_REMAINING_LEVELS
,
837 0, INTEL_REMAINING_LAYERS
,
838 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
839 mod
? mod
->supports_clear_color
: false);
843 iris_resource_get_handle(struct pipe_screen
*pscreen
,
844 struct pipe_context
*ctx
,
845 struct pipe_resource
*resource
,
846 struct winsys_handle
*whandle
,
849 struct iris_resource
*res
= (struct iris_resource
*)resource
;
851 /* Disable aux usage if explicit flush not set and this is the
852 * first time we are dealing with this resource.
854 if ((!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0)) {
855 if (p_atomic_read(&resource
->reference
.count
) == 1)
856 iris_resource_disable_aux(res
);
859 /* If this is a buffer, stride should be 0 - no need to special case */
860 whandle
->stride
= res
->surf
.row_pitch_B
;
862 res
->mod_info
? res
->mod_info
->modifier
863 : tiling_to_modifier(res
->bo
->tiling_mode
);
866 enum isl_aux_usage allowed_usage
=
867 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
869 if (res
->aux
.usage
!= allowed_usage
) {
870 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
871 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
872 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
876 switch (whandle
->type
) {
877 case WINSYS_HANDLE_TYPE_SHARED
:
878 return iris_bo_flink(res
->bo
, &whandle
->handle
) == 0;
879 case WINSYS_HANDLE_TYPE_KMS
:
880 whandle
->handle
= iris_bo_export_gem_handle(res
->bo
);
882 case WINSYS_HANDLE_TYPE_FD
:
883 return iris_bo_export_dmabuf(res
->bo
, (int *) &whandle
->handle
) == 0;
890 resource_is_busy(struct iris_context
*ice
,
891 struct iris_resource
*res
)
893 bool busy
= iris_bo_busy(res
->bo
);
895 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
896 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
902 iris_invalidate_resource(struct pipe_context
*ctx
,
903 struct pipe_resource
*resource
)
905 struct iris_screen
*screen
= (void *) ctx
->screen
;
906 struct iris_context
*ice
= (void *) ctx
;
907 struct iris_resource
*res
= (void *) resource
;
909 if (resource
->target
!= PIPE_BUFFER
)
912 if (!resource_is_busy(ice
, res
)) {
913 /* The resource is idle, so just mark that it contains no data and
914 * keep using the same underlying buffer object.
916 util_range_set_empty(&res
->valid_buffer_range
);
920 /* Otherwise, try and replace the backing storage with a new BO. */
922 /* We can't reallocate memory we didn't allocate in the first place. */
923 if (res
->bo
->userptr
)
926 // XXX: We should support this.
927 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
930 struct iris_bo
*old_bo
= res
->bo
;
931 struct iris_bo
*new_bo
=
932 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
933 iris_memzone_for_address(old_bo
->gtt_offset
));
937 /* Swap out the backing storage */
940 /* Rebind the buffer, replacing any state referring to the old BO's
941 * address, and marking state dirty so it's reemitted.
943 ice
->vtbl
.rebind_buffer(ice
, res
, old_bo
->gtt_offset
);
945 util_range_set_empty(&res
->valid_buffer_range
);
947 iris_bo_unreference(old_bo
);
951 iris_flush_staging_region(struct pipe_transfer
*xfer
,
952 const struct pipe_box
*flush_box
)
954 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
957 struct iris_transfer
*map
= (void *) xfer
;
959 struct pipe_box src_box
= *flush_box
;
961 /* Account for extra alignment padding in staging buffer */
962 if (xfer
->resource
->target
== PIPE_BUFFER
)
963 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
965 struct pipe_box dst_box
= (struct pipe_box
) {
966 .x
= xfer
->box
.x
+ flush_box
->x
,
967 .y
= xfer
->box
.y
+ flush_box
->y
,
968 .z
= xfer
->box
.z
+ flush_box
->z
,
969 .width
= flush_box
->width
,
970 .height
= flush_box
->height
,
971 .depth
= flush_box
->depth
,
974 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
975 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
980 iris_unmap_copy_region(struct iris_transfer
*map
)
982 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
988 iris_map_copy_region(struct iris_transfer
*map
)
990 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
991 struct pipe_transfer
*xfer
= &map
->base
;
992 struct pipe_box
*box
= &xfer
->box
;
993 struct iris_resource
*res
= (void *) xfer
->resource
;
995 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
996 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
998 struct pipe_resource templ
= (struct pipe_resource
) {
999 .usage
= PIPE_USAGE_STAGING
,
1000 .width0
= box
->width
+ extra
,
1001 .height0
= box
->height
,
1003 .nr_samples
= xfer
->resource
->nr_samples
,
1004 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1005 .array_size
= box
->depth
,
1008 if (xfer
->resource
->target
== PIPE_BUFFER
)
1009 templ
.target
= PIPE_BUFFER
;
1010 else if (templ
.array_size
> 1)
1011 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1013 templ
.target
= PIPE_TEXTURE_2D
;
1015 /* Depth, stencil, and ASTC can't be linear surfaces, so we can't use
1016 * xfer->resource->format directly. Pick a bpb compatible format so
1017 * resource creation will succeed; blorp_copy will override it anyway.
1019 switch (util_format_get_blocksizebits(res
->internal_format
)) {
1020 case 8: templ
.format
= PIPE_FORMAT_R8_UINT
; break;
1021 case 16: templ
.format
= PIPE_FORMAT_R8G8_UINT
; break;
1022 case 24: templ
.format
= PIPE_FORMAT_R8G8B8_UINT
; break;
1023 case 32: templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
; break;
1024 case 48: templ
.format
= PIPE_FORMAT_R16G16B16_UINT
; break;
1025 case 64: templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
; break;
1026 case 96: templ
.format
= PIPE_FORMAT_R32G32B32_UINT
; break;
1027 case 128: templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
; break;
1028 default: unreachable("Invalid bpb");
1031 map
->staging
= iris_resource_create(pscreen
, &templ
);
1032 assert(map
->staging
);
1034 if (templ
.target
!= PIPE_BUFFER
) {
1035 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1036 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1037 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1040 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1041 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1042 xfer
->resource
, xfer
->level
, box
);
1043 /* Ensure writes to the staging BO land before we map it below. */
1044 iris_emit_pipe_control_flush(map
->batch
,
1045 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1046 PIPE_CONTROL_CS_STALL
);
1049 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1051 if (iris_batch_references(map
->batch
, staging_bo
))
1052 iris_batch_flush(map
->batch
);
1055 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1057 map
->unmap
= iris_unmap_copy_region
;
1061 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1062 unsigned *out_x0_el
, unsigned *out_y0_el
)
1064 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1065 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1067 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1072 * Get pointer offset into stencil buffer.
1074 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1075 * must decode the tile's layout in software.
1078 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1080 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1082 * Even though the returned offset is always positive, the return type is
1084 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1085 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1088 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1090 uint32_t tile_size
= 4096;
1091 uint32_t tile_width
= 64;
1092 uint32_t tile_height
= 64;
1093 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1095 uint32_t tile_x
= x
/ tile_width
;
1096 uint32_t tile_y
= y
/ tile_height
;
1098 /* The byte's address relative to the tile's base addres. */
1099 uint32_t byte_x
= x
% tile_width
;
1100 uint32_t byte_y
= y
% tile_height
;
1102 uintptr_t u
= tile_y
* row_size
1103 + tile_x
* tile_size
1104 + 512 * (byte_x
/ 8)
1106 + 32 * ((byte_y
/ 4) % 2)
1107 + 16 * ((byte_x
/ 4) % 2)
1108 + 8 * ((byte_y
/ 2) % 2)
1109 + 4 * ((byte_x
/ 2) % 2)
1114 /* adjust for bit6 swizzling */
1115 if (((byte_x
/ 8) % 2) == 1) {
1116 if (((byte_y
/ 8) % 2) == 0) {
1128 iris_unmap_s8(struct iris_transfer
*map
)
1130 struct pipe_transfer
*xfer
= &map
->base
;
1131 const struct pipe_box
*box
= &xfer
->box
;
1132 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1133 struct isl_surf
*surf
= &res
->surf
;
1134 const bool has_swizzling
= false;
1136 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1137 uint8_t *untiled_s8_map
= map
->ptr
;
1138 uint8_t *tiled_s8_map
=
1139 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1141 for (int s
= 0; s
< box
->depth
; s
++) {
1142 unsigned x0_el
, y0_el
;
1143 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1145 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1146 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1147 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1151 tiled_s8_map
[offset
] =
1152 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1162 iris_map_s8(struct iris_transfer
*map
)
1164 struct pipe_transfer
*xfer
= &map
->base
;
1165 const struct pipe_box
*box
= &xfer
->box
;
1166 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1167 struct isl_surf
*surf
= &res
->surf
;
1169 xfer
->stride
= surf
->row_pitch_B
;
1170 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1172 /* The tiling and detiling functions require that the linear buffer has
1173 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1174 * over-allocate the linear buffer to get the proper alignment.
1176 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1177 assert(map
->buffer
);
1179 const bool has_swizzling
= false;
1181 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1182 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1183 * invalidate is set, since we'll be writing the whole rectangle from our
1184 * temporary buffer back out.
1186 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1187 uint8_t *untiled_s8_map
= map
->ptr
;
1188 uint8_t *tiled_s8_map
=
1189 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1191 for (int s
= 0; s
< box
->depth
; s
++) {
1192 unsigned x0_el
, y0_el
;
1193 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1195 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1196 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1197 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1201 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1202 tiled_s8_map
[offset
];
1208 map
->unmap
= iris_unmap_s8
;
1211 /* Compute extent parameters for use with tiled_memcpy functions.
1212 * xs are in units of bytes and ys are in units of strides.
1215 tile_extents(const struct isl_surf
*surf
,
1216 const struct pipe_box
*box
,
1217 unsigned level
, int z
,
1218 unsigned *x1_B
, unsigned *x2_B
,
1219 unsigned *y1_el
, unsigned *y2_el
)
1221 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1222 const unsigned cpp
= fmtl
->bpb
/ 8;
1224 assert(box
->x
% fmtl
->bw
== 0);
1225 assert(box
->y
% fmtl
->bh
== 0);
1227 unsigned x0_el
, y0_el
;
1228 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1230 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1231 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1232 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1233 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1237 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1239 struct pipe_transfer
*xfer
= &map
->base
;
1240 const struct pipe_box
*box
= &xfer
->box
;
1241 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1242 struct isl_surf
*surf
= &res
->surf
;
1244 const bool has_swizzling
= false;
1246 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1248 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1250 for (int s
= 0; s
< box
->depth
; s
++) {
1251 unsigned x1
, x2
, y1
, y2
;
1252 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1254 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1256 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1257 surf
->row_pitch_B
, xfer
->stride
,
1258 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1261 os_free_aligned(map
->buffer
);
1262 map
->buffer
= map
->ptr
= NULL
;
1266 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1268 struct pipe_transfer
*xfer
= &map
->base
;
1269 const struct pipe_box
*box
= &xfer
->box
;
1270 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1271 struct isl_surf
*surf
= &res
->surf
;
1273 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1274 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1276 unsigned x1
, x2
, y1
, y2
;
1277 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1279 /* The tiling and detiling functions require that the linear buffer has
1280 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1281 * over-allocate the linear buffer to get the proper alignment.
1284 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1285 assert(map
->buffer
);
1286 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1288 const bool has_swizzling
= false;
1290 // XXX: PIPE_TRANSFER_READ?
1291 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1293 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1295 for (int s
= 0; s
< box
->depth
; s
++) {
1296 unsigned x1
, x2
, y1
, y2
;
1297 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1299 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1300 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1302 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1303 surf
->row_pitch_B
, has_swizzling
,
1304 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1308 map
->unmap
= iris_unmap_tiled_memcpy
;
1312 iris_map_direct(struct iris_transfer
*map
)
1314 struct pipe_transfer
*xfer
= &map
->base
;
1315 struct pipe_box
*box
= &xfer
->box
;
1316 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1318 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1320 if (res
->base
.target
== PIPE_BUFFER
) {
1322 xfer
->layer_stride
= 0;
1324 map
->ptr
= ptr
+ box
->x
;
1326 struct isl_surf
*surf
= &res
->surf
;
1327 const struct isl_format_layout
*fmtl
=
1328 isl_format_get_layout(surf
->format
);
1329 const unsigned cpp
= fmtl
->bpb
/ 8;
1330 unsigned x0_el
, y0_el
;
1332 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1334 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1335 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1337 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1342 can_promote_to_async(const struct iris_resource
*res
,
1343 const struct pipe_box
*box
,
1344 enum pipe_transfer_usage usage
)
1346 /* If we're writing to a section of the buffer that hasn't even been
1347 * initialized with useful data, then we can safely promote this write
1348 * to be unsynchronized. This helps the common pattern of appending data.
1350 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1351 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1352 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1353 box
->x
+ box
->width
);
1357 iris_transfer_map(struct pipe_context
*ctx
,
1358 struct pipe_resource
*resource
,
1360 enum pipe_transfer_usage usage
,
1361 const struct pipe_box
*box
,
1362 struct pipe_transfer
**ptransfer
)
1364 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1365 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1366 struct isl_surf
*surf
= &res
->surf
;
1368 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1369 /* Replace the backing storage with a fresh buffer for non-async maps */
1370 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1371 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1372 iris_invalidate_resource(ctx
, resource
);
1374 /* If we can discard the whole resource, we can discard the range. */
1375 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1378 bool map_would_stall
= false;
1380 if (resource
->target
!= PIPE_BUFFER
) {
1381 iris_resource_access_raw(ice
, &ice
->batches
[IRIS_BATCH_RENDER
], res
,
1382 level
, box
->z
, box
->depth
,
1383 usage
& PIPE_TRANSFER_WRITE
);
1386 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1387 can_promote_to_async(res
, box
, usage
)) {
1388 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1391 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1392 map_would_stall
= resource_is_busy(ice
, res
);
1394 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1395 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1399 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1400 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1403 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1404 struct pipe_transfer
*xfer
= &map
->base
;
1409 memset(map
, 0, sizeof(*map
));
1410 map
->dbg
= &ice
->dbg
;
1412 pipe_resource_reference(&xfer
->resource
, resource
);
1413 xfer
->level
= level
;
1414 xfer
->usage
= usage
;
1418 if (usage
& PIPE_TRANSFER_WRITE
)
1419 util_range_add(&res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1421 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1422 * there is to access them simultaneously on the CPU & GPU. This also
1423 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1424 * contain state we're constructing for a GPU draw call, which would
1425 * kill us with infinite stack recursion.
1427 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1428 PIPE_TRANSFER_COHERENT
|
1429 PIPE_TRANSFER_MAP_DIRECTLY
);
1431 /* GPU copies are not useful for buffer reads. Instead of stalling to
1432 * read from the original buffer, we'd simply copy it to a temporary...
1433 * then stall (a bit longer) to read from that buffer.
1435 * Images are less clear-cut. Color resolves are destructive, removing
1436 * the underlying compression, so we'd rather blit the data to a linear
1437 * temporary and map that, to avoid the resolve. (It might be better to
1438 * a tiled temporary and use the tiled_memcpy paths...)
1440 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) &&
1441 res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
&&
1442 res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
) {
1446 if ((map_would_stall
|| res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) && !no_gpu
) {
1447 /* If we need a synchronous mapping and the resource is busy,
1448 * we copy to/from a linear temporary buffer using the GPU.
1450 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1451 map
->blorp
= &ice
->blorp
;
1452 iris_map_copy_region(map
);
1454 /* Otherwise we're free to map on the CPU. Flush if needed. */
1455 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1456 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1457 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1458 iris_batch_flush(&ice
->batches
[i
]);
1462 if (surf
->tiling
== ISL_TILING_W
) {
1463 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1465 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1466 iris_map_tiled_memcpy(map
);
1468 iris_map_direct(map
);
1476 iris_transfer_flush_region(struct pipe_context
*ctx
,
1477 struct pipe_transfer
*xfer
,
1478 const struct pipe_box
*box
)
1480 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1481 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1482 struct iris_transfer
*map
= (void *) xfer
;
1485 iris_flush_staging_region(xfer
, box
);
1487 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1488 if (ice
->batches
[i
].contains_draw
||
1489 ice
->batches
[i
].cache
.render
->entries
) {
1490 iris_batch_maybe_flush(&ice
->batches
[i
], 24);
1491 iris_flush_and_dirty_for_history(ice
, &ice
->batches
[i
], res
);
1495 /* Make sure we flag constants dirty even if there's no need to emit
1496 * any PIPE_CONTROLs to a batch.
1498 iris_flush_and_dirty_for_history(ice
, NULL
, res
);
1502 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1504 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1505 struct iris_transfer
*map
= (void *) xfer
;
1507 if (!(xfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
)) {
1508 struct pipe_box flush_box
= {
1509 .x
= 0, .y
= 0, .z
= 0,
1510 .width
= xfer
->box
.width
,
1511 .height
= xfer
->box
.height
,
1512 .depth
= xfer
->box
.depth
,
1514 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
1520 pipe_resource_reference(&xfer
->resource
, NULL
);
1521 slab_free(&ice
->transfer_pool
, map
);
1525 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
1526 struct iris_batch
*batch
,
1527 struct iris_resource
*res
)
1529 if (res
->base
.target
!= PIPE_BUFFER
)
1532 unsigned flush
= PIPE_CONTROL_CS_STALL
;
1534 /* We've likely used the rendering engine (i.e. BLORP) to write to this
1535 * surface. Flush the render cache so the data actually lands.
1537 if (batch
&& batch
->name
!= IRIS_BATCH_COMPUTE
)
1538 flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
1540 uint64_t dirty
= 0ull;
1542 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1543 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
1544 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1545 dirty
|= IRIS_DIRTY_CONSTANTS_VS
|
1546 IRIS_DIRTY_CONSTANTS_TCS
|
1547 IRIS_DIRTY_CONSTANTS_TES
|
1548 IRIS_DIRTY_CONSTANTS_GS
|
1549 IRIS_DIRTY_CONSTANTS_FS
|
1550 IRIS_DIRTY_CONSTANTS_CS
|
1551 IRIS_ALL_DIRTY_BINDINGS
;
1554 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
1555 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1557 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
1558 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1560 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
1561 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
1564 iris_emit_pipe_control_flush(batch
, flush
);
1566 ice
->state
.dirty
|= dirty
;
1570 iris_resource_set_clear_color(struct iris_context
*ice
,
1571 struct iris_resource
*res
,
1572 union isl_color_value color
)
1574 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
1575 res
->aux
.clear_color
= color
;
1582 union isl_color_value
1583 iris_resource_get_clear_color(const struct iris_resource
*res
,
1584 struct iris_bo
**clear_color_bo
,
1585 uint64_t *clear_color_offset
)
1587 assert(res
->aux
.bo
);
1590 *clear_color_bo
= res
->aux
.clear_color_bo
;
1591 if (clear_color_offset
)
1592 *clear_color_offset
= res
->aux
.clear_color_offset
;
1593 return res
->aux
.clear_color
;
1596 static enum pipe_format
1597 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
1599 struct iris_resource
*res
= (void *) p_res
;
1600 return res
->internal_format
;
1603 static const struct u_transfer_vtbl transfer_vtbl
= {
1604 .resource_create
= iris_resource_create
,
1605 .resource_destroy
= iris_resource_destroy
,
1606 .transfer_map
= iris_transfer_map
,
1607 .transfer_unmap
= iris_transfer_unmap
,
1608 .transfer_flush_region
= iris_transfer_flush_region
,
1609 .get_internal_format
= iris_resource_get_internal_format
,
1610 .set_stencil
= iris_resource_set_separate_stencil
,
1611 .get_stencil
= iris_resource_get_separate_stencil
,
1615 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
1617 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
1618 pscreen
->resource_create_with_modifiers
=
1619 iris_resource_create_with_modifiers
;
1620 pscreen
->resource_create
= u_transfer_helper_resource_create
;
1621 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
1622 pscreen
->resource_from_handle
= iris_resource_from_handle
;
1623 pscreen
->resource_get_handle
= iris_resource_get_handle
;
1624 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
1625 pscreen
->transfer_helper
=
1626 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
1630 iris_init_resource_functions(struct pipe_context
*ctx
)
1632 ctx
->flush_resource
= iris_flush_resource
;
1633 ctx
->invalidate_resource
= iris_invalidate_resource
;
1634 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
1635 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
1636 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
1637 ctx
->buffer_subdata
= u_default_buffer_subdata
;
1638 ctx
->texture_subdata
= u_default_texture_subdata
;