2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_transfer.h"
42 #include "util/u_transfer_helper.h"
43 #include "util/u_upload_mgr.h"
44 #include "util/ralloc.h"
45 #include "iris_batch.h"
46 #include "iris_context.h"
47 #include "iris_resource.h"
48 #include "iris_screen.h"
49 #include "intel/common/gen_debug.h"
51 #include "drm-uapi/drm_fourcc.h"
52 #include "drm-uapi/i915_drm.h"
54 enum modifier_priority
{
55 MODIFIER_PRIORITY_INVALID
= 0,
56 MODIFIER_PRIORITY_LINEAR
,
59 MODIFIER_PRIORITY_Y_CCS
,
62 static const uint64_t priority_to_modifier
[] = {
63 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
64 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
65 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
66 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
67 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
71 modifier_is_supported(const struct gen_device_info
*devinfo
,
74 /* XXX: do something real */
76 case I915_FORMAT_MOD_Y_TILED
:
77 case I915_FORMAT_MOD_X_TILED
:
78 case DRM_FORMAT_MOD_LINEAR
:
80 case I915_FORMAT_MOD_Y_TILED_CCS
:
81 case DRM_FORMAT_MOD_INVALID
:
88 select_best_modifier(struct gen_device_info
*devinfo
,
89 const uint64_t *modifiers
,
92 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
94 for (int i
= 0; i
< count
; i
++) {
95 if (!modifier_is_supported(devinfo
, modifiers
[i
]))
98 switch (modifiers
[i
]) {
99 case I915_FORMAT_MOD_Y_TILED_CCS
:
100 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
102 case I915_FORMAT_MOD_Y_TILED
:
103 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
105 case I915_FORMAT_MOD_X_TILED
:
106 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
108 case DRM_FORMAT_MOD_LINEAR
:
109 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
111 case DRM_FORMAT_MOD_INVALID
:
117 return priority_to_modifier
[prio
];
120 static enum isl_surf_dim
121 target_to_isl_surf_dim(enum pipe_texture_target target
)
125 case PIPE_TEXTURE_1D
:
126 case PIPE_TEXTURE_1D_ARRAY
:
127 return ISL_SURF_DIM_1D
;
128 case PIPE_TEXTURE_2D
:
129 case PIPE_TEXTURE_CUBE
:
130 case PIPE_TEXTURE_RECT
:
131 case PIPE_TEXTURE_2D_ARRAY
:
132 case PIPE_TEXTURE_CUBE_ARRAY
:
133 return ISL_SURF_DIM_2D
;
134 case PIPE_TEXTURE_3D
:
135 return ISL_SURF_DIM_3D
;
136 case PIPE_MAX_TEXTURE_TYPES
:
139 unreachable("invalid texture type");
142 static isl_surf_usage_flags_t
143 pipe_bind_to_isl_usage(unsigned bindings
)
145 isl_surf_usage_flags_t usage
= 0;
147 if (bindings
& PIPE_BIND_RENDER_TARGET
)
148 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
150 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
151 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
153 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
154 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
156 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
157 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
162 struct pipe_resource
*
163 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
165 /* For packed depth-stencil, we treat depth as the primary resource
166 * and store S8 as the "second plane" resource.
172 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
173 struct pipe_resource
*stencil
)
175 assert(util_format_has_depth(util_format_description(p_res
->format
)));
176 pipe_resource_reference(&p_res
->next
, stencil
);
180 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
181 struct iris_resource
**out_z
,
182 struct iris_resource
**out_s
)
190 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
191 *out_z
= (void *) res
;
192 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
195 *out_s
= (void *) res
;
200 iris_resource_disable_aux(struct iris_resource
*res
)
202 iris_bo_unreference(res
->aux
.bo
);
203 free(res
->aux
.state
);
205 // XXX: clear color BO
207 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
208 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
209 res
->aux
.surf
.size_B
= 0;
211 res
->aux
.state
= NULL
;
215 iris_resource_destroy(struct pipe_screen
*screen
,
216 struct pipe_resource
*resource
)
218 struct iris_resource
*res
= (struct iris_resource
*)resource
;
220 iris_resource_disable_aux(res
);
222 iris_bo_unreference(res
->bo
);
226 static struct iris_resource
*
227 iris_alloc_resource(struct pipe_screen
*pscreen
,
228 const struct pipe_resource
*templ
)
230 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
235 res
->base
.screen
= pscreen
;
236 pipe_reference_init(&res
->base
.reference
, 1);
238 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
244 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
246 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
247 return minify(res
->surf
.logical_level0_px
.depth
, level
);
249 return res
->surf
.logical_level0_px
.array_len
;
252 static enum isl_aux_state
**
253 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
255 uint32_t total_slices
= 0;
256 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
257 total_slices
+= iris_get_num_logical_layers(res
, level
);
259 const size_t per_level_array_size
=
260 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
262 /* We're going to allocate a single chunk of data for both the per-level
263 * reference array and the arrays of aux_state. This makes cleanup
264 * significantly easier.
266 const size_t total_size
=
267 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
269 void *data
= malloc(total_size
);
273 enum isl_aux_state
**per_level_arr
= data
;
274 enum isl_aux_state
*s
= data
+ per_level_array_size
;
275 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
276 per_level_arr
[level
] = s
;
277 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
278 for (uint32_t a
= 0; a
< level_layers
; a
++)
281 assert((void *)s
== data
+ total_size
);
283 return per_level_arr
;
287 * Allocate the initial aux surface for a resource based on aux.usage
290 iris_resource_alloc_aux(struct iris_screen
*screen
, struct iris_resource
*res
)
292 struct isl_device
*isl_dev
= &screen
->isl_dev
;
293 enum isl_aux_state initial_state
;
294 UNUSED
bool ok
= false;
295 uint8_t memset_value
= 0;
296 uint32_t alloc_flags
= 0;
298 assert(!res
->aux
.bo
);
300 switch (res
->aux
.usage
) {
301 case ISL_AUX_USAGE_NONE
:
302 res
->aux
.surf
.size_B
= 0;
304 case ISL_AUX_USAGE_HIZ
:
305 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
307 ok
= isl_surf_get_hiz_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
309 case ISL_AUX_USAGE_MCS
:
310 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
312 * "When MCS buffer is enabled and bound to MSRT, it is required
313 * that it is cleared prior to any rendering."
315 * Since we only use the MCS buffer for rendering, we just clear it
316 * immediately on allocation. The clear value for MCS buffers is all
317 * 1's, so we simply memset it to 0xff.
319 initial_state
= ISL_AUX_STATE_CLEAR
;
321 ok
= isl_surf_get_mcs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
323 case ISL_AUX_USAGE_CCS_D
:
324 case ISL_AUX_USAGE_CCS_E
:
325 /* When CCS_E is used, we need to ensure that the CCS starts off in
326 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
329 * "If Software wants to enable Color Compression without Fast
330 * clear, Software needs to initialize MCS with zeros."
332 * A CCS value of 0 indicates that the corresponding block is in the
333 * pass-through state which is what we want.
335 * For CCS_D, do the same thing. On Gen9+, this avoids having any
336 * undefined bits in the aux buffer.
338 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
339 alloc_flags
|= BO_ALLOC_ZEROED
;
340 ok
= isl_surf_get_ccs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
, 0);
344 /* No work is needed for a zero-sized auxiliary buffer. */
345 if (res
->aux
.surf
.size_B
== 0)
348 /* Assert that ISL gave us a valid aux surf */
351 /* Create the aux_state for the auxiliary buffer. */
352 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
356 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
357 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
358 * of bytes instead of trying to recalculate based on different format
361 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer",
362 res
->aux
.surf
.size_B
,
363 IRIS_MEMZONE_OTHER
, I915_TILING_Y
,
364 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
366 iris_resource_disable_aux(res
);
370 /* Optionally, initialize the auxiliary data to the desired value. */
371 if (memset_value
!= 0) {
372 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
374 iris_resource_disable_aux(res
);
378 memset(map
, memset_value
, res
->aux
.surf
.size_B
);
379 iris_bo_unmap(res
->aux
.bo
);
382 if (res
->aux
.usage
== ISL_AUX_USAGE_HIZ
) {
383 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
384 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
385 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
387 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
388 * For LOD == 0, we can grow the dimensions to make it work.
390 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
391 res
->aux
.has_hiz
|= 1 << level
;
399 supports_mcs(const struct isl_surf
*surf
)
401 /* MCS compression only applies to multisampled resources. */
402 if (surf
->samples
<= 1)
405 /* See isl_surf_get_mcs_surf for details. */
406 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
409 /* Depth and stencil buffers use the IMS (interleaved) layout. */
410 if (isl_surf_usage_is_depth_or_stencil(surf
->usage
))
417 supports_ccs(const struct gen_device_info
*devinfo
,
418 const struct isl_surf
*surf
)
420 /* Gen9+ only supports CCS for Y-tiled buffers. */
421 if (surf
->tiling
!= ISL_TILING_Y0
)
424 /* CCS only supports singlesampled resources. */
425 if (surf
->samples
> 1)
428 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
429 * work for 3D textures until Gen9 where the layout of 3D textures changes
430 * to match 2D array textures.
432 if (devinfo
->gen
< 9 && surf
->dim
!= ISL_SURF_DIM_2D
)
435 /* Note: still need to check the format! */
440 static struct pipe_resource
*
441 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
442 const struct pipe_resource
*templ
)
444 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
445 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
447 assert(templ
->target
== PIPE_BUFFER
);
448 assert(templ
->height0
<= 1);
449 assert(templ
->depth0
<= 1);
450 assert(templ
->format
== PIPE_FORMAT_NONE
||
451 util_format_get_blocksize(templ
->format
) == 1);
453 res
->internal_format
= templ
->format
;
454 res
->surf
.tiling
= ISL_TILING_LINEAR
;
456 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
457 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
458 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
459 memzone
= IRIS_MEMZONE_SHADER
;
460 name
= "shader kernels";
461 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
462 memzone
= IRIS_MEMZONE_SURFACE
;
463 name
= "surface state";
464 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
465 memzone
= IRIS_MEMZONE_DYNAMIC
;
466 name
= "dynamic state";
469 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
471 iris_resource_destroy(pscreen
, &res
->base
);
478 static struct pipe_resource
*
479 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
480 const struct pipe_resource
*templ
,
481 const uint64_t *modifiers
,
484 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
485 struct gen_device_info
*devinfo
= &screen
->devinfo
;
486 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
491 const struct util_format_description
*format_desc
=
492 util_format_description(templ
->format
);
493 const bool has_depth
= util_format_has_depth(format_desc
);
495 select_best_modifier(devinfo
, modifiers
, modifiers_count
);
497 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
499 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
500 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
502 tiling_flags
= 1 << res
->mod_info
->tiling
;
504 if (modifiers_count
> 0) {
505 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
509 /* No modifiers - we can select our own tiling. */
512 /* Depth must be Y-tiled */
513 tiling_flags
= ISL_TILING_Y0_BIT
;
514 } else if (templ
->format
== PIPE_FORMAT_S8_UINT
) {
515 /* Stencil must be W-tiled */
516 tiling_flags
= ISL_TILING_W_BIT
;
517 } else if (templ
->target
== PIPE_BUFFER
||
518 templ
->target
== PIPE_TEXTURE_1D
||
519 templ
->target
== PIPE_TEXTURE_1D_ARRAY
) {
520 /* Use linear for buffers and 1D textures */
521 tiling_flags
= ISL_TILING_LINEAR_BIT
;
524 /* Use linear for staging buffers */
525 if (templ
->usage
== PIPE_USAGE_STAGING
||
526 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
527 tiling_flags
= ISL_TILING_LINEAR_BIT
;
530 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
532 if (templ
->target
== PIPE_TEXTURE_CUBE
||
533 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
534 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
536 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
537 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
538 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
540 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
543 enum pipe_format pfmt
= templ
->format
;
544 res
->internal_format
= pfmt
;
546 /* Should be handled by u_transfer_helper */
547 assert(!util_format_is_depth_and_stencil(pfmt
));
549 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
550 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
552 UNUSED
const bool isl_surf_created_successfully
=
553 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
554 .dim
= target_to_isl_surf_dim(templ
->target
),
556 .width
= templ
->width0
,
557 .height
= templ
->height0
,
558 .depth
= templ
->depth0
,
559 .levels
= templ
->last_level
+ 1,
560 .array_len
= templ
->array_size
,
561 .samples
= MAX2(templ
->nr_samples
, 1),
562 .min_alignment_B
= 0,
565 .tiling_flags
= tiling_flags
);
566 assert(isl_surf_created_successfully
);
569 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
570 } else if (res
->surf
.samples
> 1) {
571 if (supports_mcs(&res
->surf
))
572 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_MCS
;
575 if (likely(!(INTEL_DEBUG
& DEBUG_NO_HIZ
)))
576 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
577 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO_RBC
)) &&
578 supports_ccs(devinfo
, &res
->surf
)) {
579 if (isl_format_supports_ccs_e(devinfo
, res
->surf
.format
))
580 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
582 if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
583 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
587 // XXX: we don't actually do aux yet
588 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
590 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
592 const char *name
= "miptree";
593 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
595 /* These are for u_upload_mgr buffers only */
596 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
597 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
598 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
600 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, res
->surf
.size_B
,
602 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
603 res
->surf
.row_pitch_B
, 0);
608 if (!iris_resource_alloc_aux(screen
, res
))
614 fprintf(stderr
, "XXX: resource creation failed\n");
615 iris_resource_destroy(pscreen
, &res
->base
);
620 static struct pipe_resource
*
621 iris_resource_create(struct pipe_screen
*pscreen
,
622 const struct pipe_resource
*templ
)
624 if (templ
->target
== PIPE_BUFFER
)
625 return iris_resource_create_for_buffer(pscreen
, templ
);
627 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
631 tiling_to_modifier(uint32_t tiling
)
633 static const uint64_t map
[] = {
634 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
635 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
636 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
639 assert(tiling
< ARRAY_SIZE(map
));
644 static struct pipe_resource
*
645 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
646 const struct pipe_resource
*templ
,
649 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
650 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
651 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
655 assert(templ
->target
== PIPE_BUFFER
);
657 res
->internal_format
= templ
->format
;
658 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
659 user_memory
, templ
->width0
,
669 static struct pipe_resource
*
670 iris_resource_from_handle(struct pipe_screen
*pscreen
,
671 const struct pipe_resource
*templ
,
672 struct winsys_handle
*whandle
,
675 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
676 struct gen_device_info
*devinfo
= &screen
->devinfo
;
677 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
678 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
682 if (whandle
->offset
!= 0) {
683 dbg_printf("Attempt to import unsupported winsys offset %u\n",
688 switch (whandle
->type
) {
689 case WINSYS_HANDLE_TYPE_FD
:
690 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
);
692 case WINSYS_HANDLE_TYPE_SHARED
:
693 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
697 unreachable("invalid winsys handle type");
702 uint64_t modifier
= whandle
->modifier
;
703 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
704 modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
706 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
707 assert(res
->mod_info
);
709 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
711 const struct iris_format_info fmt
=
712 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
713 res
->internal_format
= templ
->format
;
715 if (templ
->target
== PIPE_BUFFER
) {
716 res
->surf
.tiling
= ISL_TILING_LINEAR
;
718 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
719 .dim
= target_to_isl_surf_dim(templ
->target
),
721 .width
= templ
->width0
,
722 .height
= templ
->height0
,
723 .depth
= templ
->depth0
,
724 .levels
= templ
->last_level
+ 1,
725 .array_len
= templ
->array_size
,
726 .samples
= MAX2(templ
->nr_samples
, 1),
727 .min_alignment_B
= 0,
728 .row_pitch_B
= whandle
->stride
,
730 .tiling_flags
= 1 << res
->mod_info
->tiling
);
732 assert(res
->bo
->tiling_mode
==
733 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
735 // XXX: create_ccs_buf_for_image?
736 if (!iris_resource_alloc_aux(screen
, res
))
743 iris_resource_destroy(pscreen
, &res
->base
);
748 iris_resource_get_handle(struct pipe_screen
*pscreen
,
749 struct pipe_context
*ctx
,
750 struct pipe_resource
*resource
,
751 struct winsys_handle
*whandle
,
754 struct iris_context
*ice
= (struct iris_context
*)ctx
;
755 struct iris_resource
*res
= (struct iris_resource
*)resource
;
757 /* If this is a buffer, stride should be 0 - no need to special case */
758 whandle
->stride
= res
->surf
.row_pitch_B
;
760 res
->mod_info
? res
->mod_info
->modifier
761 : tiling_to_modifier(res
->bo
->tiling_mode
);
764 (!res
->mod_info
|| res
->mod_info
->aux_usage
!= res
->aux
.usage
)) {
765 struct iris_batch
*render_batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
766 iris_resource_prepare_access(ice
, render_batch
, res
,
767 0, INTEL_REMAINING_LEVELS
,
768 0, INTEL_REMAINING_LAYERS
,
769 ISL_AUX_USAGE_NONE
, false);
770 if (res
->aux
.usage
!= ISL_AUX_USAGE_NONE
) {
771 iris_resource_disable_aux(res
);
772 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
775 if (res
->aux
.usage
!= ISL_AUX_USAGE_NONE
) {
776 enum isl_aux_state aux_state
=
777 iris_resource_get_aux_state(res
, 0, 0);
778 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
779 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
783 switch (whandle
->type
) {
784 case WINSYS_HANDLE_TYPE_SHARED
:
785 return iris_bo_flink(res
->bo
, &whandle
->handle
) == 0;
786 case WINSYS_HANDLE_TYPE_KMS
:
787 whandle
->handle
= iris_bo_export_gem_handle(res
->bo
);
789 case WINSYS_HANDLE_TYPE_FD
:
790 return iris_bo_export_dmabuf(res
->bo
, (int *) &whandle
->handle
) == 0;
797 get_image_offset_el(struct isl_surf
*surf
, unsigned level
, unsigned z
,
798 unsigned *out_x0_el
, unsigned *out_y0_el
)
800 if (surf
->dim
== ISL_SURF_DIM_3D
) {
801 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
803 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
808 * Get pointer offset into stencil buffer.
810 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
811 * must decode the tile's layout in software.
814 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
816 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
818 * Even though the returned offset is always positive, the return type is
820 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
821 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
824 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
826 uint32_t tile_size
= 4096;
827 uint32_t tile_width
= 64;
828 uint32_t tile_height
= 64;
829 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
831 uint32_t tile_x
= x
/ tile_width
;
832 uint32_t tile_y
= y
/ tile_height
;
834 /* The byte's address relative to the tile's base addres. */
835 uint32_t byte_x
= x
% tile_width
;
836 uint32_t byte_y
= y
% tile_height
;
838 uintptr_t u
= tile_y
* row_size
842 + 32 * ((byte_y
/ 4) % 2)
843 + 16 * ((byte_x
/ 4) % 2)
844 + 8 * ((byte_y
/ 2) % 2)
845 + 4 * ((byte_x
/ 2) % 2)
850 /* adjust for bit6 swizzling */
851 if (((byte_x
/ 8) % 2) == 1) {
852 if (((byte_y
/ 8) % 2) == 0) {
864 iris_unmap_s8(struct iris_transfer
*map
)
866 struct pipe_transfer
*xfer
= &map
->base
;
867 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
868 struct isl_surf
*surf
= &res
->surf
;
869 const bool has_swizzling
= false;
871 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
872 uint8_t *untiled_s8_map
= map
->ptr
;
873 uint8_t *tiled_s8_map
=
874 iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
876 struct pipe_box box
= xfer
->box
;
878 for (int s
= 0; s
< box
.depth
; s
++) {
879 unsigned x0_el
, y0_el
;
880 get_image_offset_el(surf
, xfer
->level
, box
.z
, &x0_el
, &y0_el
);
882 for (uint32_t y
= 0; y
< box
.height
; y
++) {
883 for (uint32_t x
= 0; x
< box
.width
; x
++) {
884 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
888 tiled_s8_map
[offset
] =
889 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
901 iris_map_s8(struct iris_transfer
*map
)
903 struct pipe_transfer
*xfer
= &map
->base
;
904 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
905 struct isl_surf
*surf
= &res
->surf
;
907 xfer
->stride
= surf
->row_pitch_B
;
908 xfer
->layer_stride
= xfer
->stride
* xfer
->box
.height
;
910 /* The tiling and detiling functions require that the linear buffer has
911 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
912 * over-allocate the linear buffer to get the proper alignment.
914 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* xfer
->box
.depth
);
917 const bool has_swizzling
= false;
919 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
920 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
921 * invalidate is set, since we'll be writing the whole rectangle from our
922 * temporary buffer back out.
924 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
925 uint8_t *untiled_s8_map
= map
->ptr
;
926 uint8_t *tiled_s8_map
=
927 iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
929 struct pipe_box box
= xfer
->box
;
931 for (int s
= 0; s
< box
.depth
; s
++) {
932 unsigned x0_el
, y0_el
;
933 get_image_offset_el(surf
, xfer
->level
, box
.z
, &x0_el
, &y0_el
);
935 for (uint32_t y
= 0; y
< box
.height
; y
++) {
936 for (uint32_t x
= 0; x
< box
.width
; x
++) {
937 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
941 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
942 tiled_s8_map
[offset
];
950 map
->unmap
= iris_unmap_s8
;
953 /* Compute extent parameters for use with tiled_memcpy functions.
954 * xs are in units of bytes and ys are in units of strides.
957 tile_extents(struct isl_surf
*surf
,
958 const struct pipe_box
*box
,
960 unsigned *x1_B
, unsigned *x2_B
,
961 unsigned *y1_el
, unsigned *y2_el
)
963 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
964 const unsigned cpp
= fmtl
->bpb
/ 8;
966 assert(box
->x
% fmtl
->bw
== 0);
967 assert(box
->y
% fmtl
->bh
== 0);
969 unsigned x0_el
, y0_el
;
970 get_image_offset_el(surf
, level
, box
->z
, &x0_el
, &y0_el
);
972 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
973 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
974 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
975 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
979 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
981 struct pipe_transfer
*xfer
= &map
->base
;
982 struct pipe_box box
= xfer
->box
;
983 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
984 struct isl_surf
*surf
= &res
->surf
;
986 const bool has_swizzling
= false;
988 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
989 char *dst
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
991 for (int s
= 0; s
< box
.depth
; s
++) {
992 unsigned x1
, x2
, y1
, y2
;
993 tile_extents(surf
, &box
, xfer
->level
, &x1
, &x2
, &y1
, &y2
);
995 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
997 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
998 surf
->row_pitch_B
, xfer
->stride
,
999 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1003 os_free_aligned(map
->buffer
);
1004 map
->buffer
= map
->ptr
= NULL
;
1008 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1010 struct pipe_transfer
*xfer
= &map
->base
;
1011 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1012 struct isl_surf
*surf
= &res
->surf
;
1014 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1015 xfer
->layer_stride
= xfer
->stride
* xfer
->box
.height
;
1017 unsigned x1
, x2
, y1
, y2
;
1018 tile_extents(surf
, &xfer
->box
, xfer
->level
, &x1
, &x2
, &y1
, &y2
);
1020 /* The tiling and detiling functions require that the linear buffer has
1021 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1022 * over-allocate the linear buffer to get the proper alignment.
1025 os_malloc_aligned(xfer
->layer_stride
* xfer
->box
.depth
, 16);
1026 assert(map
->buffer
);
1027 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1029 const bool has_swizzling
= false;
1031 // XXX: PIPE_TRANSFER_READ?
1032 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1033 char *src
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
| MAP_RAW
);
1035 struct pipe_box box
= xfer
->box
;
1037 for (int s
= 0; s
< box
.depth
; s
++) {
1038 unsigned x1
, x2
, y1
, y2
;
1039 tile_extents(surf
, &box
, xfer
->level
, &x1
, &x2
, &y1
, &y2
);
1041 /* Use 's' rather than 'box.z' to rebase the first slice to 0. */
1042 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1044 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1045 surf
->row_pitch_B
, has_swizzling
,
1046 surf
->tiling
, ISL_MEMCPY
);
1051 map
->unmap
= iris_unmap_tiled_memcpy
;
1055 iris_map_direct(struct iris_transfer
*map
)
1057 struct pipe_transfer
*xfer
= &map
->base
;
1058 struct pipe_box
*box
= &xfer
->box
;
1059 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1061 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
);
1063 if (res
->base
.target
== PIPE_BUFFER
) {
1065 xfer
->layer_stride
= 0;
1067 map
->ptr
= ptr
+ box
->x
;
1069 struct isl_surf
*surf
= &res
->surf
;
1070 const struct isl_format_layout
*fmtl
=
1071 isl_format_get_layout(surf
->format
);
1072 const unsigned cpp
= fmtl
->bpb
/ 8;
1073 unsigned x0_el
, y0_el
;
1075 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1077 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1078 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1080 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1085 iris_transfer_map(struct pipe_context
*ctx
,
1086 struct pipe_resource
*resource
,
1088 enum pipe_transfer_usage usage
,
1089 const struct pipe_box
*box
,
1090 struct pipe_transfer
**ptransfer
)
1092 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1093 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1094 struct isl_surf
*surf
= &res
->surf
;
1096 /* If we can discard the whole resource, we can also discard the
1097 * subrange being accessed.
1099 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
)
1100 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1102 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1103 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1106 if (resource
->target
!= PIPE_BUFFER
) {
1107 iris_resource_access_raw(ice
, &ice
->batches
[IRIS_BATCH_RENDER
], res
,
1108 level
, box
->z
, box
->depth
,
1109 usage
& PIPE_TRANSFER_WRITE
);
1112 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1113 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1114 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1115 iris_batch_flush(&ice
->batches
[i
]);
1119 if ((usage
& PIPE_TRANSFER_DONTBLOCK
) && iris_bo_busy(res
->bo
))
1122 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1123 struct pipe_transfer
*xfer
= &map
->base
;
1128 memset(map
, 0, sizeof(*map
));
1129 map
->dbg
= &ice
->dbg
;
1131 pipe_resource_reference(&xfer
->resource
, resource
);
1132 xfer
->level
= level
;
1133 xfer
->usage
= usage
;
1137 xfer
->usage
&= (PIPE_TRANSFER_READ
|
1138 PIPE_TRANSFER_WRITE
|
1139 PIPE_TRANSFER_UNSYNCHRONIZED
|
1140 PIPE_TRANSFER_PERSISTENT
|
1141 PIPE_TRANSFER_COHERENT
|
1142 PIPE_TRANSFER_DISCARD_RANGE
);
1144 if (surf
->tiling
== ISL_TILING_W
) {
1145 // XXX: just teach iris_map_tiled_memcpy about W tiling...
1147 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1148 iris_map_tiled_memcpy(map
);
1150 iris_map_direct(map
);
1157 iris_transfer_flush_region(struct pipe_context
*ctx
,
1158 struct pipe_transfer
*xfer
,
1159 const struct pipe_box
*box
)
1161 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1162 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1165 // XXX: don't emit flushes in both engines...? we may also need to flush
1166 // even if there isn't a draw yet - may still be stale data in caches...
1167 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1168 if (ice
->batches
[i
].contains_draw
) {
1169 iris_batch_maybe_flush(&ice
->batches
[i
], 24);
1170 iris_flush_and_dirty_for_history(ice
, &ice
->batches
[i
], res
);
1176 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1178 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1179 struct iris_transfer
*map
= (void *) xfer
;
1180 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1185 // XXX: don't emit flushes in both engines...?
1186 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1187 if (ice
->batches
[i
].contains_draw
) {
1188 iris_batch_maybe_flush(&ice
->batches
[i
], 24);
1189 iris_flush_and_dirty_for_history(ice
, &ice
->batches
[i
], res
);
1193 pipe_resource_reference(&xfer
->resource
, NULL
);
1194 slab_free(&ice
->transfer_pool
, map
);
1198 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
1203 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
1204 struct iris_batch
*batch
,
1205 struct iris_resource
*res
)
1207 if (res
->base
.target
!= PIPE_BUFFER
)
1210 unsigned flush
= PIPE_CONTROL_CS_STALL
;
1212 /* We've likely used the rendering engine (i.e. BLORP) to write to this
1213 * surface. Flush the render cache so the data actually lands.
1215 if (batch
->name
!= IRIS_BATCH_COMPUTE
)
1216 flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
1218 uint64_t dirty
= 0ull;
1220 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1221 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
1222 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1223 dirty
|= IRIS_DIRTY_CONSTANTS_VS
|
1224 IRIS_DIRTY_CONSTANTS_TCS
|
1225 IRIS_DIRTY_CONSTANTS_TES
|
1226 IRIS_DIRTY_CONSTANTS_GS
|
1227 IRIS_DIRTY_CONSTANTS_FS
|
1228 IRIS_DIRTY_CONSTANTS_CS
|
1229 IRIS_ALL_DIRTY_BINDINGS
;
1232 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
1233 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1235 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
1236 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1238 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
1239 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
1241 iris_emit_pipe_control_flush(batch
, flush
);
1243 ice
->state
.dirty
|= dirty
;
1246 static enum pipe_format
1247 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
1249 struct iris_resource
*res
= (void *) p_res
;
1250 return res
->internal_format
;
1253 static const struct u_transfer_vtbl transfer_vtbl
= {
1254 .resource_create
= iris_resource_create
,
1255 .resource_destroy
= iris_resource_destroy
,
1256 .transfer_map
= iris_transfer_map
,
1257 .transfer_unmap
= iris_transfer_unmap
,
1258 .transfer_flush_region
= iris_transfer_flush_region
,
1259 .get_internal_format
= iris_resource_get_internal_format
,
1260 .set_stencil
= iris_resource_set_separate_stencil
,
1261 .get_stencil
= iris_resource_get_separate_stencil
,
1265 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
1267 pscreen
->resource_create_with_modifiers
=
1268 iris_resource_create_with_modifiers
;
1269 pscreen
->resource_create
= u_transfer_helper_resource_create
;
1270 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
1271 pscreen
->resource_from_handle
= iris_resource_from_handle
;
1272 pscreen
->resource_get_handle
= iris_resource_get_handle
;
1273 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
1274 pscreen
->transfer_helper
=
1275 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
1279 iris_init_resource_functions(struct pipe_context
*ctx
)
1281 ctx
->flush_resource
= iris_flush_resource
;
1282 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
1283 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
1284 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
1285 ctx
->buffer_subdata
= u_default_buffer_subdata
;
1286 ctx
->texture_subdata
= u_default_texture_subdata
;