2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/format/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
56 enum modifier_priority
{
57 MODIFIER_PRIORITY_INVALID
= 0,
58 MODIFIER_PRIORITY_LINEAR
,
61 MODIFIER_PRIORITY_Y_CCS
,
64 static const uint64_t priority_to_modifier
[] = {
65 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
66 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
67 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
68 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
69 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
73 modifier_is_supported(const struct gen_device_info
*devinfo
,
74 enum pipe_format pfmt
, uint64_t modifier
)
76 /* XXX: do something real */
78 case I915_FORMAT_MOD_Y_TILED_CCS
: {
79 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
82 enum isl_format rt_format
=
83 iris_format_for_usage(devinfo
, pfmt
,
84 ISL_SURF_USAGE_RENDER_TARGET_BIT
).fmt
;
86 enum isl_format linear_format
= isl_format_srgb_to_linear(rt_format
);
88 if (linear_format
== ISL_FORMAT_UNSUPPORTED
||
89 !isl_format_supports_ccs_e(devinfo
, linear_format
))
92 return devinfo
->gen
>= 9 && devinfo
->gen
<= 11;
94 case I915_FORMAT_MOD_Y_TILED
:
95 case I915_FORMAT_MOD_X_TILED
:
96 case DRM_FORMAT_MOD_LINEAR
:
98 case DRM_FORMAT_MOD_INVALID
:
105 select_best_modifier(struct gen_device_info
*devinfo
, enum pipe_format pfmt
,
106 const uint64_t *modifiers
,
109 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
111 for (int i
= 0; i
< count
; i
++) {
112 if (!modifier_is_supported(devinfo
, pfmt
, modifiers
[i
]))
115 switch (modifiers
[i
]) {
116 case I915_FORMAT_MOD_Y_TILED_CCS
:
117 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
119 case I915_FORMAT_MOD_Y_TILED
:
120 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
122 case I915_FORMAT_MOD_X_TILED
:
123 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
125 case DRM_FORMAT_MOD_LINEAR
:
126 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
128 case DRM_FORMAT_MOD_INVALID
:
134 return priority_to_modifier
[prio
];
138 target_to_isl_surf_dim(enum pipe_texture_target target
)
142 case PIPE_TEXTURE_1D
:
143 case PIPE_TEXTURE_1D_ARRAY
:
144 return ISL_SURF_DIM_1D
;
145 case PIPE_TEXTURE_2D
:
146 case PIPE_TEXTURE_CUBE
:
147 case PIPE_TEXTURE_RECT
:
148 case PIPE_TEXTURE_2D_ARRAY
:
149 case PIPE_TEXTURE_CUBE_ARRAY
:
150 return ISL_SURF_DIM_2D
;
151 case PIPE_TEXTURE_3D
:
152 return ISL_SURF_DIM_3D
;
153 case PIPE_MAX_TEXTURE_TYPES
:
156 unreachable("invalid texture type");
160 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
161 enum pipe_format pfmt
,
164 unsigned int *external_only
,
167 struct iris_screen
*screen
= (void *) pscreen
;
168 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
170 uint64_t all_modifiers
[] = {
171 DRM_FORMAT_MOD_LINEAR
,
172 I915_FORMAT_MOD_X_TILED
,
173 I915_FORMAT_MOD_Y_TILED
,
174 I915_FORMAT_MOD_Y_TILED_CCS
,
177 int supported_mods
= 0;
179 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
180 if (!modifier_is_supported(devinfo
, pfmt
, all_modifiers
[i
]))
183 if (supported_mods
< max
) {
185 modifiers
[supported_mods
] = all_modifiers
[i
];
188 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
194 *count
= supported_mods
;
197 static isl_surf_usage_flags_t
198 pipe_bind_to_isl_usage(unsigned bindings
)
200 isl_surf_usage_flags_t usage
= 0;
202 if (bindings
& PIPE_BIND_RENDER_TARGET
)
203 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
205 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
206 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
208 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
209 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
211 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
212 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
218 iris_image_view_get_format(struct iris_context
*ice
,
219 const struct pipe_image_view
*img
)
221 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
222 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
224 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
225 enum isl_format isl_fmt
=
226 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
228 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
229 /* On Gen8, try to use typed surfaces reads (which support a
230 * limited number of formats), and if not possible, fall back
233 if (devinfo
->gen
== 8 &&
234 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
))
235 return ISL_FORMAT_RAW
;
237 return isl_lower_storage_image_format(devinfo
, isl_fmt
);
243 struct pipe_resource
*
244 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
246 /* For packed depth-stencil, we treat depth as the primary resource
247 * and store S8 as the "second plane" resource.
249 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
257 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
258 struct pipe_resource
*stencil
)
260 assert(util_format_has_depth(util_format_description(p_res
->format
)));
261 pipe_resource_reference(&p_res
->next
, stencil
);
265 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
266 struct iris_resource
**out_z
,
267 struct iris_resource
**out_s
)
275 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
276 *out_z
= (void *) res
;
277 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
280 *out_s
= (void *) res
;
285 iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
286 enum isl_tiling tiling
,
287 enum pipe_texture_target target
)
290 case PIPE_TEXTURE_1D
:
291 case PIPE_TEXTURE_1D_ARRAY
:
292 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
293 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
295 case PIPE_TEXTURE_2D
:
296 case PIPE_TEXTURE_2D_ARRAY
:
297 case PIPE_TEXTURE_RECT
:
298 case PIPE_TEXTURE_CUBE
:
299 case PIPE_TEXTURE_CUBE_ARRAY
:
300 return ISL_DIM_LAYOUT_GEN4_2D
;
302 case PIPE_TEXTURE_3D
:
303 return (devinfo
->gen
>= 9 ?
304 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
306 case PIPE_MAX_TEXTURE_TYPES
:
310 unreachable("invalid texture type");
314 iris_resource_disable_aux(struct iris_resource
*res
)
316 iris_bo_unreference(res
->aux
.bo
);
317 iris_bo_unreference(res
->aux
.clear_color_bo
);
318 free(res
->aux
.state
);
320 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
321 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
322 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
323 res
->aux
.has_hiz
= 0;
324 res
->aux
.surf
.size_B
= 0;
326 res
->aux
.extra_aux
.surf
.size_B
= 0;
327 res
->aux
.clear_color_bo
= NULL
;
328 res
->aux
.state
= NULL
;
332 iris_resource_destroy(struct pipe_screen
*screen
,
333 struct pipe_resource
*resource
)
335 struct iris_resource
*res
= (struct iris_resource
*)resource
;
337 if (resource
->target
== PIPE_BUFFER
)
338 util_range_destroy(&res
->valid_buffer_range
);
340 iris_resource_disable_aux(res
);
342 iris_bo_unreference(res
->bo
);
343 iris_pscreen_unref(res
->base
.screen
);
348 static struct iris_resource
*
349 iris_alloc_resource(struct pipe_screen
*pscreen
,
350 const struct pipe_resource
*templ
)
352 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
357 res
->base
.screen
= iris_pscreen_ref(pscreen
);
358 pipe_reference_init(&res
->base
.reference
, 1);
360 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
361 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
363 if (templ
->target
== PIPE_BUFFER
)
364 util_range_init(&res
->valid_buffer_range
);
370 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
372 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
373 return minify(res
->surf
.logical_level0_px
.depth
, level
);
375 return res
->surf
.logical_level0_px
.array_len
;
378 static enum isl_aux_state
**
379 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
381 assert(res
->aux
.state
== NULL
);
383 uint32_t total_slices
= 0;
384 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
385 total_slices
+= iris_get_num_logical_layers(res
, level
);
387 const size_t per_level_array_size
=
388 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
390 /* We're going to allocate a single chunk of data for both the per-level
391 * reference array and the arrays of aux_state. This makes cleanup
392 * significantly easier.
394 const size_t total_size
=
395 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
397 void *data
= malloc(total_size
);
401 enum isl_aux_state
**per_level_arr
= data
;
402 enum isl_aux_state
*s
= data
+ per_level_array_size
;
403 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
404 per_level_arr
[level
] = s
;
405 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
406 for (uint32_t a
= 0; a
< level_layers
; a
++)
409 assert((void *)s
== data
+ total_size
);
411 return per_level_arr
;
415 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
417 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
418 return devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
: 0;
422 map_aux_addresses(struct iris_screen
*screen
, struct iris_resource
*res
)
424 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
425 if (devinfo
->gen
>= 12 && isl_aux_usage_has_ccs(res
->aux
.usage
)) {
426 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
428 const unsigned aux_offset
= res
->aux
.extra_aux
.surf
.size_B
> 0 ?
429 res
->aux
.extra_aux
.offset
: res
->aux
.offset
;
430 gen_aux_map_add_image(aux_map_ctx
, &res
->surf
, res
->bo
->gtt_offset
,
431 res
->aux
.bo
->gtt_offset
+ aux_offset
);
432 res
->bo
->aux_map_address
= res
->aux
.bo
->gtt_offset
;
437 want_ccs_e_for_format(const struct gen_device_info
*devinfo
,
438 enum isl_format format
)
440 if (!isl_format_supports_ccs_e(devinfo
, format
))
443 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
445 /* CCS_E seems to significantly hurt performance with 32-bit floating
446 * point formats. For example, Paraview's "Wavelet Volume" case uses
447 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
448 * formats causes a 62% FPS drop.
450 * However, many benchmarks seem to use 16-bit float with no issues.
452 if (fmtl
->channels
.r
.bits
== 32 && fmtl
->channels
.r
.type
== ISL_SFLOAT
)
459 * Configure aux for the resource, but don't allocate it. For images which
460 * might be shared with modifiers, we must allocate the image and aux data in
463 * Returns false on unexpected error (e.g. allocation failed, or invalid
464 * configuration result).
467 iris_resource_configure_aux(struct iris_screen
*screen
,
468 struct iris_resource
*res
, bool imported
,
469 uint64_t *aux_size_B
,
470 uint32_t *alloc_flags
)
472 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
474 /* Try to create the auxiliary surfaces allowed by the modifier or by
475 * the user if no modifier is specified.
477 assert(!res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
||
478 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
480 const bool has_mcs
= !res
->mod_info
&&
481 isl_surf_get_mcs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
483 const bool has_hiz
= !res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_HIZ
) &&
484 isl_surf_get_hiz_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
487 ((!res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_RBC
)) ||
488 (res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)) &&
489 isl_surf_get_ccs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
,
490 &res
->aux
.extra_aux
.surf
, 0);
492 /* Having both HIZ and MCS is impossible. */
493 assert(!has_mcs
|| !has_hiz
);
495 /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
496 if (has_ccs
&& (has_mcs
|| has_hiz
)) {
497 assert(res
->aux
.extra_aux
.surf
.size_B
> 0 &&
498 res
->aux
.extra_aux
.surf
.usage
& ISL_SURF_USAGE_CCS_BIT
);
499 assert(res
->aux
.surf
.size_B
> 0 &&
500 res
->aux
.surf
.usage
&
501 (ISL_SURF_USAGE_HIZ_BIT
| ISL_SURF_USAGE_MCS_BIT
));
504 if (res
->mod_info
&& has_ccs
) {
505 /* Only allow a CCS modifier if the aux was created successfully. */
506 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
507 } else if (has_mcs
) {
508 res
->aux
.possible_usages
|=
509 1 << (has_ccs
? ISL_AUX_USAGE_MCS_CCS
: ISL_AUX_USAGE_MCS
);
510 } else if (has_hiz
) {
512 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
513 } else if (res
->surf
.samples
== 1 &&
514 (res
->surf
.usage
& ISL_SURF_USAGE_TEXTURE_BIT
)) {
515 /* If this resource is single-sampled and will be used as a texture,
516 * put the HiZ surface in write-through mode so that we can sample
519 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS_WT
;
521 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS
;
523 } else if (has_ccs
&& isl_surf_usage_is_stencil(res
->surf
.usage
)) {
524 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_STC_CCS
;
525 } else if (has_ccs
) {
526 if (want_ccs_e_for_format(devinfo
, res
->surf
.format
))
527 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
528 else if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
529 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
532 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
534 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
536 /* We don't always support sampling with hiz. But when we do, it must be
539 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1)
540 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
542 /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
543 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ_CCS
);
545 enum isl_aux_state initial_state
;
548 assert(!res
->aux
.bo
);
550 switch (res
->aux
.usage
) {
551 case ISL_AUX_USAGE_NONE
:
552 /* Having no aux buffer is only okay if there's no modifier with aux. */
553 return !res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
;
554 case ISL_AUX_USAGE_HIZ
:
555 case ISL_AUX_USAGE_HIZ_CCS
:
556 case ISL_AUX_USAGE_HIZ_CCS_WT
:
557 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
559 case ISL_AUX_USAGE_MCS
:
560 case ISL_AUX_USAGE_MCS_CCS
:
561 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
563 * "When MCS buffer is enabled and bound to MSRT, it is required
564 * that it is cleared prior to any rendering."
566 * Since we only use the MCS buffer for rendering, we just clear it
567 * immediately on allocation. The clear value for MCS buffers is all
568 * 1's, so we simply memset it to 0xff.
570 initial_state
= ISL_AUX_STATE_CLEAR
;
572 case ISL_AUX_USAGE_CCS_D
:
573 case ISL_AUX_USAGE_CCS_E
:
574 case ISL_AUX_USAGE_STC_CCS
:
575 /* When CCS_E is used, we need to ensure that the CCS starts off in
576 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
579 * "If Software wants to enable Color Compression without Fast
580 * clear, Software needs to initialize MCS with zeros."
582 * A CCS value of 0 indicates that the corresponding block is in the
583 * pass-through state which is what we want.
585 * For CCS_D, do the same thing. On Gen9+, this avoids having any
586 * undefined bits in the aux buffer.
589 assert(res
->aux
.usage
!= ISL_AUX_USAGE_STC_CCS
);
591 isl_drm_modifier_get_default_aux_state(res
->mod_info
->modifier
);
593 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
595 *alloc_flags
|= BO_ALLOC_ZEROED
;
597 case ISL_AUX_USAGE_MC
:
598 unreachable("Unsupported aux mode");
601 /* Create the aux_state for the auxiliary buffer. */
602 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
606 /* Increase the aux offset if the main and aux surfaces will share a BO. */
608 !res
->mod_info
|| res
->mod_info
->aux_usage
== res
->aux
.usage
?
609 ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
) : 0;
610 uint64_t size
= res
->aux
.surf
.size_B
;
612 /* Allocate space in the buffer for storing the CCS. */
613 if (res
->aux
.extra_aux
.surf
.size_B
> 0) {
614 const uint64_t padded_aux_size
=
615 ALIGN(size
, res
->aux
.extra_aux
.surf
.alignment_B
);
616 res
->aux
.extra_aux
.offset
= res
->aux
.offset
+ padded_aux_size
;
617 size
= padded_aux_size
+ res
->aux
.extra_aux
.surf
.size_B
;
620 /* Allocate space in the buffer for storing the clear color. On modern
621 * platforms (gen > 9), we can read it directly from such buffer.
623 * On gen <= 9, we are going to store the clear color on the buffer
624 * anyways, and copy it back to the surface state during state emission.
626 * Also add some padding to make sure the fast clear color state buffer
627 * starts at a 4K alignment. We believe that 256B might be enough, but due
628 * to lack of testing we will leave this as 4K for now.
630 size
= ALIGN(size
, 4096);
631 res
->aux
.clear_color_offset
= res
->aux
.offset
+ size
;
632 size
+= iris_get_aux_clear_color_state_size(screen
);
635 if (isl_aux_usage_has_hiz(res
->aux
.usage
)) {
636 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
637 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
638 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
640 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
641 * For LOD == 0, we can grow the dimensions to make it work.
643 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
644 res
->aux
.has_hiz
|= 1 << level
;
652 * Initialize the aux buffer contents.
654 * Returns false on unexpected error (e.g. mapping a BO failed).
657 iris_resource_init_aux_buf(struct iris_resource
*res
, uint32_t alloc_flags
,
658 unsigned clear_color_state_size
)
660 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
661 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
666 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
667 uint8_t memset_value
= isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0;
668 memset((char*)map
+ res
->aux
.offset
, memset_value
,
669 res
->aux
.surf
.size_B
);
672 memset((char*)map
+ res
->aux
.extra_aux
.offset
,
673 0, res
->aux
.extra_aux
.surf
.size_B
);
675 /* Zero the indirect clear color to match ::fast_clear_color. */
676 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
677 clear_color_state_size
);
679 iris_bo_unmap(res
->aux
.bo
);
682 if (clear_color_state_size
> 0) {
683 res
->aux
.clear_color_bo
= res
->aux
.bo
;
684 iris_bo_reference(res
->aux
.clear_color_bo
);
691 * Allocate the initial aux surface for a resource based on aux.usage
693 * Returns false on unexpected error (e.g. allocation failed, or invalid
694 * configuration result).
697 iris_resource_alloc_separate_aux(struct iris_screen
*screen
,
698 struct iris_resource
*res
)
700 uint32_t alloc_flags
;
702 if (!iris_resource_configure_aux(screen
, res
, false, &size
, &alloc_flags
))
708 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
709 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
710 * of bytes instead of trying to recalculate based on different format
713 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
, 4096,
715 isl_tiling_to_i915_tiling(res
->aux
.surf
.tiling
),
716 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
721 if (!iris_resource_init_aux_buf(res
, alloc_flags
,
722 iris_get_aux_clear_color_state_size(screen
)))
725 map_aux_addresses(screen
, res
);
731 iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
732 struct iris_resource
*res
)
734 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
735 assert(iris_resource_unfinished_aux_import(res
));
736 assert(!res
->mod_info
->supports_clear_color
);
738 struct iris_resource
*aux_res
= (void *) res
->base
.next
;
739 assert(aux_res
->aux
.surf
.row_pitch_B
&& aux_res
->aux
.offset
&&
742 assert(res
->bo
== aux_res
->aux
.bo
);
743 iris_bo_reference(aux_res
->aux
.bo
);
744 res
->aux
.bo
= aux_res
->aux
.bo
;
746 res
->aux
.offset
= aux_res
->aux
.offset
;
748 assert(res
->bo
->size
>= (res
->aux
.offset
+ res
->aux
.surf
.size_B
));
749 assert(res
->aux
.clear_color_bo
== NULL
);
750 res
->aux
.clear_color_offset
= 0;
752 assert(aux_res
->aux
.surf
.row_pitch_B
== res
->aux
.surf
.row_pitch_B
);
754 unsigned clear_color_state_size
=
755 iris_get_aux_clear_color_state_size(screen
);
757 if (clear_color_state_size
> 0) {
758 res
->aux
.clear_color_bo
=
759 iris_bo_alloc(screen
->bufmgr
, "clear color buffer",
760 clear_color_state_size
, IRIS_MEMZONE_OTHER
);
761 res
->aux
.clear_color_offset
= 0;
764 iris_resource_destroy(&screen
->base
, res
->base
.next
);
765 res
->base
.next
= NULL
;
768 static struct pipe_resource
*
769 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
770 const struct pipe_resource
*templ
)
772 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
773 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
775 assert(templ
->target
== PIPE_BUFFER
);
776 assert(templ
->height0
<= 1);
777 assert(templ
->depth0
<= 1);
778 assert(templ
->format
== PIPE_FORMAT_NONE
||
779 util_format_get_blocksize(templ
->format
) == 1);
781 res
->internal_format
= templ
->format
;
782 res
->surf
.tiling
= ISL_TILING_LINEAR
;
784 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
785 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
786 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
787 memzone
= IRIS_MEMZONE_SHADER
;
788 name
= "shader kernels";
789 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
790 memzone
= IRIS_MEMZONE_SURFACE
;
791 name
= "surface state";
792 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
793 memzone
= IRIS_MEMZONE_DYNAMIC
;
794 name
= "dynamic state";
797 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
799 iris_resource_destroy(pscreen
, &res
->base
);
803 if (templ
->bind
& PIPE_BIND_SHARED
)
804 iris_bo_make_external(res
->bo
);
809 static struct pipe_resource
*
810 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
811 const struct pipe_resource
*templ
,
812 const uint64_t *modifiers
,
815 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
816 struct gen_device_info
*devinfo
= &screen
->devinfo
;
817 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
822 const struct util_format_description
*format_desc
=
823 util_format_description(templ
->format
);
824 const bool has_depth
= util_format_has_depth(format_desc
);
826 select_best_modifier(devinfo
, templ
->format
, modifiers
, modifiers_count
);
828 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
830 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
831 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
833 tiling_flags
= 1 << res
->mod_info
->tiling
;
835 if (modifiers_count
> 0) {
836 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
840 /* Use linear for staging buffers */
841 if (templ
->usage
== PIPE_USAGE_STAGING
||
842 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
843 tiling_flags
= ISL_TILING_LINEAR_BIT
;
844 else if (templ
->bind
& PIPE_BIND_SCANOUT
)
845 tiling_flags
= ISL_TILING_X_BIT
;
848 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
850 if (templ
->target
== PIPE_TEXTURE_CUBE
||
851 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
852 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
854 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
855 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
856 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
858 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
861 enum pipe_format pfmt
= templ
->format
;
862 res
->internal_format
= pfmt
;
864 /* Should be handled by u_transfer_helper */
865 assert(!util_format_is_depth_and_stencil(pfmt
));
867 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
868 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
870 UNUSED
const bool isl_surf_created_successfully
=
871 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
872 .dim
= target_to_isl_surf_dim(templ
->target
),
874 .width
= templ
->width0
,
875 .height
= templ
->height0
,
876 .depth
= templ
->depth0
,
877 .levels
= templ
->last_level
+ 1,
878 .array_len
= templ
->array_size
,
879 .samples
= MAX2(templ
->nr_samples
, 1),
880 .min_alignment_B
= 0,
883 .tiling_flags
= tiling_flags
);
884 assert(isl_surf_created_successfully
);
886 const char *name
= "miptree";
887 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
889 unsigned int flags
= 0;
890 if (templ
->usage
== PIPE_USAGE_STAGING
)
891 flags
|= BO_ALLOC_COHERENT
;
893 /* These are for u_upload_mgr buffers only */
894 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
895 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
896 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
898 uint32_t aux_preferred_alloc_flags
;
899 uint64_t aux_size
= 0;
900 if (!iris_resource_configure_aux(screen
, res
, false, &aux_size
,
901 &aux_preferred_alloc_flags
)) {
905 /* Modifiers require the aux data to be in the same buffer as the main
906 * surface, but we combine them even when a modifiers is not being used.
908 const uint64_t bo_size
=
909 MAX2(res
->surf
.size_B
, res
->aux
.offset
+ aux_size
);
910 uint32_t alignment
= MAX2(4096, res
->surf
.alignment_B
);
911 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, alignment
,
913 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
914 res
->surf
.row_pitch_B
, flags
);
920 res
->aux
.bo
= res
->bo
;
921 iris_bo_reference(res
->aux
.bo
);
922 unsigned clear_color_state_size
=
923 iris_get_aux_clear_color_state_size(screen
);
924 if (!iris_resource_init_aux_buf(res
, flags
, clear_color_state_size
))
926 map_aux_addresses(screen
, res
);
929 if (templ
->bind
& PIPE_BIND_SHARED
)
930 iris_bo_make_external(res
->bo
);
935 fprintf(stderr
, "XXX: resource creation failed\n");
936 iris_resource_destroy(pscreen
, &res
->base
);
941 static struct pipe_resource
*
942 iris_resource_create(struct pipe_screen
*pscreen
,
943 const struct pipe_resource
*templ
)
945 if (templ
->target
== PIPE_BUFFER
)
946 return iris_resource_create_for_buffer(pscreen
, templ
);
948 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
952 tiling_to_modifier(uint32_t tiling
)
954 static const uint64_t map
[] = {
955 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
956 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
957 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
960 assert(tiling
< ARRAY_SIZE(map
));
965 static struct pipe_resource
*
966 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
967 const struct pipe_resource
*templ
,
970 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
971 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
972 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
976 assert(templ
->target
== PIPE_BUFFER
);
978 res
->internal_format
= templ
->format
;
979 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
980 user_memory
, templ
->width0
,
983 iris_resource_destroy(pscreen
, &res
->base
);
987 util_range_add(&res
->base
, &res
->valid_buffer_range
, 0, templ
->width0
);
992 static struct pipe_resource
*
993 iris_resource_from_handle(struct pipe_screen
*pscreen
,
994 const struct pipe_resource
*templ
,
995 struct winsys_handle
*whandle
,
998 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
999 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1000 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1001 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
1002 const struct isl_drm_modifier_info
*mod_inf
=
1003 isl_drm_modifier_get_info(whandle
->modifier
);
1009 switch (whandle
->type
) {
1010 case WINSYS_HANDLE_TYPE_FD
:
1012 tiling
= isl_tiling_to_i915_tiling(mod_inf
->tiling
);
1014 tiling
= I915_TILING_LAST
+ 1;
1015 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
,
1016 tiling
, whandle
->stride
);
1018 case WINSYS_HANDLE_TYPE_SHARED
:
1019 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
1023 unreachable("invalid winsys handle type");
1028 res
->offset
= whandle
->offset
;
1030 if (mod_inf
== NULL
) {
1032 isl_drm_modifier_get_info(tiling_to_modifier(res
->bo
->tiling_mode
));
1036 res
->external_format
= whandle
->format
;
1037 res
->mod_info
= mod_inf
;
1039 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
1041 const struct iris_format_info fmt
=
1042 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
1043 res
->internal_format
= templ
->format
;
1045 if (templ
->target
== PIPE_BUFFER
) {
1046 res
->surf
.tiling
= ISL_TILING_LINEAR
;
1048 /* Create a surface for each plane specified by the external format. */
1049 if (whandle
->plane
< util_format_get_num_planes(whandle
->format
)) {
1050 UNUSED
const bool isl_surf_created_successfully
=
1051 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
1052 .dim
= target_to_isl_surf_dim(templ
->target
),
1054 .width
= templ
->width0
,
1055 .height
= templ
->height0
,
1056 .depth
= templ
->depth0
,
1057 .levels
= templ
->last_level
+ 1,
1058 .array_len
= templ
->array_size
,
1059 .samples
= MAX2(templ
->nr_samples
, 1),
1060 .min_alignment_B
= 0,
1061 .row_pitch_B
= whandle
->stride
,
1063 .tiling_flags
= 1 << res
->mod_info
->tiling
);
1064 assert(isl_surf_created_successfully
);
1065 assert(res
->bo
->tiling_mode
==
1066 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
1068 // XXX: create_ccs_buf_for_image?
1069 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
) {
1070 if (!iris_resource_alloc_separate_aux(screen
, res
))
1073 if (res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1074 uint32_t alloc_flags
;
1076 bool ok
= iris_resource_configure_aux(screen
, res
, true, &size
,
1079 /* The gallium dri layer will create a separate plane resource
1080 * for the aux image. iris_resource_finish_aux_import will
1081 * merge the separate aux parameters back into a single
1087 /* Save modifier import information to reconstruct later. After
1088 * import, this will be available under a second image accessible
1089 * from the main image with res->base.next. See
1090 * iris_resource_finish_aux_import.
1092 res
->aux
.surf
.row_pitch_B
= whandle
->stride
;
1093 res
->aux
.offset
= whandle
->offset
;
1094 res
->aux
.bo
= res
->bo
;
1102 iris_resource_destroy(pscreen
, &res
->base
);
1107 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
1109 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1110 struct iris_resource
*res
= (void *) resource
;
1111 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
1113 iris_resource_prepare_access(ice
, res
,
1114 0, INTEL_REMAINING_LEVELS
,
1115 0, INTEL_REMAINING_LAYERS
,
1116 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
1117 mod
? mod
->supports_clear_color
: false);
1121 iris_resource_disable_aux_on_first_query(struct pipe_resource
*resource
,
1124 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1126 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1128 /* Disable aux usage if explicit flush not set and this is the first time
1129 * we are dealing with this resource and the resource was not created with
1130 * a modifier with aux.
1132 if (!mod_with_aux
&&
1133 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0) &&
1134 p_atomic_read(&resource
->reference
.count
) == 1) {
1135 iris_resource_disable_aux(res
);
1140 iris_resource_get_param(struct pipe_screen
*pscreen
,
1141 struct pipe_context
*context
,
1142 struct pipe_resource
*resource
,
1145 enum pipe_resource_param param
,
1146 unsigned handle_usage
,
1149 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
1150 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1152 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1153 bool wants_aux
= mod_with_aux
&& plane
> 0;
1157 if (iris_resource_unfinished_aux_import(res
))
1158 iris_resource_finish_aux_import(pscreen
, res
);
1160 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
1162 iris_resource_disable_aux_on_first_query(resource
, handle_usage
);
1165 case PIPE_RESOURCE_PARAM_NPLANES
:
1170 for (struct pipe_resource
*cur
= resource
; cur
; cur
= cur
->next
)
1175 case PIPE_RESOURCE_PARAM_STRIDE
:
1176 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
1178 case PIPE_RESOURCE_PARAM_OFFSET
:
1179 *value
= wants_aux
? res
->aux
.offset
: 0;
1181 case PIPE_RESOURCE_PARAM_MODIFIER
:
1182 *value
= res
->mod_info
? res
->mod_info
->modifier
:
1183 tiling_to_modifier(res
->bo
->tiling_mode
);
1185 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
1186 result
= iris_bo_flink(bo
, &handle
) == 0;
1190 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
: {
1191 /* Because we share the same drm file across multiple iris_screen, when
1192 * we export a GEM handle we must make sure it is valid in the DRM file
1193 * descriptor the caller is using (this is the FD given at screen
1197 if (iris_bo_export_gem_handle_for_device(bo
, screen
->winsys_fd
, &handle
))
1203 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
1204 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
1214 iris_resource_get_handle(struct pipe_screen
*pscreen
,
1215 struct pipe_context
*ctx
,
1216 struct pipe_resource
*resource
,
1217 struct winsys_handle
*whandle
,
1220 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
1221 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1223 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1225 iris_resource_disable_aux_on_first_query(resource
, usage
);
1228 if (mod_with_aux
&& whandle
->plane
> 0) {
1229 assert(res
->aux
.bo
);
1231 whandle
->stride
= res
->aux
.surf
.row_pitch_B
;
1232 whandle
->offset
= res
->aux
.offset
;
1234 /* If this is a buffer, stride should be 0 - no need to special case */
1235 whandle
->stride
= res
->surf
.row_pitch_B
;
1239 whandle
->format
= res
->external_format
;
1241 res
->mod_info
? res
->mod_info
->modifier
1242 : tiling_to_modifier(res
->bo
->tiling_mode
);
1245 enum isl_aux_usage allowed_usage
=
1246 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1248 if (res
->aux
.usage
!= allowed_usage
) {
1249 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
1250 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
1251 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
1255 switch (whandle
->type
) {
1256 case WINSYS_HANDLE_TYPE_SHARED
:
1257 return iris_bo_flink(bo
, &whandle
->handle
) == 0;
1258 case WINSYS_HANDLE_TYPE_KMS
: {
1259 /* Because we share the same drm file across multiple iris_screen, when
1260 * we export a GEM handle we must make sure it is valid in the DRM file
1261 * descriptor the caller is using (this is the FD given at screen
1265 if (iris_bo_export_gem_handle_for_device(bo
, screen
->winsys_fd
, &handle
))
1267 whandle
->handle
= handle
;
1270 case WINSYS_HANDLE_TYPE_FD
:
1271 return iris_bo_export_dmabuf(bo
, (int *) &whandle
->handle
) == 0;
1278 resource_is_busy(struct iris_context
*ice
,
1279 struct iris_resource
*res
)
1281 bool busy
= iris_bo_busy(res
->bo
);
1283 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1284 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1290 iris_invalidate_resource(struct pipe_context
*ctx
,
1291 struct pipe_resource
*resource
)
1293 struct iris_screen
*screen
= (void *) ctx
->screen
;
1294 struct iris_context
*ice
= (void *) ctx
;
1295 struct iris_resource
*res
= (void *) resource
;
1297 if (resource
->target
!= PIPE_BUFFER
)
1300 /* If it's already invalidated, don't bother doing anything. */
1301 if (res
->valid_buffer_range
.start
> res
->valid_buffer_range
.end
)
1304 if (!resource_is_busy(ice
, res
)) {
1305 /* The resource is idle, so just mark that it contains no data and
1306 * keep using the same underlying buffer object.
1308 util_range_set_empty(&res
->valid_buffer_range
);
1312 /* Otherwise, try and replace the backing storage with a new BO. */
1314 /* We can't reallocate memory we didn't allocate in the first place. */
1315 if (res
->bo
->userptr
)
1318 // XXX: We should support this.
1319 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1322 struct iris_bo
*old_bo
= res
->bo
;
1323 struct iris_bo
*new_bo
=
1324 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1325 iris_memzone_for_address(old_bo
->gtt_offset
));
1329 /* Swap out the backing storage */
1332 /* Rebind the buffer, replacing any state referring to the old BO's
1333 * address, and marking state dirty so it's reemitted.
1335 screen
->vtbl
.rebind_buffer(ice
, res
);
1337 util_range_set_empty(&res
->valid_buffer_range
);
1339 iris_bo_unreference(old_bo
);
1343 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1344 const struct pipe_box
*flush_box
)
1346 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1349 struct iris_transfer
*map
= (void *) xfer
;
1351 struct pipe_box src_box
= *flush_box
;
1353 /* Account for extra alignment padding in staging buffer */
1354 if (xfer
->resource
->target
== PIPE_BUFFER
)
1355 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1357 struct pipe_box dst_box
= (struct pipe_box
) {
1358 .x
= xfer
->box
.x
+ flush_box
->x
,
1359 .y
= xfer
->box
.y
+ flush_box
->y
,
1360 .z
= xfer
->box
.z
+ flush_box
->z
,
1361 .width
= flush_box
->width
,
1362 .height
= flush_box
->height
,
1363 .depth
= flush_box
->depth
,
1366 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1367 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1372 iris_unmap_copy_region(struct iris_transfer
*map
)
1374 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1380 iris_map_copy_region(struct iris_transfer
*map
)
1382 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1383 struct pipe_transfer
*xfer
= &map
->base
;
1384 struct pipe_box
*box
= &xfer
->box
;
1385 struct iris_resource
*res
= (void *) xfer
->resource
;
1387 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1388 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1390 struct pipe_resource templ
= (struct pipe_resource
) {
1391 .usage
= PIPE_USAGE_STAGING
,
1392 .width0
= box
->width
+ extra
,
1393 .height0
= box
->height
,
1395 .nr_samples
= xfer
->resource
->nr_samples
,
1396 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1397 .array_size
= box
->depth
,
1398 .format
= res
->internal_format
,
1401 if (xfer
->resource
->target
== PIPE_BUFFER
)
1402 templ
.target
= PIPE_BUFFER
;
1403 else if (templ
.array_size
> 1)
1404 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1406 templ
.target
= PIPE_TEXTURE_2D
;
1408 map
->staging
= iris_resource_create(pscreen
, &templ
);
1409 assert(map
->staging
);
1411 if (templ
.target
!= PIPE_BUFFER
) {
1412 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1413 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1414 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1417 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1418 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1419 xfer
->resource
, xfer
->level
, box
);
1420 /* Ensure writes to the staging BO land before we map it below. */
1421 iris_emit_pipe_control_flush(map
->batch
,
1422 "transfer read: flush before mapping",
1423 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1424 PIPE_CONTROL_CS_STALL
);
1427 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1429 if (iris_batch_references(map
->batch
, staging_bo
))
1430 iris_batch_flush(map
->batch
);
1433 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1435 map
->unmap
= iris_unmap_copy_region
;
1439 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1440 unsigned *out_x0_el
, unsigned *out_y0_el
)
1442 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1443 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1445 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1450 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1451 * different tiling patterns.
1454 iris_resource_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1455 uint32_t *tile_w
, uint32_t *tile_h
)
1466 case ISL_TILING_LINEAR
:
1471 unreachable("not reached");
1477 * This function computes masks that may be used to select the bits of the X
1478 * and Y coordinates that indicate the offset within a tile. If the BO is
1479 * untiled, the masks are set to 0.
1482 iris_resource_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1483 uint32_t *mask_x
, uint32_t *mask_y
)
1485 uint32_t tile_w_bytes
, tile_h
;
1487 iris_resource_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1489 *mask_x
= tile_w_bytes
/ cpp
- 1;
1490 *mask_y
= tile_h
- 1;
1494 * Compute the offset (in bytes) from the start of the BO to the given x
1495 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1496 * multiples of the tile size.
1499 iris_resource_get_aligned_offset(const struct iris_resource
*res
,
1500 uint32_t x
, uint32_t y
)
1502 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1503 unsigned cpp
= fmtl
->bpb
/ 8;
1504 uint32_t pitch
= res
->surf
.row_pitch_B
;
1506 switch (res
->surf
.tiling
) {
1508 unreachable("not reached");
1509 case ISL_TILING_LINEAR
:
1510 return y
* pitch
+ x
* cpp
;
1512 assert((x
% (512 / cpp
)) == 0);
1513 assert((y
% 8) == 0);
1514 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1516 assert((x
% (128 / cpp
)) == 0);
1517 assert((y
% 32) == 0);
1518 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1523 * Rendering with tiled buffers requires that the base address of the buffer
1524 * be aligned to a page boundary. For renderbuffers, and sometimes with
1525 * textures, we may want the surface to point at a texture image level that
1526 * isn't at a page boundary.
1528 * This function returns an appropriately-aligned base offset
1529 * according to the tiling restrictions, plus any required x/y offset
1533 iris_resource_get_tile_offsets(const struct iris_resource
*res
,
1534 uint32_t level
, uint32_t z
,
1535 uint32_t *tile_x
, uint32_t *tile_y
)
1538 uint32_t mask_x
, mask_y
;
1540 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1541 const unsigned cpp
= fmtl
->bpb
/ 8;
1543 iris_resource_get_tile_masks(res
->surf
.tiling
, cpp
, &mask_x
, &mask_y
);
1544 get_image_offset_el(&res
->surf
, level
, z
, &x
, &y
);
1546 *tile_x
= x
& mask_x
;
1547 *tile_y
= y
& mask_y
;
1549 return iris_resource_get_aligned_offset(res
, x
& ~mask_x
, y
& ~mask_y
);
1553 * Get pointer offset into stencil buffer.
1555 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1556 * must decode the tile's layout in software.
1559 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1561 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1563 * Even though the returned offset is always positive, the return type is
1565 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1566 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1569 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
)
1571 uint32_t tile_size
= 4096;
1572 uint32_t tile_width
= 64;
1573 uint32_t tile_height
= 64;
1574 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1576 uint32_t tile_x
= x
/ tile_width
;
1577 uint32_t tile_y
= y
/ tile_height
;
1579 /* The byte's address relative to the tile's base addres. */
1580 uint32_t byte_x
= x
% tile_width
;
1581 uint32_t byte_y
= y
% tile_height
;
1583 uintptr_t u
= tile_y
* row_size
1584 + tile_x
* tile_size
1585 + 512 * (byte_x
/ 8)
1587 + 32 * ((byte_y
/ 4) % 2)
1588 + 16 * ((byte_x
/ 4) % 2)
1589 + 8 * ((byte_y
/ 2) % 2)
1590 + 4 * ((byte_x
/ 2) % 2)
1598 iris_unmap_s8(struct iris_transfer
*map
)
1600 struct pipe_transfer
*xfer
= &map
->base
;
1601 const struct pipe_box
*box
= &xfer
->box
;
1602 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1603 struct isl_surf
*surf
= &res
->surf
;
1605 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1606 uint8_t *untiled_s8_map
= map
->ptr
;
1607 uint8_t *tiled_s8_map
=
1608 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1610 for (int s
= 0; s
< box
->depth
; s
++) {
1611 unsigned x0_el
, y0_el
;
1612 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1614 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1615 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1616 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1618 y0_el
+ box
->y
+ y
);
1619 tiled_s8_map
[offset
] =
1620 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1630 iris_map_s8(struct iris_transfer
*map
)
1632 struct pipe_transfer
*xfer
= &map
->base
;
1633 const struct pipe_box
*box
= &xfer
->box
;
1634 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1635 struct isl_surf
*surf
= &res
->surf
;
1637 xfer
->stride
= surf
->row_pitch_B
;
1638 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1640 /* The tiling and detiling functions require that the linear buffer has
1641 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1642 * over-allocate the linear buffer to get the proper alignment.
1644 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1645 assert(map
->buffer
);
1647 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1648 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1649 * invalidate is set, since we'll be writing the whole rectangle from our
1650 * temporary buffer back out.
1652 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1653 uint8_t *untiled_s8_map
= map
->ptr
;
1654 uint8_t *tiled_s8_map
=
1655 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1657 for (int s
= 0; s
< box
->depth
; s
++) {
1658 unsigned x0_el
, y0_el
;
1659 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1661 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1662 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1663 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1665 y0_el
+ box
->y
+ y
);
1666 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1667 tiled_s8_map
[offset
];
1673 map
->unmap
= iris_unmap_s8
;
1676 /* Compute extent parameters for use with tiled_memcpy functions.
1677 * xs are in units of bytes and ys are in units of strides.
1680 tile_extents(const struct isl_surf
*surf
,
1681 const struct pipe_box
*box
,
1682 unsigned level
, int z
,
1683 unsigned *x1_B
, unsigned *x2_B
,
1684 unsigned *y1_el
, unsigned *y2_el
)
1686 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1687 const unsigned cpp
= fmtl
->bpb
/ 8;
1689 assert(box
->x
% fmtl
->bw
== 0);
1690 assert(box
->y
% fmtl
->bh
== 0);
1692 unsigned x0_el
, y0_el
;
1693 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1695 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1696 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1697 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1698 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1702 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1704 struct pipe_transfer
*xfer
= &map
->base
;
1705 const struct pipe_box
*box
= &xfer
->box
;
1706 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1707 struct isl_surf
*surf
= &res
->surf
;
1709 const bool has_swizzling
= false;
1711 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1713 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1715 for (int s
= 0; s
< box
->depth
; s
++) {
1716 unsigned x1
, x2
, y1
, y2
;
1717 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1719 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1721 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1722 surf
->row_pitch_B
, xfer
->stride
,
1723 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1726 os_free_aligned(map
->buffer
);
1727 map
->buffer
= map
->ptr
= NULL
;
1731 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1733 struct pipe_transfer
*xfer
= &map
->base
;
1734 const struct pipe_box
*box
= &xfer
->box
;
1735 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1736 struct isl_surf
*surf
= &res
->surf
;
1738 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1739 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1741 unsigned x1
, x2
, y1
, y2
;
1742 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1744 /* The tiling and detiling functions require that the linear buffer has
1745 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1746 * over-allocate the linear buffer to get the proper alignment.
1749 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1750 assert(map
->buffer
);
1751 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1753 const bool has_swizzling
= false;
1755 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1757 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1759 for (int s
= 0; s
< box
->depth
; s
++) {
1760 unsigned x1
, x2
, y1
, y2
;
1761 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1763 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1764 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1766 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1767 surf
->row_pitch_B
, has_swizzling
,
1768 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1772 map
->unmap
= iris_unmap_tiled_memcpy
;
1776 iris_map_direct(struct iris_transfer
*map
)
1778 struct pipe_transfer
*xfer
= &map
->base
;
1779 struct pipe_box
*box
= &xfer
->box
;
1780 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1782 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1784 if (res
->base
.target
== PIPE_BUFFER
) {
1786 xfer
->layer_stride
= 0;
1788 map
->ptr
= ptr
+ box
->x
;
1790 struct isl_surf
*surf
= &res
->surf
;
1791 const struct isl_format_layout
*fmtl
=
1792 isl_format_get_layout(surf
->format
);
1793 const unsigned cpp
= fmtl
->bpb
/ 8;
1794 unsigned x0_el
, y0_el
;
1796 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1798 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1799 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1801 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1806 can_promote_to_async(const struct iris_resource
*res
,
1807 const struct pipe_box
*box
,
1808 enum pipe_transfer_usage usage
)
1810 /* If we're writing to a section of the buffer that hasn't even been
1811 * initialized with useful data, then we can safely promote this write
1812 * to be unsynchronized. This helps the common pattern of appending data.
1814 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1815 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1816 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1817 box
->x
+ box
->width
);
1821 iris_transfer_map(struct pipe_context
*ctx
,
1822 struct pipe_resource
*resource
,
1824 enum pipe_transfer_usage usage
,
1825 const struct pipe_box
*box
,
1826 struct pipe_transfer
**ptransfer
)
1828 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1829 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1830 struct isl_surf
*surf
= &res
->surf
;
1832 if (iris_resource_unfinished_aux_import(res
))
1833 iris_resource_finish_aux_import(ctx
->screen
, res
);
1835 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1836 /* Replace the backing storage with a fresh buffer for non-async maps */
1837 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1838 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1839 iris_invalidate_resource(ctx
, resource
);
1841 /* If we can discard the whole resource, we can discard the range. */
1842 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1845 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1846 can_promote_to_async(res
, box
, usage
)) {
1847 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1850 bool need_resolve
= false;
1851 bool need_color_resolve
= false;
1853 if (resource
->target
!= PIPE_BUFFER
) {
1854 bool need_hiz_resolve
= iris_resource_level_has_hiz(res
, level
);
1855 bool need_stencil_resolve
= res
->aux
.usage
== ISL_AUX_USAGE_STC_CCS
;
1857 need_color_resolve
=
1858 (res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
||
1859 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) &&
1860 iris_has_color_unresolved(res
, level
, 1, box
->z
, box
->depth
);
1862 need_resolve
= need_color_resolve
||
1864 need_stencil_resolve
;
1867 bool map_would_stall
= false;
1869 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1870 map_would_stall
= need_resolve
|| resource_is_busy(ice
, res
);
1872 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1873 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1877 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1878 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1881 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1882 struct pipe_transfer
*xfer
= &map
->base
;
1887 memset(map
, 0, sizeof(*map
));
1888 map
->dbg
= &ice
->dbg
;
1890 pipe_resource_reference(&xfer
->resource
, resource
);
1891 xfer
->level
= level
;
1892 xfer
->usage
= usage
;
1896 map
->dest_had_defined_contents
=
1897 util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1898 box
->x
+ box
->width
);
1900 if (usage
& PIPE_TRANSFER_WRITE
)
1901 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1903 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1904 * there is to access them simultaneously on the CPU & GPU. This also
1905 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1906 * contain state we're constructing for a GPU draw call, which would
1907 * kill us with infinite stack recursion.
1909 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1910 PIPE_TRANSFER_COHERENT
|
1911 PIPE_TRANSFER_MAP_DIRECTLY
);
1913 /* GPU copies are not useful for buffer reads. Instead of stalling to
1914 * read from the original buffer, we'd simply copy it to a temporary...
1915 * then stall (a bit longer) to read from that buffer.
1917 * Images are less clear-cut. Color resolves are destructive, removing
1918 * the underlying compression, so we'd rather blit the data to a linear
1919 * temporary and map that, to avoid the resolve. (It might be better to
1920 * a tiled temporary and use the tiled_memcpy paths...)
1922 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) && !need_color_resolve
)
1925 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1926 if (fmtl
->txc
== ISL_TXC_ASTC
)
1929 if ((map_would_stall
|| res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) && !no_gpu
) {
1930 /* If we need a synchronous mapping and the resource is busy, or needs
1931 * resolving, we copy to/from a linear temporary buffer using the GPU.
1933 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1934 map
->blorp
= &ice
->blorp
;
1935 iris_map_copy_region(map
);
1937 /* Otherwise we're free to map on the CPU. */
1940 iris_resource_access_raw(ice
, res
, level
, box
->z
, box
->depth
,
1941 usage
& PIPE_TRANSFER_WRITE
);
1944 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1945 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1946 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1947 iris_batch_flush(&ice
->batches
[i
]);
1951 if (surf
->tiling
== ISL_TILING_W
) {
1952 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1954 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1955 iris_map_tiled_memcpy(map
);
1957 iris_map_direct(map
);
1965 iris_transfer_flush_region(struct pipe_context
*ctx
,
1966 struct pipe_transfer
*xfer
,
1967 const struct pipe_box
*box
)
1969 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1970 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1971 struct iris_transfer
*map
= (void *) xfer
;
1974 iris_flush_staging_region(xfer
, box
);
1976 uint32_t history_flush
= 0;
1978 if (res
->base
.target
== PIPE_BUFFER
) {
1980 history_flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
1982 if (map
->dest_had_defined_contents
)
1983 history_flush
|= iris_flush_bits_for_history(res
);
1985 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1988 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
1989 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1990 struct iris_batch
*batch
= &ice
->batches
[i
];
1991 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
1992 iris_batch_maybe_flush(batch
, 24);
1993 iris_emit_pipe_control_flush(batch
,
1994 "cache history: transfer flush",
2000 /* Make sure we flag constants dirty even if there's no need to emit
2001 * any PIPE_CONTROLs to a batch.
2003 iris_dirty_for_history(ice
, res
);
2007 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
2009 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2010 struct iris_transfer
*map
= (void *) xfer
;
2012 if (!(xfer
->usage
& (PIPE_TRANSFER_FLUSH_EXPLICIT
|
2013 PIPE_TRANSFER_COHERENT
))) {
2014 struct pipe_box flush_box
= {
2015 .x
= 0, .y
= 0, .z
= 0,
2016 .width
= xfer
->box
.width
,
2017 .height
= xfer
->box
.height
,
2018 .depth
= xfer
->box
.depth
,
2020 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
2026 pipe_resource_reference(&xfer
->resource
, NULL
);
2027 slab_free(&ice
->transfer_pool
, map
);
2031 * Mark state dirty that needs to be re-emitted when a resource is written.
2034 iris_dirty_for_history(struct iris_context
*ice
,
2035 struct iris_resource
*res
)
2037 uint64_t stage_dirty
= 0ull;
2039 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2040 stage_dirty
|= ((uint64_t)res
->bind_stages
)
2041 << IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS
;
2044 ice
->state
.stage_dirty
|= stage_dirty
;
2048 * Produce a set of PIPE_CONTROL bits which ensure data written to a
2049 * resource becomes visible, and any stale read cache data is invalidated.
2052 iris_flush_bits_for_history(struct iris_resource
*res
)
2054 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
2056 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2057 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
2058 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2061 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
2062 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2064 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
2065 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
2067 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
2068 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
2074 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
2075 struct iris_batch
*batch
,
2076 struct iris_resource
*res
,
2077 uint32_t extra_flags
,
2080 if (res
->base
.target
!= PIPE_BUFFER
)
2083 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
2085 iris_emit_pipe_control_flush(batch
, reason
, flush
);
2087 iris_dirty_for_history(ice
, res
);
2091 iris_resource_set_clear_color(struct iris_context
*ice
,
2092 struct iris_resource
*res
,
2093 union isl_color_value color
)
2095 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
2096 res
->aux
.clear_color
= color
;
2103 union isl_color_value
2104 iris_resource_get_clear_color(const struct iris_resource
*res
,
2105 struct iris_bo
**clear_color_bo
,
2106 uint64_t *clear_color_offset
)
2108 assert(res
->aux
.bo
);
2111 *clear_color_bo
= res
->aux
.clear_color_bo
;
2112 if (clear_color_offset
)
2113 *clear_color_offset
= res
->aux
.clear_color_offset
;
2114 return res
->aux
.clear_color
;
2117 static enum pipe_format
2118 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
2120 struct iris_resource
*res
= (void *) p_res
;
2121 return res
->internal_format
;
2124 static const struct u_transfer_vtbl transfer_vtbl
= {
2125 .resource_create
= iris_resource_create
,
2126 .resource_destroy
= iris_resource_destroy
,
2127 .transfer_map
= iris_transfer_map
,
2128 .transfer_unmap
= iris_transfer_unmap
,
2129 .transfer_flush_region
= iris_transfer_flush_region
,
2130 .get_internal_format
= iris_resource_get_internal_format
,
2131 .set_stencil
= iris_resource_set_separate_stencil
,
2132 .get_stencil
= iris_resource_get_separate_stencil
,
2136 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
2138 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
2139 pscreen
->resource_create_with_modifiers
=
2140 iris_resource_create_with_modifiers
;
2141 pscreen
->resource_create
= u_transfer_helper_resource_create
;
2142 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
2143 pscreen
->resource_from_handle
= iris_resource_from_handle
;
2144 pscreen
->resource_get_handle
= iris_resource_get_handle
;
2145 pscreen
->resource_get_param
= iris_resource_get_param
;
2146 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
2147 pscreen
->transfer_helper
=
2148 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
2152 iris_init_resource_functions(struct pipe_context
*ctx
)
2154 ctx
->flush_resource
= iris_flush_resource
;
2155 ctx
->invalidate_resource
= iris_invalidate_resource
;
2156 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
2157 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
2158 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
2159 ctx
->buffer_subdata
= u_default_buffer_subdata
;
2160 ctx
->texture_subdata
= u_default_texture_subdata
;