src/gallium/drivers/iris/iris_resource.h

   1 /*
   2  * Copyright 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_RESOURCE_H
  24 #define IRIS_RESOURCE_H
  25
  26 #include "pipe/p_state.h"
  27 #include "util/u_inlines.h"
  28 #include "intel/isl/isl.h"
  29
  30 struct iris_batch;
  31 struct iris_context;
  32
  33 #define IRIS_MAX_MIPLEVELS 15
  34
  35 struct iris_format_info {
  36    enum isl_format fmt;
  37    struct isl_swizzle swizzle;
  38 };
  39
  40 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE  (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  41 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  42 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  43
  44 /**
  45  * Resources represent a GPU buffer object or image (mipmap tree).
  46  *
  47  * They contain the storage (BO) and layout information (ISL surface).
  48  */
  49 struct iris_resource {
  50    struct pipe_resource base;
  51    enum pipe_format internal_format;
  52
  53    /**
  54     * The ISL surface layout information for this resource.
  55     *
  56     * This is not filled out for PIPE_BUFFER resources, but is guaranteed
  57     * to be zeroed.  Note that this also guarantees that res->surf.tiling
  58     * will be ISL_TILING_LINEAR, so it's safe to check that.
  59     */
  60    struct isl_surf surf;
  61
  62    /** Backing storage for the resource */
  63    struct iris_bo *bo;
  64
  65    /**
  66     * A bitfield of PIPE_BIND_* indicating how this resource was bound
  67     * in the past.  Only meaningful for PIPE_BUFFER; used for flushing.
  68     */
  69    unsigned bind_history;
  70
  71    /**
  72     * Auxiliary buffer information (CCS, MCS, or HiZ).
  73     */
  74    struct {
  75       /** The surface layout for the auxiliary buffer. */
  76       struct isl_surf surf;
  77
  78       /** The buffer object containing the auxiliary data. */
  79       struct iris_bo *bo;
  80
  81       /** Offset into 'bo' where the auxiliary surface starts. */
  82       uint32_t offset;
  83
  84       /**
  85        * \brief The type of auxiliary compression used by this resource.
  86        *
  87        * This describes the type of auxiliary compression that is intended to
  88        * be used by this resource.  An aux usage of ISL_AUX_USAGE_NONE means
  89        * that auxiliary compression is permanently disabled.  An aux usage
  90        * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
  91        * compression will always be enabled for this surface.
  92        */
  93       enum isl_aux_usage usage;
  94
  95       /**
  96        * A bitfield of ISL_AUX_* modes that might this resource might use.
  97        *
  98        * For example, a surface might use both CCS_E and CCS_D at times.
  99        */
 100       unsigned possible_usages;
 101
 102       /**
 103        * \brief Maps miptree slices to their current aux state.
 104        *
 105        * This two-dimensional array is indexed as [level][layer] and stores an
 106        * aux state for each slice.
 107        */
 108       enum isl_aux_state **state;
 109    } aux;
 110 };
 111
 112 /**
 113  * A simple <resource, offset> tuple for storing a reference to a
 114  * piece of state stored in a GPU buffer object.
 115  */
 116 struct iris_state_ref {
 117    struct pipe_resource *res;
 118    uint32_t offset;
 119 };
 120
 121 /**
 122  * Gallium CSO for sampler views (texture views).
 123  *
 124  * In addition to the normal pipe_resource, this adds an ISL view
 125  * which may reinterpret the format or restrict levels/layers.
 126  *
 127  * These can also be linear texture buffers.
 128  */
 129 struct iris_sampler_view {
 130    struct pipe_sampler_view base;
 131    struct isl_view view;
 132
 133    /* A short-cut (not a reference) to the actual resource being viewed.
 134     * Multi-planar (or depth+stencil) images may have multiple resources
 135     * chained together; this skips having to traverse base->texture->*.
 136     */
 137    struct iris_resource *res;
 138
 139    /** The resource (BO) holding our SURFACE_STATE. */
 140    struct iris_state_ref surface_state;
 141 };
 142
 143 /**
 144  * Gallium CSO for surfaces (framebuffer attachments).
 145  *
 146  * A view of a surface that can be bound to a color render target or
 147  * depth/stencil attachment.
 148  */
 149 struct iris_surface {
 150    struct pipe_surface base;
 151    struct isl_view view;
 152
 153    /** The resource (BO) holding our SURFACE_STATE. */
 154    struct iris_state_ref surface_state;
 155 };
 156
 157 /**
 158  * Transfer object - information about a buffer mapping.
 159  */
 160 struct iris_transfer {
 161    struct pipe_transfer base;
 162    struct pipe_debug_callback *dbg;
 163    void *buffer;
 164    void *ptr;
 165
 166    void (*unmap)(struct iris_transfer *);
 167 };
 168
 169 /**
 170  * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
 171  */
 172 static inline struct iris_bo *
 173 iris_resource_bo(struct pipe_resource *p_res)
 174 {
 175    struct iris_resource *res = (void *) p_res;
 176    return res->bo;
 177 }
 178
 179 struct iris_format_info iris_format_for_usage(const struct gen_device_info *,
 180                                               enum pipe_format pf,
 181                                               isl_surf_usage_flags_t usage);
 182
 183 struct pipe_resource *iris_resource_get_separate_stencil(struct pipe_resource *);
 184
 185 void iris_get_depth_stencil_resources(struct pipe_resource *res,
 186                                       struct iris_resource **out_z,
 187                                       struct iris_resource **out_s);
 188
 189 void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
 190
 191 void iris_flush_and_dirty_for_history(struct iris_context *ice,
 192                                       struct iris_batch *batch,
 193                                       struct iris_resource *res);
 194
 195 unsigned iris_get_num_logical_layers(const struct iris_resource *res,
 196                                      unsigned level);
 197
 198 #endif