2 * Copyright 2017 Intel Corporation
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9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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23 #ifndef IRIS_RESOURCE_H
24 #define IRIS_RESOURCE_H
26 #include "pipe/p_state.h"
27 #include "util/u_inlines.h"
28 #include "intel/isl/isl.h"
33 #define IRIS_MAX_MIPLEVELS 15
35 struct iris_format_info
{
37 struct isl_swizzle swizzle
;
40 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
41 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
42 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
44 enum gen9_astc5x5_wa_tex_type
{
45 GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
= 1 << 0,
46 GEN9_ASTC5X5_WA_TEX_TYPE_AUX
= 1 << 1,
50 * Resources represent a GPU buffer object or image (mipmap tree).
52 * They contain the storage (BO) and layout information (ISL surface).
54 struct iris_resource
{
55 struct pipe_resource base
;
56 enum pipe_format internal_format
;
59 * The ISL surface layout information for this resource.
61 * This is not filled out for PIPE_BUFFER resources, but is guaranteed
62 * to be zeroed. Note that this also guarantees that res->surf.tiling
63 * will be ISL_TILING_LINEAR, so it's safe to check that.
67 /** Backing storage for the resource */
71 * A bitfield of PIPE_BIND_* indicating how this resource was bound
72 * in the past. Only meaningful for PIPE_BUFFER; used for flushing.
74 unsigned bind_history
;
77 * Auxiliary buffer information (CCS, MCS, or HiZ).
80 /** The surface layout for the auxiliary buffer. */
83 /** The buffer object containing the auxiliary data. */
86 /** Offset into 'bo' where the auxiliary surface starts. */
90 * Fast clear color for this surface. For depth surfaces, the clear
91 * value is stored as a float32 in the red component.
93 union isl_color_value clear_color
;
95 /** Buffer object containing the indirect clear color. */
96 struct iris_bo
*clear_color_bo
;
98 /** Offset into bo where the clear color can be found. */
99 uint64_t clear_color_offset
;
102 * \brief The type of auxiliary compression used by this resource.
104 * This describes the type of auxiliary compression that is intended to
105 * be used by this resource. An aux usage of ISL_AUX_USAGE_NONE means
106 * that auxiliary compression is permanently disabled. An aux usage
107 * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
108 * compression will always be enabled for this surface.
110 enum isl_aux_usage usage
;
113 * A bitfield of ISL_AUX_* modes that might this resource might use.
115 * For example, a surface might use both CCS_E and CCS_D at times.
117 unsigned possible_usages
;
120 * \brief Maps miptree slices to their current aux state.
122 * This two-dimensional array is indexed as [level][layer] and stores an
123 * aux state for each slice.
125 enum isl_aux_state
**state
;
128 * If (1 << level) is set, HiZ is enabled for that miplevel.
134 * For external surfaces, this is DRM format modifier that was used to
135 * create or import the surface. For internal surfaces, this will always
136 * be DRM_FORMAT_MOD_INVALID.
138 const struct isl_drm_modifier_info
*mod_info
;
142 * A simple <resource, offset> tuple for storing a reference to a
143 * piece of state stored in a GPU buffer object.
145 struct iris_state_ref
{
146 struct pipe_resource
*res
;
151 * Gallium CSO for sampler views (texture views).
153 * In addition to the normal pipe_resource, this adds an ISL view
154 * which may reinterpret the format or restrict levels/layers.
156 * These can also be linear texture buffers.
158 struct iris_sampler_view
{
159 struct pipe_sampler_view base
;
160 struct isl_view view
;
162 /* A short-cut (not a reference) to the actual resource being viewed.
163 * Multi-planar (or depth+stencil) images may have multiple resources
164 * chained together; this skips having to traverse base->texture->*.
166 struct iris_resource
*res
;
168 /** The resource (BO) holding our SURFACE_STATE. */
169 struct iris_state_ref surface_state
;
173 * Gallium CSO for surfaces (framebuffer attachments).
175 * A view of a surface that can be bound to a color render target or
176 * depth/stencil attachment.
178 struct iris_surface
{
179 struct pipe_surface base
;
180 struct isl_view view
;
182 /** The resource (BO) holding our SURFACE_STATE. */
183 struct iris_state_ref surface_state
;
187 * Transfer object - information about a buffer mapping.
189 struct iris_transfer
{
190 struct pipe_transfer base
;
191 struct pipe_debug_callback
*dbg
;
195 /** A linear staging resource for GPU-based copy_region transfers. */
196 struct pipe_resource
*staging
;
197 struct blorp_context
*blorp
;
198 struct iris_batch
*batch
;
200 void (*unmap
)(struct iris_transfer
*);
204 * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
206 static inline struct iris_bo
*
207 iris_resource_bo(struct pipe_resource
*p_res
)
209 struct iris_resource
*res
= (void *) p_res
;
213 struct iris_format_info
iris_format_for_usage(const struct gen_device_info
*,
215 isl_surf_usage_flags_t usage
);
217 struct pipe_resource
*iris_resource_get_separate_stencil(struct pipe_resource
*);
219 void iris_get_depth_stencil_resources(struct pipe_resource
*res
,
220 struct iris_resource
**out_z
,
221 struct iris_resource
**out_s
);
222 bool iris_resource_set_clear_color(struct iris_context
*ice
,
223 struct iris_resource
*res
,
224 union isl_color_value color
);
225 union isl_color_value
226 iris_resource_get_clear_color(const struct iris_resource
*res
,
227 struct iris_bo
**clear_color_bo
,
228 uint64_t *clear_color_offset
);
230 void iris_init_screen_resource_functions(struct pipe_screen
*pscreen
);
232 void iris_flush_and_dirty_for_history(struct iris_context
*ice
,
233 struct iris_batch
*batch
,
234 struct iris_resource
*res
);
236 unsigned iris_get_num_logical_layers(const struct iris_resource
*res
,
239 void iris_resource_disable_aux(struct iris_resource
*res
);
241 #define INTEL_REMAINING_LAYERS UINT32_MAX
242 #define INTEL_REMAINING_LEVELS UINT32_MAX
245 iris_hiz_exec(struct iris_context
*ice
,
246 struct iris_batch
*batch
,
247 struct iris_resource
*res
,
248 unsigned int level
, unsigned int start_layer
,
249 unsigned int num_layers
, enum isl_aux_op op
);
252 * Prepare a miptree for access
254 * This function should be called prior to any access to miptree in order to
255 * perform any needed resolves.
257 * \param[in] start_level The first mip level to be accessed
259 * \param[in] num_levels The number of miplevels to be accessed or
260 * INTEL_REMAINING_LEVELS to indicate every level
261 * above start_level will be accessed
263 * \param[in] start_layer The first array slice or 3D layer to be accessed
265 * \param[in] num_layers The number of array slices or 3D layers be
266 * accessed or INTEL_REMAINING_LAYERS to indicate
267 * every layer above start_layer will be accessed
269 * \param[in] aux_supported Whether or not the access will support the
270 * miptree's auxiliary compression format; this
271 * must be false for uncompressed miptrees
273 * \param[in] fast_clear_supported Whether or not the access will support
274 * fast clears in the miptree's auxiliary
278 iris_resource_prepare_access(struct iris_context
*ice
,
279 struct iris_batch
*batch
,
280 struct iris_resource
*res
,
281 uint32_t start_level
, uint32_t num_levels
,
282 uint32_t start_layer
, uint32_t num_layers
,
283 enum isl_aux_usage aux_usage
,
284 bool fast_clear_supported
);
287 * Complete a write operation
289 * This function should be called after any operation writes to a miptree.
290 * This will update the miptree's compression state so that future resolves
291 * happen correctly. Technically, this function can be called before the
292 * write occurs but the caller must ensure that they don't interlace
293 * iris_resource_prepare_access and iris_resource_finish_write calls to
294 * overlapping layer/level ranges.
296 * \param[in] level The mip level that was written
298 * \param[in] start_layer The first array slice or 3D layer written
300 * \param[in] num_layers The number of array slices or 3D layers
301 * written or INTEL_REMAINING_LAYERS to indicate
302 * every layer above start_layer was written
304 * \param[in] written_with_aux Whether or not the write was done with
305 * auxiliary compression enabled
308 iris_resource_finish_write(struct iris_context
*ice
,
309 struct iris_resource
*res
, uint32_t level
,
310 uint32_t start_layer
, uint32_t num_layers
,
311 enum isl_aux_usage aux_usage
);
313 /** Get the auxiliary compression state of a miptree slice */
315 iris_resource_get_aux_state(const struct iris_resource
*res
,
316 uint32_t level
, uint32_t layer
);
319 * Set the auxiliary compression state of a miptree slice range
321 * This function directly sets the auxiliary compression state of a slice
322 * range of a miptree. It only modifies data structures and does not do any
323 * resolves. This should only be called by code which directly performs
324 * compression operations such as fast clears and resolves. Most code should
325 * use iris_resource_prepare_access or iris_resource_finish_write.
328 iris_resource_set_aux_state(struct iris_context
*ice
,
329 struct iris_resource
*res
, uint32_t level
,
330 uint32_t start_layer
, uint32_t num_layers
,
331 enum isl_aux_state aux_state
);
334 * Prepare a miptree for raw access
336 * This helper prepares the miptree for access that knows nothing about any
337 * sort of compression whatsoever. This is useful when mapping the surface or
338 * using it with the blitter.
341 iris_resource_access_raw(struct iris_context
*ice
,
342 struct iris_batch
*batch
,
343 struct iris_resource
*res
,
344 uint32_t level
, uint32_t layer
,
348 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, layer
, num_layers
,
349 ISL_AUX_USAGE_NONE
, false);
351 iris_resource_finish_write(ice
, res
, level
, layer
, num_layers
,
356 enum isl_aux_usage
iris_resource_texture_aux_usage(struct iris_context
*ice
,
357 const struct iris_resource
*res
,
358 enum isl_format view_fmt
,
359 enum gen9_astc5x5_wa_tex_type
);
360 void iris_resource_prepare_texture(struct iris_context
*ice
,
361 struct iris_batch
*batch
,
362 struct iris_resource
*res
,
363 enum isl_format view_format
,
364 uint32_t start_level
, uint32_t num_levels
,
365 uint32_t start_layer
, uint32_t num_layers
,
366 enum gen9_astc5x5_wa_tex_type
);
367 void iris_resource_prepare_image(struct iris_context
*ice
,
368 struct iris_batch
*batch
,
369 struct iris_resource
*res
);
371 void iris_resource_check_level_layer(const struct iris_resource
*res
,
372 uint32_t level
, uint32_t layer
);
374 bool iris_resource_level_has_hiz(const struct iris_resource
*res
,
377 enum isl_aux_usage
iris_resource_render_aux_usage(struct iris_context
*ice
,
378 struct iris_resource
*res
,
379 enum isl_format render_fmt
,
381 bool draw_aux_disabled
);
382 void iris_resource_prepare_render(struct iris_context
*ice
,
383 struct iris_batch
*batch
,
384 struct iris_resource
*res
, uint32_t level
,
385 uint32_t start_layer
, uint32_t layer_count
,
386 enum isl_aux_usage aux_usage
);
387 void iris_resource_finish_render(struct iris_context
*ice
,
388 struct iris_resource
*res
, uint32_t level
,
389 uint32_t start_layer
, uint32_t layer_count
,
390 enum isl_aux_usage aux_usage
);
391 void iris_resource_prepare_depth(struct iris_context
*ice
,
392 struct iris_batch
*batch
,
393 struct iris_resource
*res
, uint32_t level
,
394 uint32_t start_layer
, uint32_t layer_count
);
395 void iris_resource_finish_depth(struct iris_context
*ice
,
396 struct iris_resource
*res
, uint32_t level
,
397 uint32_t start_layer
, uint32_t layer_count
,