2 * Copyright 2017 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef IRIS_RESOURCE_H
24 #define IRIS_RESOURCE_H
26 #include "pipe/p_state.h"
27 #include "util/u_inlines.h"
28 #include "util/u_range.h"
29 #include "intel/isl/isl.h"
30 #include "iris_bufmgr.h"
36 #define IRIS_MAX_MIPLEVELS 15
38 struct iris_format_info
{
40 struct isl_swizzle swizzle
;
43 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
44 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
45 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
48 * Resources represent a GPU buffer object or image (mipmap tree).
50 * They contain the storage (BO) and layout information (ISL surface).
52 struct iris_resource
{
53 struct pipe_resource base
;
54 enum pipe_format internal_format
;
57 * The ISL surface layout information for this resource.
59 * This is not filled out for PIPE_BUFFER resources, but is guaranteed
60 * to be zeroed. Note that this also guarantees that res->surf.tiling
61 * will be ISL_TILING_LINEAR, so it's safe to check that.
65 /** Backing storage for the resource */
68 /** offset at which data starts in the BO */
72 * A bitfield of PIPE_BIND_* indicating how this resource was bound
73 * in the past. Only meaningful for PIPE_BUFFER; used for flushing.
75 unsigned bind_history
;
78 * A bitfield of MESA_SHADER_* stages indicating where this resource
84 * For PIPE_BUFFER resources, a range which may contain valid data.
86 * This is a conservative estimate of what part of the buffer contains
87 * valid data that we have to preserve. The rest of the buffer is
88 * considered invalid, and we can promote writes to that region to
89 * be unsynchronized writes, avoiding blit copies.
91 struct util_range valid_buffer_range
;
94 * Auxiliary buffer information (CCS, MCS, or HiZ).
97 /** The surface layout for the auxiliary buffer. */
100 /** The buffer object containing the auxiliary data. */
103 /** Offset into 'bo' where the auxiliary surface starts. */
107 struct isl_surf surf
;
109 /** Offset into 'bo' where the auxiliary surface starts. */
114 * Fast clear color for this surface. For depth surfaces, the clear
115 * value is stored as a float32 in the red component.
117 union isl_color_value clear_color
;
119 /** Buffer object containing the indirect clear color. */
120 struct iris_bo
*clear_color_bo
;
122 /** Offset into bo where the clear color can be found. */
123 uint64_t clear_color_offset
;
126 * \brief The type of auxiliary compression used by this resource.
128 * This describes the type of auxiliary compression that is intended to
129 * be used by this resource. An aux usage of ISL_AUX_USAGE_NONE means
130 * that auxiliary compression is permanently disabled. An aux usage
131 * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
132 * compression will always be enabled for this surface.
134 enum isl_aux_usage usage
;
137 * A bitfield of ISL_AUX_* modes that might this resource might use.
139 * For example, a surface might use both CCS_E and CCS_D at times.
141 unsigned possible_usages
;
144 * Same as possible_usages, but only with modes supported for sampling.
146 unsigned sampler_usages
;
149 * \brief Maps miptree slices to their current aux state.
151 * This two-dimensional array is indexed as [level][layer] and stores an
152 * aux state for each slice.
154 enum isl_aux_state
**state
;
157 * If (1 << level) is set, HiZ is enabled for that miplevel.
163 * For external surfaces, this is format that was used to create or import
164 * the surface. For internal surfaces, this will always be
167 enum pipe_format external_format
;
170 * For external surfaces, this is DRM format modifier that was used to
171 * create or import the surface. For internal surfaces, this will always
172 * be DRM_FORMAT_MOD_INVALID.
174 const struct isl_drm_modifier_info
*mod_info
;
178 * A simple <resource, offset> tuple for storing a reference to a
179 * piece of state stored in a GPU buffer object.
181 struct iris_state_ref
{
182 struct pipe_resource
*res
;
187 * The SURFACE_STATE descriptors for a resource.
189 struct iris_surface_state
{
191 * CPU-side copy of the packed SURFACE_STATE structures, already
192 * aligned so they can be uploaded as a contiguous pile of bytes.
194 * This can be updated and re-uploaded if (e.g.) addresses need to change.
199 * How many states are there? (Each aux mode has its own state.)
204 * Address of the resource (res->bo->gtt_offset). Note that "Surface
205 * Base Address" may be offset from this value.
209 /** A reference to the GPU buffer holding our uploaded SURFACE_STATE */
210 struct iris_state_ref ref
;
214 * Gallium CSO for sampler views (texture views).
216 * In addition to the normal pipe_resource, this adds an ISL view
217 * which may reinterpret the format or restrict levels/layers.
219 * These can also be linear texture buffers.
221 struct iris_sampler_view
{
222 struct pipe_sampler_view base
;
223 struct isl_view view
;
225 union isl_color_value clear_color
;
227 /* A short-cut (not a reference) to the actual resource being viewed.
228 * Multi-planar (or depth+stencil) images may have multiple resources
229 * chained together; this skips having to traverse base->texture->*.
231 struct iris_resource
*res
;
233 /** The resource (BO) holding our SURFACE_STATE. */
234 struct iris_surface_state surface_state
;
238 * Image view representation.
240 struct iris_image_view
{
241 struct pipe_image_view base
;
243 /** The resource (BO) holding our SURFACE_STATE. */
244 struct iris_surface_state surface_state
;
248 * Gallium CSO for surfaces (framebuffer attachments).
250 * A view of a surface that can be bound to a color render target or
251 * depth/stencil attachment.
253 struct iris_surface
{
254 struct pipe_surface base
;
255 struct isl_view view
;
256 struct isl_view read_view
;
257 union isl_color_value clear_color
;
259 /** The resource (BO) holding our SURFACE_STATE. */
260 struct iris_surface_state surface_state
;
261 /** The resource (BO) holding our SURFACE_STATE for read. */
262 struct iris_surface_state surface_state_read
;
266 * Transfer object - information about a buffer mapping.
268 struct iris_transfer
{
269 struct pipe_transfer base
;
270 struct pipe_debug_callback
*dbg
;
274 /** A linear staging resource for GPU-based copy_region transfers. */
275 struct pipe_resource
*staging
;
276 struct blorp_context
*blorp
;
277 struct iris_batch
*batch
;
279 bool dest_had_defined_contents
;
281 void (*unmap
)(struct iris_transfer
*);
285 * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
287 static inline struct iris_bo
*
288 iris_resource_bo(struct pipe_resource
*p_res
)
290 struct iris_resource
*res
= (void *) p_res
;
294 static inline uint32_t
295 iris_mocs(const struct iris_bo
*bo
, const struct isl_device
*dev
)
297 return bo
&& bo
->external
? dev
->mocs
.external
: dev
->mocs
.internal
;
300 struct iris_format_info
iris_format_for_usage(const struct gen_device_info
*,
302 isl_surf_usage_flags_t usage
);
304 struct pipe_resource
*iris_resource_get_separate_stencil(struct pipe_resource
*);
306 void iris_get_depth_stencil_resources(struct pipe_resource
*res
,
307 struct iris_resource
**out_z
,
308 struct iris_resource
**out_s
);
309 bool iris_resource_set_clear_color(struct iris_context
*ice
,
310 struct iris_resource
*res
,
311 union isl_color_value color
);
312 union isl_color_value
313 iris_resource_get_clear_color(const struct iris_resource
*res
,
314 struct iris_bo
**clear_color_bo
,
315 uint64_t *clear_color_offset
);
317 void iris_init_screen_resource_functions(struct pipe_screen
*pscreen
);
319 void iris_dirty_for_history(struct iris_context
*ice
,
320 struct iris_resource
*res
);
321 uint32_t iris_flush_bits_for_history(struct iris_resource
*res
);
323 void iris_flush_and_dirty_for_history(struct iris_context
*ice
,
324 struct iris_batch
*batch
,
325 struct iris_resource
*res
,
326 uint32_t extra_flags
,
329 unsigned iris_get_num_logical_layers(const struct iris_resource
*res
,
332 void iris_resource_disable_aux(struct iris_resource
*res
);
334 #define INTEL_REMAINING_LAYERS UINT32_MAX
335 #define INTEL_REMAINING_LEVELS UINT32_MAX
338 iris_hiz_exec(struct iris_context
*ice
,
339 struct iris_batch
*batch
,
340 struct iris_resource
*res
,
341 unsigned int level
, unsigned int start_layer
,
342 unsigned int num_layers
, enum isl_aux_op op
,
343 bool update_clear_depth
);
346 * Prepare a miptree for access
348 * This function should be called prior to any access to miptree in order to
349 * perform any needed resolves.
351 * \param[in] start_level The first mip level to be accessed
353 * \param[in] num_levels The number of miplevels to be accessed or
354 * INTEL_REMAINING_LEVELS to indicate every level
355 * above start_level will be accessed
357 * \param[in] start_layer The first array slice or 3D layer to be accessed
359 * \param[in] num_layers The number of array slices or 3D layers be
360 * accessed or INTEL_REMAINING_LAYERS to indicate
361 * every layer above start_layer will be accessed
363 * \param[in] aux_supported Whether or not the access will support the
364 * miptree's auxiliary compression format; this
365 * must be false for uncompressed miptrees
367 * \param[in] fast_clear_supported Whether or not the access will support
368 * fast clears in the miptree's auxiliary
372 iris_resource_prepare_access(struct iris_context
*ice
,
373 struct iris_batch
*batch
,
374 struct iris_resource
*res
,
375 uint32_t start_level
, uint32_t num_levels
,
376 uint32_t start_layer
, uint32_t num_layers
,
377 enum isl_aux_usage aux_usage
,
378 bool fast_clear_supported
);
381 * Complete a write operation
383 * This function should be called after any operation writes to a miptree.
384 * This will update the miptree's compression state so that future resolves
385 * happen correctly. Technically, this function can be called before the
386 * write occurs but the caller must ensure that they don't interlace
387 * iris_resource_prepare_access and iris_resource_finish_write calls to
388 * overlapping layer/level ranges.
390 * \param[in] level The mip level that was written
392 * \param[in] start_layer The first array slice or 3D layer written
394 * \param[in] num_layers The number of array slices or 3D layers
395 * written or INTEL_REMAINING_LAYERS to indicate
396 * every layer above start_layer was written
398 * \param[in] written_with_aux Whether or not the write was done with
399 * auxiliary compression enabled
402 iris_resource_finish_write(struct iris_context
*ice
,
403 struct iris_resource
*res
, uint32_t level
,
404 uint32_t start_layer
, uint32_t num_layers
,
405 enum isl_aux_usage aux_usage
);
407 /** Get the auxiliary compression state of a miptree slice */
409 iris_resource_get_aux_state(const struct iris_resource
*res
,
410 uint32_t level
, uint32_t layer
);
413 * Set the auxiliary compression state of a miptree slice range
415 * This function directly sets the auxiliary compression state of a slice
416 * range of a miptree. It only modifies data structures and does not do any
417 * resolves. This should only be called by code which directly performs
418 * compression operations such as fast clears and resolves. Most code should
419 * use iris_resource_prepare_access or iris_resource_finish_write.
422 iris_resource_set_aux_state(struct iris_context
*ice
,
423 struct iris_resource
*res
, uint32_t level
,
424 uint32_t start_layer
, uint32_t num_layers
,
425 enum isl_aux_state aux_state
);
428 * Prepare a miptree for raw access
430 * This helper prepares the miptree for access that knows nothing about any
431 * sort of compression whatsoever. This is useful when mapping the surface or
432 * using it with the blitter.
435 iris_resource_access_raw(struct iris_context
*ice
,
436 struct iris_batch
*batch
,
437 struct iris_resource
*res
,
438 uint32_t level
, uint32_t layer
,
442 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, layer
, num_layers
,
443 ISL_AUX_USAGE_NONE
, false);
445 iris_resource_finish_write(ice
, res
, level
, layer
, num_layers
,
450 enum isl_dim_layout
iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
451 enum isl_tiling tiling
,
452 enum pipe_texture_target target
);
453 enum isl_surf_dim
target_to_isl_surf_dim(enum pipe_texture_target target
);
454 uint32_t iris_resource_get_tile_offsets(const struct iris_resource
*res
,
455 uint32_t level
, uint32_t z
,
456 uint32_t *tile_x
, uint32_t *tile_y
);
457 enum isl_aux_usage
iris_resource_texture_aux_usage(struct iris_context
*ice
,
458 const struct iris_resource
*res
,
459 enum isl_format view_fmt
);
460 void iris_resource_prepare_texture(struct iris_context
*ice
,
461 struct iris_batch
*batch
,
462 struct iris_resource
*res
,
463 enum isl_format view_format
,
464 uint32_t start_level
, uint32_t num_levels
,
465 uint32_t start_layer
, uint32_t num_layers
);
467 enum isl_aux_usage
iris_image_view_aux_usage(struct iris_context
*ice
,
468 const struct pipe_image_view
*pview
,
469 const struct shader_info
*info
);
470 enum isl_format
iris_image_view_get_format(struct iris_context
*ice
,
471 const struct pipe_image_view
*img
);
474 iris_resource_unfinished_aux_import(struct iris_resource
*res
)
476 return res
->base
.next
!= NULL
&& res
->mod_info
&&
477 res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
480 void iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
481 struct iris_resource
*res
);
483 bool iris_has_color_unresolved(const struct iris_resource
*res
,
484 unsigned start_level
, unsigned num_levels
,
485 unsigned start_layer
, unsigned num_layers
);
487 void iris_resource_check_level_layer(const struct iris_resource
*res
,
488 uint32_t level
, uint32_t layer
);
490 bool iris_resource_level_has_hiz(const struct iris_resource
*res
,
493 bool iris_sample_with_depth_aux(const struct gen_device_info
*devinfo
,
494 const struct iris_resource
*res
);
496 bool iris_has_color_unresolved(const struct iris_resource
*res
,
497 unsigned start_level
, unsigned num_levels
,
498 unsigned start_layer
, unsigned num_layers
);
500 enum isl_aux_usage
iris_resource_render_aux_usage(struct iris_context
*ice
,
501 struct iris_resource
*res
,
502 enum isl_format render_fmt
,
504 bool draw_aux_disabled
);
505 void iris_resource_prepare_render(struct iris_context
*ice
,
506 struct iris_batch
*batch
,
507 struct iris_resource
*res
, uint32_t level
,
508 uint32_t start_layer
, uint32_t layer_count
,
509 enum isl_aux_usage aux_usage
);
510 void iris_resource_finish_render(struct iris_context
*ice
,
511 struct iris_resource
*res
, uint32_t level
,
512 uint32_t start_layer
, uint32_t layer_count
,
513 enum isl_aux_usage aux_usage
);
514 void iris_resource_prepare_depth(struct iris_context
*ice
,
515 struct iris_batch
*batch
,
516 struct iris_resource
*res
, uint32_t level
,
517 uint32_t start_layer
, uint32_t layer_count
);
518 void iris_resource_finish_depth(struct iris_context
*ice
,
519 struct iris_resource
*res
, uint32_t level
,
520 uint32_t start_layer
, uint32_t layer_count
,