src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/debug.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_format.h"
  43 #include "util/u_transfer_helper.h"
  44 #include "util/u_upload_mgr.h"
  45 #include "util/ralloc.h"
  46 #include "util/xmlconfig.h"
  47 #include "drm-uapi/i915_drm.h"
  48 #include "iris_context.h"
  49 #include "iris_defines.h"
  50 #include "iris_fence.h"
  51 #include "iris_pipe.h"
  52 #include "iris_resource.h"
  53 #include "iris_screen.h"
  54 #include "intel/compiler/brw_compiler.h"
  55 #include "intel/common/gen_gem.h"
  56 #include "iris_monitor.h"
  57
  58 static void
  59 iris_flush_frontbuffer(struct pipe_screen *_screen,
  60                        struct pipe_resource *resource,
  61                        unsigned level, unsigned layer,
  62                        void *context_private, struct pipe_box *box)
  63 {
  64 }
  65
  66 static const char *
  67 iris_get_vendor(struct pipe_screen *pscreen)
  68 {
  69    return "Intel";
  70 }
  71
  72 static const char *
  73 iris_get_device_vendor(struct pipe_screen *pscreen)
  74 {
  75    return "Intel";
  76 }
  77
  78 static const char *
  79 iris_get_name(struct pipe_screen *pscreen)
  80 {
  81    struct iris_screen *screen = (struct iris_screen *)pscreen;
  82    static char buf[128];
  83    const char *chipset;
  84
  85    switch (screen->pci_id) {
  86 #undef CHIPSET
  87 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  88 #include "pci_ids/i965_pci_ids.h"
  89    default:
  90       chipset = "Unknown Intel Chipset";
  91       break;
  92    }
  93
  94    snprintf(buf, sizeof(buf), "Mesa %s", chipset);
  95    return buf;
  96 }
  97
  98 static uint64_t
  99 get_aperture_size(int fd)
 100 {
 101    struct drm_i915_gem_get_aperture aperture = {};
 102    gen_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
 103    return aperture.aper_size;
 104 }
 105
 106 static int
 107 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 108 {
 109    struct iris_screen *screen = (struct iris_screen *)pscreen;
 110    const struct gen_device_info *devinfo = &screen->devinfo;
 111
 112    switch (param) {
 113    case PIPE_CAP_NPOT_TEXTURES:
 114    case PIPE_CAP_ANISOTROPIC_FILTER:
 115    case PIPE_CAP_POINT_SPRITE:
 116    case PIPE_CAP_OCCLUSION_QUERY:
 117    case PIPE_CAP_QUERY_TIME_ELAPSED:
 118    case PIPE_CAP_TEXTURE_SWIZZLE:
 119    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 120    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 121    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 122    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 123    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 124    case PIPE_CAP_PRIMITIVE_RESTART:
 125    case PIPE_CAP_INDEP_BLEND_ENABLE:
 126    case PIPE_CAP_INDEP_BLEND_FUNC:
 127    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 128    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 129    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 130    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 131    case PIPE_CAP_TGSI_INSTANCEID:
 132    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 133    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 134    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 135    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 136    case PIPE_CAP_CONDITIONAL_RENDER:
 137    case PIPE_CAP_TEXTURE_BARRIER:
 138    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 139    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 140    case PIPE_CAP_COMPUTE:
 141    case PIPE_CAP_START_INSTANCE:
 142    case PIPE_CAP_QUERY_TIMESTAMP:
 143    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 144    case PIPE_CAP_CUBE_MAP_ARRAY:
 145    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 146    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 147    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 148    case PIPE_CAP_TEXTURE_QUERY_LOD:
 149    case PIPE_CAP_SAMPLE_SHADING:
 150    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 151    case PIPE_CAP_DRAW_INDIRECT:
 152    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 153    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 154    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 155    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 156    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 157    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 158    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 159    case PIPE_CAP_ACCELERATED:
 160    case PIPE_CAP_UMA:
 161    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 162    case PIPE_CAP_CLIP_HALFZ:
 163    case PIPE_CAP_TGSI_TEXCOORD:
 164    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 165    case PIPE_CAP_DOUBLES:
 166    case PIPE_CAP_INT64:
 167    case PIPE_CAP_INT64_DIVMOD:
 168    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 169    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 170    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 171    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 172    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 173    case PIPE_CAP_CULL_DISTANCE:
 174    case PIPE_CAP_PACKED_UNIFORMS:
 175    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 176    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 177    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 178    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 179    case PIPE_CAP_QUERY_SO_OVERFLOW:
 180    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 181    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 182    case PIPE_CAP_TGSI_TXQS:
 183    case PIPE_CAP_TGSI_CLOCK:
 184    case PIPE_CAP_TGSI_BALLOT:
 185    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 186    case PIPE_CAP_CLEAR_TEXTURE:
 187    case PIPE_CAP_TGSI_VOTE:
 188    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 189    case PIPE_CAP_TEXTURE_GATHER_SM5:
 190    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 191    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 192    case PIPE_CAP_LOAD_CONSTBUF:
 193    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 194    case PIPE_CAP_DRAW_PARAMETERS:
 195    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 196    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 197    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 198    case PIPE_CAP_INVALIDATE_BUFFER:
 199    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 200    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
 201    case PIPE_CAP_TEXTURE_SHADOW_LOD:
 202    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 203       return true;
 204    case PIPE_CAP_FBFETCH:
 205       return BRW_MAX_DRAW_BUFFERS;
 206    case PIPE_CAP_FBFETCH_COHERENT:
 207    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 208    case PIPE_CAP_POST_DEPTH_COVERAGE:
 209    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 210    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 211    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 212    case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
 213       return devinfo->gen >= 9;
 214    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 215       return 1;
 216    case PIPE_CAP_MAX_RENDER_TARGETS:
 217       return BRW_MAX_DRAW_BUFFERS;
 218    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 219       return 16384;
 220    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 221       return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
 222    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 223       return 12; /* 2048x2048 */
 224    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 225       return 4;
 226    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 227       return 2048;
 228    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 229       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 230    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 231       return BRW_MAX_SOL_BINDINGS;
 232    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 233    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 234       return 460;
 235    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 236       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 237       return 32;
 238    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 239       return IRIS_MAP_BUFFER_ALIGNMENT;
 240    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 241       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 242        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 243        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 244        * GPU and the CPU can be updating disjoint regions of the buffer
 245        * simultaneously and that will break if the regions overlap the same
 246        * cacheline.
 247        */
 248       return 64;
 249    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 250       return 1 << 27;
 251    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 252       return 16; // XXX: u_screen says 256 is the minimum value...
 253    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 254       return true;
 255    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 256       return IRIS_MAX_TEXTURE_BUFFER_SIZE;
 257    case PIPE_CAP_MAX_VIEWPORTS:
 258       return 16;
 259    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 260       return 256;
 261    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 262       return 1024;
 263    case PIPE_CAP_MAX_GS_INVOCATIONS:
 264       return 32;
 265    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 266       return 4;
 267    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 268       return -32;
 269    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 270       return 31;
 271    case PIPE_CAP_MAX_VERTEX_STREAMS:
 272       return 4;
 273    case PIPE_CAP_VENDOR_ID:
 274       return 0x8086;
 275    case PIPE_CAP_DEVICE_ID:
 276       return screen->pci_id;
 277    case PIPE_CAP_VIDEO_MEMORY: {
 278       /* Once a batch uses more than 75% of the maximum mappable size, we
 279        * assume that there's some fragmentation, and we start doing extra
 280        * flushing, etc.  That's the big cliff apps will care about.
 281        */
 282       const unsigned gpu_mappable_megabytes =
 283          (screen->aperture_bytes * 3 / 4) / (1024 * 1024);
 284
 285       const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
 286       const long system_page_size = sysconf(_SC_PAGE_SIZE);
 287
 288       if (system_memory_pages <= 0 || system_page_size <= 0)
 289          return -1;
 290
 291       const uint64_t system_memory_bytes =
 292          (uint64_t) system_memory_pages * (uint64_t) system_page_size;
 293
 294       const unsigned system_memory_megabytes =
 295          (unsigned) (system_memory_bytes / (1024 * 1024));
 296
 297       return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
 298    }
 299    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 300    case PIPE_CAP_MAX_VARYINGS:
 301       return 32;
 302    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 303       /* AMD_pinned_memory assumes the flexibility of using client memory
 304        * for any buffer (incl. vertex buffers) which rules out the prospect
 305        * of using snooped buffers, as using snooped buffers without
 306        * cogniscience is likely to be detrimental to performance and require
 307        * extensive checking in the driver for correctness, e.g. to prevent
 308        * illegal snoop <-> snoop transfers.
 309        */
 310       return devinfo->has_llc;
 311    case PIPE_CAP_MAX_FRAMES_IN_FLIGHT:
 312       return screen->driconf.disable_throttling ? 0 : 1;
 313
 314    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 315       return PIPE_CONTEXT_PRIORITY_LOW |
 316              PIPE_CONTEXT_PRIORITY_MEDIUM |
 317              PIPE_CONTEXT_PRIORITY_HIGH;
 318
 319    // XXX: don't hardcode 00:00:02.0 PCI here
 320    case PIPE_CAP_PCI_GROUP:
 321       return 0;
 322    case PIPE_CAP_PCI_BUS:
 323       return 0;
 324    case PIPE_CAP_PCI_DEVICE:
 325       return 2;
 326    case PIPE_CAP_PCI_FUNCTION:
 327       return 0;
 328
 329    default:
 330       return u_pipe_screen_get_param_defaults(pscreen, param);
 331    }
 332    return 0;
 333 }
 334
 335 static float
 336 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 337 {
 338    switch (param) {
 339    case PIPE_CAPF_MAX_LINE_WIDTH:
 340    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 341       return 7.375f;
 342
 343    case PIPE_CAPF_MAX_POINT_WIDTH:
 344    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 345       return 255.0f;
 346
 347    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 348       return 16.0f;
 349    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 350       return 15.0f;
 351    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 352    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 353    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 354       return 0.0f;
 355    default:
 356       unreachable("unknown param");
 357    }
 358 }
 359
 360 static int
 361 iris_get_shader_param(struct pipe_screen *pscreen,
 362                       enum pipe_shader_type p_stage,
 363                       enum pipe_shader_cap param)
 364 {
 365    gl_shader_stage stage = stage_from_pipe(p_stage);
 366
 367    /* this is probably not totally correct.. but it's a start: */
 368    switch (param) {
 369    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 370       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 371    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 372    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 373    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 374       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 375
 376    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 377       return UINT_MAX;
 378
 379    case PIPE_SHADER_CAP_MAX_INPUTS:
 380       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 381    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 382       return 32;
 383    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 384       return 16 * 1024 * sizeof(float);
 385    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 386       return 16;
 387    case PIPE_SHADER_CAP_MAX_TEMPS:
 388       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 389    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 390       return 0;
 391    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 392    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 393    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 394    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 395       /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
 396        * which we don't want.  Our compiler backend will check brw_compiler's
 397        * options and call nir_lower_indirect_derefs appropriately anyway.
 398        */
 399       return true;
 400    case PIPE_SHADER_CAP_SUBROUTINES:
 401       return 0;
 402    case PIPE_SHADER_CAP_INTEGERS:
 403    case PIPE_SHADER_CAP_SCALAR_ISA:
 404       return 1;
 405    case PIPE_SHADER_CAP_INT64_ATOMICS:
 406    case PIPE_SHADER_CAP_FP16:
 407       return 0;
 408    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 409    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 410    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 411       return IRIS_MAX_TEXTURE_SAMPLERS;
 412    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 413       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 414    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 415    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 416       return 0;
 417    case PIPE_SHADER_CAP_PREFERRED_IR:
 418       return PIPE_SHADER_IR_NIR;
 419    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 420       return 1 << PIPE_SHADER_IR_NIR;
 421    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 422    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 423       return 1;
 424    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 425    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 426    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 427    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 428    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 429    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 430    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 431       return 0;
 432    default:
 433       unreachable("unknown shader param");
 434    }
 435 }
 436
 437 static int
 438 iris_get_compute_param(struct pipe_screen *pscreen,
 439                        enum pipe_shader_ir ir_type,
 440                        enum pipe_compute_cap param,
 441                        void *ret)
 442 {
 443    struct iris_screen *screen = (struct iris_screen *)pscreen;
 444    const struct gen_device_info *devinfo = &screen->devinfo;
 445
 446    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 447    const uint32_t max_invocations = 32 * max_threads;
 448
 449 #define RET(x) do {                  \
 450    if (ret)                          \
 451       memcpy(ret, x, sizeof(x));     \
 452    return sizeof(x);                 \
 453 } while (0)
 454
 455    switch (param) {
 456    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 457       RET((uint32_t []){ 32 });
 458
 459    case PIPE_COMPUTE_CAP_IR_TARGET:
 460       if (ret)
 461          strcpy(ret, "gen");
 462       return 4;
 463
 464    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 465       RET((uint64_t []) { 3 });
 466
 467    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 468       RET(((uint64_t []) { 65535, 65535, 65535 }));
 469
 470    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 471       /* MaxComputeWorkGroupSize[0..2] */
 472       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 473
 474    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 475       /* MaxComputeWorkGroupInvocations */
 476       RET((uint64_t []) { max_invocations });
 477
 478    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 479       /* MaxComputeSharedMemorySize */
 480       RET((uint64_t []) { 64 * 1024 });
 481
 482    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 483       RET((uint32_t []) { 1 });
 484
 485    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 486       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 487
 488    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 489    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 490    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 491    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 492    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 493    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 494    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 495       // XXX: I think these are for Clover...
 496       return 0;
 497
 498    default:
 499       unreachable("unknown compute param");
 500    }
 501 }
 502
 503 static uint64_t
 504 iris_get_timestamp(struct pipe_screen *pscreen)
 505 {
 506    struct iris_screen *screen = (struct iris_screen *) pscreen;
 507    const unsigned TIMESTAMP = 0x2358;
 508    uint64_t result;
 509
 510    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 511
 512    result = gen_device_info_timebase_scale(&screen->devinfo, result);
 513    result &= (1ull << TIMESTAMP_BITS) - 1;
 514
 515    return result;
 516 }
 517
 518 static void
 519 iris_destroy_screen(struct pipe_screen *pscreen)
 520 {
 521    struct iris_screen *screen = (struct iris_screen *) pscreen;
 522    iris_bo_unreference(screen->workaround_bo);
 523    u_transfer_helper_destroy(pscreen->transfer_helper);
 524    iris_bufmgr_destroy(screen->bufmgr);
 525    disk_cache_destroy(screen->disk_cache);
 526    ralloc_free(screen);
 527 }
 528
 529 static void
 530 iris_query_memory_info(struct pipe_screen *pscreen,
 531                        struct pipe_memory_info *info)
 532 {
 533 }
 534
 535 static const void *
 536 iris_get_compiler_options(struct pipe_screen *pscreen,
 537                           enum pipe_shader_ir ir,
 538                           enum pipe_shader_type pstage)
 539 {
 540    struct iris_screen *screen = (struct iris_screen *) pscreen;
 541    gl_shader_stage stage = stage_from_pipe(pstage);
 542    assert(ir == PIPE_SHADER_IR_NIR);
 543
 544    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 545 }
 546
 547 static struct disk_cache *
 548 iris_get_disk_shader_cache(struct pipe_screen *pscreen)
 549 {
 550    struct iris_screen *screen = (struct iris_screen *) pscreen;
 551    return screen->disk_cache;
 552 }
 553
 554 static int
 555 iris_getparam(struct iris_screen *screen, int param, int *value)
 556 {
 557    struct drm_i915_getparam gp = { .param = param, .value = value };
 558
 559    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 560       return -errno;
 561
 562    return 0;
 563 }
 564
 565 static int
 566 iris_getparam_integer(struct iris_screen *screen, int param)
 567 {
 568    int value = -1;
 569
 570    if (iris_getparam(screen, param, &value) == 0)
 571       return value;
 572
 573    return -1;
 574 }
 575
 576 static void
 577 iris_shader_debug_log(void *data, const char *fmt, ...)
 578 {
 579    struct pipe_debug_callback *dbg = data;
 580    unsigned id = 0;
 581    va_list args;
 582
 583    if (!dbg->debug_message)
 584       return;
 585
 586    va_start(args, fmt);
 587    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 588    va_end(args);
 589 }
 590
 591 static void
 592 iris_shader_perf_log(void *data, const char *fmt, ...)
 593 {
 594    struct pipe_debug_callback *dbg = data;
 595    unsigned id = 0;
 596    va_list args;
 597    va_start(args, fmt);
 598
 599    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
 600       va_list args_copy;
 601       va_copy(args_copy, args);
 602       vfprintf(stderr, fmt, args_copy);
 603       va_end(args_copy);
 604    }
 605
 606    if (dbg->debug_message) {
 607       dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 608    }
 609
 610    va_end(args);
 611 }
 612
 613 struct pipe_screen *
 614 iris_screen_create(int fd, const struct pipe_screen_config *config)
 615 {
 616    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 617    if (!screen)
 618       return NULL;
 619
 620    screen->fd = fd;
 621
 622    if (!gen_get_device_info_from_fd(fd, &screen->devinfo))
 623       return NULL;
 624    screen->pci_id = screen->devinfo.chipset_id;
 625    screen->no_hw = screen->devinfo.no_hw;
 626
 627    if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
 628       return NULL;
 629
 630    screen->aperture_bytes = get_aperture_size(fd);
 631
 632    if (getenv("INTEL_NO_HW") != NULL)
 633       screen->no_hw = true;
 634
 635    bool bo_reuse = false;
 636    int bo_reuse_mode = driQueryOptioni(config->options, "bo_reuse");
 637    switch (bo_reuse_mode) {
 638    case DRI_CONF_BO_REUSE_DISABLED:
 639       break;
 640    case DRI_CONF_BO_REUSE_ALL:
 641       bo_reuse = true;
 642       break;
 643    }
 644
 645    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd, bo_reuse);
 646    if (!screen->bufmgr)
 647       return NULL;
 648
 649    screen->workaround_bo =
 650       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 651    if (!screen->workaround_bo)
 652       return NULL;
 653
 654    brw_process_intel_debug_variable();
 655
 656    screen->driconf.dual_color_blend_by_location =
 657       driQueryOptionb(config->options, "dual_color_blend_by_location");
 658    screen->driconf.disable_throttling =
 659       driQueryOptionb(config->options, "disable_throttling");
 660
 661    screen->precompile = env_var_as_boolean("shader_precompile", true);
 662
 663    isl_device_init(&screen->isl_dev, &screen->devinfo, false);
 664
 665    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 666    screen->compiler->shader_debug_log = iris_shader_debug_log;
 667    screen->compiler->shader_perf_log = iris_shader_perf_log;
 668    screen->compiler->supports_pull_constants = false;
 669    screen->compiler->supports_shader_constants = true;
 670
 671    iris_disk_cache_init(screen);
 672
 673    slab_create_parent(&screen->transfer_pool,
 674                       sizeof(struct iris_transfer), 64);
 675
 676    screen->subslice_total =
 677       iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
 678    assert(screen->subslice_total >= 1);
 679
 680    struct pipe_screen *pscreen = &screen->base;
 681
 682    iris_init_screen_fence_functions(pscreen);
 683    iris_init_screen_resource_functions(pscreen);
 684
 685    pscreen->destroy = iris_destroy_screen;
 686    pscreen->get_name = iris_get_name;
 687    pscreen->get_vendor = iris_get_vendor;
 688    pscreen->get_device_vendor = iris_get_device_vendor;
 689    pscreen->get_param = iris_get_param;
 690    pscreen->get_shader_param = iris_get_shader_param;
 691    pscreen->get_compute_param = iris_get_compute_param;
 692    pscreen->get_paramf = iris_get_paramf;
 693    pscreen->get_compiler_options = iris_get_compiler_options;
 694    pscreen->get_disk_shader_cache = iris_get_disk_shader_cache;
 695    pscreen->is_format_supported = iris_is_format_supported;
 696    pscreen->context_create = iris_create_context;
 697    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 698    pscreen->get_timestamp = iris_get_timestamp;
 699    pscreen->query_memory_info = iris_query_memory_info;
 700    pscreen->get_driver_query_group_info = iris_get_monitor_group_info;
 701    pscreen->get_driver_query_info = iris_get_monitor_info;
 702
 703    return pscreen;
 704 }