src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/debug.h"
  41 #include "util/u_inlines.h"
  42 #include "util/format/u_format.h"
  43 #include "util/u_transfer_helper.h"
  44 #include "util/u_upload_mgr.h"
  45 #include "util/ralloc.h"
  46 #include "util/xmlconfig.h"
  47 #include "drm-uapi/i915_drm.h"
  48 #include "iris_context.h"
  49 #include "iris_defines.h"
  50 #include "iris_fence.h"
  51 #include "iris_pipe.h"
  52 #include "iris_resource.h"
  53 #include "iris_screen.h"
  54 #include "intel/compiler/brw_compiler.h"
  55 #include "intel/common/gen_gem.h"
  56 #include "iris_monitor.h"
  57
  58 static void
  59 iris_flush_frontbuffer(struct pipe_screen *_screen,
  60                        struct pipe_resource *resource,
  61                        unsigned level, unsigned layer,
  62                        void *context_private, struct pipe_box *box)
  63 {
  64 }
  65
  66 static const char *
  67 iris_get_vendor(struct pipe_screen *pscreen)
  68 {
  69    return "Intel";
  70 }
  71
  72 static const char *
  73 iris_get_device_vendor(struct pipe_screen *pscreen)
  74 {
  75    return "Intel";
  76 }
  77
  78 static const char *
  79 iris_get_name(struct pipe_screen *pscreen)
  80 {
  81    struct iris_screen *screen = (struct iris_screen *)pscreen;
  82    static char buf[128];
  83    const char *name = gen_get_device_name(screen->pci_id);
  84
  85    if (!name)
  86       name = "Intel Unknown";
  87
  88    snprintf(buf, sizeof(buf), "Mesa %s", name);
  89    return buf;
  90 }
  91
  92 static uint64_t
  93 get_aperture_size(int fd)
  94 {
  95    struct drm_i915_gem_get_aperture aperture = {};
  96    gen_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
  97    return aperture.aper_size;
  98 }
  99
 100 static int
 101 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 102 {
 103    struct iris_screen *screen = (struct iris_screen *)pscreen;
 104    const struct gen_device_info *devinfo = &screen->devinfo;
 105
 106    switch (param) {
 107    case PIPE_CAP_NPOT_TEXTURES:
 108    case PIPE_CAP_ANISOTROPIC_FILTER:
 109    case PIPE_CAP_POINT_SPRITE:
 110    case PIPE_CAP_OCCLUSION_QUERY:
 111    case PIPE_CAP_QUERY_TIME_ELAPSED:
 112    case PIPE_CAP_TEXTURE_SWIZZLE:
 113    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 114    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 115    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 116    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 117    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 118    case PIPE_CAP_PRIMITIVE_RESTART:
 119    case PIPE_CAP_INDEP_BLEND_ENABLE:
 120    case PIPE_CAP_INDEP_BLEND_FUNC:
 121    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 122    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 123    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 124    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 125    case PIPE_CAP_TGSI_INSTANCEID:
 126    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 127    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 128    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 129    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 130    case PIPE_CAP_CONDITIONAL_RENDER:
 131    case PIPE_CAP_TEXTURE_BARRIER:
 132    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 133    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 134    case PIPE_CAP_COMPUTE:
 135    case PIPE_CAP_START_INSTANCE:
 136    case PIPE_CAP_QUERY_TIMESTAMP:
 137    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 138    case PIPE_CAP_CUBE_MAP_ARRAY:
 139    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 140    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 141    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 142    case PIPE_CAP_TEXTURE_QUERY_LOD:
 143    case PIPE_CAP_SAMPLE_SHADING:
 144    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 145    case PIPE_CAP_DRAW_INDIRECT:
 146    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 147    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 148    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 149    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 150    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 151    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 152    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 153    case PIPE_CAP_ACCELERATED:
 154    case PIPE_CAP_UMA:
 155    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 156    case PIPE_CAP_CLIP_HALFZ:
 157    case PIPE_CAP_TGSI_TEXCOORD:
 158    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 159    case PIPE_CAP_DOUBLES:
 160    case PIPE_CAP_INT64:
 161    case PIPE_CAP_INT64_DIVMOD:
 162    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 163    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 164    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 165    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 166    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 167    case PIPE_CAP_CULL_DISTANCE:
 168    case PIPE_CAP_PACKED_UNIFORMS:
 169    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 170    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 171    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 172    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 173    case PIPE_CAP_QUERY_SO_OVERFLOW:
 174    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 175    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 176    case PIPE_CAP_TGSI_TXQS:
 177    case PIPE_CAP_TGSI_CLOCK:
 178    case PIPE_CAP_TGSI_BALLOT:
 179    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 180    case PIPE_CAP_CLEAR_TEXTURE:
 181    case PIPE_CAP_TGSI_VOTE:
 182    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 183    case PIPE_CAP_TEXTURE_GATHER_SM5:
 184    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 185    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 186    case PIPE_CAP_LOAD_CONSTBUF:
 187    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 188    case PIPE_CAP_DRAW_PARAMETERS:
 189    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 190    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 191    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 192    case PIPE_CAP_INVALIDATE_BUFFER:
 193    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 194    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
 195    case PIPE_CAP_TEXTURE_SHADOW_LOD:
 196    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 197    case PIPE_CAP_GL_SPIRV:
 198    case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS:
 199    case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
 200       return true;
 201    case PIPE_CAP_FBFETCH:
 202       return BRW_MAX_DRAW_BUFFERS;
 203    case PIPE_CAP_FBFETCH_COHERENT:
 204    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 205    case PIPE_CAP_POST_DEPTH_COVERAGE:
 206    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 207    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 208    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 209    case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
 210       return devinfo->gen >= 9;
 211    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 212       return 1;
 213    case PIPE_CAP_MAX_RENDER_TARGETS:
 214       return BRW_MAX_DRAW_BUFFERS;
 215    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 216       return 16384;
 217    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 218       return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
 219    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 220       return 12; /* 2048x2048 */
 221    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 222       return 4;
 223    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 224       return 2048;
 225    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 226       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 227    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 228       return BRW_MAX_SOL_BINDINGS;
 229    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 230    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 231       return 460;
 232    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 233       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 234       return 32;
 235    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 236       return IRIS_MAP_BUFFER_ALIGNMENT;
 237    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 238       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 239        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 240        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 241        * GPU and the CPU can be updating disjoint regions of the buffer
 242        * simultaneously and that will break if the regions overlap the same
 243        * cacheline.
 244        */
 245       return 64;
 246    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 247       return 1 << 27;
 248    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 249       return 16; // XXX: u_screen says 256 is the minimum value...
 250    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 251       return true;
 252    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 253       return IRIS_MAX_TEXTURE_BUFFER_SIZE;
 254    case PIPE_CAP_MAX_VIEWPORTS:
 255       return 16;
 256    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 257       return 256;
 258    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 259       return 1024;
 260    case PIPE_CAP_MAX_GS_INVOCATIONS:
 261       return 32;
 262    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 263       return 4;
 264    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 265       return -32;
 266    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 267       return 31;
 268    case PIPE_CAP_MAX_VERTEX_STREAMS:
 269       return 4;
 270    case PIPE_CAP_VENDOR_ID:
 271       return 0x8086;
 272    case PIPE_CAP_DEVICE_ID:
 273       return screen->pci_id;
 274    case PIPE_CAP_VIDEO_MEMORY: {
 275       /* Once a batch uses more than 75% of the maximum mappable size, we
 276        * assume that there's some fragmentation, and we start doing extra
 277        * flushing, etc.  That's the big cliff apps will care about.
 278        */
 279       const unsigned gpu_mappable_megabytes =
 280          (screen->aperture_bytes * 3 / 4) / (1024 * 1024);
 281
 282       const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
 283       const long system_page_size = sysconf(_SC_PAGE_SIZE);
 284
 285       if (system_memory_pages <= 0 || system_page_size <= 0)
 286          return -1;
 287
 288       const uint64_t system_memory_bytes =
 289          (uint64_t) system_memory_pages * (uint64_t) system_page_size;
 290
 291       const unsigned system_memory_megabytes =
 292          (unsigned) (system_memory_bytes / (1024 * 1024));
 293
 294       return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
 295    }
 296    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 297    case PIPE_CAP_MAX_VARYINGS:
 298       return 32;
 299    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 300       /* AMD_pinned_memory assumes the flexibility of using client memory
 301        * for any buffer (incl. vertex buffers) which rules out the prospect
 302        * of using snooped buffers, as using snooped buffers without
 303        * cogniscience is likely to be detrimental to performance and require
 304        * extensive checking in the driver for correctness, e.g. to prevent
 305        * illegal snoop <-> snoop transfers.
 306        */
 307       return devinfo->has_llc;
 308    case PIPE_CAP_THROTTLE:
 309       return screen->driconf.disable_throttling ? 0 : 1;
 310
 311    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 312       return PIPE_CONTEXT_PRIORITY_LOW |
 313              PIPE_CONTEXT_PRIORITY_MEDIUM |
 314              PIPE_CONTEXT_PRIORITY_HIGH;
 315
 316    // XXX: don't hardcode 00:00:02.0 PCI here
 317    case PIPE_CAP_PCI_GROUP:
 318       return 0;
 319    case PIPE_CAP_PCI_BUS:
 320       return 0;
 321    case PIPE_CAP_PCI_DEVICE:
 322       return 2;
 323    case PIPE_CAP_PCI_FUNCTION:
 324       return 0;
 325
 326    default:
 327       return u_pipe_screen_get_param_defaults(pscreen, param);
 328    }
 329    return 0;
 330 }
 331
 332 static float
 333 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 334 {
 335    switch (param) {
 336    case PIPE_CAPF_MAX_LINE_WIDTH:
 337    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 338       return 7.375f;
 339
 340    case PIPE_CAPF_MAX_POINT_WIDTH:
 341    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 342       return 255.0f;
 343
 344    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 345       return 16.0f;
 346    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 347       return 15.0f;
 348    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 349    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 350    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 351       return 0.0f;
 352    default:
 353       unreachable("unknown param");
 354    }
 355 }
 356
 357 static int
 358 iris_get_shader_param(struct pipe_screen *pscreen,
 359                       enum pipe_shader_type p_stage,
 360                       enum pipe_shader_cap param)
 361 {
 362    gl_shader_stage stage = stage_from_pipe(p_stage);
 363
 364    /* this is probably not totally correct.. but it's a start: */
 365    switch (param) {
 366    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 367       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 368    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 369    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 370    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 371       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 372
 373    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 374       return UINT_MAX;
 375
 376    case PIPE_SHADER_CAP_MAX_INPUTS:
 377       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 378    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 379       return 32;
 380    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 381       return 16 * 1024 * sizeof(float);
 382    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 383       return 16;
 384    case PIPE_SHADER_CAP_MAX_TEMPS:
 385       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 386    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 387       return 0;
 388    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 389    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 390    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 391    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 392       /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
 393        * which we don't want.  Our compiler backend will check brw_compiler's
 394        * options and call nir_lower_indirect_derefs appropriately anyway.
 395        */
 396       return true;
 397    case PIPE_SHADER_CAP_SUBROUTINES:
 398       return 0;
 399    case PIPE_SHADER_CAP_INTEGERS:
 400       return 1;
 401    case PIPE_SHADER_CAP_INT64_ATOMICS:
 402    case PIPE_SHADER_CAP_FP16:
 403       return 0;
 404    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 405    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 406    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 407       return IRIS_MAX_TEXTURE_SAMPLERS;
 408    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 409       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 410    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 411    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 412       return 0;
 413    case PIPE_SHADER_CAP_PREFERRED_IR:
 414       return PIPE_SHADER_IR_NIR;
 415    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 416       return 1 << PIPE_SHADER_IR_NIR;
 417    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 418    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 419       return 1;
 420    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 421    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 422    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 423    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 424    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 425    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 426    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 427       return 0;
 428    default:
 429       unreachable("unknown shader param");
 430    }
 431 }
 432
 433 static int
 434 iris_get_compute_param(struct pipe_screen *pscreen,
 435                        enum pipe_shader_ir ir_type,
 436                        enum pipe_compute_cap param,
 437                        void *ret)
 438 {
 439    struct iris_screen *screen = (struct iris_screen *)pscreen;
 440    const struct gen_device_info *devinfo = &screen->devinfo;
 441
 442    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 443    const uint32_t max_invocations = 32 * max_threads;
 444
 445 #define RET(x) do {                  \
 446    if (ret)                          \
 447       memcpy(ret, x, sizeof(x));     \
 448    return sizeof(x);                 \
 449 } while (0)
 450
 451    switch (param) {
 452    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 453       RET((uint32_t []){ 32 });
 454
 455    case PIPE_COMPUTE_CAP_IR_TARGET:
 456       if (ret)
 457          strcpy(ret, "gen");
 458       return 4;
 459
 460    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 461       RET((uint64_t []) { 3 });
 462
 463    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 464       RET(((uint64_t []) { 65535, 65535, 65535 }));
 465
 466    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 467       /* MaxComputeWorkGroupSize[0..2] */
 468       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 469
 470    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 471       /* MaxComputeWorkGroupInvocations */
 472       RET((uint64_t []) { max_invocations });
 473
 474    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 475       /* MaxComputeSharedMemorySize */
 476       RET((uint64_t []) { 64 * 1024 });
 477
 478    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 479       RET((uint32_t []) { 1 });
 480
 481    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 482       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 483
 484    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 485    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 486    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 487    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 488    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 489    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 490    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 491       // XXX: I think these are for Clover...
 492       return 0;
 493
 494    default:
 495       unreachable("unknown compute param");
 496    }
 497 }
 498
 499 static uint64_t
 500 iris_get_timestamp(struct pipe_screen *pscreen)
 501 {
 502    struct iris_screen *screen = (struct iris_screen *) pscreen;
 503    const unsigned TIMESTAMP = 0x2358;
 504    uint64_t result;
 505
 506    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 507
 508    result = gen_device_info_timebase_scale(&screen->devinfo, result);
 509    result &= (1ull << TIMESTAMP_BITS) - 1;
 510
 511    return result;
 512 }
 513
 514 static void
 515 iris_destroy_screen(struct pipe_screen *pscreen)
 516 {
 517    struct iris_screen *screen = (struct iris_screen *) pscreen;
 518    iris_bo_unreference(screen->workaround_bo);
 519    u_transfer_helper_destroy(pscreen->transfer_helper);
 520    iris_bufmgr_destroy(screen->bufmgr);
 521    disk_cache_destroy(screen->disk_cache);
 522    close(screen->fd);
 523    ralloc_free(screen);
 524 }
 525
 526 static void
 527 iris_query_memory_info(struct pipe_screen *pscreen,
 528                        struct pipe_memory_info *info)
 529 {
 530 }
 531
 532 static const void *
 533 iris_get_compiler_options(struct pipe_screen *pscreen,
 534                           enum pipe_shader_ir ir,
 535                           enum pipe_shader_type pstage)
 536 {
 537    struct iris_screen *screen = (struct iris_screen *) pscreen;
 538    gl_shader_stage stage = stage_from_pipe(pstage);
 539    assert(ir == PIPE_SHADER_IR_NIR);
 540
 541    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 542 }
 543
 544 static struct disk_cache *
 545 iris_get_disk_shader_cache(struct pipe_screen *pscreen)
 546 {
 547    struct iris_screen *screen = (struct iris_screen *) pscreen;
 548    return screen->disk_cache;
 549 }
 550
 551 static int
 552 iris_getparam(struct iris_screen *screen, int param, int *value)
 553 {
 554    struct drm_i915_getparam gp = { .param = param, .value = value };
 555
 556    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 557       return -errno;
 558
 559    return 0;
 560 }
 561
 562 static int
 563 iris_getparam_integer(struct iris_screen *screen, int param)
 564 {
 565    int value = -1;
 566
 567    if (iris_getparam(screen, param, &value) == 0)
 568       return value;
 569
 570    return -1;
 571 }
 572
 573 static void
 574 iris_shader_debug_log(void *data, const char *fmt, ...)
 575 {
 576    struct pipe_debug_callback *dbg = data;
 577    unsigned id = 0;
 578    va_list args;
 579
 580    if (!dbg->debug_message)
 581       return;
 582
 583    va_start(args, fmt);
 584    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 585    va_end(args);
 586 }
 587
 588 static void
 589 iris_shader_perf_log(void *data, const char *fmt, ...)
 590 {
 591    struct pipe_debug_callback *dbg = data;
 592    unsigned id = 0;
 593    va_list args;
 594    va_start(args, fmt);
 595
 596    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
 597       va_list args_copy;
 598       va_copy(args_copy, args);
 599       vfprintf(stderr, fmt, args_copy);
 600       va_end(args_copy);
 601    }
 602
 603    if (dbg->debug_message) {
 604       dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 605    }
 606
 607    va_end(args);
 608 }
 609
 610 struct pipe_screen *
 611 iris_screen_create(int fd, const struct pipe_screen_config *config)
 612 {
 613    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 614    if (!screen)
 615       return NULL;
 616
 617    screen->fd = fd;
 618
 619    if (!gen_get_device_info_from_fd(fd, &screen->devinfo))
 620       return NULL;
 621    screen->pci_id = screen->devinfo.chipset_id;
 622    screen->no_hw = screen->devinfo.no_hw;
 623
 624    if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
 625       return NULL;
 626
 627    screen->aperture_bytes = get_aperture_size(fd);
 628
 629    if (getenv("INTEL_NO_HW") != NULL)
 630       screen->no_hw = true;
 631
 632    bool bo_reuse = false;
 633    int bo_reuse_mode = driQueryOptioni(config->options, "bo_reuse");
 634    switch (bo_reuse_mode) {
 635    case DRI_CONF_BO_REUSE_DISABLED:
 636       break;
 637    case DRI_CONF_BO_REUSE_ALL:
 638       bo_reuse = true;
 639       break;
 640    }
 641
 642    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd, bo_reuse);
 643    if (!screen->bufmgr)
 644       return NULL;
 645
 646    screen->workaround_bo =
 647       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 648    if (!screen->workaround_bo)
 649       return NULL;
 650
 651    brw_process_intel_debug_variable();
 652
 653    screen->driconf.dual_color_blend_by_location =
 654       driQueryOptionb(config->options, "dual_color_blend_by_location");
 655    screen->driconf.disable_throttling =
 656       driQueryOptionb(config->options, "disable_throttling");
 657    screen->driconf.always_flush_cache =
 658       driQueryOptionb(config->options, "always_flush_cache");
 659
 660    screen->precompile = env_var_as_boolean("shader_precompile", true);
 661
 662    isl_device_init(&screen->isl_dev, &screen->devinfo, false);
 663
 664    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 665    screen->compiler->shader_debug_log = iris_shader_debug_log;
 666    screen->compiler->shader_perf_log = iris_shader_perf_log;
 667    screen->compiler->supports_pull_constants = false;
 668    screen->compiler->supports_shader_constants = true;
 669    screen->compiler->compact_params = false;
 670
 671    iris_disk_cache_init(screen);
 672
 673    slab_create_parent(&screen->transfer_pool,
 674                       sizeof(struct iris_transfer), 64);
 675
 676    screen->subslice_total =
 677       iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
 678    assert(screen->subslice_total >= 1);
 679
 680    struct pipe_screen *pscreen = &screen->base;
 681
 682    iris_init_screen_fence_functions(pscreen);
 683    iris_init_screen_resource_functions(pscreen);
 684
 685    pscreen->destroy = iris_destroy_screen;
 686    pscreen->get_name = iris_get_name;
 687    pscreen->get_vendor = iris_get_vendor;
 688    pscreen->get_device_vendor = iris_get_device_vendor;
 689    pscreen->get_param = iris_get_param;
 690    pscreen->get_shader_param = iris_get_shader_param;
 691    pscreen->get_compute_param = iris_get_compute_param;
 692    pscreen->get_paramf = iris_get_paramf;
 693    pscreen->get_compiler_options = iris_get_compiler_options;
 694    pscreen->get_disk_shader_cache = iris_get_disk_shader_cache;
 695    pscreen->is_format_supported = iris_is_format_supported;
 696    pscreen->context_create = iris_create_context;
 697    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 698    pscreen->get_timestamp = iris_get_timestamp;
 699    pscreen->query_memory_info = iris_query_memory_info;
 700    pscreen->get_driver_query_group_info = iris_get_monitor_group_info;
 701    pscreen->get_driver_query_info = iris_get_monitor_info;
 702
 703    return pscreen;
 704 }