src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/debug.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_format.h"
  43 #include "util/u_transfer_helper.h"
  44 #include "util/u_upload_mgr.h"
  45 #include "util/ralloc.h"
  46 #include "util/xmlconfig.h"
  47 #include "drm-uapi/i915_drm.h"
  48 #include "iris_context.h"
  49 #include "iris_defines.h"
  50 #include "iris_fence.h"
  51 #include "iris_pipe.h"
  52 #include "iris_resource.h"
  53 #include "iris_screen.h"
  54 #include "intel/compiler/brw_compiler.h"
  55
  56 static void
  57 iris_flush_frontbuffer(struct pipe_screen *_screen,
  58                        struct pipe_resource *resource,
  59                        unsigned level, unsigned layer,
  60                        void *context_private, struct pipe_box *box)
  61 {
  62 }
  63
  64 static const char *
  65 iris_get_vendor(struct pipe_screen *pscreen)
  66 {
  67    return "Intel";
  68 }
  69
  70 static const char *
  71 iris_get_device_vendor(struct pipe_screen *pscreen)
  72 {
  73    return "Intel";
  74 }
  75
  76 static const char *
  77 iris_get_name(struct pipe_screen *pscreen)
  78 {
  79    struct iris_screen *screen = (struct iris_screen *)pscreen;
  80    static char buf[128];
  81    const char *chipset;
  82
  83    switch (screen->pci_id) {
  84 #undef CHIPSET
  85 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  86 #include "pci_ids/i965_pci_ids.h"
  87    default:
  88       chipset = "Unknown Intel Chipset";
  89       break;
  90    }
  91
  92    snprintf(buf, sizeof(buf), "Mesa %s", chipset);
  93    return buf;
  94 }
  95
  96 static uint64_t
  97 get_aperture_size(int fd)
  98 {
  99    struct drm_i915_gem_get_aperture aperture = {};
 100    drm_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
 101    return aperture.aper_size;
 102 }
 103
 104 static int
 105 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 106 {
 107    struct iris_screen *screen = (struct iris_screen *)pscreen;
 108    const struct gen_device_info *devinfo = &screen->devinfo;
 109
 110    switch (param) {
 111    case PIPE_CAP_NPOT_TEXTURES:
 112    case PIPE_CAP_ANISOTROPIC_FILTER:
 113    case PIPE_CAP_POINT_SPRITE:
 114    case PIPE_CAP_OCCLUSION_QUERY:
 115    case PIPE_CAP_QUERY_TIME_ELAPSED:
 116    case PIPE_CAP_TEXTURE_SWIZZLE:
 117    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 118    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 119    case PIPE_CAP_SM3:
 120    case PIPE_CAP_PRIMITIVE_RESTART:
 121    case PIPE_CAP_INDEP_BLEND_ENABLE:
 122    case PIPE_CAP_INDEP_BLEND_FUNC:
 123    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 124    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 125    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 126    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 127    case PIPE_CAP_TGSI_INSTANCEID:
 128    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 129    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 130    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 131    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 132    case PIPE_CAP_CONDITIONAL_RENDER:
 133    case PIPE_CAP_TEXTURE_BARRIER:
 134    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 135    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 136    case PIPE_CAP_COMPUTE:
 137    case PIPE_CAP_START_INSTANCE:
 138    case PIPE_CAP_QUERY_TIMESTAMP:
 139    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 140    case PIPE_CAP_CUBE_MAP_ARRAY:
 141    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 142    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 143    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 144    case PIPE_CAP_TEXTURE_QUERY_LOD:
 145    case PIPE_CAP_SAMPLE_SHADING:
 146    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 147    case PIPE_CAP_DRAW_INDIRECT:
 148    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 149    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 150    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 151    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 152    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 153    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 154    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 155    case PIPE_CAP_ACCELERATED:
 156    case PIPE_CAP_UMA:
 157    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 158    case PIPE_CAP_CLIP_HALFZ:
 159    case PIPE_CAP_TGSI_TEXCOORD:
 160    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 161    case PIPE_CAP_DOUBLES:
 162    case PIPE_CAP_INT64:
 163    case PIPE_CAP_INT64_DIVMOD:
 164    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 165    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 166    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 167    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 168    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 169    case PIPE_CAP_CULL_DISTANCE:
 170    case PIPE_CAP_PACKED_UNIFORMS:
 171    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 172    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 173    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 174    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 175    case PIPE_CAP_QUERY_SO_OVERFLOW:
 176    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 177    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 178    case PIPE_CAP_TGSI_TXQS:
 179    case PIPE_CAP_TGSI_CLOCK:
 180    case PIPE_CAP_TGSI_BALLOT:
 181    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 182    case PIPE_CAP_CLEAR_TEXTURE:
 183    case PIPE_CAP_TGSI_VOTE:
 184    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 185    case PIPE_CAP_TEXTURE_GATHER_SM5:
 186    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 187    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 188    case PIPE_CAP_LOAD_CONSTBUF:
 189    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 190    case PIPE_CAP_DRAW_PARAMETERS:
 191    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 192    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 193    case PIPE_CAP_INVALIDATE_BUFFER:
 194    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 195    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
 196       return true;
 197    case PIPE_CAP_FBFETCH:
 198       /* TODO: Support non-coherent FB fetch on Broadwell */
 199       return devinfo->gen >= 9 ? BRW_MAX_DRAW_BUFFERS : 0;
 200    case PIPE_CAP_FBFETCH_COHERENT:
 201    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 202    case PIPE_CAP_POST_DEPTH_COVERAGE:
 203    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 204    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 205    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 206       return devinfo->gen >= 9;
 207    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 208       return 1;
 209    case PIPE_CAP_MAX_RENDER_TARGETS:
 210       return BRW_MAX_DRAW_BUFFERS;
 211    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 212       return 16384;
 213    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 214       return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
 215    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 216       return 12; /* 2048x2048 */
 217    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 218       return 4;
 219    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 220       return 2048;
 221    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 222       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 223    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 224       return BRW_MAX_SOL_BINDINGS;
 225    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 226       return 460;
 227    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 228       return 140;
 229    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 230       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 231       return 32;
 232    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 233       return IRIS_MAP_BUFFER_ALIGNMENT;
 234    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 235       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 236        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 237        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 238        * GPU and the CPU can be updating disjoint regions of the buffer
 239        * simultaneously and that will break if the regions overlap the same
 240        * cacheline.
 241        */
 242       return 64;
 243    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 244       return 1 << 27;
 245    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 246       return 16; // XXX: u_screen says 256 is the minimum value...
 247    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 248       return true; // XXX: ?????
 249    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 250       return IRIS_MAX_TEXTURE_BUFFER_SIZE;
 251    case PIPE_CAP_MAX_VIEWPORTS:
 252       return 16;
 253    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 254       return 256;
 255    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 256       return 1024;
 257    case PIPE_CAP_MAX_GS_INVOCATIONS:
 258       return 32;
 259    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 260       return 4;
 261    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 262       return -32;
 263    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 264       return 31;
 265    case PIPE_CAP_MAX_VERTEX_STREAMS:
 266       return 4;
 267    case PIPE_CAP_VENDOR_ID:
 268       return 0x8086;
 269    case PIPE_CAP_DEVICE_ID:
 270       return screen->pci_id;
 271    case PIPE_CAP_VIDEO_MEMORY: {
 272       /* Once a batch uses more than 75% of the maximum mappable size, we
 273        * assume that there's some fragmentation, and we start doing extra
 274        * flushing, etc.  That's the big cliff apps will care about.
 275        */
 276       const unsigned gpu_mappable_megabytes =
 277          (screen->aperture_bytes * 3 / 4) / (1024 * 1024);
 278
 279       const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
 280       const long system_page_size = sysconf(_SC_PAGE_SIZE);
 281
 282       if (system_memory_pages <= 0 || system_page_size <= 0)
 283          return -1;
 284
 285       const uint64_t system_memory_bytes =
 286          (uint64_t) system_memory_pages * (uint64_t) system_page_size;
 287
 288       const unsigned system_memory_megabytes =
 289          (unsigned) (system_memory_bytes / (1024 * 1024));
 290
 291       return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
 292    }
 293    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 294    case PIPE_CAP_MAX_VARYINGS:
 295       return 32;
 296    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 297       /* AMD_pinned_memory assumes the flexibility of using client memory
 298        * for any buffer (incl. vertex buffers) which rules out the prospect
 299        * of using snooped buffers, as using snooped buffers without
 300        * cogniscience is likely to be detrimental to performance and require
 301        * extensive checking in the driver for correctness, e.g. to prevent
 302        * illegal snoop <-> snoop transfers.
 303        */
 304       return devinfo->has_llc;
 305
 306    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 307       return PIPE_CONTEXT_PRIORITY_LOW |
 308              PIPE_CONTEXT_PRIORITY_MEDIUM |
 309              PIPE_CONTEXT_PRIORITY_HIGH;
 310
 311    // XXX: don't hardcode 00:00:02.0 PCI here
 312    case PIPE_CAP_PCI_GROUP:
 313       return 0;
 314    case PIPE_CAP_PCI_BUS:
 315       return 0;
 316    case PIPE_CAP_PCI_DEVICE:
 317       return 2;
 318    case PIPE_CAP_PCI_FUNCTION:
 319       return 0;
 320
 321    default:
 322       return u_pipe_screen_get_param_defaults(pscreen, param);
 323    }
 324    return 0;
 325 }
 326
 327 static float
 328 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 329 {
 330    switch (param) {
 331    case PIPE_CAPF_MAX_LINE_WIDTH:
 332    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 333       return 7.375f;
 334
 335    case PIPE_CAPF_MAX_POINT_WIDTH:
 336    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 337       return 255.0f;
 338
 339    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 340       return 16.0f;
 341    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 342       return 15.0f;
 343    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 344    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 345    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 346       return 0.0f;
 347    default:
 348       unreachable("unknown param");
 349    }
 350 }
 351
 352 static int
 353 iris_get_shader_param(struct pipe_screen *pscreen,
 354                       enum pipe_shader_type p_stage,
 355                       enum pipe_shader_cap param)
 356 {
 357    gl_shader_stage stage = stage_from_pipe(p_stage);
 358
 359    /* this is probably not totally correct.. but it's a start: */
 360    switch (param) {
 361    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 362       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 363    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 364    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 365    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 366       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 367
 368    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 369       return UINT_MAX;
 370
 371    case PIPE_SHADER_CAP_MAX_INPUTS:
 372       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 373    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 374       return 32;
 375    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 376       return 16 * 1024 * sizeof(float);
 377    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 378       return 16;
 379    case PIPE_SHADER_CAP_MAX_TEMPS:
 380       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 381    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 382       return 0;
 383    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 384    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 385    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 386    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 387       /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
 388        * which we don't want.  Our compiler backend will check brw_compiler's
 389        * options and call nir_lower_indirect_derefs appropriately anyway.
 390        */
 391       return true;
 392    case PIPE_SHADER_CAP_SUBROUTINES:
 393       return 0;
 394    case PIPE_SHADER_CAP_INTEGERS:
 395    case PIPE_SHADER_CAP_SCALAR_ISA:
 396       return 1;
 397    case PIPE_SHADER_CAP_INT64_ATOMICS:
 398    case PIPE_SHADER_CAP_FP16:
 399       return 0;
 400    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 401    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 402    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 403       return IRIS_MAX_TEXTURE_SAMPLERS;
 404    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 405       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 406    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 407    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 408       return 0;
 409    case PIPE_SHADER_CAP_PREFERRED_IR:
 410       return PIPE_SHADER_IR_NIR;
 411    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 412       return 1 << PIPE_SHADER_IR_NIR;
 413    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 414       return 32;
 415    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 416    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 417       return 1;
 418    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 419    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 420    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 421    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 422    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 423    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 424       return 0;
 425    default:
 426       unreachable("unknown shader param");
 427    }
 428 }
 429
 430 static int
 431 iris_get_compute_param(struct pipe_screen *pscreen,
 432                        enum pipe_shader_ir ir_type,
 433                        enum pipe_compute_cap param,
 434                        void *ret)
 435 {
 436    struct iris_screen *screen = (struct iris_screen *)pscreen;
 437    const struct gen_device_info *devinfo = &screen->devinfo;
 438
 439    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 440    const uint32_t max_invocations = 32 * max_threads;
 441
 442 #define RET(x) do {                  \
 443    if (ret)                          \
 444       memcpy(ret, x, sizeof(x));     \
 445    return sizeof(x);                 \
 446 } while (0)
 447
 448    switch (param) {
 449    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 450       RET((uint32_t []){ 32 });
 451
 452    case PIPE_COMPUTE_CAP_IR_TARGET:
 453       if (ret)
 454          strcpy(ret, "gen");
 455       return 4;
 456
 457    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 458       RET((uint64_t []) { 3 });
 459
 460    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 461       RET(((uint64_t []) { 65535, 65535, 65535 }));
 462
 463    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 464       /* MaxComputeWorkGroupSize[0..2] */
 465       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 466
 467    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 468       /* MaxComputeWorkGroupInvocations */
 469       RET((uint64_t []) { max_invocations });
 470
 471    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 472       /* MaxComputeSharedMemorySize */
 473       RET((uint64_t []) { 64 * 1024 });
 474
 475    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 476       RET((uint32_t []) { 1 });
 477
 478    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 479       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 480
 481    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 482    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 483    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 484    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 485    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 486    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 487    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 488       // XXX: I think these are for Clover...
 489       return 0;
 490
 491    default:
 492       unreachable("unknown compute param");
 493    }
 494 }
 495
 496 static uint64_t
 497 iris_get_timestamp(struct pipe_screen *pscreen)
 498 {
 499    struct iris_screen *screen = (struct iris_screen *) pscreen;
 500    const unsigned TIMESTAMP = 0x2358;
 501    uint64_t result;
 502
 503    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 504
 505    result = iris_timebase_scale(&screen->devinfo, result);
 506    result &= (1ull << TIMESTAMP_BITS) - 1;
 507
 508    return result;
 509 }
 510
 511 static void
 512 iris_destroy_screen(struct pipe_screen *pscreen)
 513 {
 514    struct iris_screen *screen = (struct iris_screen *) pscreen;
 515    iris_bo_unreference(screen->workaround_bo);
 516    u_transfer_helper_destroy(pscreen->transfer_helper);
 517    iris_bufmgr_destroy(screen->bufmgr);
 518    disk_cache_destroy(screen->disk_cache);
 519    ralloc_free(screen);
 520 }
 521
 522 static void
 523 iris_query_memory_info(struct pipe_screen *pscreen,
 524                        struct pipe_memory_info *info)
 525 {
 526 }
 527
 528 static const void *
 529 iris_get_compiler_options(struct pipe_screen *pscreen,
 530                           enum pipe_shader_ir ir,
 531                           enum pipe_shader_type pstage)
 532 {
 533    struct iris_screen *screen = (struct iris_screen *) pscreen;
 534    gl_shader_stage stage = stage_from_pipe(pstage);
 535    assert(ir == PIPE_SHADER_IR_NIR);
 536
 537    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 538 }
 539
 540 static struct disk_cache *
 541 iris_get_disk_shader_cache(struct pipe_screen *pscreen)
 542 {
 543    struct iris_screen *screen = (struct iris_screen *) pscreen;
 544    return screen->disk_cache;
 545 }
 546
 547 static int
 548 iris_getparam(struct iris_screen *screen, int param, int *value)
 549 {
 550    struct drm_i915_getparam gp = { .param = param, .value = value };
 551
 552    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 553       return -errno;
 554
 555    return 0;
 556 }
 557
 558 static int
 559 iris_getparam_integer(struct iris_screen *screen, int param)
 560 {
 561    int value = -1;
 562
 563    if (iris_getparam(screen, param, &value) == 0)
 564       return value;
 565
 566    return -1;
 567 }
 568
 569 static void
 570 iris_shader_debug_log(void *data, const char *fmt, ...)
 571 {
 572    struct pipe_debug_callback *dbg = data;
 573    unsigned id = 0;
 574    va_list args;
 575
 576    if (!dbg->debug_message)
 577       return;
 578
 579    va_start(args, fmt);
 580    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 581    va_end(args);
 582 }
 583
 584 static void
 585 iris_shader_perf_log(void *data, const char *fmt, ...)
 586 {
 587    struct pipe_debug_callback *dbg = data;
 588    unsigned id = 0;
 589    va_list args;
 590    va_start(args, fmt);
 591
 592    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
 593       va_list args_copy;
 594       va_copy(args_copy, args);
 595       vfprintf(stderr, fmt, args_copy);
 596       va_end(args_copy);
 597    }
 598
 599    if (dbg->debug_message) {
 600       dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 601    }
 602
 603    va_end(args);
 604 }
 605
 606 struct pipe_screen *
 607 iris_screen_create(int fd, const struct pipe_screen_config *config)
 608 {
 609    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 610    if (!screen)
 611       return NULL;
 612
 613    screen->fd = fd;
 614    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 615
 616    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 617       return NULL;
 618
 619    if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
 620       return NULL;
 621
 622    screen->devinfo.timestamp_frequency =
 623       iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY);
 624
 625    screen->aperture_bytes = get_aperture_size(fd);
 626
 627    if (getenv("INTEL_NO_HW") != NULL)
 628       screen->no_hw = true;
 629
 630    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 631    if (!screen->bufmgr)
 632       return NULL;
 633
 634    screen->workaround_bo =
 635       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 636    if (!screen->workaround_bo)
 637       return NULL;
 638
 639    brw_process_intel_debug_variable();
 640
 641    screen->driconf.dual_color_blend_by_location =
 642       driQueryOptionb(config->options, "dual_color_blend_by_location");
 643
 644    screen->precompile = env_var_as_boolean("shader_precompile", true);
 645
 646    isl_device_init(&screen->isl_dev, &screen->devinfo, false);
 647
 648    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 649    screen->compiler->shader_debug_log = iris_shader_debug_log;
 650    screen->compiler->shader_perf_log = iris_shader_perf_log;
 651    screen->compiler->supports_pull_constants = false;
 652    screen->compiler->supports_shader_constants = true;
 653
 654    iris_disk_cache_init(screen);
 655
 656    slab_create_parent(&screen->transfer_pool,
 657                       sizeof(struct iris_transfer), 64);
 658
 659    screen->subslice_total =
 660       iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
 661    assert(screen->subslice_total >= 1);
 662
 663    struct pipe_screen *pscreen = &screen->base;
 664
 665    iris_init_screen_fence_functions(pscreen);
 666    iris_init_screen_resource_functions(pscreen);
 667
 668    pscreen->destroy = iris_destroy_screen;
 669    pscreen->get_name = iris_get_name;
 670    pscreen->get_vendor = iris_get_vendor;
 671    pscreen->get_device_vendor = iris_get_device_vendor;
 672    pscreen->get_param = iris_get_param;
 673    pscreen->get_shader_param = iris_get_shader_param;
 674    pscreen->get_compute_param = iris_get_compute_param;
 675    pscreen->get_paramf = iris_get_paramf;
 676    pscreen->get_compiler_options = iris_get_compiler_options;
 677    pscreen->get_disk_shader_cache = iris_get_disk_shader_cache;
 678    pscreen->is_format_supported = iris_is_format_supported;
 679    pscreen->context_create = iris_create_context;
 680    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 681    pscreen->get_timestamp = iris_get_timestamp;
 682    pscreen->query_memory_info = iris_query_memory_info;
 683
 684    return pscreen;
 685 }