src/gallium/drivers/iris/iris_screen.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_SCREEN_H
  24 #define IRIS_SCREEN_H
  25
  26 #include "pipe/p_screen.h"
  27 #include "state_tracker/drm_driver.h"
  28 #include "util/disk_cache.h"
  29 #include "util/slab.h"
  30 #include "util/u_screen.h"
  31 #include "intel/dev/gen_device_info.h"
  32 #include "intel/isl/isl.h"
  33 #include "iris_bufmgr.h"
  34
  35 struct iris_bo;
  36 struct iris_monitor_config;
  37 struct gen_l3_config;
  38
  39 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
  40 #define WRITE_ONCE(x, v) *(volatile __typeof__(x) *)&(x) = (v)
  41
  42 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  43 #define IRIS_MAX_SOL_BUFFERS 4
  44 #define IRIS_MAP_BUFFER_ALIGNMENT 64
  45
  46 struct iris_screen {
  47    struct pipe_screen base;
  48
  49    /** Global slab allocator for iris_transfer_map objects */
  50    struct slab_parent_pool transfer_pool;
  51
  52    /** drm device file descriptor */
  53    int fd;
  54
  55    /** PCI ID for our GPU device */
  56    int pci_id;
  57
  58    bool no_hw;
  59
  60    /** Global program_string_id counter (see get_program_string_id()) */
  61    unsigned program_id;
  62
  63    /** Precompile shaders at link time?  (Can be disabled for debugging.) */
  64    bool precompile;
  65
  66    /** driconf options and application workarounds */
  67    struct {
  68       /** Dual color blend by location instead of index (for broken apps) */
  69       bool dual_color_blend_by_location;
  70       bool disable_throttling;
  71       bool always_flush_cache;
  72    } driconf;
  73
  74    unsigned subslice_total;
  75
  76    uint64_t aperture_bytes;
  77
  78    struct gen_device_info devinfo;
  79    struct isl_device isl_dev;
  80    struct iris_bufmgr *bufmgr;
  81    struct brw_compiler *compiler;
  82    struct iris_monitor_config *monitor_cfg;
  83
  84    const struct gen_l3_config *l3_config_3d;
  85    const struct gen_l3_config *l3_config_cs;
  86
  87    /**
  88     * A buffer containing nothing useful, for hardware workarounds that
  89     * require scratch writes or reads from some unimportant memory.
  90     */
  91    struct iris_bo *workaround_bo;
  92
  93    struct disk_cache *disk_cache;
  94 };
  95
  96 struct pipe_screen *
  97 iris_screen_create(int fd, const struct pipe_screen_config *config);
  98
  99 bool
 100 iris_is_format_supported(struct pipe_screen *pscreen,
 101                          enum pipe_format format,
 102                          enum pipe_texture_target target,
 103                          unsigned sample_count,
 104                          unsigned storage_sample_count,
 105                          unsigned usage);
 106
 107 void iris_disk_cache_init(struct iris_screen *screen);
 108
 109 #endif