src/gallium/drivers/iris/iris_screen.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_SCREEN_H
  24 #define IRIS_SCREEN_H
  25
  26 #include "pipe/p_screen.h"
  27 #include "state_tracker/drm_driver.h"
  28 #include "util/disk_cache.h"
  29 #include "util/slab.h"
  30 #include "util/u_screen.h"
  31 #include "intel/dev/gen_device_info.h"
  32 #include "intel/isl/isl.h"
  33 #include "iris_bufmgr.h"
  34 #include "iris_binder.h"
  35 #include "iris_resource.h"
  36
  37 struct gen_l3_config;
  38 struct brw_vue_map;
  39 struct iris_monitor_config;
  40 struct iris_vs_prog_key;
  41 struct iris_tcs_prog_key;
  42 struct iris_tes_prog_key;
  43 struct iris_gs_prog_key;
  44 struct iris_fs_prog_key;
  45 struct iris_cs_prog_key;
  46 enum iris_program_cache_id;
  47
  48 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
  49 #define WRITE_ONCE(x, v) *(volatile __typeof__(x) *)&(x) = (v)
  50
  51 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  52 #define IRIS_MAX_SOL_BUFFERS 4
  53 #define IRIS_MAP_BUFFER_ALIGNMENT 64
  54
  55 /**
  56  * Virtual table for generation-specific (genxml) function calls.
  57  */
  58 struct iris_vtable {
  59    void (*destroy_state)(struct iris_context *ice);
  60    void (*init_render_context)(struct iris_batch *batch);
  61    void (*init_compute_context)(struct iris_batch *batch);
  62    void (*upload_render_state)(struct iris_context *ice,
  63                                struct iris_batch *batch,
  64                                const struct pipe_draw_info *draw);
  65    void (*update_surface_base_address)(struct iris_batch *batch,
  66                                        struct iris_binder *binder);
  67    void (*upload_compute_state)(struct iris_context *ice,
  68                                 struct iris_batch *batch,
  69                                 const struct pipe_grid_info *grid);
  70    void (*rebind_buffer)(struct iris_context *ice,
  71                          struct iris_resource *res);
  72    void (*resolve_conditional_render)(struct iris_context *ice);
  73    void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
  74                                uint32_t src);
  75    void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
  76                                uint32_t src);
  77    void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
  78                                uint32_t val);
  79    void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
  80                                uint64_t val);
  81    void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
  82                                struct iris_bo *bo, uint32_t offset);
  83    void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
  84                                struct iris_bo *bo, uint32_t offset);
  85    void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
  86                                 struct iris_bo *bo, uint32_t offset,
  87                                 bool predicated);
  88    void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
  89                                 struct iris_bo *bo, uint32_t offset,
  90                                 bool predicated);
  91    void (*store_data_imm32)(struct iris_batch *batch,
  92                             struct iris_bo *bo, uint32_t offset,
  93                             uint32_t value);
  94    void (*store_data_imm64)(struct iris_batch *batch,
  95                             struct iris_bo *bo, uint32_t offset,
  96                             uint64_t value);
  97    void (*copy_mem_mem)(struct iris_batch *batch,
  98                         struct iris_bo *dst_bo, uint32_t dst_offset,
  99                         struct iris_bo *src_bo, uint32_t src_offset,
 100                         unsigned bytes);
 101    void (*emit_raw_pipe_control)(struct iris_batch *batch,
 102                                  const char *reason, uint32_t flags,
 103                                  struct iris_bo *bo, uint32_t offset,
 104                                  uint64_t imm);
 105
 106    void (*emit_mi_report_perf_count)(struct iris_batch *batch,
 107                                      struct iris_bo *bo,
 108                                      uint32_t offset_in_bytes,
 109                                      uint32_t report_id);
 110
 111    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 112    void (*store_derived_program_state)(struct iris_context *ice,
 113                                        enum iris_program_cache_id cache_id,
 114                                        struct iris_compiled_shader *shader);
 115    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 116                                     const struct brw_vue_map *vue_map);
 117    void (*populate_vs_key)(const struct iris_context *ice,
 118                            const struct shader_info *info,
 119                            gl_shader_stage last_stage,
 120                            struct iris_vs_prog_key *key);
 121    void (*populate_tcs_key)(const struct iris_context *ice,
 122                             struct iris_tcs_prog_key *key);
 123    void (*populate_tes_key)(const struct iris_context *ice,
 124                             const struct shader_info *info,
 125                             gl_shader_stage last_stage,
 126                             struct iris_tes_prog_key *key);
 127    void (*populate_gs_key)(const struct iris_context *ice,
 128                            const struct shader_info *info,
 129                            gl_shader_stage last_stage,
 130                            struct iris_gs_prog_key *key);
 131    void (*populate_fs_key)(const struct iris_context *ice,
 132                            const struct shader_info *info,
 133                            struct iris_fs_prog_key *key);
 134    void (*populate_cs_key)(const struct iris_context *ice,
 135                            struct iris_cs_prog_key *key);
 136    void (*lost_genx_state)(struct iris_context *ice, struct iris_batch *batch);
 137 };
 138
 139 struct iris_screen {
 140    struct pipe_screen base;
 141
 142    uint32_t refcount;
 143
 144    /** Global slab allocator for iris_transfer_map objects */
 145    struct slab_parent_pool transfer_pool;
 146
 147    /** drm device file descriptor, on shared with bufmgr, do not close. */
 148    int fd;
 149
 150    /** PCI ID for our GPU device */
 151    int pci_id;
 152
 153    bool no_hw;
 154
 155    struct iris_vtable vtbl;
 156
 157    /** Global program_string_id counter (see get_program_string_id()) */
 158    unsigned program_id;
 159
 160    /** Precompile shaders at link time?  (Can be disabled for debugging.) */
 161    bool precompile;
 162
 163    /** driconf options and application workarounds */
 164    struct {
 165       /** Dual color blend by location instead of index (for broken apps) */
 166       bool dual_color_blend_by_location;
 167       bool disable_throttling;
 168       bool always_flush_cache;
 169    } driconf;
 170
 171    unsigned subslice_total;
 172
 173    uint64_t aperture_bytes;
 174
 175    struct gen_device_info devinfo;
 176    struct isl_device isl_dev;
 177    struct iris_bufmgr *bufmgr;
 178    struct brw_compiler *compiler;
 179    struct iris_monitor_config *monitor_cfg;
 180
 181    const struct gen_l3_config *l3_config_3d;
 182    const struct gen_l3_config *l3_config_cs;
 183
 184    /**
 185     * A buffer containing nothing useful, for hardware workarounds that
 186     * require scratch writes or reads from some unimportant memory.
 187     */
 188    struct iris_bo *workaround_bo;
 189
 190    struct disk_cache *disk_cache;
 191 };
 192
 193 struct pipe_screen *
 194 iris_screen_create(int fd, const struct pipe_screen_config *config);
 195
 196 void iris_screen_destroy(struct iris_screen *screen);
 197
 198 UNUSED static inline struct pipe_screen *
 199 iris_pscreen_ref(struct pipe_screen *pscreen)
 200 {
 201    struct iris_screen *screen = (struct iris_screen *) pscreen;
 202
 203    p_atomic_inc(&screen->refcount);
 204    return pscreen;
 205 }
 206
 207 UNUSED static inline void
 208 iris_pscreen_unref(struct pipe_screen *pscreen)
 209 {
 210    struct iris_screen *screen = (struct iris_screen *) pscreen;
 211
 212    if (p_atomic_dec_zero(&screen->refcount))
 213       iris_screen_destroy(screen);
 214 }
 215
 216 bool
 217 iris_is_format_supported(struct pipe_screen *pscreen,
 218                          enum pipe_format format,
 219                          enum pipe_texture_target target,
 220                          unsigned sample_count,
 221                          unsigned storage_sample_count,
 222                          unsigned usage);
 223
 224 void iris_disk_cache_init(struct iris_screen *screen);
 225
 226 #endif