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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_inlines.h"
92 #include "util/u_format.h"
93 #include "util/u_framebuffer.h"
94 #include "util/u_transfer.h"
95 #include "util/u_upload_mgr.h"
96 #include "util/u_viewport.h"
99 #include "intel/compiler/brw_compiler.h"
100 #include "intel/common/gen_l3_config.h"
101 #include "intel/common/gen_sample_positions.h"
102 #include "iris_batch.h"
103 #include "iris_context.h"
104 #include "iris_defines.h"
105 #include "iris_pipe.h"
106 #include "iris_resource.h"
108 #define __gen_address_type struct iris_address
109 #define __gen_user_data struct iris_batch
111 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
114 __gen_combine_address(struct iris_batch
*batch
, void *location
,
115 struct iris_address addr
, uint32_t delta
)
117 uint64_t result
= addr
.offset
+ delta
;
120 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
121 /* Assume this is a general address, not relative to a base. */
122 result
+= addr
.bo
->gtt_offset
;
128 #define __genxml_cmd_length(cmd) cmd ## _length
129 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
130 #define __genxml_cmd_header(cmd) cmd ## _header
131 #define __genxml_cmd_pack(cmd) cmd ## _pack
133 #define _iris_pack_command(batch, cmd, dst, name) \
134 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
135 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
136 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
140 #define iris_pack_command(cmd, dst, name) \
141 _iris_pack_command(NULL, cmd, dst, name)
143 #define iris_pack_state(cmd, dst, name) \
144 for (struct cmd name = {}, \
145 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
146 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
149 #define iris_emit_cmd(batch, cmd, name) \
150 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
152 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
154 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
155 for (uint32_t i = 0; i < num_dwords; i++) \
156 dw[i] = (dwords0)[i] | (dwords1)[i]; \
157 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
160 #include "genxml/genX_pack.h"
161 #include "genxml/gen_macros.h"
162 #include "genxml/genX_bits.h"
164 #define MOCS_WB (2 << 1)
167 * Statically assert that PIPE_* enums match the hardware packets.
168 * (As long as they match, we don't need to translate them.)
170 UNUSED
static void pipe_asserts()
172 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
174 /* pipe_logicop happens to match the hardware. */
175 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
176 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
177 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
178 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
179 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
180 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
181 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
182 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
183 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
184 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
185 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
186 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
187 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
188 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
189 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
190 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
192 /* pipe_blend_func happens to match the hardware. */
193 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
194 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
195 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
196 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
197 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
198 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
199 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
200 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
201 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
202 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
203 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
204 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
205 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
206 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
207 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
211 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
213 /* pipe_blend_func happens to match the hardware. */
214 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
215 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
216 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
217 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
218 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
220 /* pipe_stencil_op happens to match the hardware. */
221 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
222 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
223 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
224 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
225 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
226 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
227 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
228 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
230 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
231 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
232 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
237 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
239 static const unsigned map
[] = {
240 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
241 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
242 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
243 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
244 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
245 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
246 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
247 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
248 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
249 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
250 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
251 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
252 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
253 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
254 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
257 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
261 translate_compare_func(enum pipe_compare_func pipe_func
)
263 static const unsigned map
[] = {
264 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
265 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
266 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
267 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
268 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
269 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
270 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
271 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
273 return map
[pipe_func
];
277 translate_shadow_func(enum pipe_compare_func pipe_func
)
279 /* Gallium specifies the result of shadow comparisons as:
281 * 1 if ref <op> texel,
286 * 0 if texel <op> ref,
289 * So we need to flip the operator and also negate.
291 static const unsigned map
[] = {
292 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
293 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
294 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
295 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
296 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
297 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
298 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
299 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
301 return map
[pipe_func
];
305 translate_cull_mode(unsigned pipe_face
)
307 static const unsigned map
[4] = {
308 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
309 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
310 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
311 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
313 return map
[pipe_face
];
317 translate_fill_mode(unsigned pipe_polymode
)
319 static const unsigned map
[4] = {
320 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
321 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
322 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
323 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
325 return map
[pipe_polymode
];
329 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
331 static const unsigned map
[] = {
332 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
333 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
334 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
336 return map
[pipe_mip
];
340 translate_wrap(unsigned pipe_wrap
)
342 static const unsigned map
[] = {
343 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
344 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
345 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
346 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
347 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
348 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
350 /* These are unsupported. */
351 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
352 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
354 return map
[pipe_wrap
];
357 static struct iris_address
358 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
360 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
361 * validation list at CSO creation time, instead of draw time.
363 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
366 static struct iris_address
367 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
369 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
370 * validation list at CSO creation time, instead of draw time.
372 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
376 * Allocate space for some indirect state.
378 * Return a pointer to the map (to fill it out) and a state ref (for
379 * referring to the state in GPU commands).
382 upload_state(struct u_upload_mgr
*uploader
,
383 struct iris_state_ref
*ref
,
388 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
393 * Stream out temporary/short-lived state.
395 * This allocates space, pins the BO, and includes the BO address in the
396 * returned offset (which works because all state lives in 32-bit memory
400 stream_state(struct iris_batch
*batch
,
401 struct u_upload_mgr
*uploader
,
402 struct pipe_resource
**out_res
,
405 uint32_t *out_offset
)
409 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
411 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
412 iris_use_pinned_bo(batch
, bo
, false);
414 *out_offset
+= iris_bo_offset_from_base_address(bo
);
420 * stream_state() + memcpy.
423 emit_state(struct iris_batch
*batch
,
424 struct u_upload_mgr
*uploader
,
425 struct pipe_resource
**out_res
,
432 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
435 memcpy(map
, data
, size
);
441 * Did field 'x' change between 'old_cso' and 'new_cso'?
443 * (If so, we may want to set some dirty flags.)
445 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
446 #define cso_changed_memcmp(x) \
447 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
450 flush_for_state_base_change(struct iris_batch
*batch
)
452 /* Flush before emitting STATE_BASE_ADDRESS.
454 * This isn't documented anywhere in the PRM. However, it seems to be
455 * necessary prior to changing the surface state base adress. We've
456 * seen issues in Vulkan where we get GPU hangs when using multi-level
457 * command buffers which clear depth, reset state base address, and then
460 * Normally, in GL, we would trust the kernel to do sufficient stalls
461 * and flushes prior to executing our batch. However, it doesn't seem
462 * as if the kernel's flushing is always sufficient and we don't want to
465 * We make this an end-of-pipe sync instead of a normal flush because we
466 * do not know the current status of the GPU. On Haswell at least,
467 * having a fast-clear operation in flight at the same time as a normal
468 * rendering operation can cause hangs. Since the kernel's flushing is
469 * insufficient, we need to ensure that any rendering operations from
470 * other processes are definitely complete before we try to do our own
471 * rendering. It's a bit of a big hammer but it appears to work.
473 iris_emit_end_of_pipe_sync(batch
,
474 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
475 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
476 PIPE_CONTROL_DATA_CACHE_FLUSH
);
480 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
482 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
483 lri
.RegisterOffset
= reg
;
487 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
490 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
492 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
493 lrr
.SourceRegisterAddress
= src
;
494 lrr
.DestinationRegisterAddress
= dst
;
499 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
501 #if GEN_GEN >= 8 && GEN_GEN < 10
502 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
504 * Software must clear the COLOR_CALC_STATE Valid field in
505 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
506 * with Pipeline Select set to GPGPU.
508 * The internal hardware docs recommend the same workaround for Gen9
511 if (pipeline
== GPGPU
)
512 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
516 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
517 * PIPELINE_SELECT [DevBWR+]":
521 * Software must ensure all the write caches are flushed through a
522 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
523 * command to invalidate read only caches prior to programming
524 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
526 iris_emit_pipe_control_flush(batch
,
527 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
528 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
529 PIPE_CONTROL_DATA_CACHE_FLUSH
|
530 PIPE_CONTROL_CS_STALL
);
532 iris_emit_pipe_control_flush(batch
,
533 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
534 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
535 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
536 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
538 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
542 sel
.PipelineSelection
= pipeline
;
547 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
552 * "This chicken bit works around a hardware issue with barrier
553 * logic encountered when switching between GPGPU and 3D pipelines.
554 * To workaround the issue, this mode bit should be set after a
555 * pipeline is selected."
558 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
559 reg
.GLKBarrierMode
= value
;
560 reg
.GLKBarrierModeMask
= 1;
562 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
567 init_state_base_address(struct iris_batch
*batch
)
569 flush_for_state_base_change(batch
);
571 /* We program most base addresses once at context initialization time.
572 * Each base address points at a 4GB memory zone, and never needs to
573 * change. See iris_bufmgr.h for a description of the memory zones.
575 * The one exception is Surface State Base Address, which needs to be
576 * updated occasionally. See iris_binder.c for the details there.
578 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
580 // XXX: MOCS is stupid for this.
581 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
582 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
583 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
584 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
585 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
586 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
589 sba
.GeneralStateBaseAddressModifyEnable
= true;
590 sba
.DynamicStateBaseAddressModifyEnable
= true;
591 sba
.IndirectObjectBaseAddressModifyEnable
= true;
592 sba
.InstructionBaseAddressModifyEnable
= true;
593 sba
.GeneralStateBufferSizeModifyEnable
= true;
594 sba
.DynamicStateBufferSizeModifyEnable
= true;
595 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
596 sba
.IndirectObjectBufferSizeModifyEnable
= true;
597 sba
.InstructionBuffersizeModifyEnable
= true;
599 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
600 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
602 sba
.GeneralStateBufferSize
= 0xfffff;
603 sba
.IndirectObjectBufferSize
= 0xfffff;
604 sba
.InstructionBufferSize
= 0xfffff;
605 sba
.DynamicStateBufferSize
= 0xfffff;
610 * Upload the initial GPU state for a render context.
612 * This sets some invariant state that needs to be programmed a particular
613 * way, but we never actually change.
616 iris_init_render_context(struct iris_screen
*screen
,
617 struct iris_batch
*batch
,
618 struct iris_vtable
*vtbl
,
619 struct pipe_debug_callback
*dbg
)
621 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
624 emit_pipeline_select(batch
, _3D
);
626 init_state_base_address(batch
);
628 // XXX: INSTPM on Gen8
629 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
630 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
631 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
633 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
636 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
637 reg
.FloatBlendOptimizationEnable
= true;
638 reg
.FloatBlendOptimizationEnableMask
= true;
639 reg
.PartialResolveDisableInVC
= true;
640 reg
.PartialResolveDisableInVCMask
= true;
642 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
644 if (devinfo
->is_geminilake
)
645 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
649 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
650 reg
.HeaderlessMessageforPreemptableContexts
= 1;
651 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
653 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
658 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
659 * changing it dynamically. We set it to the maximum size here, and
660 * instead include the render target dimensions in the viewport, so
661 * viewport extents clipping takes care of pruning stray geometry.
663 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
664 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
665 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
668 /* Set the initial MSAA sample positions. */
669 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
670 GEN_SAMPLE_POS_1X(pat
._1xSample
);
671 GEN_SAMPLE_POS_2X(pat
._2xSample
);
672 GEN_SAMPLE_POS_4X(pat
._4xSample
);
673 GEN_SAMPLE_POS_8X(pat
._8xSample
);
674 GEN_SAMPLE_POS_16X(pat
._16xSample
);
677 /* Use the legacy AA line coverage computation. */
678 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
680 /* Disable chromakeying (it's for media) */
681 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
683 /* We want regular rendering, not special HiZ operations. */
684 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
686 /* No polygon stippling offsets are necessary. */
687 // XXX: may need to set an offset for origin-UL framebuffers
688 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
690 /* Set a static partitioning of the push constant area. */
691 // XXX: this may be a bad idea...could starve the push ringbuffers...
692 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
693 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
694 alloc
._3DCommandSubOpcode
= 18 + i
;
695 alloc
.ConstantBufferOffset
= 6 * i
;
696 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
702 iris_init_compute_context(struct iris_screen
*screen
,
703 struct iris_batch
*batch
,
704 struct iris_vtable
*vtbl
,
705 struct pipe_debug_callback
*dbg
)
707 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
709 emit_pipeline_select(batch
, GPGPU
);
711 const bool has_slm
= true;
712 const bool wants_dc_cache
= true;
714 const struct gen_l3_weights w
=
715 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
716 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
719 iris_pack_state(GENX(L3CNTLREG
), ®_val
, reg
) {
720 reg
.SLMEnable
= has_slm
;
722 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
723 * in L3CNTLREG register. The default setting of the bit is not the
724 * desirable behavior.
726 reg
.ErrorDetectionBehaviorControl
= true;
728 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
729 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
730 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
731 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
733 iris_emit_lri(batch
, L3CNTLREG
, reg_val
);
735 init_state_base_address(batch
);
738 if (devinfo
->is_geminilake
)
739 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
743 struct iris_vertex_buffer_state
{
744 /** The VERTEX_BUFFER_STATE hardware structure. */
745 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
747 /** The resource to source vertex data from. */
748 struct pipe_resource
*resource
;
751 struct iris_depth_buffer_state
{
752 /* Depth/HiZ/Stencil related hardware packets. */
753 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
754 GENX(3DSTATE_STENCIL_BUFFER_length
) +
755 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
756 GENX(3DSTATE_CLEAR_PARAMS_length
)];
760 * Generation-specific context state (ice->state.genx->...).
762 * Most state can go in iris_context directly, but these encode hardware
763 * packets which vary by generation.
765 struct iris_genx_state
{
766 struct iris_vertex_buffer_state vertex_buffers
[33];
768 /** The number of bound vertex buffers. */
769 uint64_t bound_vertex_buffers
;
771 struct iris_depth_buffer_state depth_buffer
;
773 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
774 uint32_t streamout
[4 * GENX(3DSTATE_STREAMOUT_length
)];
778 * The pipe->set_blend_color() driver hook.
780 * This corresponds to our COLOR_CALC_STATE.
783 iris_set_blend_color(struct pipe_context
*ctx
,
784 const struct pipe_blend_color
*state
)
786 struct iris_context
*ice
= (struct iris_context
*) ctx
;
788 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
789 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
790 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
794 * Gallium CSO for blend state (see pipe_blend_state).
796 struct iris_blend_state
{
797 /** Partial 3DSTATE_PS_BLEND */
798 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
800 /** Partial BLEND_STATE */
801 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
802 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
804 bool alpha_to_coverage
; /* for shader key */
807 static enum pipe_blendfactor
808 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
811 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
812 return PIPE_BLENDFACTOR_ONE
;
814 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
815 return PIPE_BLENDFACTOR_ZERO
;
822 * The pipe->create_blend_state() driver hook.
824 * Translates a pipe_blend_state into iris_blend_state.
827 iris_create_blend_state(struct pipe_context
*ctx
,
828 const struct pipe_blend_state
*state
)
830 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
831 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
833 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
835 bool indep_alpha_blend
= false;
837 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
838 const struct pipe_rt_blend_state
*rt
=
839 &state
->rt
[state
->independent_blend_enable
? i
: 0];
841 enum pipe_blendfactor src_rgb
=
842 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
843 enum pipe_blendfactor src_alpha
=
844 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
845 enum pipe_blendfactor dst_rgb
=
846 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
847 enum pipe_blendfactor dst_alpha
=
848 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
850 if (rt
->rgb_func
!= rt
->alpha_func
||
851 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
852 indep_alpha_blend
= true;
854 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
855 be
.LogicOpEnable
= state
->logicop_enable
;
856 be
.LogicOpFunction
= state
->logicop_func
;
858 be
.PreBlendSourceOnlyClampEnable
= false;
859 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
860 be
.PreBlendColorClampEnable
= true;
861 be
.PostBlendColorClampEnable
= true;
863 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
865 be
.ColorBlendFunction
= rt
->rgb_func
;
866 be
.AlphaBlendFunction
= rt
->alpha_func
;
867 be
.SourceBlendFactor
= src_rgb
;
868 be
.SourceAlphaBlendFactor
= src_alpha
;
869 be
.DestinationBlendFactor
= dst_rgb
;
870 be
.DestinationAlphaBlendFactor
= dst_alpha
;
872 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
873 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
874 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
875 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
877 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
880 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
881 /* pb.HasWriteableRT is filled in at draw time. */
882 /* pb.AlphaTestEnable is filled in at draw time. */
883 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
884 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
886 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
888 pb
.SourceBlendFactor
=
889 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
890 pb
.SourceAlphaBlendFactor
=
891 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
892 pb
.DestinationBlendFactor
=
893 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
894 pb
.DestinationAlphaBlendFactor
=
895 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
898 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
899 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
900 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
901 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
902 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
903 bs
.ColorDitherEnable
= state
->dither
;
904 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
912 * The pipe->bind_blend_state() driver hook.
914 * Bind a blending CSO and flag related dirty bits.
917 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
919 struct iris_context
*ice
= (struct iris_context
*) ctx
;
920 ice
->state
.cso_blend
= state
;
921 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
922 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
923 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
927 * Gallium CSO for depth, stencil, and alpha testing state.
929 struct iris_depth_stencil_alpha_state
{
930 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
931 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
933 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
934 struct pipe_alpha_state alpha
;
936 /** Outbound to resolve and cache set tracking. */
937 bool depth_writes_enabled
;
938 bool stencil_writes_enabled
;
942 * The pipe->create_depth_stencil_alpha_state() driver hook.
944 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
945 * testing state since we need pieces of it in a variety of places.
948 iris_create_zsa_state(struct pipe_context
*ctx
,
949 const struct pipe_depth_stencil_alpha_state
*state
)
951 struct iris_depth_stencil_alpha_state
*cso
=
952 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
954 bool two_sided_stencil
= state
->stencil
[1].enabled
;
956 cso
->alpha
= state
->alpha
;
957 cso
->depth_writes_enabled
= state
->depth
.writemask
;
958 cso
->stencil_writes_enabled
=
959 state
->stencil
[0].writemask
!= 0 ||
960 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 1);
962 /* The state tracker needs to optimize away EQUAL writes for us. */
963 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
965 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
966 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
967 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
968 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
969 wmds
.StencilTestFunction
=
970 translate_compare_func(state
->stencil
[0].func
);
971 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
972 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
973 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
974 wmds
.BackfaceStencilTestFunction
=
975 translate_compare_func(state
->stencil
[1].func
);
976 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
977 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
978 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
979 wmds
.StencilBufferWriteEnable
=
980 state
->stencil
[0].writemask
!= 0 ||
981 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
982 wmds
.DepthTestEnable
= state
->depth
.enabled
;
983 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
984 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
985 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
986 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
987 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
988 /* wmds.[Backface]StencilReferenceValue are merged later */
995 * The pipe->bind_depth_stencil_alpha_state() driver hook.
997 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1000 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1002 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1003 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1004 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1007 if (cso_changed(alpha
.ref_value
))
1008 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1010 if (cso_changed(alpha
.enabled
))
1011 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1013 if (cso_changed(alpha
.func
))
1014 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1016 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1017 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1020 ice
->state
.cso_zsa
= new_cso
;
1021 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1022 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1023 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1027 * Gallium CSO for rasterizer state.
1029 struct iris_rasterizer_state
{
1030 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1031 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1032 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1033 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1034 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1036 uint8_t num_clip_plane_consts
;
1037 bool clip_halfz
; /* for CC_VIEWPORT */
1038 bool depth_clip_near
; /* for CC_VIEWPORT */
1039 bool depth_clip_far
; /* for CC_VIEWPORT */
1040 bool flatshade
; /* for shader state */
1041 bool flatshade_first
; /* for stream output */
1042 bool clamp_fragment_color
; /* for shader state */
1043 bool light_twoside
; /* for shader state */
1044 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1045 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1046 bool line_stipple_enable
;
1047 bool poly_stipple_enable
;
1049 bool force_persample_interp
;
1050 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1051 uint16_t sprite_coord_enable
;
1055 get_line_width(const struct pipe_rasterizer_state
*state
)
1057 float line_width
= state
->line_width
;
1059 /* From the OpenGL 4.4 spec:
1061 * "The actual width of non-antialiased lines is determined by rounding
1062 * the supplied width to the nearest integer, then clamping it to the
1063 * implementation-dependent maximum non-antialiased line width."
1065 if (!state
->multisample
&& !state
->line_smooth
)
1066 line_width
= roundf(state
->line_width
);
1068 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1069 /* For 1 pixel line thickness or less, the general anti-aliasing
1070 * algorithm gives up, and a garbage line is generated. Setting a
1071 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1072 * (one-pixel-wide), non-antialiased lines.
1074 * Lines rendered with zero Line Width are rasterized using the
1075 * "Grid Intersection Quantization" rules as specified by the
1076 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1085 * The pipe->create_rasterizer_state() driver hook.
1088 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1089 const struct pipe_rasterizer_state
*state
)
1091 struct iris_rasterizer_state
*cso
=
1092 malloc(sizeof(struct iris_rasterizer_state
));
1095 point_quad_rasterization
-> SBE
?
1102 offset_units_unscaled
- cap
not exposed
1106 // XXX: it may make more sense just to store the pipe_rasterizer_state,
1107 // we're copying a lot of booleans here. But we don't need all of them...
1109 cso
->multisample
= state
->multisample
;
1110 cso
->force_persample_interp
= state
->force_persample_interp
;
1111 cso
->clip_halfz
= state
->clip_halfz
;
1112 cso
->depth_clip_near
= state
->depth_clip_near
;
1113 cso
->depth_clip_far
= state
->depth_clip_far
;
1114 cso
->flatshade
= state
->flatshade
;
1115 cso
->flatshade_first
= state
->flatshade_first
;
1116 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1117 cso
->light_twoside
= state
->light_twoside
;
1118 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1119 cso
->half_pixel_center
= state
->half_pixel_center
;
1120 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1121 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1122 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1123 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1125 if (state
->clip_plane_enable
!= 0)
1126 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1128 cso
->num_clip_plane_consts
= 0;
1130 float line_width
= get_line_width(state
);
1132 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1133 sf
.StatisticsEnable
= true;
1134 sf
.ViewportTransformEnable
= true;
1135 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1136 sf
.LineEndCapAntialiasingRegionWidth
=
1137 state
->line_smooth
? _10pixels
: _05pixels
;
1138 sf
.LastPixelEnable
= state
->line_last_pixel
;
1139 sf
.LineWidth
= line_width
;
1140 sf
.SmoothPointEnable
= state
->point_smooth
|| state
->multisample
;
1141 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1142 sf
.PointWidth
= state
->point_size
;
1144 if (state
->flatshade_first
) {
1145 sf
.TriangleFanProvokingVertexSelect
= 1;
1147 sf
.TriangleStripListProvokingVertexSelect
= 2;
1148 sf
.TriangleFanProvokingVertexSelect
= 2;
1149 sf
.LineStripListProvokingVertexSelect
= 1;
1153 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1154 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1155 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1156 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1157 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1158 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1159 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1160 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1161 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1162 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1163 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1164 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1165 rr
.SmoothPointEnable
= state
->point_smooth
|| state
->multisample
;
1166 rr
.AntialiasingEnable
= state
->line_smooth
;
1167 rr
.ScissorRectangleEnable
= state
->scissor
;
1168 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1169 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1170 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
1173 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1174 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1175 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1177 cl
.EarlyCullEnable
= true;
1178 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1179 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1180 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1181 cl
.GuardbandClipTestEnable
= true;
1182 cl
.ClipEnable
= true;
1183 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
1184 cl
.MinimumPointWidth
= 0.125;
1185 cl
.MaximumPointWidth
= 255.875;
1187 if (state
->flatshade_first
) {
1188 cl
.TriangleFanProvokingVertexSelect
= 1;
1190 cl
.TriangleStripListProvokingVertexSelect
= 2;
1191 cl
.TriangleFanProvokingVertexSelect
= 2;
1192 cl
.LineStripListProvokingVertexSelect
= 1;
1196 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1197 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1198 * filled in at draw time from the FS program.
1200 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1201 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1202 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1203 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1204 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1207 /* Remap from 0..255 back to 1..256 */
1208 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1210 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1211 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1212 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1213 line
.LineStippleRepeatCount
= line_stipple_factor
;
1220 * The pipe->bind_rasterizer_state() driver hook.
1222 * Bind a rasterizer CSO and flag related dirty bits.
1225 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1227 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1228 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1229 struct iris_rasterizer_state
*new_cso
= state
;
1232 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1233 if (cso_changed_memcmp(line_stipple
))
1234 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1236 if (cso_changed(half_pixel_center
))
1237 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1239 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1240 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1242 if (cso_changed(rasterizer_discard
))
1243 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1245 if (cso_changed(flatshade_first
))
1246 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1248 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1249 cso_changed(clip_halfz
))
1250 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1252 if (cso_changed(sprite_coord_enable
) ||
1253 cso_changed(sprite_coord_mode
) ||
1254 cso_changed(light_twoside
))
1255 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1258 ice
->state
.cso_rast
= new_cso
;
1259 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1260 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1261 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1265 * Return true if the given wrap mode requires the border color to exist.
1267 * (We can skip uploading it if the sampler isn't going to use it.)
1270 wrap_mode_needs_border_color(unsigned wrap_mode
)
1272 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1276 * Gallium CSO for sampler state.
1278 struct iris_sampler_state
{
1279 union pipe_color_union border_color
;
1280 bool needs_border_color
;
1282 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1286 * The pipe->create_sampler_state() driver hook.
1288 * We fill out SAMPLER_STATE (except for the border color pointer), and
1289 * store that on the CPU. It doesn't make sense to upload it to a GPU
1290 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1291 * all bound sampler states to be in contiguous memor.
1294 iris_create_sampler_state(struct pipe_context
*ctx
,
1295 const struct pipe_sampler_state
*state
)
1297 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1302 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1303 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1305 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1306 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1307 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1309 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1311 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1312 wrap_mode_needs_border_color(wrap_t
) ||
1313 wrap_mode_needs_border_color(wrap_r
);
1315 float min_lod
= state
->min_lod
;
1316 unsigned mag_img_filter
= state
->mag_img_filter
;
1318 // XXX: explain this code ported from ilo...I don't get it at all...
1319 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1320 state
->min_lod
> 0.0f
) {
1322 mag_img_filter
= state
->min_img_filter
;
1325 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1326 samp
.TCXAddressControlMode
= wrap_s
;
1327 samp
.TCYAddressControlMode
= wrap_t
;
1328 samp
.TCZAddressControlMode
= wrap_r
;
1329 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1330 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1331 samp
.MinModeFilter
= state
->min_img_filter
;
1332 samp
.MagModeFilter
= mag_img_filter
;
1333 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1334 samp
.MaximumAnisotropy
= RATIO21
;
1336 if (state
->max_anisotropy
>= 2) {
1337 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1338 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1339 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1342 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1343 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1345 samp
.MaximumAnisotropy
=
1346 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1349 /* Set address rounding bits if not using nearest filtering. */
1350 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1351 samp
.UAddressMinFilterRoundingEnable
= true;
1352 samp
.VAddressMinFilterRoundingEnable
= true;
1353 samp
.RAddressMinFilterRoundingEnable
= true;
1356 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1357 samp
.UAddressMagFilterRoundingEnable
= true;
1358 samp
.VAddressMagFilterRoundingEnable
= true;
1359 samp
.RAddressMagFilterRoundingEnable
= true;
1362 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1363 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1365 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1367 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1368 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1369 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1370 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1372 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1379 * The pipe->bind_sampler_states() driver hook.
1381 * Now that we know all the sampler states, we upload them all into a
1382 * contiguous area of GPU memory, for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1383 * We also fill out the border color state pointers at this point.
1385 * We could defer this work to draw time, but we assume that binding
1386 * will be less frequent than drawing.
1388 // XXX: this may be a bad idea, need to make sure that st/mesa calls us
1389 // XXX: with the complete set of shaders. If it makes multiple calls to
1390 // XXX: things one at a time, we could waste a lot of time assembling things.
1391 // XXX: it doesn't even BUY us anything to do it here, because we only flag
1392 // XXX: IRIS_DIRTY_SAMPLER_STATE when this is called...
1394 iris_bind_sampler_states(struct pipe_context
*ctx
,
1395 enum pipe_shader_type p_stage
,
1396 unsigned start
, unsigned count
,
1399 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1400 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1401 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1403 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1405 for (int i
= 0; i
< count
; i
++) {
1406 shs
->samplers
[start
+ i
] = states
[i
];
1409 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1410 * in the dynamic state memory zone, so we can point to it via the
1411 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1414 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
,
1415 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
1419 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1420 shs
->sampler_table
.offset
+=
1421 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1423 /* Make sure all land in the same BO */
1424 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1426 for (int i
= 0; i
< count
; i
++) {
1427 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1430 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1431 } else if (!state
->needs_border_color
) {
1432 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1434 ice
->state
.need_border_colors
= true;
1436 /* Stream out the border color and merge the pointer. */
1438 iris_upload_border_color(ice
, &state
->border_color
);
1440 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1441 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1442 dyns
.BorderColorPointer
= offset
;
1445 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1446 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1449 map
+= GENX(SAMPLER_STATE_length
);
1452 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1455 static enum isl_channel_select
1456 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1459 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1460 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1461 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1462 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1463 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1464 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1465 default: unreachable("invalid swizzle");
1470 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1473 enum isl_format format
,
1477 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1478 const unsigned cpp
= fmtl
->bpb
/ 8;
1480 /* The ARB_texture_buffer_specification says:
1482 * "The number of texels in the buffer texture's texel array is given by
1484 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1486 * where <buffer_size> is the size of the buffer object, in basic
1487 * machine units and <components> and <base_type> are the element count
1488 * and base data type for elements, as specified in Table X.1. The
1489 * number of texels in the texel array is then clamped to the
1490 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1492 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1493 * so that when ISL divides by stride to obtain the number of texels, that
1494 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1496 unsigned final_size
=
1497 MIN3(size
, bo
->size
- offset
, IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1499 isl_buffer_fill_state(isl_dev
, map
,
1500 .address
= bo
->gtt_offset
+ offset
,
1501 .size_B
= final_size
,
1508 * The pipe->create_sampler_view() driver hook.
1510 static struct pipe_sampler_view
*
1511 iris_create_sampler_view(struct pipe_context
*ctx
,
1512 struct pipe_resource
*tex
,
1513 const struct pipe_sampler_view
*tmpl
)
1515 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1516 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1517 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1518 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1523 /* initialize base object */
1525 isv
->base
.context
= ctx
;
1526 isv
->base
.texture
= NULL
;
1527 pipe_reference_init(&isv
->base
.reference
, 1);
1528 pipe_resource_reference(&isv
->base
.texture
, tex
);
1530 void *map
= upload_state(ice
->state
.surface_uploader
, &isv
->surface_state
,
1531 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1535 struct iris_bo
*state_bo
= iris_resource_bo(isv
->surface_state
.res
);
1536 isv
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1538 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1539 struct iris_resource
*zres
, *sres
;
1540 const struct util_format_description
*desc
=
1541 util_format_description(tmpl
->format
);
1543 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1545 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1548 isv
->res
= (struct iris_resource
*) tex
;
1550 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1552 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1553 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1554 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1556 const struct iris_format_info fmt
=
1557 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1559 isv
->view
= (struct isl_view
) {
1561 .swizzle
= (struct isl_swizzle
) {
1562 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1563 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1564 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1565 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1570 /* Fill out SURFACE_STATE for this view. */
1571 if (tmpl
->target
!= PIPE_BUFFER
) {
1572 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1573 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1574 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1575 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1576 isv
->view
.array_len
=
1577 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1579 isl_surf_fill_state(&screen
->isl_dev
, map
,
1580 .surf
= &isv
->res
->surf
, .view
= &isv
->view
,
1582 .address
= isv
->res
->bo
->gtt_offset
);
1584 // .clear_color = clear_color,
1586 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
->bo
, map
,
1587 isv
->view
.format
, tmpl
->u
.buf
.offset
,
1595 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1596 struct pipe_sampler_view
*state
)
1598 struct iris_sampler_view
*isv
= (void *) state
;
1599 pipe_resource_reference(&state
->texture
, NULL
);
1600 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1605 * The pipe->create_surface() driver hook.
1607 * In Gallium nomenclature, "surfaces" are a view of a resource that
1608 * can be bound as a render target or depth/stencil buffer.
1610 static struct pipe_surface
*
1611 iris_create_surface(struct pipe_context
*ctx
,
1612 struct pipe_resource
*tex
,
1613 const struct pipe_surface
*tmpl
)
1615 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1616 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1617 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1618 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1619 struct pipe_surface
*psurf
= &surf
->base
;
1620 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1625 pipe_reference_init(&psurf
->reference
, 1);
1626 pipe_resource_reference(&psurf
->texture
, tex
);
1627 psurf
->context
= ctx
;
1628 psurf
->format
= tmpl
->format
;
1629 psurf
->width
= tex
->width0
;
1630 psurf
->height
= tex
->height0
;
1631 psurf
->texture
= tex
;
1632 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1633 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1634 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1636 isl_surf_usage_flags_t usage
= 0;
1638 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1639 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1640 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1642 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1644 const struct iris_format_info fmt
=
1645 iris_format_for_usage(devinfo
, psurf
->format
, usage
);
1647 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1648 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1649 /* Framebuffer validation will reject this invalid case, but it
1650 * hasn't had the opportunity yet. In the meantime, we need to
1651 * avoid hitting ISL asserts about unsupported formats below.
1657 surf
->view
= (struct isl_view
) {
1659 .base_level
= tmpl
->u
.tex
.level
,
1661 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1662 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1663 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1667 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1668 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1669 ISL_SURF_USAGE_STENCIL_BIT
))
1673 void *map
= upload_state(ice
->state
.surface_uploader
, &surf
->surface_state
,
1674 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1678 struct iris_bo
*state_bo
= iris_resource_bo(surf
->surface_state
.res
);
1679 surf
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1681 isl_surf_fill_state(&screen
->isl_dev
, map
,
1682 .surf
= &res
->surf
, .view
= &surf
->view
,
1684 .address
= res
->bo
->gtt_offset
);
1686 // .clear_color = clear_color,
1692 * The pipe->set_shader_images() driver hook.
1695 iris_set_shader_images(struct pipe_context
*ctx
,
1696 enum pipe_shader_type p_stage
,
1697 unsigned start_slot
, unsigned count
,
1698 const struct pipe_image_view
*p_images
)
1700 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1701 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1702 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1703 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1704 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1706 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
1708 for (unsigned i
= 0; i
< count
; i
++) {
1709 if (p_images
&& p_images
[i
].resource
) {
1710 const struct pipe_image_view
*img
= &p_images
[i
];
1711 struct iris_resource
*res
= (void *) img
->resource
;
1712 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, &res
->base
);
1714 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
1716 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
1718 // XXX: these are not retained forever, use a separate uploader?
1720 upload_state(ice
->state
.surface_uploader
,
1721 &shs
->image
[start_slot
+ i
].surface_state
,
1722 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1723 if (!unlikely(map
)) {
1724 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1728 struct iris_bo
*surf_state_bo
=
1729 iris_resource_bo(shs
->image
[start_slot
+ i
].surface_state
.res
);
1730 shs
->image
[start_slot
+ i
].surface_state
.offset
+=
1731 iris_bo_offset_from_base_address(surf_state_bo
);
1733 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1734 enum isl_format isl_format
=
1735 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
1737 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
)
1738 isl_format
= isl_lower_storage_image_format(devinfo
, isl_format
);
1740 shs
->image
[start_slot
+ i
].access
= img
->shader_access
;
1742 if (res
->base
.target
!= PIPE_BUFFER
) {
1743 struct isl_view view
= {
1744 .format
= isl_format
,
1745 .base_level
= img
->u
.tex
.level
,
1747 .base_array_layer
= img
->u
.tex
.first_layer
,
1748 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
1749 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1753 isl_surf_fill_state(&screen
->isl_dev
, map
,
1754 .surf
= &res
->surf
, .view
= &view
,
1756 .address
= res
->bo
->gtt_offset
);
1758 // .clear_color = clear_color,
1760 fill_buffer_surface_state(&screen
->isl_dev
, res
->bo
, map
,
1761 isl_format
, img
->u
.buf
.offset
,
1765 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1766 pipe_resource_reference(&shs
->image
[start_slot
+ i
].surface_state
.res
,
1771 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1776 * The pipe->set_sampler_views() driver hook.
1779 iris_set_sampler_views(struct pipe_context
*ctx
,
1780 enum pipe_shader_type p_stage
,
1781 unsigned start
, unsigned count
,
1782 struct pipe_sampler_view
**views
)
1784 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1785 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1786 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1788 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
1790 for (unsigned i
= 0; i
< count
; i
++) {
1791 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1792 &shs
->textures
[start
+ i
], views
[i
]);
1793 struct iris_sampler_view
*view
= (void *) views
[i
];
1795 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
1796 shs
->bound_sampler_views
|= 1 << (start
+ i
);
1800 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
1804 * The pipe->set_tess_state() driver hook.
1807 iris_set_tess_state(struct pipe_context
*ctx
,
1808 const float default_outer_level
[4],
1809 const float default_inner_level
[2])
1811 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1813 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
1814 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
1816 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
1820 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1822 struct iris_surface
*surf
= (void *) p_surf
;
1823 pipe_resource_reference(&p_surf
->texture
, NULL
);
1824 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
1829 iris_set_clip_state(struct pipe_context
*ctx
,
1830 const struct pipe_clip_state
*state
)
1832 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1833 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
1835 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
1837 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
;
1838 shs
->cbuf0_needs_upload
= true;
1842 * The pipe->set_polygon_stipple() driver hook.
1845 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1846 const struct pipe_poly_stipple
*state
)
1848 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1849 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1850 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1854 * The pipe->set_sample_mask() driver hook.
1857 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1859 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1861 /* We only support 16x MSAA, so we have 16 bits of sample maks.
1862 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
1864 ice
->state
.sample_mask
= sample_mask
& 0xffff;
1865 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1869 * The pipe->set_scissor_states() driver hook.
1871 * This corresponds to our SCISSOR_RECT state structures. It's an
1872 * exact match, so we just store them, and memcpy them out later.
1875 iris_set_scissor_states(struct pipe_context
*ctx
,
1876 unsigned start_slot
,
1877 unsigned num_scissors
,
1878 const struct pipe_scissor_state
*rects
)
1880 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1882 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1883 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
1884 /* If the scissor was out of bounds and got clamped to 0 width/height
1885 * at the bounds, the subtraction of 1 from maximums could produce a
1886 * negative number and thus not clip anything. Instead, just provide
1887 * a min > max scissor inside the bounds, which produces the expected
1890 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
1891 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
1894 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
1895 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
1896 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
1901 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1905 * The pipe->set_stencil_ref() driver hook.
1907 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
1910 iris_set_stencil_ref(struct pipe_context
*ctx
,
1911 const struct pipe_stencil_ref
*state
)
1913 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1914 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1915 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1919 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1921 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1925 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1926 float m00
, float m11
, float m30
, float m31
,
1927 float *xmin
, float *xmax
,
1928 float *ymin
, float *ymax
)
1930 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1931 * Strips and Fans documentation:
1933 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1934 * fixed-point "guardband" range supported by the rasterization hardware"
1938 * "In almost all circumstances, if an object’s vertices are actually
1939 * modified by this clamping (i.e., had X or Y coordinates outside of
1940 * the guardband extent the rendered object will not match the intended
1941 * result. Therefore software should take steps to ensure that this does
1942 * not happen - e.g., by clipping objects such that they do not exceed
1943 * these limits after the Drawing Rectangle is applied."
1945 * I believe the fundamental restriction is that the rasterizer (in
1946 * the SF/WM stages) have a limit on the number of pixels that can be
1947 * rasterized. We need to ensure any coordinates beyond the rasterizer
1948 * limit are handled by the clipper. So effectively that limit becomes
1949 * the clipper's guardband size.
1951 * It goes on to say:
1953 * "In addition, in order to be correctly rendered, objects must have a
1954 * screenspace bounding box not exceeding 8K in the X or Y direction.
1955 * This additional restriction must also be comprehended by software,
1956 * i.e., enforced by use of clipping."
1958 * This makes no sense. Gen7+ hardware supports 16K render targets,
1959 * and you definitely need to be able to draw polygons that fill the
1960 * surface. Our assumption is that the rasterizer was limited to 8K
1961 * on Sandybridge, which only supports 8K surfaces, and it was actually
1962 * increased to 16K on Ivybridge and later.
1964 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1966 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1968 if (m00
!= 0 && m11
!= 0) {
1969 /* First, we compute the screen-space render area */
1970 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1971 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1972 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1973 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1975 /* We want the guardband to be centered on that */
1976 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1977 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1978 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1979 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1981 /* Now we need it in native device coordinates */
1982 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1983 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1984 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1985 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1987 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1988 * flipped upside-down. X should be fine though.
1990 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1991 *xmin
= ndc_gb_xmin
;
1992 *xmax
= ndc_gb_xmax
;
1993 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1994 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1996 /* The viewport scales to 0, so nothing will be rendered. */
2005 * The pipe->set_viewport_states() driver hook.
2007 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2008 * the guardband yet, as we need the framebuffer dimensions, but we can
2009 * at least fill out the rest.
2012 iris_set_viewport_states(struct pipe_context
*ctx
,
2013 unsigned start_slot
,
2015 const struct pipe_viewport_state
*states
)
2017 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2019 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2021 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2023 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2024 !ice
->state
.cso_rast
->depth_clip_far
))
2025 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2029 * The pipe->set_framebuffer_state() driver hook.
2031 * Sets the current draw FBO, including color render targets, depth,
2032 * and stencil buffers.
2035 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2036 const struct pipe_framebuffer_state
*state
)
2038 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2039 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2040 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2041 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2042 struct iris_resource
*zres
;
2043 struct iris_resource
*stencil_res
;
2045 unsigned samples
= util_framebuffer_get_num_samples(state
);
2047 if (cso
->samples
!= samples
) {
2048 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2051 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2052 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2055 if ((cso
->layers
== 0) != (state
->layers
== 0)) {
2056 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2059 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2060 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2063 util_copy_framebuffer_state(cso
, state
);
2064 cso
->samples
= samples
;
2066 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2068 struct isl_view view
= {
2071 .base_array_layer
= 0,
2073 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2076 struct isl_depth_stencil_hiz_emit_info info
= {
2082 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2085 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2086 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2088 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2091 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2093 info
.depth_surf
= &zres
->surf
;
2094 info
.depth_address
= zres
->bo
->gtt_offset
;
2095 info
.hiz_usage
= ISL_AUX_USAGE_NONE
;
2097 view
.format
= zres
->surf
.format
;
2101 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2102 info
.stencil_surf
= &stencil_res
->surf
;
2103 info
.stencil_address
= stencil_res
->bo
->gtt_offset
;
2105 view
.format
= stencil_res
->surf
.format
;
2109 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2111 /* Make a null surface for unbound buffers */
2112 void *null_surf_map
=
2113 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2114 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2115 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2116 isl_extent3d(MAX2(cso
->width
, 1),
2117 MAX2(cso
->height
, 1),
2118 cso
->layers
? cso
->layers
: 1));
2119 ice
->state
.null_fb
.offset
+=
2120 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2122 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2124 /* Render target change */
2125 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2127 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2130 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2131 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2133 /* The PIPE_CONTROL command description says:
2135 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2136 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2137 * Target Cache Flush by enabling this bit. When render target flush
2138 * is set due to new association of BTI, PS Scoreboard Stall bit must
2139 * be set in this packet."
2141 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2142 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2143 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2144 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2149 upload_ubo_surf_state(struct iris_context
*ice
,
2150 struct iris_const_buffer
*cbuf
,
2151 unsigned buffer_size
)
2153 struct pipe_context
*ctx
= &ice
->ctx
;
2154 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
2156 // XXX: these are not retained forever, use a separate uploader?
2158 upload_state(ice
->state
.surface_uploader
, &cbuf
->surface_state
,
2159 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2160 if (!unlikely(map
)) {
2161 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2165 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2166 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state
.res
);
2167 cbuf
->surface_state
.offset
+= iris_bo_offset_from_base_address(surf_bo
);
2169 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2170 .address
= res
->bo
->gtt_offset
+ cbuf
->data
.offset
,
2171 .size_B
= MIN2(buffer_size
,
2172 res
->bo
->size
- cbuf
->data
.offset
),
2173 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
2179 * The pipe->set_constant_buffer() driver hook.
2181 * This uploads any constant data in user buffers, and references
2182 * any UBO resources containing constant data.
2185 iris_set_constant_buffer(struct pipe_context
*ctx
,
2186 enum pipe_shader_type p_stage
, unsigned index
,
2187 const struct pipe_constant_buffer
*input
)
2189 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2190 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2191 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2192 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
2194 if (input
&& input
->buffer
) {
2197 pipe_resource_reference(&cbuf
->data
.res
, input
->buffer
);
2198 cbuf
->data
.offset
= input
->buffer_offset
;
2200 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2201 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2203 upload_ubo_surf_state(ice
, cbuf
, input
->buffer_size
);
2205 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2206 pipe_resource_reference(&cbuf
->surface_state
.res
, NULL
);
2211 memcpy(&shs
->cbuf0
, input
, sizeof(shs
->cbuf0
));
2213 memset(&shs
->cbuf0
, 0, sizeof(shs
->cbuf0
));
2215 shs
->cbuf0_needs_upload
= true;
2218 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2219 // XXX: maybe not necessary all the time...?
2220 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2221 // XXX: pull model we may need actual new bindings...
2222 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2226 upload_uniforms(struct iris_context
*ice
,
2227 gl_shader_stage stage
)
2229 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2230 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
2231 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2233 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t) +
2234 shs
->cbuf0
.buffer_size
;
2236 if (upload_size
== 0)
2240 upload_state(ice
->ctx
.const_uploader
, &cbuf
->data
, upload_size
, 64);
2242 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2243 uint32_t sysval
= shader
->system_values
[i
];
2246 if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2247 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2248 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2249 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2250 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
2251 if (stage
== MESA_SHADER_TESS_CTRL
) {
2252 value
= ice
->state
.vertices_per_patch
;
2254 assert(stage
== MESA_SHADER_TESS_EVAL
);
2255 const struct shader_info
*tcs_info
=
2256 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
2259 value
= tcs_info
->tess
.tcs_vertices_out
;
2262 assert(!"unhandled system value");
2268 if (shs
->cbuf0
.user_buffer
) {
2269 memcpy(map
, shs
->cbuf0
.user_buffer
, shs
->cbuf0
.buffer_size
);
2272 upload_ubo_surf_state(ice
, cbuf
, upload_size
);
2276 * The pipe->set_shader_buffers() driver hook.
2278 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2279 * SURFACE_STATE here, as the buffer offset may change each time.
2282 iris_set_shader_buffers(struct pipe_context
*ctx
,
2283 enum pipe_shader_type p_stage
,
2284 unsigned start_slot
, unsigned count
,
2285 const struct pipe_shader_buffer
*buffers
)
2287 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2288 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2289 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2290 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2292 for (unsigned i
= 0; i
< count
; i
++) {
2293 if (buffers
&& buffers
[i
].buffer
) {
2294 const struct pipe_shader_buffer
*buffer
= &buffers
[i
];
2295 struct iris_resource
*res
= (void *) buffer
->buffer
;
2296 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], &res
->base
);
2298 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2300 // XXX: these are not retained forever, use a separate uploader?
2302 upload_state(ice
->state
.surface_uploader
,
2303 &shs
->ssbo_surface_state
[start_slot
+ i
],
2304 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2305 if (!unlikely(map
)) {
2306 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2310 struct iris_bo
*surf_state_bo
=
2311 iris_resource_bo(shs
->ssbo_surface_state
[start_slot
+ i
].res
);
2312 shs
->ssbo_surface_state
[start_slot
+ i
].offset
+=
2313 iris_bo_offset_from_base_address(surf_state_bo
);
2315 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2317 res
->bo
->gtt_offset
+ buffer
->buffer_offset
,
2319 MIN2(buffer
->buffer_size
,
2320 res
->bo
->size
- buffer
->buffer_offset
),
2321 .format
= ISL_FORMAT_RAW
,
2325 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2326 pipe_resource_reference(&shs
->ssbo_surface_state
[start_slot
+ i
].res
,
2331 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2335 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2341 * The pipe->set_vertex_buffers() driver hook.
2343 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2346 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2347 unsigned start_slot
, unsigned count
,
2348 const struct pipe_vertex_buffer
*buffers
)
2350 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2351 struct iris_genx_state
*genx
= ice
->state
.genx
;
2353 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
2355 for (unsigned i
= 0; i
< count
; i
++) {
2356 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
2357 struct iris_vertex_buffer_state
*state
=
2358 &genx
->vertex_buffers
[start_slot
+ i
];
2361 pipe_resource_reference(&state
->resource
, NULL
);
2365 assert(!buffer
->is_user_buffer
);
2367 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
2369 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
2370 struct iris_resource
*res
= (void *) state
->resource
;
2373 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2375 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
2376 vb
.VertexBufferIndex
= start_slot
+ i
;
2378 vb
.AddressModifyEnable
= true;
2379 vb
.BufferPitch
= buffer
->stride
;
2381 vb
.BufferSize
= res
->bo
->size
;
2382 vb
.BufferStartingAddress
=
2383 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffer
->buffer_offset
);
2385 vb
.NullVertexBuffer
= true;
2390 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2394 * Gallium CSO for vertex elements.
2396 struct iris_vertex_element_state
{
2397 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2398 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2403 * The pipe->create_vertex_elements() driver hook.
2405 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2406 * and 3DSTATE_VF_INSTANCING commands. SGVs are handled at draw time.
2409 iris_create_vertex_elements(struct pipe_context
*ctx
,
2411 const struct pipe_vertex_element
*state
)
2413 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2414 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2415 struct iris_vertex_element_state
*cso
=
2416 malloc(sizeof(struct iris_vertex_element_state
));
2421 * - create edge flag one
2423 * - if those are necessary, use count + 1/2/3... OR in the length
2425 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2427 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2430 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2431 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2434 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2436 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2437 ve
.Component0Control
= VFCOMP_STORE_0
;
2438 ve
.Component1Control
= VFCOMP_STORE_0
;
2439 ve
.Component2Control
= VFCOMP_STORE_0
;
2440 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2443 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2447 for (int i
= 0; i
< count
; i
++) {
2448 const struct iris_format_info fmt
=
2449 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2450 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2451 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2453 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2454 case 0: comp
[0] = VFCOMP_STORE_0
;
2455 case 1: comp
[1] = VFCOMP_STORE_0
;
2456 case 2: comp
[2] = VFCOMP_STORE_0
;
2458 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2459 : VFCOMP_STORE_1_FP
;
2462 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2463 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2465 ve
.SourceElementOffset
= state
[i
].src_offset
;
2466 ve
.SourceElementFormat
= fmt
.fmt
;
2467 ve
.Component0Control
= comp
[0];
2468 ve
.Component1Control
= comp
[1];
2469 ve
.Component2Control
= comp
[2];
2470 ve
.Component3Control
= comp
[3];
2473 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2474 vi
.VertexElementIndex
= i
;
2475 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2476 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2479 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2480 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2487 * The pipe->bind_vertex_elements_state() driver hook.
2490 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2492 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2493 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2494 struct iris_vertex_element_state
*new_cso
= state
;
2496 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2497 * we need to re-emit it to ensure we're overriding the right one.
2499 if (new_cso
&& cso_changed(count
))
2500 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2502 ice
->state
.cso_vertex_elements
= state
;
2503 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2507 * The pipe->create_stream_output_target() driver hook.
2509 * "Target" here refers to a destination buffer. We translate this into
2510 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2511 * know which buffer this represents, or whether we ought to zero the
2512 * write-offsets, or append. Those are handled in the set() hook.
2514 static struct pipe_stream_output_target
*
2515 iris_create_stream_output_target(struct pipe_context
*ctx
,
2516 struct pipe_resource
*p_res
,
2517 unsigned buffer_offset
,
2518 unsigned buffer_size
)
2520 struct iris_resource
*res
= (void *) p_res
;
2521 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2525 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
2527 pipe_reference_init(&cso
->base
.reference
, 1);
2528 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
2529 cso
->base
.buffer_offset
= buffer_offset
;
2530 cso
->base
.buffer_size
= buffer_size
;
2531 cso
->base
.context
= ctx
;
2533 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
2539 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2540 struct pipe_stream_output_target
*state
)
2542 struct iris_stream_output_target
*cso
= (void *) state
;
2544 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2545 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2551 * The pipe->set_stream_output_targets() driver hook.
2553 * At this point, we know which targets are bound to a particular index,
2554 * and also whether we want to append or start over. We can finish the
2555 * 3DSTATE_SO_BUFFER packets we started earlier.
2558 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2559 unsigned num_targets
,
2560 struct pipe_stream_output_target
**targets
,
2561 const unsigned *offsets
)
2563 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2564 struct iris_genx_state
*genx
= ice
->state
.genx
;
2565 uint32_t *so_buffers
= genx
->so_buffers
;
2567 const bool active
= num_targets
> 0;
2568 if (ice
->state
.streamout_active
!= active
) {
2569 ice
->state
.streamout_active
= active
;
2570 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2572 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
2573 * it's a non-pipelined command. If we're switching streamout on, we
2574 * may have missed emitting it earlier, so do so now. (We're already
2575 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
2578 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
2581 for (int i
= 0; i
< 4; i
++) {
2582 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2583 i
< num_targets
? targets
[i
] : NULL
);
2586 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2590 for (unsigned i
= 0; i
< 4; i
++,
2591 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2593 if (i
>= num_targets
|| !targets
[i
]) {
2594 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
2595 sob
.SOBufferIndex
= i
;
2599 struct iris_stream_output_target
*tgt
= (void *) targets
[i
];
2600 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
2602 /* Note that offsets[i] will either be 0, causing us to zero
2603 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
2604 * "continue appending at the existing offset."
2606 assert(offsets
[i
] == 0 || offsets
[i
] == 0xFFFFFFFF);
2608 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
2609 sob
.SurfaceBaseAddress
=
2610 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
2611 sob
.SOBufferEnable
= true;
2612 sob
.StreamOffsetWriteEnable
= true;
2613 sob
.StreamOutputBufferOffsetAddressEnable
= true;
2614 sob
.MOCS
= MOCS_WB
; // XXX: MOCS
2616 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
2618 sob
.SOBufferIndex
= i
;
2619 sob
.StreamOffset
= offsets
[i
];
2620 sob
.StreamOutputBufferOffsetAddress
=
2621 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
2622 tgt
->offset
.offset
);
2626 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
2630 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
2631 * 3DSTATE_STREAMOUT packets.
2633 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
2634 * hardware to record. We can create it entirely based on the shader, with
2635 * no dynamic state dependencies.
2637 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
2638 * state-based settings. We capture the shader-related ones here, and merge
2639 * the rest in at draw time.
2642 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
2643 const struct brw_vue_map
*vue_map
)
2645 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2646 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2647 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2648 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2650 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2652 memset(so_decl
, 0, sizeof(so_decl
));
2654 /* Construct the list of SO_DECLs to be emitted. The formatting of the
2655 * command feels strange -- each dword pair contains a SO_DECL per stream.
2657 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
2658 const struct pipe_stream_output
*output
= &info
->output
[i
];
2659 const int buffer
= output
->output_buffer
;
2660 const int varying
= output
->register_index
;
2661 const unsigned stream_id
= output
->stream
;
2662 assert(stream_id
< MAX_VERTEX_STREAMS
);
2664 buffer_mask
[stream_id
] |= 1 << buffer
;
2666 assert(vue_map
->varying_to_slot
[varying
] >= 0);
2668 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
2669 * array. Instead, it simply increments DstOffset for the following
2670 * input by the number of components that should be skipped.
2672 * Our hardware is unusual in that it requires us to program SO_DECLs
2673 * for fake "hole" components, rather than simply taking the offset
2674 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
2675 * program as many size = 4 holes as we can, then a final hole to
2676 * accommodate the final 1, 2, or 3 remaining.
2678 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
2680 while (skip_components
> 0) {
2681 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2683 .OutputBufferSlot
= output
->output_buffer
,
2684 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
2686 skip_components
-= 4;
2689 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
2691 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2692 .OutputBufferSlot
= output
->output_buffer
,
2693 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
2695 ((1 << output
->num_components
) - 1) << output
->start_component
,
2698 if (decls
[stream_id
] > max_decls
)
2699 max_decls
= decls
[stream_id
];
2702 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
2703 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
2704 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
2706 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
2707 int urb_entry_read_offset
= 0;
2708 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
2709 urb_entry_read_offset
;
2711 /* We always read the whole vertex. This could be reduced at some
2712 * point by reading less and offsetting the register index in the
2715 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
2716 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
2717 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
2718 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
2719 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
2720 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
2721 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
2722 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
2724 /* Set buffer pitches; 0 means unbound. */
2725 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
2726 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
2727 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
2728 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
2731 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
2732 list
.DWordLength
= 3 + 2 * max_decls
- 2;
2733 list
.StreamtoBufferSelects0
= buffer_mask
[0];
2734 list
.StreamtoBufferSelects1
= buffer_mask
[1];
2735 list
.StreamtoBufferSelects2
= buffer_mask
[2];
2736 list
.StreamtoBufferSelects3
= buffer_mask
[3];
2737 list
.NumEntries0
= decls
[0];
2738 list
.NumEntries1
= decls
[1];
2739 list
.NumEntries2
= decls
[2];
2740 list
.NumEntries3
= decls
[3];
2743 for (int i
= 0; i
< max_decls
; i
++) {
2744 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
2745 entry
.Stream0Decl
= so_decl
[0][i
];
2746 entry
.Stream1Decl
= so_decl
[1][i
];
2747 entry
.Stream2Decl
= so_decl
[2][i
];
2748 entry
.Stream3Decl
= so_decl
[3][i
];
2756 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
2757 const struct brw_vue_map
*last_vue_map
,
2758 bool two_sided_color
,
2759 unsigned *out_offset
,
2760 unsigned *out_length
)
2762 /* The compiler computes the first URB slot without considering COL/BFC
2763 * swizzling (because it doesn't know whether it's enabled), so we need
2764 * to do that here too. This may result in a smaller offset, which
2767 const unsigned first_slot
=
2768 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
2770 /* This becomes the URB read offset (counted in pairs of slots). */
2771 assert(first_slot
% 2 == 0);
2772 *out_offset
= first_slot
/ 2;
2774 /* We need to adjust the inputs read to account for front/back color
2775 * swizzling, as it can make the URB length longer.
2777 for (int c
= 0; c
<= 1; c
++) {
2778 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
2779 /* If two sided color is enabled, the fragment shader's gl_Color
2780 * (COL0) input comes from either the gl_FrontColor (COL0) or
2781 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
2783 if (two_sided_color
)
2784 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2786 /* If front color isn't written, we opt to give them back color
2787 * instead of an undefined value. Switch from COL to BFC.
2789 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
2790 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
2791 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2796 /* Compute the minimum URB Read Length necessary for the FS inputs.
2798 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
2799 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
2801 * "This field should be set to the minimum length required to read the
2802 * maximum source attribute. The maximum source attribute is indicated
2803 * by the maximum value of the enabled Attribute # Source Attribute if
2804 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
2805 * enable is not set.
2806 * read_length = ceiling((max_source_attr + 1) / 2)
2808 * [errata] Corruption/Hang possible if length programmed larger than
2811 * Similar text exists for Ivy Bridge.
2813 * We find the last URB slot that's actually read by the FS.
2815 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
2816 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
2817 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
2820 /* The URB read length is the difference of the two, counted in pairs. */
2821 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
2825 iris_emit_sbe_swiz(struct iris_batch
*batch
,
2826 const struct iris_context
*ice
,
2827 unsigned urb_read_offset
,
2828 unsigned sprite_coord_enables
)
2830 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
2831 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2832 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2833 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
2834 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2836 /* XXX: this should be generated when putting programs in place */
2838 // XXX: raster->sprite_coord_enable
2840 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
2841 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
2842 if (input_index
< 0 || input_index
>= 16)
2845 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
2846 &attr_overrides
[input_index
];
2847 int slot
= vue_map
->varying_to_slot
[fs_attr
];
2849 /* Viewport and Layer are stored in the VUE header. We need to override
2850 * them to zero if earlier stages didn't write them, as GL requires that
2851 * they read back as zero when not explicitly set.
2854 case VARYING_SLOT_VIEWPORT
:
2855 case VARYING_SLOT_LAYER
:
2856 attr
->ComponentOverrideX
= true;
2857 attr
->ComponentOverrideW
= true;
2858 attr
->ConstantSource
= CONST_0000
;
2860 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
2861 attr
->ComponentOverrideY
= true;
2862 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
2863 attr
->ComponentOverrideZ
= true;
2866 case VARYING_SLOT_PRIMITIVE_ID
:
2867 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
2869 attr
->ComponentOverrideX
= true;
2870 attr
->ComponentOverrideY
= true;
2871 attr
->ComponentOverrideZ
= true;
2872 attr
->ComponentOverrideW
= true;
2873 attr
->ConstantSource
= PRIM_ID
;
2881 if (sprite_coord_enables
& (1 << input_index
))
2884 /* If there was only a back color written but not front, use back
2885 * as the color instead of undefined.
2887 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
2888 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
2889 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
2890 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
2892 /* Not written by the previous stage - undefined. */
2894 attr
->ComponentOverrideX
= true;
2895 attr
->ComponentOverrideY
= true;
2896 attr
->ComponentOverrideZ
= true;
2897 attr
->ComponentOverrideW
= true;
2898 attr
->ConstantSource
= CONST_0001_FLOAT
;
2902 /* Compute the location of the attribute relative to the read offset,
2903 * which is counted in 256-bit increments (two 128-bit VUE slots).
2905 const int source_attr
= slot
- 2 * urb_read_offset
;
2906 assert(source_attr
>= 0 && source_attr
<= 32);
2907 attr
->SourceAttribute
= source_attr
;
2909 /* If we are doing two-sided color, and the VUE slot following this one
2910 * represents a back-facing color, then we need to instruct the SF unit
2911 * to do back-facing swizzling.
2913 if (cso_rast
->light_twoside
&&
2914 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
2915 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
2916 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
2917 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
2918 attr
->SwizzleSelect
= INPUTATTR_FACING
;
2921 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
2922 for (int i
= 0; i
< 16; i
++)
2923 sbes
.Attribute
[i
] = attr_overrides
[i
];
2928 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
2929 const struct iris_rasterizer_state
*cso
)
2931 unsigned overrides
= 0;
2933 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
2934 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
2936 for (int i
= 0; i
< 8; i
++) {
2937 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
2938 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
2939 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
2946 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
2948 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2949 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2950 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2951 const struct shader_info
*fs_info
=
2952 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
2954 unsigned urb_read_offset
, urb_read_length
;
2955 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
2956 ice
->shaders
.last_vue_map
,
2957 cso_rast
->light_twoside
,
2958 &urb_read_offset
, &urb_read_length
);
2960 unsigned sprite_coord_overrides
=
2961 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
2963 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
2964 sbe
.AttributeSwizzleEnable
= true;
2965 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2966 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
2967 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
2968 sbe
.VertexURBEntryReadLength
= urb_read_length
;
2969 sbe
.ForceVertexURBEntryReadOffset
= true;
2970 sbe
.ForceVertexURBEntryReadLength
= true;
2971 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
2972 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
2974 for (int i
= 0; i
< 32; i
++) {
2975 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
2979 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
2982 /* ------------------------------------------------------------------- */
2985 * Populate VS program key fields based on the current state.
2988 iris_populate_vs_key(const struct iris_context
*ice
,
2989 const struct shader_info
*info
,
2990 struct brw_vs_prog_key
*key
)
2992 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2994 if (info
->clip_distance_array_size
== 0 &&
2995 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)))
2996 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3000 * Populate TCS program key fields based on the current state.
3003 iris_populate_tcs_key(const struct iris_context
*ice
,
3004 struct brw_tcs_prog_key
*key
)
3009 * Populate TES program key fields based on the current state.
3012 iris_populate_tes_key(const struct iris_context
*ice
,
3013 struct brw_tes_prog_key
*key
)
3018 * Populate GS program key fields based on the current state.
3021 iris_populate_gs_key(const struct iris_context
*ice
,
3022 struct brw_gs_prog_key
*key
)
3027 * Populate FS program key fields based on the current state.
3030 iris_populate_fs_key(const struct iris_context
*ice
,
3031 struct brw_wm_prog_key
*key
)
3033 /* XXX: dirty flags? */
3034 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3035 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3036 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3037 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3039 key
->nr_color_regions
= fb
->nr_cbufs
;
3041 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3043 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
3044 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
3046 /* XXX: only bother if COL0/1 are read */
3047 key
->flat_shade
= rast
->flatshade
;
3049 key
->persample_interp
= rast
->force_persample_interp
;
3050 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3052 key
->coherent_fb_fetch
= true;
3054 // XXX: uint64_t input_slots_valid; - for >16 inputs
3056 // XXX: key->force_dual_color_blend for unigine
3057 // XXX: respect hint for high_quality_derivatives:1;
3061 iris_populate_cs_key(const struct iris_context
*ice
,
3062 struct brw_cs_prog_key
*key
)
3067 // XXX: these need to go in INIT_THREAD_DISPATCH_FIELDS
3068 pkt
.SamplerCount
= \
3069 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4); \
3074 KSP(const struct iris_compiled_shader
*shader
)
3076 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3077 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3080 // Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3081 // prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3082 // this WA on C0 stepping.
3084 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3085 pkt.KernelStartPointer = KSP(shader); \
3086 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3087 prog_data->binding_table.size_bytes / 4; \
3088 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3090 pkt.DispatchGRFStartRegisterForURBData = \
3091 prog_data->dispatch_grf_start_reg; \
3092 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3093 pkt.prefix##URBEntryReadOffset = 0; \
3095 pkt.StatisticsEnable = true; \
3096 pkt.Enable = true; \
3098 if (prog_data->total_scratch) { \
3099 uint32_t scratch_addr = \
3100 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3101 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3102 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3106 * Encode most of 3DSTATE_VS based on the compiled shader.
3109 iris_store_vs_state(struct iris_context
*ice
,
3110 const struct gen_device_info
*devinfo
,
3111 struct iris_compiled_shader
*shader
)
3113 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3114 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3116 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3117 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3118 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3119 vs
.SIMD8DispatchEnable
= true;
3120 vs
.UserClipDistanceCullTestEnableBitmask
=
3121 vue_prog_data
->cull_distance_mask
;
3126 * Encode most of 3DSTATE_HS based on the compiled shader.
3129 iris_store_tcs_state(struct iris_context
*ice
,
3130 const struct gen_device_info
*devinfo
,
3131 struct iris_compiled_shader
*shader
)
3133 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3134 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3135 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3137 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3138 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3140 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3141 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3142 hs
.IncludeVertexHandles
= true;
3147 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3150 iris_store_tes_state(struct iris_context
*ice
,
3151 const struct gen_device_info
*devinfo
,
3152 struct iris_compiled_shader
*shader
)
3154 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3155 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3156 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3158 uint32_t *te_state
= (void *) shader
->derived_data
;
3159 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3161 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3162 te
.Partitioning
= tes_prog_data
->partitioning
;
3163 te
.OutputTopology
= tes_prog_data
->output_topology
;
3164 te
.TEDomain
= tes_prog_data
->domain
;
3166 te
.MaximumTessellationFactorOdd
= 63.0;
3167 te
.MaximumTessellationFactorNotOdd
= 64.0;
3170 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3171 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3173 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3174 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3175 ds
.ComputeWCoordinateEnable
=
3176 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3178 ds
.UserClipDistanceCullTestEnableBitmask
=
3179 vue_prog_data
->cull_distance_mask
;
3185 * Encode most of 3DSTATE_GS based on the compiled shader.
3188 iris_store_gs_state(struct iris_context
*ice
,
3189 const struct gen_device_info
*devinfo
,
3190 struct iris_compiled_shader
*shader
)
3192 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3193 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3194 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3196 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3197 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3199 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3200 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3201 gs
.ControlDataHeaderSize
=
3202 gs_prog_data
->control_data_header_size_hwords
;
3203 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3204 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3205 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3206 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3207 gs
.ReorderMode
= TRAILING
;
3208 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3209 gs
.MaximumNumberofThreads
=
3210 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3211 : (devinfo
->max_gs_threads
- 1);
3213 if (gs_prog_data
->static_vertex_count
!= -1) {
3214 gs
.StaticOutput
= true;
3215 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3217 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3219 gs
.UserClipDistanceCullTestEnableBitmask
=
3220 vue_prog_data
->cull_distance_mask
;
3222 const int urb_entry_write_offset
= 1;
3223 const uint32_t urb_entry_output_length
=
3224 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3225 urb_entry_write_offset
;
3227 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3228 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3233 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3236 iris_store_fs_state(struct iris_context
*ice
,
3237 const struct gen_device_info
*devinfo
,
3238 struct iris_compiled_shader
*shader
)
3240 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3241 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3243 uint32_t *ps_state
= (void *) shader
->derived_data
;
3244 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3246 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3247 ps
.VectorMaskEnable
= true;
3248 //ps.SamplerCount = ...
3249 // XXX: WABTPPrefetchDisable, see above, drop at C0
3250 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3251 prog_data
->binding_table
.size_bytes
/ 4;
3252 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3253 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3255 ps
.PushConstantEnable
= shader
->num_system_values
> 0 ||
3256 prog_data
->ubo_ranges
[0].length
> 0;
3258 /* From the documentation for this packet:
3259 * "If the PS kernel does not need the Position XY Offsets to
3260 * compute a Position Value, then this field should be programmed
3261 * to POSOFFSET_NONE."
3263 * "SW Recommendation: If the PS kernel needs the Position Offsets
3264 * to compute a Position XY value, this field should match Position
3265 * ZW Interpolation Mode to ensure a consistent position.xyzw
3268 * We only require XY sample offsets. So, this recommendation doesn't
3269 * look useful at the moment. We might need this in future.
3271 ps
.PositionXYOffsetSelect
=
3272 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3273 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
3274 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
3275 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
3277 // XXX: Disable SIMD32 with 16x MSAA
3279 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3280 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
3281 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
3282 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
3283 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3284 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
3286 ps
.KernelStartPointer0
=
3287 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
3288 ps
.KernelStartPointer1
=
3289 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
3290 ps
.KernelStartPointer2
=
3291 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
3293 if (prog_data
->total_scratch
) {
3294 uint32_t scratch_addr
=
3295 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3296 MESA_SHADER_FRAGMENT
);
3297 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3298 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3302 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3303 psx
.PixelShaderValid
= true;
3304 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3305 // XXX: alpha test / alpha to coverage :/
3306 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
||
3307 wm_prog_data
->uses_omask
;
3308 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3309 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3310 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3311 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3313 if (wm_prog_data
->uses_sample_mask
) {
3314 /* TODO: conservative rasterization */
3315 if (wm_prog_data
->post_depth_coverage
)
3316 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
3318 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
3321 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3322 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3323 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3330 * Compute the size of the derived data (shader command packets).
3332 * This must match the data written by the iris_store_xs_state() functions.
3335 iris_store_cs_state(struct iris_context
*ice
,
3336 const struct gen_device_info
*devinfo
,
3337 struct iris_compiled_shader
*shader
)
3339 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3340 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3341 void *map
= shader
->derived_data
;
3343 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3344 desc
.KernelStartPointer
= KSP(shader
);
3345 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3346 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3347 desc
.SharedLocalMemorySize
=
3348 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3349 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3350 desc
.CrossThreadConstantDataReadLength
=
3351 cs_prog_data
->push
.cross_thread
.regs
;
3356 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3358 assert(cache_id
<= IRIS_CACHE_BLORP
);
3360 static const unsigned dwords
[] = {
3361 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3362 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3363 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3364 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3366 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3367 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3368 [IRIS_CACHE_BLORP
] = 0,
3371 return sizeof(uint32_t) * dwords
[cache_id
];
3375 * Create any state packets corresponding to the given shader stage
3376 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3377 * This means that we can look up a program in the in-memory cache and
3378 * get most of the state packet without having to reconstruct it.
3381 iris_store_derived_program_state(struct iris_context
*ice
,
3382 enum iris_program_cache_id cache_id
,
3383 struct iris_compiled_shader
*shader
)
3385 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3386 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3390 iris_store_vs_state(ice
, devinfo
, shader
);
3392 case IRIS_CACHE_TCS
:
3393 iris_store_tcs_state(ice
, devinfo
, shader
);
3395 case IRIS_CACHE_TES
:
3396 iris_store_tes_state(ice
, devinfo
, shader
);
3399 iris_store_gs_state(ice
, devinfo
, shader
);
3402 iris_store_fs_state(ice
, devinfo
, shader
);
3405 iris_store_cs_state(ice
, devinfo
, shader
);
3406 case IRIS_CACHE_BLORP
:
3413 /* ------------------------------------------------------------------- */
3416 * Configure the URB.
3418 * XXX: write a real comment.
3421 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
3423 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
3424 const unsigned push_size_kB
= 32;
3425 unsigned entries
[4];
3429 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3430 if (!ice
->shaders
.prog
[i
]) {
3433 struct brw_vue_prog_data
*vue_prog_data
=
3434 (void *) ice
->shaders
.prog
[i
]->prog_data
;
3435 size
[i
] = vue_prog_data
->urb_entry_size
;
3437 assert(size
[i
] != 0);
3440 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
3441 1024 * ice
->shaders
.urb_size
,
3442 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
3443 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
3444 size
, entries
, start
);
3446 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3447 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
3448 urb
._3DCommandSubOpcode
+= i
;
3449 urb
.VSURBStartingAddress
= start
[i
];
3450 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
3451 urb
.VSNumberofURBEntries
= entries
[i
];
3456 static const uint32_t push_constant_opcodes
[] = {
3457 [MESA_SHADER_VERTEX
] = 21,
3458 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3459 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3460 [MESA_SHADER_GEOMETRY
] = 22,
3461 [MESA_SHADER_FRAGMENT
] = 23,
3462 [MESA_SHADER_COMPUTE
] = 0,
3466 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3468 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3470 iris_use_pinned_bo(batch
, state_bo
, false);
3472 return ice
->state
.unbound_tex
.offset
;
3476 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3478 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3479 if (!ice
->state
.null_fb
.res
)
3480 return use_null_surface(batch
, ice
);
3482 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3484 iris_use_pinned_bo(batch
, state_bo
, false);
3486 return ice
->state
.null_fb
.offset
;
3490 * Add a surface to the validation list, as well as the buffer containing
3491 * the corresponding SURFACE_STATE.
3493 * Returns the binding table entry (offset to SURFACE_STATE).
3496 use_surface(struct iris_batch
*batch
,
3497 struct pipe_surface
*p_surf
,
3500 struct iris_surface
*surf
= (void *) p_surf
;
3502 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
3503 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
3505 return surf
->surface_state
.offset
;
3509 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
3511 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
3512 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
3514 return isv
->surface_state
.offset
;
3518 use_const_buffer(struct iris_batch
*batch
,
3519 struct iris_context
*ice
,
3520 struct iris_const_buffer
*cbuf
)
3522 if (!cbuf
->surface_state
.res
)
3523 return use_null_surface(batch
, ice
);
3525 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->data
.res
), false);
3526 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->surface_state
.res
), false);
3528 return cbuf
->surface_state
.offset
;
3532 use_ssbo(struct iris_batch
*batch
, struct iris_context
*ice
,
3533 struct iris_shader_state
*shs
, int i
)
3536 return use_null_surface(batch
, ice
);
3538 struct iris_state_ref
*surf_state
= &shs
->ssbo_surface_state
[i
];
3540 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->ssbo
[i
]), true);
3541 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3543 return surf_state
->offset
;
3547 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
3548 struct iris_shader_state
*shs
, int i
)
3550 if (!shs
->image
[i
].res
)
3551 return use_null_surface(batch
, ice
);
3553 struct iris_state_ref
*surf_state
= &shs
->image
[i
].surface_state
;
3555 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->image
[i
].res
),
3556 shs
->image
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
);
3557 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3559 return surf_state
->offset
;
3562 #define push_bt_entry(addr) \
3563 assert(addr >= binder_addr); \
3564 assert(s < prog_data->binding_table.size_bytes / sizeof(uint32_t)); \
3565 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
3567 #define bt_assert(section, exists) \
3568 if (!pin_only) assert(prog_data->binding_table.section == \
3569 (exists) ? s : 0xd0d0d0d0)
3572 * Populate the binding table for a given shader stage.
3574 * This fills out the table of pointers to surfaces required by the shader,
3575 * and also adds those buffers to the validation list so the kernel can make
3576 * resident before running our batch.
3579 iris_populate_binding_table(struct iris_context
*ice
,
3580 struct iris_batch
*batch
,
3581 gl_shader_stage stage
,
3584 const struct iris_binder
*binder
= &ice
->state
.binder
;
3585 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3589 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3590 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3591 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
3593 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
3594 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
3597 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
3599 /* TCS passthrough doesn't need a binding table. */
3600 assert(stage
== MESA_SHADER_TESS_CTRL
);
3604 if (stage
== MESA_SHADER_COMPUTE
) {
3605 /* surface for gl_NumWorkGroups */
3606 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
3607 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
3608 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
3609 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
3610 push_bt_entry(grid_state
->offset
);
3613 if (stage
== MESA_SHADER_FRAGMENT
) {
3614 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3615 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
3616 if (cso_fb
->nr_cbufs
) {
3617 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
3619 cso_fb
->cbufs
[i
] ? use_surface(batch
, cso_fb
->cbufs
[i
], true)
3620 : use_null_fb_surface(batch
, ice
);
3621 push_bt_entry(addr
);
3624 uint32_t addr
= use_null_fb_surface(batch
, ice
);
3625 push_bt_entry(addr
);
3629 bt_assert(texture_start
, info
->num_textures
> 0);
3631 for (int i
= 0; i
< info
->num_textures
; i
++) {
3632 struct iris_sampler_view
*view
= shs
->textures
[i
];
3633 uint32_t addr
= view
? use_sampler_view(batch
, view
)
3634 : use_null_surface(batch
, ice
);
3635 push_bt_entry(addr
);
3638 bt_assert(image_start
, info
->num_images
> 0);
3640 for (int i
= 0; i
< info
->num_images
; i
++) {
3641 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
3642 push_bt_entry(addr
);
3645 const int num_ubos
= iris_get_shader_num_ubos(ice
, stage
);
3647 bt_assert(ubo_start
, num_ubos
> 0);
3649 for (int i
= 0; i
< num_ubos
; i
++) {
3650 uint32_t addr
= use_const_buffer(batch
, ice
, &shs
->constbuf
[i
]);
3651 push_bt_entry(addr
);
3654 bt_assert(ssbo_start
, info
->num_abos
+ info
->num_ssbos
> 0);
3656 /* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
3657 * for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
3658 * in st_atom_storagebuf.c so it'll compact them into one range, with
3659 * SSBOs starting at info->num_abos. Ideally it'd reset num_abos to 0 too
3661 if (info
->num_abos
+ info
->num_ssbos
> 0) {
3662 for (int i
= 0; i
< IRIS_MAX_ABOS
+ info
->num_ssbos
; i
++) {
3663 uint32_t addr
= use_ssbo(batch
, ice
, shs
, i
);
3664 push_bt_entry(addr
);
3669 // XXX: not implemented yet
3670 bt_assert(plane_start
[1], ...);
3671 bt_assert(plane_start
[2], ...);
3676 iris_use_optional_res(struct iris_batch
*batch
,
3677 struct pipe_resource
*res
,
3681 struct iris_bo
*bo
= iris_resource_bo(res
);
3682 iris_use_pinned_bo(batch
, bo
, writeable
);
3686 /* ------------------------------------------------------------------- */
3689 * Pin any BOs which were installed by a previous batch, and restored
3690 * via the hardware logical context mechanism.
3692 * We don't need to re-emit all state every batch - the hardware context
3693 * mechanism will save and restore it for us. This includes pointers to
3694 * various BOs...which won't exist unless we ask the kernel to pin them
3695 * by adding them to the validation list.
3697 * We can skip buffers if we've re-emitted those packets, as we're
3698 * overwriting those stale pointers with new ones, and don't actually
3699 * refer to the old BOs.
3702 iris_restore_render_saved_bos(struct iris_context
*ice
,
3703 struct iris_batch
*batch
,
3704 const struct pipe_draw_info
*draw
)
3706 struct iris_genx_state
*genx
= ice
->state
.genx
;
3708 // XXX: whack IRIS_SHADER_DIRTY_BINDING_TABLE on new batch
3710 const uint64_t clean
= ~ice
->state
.dirty
;
3712 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
3713 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
3716 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3717 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
3720 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
3721 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
3724 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3725 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
3728 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
3729 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
3732 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
3733 for (int i
= 0; i
< 4; i
++) {
3734 struct iris_stream_output_target
*tgt
=
3735 (void *) ice
->state
.so_target
[i
];
3737 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
3739 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
3745 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3746 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
3749 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3750 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3755 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3757 for (int i
= 0; i
< 4; i
++) {
3758 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3760 if (range
->length
== 0)
3763 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3764 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3767 iris_use_pinned_bo(batch
, res
->bo
, false);
3769 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3773 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3774 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
3775 /* Re-pin any buffers referred to by the binding table. */
3776 iris_populate_binding_table(ice
, batch
, stage
, true);
3780 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3781 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3782 struct pipe_resource
*res
= shs
->sampler_table
.res
;
3784 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3787 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3788 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
3789 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3791 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3792 iris_use_pinned_bo(batch
, bo
, false);
3795 // XXX: scratch buffer
3799 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
3800 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3802 if (cso_fb
->zsbuf
) {
3803 struct iris_resource
*zres
, *sres
;
3804 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
3806 // XXX: might not be writable...
3808 iris_use_pinned_bo(batch
, zres
->bo
, true);
3810 iris_use_pinned_bo(batch
, sres
->bo
, true);
3814 if (draw
->index_size
== 0 && ice
->state
.last_res
.index_buffer
) {
3815 /* This draw didn't emit a new index buffer, so we are inheriting the
3816 * older index buffer. This draw didn't need it, but future ones may.
3818 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
3819 iris_use_pinned_bo(batch
, bo
, false);
3822 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
3823 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
3825 const int i
= u_bit_scan64(&bound
);
3826 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
3827 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3833 iris_restore_compute_saved_bos(struct iris_context
*ice
,
3834 struct iris_batch
*batch
,
3835 const struct pipe_grid_info
*grid
)
3837 const uint64_t clean
= ~ice
->state
.dirty
;
3839 const int stage
= MESA_SHADER_COMPUTE
;
3840 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3842 if (clean
& IRIS_DIRTY_CONSTANTS_CS
) {
3843 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3846 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3847 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[0];
3849 if (range
->length
> 0) {
3850 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3851 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3854 iris_use_pinned_bo(batch
, res
->bo
, false);
3856 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3861 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
3862 /* Re-pin any buffers referred to by the binding table. */
3863 iris_populate_binding_table(ice
, batch
, stage
, true);
3866 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
3868 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
3870 if (clean
& IRIS_DIRTY_CS
) {
3871 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3873 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3874 iris_use_pinned_bo(batch
, bo
, false);
3877 // XXX: scratch buffer
3882 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
3885 iris_update_surface_base_address(struct iris_batch
*batch
,
3886 struct iris_binder
*binder
)
3888 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
3891 flush_for_state_base_change(batch
);
3893 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
3894 // XXX: sba.SurfaceStateMemoryObjectControlState = MOCS_WB;
3895 sba
.SurfaceStateBaseAddressModifyEnable
= true;
3896 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
3899 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
3903 iris_upload_dirty_render_state(struct iris_context
*ice
,
3904 struct iris_batch
*batch
,
3905 const struct pipe_draw_info
*draw
)
3907 const uint64_t dirty
= ice
->state
.dirty
;
3909 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
3912 struct iris_genx_state
*genx
= ice
->state
.genx
;
3913 struct iris_binder
*binder
= &ice
->state
.binder
;
3914 struct brw_wm_prog_data
*wm_prog_data
= (void *)
3915 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3917 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
3918 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3919 uint32_t cc_vp_address
;
3921 /* XXX: could avoid streaming for depth_clip [0,1] case. */
3922 uint32_t *cc_vp_map
=
3923 stream_state(batch
, ice
->state
.dynamic_uploader
,
3924 &ice
->state
.last_res
.cc_vp
,
3925 4 * ice
->state
.num_viewports
*
3926 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
3927 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
3929 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
3930 cso_rast
->clip_halfz
, &zmin
, &zmax
);
3931 if (cso_rast
->depth_clip_near
)
3933 if (cso_rast
->depth_clip_far
)
3936 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
3937 ccv
.MinimumDepth
= zmin
;
3938 ccv
.MaximumDepth
= zmax
;
3941 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
3944 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
3945 ptr
.CCViewportPointer
= cc_vp_address
;
3949 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3950 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3951 uint32_t sf_cl_vp_address
;
3953 stream_state(batch
, ice
->state
.dynamic_uploader
,
3954 &ice
->state
.last_res
.sf_cl_vp
,
3955 4 * ice
->state
.num_viewports
*
3956 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
3958 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
3959 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
3960 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
3962 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
3963 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
3964 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
3965 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
3967 calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
3968 state
->scale
[0], state
->scale
[1],
3969 state
->translate
[0], state
->translate
[1],
3970 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
3972 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
3973 vp
.ViewportMatrixElementm00
= state
->scale
[0];
3974 vp
.ViewportMatrixElementm11
= state
->scale
[1];
3975 vp
.ViewportMatrixElementm22
= state
->scale
[2];
3976 vp
.ViewportMatrixElementm30
= state
->translate
[0];
3977 vp
.ViewportMatrixElementm31
= state
->translate
[1];
3978 vp
.ViewportMatrixElementm32
= state
->translate
[2];
3979 vp
.XMinClipGuardband
= gb_xmin
;
3980 vp
.XMaxClipGuardband
= gb_xmax
;
3981 vp
.YMinClipGuardband
= gb_ymin
;
3982 vp
.YMaxClipGuardband
= gb_ymax
;
3983 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
3984 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
3985 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
3986 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
3989 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
3992 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
3993 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
3999 // XXX: this is only flagged at setup, we assume a static configuration
4000 if (dirty
& IRIS_DIRTY_URB
) {
4001 iris_upload_urb_config(ice
, batch
);
4004 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
4005 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4006 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4007 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4008 const int header_dwords
= GENX(BLEND_STATE_length
);
4009 const int rt_dwords
= cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
);
4010 uint32_t blend_offset
;
4011 uint32_t *blend_map
=
4012 stream_state(batch
, ice
->state
.dynamic_uploader
,
4013 &ice
->state
.last_res
.blend
,
4014 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4016 uint32_t blend_state_header
;
4017 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4018 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4019 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4022 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4023 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4025 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4026 ptr
.BlendStatePointer
= blend_offset
;
4027 ptr
.BlendStatePointerValid
= true;
4031 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4032 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4035 stream_state(batch
, ice
->state
.dynamic_uploader
,
4036 &ice
->state
.last_res
.color_calc
,
4037 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4039 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4040 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4041 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4042 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4043 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4044 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4045 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4047 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4048 ptr
.ColorCalcStatePointer
= cc_offset
;
4049 ptr
.ColorCalcStatePointerValid
= true;
4053 /* Upload constants for TCS passthrough. */
4054 if ((dirty
& IRIS_DIRTY_CONSTANTS_TCS
) &&
4055 ice
->shaders
.prog
[MESA_SHADER_TESS_CTRL
] &&
4056 !ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
]) {
4057 struct iris_compiled_shader
*tes_shader
= ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
4060 /* Passthrough always copies 2 vec4s, so when uploading data we ensure
4061 * it is in the right layout for TES.
4064 struct brw_tes_prog_data
*tes_prog_data
= (void *) tes_shader
->prog_data
;
4065 switch (tes_prog_data
->domain
) {
4066 case BRW_TESS_DOMAIN_QUAD
:
4067 for (int i
= 0; i
< 4; i
++)
4068 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4069 hdr
[3] = ice
->state
.default_inner_level
[0];
4070 hdr
[2] = ice
->state
.default_inner_level
[1];
4072 case BRW_TESS_DOMAIN_TRI
:
4073 for (int i
= 0; i
< 3; i
++)
4074 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4075 hdr
[4] = ice
->state
.default_inner_level
[0];
4077 case BRW_TESS_DOMAIN_ISOLINE
:
4078 hdr
[7] = ice
->state
.default_outer_level
[1];
4079 hdr
[6] = ice
->state
.default_outer_level
[0];
4083 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
4084 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
4085 u_upload_data(ice
->ctx
.const_uploader
, 0, sizeof(hdr
), 32,
4086 &hdr
[0], &cbuf
->data
.offset
,
4090 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4091 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4094 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4095 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4100 if (shs
->cbuf0_needs_upload
)
4101 upload_uniforms(ice
, stage
);
4103 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4105 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4106 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4108 /* The Skylake PRM contains the following restriction:
4110 * "The driver must ensure The following case does not occur
4111 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4112 * buffer 3 read length equal to zero committed followed by a
4113 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4116 * To avoid this, we program the buffers in the highest slots.
4117 * This way, slot 0 is only used if slot 3 is also used.
4121 for (int i
= 3; i
>= 0; i
--) {
4122 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4124 if (range
->length
== 0)
4127 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4128 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
4130 assert(cbuf
->data
.offset
% 32 == 0);
4132 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4133 pkt
.ConstantBody
.Buffer
[n
] =
4134 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->data
.offset
)
4135 : ro_bo(batch
->screen
->workaround_bo
, 0);
4142 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4143 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4144 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4145 ptr
._3DCommandSubOpcode
= 38 + stage
;
4146 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4151 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4152 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4153 iris_populate_binding_table(ice
, batch
, stage
, false);
4157 if (ice
->state
.need_border_colors
)
4158 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4160 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4161 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4162 !ice
->shaders
.prog
[stage
])
4165 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4166 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4168 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4170 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4171 ptr
._3DCommandSubOpcode
= 43 + stage
;
4172 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4176 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4177 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4179 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4180 if (ice
->state
.framebuffer
.samples
> 0)
4181 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4185 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4186 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4187 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
4191 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4192 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4195 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4198 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4199 iris_use_pinned_bo(batch
, cache
->bo
, false);
4200 iris_batch_emit(batch
, shader
->derived_data
,
4201 iris_derived_program_state_size(stage
));
4203 if (stage
== MESA_SHADER_TESS_EVAL
) {
4204 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4205 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4206 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4207 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4208 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4213 if (ice
->state
.streamout_active
) {
4214 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4215 iris_batch_emit(batch
, genx
->so_buffers
,
4216 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4217 for (int i
= 0; i
< 4; i
++) {
4218 struct iris_stream_output_target
*tgt
=
4219 (void *) ice
->state
.so_target
[i
];
4221 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4223 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4229 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
4230 uint32_t *decl_list
=
4231 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
4232 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
4235 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4236 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4238 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
4239 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
4240 sol
.SOFunctionEnable
= true;
4241 sol
.SOStatisticsEnable
= true;
4243 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
4244 !ice
->state
.prims_generated_query_active
;
4245 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
4248 assert(ice
->state
.streamout
);
4250 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
4251 GENX(3DSTATE_STREAMOUT_length
));
4254 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4255 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
4259 if (dirty
& IRIS_DIRTY_CLIP
) {
4260 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4261 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4263 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
4264 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
4265 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4266 cl
.ClipMode
= cso_rast
->rasterizer_discard
? CLIPMODE_REJECT_ALL
4268 if (wm_prog_data
->barycentric_interp_modes
&
4269 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
4270 cl
.NonPerspectiveBarycentricEnable
= true;
4272 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
4273 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
4275 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
4276 ARRAY_SIZE(cso_rast
->clip
));
4279 if (dirty
& IRIS_DIRTY_RASTER
) {
4280 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4281 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
4282 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
4286 /* XXX: FS program updates needs to flag IRIS_DIRTY_WM */
4287 if (dirty
& IRIS_DIRTY_WM
) {
4288 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4289 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
4291 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
4292 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4294 wm
.BarycentricInterpolationMode
=
4295 wm_prog_data
->barycentric_interp_modes
;
4297 if (wm_prog_data
->early_fragment_tests
)
4298 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
4299 else if (wm_prog_data
->has_side_effects
)
4300 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
4302 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
4305 if (dirty
& IRIS_DIRTY_SBE
) {
4306 iris_emit_sbe(batch
, ice
);
4309 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
4310 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4311 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4312 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
4313 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
4314 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
4315 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4318 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
4319 ARRAY_SIZE(cso_blend
->ps_blend
));
4322 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
4323 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4324 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4326 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
4327 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
4328 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4329 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4331 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
4334 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
4335 uint32_t scissor_offset
=
4336 emit_state(batch
, ice
->state
.dynamic_uploader
,
4337 &ice
->state
.last_res
.scissor
,
4338 ice
->state
.scissors
,
4339 sizeof(struct pipe_scissor_state
) *
4340 ice
->state
.num_viewports
, 32);
4342 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
4343 ptr
.ScissorRectPointer
= scissor_offset
;
4347 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
4348 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4349 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
4351 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
4353 if (cso_fb
->zsbuf
) {
4354 struct iris_resource
*zres
, *sres
;
4355 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
4357 // XXX: might not be writable...
4359 iris_use_pinned_bo(batch
, zres
->bo
, true);
4361 iris_use_pinned_bo(batch
, sres
->bo
, true);
4365 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
4366 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
4367 for (int i
= 0; i
< 32; i
++) {
4368 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
4373 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
4374 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4375 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
4378 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
4379 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
4380 topo
.PrimitiveTopologyType
=
4381 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
4385 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4386 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
4389 /* The VF cache designers cut corners, and made the cache key's
4390 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
4391 * 32 bits of the address. If you have two vertex buffers which get
4392 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
4393 * you can get collisions (even within a single batch).
4395 * So, we need to do a VF cache invalidate if the buffer for a VB
4396 * slot slot changes [48:32] address bits from the previous time.
4398 unsigned flush_flags
= 0;
4400 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4402 const int i
= u_bit_scan64(&bound
);
4403 uint16_t high_bits
= 0;
4405 struct iris_resource
*res
=
4406 (void *) genx
->vertex_buffers
[i
].resource
;
4408 iris_use_pinned_bo(batch
, res
->bo
, false);
4410 high_bits
= res
->bo
->gtt_offset
>> 32ull;
4411 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
4412 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
4413 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
4416 /* If the buffer was written to by streamout, we may need
4417 * to stall so those writes land and become visible to the
4420 * TODO: This may stall more than necessary.
4422 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
4423 flush_flags
|= PIPE_CONTROL_CS_STALL
;
4428 iris_emit_pipe_control_flush(batch
, flush_flags
);
4430 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
4433 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
4434 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
4435 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
4439 bound
= ice
->state
.bound_vertex_buffers
;
4441 const int i
= u_bit_scan64(&bound
);
4442 memcpy(map
, genx
->vertex_buffers
[i
].state
,
4443 sizeof(uint32_t) * vb_dwords
);
4449 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
4450 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4451 const unsigned entries
= MAX2(cso
->count
, 1);
4452 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
4453 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
4454 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
4455 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
4458 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
4459 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
4460 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
4461 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4463 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
4464 if (vs_prog_data
->uses_vertexid
) {
4465 sgv
.VertexIDEnable
= true;
4466 sgv
.VertexIDComponentNumber
= 2;
4467 sgv
.VertexIDElementOffset
= cso
->count
;
4470 if (vs_prog_data
->uses_instanceid
) {
4471 sgv
.InstanceIDEnable
= true;
4472 sgv
.InstanceIDComponentNumber
= 3;
4473 sgv
.InstanceIDElementOffset
= cso
->count
;
4478 if (dirty
& IRIS_DIRTY_VF
) {
4479 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
4480 if (draw
->primitive_restart
) {
4481 vf
.IndexedDrawCutIndexEnable
= true;
4482 vf
.CutIndex
= draw
->restart_index
;
4487 // XXX: Gen8 - PMA fix
4491 iris_upload_render_state(struct iris_context
*ice
,
4492 struct iris_batch
*batch
,
4493 const struct pipe_draw_info
*draw
)
4495 /* Always pin the binder. If we're emitting new binding table pointers,
4496 * we need it. If not, we're probably inheriting old tables via the
4497 * context, and need it anyway. Since true zero-bindings cases are
4498 * practically non-existent, just pin it and avoid last_res tracking.
4500 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
4502 if (!batch
->contains_draw
) {
4503 iris_restore_render_saved_bos(ice
, batch
, draw
);
4504 batch
->contains_draw
= true;
4507 iris_upload_dirty_render_state(ice
, batch
, draw
);
4509 if (draw
->index_size
> 0) {
4512 if (draw
->has_user_indices
) {
4513 u_upload_data(ice
->ctx
.stream_uploader
, 0,
4514 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
4515 &offset
, &ice
->state
.last_res
.index_buffer
);
4517 struct iris_resource
*res
= (void *) draw
->index
.resource
;
4518 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
4520 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
4521 draw
->index
.resource
);
4525 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4527 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
4528 ib
.IndexFormat
= draw
->index_size
>> 1;
4530 ib
.BufferSize
= bo
->size
;
4531 ib
.BufferStartingAddress
= ro_bo(bo
, offset
);
4534 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
4535 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
4536 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
4537 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_VF_CACHE_INVALIDATE
);
4538 ice
->state
.last_index_bo_high_bits
= high_bits
;
4542 #define _3DPRIM_END_OFFSET 0x2420
4543 #define _3DPRIM_START_VERTEX 0x2430
4544 #define _3DPRIM_VERTEX_COUNT 0x2434
4545 #define _3DPRIM_INSTANCE_COUNT 0x2438
4546 #define _3DPRIM_START_INSTANCE 0x243C
4547 #define _3DPRIM_BASE_VERTEX 0x2440
4549 if (draw
->indirect
) {
4550 /* We don't support this MultidrawIndirect. */
4551 assert(!draw
->indirect
->indirect_draw_count
);
4553 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
4556 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4557 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
4558 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
4560 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4561 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
4562 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
4564 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4565 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
4566 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
4568 if (draw
->index_size
) {
4569 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4570 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
4571 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4573 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4574 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4575 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
4578 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4579 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4580 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4582 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
4583 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
4587 } else if (draw
->count_from_stream_output
) {
4588 struct iris_stream_output_target
*so
=
4589 (void *) draw
->count_from_stream_output
;
4591 // XXX: avoid if possible
4592 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
4594 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4595 lrm
.RegisterAddress
= CS_GPR(0);
4597 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
4599 iris_math_div32_gpr0(ice
, batch
, so
->stride
);
4600 _iris_emit_lrr(batch
, _3DPRIM_VERTEX_COUNT
, CS_GPR(0));
4602 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
4603 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
4604 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
4605 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
4608 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
4609 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
4610 prim
.PredicateEnable
=
4611 ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
4613 if (draw
->indirect
|| draw
->count_from_stream_output
) {
4614 prim
.IndirectParameterEnable
= true;
4616 prim
.StartInstanceLocation
= draw
->start_instance
;
4617 prim
.InstanceCount
= draw
->instance_count
;
4618 prim
.VertexCountPerInstance
= draw
->count
;
4620 // XXX: this is probably bonkers.
4621 prim
.StartVertexLocation
= draw
->start
;
4623 if (draw
->index_size
) {
4624 prim
.BaseVertexLocation
+= draw
->index_bias
;
4626 prim
.StartVertexLocation
+= draw
->index_bias
;
4629 //prim.BaseVertexLocation = ...;
4635 iris_upload_compute_state(struct iris_context
*ice
,
4636 struct iris_batch
*batch
,
4637 const struct pipe_grid_info
*grid
)
4639 const uint64_t dirty
= ice
->state
.dirty
;
4640 struct iris_screen
*screen
= batch
->screen
;
4641 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
4642 struct iris_binder
*binder
= &ice
->state
.binder
;
4643 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
4644 struct iris_compiled_shader
*shader
=
4645 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
4646 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4647 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
4649 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->cbuf0_needs_upload
)
4650 upload_uniforms(ice
, MESA_SHADER_COMPUTE
);
4652 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
4653 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
4655 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
4656 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
4658 if (ice
->state
.need_border_colors
)
4659 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4661 if (dirty
& IRIS_DIRTY_CS
) {
4662 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4664 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4665 * the only bits that are changed are scoreboard related: Scoreboard
4666 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
4667 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4670 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
4672 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4673 if (prog_data
->total_scratch
) {
4674 uint32_t scratch_addr
=
4675 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
4676 MESA_SHADER_COMPUTE
);
4677 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
4678 vfe
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
4681 vfe
.MaximumNumberofThreads
=
4682 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
4684 vfe
.ResetGatewayTimer
=
4685 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4688 vfe
.NumberofURBEntries
= 2;
4689 vfe
.URBEntryAllocationSize
= 2;
4691 // XXX: Use Indirect Payload Storage?
4692 vfe
.CURBEAllocationSize
=
4693 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4694 cs_prog_data
->push
.cross_thread
.regs
, 2);
4698 // XXX: hack iris_set_constant_buffers to upload these thread counts
4699 // XXX: along with regular uniforms for compute shaders, somehow.
4701 uint32_t curbe_data_offset
= 0;
4702 // TODO: Move subgroup-id into uniforms ubo so we can push uniforms
4703 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
4704 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
4705 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
4706 struct pipe_resource
*curbe_data_res
= NULL
;
4707 uint32_t *curbe_data_map
=
4708 stream_state(batch
, ice
->state
.dynamic_uploader
, &curbe_data_res
,
4709 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
4710 &curbe_data_offset
);
4711 assert(curbe_data_map
);
4712 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
4713 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
4715 if (dirty
& IRIS_DIRTY_CONSTANTS_CS
) {
4716 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4717 curbe
.CURBETotalDataLength
=
4718 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4719 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
4723 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
4724 IRIS_DIRTY_BINDINGS_CS
|
4725 IRIS_DIRTY_CONSTANTS_CS
|
4727 struct pipe_resource
*desc_res
= NULL
;
4728 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4730 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
4731 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
4732 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
4735 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
4736 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
4738 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4739 load
.InterfaceDescriptorTotalLength
=
4740 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4741 load
.InterfaceDescriptorDataStartAddress
=
4742 emit_state(batch
, ice
->state
.dynamic_uploader
,
4743 &desc_res
, desc
, sizeof(desc
), 32);
4746 pipe_resource_reference(&desc_res
, NULL
);
4749 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
4750 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
4751 uint32_t right_mask
;
4754 right_mask
= ~0u >> (32 - remainder
);
4756 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
4758 #define GPGPU_DISPATCHDIMX 0x2500
4759 #define GPGPU_DISPATCHDIMY 0x2504
4760 #define GPGPU_DISPATCHDIMZ 0x2508
4762 if (grid
->indirect
) {
4763 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
4764 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
4765 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4766 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
4767 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
4769 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4770 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
4771 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
4773 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4774 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
4775 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
4779 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
4780 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
4781 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
4782 ggw
.ThreadDepthCounterMaximum
= 0;
4783 ggw
.ThreadHeightCounterMaximum
= 0;
4784 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
4785 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
4786 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
4787 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
4788 ggw
.RightExecutionMask
= right_mask
;
4789 ggw
.BottomExecutionMask
= 0xffffffff;
4792 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4794 if (!batch
->contains_draw
) {
4795 iris_restore_compute_saved_bos(ice
, batch
, grid
);
4796 batch
->contains_draw
= true;
4801 * State module teardown.
4804 iris_destroy_state(struct iris_context
*ice
)
4806 struct iris_genx_state
*genx
= ice
->state
.genx
;
4808 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
4810 const int i
= u_bit_scan64(&bound_vbs
);
4811 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
4814 // XXX: unreference resources/surfaces.
4815 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
4816 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
4818 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
4820 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
4821 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4822 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
4824 free(ice
->state
.genx
);
4826 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
4828 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
4829 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
4830 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
4831 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
4832 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
4833 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
4836 /* ------------------------------------------------------------------- */
4839 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
4842 _iris_emit_lrr(batch
, dst
, src
);
4846 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
4849 _iris_emit_lrr(batch
, dst
, src
);
4850 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
4854 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
4857 _iris_emit_lri(batch
, reg
, val
);
4861 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
4864 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
4865 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
4869 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
4872 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
4873 struct iris_bo
*bo
, uint32_t offset
)
4875 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4876 lrm
.RegisterAddress
= reg
;
4877 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
4882 * Load a 64-bit value from a buffer into a MMIO register via
4883 * two MI_LOAD_REGISTER_MEM commands.
4886 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
4887 struct iris_bo
*bo
, uint32_t offset
)
4889 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
4890 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
4894 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
4895 struct iris_bo
*bo
, uint32_t offset
,
4898 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
4899 srm
.RegisterAddress
= reg
;
4900 srm
.MemoryAddress
= rw_bo(bo
, offset
);
4901 srm
.PredicateEnable
= predicated
;
4906 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
4907 struct iris_bo
*bo
, uint32_t offset
,
4910 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
4911 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
4915 iris_store_data_imm32(struct iris_batch
*batch
,
4916 struct iris_bo
*bo
, uint32_t offset
,
4919 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
4920 sdi
.Address
= rw_bo(bo
, offset
);
4921 sdi
.ImmediateData
= imm
;
4926 iris_store_data_imm64(struct iris_batch
*batch
,
4927 struct iris_bo
*bo
, uint32_t offset
,
4930 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
4931 * 2 in genxml but it's actually variable length and we need 5 DWords.
4933 void *map
= iris_get_command_space(batch
, 4 * 5);
4934 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
4935 sdi
.DWordLength
= 5 - 2;
4936 sdi
.Address
= rw_bo(bo
, offset
);
4937 sdi
.ImmediateData
= imm
;
4942 iris_copy_mem_mem(struct iris_batch
*batch
,
4943 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
4944 struct iris_bo
*src_bo
, uint32_t src_offset
,
4947 /* MI_COPY_MEM_MEM operates on DWords. */
4948 assert(bytes
% 4 == 0);
4949 assert(dst_offset
% 4 == 0);
4950 assert(src_offset
% 4 == 0);
4952 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
4953 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
4954 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
4955 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
4960 /* ------------------------------------------------------------------- */
4963 flags_to_post_sync_op(uint32_t flags
)
4965 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
4966 return WriteImmediateData
;
4968 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
4969 return WritePSDepthCount
;
4971 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
4972 return WriteTimestamp
;
4978 * Do the given flags have a Post Sync or LRI Post Sync operation?
4980 static enum pipe_control_flags
4981 get_post_sync_flags(enum pipe_control_flags flags
)
4983 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
4984 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
4985 PIPE_CONTROL_WRITE_TIMESTAMP
|
4986 PIPE_CONTROL_LRI_POST_SYNC_OP
;
4988 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
4989 * "LRI Post Sync Operation". So more than one bit set would be illegal.
4991 assert(util_bitcount(flags
) <= 1);
4996 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
4999 * Emit a series of PIPE_CONTROL commands, taking into account any
5000 * workarounds necessary to actually accomplish the caller's request.
5002 * Unless otherwise noted, spec quotations in this function come from:
5004 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
5005 * Restrictions for PIPE_CONTROL.
5007 * You should not use this function directly. Use the helpers in
5008 * iris_pipe_control.c instead, which may split the pipe control further.
5011 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
5012 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
5014 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
5015 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
5016 enum pipe_control_flags non_lri_post_sync_flags
=
5017 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
5019 /* Recursive PIPE_CONTROL workarounds --------------------------------
5020 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
5022 * We do these first because we want to look at the original operation,
5023 * rather than any workarounds we set.
5025 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
5026 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
5027 * lists several workarounds:
5029 * "Project: SKL, KBL, BXT
5031 * If the VF Cache Invalidation Enable is set to a 1 in a
5032 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
5033 * sets to 0, with the VF Cache Invalidation Enable set to 0
5034 * needs to be sent prior to the PIPE_CONTROL with VF Cache
5035 * Invalidation Enable set to a 1."
5037 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
5040 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
5041 /* Project: SKL / Argument: LRI Post Sync Operation [23]
5043 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5044 * programmed prior to programming a PIPECONTROL command with "LRI
5045 * Post Sync Operation" in GPGPU mode of operation (i.e when
5046 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
5048 * The same text exists a few rows below for Post Sync Op.
5050 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
5053 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
5055 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
5056 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
5057 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
5059 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
5063 /* "Flush Types" workarounds ---------------------------------------------
5064 * We do these now because they may add post-sync operations or CS stalls.
5067 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
5068 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
5070 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
5071 * 'Write PS Depth Count' or 'Write Timestamp'."
5074 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5075 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5076 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5077 bo
= batch
->screen
->workaround_bo
;
5081 /* #1130 from Gen10 workarounds page:
5083 * "Enable Depth Stall on every Post Sync Op if Render target Cache
5084 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
5085 * board stall if Render target cache flush is enabled."
5087 * Applicable to CNL B0 and C0 steppings only.
5089 * The wording here is unclear, and this workaround doesn't look anything
5090 * like the internal bug report recommendations, but leave it be for now...
5092 if (GEN_GEN
== 10) {
5093 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
5094 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5095 } else if (flags
& non_lri_post_sync_flags
) {
5096 flags
|= PIPE_CONTROL_DEPTH_STALL
;
5100 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
5101 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
5103 * "This bit must be DISABLED for operations other than writing
5106 * This seems like nonsense. An Ivybridge workaround requires us to
5107 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
5108 * operation. Gen8+ requires us to emit depth stalls and depth cache
5109 * flushes together. So, it's hard to imagine this means anything other
5110 * than "we originally intended this to be used for PS_DEPTH_COUNT".
5112 * We ignore the supposed restriction and do nothing.
5116 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5117 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5118 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
5120 * "This bit must be DISABLED for End-of-pipe (Read) fences,
5121 * PS_DEPTH_COUNT or TIMESTAMP queries."
5123 * TODO: Implement end-of-pipe checking.
5125 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5126 PIPE_CONTROL_WRITE_TIMESTAMP
)));
5129 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5130 /* From the PIPE_CONTROL instruction table, bit 1:
5132 * "This bit is ignored if Depth Stall Enable is set.
5133 * Further, the render cache is not flushed even if Write Cache
5134 * Flush Enable bit is set."
5136 * We assert that the caller doesn't do this combination, to try and
5137 * prevent mistakes. It shouldn't hurt the GPU, though.
5139 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
5140 * and "Render Target Flush" combo is explicitly required for BTI
5141 * update workarounds.
5143 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
5144 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
5147 /* PIPE_CONTROL page workarounds ------------------------------------- */
5149 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
5150 /* From the PIPE_CONTROL page itself:
5153 * Restriction: Pipe_control with CS-stall bit set must be issued
5154 * before a pipe-control command that has the State Cache
5155 * Invalidate bit set."
5157 flags
|= PIPE_CONTROL_CS_STALL
;
5160 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
5161 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
5164 * SW must always program Post-Sync Operation to "Write Immediate
5165 * Data" when Flush LLC is set."
5167 * For now, we just require the caller to do it.
5169 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
5172 /* "Post-Sync Operation" workarounds -------------------------------- */
5174 /* Project: All / Argument: Global Snapshot Count Reset [19]
5176 * "This bit must not be exercised on any product.
5177 * Requires stall bit ([20] of DW1) set."
5179 * We don't use this, so we just assert that it isn't used. The
5180 * PIPE_CONTROL instruction page indicates that they intended this
5181 * as a debug feature and don't think it is useful in production,
5182 * but it may actually be usable, should we ever want to.
5184 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
5186 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
5187 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
5188 /* Project: All / Arguments:
5190 * - Generic Media State Clear [16]
5191 * - Indirect State Pointers Disable [16]
5193 * "Requires stall bit ([20] of DW1) set."
5195 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
5196 * State Clear) says:
5198 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5199 * programmed prior to programming a PIPECONTROL command with "Media
5200 * State Clear" set in GPGPU mode of operation"
5202 * This is a subset of the earlier rule, so there's nothing to do.
5204 flags
|= PIPE_CONTROL_CS_STALL
;
5207 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
5208 /* Project: All / Argument: Store Data Index
5210 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5213 * For now, we just assert that the caller does this. We might want to
5214 * automatically add a write to the workaround BO...
5216 assert(non_lri_post_sync_flags
!= 0);
5219 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
5220 /* Project: All / Argument: Sync GFDT
5222 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5223 * than '0' or 0x2520[13] must be set."
5225 * For now, we just assert that the caller does this.
5227 assert(non_lri_post_sync_flags
!= 0);
5230 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
5231 /* Project: IVB+ / Argument: TLB inv
5233 * "Requires stall bit ([20] of DW1) set."
5235 * Also, from the PIPE_CONTROL instruction table:
5238 * Post Sync Operation or CS stall must be set to ensure a TLB
5239 * invalidation occurs. Otherwise no cycle will occur to the TLB
5240 * cache to invalidate."
5242 * This is not a subset of the earlier rule, so there's nothing to do.
5244 flags
|= PIPE_CONTROL_CS_STALL
;
5247 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
5248 /* TODO: The big Skylake GT4 post sync op workaround */
5251 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
5253 if (IS_COMPUTE_PIPELINE(batch
)) {
5254 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
5255 /* Project: SKL+ / Argument: Tex Invalidate
5256 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
5258 flags
|= PIPE_CONTROL_CS_STALL
;
5261 if (GEN_GEN
== 8 && (post_sync_flags
||
5262 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
5263 PIPE_CONTROL_DEPTH_STALL
|
5264 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5265 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5266 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
5267 /* Project: BDW / Arguments:
5269 * - LRI Post Sync Operation [23]
5270 * - Post Sync Op [15:14]
5272 * - Depth Stall [13]
5273 * - Render Target Cache Flush [12]
5274 * - Depth Cache Flush [0]
5275 * - DC Flush Enable [5]
5277 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
5280 flags
|= PIPE_CONTROL_CS_STALL
;
5282 /* Also, from the PIPE_CONTROL instruction table, bit 20:
5285 * This bit must be always set when PIPE_CONTROL command is
5286 * programmed by GPGPU and MEDIA workloads, except for the cases
5287 * when only Read Only Cache Invalidation bits are set (State
5288 * Cache Invalidation Enable, Instruction cache Invalidation
5289 * Enable, Texture Cache Invalidation Enable, Constant Cache
5290 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
5291 * need not implemented when FF_DOP_CG is disable via "Fixed
5292 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
5294 * It sounds like we could avoid CS stalls in some cases, but we
5295 * don't currently bother. This list isn't exactly the list above,
5301 /* "Stall" workarounds ----------------------------------------------
5302 * These have to come after the earlier ones because we may have added
5303 * some additional CS stalls above.
5306 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
5307 /* Project: PRE-SKL, VLV, CHV
5309 * "[All Stepping][All SKUs]:
5311 * One of the following must also be set:
5313 * - Render Target Cache Flush Enable ([12] of DW1)
5314 * - Depth Cache Flush Enable ([0] of DW1)
5315 * - Stall at Pixel Scoreboard ([1] of DW1)
5316 * - Depth Stall ([13] of DW1)
5317 * - Post-Sync Operation ([13] of DW1)
5318 * - DC Flush Enable ([5] of DW1)"
5320 * If we don't already have one of those bits set, we choose to add
5321 * "Stall at Pixel Scoreboard". Some of the other bits require a
5322 * CS stall as a workaround (see above), which would send us into
5323 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
5324 * appears to be safe, so we choose that.
5326 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5327 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5328 PIPE_CONTROL_WRITE_IMMEDIATE
|
5329 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5330 PIPE_CONTROL_WRITE_TIMESTAMP
|
5331 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
5332 PIPE_CONTROL_DEPTH_STALL
|
5333 PIPE_CONTROL_DATA_CACHE_FLUSH
;
5334 if (!(flags
& wa_bits
))
5335 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5338 /* Emit --------------------------------------------------------------- */
5340 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
5341 pc
.LRIPostSyncOperation
= NoLRIOperation
;
5342 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
5343 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
5344 pc
.StoreDataIndex
= 0;
5345 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
5346 pc
.GlobalSnapshotCountReset
=
5347 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
5348 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
5349 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
5350 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5351 pc
.RenderTargetCacheFlushEnable
=
5352 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
5353 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
5354 pc
.StateCacheInvalidationEnable
=
5355 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
5356 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
5357 pc
.ConstantCacheInvalidationEnable
=
5358 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
5359 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
5360 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
5361 pc
.InstructionCacheInvalidateEnable
=
5362 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
5363 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
5364 pc
.IndirectStatePointersDisable
=
5365 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
5366 pc
.TextureCacheInvalidationEnable
=
5367 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
5368 pc
.Address
= rw_bo(bo
, offset
);
5369 pc
.ImmediateData
= imm
;
5374 genX(init_state
)(struct iris_context
*ice
)
5376 struct pipe_context
*ctx
= &ice
->ctx
;
5377 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
5379 ctx
->create_blend_state
= iris_create_blend_state
;
5380 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
5381 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
5382 ctx
->create_sampler_state
= iris_create_sampler_state
;
5383 ctx
->create_sampler_view
= iris_create_sampler_view
;
5384 ctx
->create_surface
= iris_create_surface
;
5385 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
5386 ctx
->bind_blend_state
= iris_bind_blend_state
;
5387 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
5388 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
5389 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
5390 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
5391 ctx
->delete_blend_state
= iris_delete_state
;
5392 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
5393 ctx
->delete_rasterizer_state
= iris_delete_state
;
5394 ctx
->delete_sampler_state
= iris_delete_state
;
5395 ctx
->delete_vertex_elements_state
= iris_delete_state
;
5396 ctx
->set_blend_color
= iris_set_blend_color
;
5397 ctx
->set_clip_state
= iris_set_clip_state
;
5398 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
5399 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
5400 ctx
->set_shader_images
= iris_set_shader_images
;
5401 ctx
->set_sampler_views
= iris_set_sampler_views
;
5402 ctx
->set_tess_state
= iris_set_tess_state
;
5403 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
5404 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
5405 ctx
->set_sample_mask
= iris_set_sample_mask
;
5406 ctx
->set_scissor_states
= iris_set_scissor_states
;
5407 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
5408 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
5409 ctx
->set_viewport_states
= iris_set_viewport_states
;
5410 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
5411 ctx
->surface_destroy
= iris_surface_destroy
;
5412 ctx
->draw_vbo
= iris_draw_vbo
;
5413 ctx
->launch_grid
= iris_launch_grid
;
5414 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
5415 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
5416 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
5418 ice
->vtbl
.destroy_state
= iris_destroy_state
;
5419 ice
->vtbl
.init_render_context
= iris_init_render_context
;
5420 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
5421 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
5422 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
5423 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
5424 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
5425 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
5426 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
5427 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
5428 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
5429 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
5430 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
5431 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
5432 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
5433 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
5434 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
5435 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
5436 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
5437 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
5438 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
5439 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
5440 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
5441 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
5442 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
5443 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
5444 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
5446 ice
->state
.dirty
= ~0ull;
5448 ice
->state
.statistics_counters_enabled
= true;
5450 ice
->state
.sample_mask
= 0xffff;
5451 ice
->state
.num_viewports
= 1;
5452 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
5454 /* Make a 1x1x1 null surface for unbound textures */
5455 void *null_surf_map
=
5456 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
5457 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
5458 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
5459 ice
->state
.unbound_tex
.offset
+=
5460 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
5462 /* Default all scissor rectangles to be empty regions. */
5463 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
5464 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
5465 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,