2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_dual_blend.h"
92 #include "util/u_inlines.h"
93 #include "util/u_format.h"
94 #include "util/u_framebuffer.h"
95 #include "util/u_transfer.h"
96 #include "util/u_upload_mgr.h"
97 #include "util/u_viewport.h"
98 #include "drm-uapi/i915_drm.h"
100 #include "intel/compiler/brw_compiler.h"
101 #include "intel/common/gen_l3_config.h"
102 #include "intel/common/gen_sample_positions.h"
103 #include "iris_batch.h"
104 #include "iris_context.h"
105 #include "iris_defines.h"
106 #include "iris_pipe.h"
107 #include "iris_resource.h"
109 #define __gen_address_type struct iris_address
110 #define __gen_user_data struct iris_batch
112 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
115 __gen_combine_address(struct iris_batch
*batch
, void *location
,
116 struct iris_address addr
, uint32_t delta
)
118 uint64_t result
= addr
.offset
+ delta
;
121 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
122 /* Assume this is a general address, not relative to a base. */
123 result
+= addr
.bo
->gtt_offset
;
129 #define __genxml_cmd_length(cmd) cmd ## _length
130 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
131 #define __genxml_cmd_header(cmd) cmd ## _header
132 #define __genxml_cmd_pack(cmd) cmd ## _pack
134 #define _iris_pack_command(batch, cmd, dst, name) \
135 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
136 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
137 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
141 #define iris_pack_command(cmd, dst, name) \
142 _iris_pack_command(NULL, cmd, dst, name)
144 #define iris_pack_state(cmd, dst, name) \
145 for (struct cmd name = {}, \
146 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
147 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
150 #define iris_emit_cmd(batch, cmd, name) \
151 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
153 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
155 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
156 for (uint32_t i = 0; i < num_dwords; i++) \
157 dw[i] = (dwords0)[i] | (dwords1)[i]; \
158 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
161 #include "genxml/genX_pack.h"
162 #include "genxml/gen_macros.h"
163 #include "genxml/genX_bits.h"
166 #define MOCS_PTE 0x18
169 #define MOCS_PTE (1 << 1)
170 #define MOCS_WB (2 << 1)
174 mocs(const struct iris_bo
*bo
)
176 return bo
&& bo
->external
? MOCS_PTE
: MOCS_WB
;
180 * Statically assert that PIPE_* enums match the hardware packets.
181 * (As long as they match, we don't need to translate them.)
183 UNUSED
static void pipe_asserts()
185 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
187 /* pipe_logicop happens to match the hardware. */
188 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
189 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
190 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
191 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
192 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
193 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
194 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
195 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
196 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
197 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
198 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
199 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
200 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
201 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
202 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
203 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
205 /* pipe_blend_func happens to match the hardware. */
206 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
207 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
211 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
212 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
213 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
214 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
215 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
216 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
217 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
218 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
219 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
220 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
221 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
222 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
223 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
224 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
226 /* pipe_blend_func happens to match the hardware. */
227 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
228 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
229 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
230 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
231 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
233 /* pipe_stencil_op happens to match the hardware. */
234 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
235 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
236 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
237 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
238 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
239 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
240 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
241 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
243 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
244 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
245 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
250 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
252 static const unsigned map
[] = {
253 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
254 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
255 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
256 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
257 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
258 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
259 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
260 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
261 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
262 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
263 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
264 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
265 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
266 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
267 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
270 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
274 translate_compare_func(enum pipe_compare_func pipe_func
)
276 static const unsigned map
[] = {
277 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
278 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
279 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
280 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
281 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
282 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
283 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
284 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
286 return map
[pipe_func
];
290 translate_shadow_func(enum pipe_compare_func pipe_func
)
292 /* Gallium specifies the result of shadow comparisons as:
294 * 1 if ref <op> texel,
299 * 0 if texel <op> ref,
302 * So we need to flip the operator and also negate.
304 static const unsigned map
[] = {
305 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
306 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
307 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
308 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
309 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
310 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
311 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
312 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
314 return map
[pipe_func
];
318 translate_cull_mode(unsigned pipe_face
)
320 static const unsigned map
[4] = {
321 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
322 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
323 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
324 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
326 return map
[pipe_face
];
330 translate_fill_mode(unsigned pipe_polymode
)
332 static const unsigned map
[4] = {
333 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
334 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
335 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
336 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
338 return map
[pipe_polymode
];
342 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
344 static const unsigned map
[] = {
345 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
346 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
347 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
349 return map
[pipe_mip
];
353 translate_wrap(unsigned pipe_wrap
)
355 static const unsigned map
[] = {
356 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
357 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
358 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
359 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
360 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
361 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
363 /* These are unsupported. */
364 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
365 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
367 return map
[pipe_wrap
];
370 static struct iris_address
371 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
373 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
374 * validation list at CSO creation time, instead of draw time.
376 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
379 static struct iris_address
380 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
382 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
383 * validation list at CSO creation time, instead of draw time.
385 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
389 * Allocate space for some indirect state.
391 * Return a pointer to the map (to fill it out) and a state ref (for
392 * referring to the state in GPU commands).
395 upload_state(struct u_upload_mgr
*uploader
,
396 struct iris_state_ref
*ref
,
401 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
406 * Stream out temporary/short-lived state.
408 * This allocates space, pins the BO, and includes the BO address in the
409 * returned offset (which works because all state lives in 32-bit memory
413 stream_state(struct iris_batch
*batch
,
414 struct u_upload_mgr
*uploader
,
415 struct pipe_resource
**out_res
,
418 uint32_t *out_offset
)
422 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
424 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
425 iris_use_pinned_bo(batch
, bo
, false);
427 *out_offset
+= iris_bo_offset_from_base_address(bo
);
429 iris_record_state_size(batch
->state_sizes
, *out_offset
, size
);
435 * stream_state() + memcpy.
438 emit_state(struct iris_batch
*batch
,
439 struct u_upload_mgr
*uploader
,
440 struct pipe_resource
**out_res
,
447 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
450 memcpy(map
, data
, size
);
456 * Did field 'x' change between 'old_cso' and 'new_cso'?
458 * (If so, we may want to set some dirty flags.)
460 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
461 #define cso_changed_memcmp(x) \
462 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
465 flush_for_state_base_change(struct iris_batch
*batch
)
467 /* Flush before emitting STATE_BASE_ADDRESS.
469 * This isn't documented anywhere in the PRM. However, it seems to be
470 * necessary prior to changing the surface state base adress. We've
471 * seen issues in Vulkan where we get GPU hangs when using multi-level
472 * command buffers which clear depth, reset state base address, and then
475 * Normally, in GL, we would trust the kernel to do sufficient stalls
476 * and flushes prior to executing our batch. However, it doesn't seem
477 * as if the kernel's flushing is always sufficient and we don't want to
480 * We make this an end-of-pipe sync instead of a normal flush because we
481 * do not know the current status of the GPU. On Haswell at least,
482 * having a fast-clear operation in flight at the same time as a normal
483 * rendering operation can cause hangs. Since the kernel's flushing is
484 * insufficient, we need to ensure that any rendering operations from
485 * other processes are definitely complete before we try to do our own
486 * rendering. It's a bit of a big hammer but it appears to work.
488 iris_emit_end_of_pipe_sync(batch
,
489 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
490 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
491 PIPE_CONTROL_DATA_CACHE_FLUSH
);
495 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
497 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
498 lri
.RegisterOffset
= reg
;
502 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
505 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
507 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
508 lrr
.SourceRegisterAddress
= src
;
509 lrr
.DestinationRegisterAddress
= dst
;
514 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
516 #if GEN_GEN >= 8 && GEN_GEN < 10
517 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
519 * Software must clear the COLOR_CALC_STATE Valid field in
520 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
521 * with Pipeline Select set to GPGPU.
523 * The internal hardware docs recommend the same workaround for Gen9
526 if (pipeline
== GPGPU
)
527 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
531 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
532 * PIPELINE_SELECT [DevBWR+]":
536 * Software must ensure all the write caches are flushed through a
537 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
538 * command to invalidate read only caches prior to programming
539 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
541 iris_emit_pipe_control_flush(batch
,
542 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
543 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
544 PIPE_CONTROL_DATA_CACHE_FLUSH
|
545 PIPE_CONTROL_CS_STALL
);
547 iris_emit_pipe_control_flush(batch
,
548 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
549 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
550 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
551 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
553 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
557 sel
.PipelineSelection
= pipeline
;
562 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
567 * "This chicken bit works around a hardware issue with barrier
568 * logic encountered when switching between GPGPU and 3D pipelines.
569 * To workaround the issue, this mode bit should be set after a
570 * pipeline is selected."
573 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
574 reg
.GLKBarrierMode
= value
;
575 reg
.GLKBarrierModeMask
= 1;
577 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
582 init_state_base_address(struct iris_batch
*batch
)
584 flush_for_state_base_change(batch
);
586 /* We program most base addresses once at context initialization time.
587 * Each base address points at a 4GB memory zone, and never needs to
588 * change. See iris_bufmgr.h for a description of the memory zones.
590 * The one exception is Surface State Base Address, which needs to be
591 * updated occasionally. See iris_binder.c for the details there.
593 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
594 sba
.GeneralStateMOCS
= MOCS_WB
;
595 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
596 sba
.DynamicStateMOCS
= MOCS_WB
;
597 sba
.IndirectObjectMOCS
= MOCS_WB
;
598 sba
.InstructionMOCS
= MOCS_WB
;
600 sba
.GeneralStateBaseAddressModifyEnable
= true;
601 sba
.DynamicStateBaseAddressModifyEnable
= true;
602 sba
.IndirectObjectBaseAddressModifyEnable
= true;
603 sba
.InstructionBaseAddressModifyEnable
= true;
604 sba
.GeneralStateBufferSizeModifyEnable
= true;
605 sba
.DynamicStateBufferSizeModifyEnable
= true;
607 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
608 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
610 sba
.IndirectObjectBufferSizeModifyEnable
= true;
611 sba
.InstructionBuffersizeModifyEnable
= true;
613 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
614 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
616 sba
.GeneralStateBufferSize
= 0xfffff;
617 sba
.IndirectObjectBufferSize
= 0xfffff;
618 sba
.InstructionBufferSize
= 0xfffff;
619 sba
.DynamicStateBufferSize
= 0xfffff;
624 iris_emit_l3_config(struct iris_batch
*batch
, const struct gen_l3_config
*cfg
,
625 bool has_slm
, bool wants_dc_cache
)
628 iris_pack_state(GENX(L3CNTLREG
), ®_val
, reg
) {
629 reg
.SLMEnable
= has_slm
;
631 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
632 * in L3CNTLREG register. The default setting of the bit is not the
633 * desirable behavior.
635 reg
.ErrorDetectionBehaviorControl
= true;
636 reg
.UseFullWays
= true;
638 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
639 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
640 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
641 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
643 iris_emit_lri(batch
, L3CNTLREG
, reg_val
);
647 iris_emit_default_l3_config(struct iris_batch
*batch
,
648 const struct gen_device_info
*devinfo
,
651 bool wants_dc_cache
= true;
652 bool has_slm
= compute
;
653 const struct gen_l3_weights w
=
654 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
655 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
656 iris_emit_l3_config(batch
, cfg
, has_slm
, wants_dc_cache
);
659 #if GEN_GEN == 9 || GEN_GEN == 10
661 iris_enable_obj_preemption(struct iris_batch
*batch
, bool enable
)
665 /* A fixed function pipe flush is required before modifying this field */
666 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
668 /* enable object level preemption */
669 iris_pack_state(GENX(CS_CHICKEN1
), ®_val
, reg
) {
670 reg
.ReplayMode
= enable
;
671 reg
.ReplayModeMask
= true;
673 iris_emit_lri(batch
, CS_CHICKEN1
, reg_val
);
678 * Upload the initial GPU state for a render context.
680 * This sets some invariant state that needs to be programmed a particular
681 * way, but we never actually change.
684 iris_init_render_context(struct iris_screen
*screen
,
685 struct iris_batch
*batch
,
686 struct iris_vtable
*vtbl
,
687 struct pipe_debug_callback
*dbg
)
689 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
692 emit_pipeline_select(batch
, _3D
);
694 iris_emit_default_l3_config(batch
, devinfo
, false);
696 init_state_base_address(batch
);
699 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
700 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
701 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
703 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
705 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
706 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
707 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
709 iris_emit_lri(batch
, INSTPM
, reg_val
);
713 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
714 reg
.FloatBlendOptimizationEnable
= true;
715 reg
.FloatBlendOptimizationEnableMask
= true;
716 reg
.PartialResolveDisableInVC
= true;
717 reg
.PartialResolveDisableInVCMask
= true;
719 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
721 if (devinfo
->is_geminilake
)
722 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
726 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
727 reg
.HeaderlessMessageforPreemptableContexts
= 1;
728 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
730 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
732 /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
733 iris_pack_state(GENX(HALF_SLICE_CHICKEN7
), ®_val
, reg
) {
734 reg
.EnabledTexelOffsetPrecisionFix
= 1;
735 reg
.EnabledTexelOffsetPrecisionFixMask
= 1;
737 iris_emit_lri(batch
, HALF_SLICE_CHICKEN7
, reg_val
);
739 /* WA_2204188704: Pixel Shader Panic dispatch must be disabled. */
740 iris_pack_state(GENX(COMMON_SLICE_CHICKEN3
), ®_val
, reg
) {
741 reg
.PSThreadPanicDispatch
= 0x3;
742 reg
.PSThreadPanicDispatchMask
= 0x3;
744 iris_emit_lri(batch
, COMMON_SLICE_CHICKEN3
, reg_val
);
746 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
747 reg
.StateCacheRedirectToCSSectionEnable
= true;
748 reg
.StateCacheRedirectToCSSectionEnableMask
= true;
750 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
756 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
757 * changing it dynamically. We set it to the maximum size here, and
758 * instead include the render target dimensions in the viewport, so
759 * viewport extents clipping takes care of pruning stray geometry.
761 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
762 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
763 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
766 /* Set the initial MSAA sample positions. */
767 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
768 GEN_SAMPLE_POS_1X(pat
._1xSample
);
769 GEN_SAMPLE_POS_2X(pat
._2xSample
);
770 GEN_SAMPLE_POS_4X(pat
._4xSample
);
771 GEN_SAMPLE_POS_8X(pat
._8xSample
);
773 GEN_SAMPLE_POS_16X(pat
._16xSample
);
777 /* Use the legacy AA line coverage computation. */
778 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
780 /* Disable chromakeying (it's for media) */
781 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
783 /* We want regular rendering, not special HiZ operations. */
784 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
786 /* No polygon stippling offsets are necessary. */
787 /* TODO: may need to set an offset for origin-UL framebuffers */
788 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
790 /* Set a static partitioning of the push constant area. */
791 /* TODO: this may be a bad idea...could starve the push ringbuffers... */
792 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
793 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
794 alloc
._3DCommandSubOpcode
= 18 + i
;
795 alloc
.ConstantBufferOffset
= 6 * i
;
796 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
801 /* Gen11+ is enabled for us by the kernel. */
802 iris_enable_obj_preemption(batch
, true);
807 iris_init_compute_context(struct iris_screen
*screen
,
808 struct iris_batch
*batch
,
809 struct iris_vtable
*vtbl
,
810 struct pipe_debug_callback
*dbg
)
812 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
814 emit_pipeline_select(batch
, GPGPU
);
816 iris_emit_default_l3_config(batch
, devinfo
, true);
818 init_state_base_address(batch
);
821 if (devinfo
->is_geminilake
)
822 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
826 struct iris_vertex_buffer_state
{
827 /** The VERTEX_BUFFER_STATE hardware structure. */
828 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
830 /** The resource to source vertex data from. */
831 struct pipe_resource
*resource
;
834 struct iris_depth_buffer_state
{
835 /* Depth/HiZ/Stencil related hardware packets. */
836 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
837 GENX(3DSTATE_STENCIL_BUFFER_length
) +
838 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
839 GENX(3DSTATE_CLEAR_PARAMS_length
)];
843 * Generation-specific context state (ice->state.genx->...).
845 * Most state can go in iris_context directly, but these encode hardware
846 * packets which vary by generation.
848 struct iris_genx_state
{
849 struct iris_vertex_buffer_state vertex_buffers
[33];
851 struct iris_depth_buffer_state depth_buffer
;
853 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
856 /* Is object level preemption enabled? */
857 bool object_preemption
;
862 struct brw_image_param image_param
[PIPE_MAX_SHADER_IMAGES
];
864 } shaders
[MESA_SHADER_STAGES
];
868 * The pipe->set_blend_color() driver hook.
870 * This corresponds to our COLOR_CALC_STATE.
873 iris_set_blend_color(struct pipe_context
*ctx
,
874 const struct pipe_blend_color
*state
)
876 struct iris_context
*ice
= (struct iris_context
*) ctx
;
878 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
879 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
880 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
884 * Gallium CSO for blend state (see pipe_blend_state).
886 struct iris_blend_state
{
887 /** Partial 3DSTATE_PS_BLEND */
888 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
890 /** Partial BLEND_STATE */
891 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
892 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
894 bool alpha_to_coverage
; /* for shader key */
896 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
897 uint8_t blend_enables
;
899 /** Bitfield of whether color writes are enabled for RT[i] */
900 uint8_t color_write_enables
;
902 /** Does RT[0] use dual color blending? */
903 bool dual_color_blending
;
906 static enum pipe_blendfactor
907 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
910 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
911 return PIPE_BLENDFACTOR_ONE
;
913 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
914 return PIPE_BLENDFACTOR_ZERO
;
921 * The pipe->create_blend_state() driver hook.
923 * Translates a pipe_blend_state into iris_blend_state.
926 iris_create_blend_state(struct pipe_context
*ctx
,
927 const struct pipe_blend_state
*state
)
929 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
930 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
932 cso
->blend_enables
= 0;
933 cso
->color_write_enables
= 0;
934 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
936 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
938 bool indep_alpha_blend
= false;
940 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
941 const struct pipe_rt_blend_state
*rt
=
942 &state
->rt
[state
->independent_blend_enable
? i
: 0];
944 enum pipe_blendfactor src_rgb
=
945 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
946 enum pipe_blendfactor src_alpha
=
947 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
948 enum pipe_blendfactor dst_rgb
=
949 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
950 enum pipe_blendfactor dst_alpha
=
951 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
953 if (rt
->rgb_func
!= rt
->alpha_func
||
954 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
955 indep_alpha_blend
= true;
957 if (rt
->blend_enable
)
958 cso
->blend_enables
|= 1u << i
;
961 cso
->color_write_enables
|= 1u << i
;
963 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
964 be
.LogicOpEnable
= state
->logicop_enable
;
965 be
.LogicOpFunction
= state
->logicop_func
;
967 be
.PreBlendSourceOnlyClampEnable
= false;
968 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
969 be
.PreBlendColorClampEnable
= true;
970 be
.PostBlendColorClampEnable
= true;
972 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
974 be
.ColorBlendFunction
= rt
->rgb_func
;
975 be
.AlphaBlendFunction
= rt
->alpha_func
;
976 be
.SourceBlendFactor
= src_rgb
;
977 be
.SourceAlphaBlendFactor
= src_alpha
;
978 be
.DestinationBlendFactor
= dst_rgb
;
979 be
.DestinationAlphaBlendFactor
= dst_alpha
;
981 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
982 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
983 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
984 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
986 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
989 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
990 /* pb.HasWriteableRT is filled in at draw time.
991 * pb.AlphaTestEnable is filled in at draw time.
993 * pb.ColorBufferBlendEnable is filled in at draw time so we can avoid
994 * setting it when dual color blending without an appropriate shader.
997 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
998 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1000 pb
.SourceBlendFactor
=
1001 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
1002 pb
.SourceAlphaBlendFactor
=
1003 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
1004 pb
.DestinationBlendFactor
=
1005 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
1006 pb
.DestinationAlphaBlendFactor
=
1007 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
1010 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
1011 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1012 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1013 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
1014 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
1015 bs
.ColorDitherEnable
= state
->dither
;
1016 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
1019 cso
->dual_color_blending
= util_blend_state_is_dual(state
, 0);
1025 * The pipe->bind_blend_state() driver hook.
1027 * Bind a blending CSO and flag related dirty bits.
1030 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
1032 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1033 struct iris_blend_state
*cso
= state
;
1035 ice
->state
.cso_blend
= cso
;
1036 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
1038 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1039 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1040 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1041 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
1045 * Return true if the FS writes to any color outputs which are not disabled
1046 * via color masking.
1049 has_writeable_rt(const struct iris_blend_state
*cso_blend
,
1050 const struct shader_info
*fs_info
)
1055 unsigned rt_outputs
= fs_info
->outputs_written
>> FRAG_RESULT_DATA0
;
1057 if (fs_info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
))
1058 rt_outputs
= (1 << BRW_MAX_DRAW_BUFFERS
) - 1;
1060 return cso_blend
->color_write_enables
& rt_outputs
;
1064 * Gallium CSO for depth, stencil, and alpha testing state.
1066 struct iris_depth_stencil_alpha_state
{
1067 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
1068 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1070 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
1071 struct pipe_alpha_state alpha
;
1073 /** Outbound to resolve and cache set tracking. */
1074 bool depth_writes_enabled
;
1075 bool stencil_writes_enabled
;
1079 * The pipe->create_depth_stencil_alpha_state() driver hook.
1081 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
1082 * testing state since we need pieces of it in a variety of places.
1085 iris_create_zsa_state(struct pipe_context
*ctx
,
1086 const struct pipe_depth_stencil_alpha_state
*state
)
1088 struct iris_depth_stencil_alpha_state
*cso
=
1089 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
1091 bool two_sided_stencil
= state
->stencil
[1].enabled
;
1093 cso
->alpha
= state
->alpha
;
1094 cso
->depth_writes_enabled
= state
->depth
.writemask
;
1095 cso
->stencil_writes_enabled
=
1096 state
->stencil
[0].writemask
!= 0 ||
1097 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1099 /* The state tracker needs to optimize away EQUAL writes for us. */
1100 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
1102 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
1103 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1104 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1105 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1106 wmds
.StencilTestFunction
=
1107 translate_compare_func(state
->stencil
[0].func
);
1108 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1109 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1110 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1111 wmds
.BackfaceStencilTestFunction
=
1112 translate_compare_func(state
->stencil
[1].func
);
1113 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1114 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1115 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1116 wmds
.StencilBufferWriteEnable
=
1117 state
->stencil
[0].writemask
!= 0 ||
1118 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1119 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1120 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1121 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1122 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1123 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1124 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1125 /* wmds.[Backface]StencilReferenceValue are merged later */
1132 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1134 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1137 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1139 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1140 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1141 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1144 if (cso_changed(alpha
.ref_value
))
1145 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1147 if (cso_changed(alpha
.enabled
))
1148 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1150 if (cso_changed(alpha
.func
))
1151 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1153 if (cso_changed(depth_writes_enabled
))
1154 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1156 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1157 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1160 ice
->state
.cso_zsa
= new_cso
;
1161 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1162 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1163 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1167 * Gallium CSO for rasterizer state.
1169 struct iris_rasterizer_state
{
1170 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1171 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1172 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1173 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1174 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1176 uint8_t num_clip_plane_consts
;
1177 bool clip_halfz
; /* for CC_VIEWPORT */
1178 bool depth_clip_near
; /* for CC_VIEWPORT */
1179 bool depth_clip_far
; /* for CC_VIEWPORT */
1180 bool flatshade
; /* for shader state */
1181 bool flatshade_first
; /* for stream output */
1182 bool clamp_fragment_color
; /* for shader state */
1183 bool light_twoside
; /* for shader state */
1184 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1185 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1186 bool line_stipple_enable
;
1187 bool poly_stipple_enable
;
1189 bool force_persample_interp
;
1190 bool conservative_rasterization
;
1191 bool fill_mode_point_or_line
;
1192 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1193 uint16_t sprite_coord_enable
;
1197 get_line_width(const struct pipe_rasterizer_state
*state
)
1199 float line_width
= state
->line_width
;
1201 /* From the OpenGL 4.4 spec:
1203 * "The actual width of non-antialiased lines is determined by rounding
1204 * the supplied width to the nearest integer, then clamping it to the
1205 * implementation-dependent maximum non-antialiased line width."
1207 if (!state
->multisample
&& !state
->line_smooth
)
1208 line_width
= roundf(state
->line_width
);
1210 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1211 /* For 1 pixel line thickness or less, the general anti-aliasing
1212 * algorithm gives up, and a garbage line is generated. Setting a
1213 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1214 * (one-pixel-wide), non-antialiased lines.
1216 * Lines rendered with zero Line Width are rasterized using the
1217 * "Grid Intersection Quantization" rules as specified by the
1218 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1227 * The pipe->create_rasterizer_state() driver hook.
1230 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1231 const struct pipe_rasterizer_state
*state
)
1233 struct iris_rasterizer_state
*cso
=
1234 malloc(sizeof(struct iris_rasterizer_state
));
1236 cso
->multisample
= state
->multisample
;
1237 cso
->force_persample_interp
= state
->force_persample_interp
;
1238 cso
->clip_halfz
= state
->clip_halfz
;
1239 cso
->depth_clip_near
= state
->depth_clip_near
;
1240 cso
->depth_clip_far
= state
->depth_clip_far
;
1241 cso
->flatshade
= state
->flatshade
;
1242 cso
->flatshade_first
= state
->flatshade_first
;
1243 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1244 cso
->light_twoside
= state
->light_twoside
;
1245 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1246 cso
->half_pixel_center
= state
->half_pixel_center
;
1247 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1248 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1249 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1250 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1251 cso
->conservative_rasterization
=
1252 state
->conservative_raster_mode
== PIPE_CONSERVATIVE_RASTER_POST_SNAP
;
1254 cso
->fill_mode_point_or_line
=
1255 state
->fill_front
== PIPE_POLYGON_MODE_LINE
||
1256 state
->fill_front
== PIPE_POLYGON_MODE_POINT
||
1257 state
->fill_back
== PIPE_POLYGON_MODE_LINE
||
1258 state
->fill_back
== PIPE_POLYGON_MODE_POINT
;
1260 if (state
->clip_plane_enable
!= 0)
1261 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1263 cso
->num_clip_plane_consts
= 0;
1265 float line_width
= get_line_width(state
);
1267 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1268 sf
.StatisticsEnable
= true;
1269 sf
.ViewportTransformEnable
= true;
1270 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1271 sf
.LineEndCapAntialiasingRegionWidth
=
1272 state
->line_smooth
? _10pixels
: _05pixels
;
1273 sf
.LastPixelEnable
= state
->line_last_pixel
;
1274 sf
.LineWidth
= line_width
;
1275 sf
.SmoothPointEnable
= (state
->point_smooth
|| state
->multisample
) &&
1276 !state
->point_quad_rasterization
;
1277 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1278 sf
.PointWidth
= state
->point_size
;
1280 if (state
->flatshade_first
) {
1281 sf
.TriangleFanProvokingVertexSelect
= 1;
1283 sf
.TriangleStripListProvokingVertexSelect
= 2;
1284 sf
.TriangleFanProvokingVertexSelect
= 2;
1285 sf
.LineStripListProvokingVertexSelect
= 1;
1289 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1290 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1291 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1292 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1293 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1294 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1295 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1296 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1297 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1298 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1299 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1300 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1301 rr
.SmoothPointEnable
= state
->point_smooth
;
1302 rr
.AntialiasingEnable
= state
->line_smooth
;
1303 rr
.ScissorRectangleEnable
= state
->scissor
;
1305 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1306 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1307 rr
.ConservativeRasterizationEnable
=
1308 cso
->conservative_rasterization
;
1310 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1314 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1315 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1316 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1318 cl
.EarlyCullEnable
= true;
1319 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1320 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1321 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1322 cl
.GuardbandClipTestEnable
= true;
1323 cl
.ClipEnable
= true;
1324 cl
.MinimumPointWidth
= 0.125;
1325 cl
.MaximumPointWidth
= 255.875;
1327 if (state
->flatshade_first
) {
1328 cl
.TriangleFanProvokingVertexSelect
= 1;
1330 cl
.TriangleStripListProvokingVertexSelect
= 2;
1331 cl
.TriangleFanProvokingVertexSelect
= 2;
1332 cl
.LineStripListProvokingVertexSelect
= 1;
1336 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1337 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1338 * filled in at draw time from the FS program.
1340 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1341 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1342 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1343 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1344 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1347 /* Remap from 0..255 back to 1..256 */
1348 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1350 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1351 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1352 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1353 line
.LineStippleRepeatCount
= line_stipple_factor
;
1360 * The pipe->bind_rasterizer_state() driver hook.
1362 * Bind a rasterizer CSO and flag related dirty bits.
1365 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1367 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1368 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1369 struct iris_rasterizer_state
*new_cso
= state
;
1372 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1373 if (cso_changed_memcmp(line_stipple
))
1374 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1376 if (cso_changed(half_pixel_center
))
1377 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1379 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1380 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1382 if (cso_changed(rasterizer_discard
))
1383 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1385 if (cso_changed(flatshade_first
))
1386 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1388 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1389 cso_changed(clip_halfz
))
1390 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1392 if (cso_changed(sprite_coord_enable
) ||
1393 cso_changed(sprite_coord_mode
) ||
1394 cso_changed(light_twoside
))
1395 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1397 if (cso_changed(conservative_rasterization
))
1398 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
1401 ice
->state
.cso_rast
= new_cso
;
1402 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1403 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1404 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1408 * Return true if the given wrap mode requires the border color to exist.
1410 * (We can skip uploading it if the sampler isn't going to use it.)
1413 wrap_mode_needs_border_color(unsigned wrap_mode
)
1415 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1419 * Gallium CSO for sampler state.
1421 struct iris_sampler_state
{
1422 union pipe_color_union border_color
;
1423 bool needs_border_color
;
1425 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1429 * The pipe->create_sampler_state() driver hook.
1431 * We fill out SAMPLER_STATE (except for the border color pointer), and
1432 * store that on the CPU. It doesn't make sense to upload it to a GPU
1433 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1434 * all bound sampler states to be in contiguous memor.
1437 iris_create_sampler_state(struct pipe_context
*ctx
,
1438 const struct pipe_sampler_state
*state
)
1440 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1445 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1446 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1448 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1449 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1450 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1452 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1454 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1455 wrap_mode_needs_border_color(wrap_t
) ||
1456 wrap_mode_needs_border_color(wrap_r
);
1458 float min_lod
= state
->min_lod
;
1459 unsigned mag_img_filter
= state
->mag_img_filter
;
1461 // XXX: explain this code ported from ilo...I don't get it at all...
1462 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1463 state
->min_lod
> 0.0f
) {
1465 mag_img_filter
= state
->min_img_filter
;
1468 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1469 samp
.TCXAddressControlMode
= wrap_s
;
1470 samp
.TCYAddressControlMode
= wrap_t
;
1471 samp
.TCZAddressControlMode
= wrap_r
;
1472 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1473 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1474 samp
.MinModeFilter
= state
->min_img_filter
;
1475 samp
.MagModeFilter
= mag_img_filter
;
1476 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1477 samp
.MaximumAnisotropy
= RATIO21
;
1479 if (state
->max_anisotropy
>= 2) {
1480 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1481 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1482 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1485 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1486 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1488 samp
.MaximumAnisotropy
=
1489 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1492 /* Set address rounding bits if not using nearest filtering. */
1493 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1494 samp
.UAddressMinFilterRoundingEnable
= true;
1495 samp
.VAddressMinFilterRoundingEnable
= true;
1496 samp
.RAddressMinFilterRoundingEnable
= true;
1499 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1500 samp
.UAddressMagFilterRoundingEnable
= true;
1501 samp
.VAddressMagFilterRoundingEnable
= true;
1502 samp
.RAddressMagFilterRoundingEnable
= true;
1505 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1506 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1508 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1510 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1511 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1512 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1513 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1515 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1522 * The pipe->bind_sampler_states() driver hook.
1525 iris_bind_sampler_states(struct pipe_context
*ctx
,
1526 enum pipe_shader_type p_stage
,
1527 unsigned start
, unsigned count
,
1530 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1531 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1532 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1534 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1536 for (int i
= 0; i
< count
; i
++) {
1537 shs
->samplers
[start
+ i
] = states
[i
];
1540 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1544 * Upload the sampler states into a contiguous area of GPU memory, for
1545 * for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1547 * Also fill out the border color state pointers.
1550 iris_upload_sampler_states(struct iris_context
*ice
, gl_shader_stage stage
)
1552 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1553 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
1555 /* We assume the state tracker will call pipe->bind_sampler_states()
1556 * if the program's number of textures changes.
1558 unsigned count
= info
? util_last_bit(info
->textures_used
) : 0;
1563 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1564 * in the dynamic state memory zone, so we can point to it via the
1565 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1567 unsigned size
= count
* 4 * GENX(SAMPLER_STATE_length
);
1569 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
, size
, 32);
1573 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1574 shs
->sampler_table
.offset
+=
1575 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1577 iris_record_state_size(ice
->state
.sizes
, shs
->sampler_table
.offset
, size
);
1579 /* Make sure all land in the same BO */
1580 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1582 ice
->state
.need_border_colors
&= ~(1 << stage
);
1584 for (int i
= 0; i
< count
; i
++) {
1585 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1586 struct iris_sampler_view
*tex
= shs
->textures
[i
];
1589 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1590 } else if (!state
->needs_border_color
) {
1591 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1593 ice
->state
.need_border_colors
|= 1 << stage
;
1595 /* We may need to swizzle the border color for format faking.
1596 * A/LA formats are faked as R/RG with 000R or R00G swizzles.
1597 * This means we need to move the border color's A channel into
1598 * the R or G channels so that those read swizzles will move it
1601 union pipe_color_union
*color
= &state
->border_color
;
1602 union pipe_color_union tmp
;
1604 enum pipe_format internal_format
= tex
->res
->internal_format
;
1606 if (util_format_is_alpha(internal_format
)) {
1607 unsigned char swz
[4] = {
1608 PIPE_SWIZZLE_W
, PIPE_SWIZZLE_0
,
1609 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1611 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1613 } else if (util_format_is_luminance_alpha(internal_format
) &&
1614 internal_format
!= PIPE_FORMAT_L8A8_SRGB
) {
1615 unsigned char swz
[4] = {
1616 PIPE_SWIZZLE_X
, PIPE_SWIZZLE_W
,
1617 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1619 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1624 /* Stream out the border color and merge the pointer. */
1625 uint32_t offset
= iris_upload_border_color(ice
, color
);
1627 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1628 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1629 dyns
.BorderColorPointer
= offset
;
1632 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1633 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1636 map
+= GENX(SAMPLER_STATE_length
);
1640 static enum isl_channel_select
1641 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1644 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1645 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1646 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1647 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1648 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1649 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1650 default: unreachable("invalid swizzle");
1655 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1656 struct iris_resource
*res
,
1658 enum isl_format format
,
1659 struct isl_swizzle swizzle
,
1663 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1664 const unsigned cpp
= format
== ISL_FORMAT_RAW
? 1 : fmtl
->bpb
/ 8;
1666 /* The ARB_texture_buffer_specification says:
1668 * "The number of texels in the buffer texture's texel array is given by
1670 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1672 * where <buffer_size> is the size of the buffer object, in basic
1673 * machine units and <components> and <base_type> are the element count
1674 * and base data type for elements, as specified in Table X.1. The
1675 * number of texels in the texel array is then clamped to the
1676 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1678 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1679 * so that when ISL divides by stride to obtain the number of texels, that
1680 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1682 unsigned final_size
=
1683 MIN3(size
, res
->bo
->size
- res
->offset
- offset
,
1684 IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1686 isl_buffer_fill_state(isl_dev
, map
,
1687 .address
= res
->bo
->gtt_offset
+ res
->offset
+ offset
,
1688 .size_B
= final_size
,
1692 .mocs
= mocs(res
->bo
));
1695 #define SURFACE_STATE_ALIGNMENT 64
1698 * Allocate several contiguous SURFACE_STATE structures, one for each
1699 * supported auxiliary surface mode.
1702 alloc_surface_states(struct u_upload_mgr
*mgr
,
1703 struct iris_state_ref
*ref
,
1704 unsigned aux_usages
)
1706 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
1708 /* If this changes, update this to explicitly align pointers */
1709 STATIC_ASSERT(surf_size
== SURFACE_STATE_ALIGNMENT
);
1711 assert(aux_usages
!= 0);
1714 upload_state(mgr
, ref
, util_bitcount(aux_usages
) * surf_size
,
1715 SURFACE_STATE_ALIGNMENT
);
1717 ref
->offset
+= iris_bo_offset_from_base_address(iris_resource_bo(ref
->res
));
1723 fill_surface_state(struct isl_device
*isl_dev
,
1725 struct iris_resource
*res
,
1726 struct isl_view
*view
,
1729 struct isl_surf_fill_state_info f
= {
1732 .mocs
= mocs(res
->bo
),
1733 .address
= res
->bo
->gtt_offset
+ res
->offset
,
1736 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1737 f
.aux_surf
= &res
->aux
.surf
;
1738 f
.aux_usage
= aux_usage
;
1739 f
.aux_address
= res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
;
1741 struct iris_bo
*clear_bo
= NULL
;
1742 uint64_t clear_offset
= 0;
1744 iris_resource_get_clear_color(res
, &clear_bo
, &clear_offset
);
1746 f
.clear_address
= clear_bo
->gtt_offset
+ clear_offset
;
1747 f
.use_clear_address
= isl_dev
->info
->gen
> 9;
1751 isl_surf_fill_state_s(isl_dev
, map
, &f
);
1755 * The pipe->create_sampler_view() driver hook.
1757 static struct pipe_sampler_view
*
1758 iris_create_sampler_view(struct pipe_context
*ctx
,
1759 struct pipe_resource
*tex
,
1760 const struct pipe_sampler_view
*tmpl
)
1762 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1763 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1764 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1765 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1770 /* initialize base object */
1772 isv
->base
.context
= ctx
;
1773 isv
->base
.texture
= NULL
;
1774 pipe_reference_init(&isv
->base
.reference
, 1);
1775 pipe_resource_reference(&isv
->base
.texture
, tex
);
1777 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1778 struct iris_resource
*zres
, *sres
;
1779 const struct util_format_description
*desc
=
1780 util_format_description(tmpl
->format
);
1782 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1784 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1787 isv
->res
= (struct iris_resource
*) tex
;
1789 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1790 &isv
->surface_state
,
1791 isv
->res
->aux
.sampler_usages
);
1795 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1797 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1798 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1799 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1801 const struct iris_format_info fmt
=
1802 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1804 isv
->clear_color
= isv
->res
->aux
.clear_color
;
1806 isv
->view
= (struct isl_view
) {
1808 .swizzle
= (struct isl_swizzle
) {
1809 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1810 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1811 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1812 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1817 /* Fill out SURFACE_STATE for this view. */
1818 if (tmpl
->target
!= PIPE_BUFFER
) {
1819 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1820 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1821 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1822 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1823 isv
->view
.array_len
=
1824 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1826 unsigned aux_modes
= isv
->res
->aux
.sampler_usages
;
1828 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1830 /* If we have a multisampled depth buffer, do not create a sampler
1831 * surface state with HiZ.
1833 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->view
,
1836 map
+= SURFACE_STATE_ALIGNMENT
;
1839 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
1840 isv
->view
.format
, isv
->view
.swizzle
,
1841 tmpl
->u
.buf
.offset
, tmpl
->u
.buf
.size
);
1848 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1849 struct pipe_sampler_view
*state
)
1851 struct iris_sampler_view
*isv
= (void *) state
;
1852 pipe_resource_reference(&state
->texture
, NULL
);
1853 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1858 * The pipe->create_surface() driver hook.
1860 * In Gallium nomenclature, "surfaces" are a view of a resource that
1861 * can be bound as a render target or depth/stencil buffer.
1863 static struct pipe_surface
*
1864 iris_create_surface(struct pipe_context
*ctx
,
1865 struct pipe_resource
*tex
,
1866 const struct pipe_surface
*tmpl
)
1868 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1869 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1870 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1871 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1872 struct pipe_surface
*psurf
= &surf
->base
;
1873 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1878 pipe_reference_init(&psurf
->reference
, 1);
1879 pipe_resource_reference(&psurf
->texture
, tex
);
1880 psurf
->context
= ctx
;
1881 psurf
->format
= tmpl
->format
;
1882 psurf
->width
= tex
->width0
;
1883 psurf
->height
= tex
->height0
;
1884 psurf
->texture
= tex
;
1885 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1886 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1887 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1889 isl_surf_usage_flags_t usage
= 0;
1891 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1892 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1893 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1895 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1897 const struct iris_format_info fmt
=
1898 iris_format_for_usage(devinfo
, psurf
->format
, usage
);
1900 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1901 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1902 /* Framebuffer validation will reject this invalid case, but it
1903 * hasn't had the opportunity yet. In the meantime, we need to
1904 * avoid hitting ISL asserts about unsupported formats below.
1910 struct isl_view
*view
= &surf
->view
;
1911 *view
= (struct isl_view
) {
1913 .base_level
= tmpl
->u
.tex
.level
,
1915 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1916 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1917 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1921 surf
->clear_color
= res
->aux
.clear_color
;
1923 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1924 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1925 ISL_SURF_USAGE_STENCIL_BIT
))
1929 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1930 &surf
->surface_state
,
1931 res
->aux
.possible_usages
);
1935 if (!isl_format_is_compressed(res
->surf
.format
)) {
1936 /* This is a normal surface. Fill out a SURFACE_STATE for each possible
1937 * auxiliary surface mode and return the pipe_surface.
1939 unsigned aux_modes
= res
->aux
.possible_usages
;
1941 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1943 fill_surface_state(&screen
->isl_dev
, map
, res
, view
, aux_usage
);
1945 map
+= SURFACE_STATE_ALIGNMENT
;
1951 /* The resource has a compressed format, which is not renderable, but we
1952 * have a renderable view format. We must be attempting to upload blocks
1953 * of compressed data via an uncompressed view.
1955 * In this case, we can assume there are no auxiliary buffers, a single
1956 * miplevel, and that the resource is single-sampled. Gallium may try
1957 * and create an uncompressed view with multiple layers, however.
1959 assert(!isl_format_is_compressed(fmt
.fmt
));
1960 assert(res
->aux
.possible_usages
== 1 << ISL_AUX_USAGE_NONE
);
1961 assert(res
->surf
.samples
== 1);
1962 assert(view
->levels
== 1);
1964 struct isl_surf isl_surf
;
1965 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
1967 if (view
->base_level
> 0) {
1968 /* We can't rely on the hardware's miplevel selection with such
1969 * a substantial lie about the format, so we select a single image
1970 * using the Tile X/Y Offset fields. In this case, we can't handle
1971 * multiple array slices.
1973 * On Broadwell, HALIGN and VALIGN are specified in pixels and are
1974 * hard-coded to align to exactly the block size of the compressed
1975 * texture. This means that, when reinterpreted as a non-compressed
1976 * texture, the tile offsets may be anything and we can't rely on
1979 * Return NULL to force the state tracker to take fallback paths.
1981 if (view
->array_len
> 1 || GEN_GEN
== 8)
1984 const bool is_3d
= res
->surf
.dim
== ISL_SURF_DIM_3D
;
1985 isl_surf_get_image_surf(&screen
->isl_dev
, &res
->surf
,
1987 is_3d
? 0 : view
->base_array_layer
,
1988 is_3d
? view
->base_array_layer
: 0,
1990 &offset_B
, &tile_x_sa
, &tile_y_sa
);
1992 /* We use address and tile offsets to access a single level/layer
1993 * as a subimage, so reset level/layer so it doesn't offset again.
1995 view
->base_array_layer
= 0;
1996 view
->base_level
= 0;
1998 /* Level 0 doesn't require tile offsets, and the hardware can find
1999 * array slices using QPitch even with the format override, so we
2000 * can allow layers in this case. Copy the original ISL surface.
2002 memcpy(&isl_surf
, &res
->surf
, sizeof(isl_surf
));
2005 /* Scale down the image dimensions by the block size. */
2006 const struct isl_format_layout
*fmtl
=
2007 isl_format_get_layout(res
->surf
.format
);
2008 isl_surf
.format
= fmt
.fmt
;
2009 isl_surf
.logical_level0_px
.width
=
2010 DIV_ROUND_UP(isl_surf
.logical_level0_px
.width
, fmtl
->bw
);
2011 isl_surf
.logical_level0_px
.height
=
2012 DIV_ROUND_UP(isl_surf
.logical_level0_px
.height
, fmtl
->bh
);
2013 isl_surf
.phys_level0_sa
.width
/= fmtl
->bw
;
2014 isl_surf
.phys_level0_sa
.height
/= fmtl
->bh
;
2015 tile_x_sa
/= fmtl
->bw
;
2016 tile_y_sa
/= fmtl
->bh
;
2018 psurf
->width
= isl_surf
.logical_level0_px
.width
;
2019 psurf
->height
= isl_surf
.logical_level0_px
.height
;
2021 struct isl_surf_fill_state_info f
= {
2024 .mocs
= mocs(res
->bo
),
2025 .address
= res
->bo
->gtt_offset
+ offset_B
,
2026 .x_offset_sa
= tile_x_sa
,
2027 .y_offset_sa
= tile_y_sa
,
2030 isl_surf_fill_state_s(&screen
->isl_dev
, map
, &f
);
2036 fill_default_image_param(struct brw_image_param
*param
)
2038 memset(param
, 0, sizeof(*param
));
2039 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
2040 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
2041 * detailed explanation of these parameters.
2043 param
->swizzling
[0] = 0xff;
2044 param
->swizzling
[1] = 0xff;
2048 fill_buffer_image_param(struct brw_image_param
*param
,
2049 enum pipe_format pfmt
,
2052 const unsigned cpp
= util_format_get_blocksize(pfmt
);
2054 fill_default_image_param(param
);
2055 param
->size
[0] = size
/ cpp
;
2056 param
->stride
[0] = cpp
;
2059 #define isl_surf_fill_image_param(x, ...)
2060 #define fill_default_image_param(x, ...)
2061 #define fill_buffer_image_param(x, ...)
2065 * The pipe->set_shader_images() driver hook.
2068 iris_set_shader_images(struct pipe_context
*ctx
,
2069 enum pipe_shader_type p_stage
,
2070 unsigned start_slot
, unsigned count
,
2071 const struct pipe_image_view
*p_images
)
2073 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2074 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2075 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2076 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2077 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2079 struct iris_genx_state
*genx
= ice
->state
.genx
;
2080 struct brw_image_param
*image_params
= genx
->shaders
[stage
].image_param
;
2083 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
2085 for (unsigned i
= 0; i
< count
; i
++) {
2086 struct iris_image_view
*iv
= &shs
->image
[start_slot
+ i
];
2088 if (p_images
&& p_images
[i
].resource
) {
2089 const struct pipe_image_view
*img
= &p_images
[i
];
2090 struct iris_resource
*res
= (void *) img
->resource
;
2092 // XXX: these are not retained forever, use a separate uploader?
2094 alloc_surface_states(ice
->state
.surface_uploader
,
2095 &iv
->surface_state
, 1 << ISL_AUX_USAGE_NONE
);
2100 iv
->base
.resource
= NULL
;
2101 pipe_resource_reference(&iv
->base
.resource
, &res
->base
);
2103 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
2105 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
2107 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
2108 enum isl_format isl_fmt
=
2109 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
2111 bool untyped_fallback
= false;
2113 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
2114 /* On Gen8, try to use typed surfaces reads (which support a
2115 * limited number of formats), and if not possible, fall back
2118 untyped_fallback
= GEN_GEN
== 8 &&
2119 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
);
2121 if (untyped_fallback
)
2122 isl_fmt
= ISL_FORMAT_RAW
;
2124 isl_fmt
= isl_lower_storage_image_format(devinfo
, isl_fmt
);
2127 if (res
->base
.target
!= PIPE_BUFFER
) {
2128 struct isl_view view
= {
2130 .base_level
= img
->u
.tex
.level
,
2132 .base_array_layer
= img
->u
.tex
.first_layer
,
2133 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
2134 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2138 if (untyped_fallback
) {
2139 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2140 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2143 /* Images don't support compression */
2144 unsigned aux_modes
= 1 << ISL_AUX_USAGE_NONE
;
2146 enum isl_aux_usage usage
= u_bit_scan(&aux_modes
);
2148 fill_surface_state(&screen
->isl_dev
, map
, res
, &view
, usage
);
2150 map
+= SURFACE_STATE_ALIGNMENT
;
2154 isl_surf_fill_image_param(&screen
->isl_dev
,
2155 &image_params
[start_slot
+ i
],
2158 util_range_add(&res
->valid_buffer_range
, img
->u
.buf
.offset
,
2159 img
->u
.buf
.offset
+ img
->u
.buf
.size
);
2161 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2162 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2163 img
->u
.buf
.offset
, img
->u
.buf
.size
);
2164 fill_buffer_image_param(&image_params
[start_slot
+ i
],
2165 img
->format
, img
->u
.buf
.size
);
2168 pipe_resource_reference(&iv
->base
.resource
, NULL
);
2169 pipe_resource_reference(&iv
->surface_state
.res
, NULL
);
2170 fill_default_image_param(&image_params
[start_slot
+ i
]);
2174 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2176 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2177 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2179 /* Broadwell also needs brw_image_params re-uploaded */
2181 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2182 shs
->cbuf0_needs_upload
= true;
2188 * The pipe->set_sampler_views() driver hook.
2191 iris_set_sampler_views(struct pipe_context
*ctx
,
2192 enum pipe_shader_type p_stage
,
2193 unsigned start
, unsigned count
,
2194 struct pipe_sampler_view
**views
)
2196 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2197 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2198 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2200 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
2202 for (unsigned i
= 0; i
< count
; i
++) {
2203 struct pipe_sampler_view
*pview
= views
? views
[i
] : NULL
;
2204 pipe_sampler_view_reference((struct pipe_sampler_view
**)
2205 &shs
->textures
[start
+ i
], pview
);
2206 struct iris_sampler_view
*view
= (void *) pview
;
2208 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
2209 shs
->bound_sampler_views
|= 1 << (start
+ i
);
2213 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
2215 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2216 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2220 * The pipe->set_tess_state() driver hook.
2223 iris_set_tess_state(struct pipe_context
*ctx
,
2224 const float default_outer_level
[4],
2225 const float default_inner_level
[2])
2227 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2228 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
2230 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
2231 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
2233 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
2234 shs
->cbuf0_needs_upload
= true;
2238 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
2240 struct iris_surface
*surf
= (void *) p_surf
;
2241 pipe_resource_reference(&p_surf
->texture
, NULL
);
2242 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2247 iris_set_clip_state(struct pipe_context
*ctx
,
2248 const struct pipe_clip_state
*state
)
2250 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2251 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
2253 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
2255 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
;
2256 shs
->cbuf0_needs_upload
= true;
2260 * The pipe->set_polygon_stipple() driver hook.
2263 iris_set_polygon_stipple(struct pipe_context
*ctx
,
2264 const struct pipe_poly_stipple
*state
)
2266 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2267 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
2268 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
2272 * The pipe->set_sample_mask() driver hook.
2275 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2277 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2279 /* We only support 16x MSAA, so we have 16 bits of sample maks.
2280 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
2282 ice
->state
.sample_mask
= sample_mask
& 0xffff;
2283 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
2287 * The pipe->set_scissor_states() driver hook.
2289 * This corresponds to our SCISSOR_RECT state structures. It's an
2290 * exact match, so we just store them, and memcpy them out later.
2293 iris_set_scissor_states(struct pipe_context
*ctx
,
2294 unsigned start_slot
,
2295 unsigned num_scissors
,
2296 const struct pipe_scissor_state
*rects
)
2298 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2300 for (unsigned i
= 0; i
< num_scissors
; i
++) {
2301 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
2302 /* If the scissor was out of bounds and got clamped to 0 width/height
2303 * at the bounds, the subtraction of 1 from maximums could produce a
2304 * negative number and thus not clip anything. Instead, just provide
2305 * a min > max scissor inside the bounds, which produces the expected
2308 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2309 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
2312 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2313 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
2314 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
2319 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
2323 * The pipe->set_stencil_ref() driver hook.
2325 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
2328 iris_set_stencil_ref(struct pipe_context
*ctx
,
2329 const struct pipe_stencil_ref
*state
)
2331 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2332 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2334 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2336 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2340 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2342 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2346 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2347 float m00
, float m11
, float m30
, float m31
,
2348 float *xmin
, float *xmax
,
2349 float *ymin
, float *ymax
)
2351 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2352 * Strips and Fans documentation:
2354 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2355 * fixed-point "guardband" range supported by the rasterization hardware"
2359 * "In almost all circumstances, if an object’s vertices are actually
2360 * modified by this clamping (i.e., had X or Y coordinates outside of
2361 * the guardband extent the rendered object will not match the intended
2362 * result. Therefore software should take steps to ensure that this does
2363 * not happen - e.g., by clipping objects such that they do not exceed
2364 * these limits after the Drawing Rectangle is applied."
2366 * I believe the fundamental restriction is that the rasterizer (in
2367 * the SF/WM stages) have a limit on the number of pixels that can be
2368 * rasterized. We need to ensure any coordinates beyond the rasterizer
2369 * limit are handled by the clipper. So effectively that limit becomes
2370 * the clipper's guardband size.
2372 * It goes on to say:
2374 * "In addition, in order to be correctly rendered, objects must have a
2375 * screenspace bounding box not exceeding 8K in the X or Y direction.
2376 * This additional restriction must also be comprehended by software,
2377 * i.e., enforced by use of clipping."
2379 * This makes no sense. Gen7+ hardware supports 16K render targets,
2380 * and you definitely need to be able to draw polygons that fill the
2381 * surface. Our assumption is that the rasterizer was limited to 8K
2382 * on Sandybridge, which only supports 8K surfaces, and it was actually
2383 * increased to 16K on Ivybridge and later.
2385 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2387 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2389 if (m00
!= 0 && m11
!= 0) {
2390 /* First, we compute the screen-space render area */
2391 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2392 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2393 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2394 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2396 /* We want the guardband to be centered on that */
2397 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2398 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2399 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2400 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2402 /* Now we need it in native device coordinates */
2403 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2404 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2405 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2406 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2408 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2409 * flipped upside-down. X should be fine though.
2411 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2412 *xmin
= ndc_gb_xmin
;
2413 *xmax
= ndc_gb_xmax
;
2414 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2415 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2417 /* The viewport scales to 0, so nothing will be rendered. */
2426 * The pipe->set_viewport_states() driver hook.
2428 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2429 * the guardband yet, as we need the framebuffer dimensions, but we can
2430 * at least fill out the rest.
2433 iris_set_viewport_states(struct pipe_context
*ctx
,
2434 unsigned start_slot
,
2436 const struct pipe_viewport_state
*states
)
2438 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2440 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2442 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2444 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2445 !ice
->state
.cso_rast
->depth_clip_far
))
2446 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2450 * The pipe->set_framebuffer_state() driver hook.
2452 * Sets the current draw FBO, including color render targets, depth,
2453 * and stencil buffers.
2456 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2457 const struct pipe_framebuffer_state
*state
)
2459 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2460 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2461 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2462 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2463 struct iris_resource
*zres
;
2464 struct iris_resource
*stencil_res
;
2466 unsigned samples
= util_framebuffer_get_num_samples(state
);
2467 unsigned layers
= util_framebuffer_get_num_layers(state
);
2469 if (cso
->samples
!= samples
) {
2470 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2473 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2474 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2477 if ((cso
->layers
== 0) != (layers
== 0)) {
2478 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2481 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2482 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2485 util_copy_framebuffer_state(cso
, state
);
2486 cso
->samples
= samples
;
2487 cso
->layers
= layers
;
2489 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2491 struct isl_view view
= {
2494 .base_array_layer
= 0,
2496 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2499 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
2502 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2505 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2506 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2508 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2511 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2513 info
.depth_surf
= &zres
->surf
;
2514 info
.depth_address
= zres
->bo
->gtt_offset
+ zres
->offset
;
2515 info
.mocs
= mocs(zres
->bo
);
2517 view
.format
= zres
->surf
.format
;
2519 if (iris_resource_level_has_hiz(zres
, view
.base_level
)) {
2520 info
.hiz_usage
= ISL_AUX_USAGE_HIZ
;
2521 info
.hiz_surf
= &zres
->aux
.surf
;
2522 info
.hiz_address
= zres
->aux
.bo
->gtt_offset
;
2527 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2528 info
.stencil_surf
= &stencil_res
->surf
;
2529 info
.stencil_address
= stencil_res
->bo
->gtt_offset
+ stencil_res
->offset
;
2531 view
.format
= stencil_res
->surf
.format
;
2532 info
.mocs
= mocs(stencil_res
->bo
);
2537 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2539 /* Make a null surface for unbound buffers */
2540 void *null_surf_map
=
2541 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2542 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2543 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2544 isl_extent3d(MAX2(cso
->width
, 1),
2545 MAX2(cso
->height
, 1),
2546 cso
->layers
? cso
->layers
: 1));
2547 ice
->state
.null_fb
.offset
+=
2548 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2550 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2552 /* Render target change */
2553 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2555 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2557 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2560 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2561 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2563 /* The PIPE_CONTROL command description says:
2565 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2566 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2567 * Target Cache Flush by enabling this bit. When render target flush
2568 * is set due to new association of BTI, PS Scoreboard Stall bit must
2569 * be set in this packet."
2571 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2572 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2573 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2574 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2579 * The pipe->set_constant_buffer() driver hook.
2581 * This uploads any constant data in user buffers, and references
2582 * any UBO resources containing constant data.
2585 iris_set_constant_buffer(struct pipe_context
*ctx
,
2586 enum pipe_shader_type p_stage
, unsigned index
,
2587 const struct pipe_constant_buffer
*input
)
2589 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2590 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2591 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2592 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[index
];
2594 if (input
&& input
->buffer
) {
2595 shs
->bound_cbufs
|= 1u << index
;
2599 pipe_resource_reference(&cbuf
->buffer
, input
->buffer
);
2600 cbuf
->buffer_offset
= input
->buffer_offset
;
2602 MIN2(input
->buffer_size
,
2603 iris_resource_bo(input
->buffer
)->size
- cbuf
->buffer_offset
);
2605 struct iris_resource
*res
= (void *) cbuf
->buffer
;
2606 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2608 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
2609 &shs
->constbuf_surf_state
[index
],
2612 shs
->bound_cbufs
&= ~(1u << index
);
2613 pipe_resource_reference(&cbuf
->buffer
, NULL
);
2614 pipe_resource_reference(&shs
->constbuf_surf_state
[index
].res
, NULL
);
2619 memcpy(&shs
->cbuf0
, input
, sizeof(shs
->cbuf0
));
2621 memset(&shs
->cbuf0
, 0, sizeof(shs
->cbuf0
));
2623 shs
->cbuf0_needs_upload
= true;
2626 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2627 // XXX: maybe not necessary all the time...?
2628 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2629 // XXX: pull model we may need actual new bindings...
2630 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2634 upload_uniforms(struct iris_context
*ice
,
2635 gl_shader_stage stage
)
2637 UNUSED
struct iris_genx_state
*genx
= ice
->state
.genx
;
2638 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2639 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[0];
2640 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2642 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t) +
2643 shs
->cbuf0
.buffer_size
;
2645 if (upload_size
== 0)
2648 uint32_t *map
= NULL
;
2649 u_upload_alloc(ice
->ctx
.const_uploader
, 0, upload_size
, 64,
2650 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
2652 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2653 uint32_t sysval
= shader
->system_values
[i
];
2656 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
2658 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
2659 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
2660 struct brw_image_param
*param
=
2661 &genx
->shaders
[stage
].image_param
[img
];
2663 assert(offset
< sizeof(struct brw_image_param
));
2664 value
= ((uint32_t *) param
)[offset
];
2666 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
2668 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2669 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2670 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2671 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2672 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
2673 if (stage
== MESA_SHADER_TESS_CTRL
) {
2674 value
= ice
->state
.vertices_per_patch
;
2676 assert(stage
== MESA_SHADER_TESS_EVAL
);
2677 const struct shader_info
*tcs_info
=
2678 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
2680 value
= tcs_info
->tess
.tcs_vertices_out
;
2682 value
= ice
->state
.vertices_per_patch
;
2684 } else if (sysval
>= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
&&
2685 sysval
<= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
) {
2686 unsigned i
= sysval
- BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
2687 value
= fui(ice
->state
.default_outer_level
[i
]);
2688 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
) {
2689 value
= fui(ice
->state
.default_inner_level
[0]);
2690 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
) {
2691 value
= fui(ice
->state
.default_inner_level
[1]);
2693 assert(!"unhandled system value");
2699 if (shs
->cbuf0
.user_buffer
) {
2700 memcpy(map
, shs
->cbuf0
.user_buffer
, shs
->cbuf0
.buffer_size
);
2703 cbuf
->buffer_size
= upload_size
;
2704 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
2705 &shs
->constbuf_surf_state
[0], false);
2709 * The pipe->set_shader_buffers() driver hook.
2711 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2712 * SURFACE_STATE here, as the buffer offset may change each time.
2715 iris_set_shader_buffers(struct pipe_context
*ctx
,
2716 enum pipe_shader_type p_stage
,
2717 unsigned start_slot
, unsigned count
,
2718 const struct pipe_shader_buffer
*buffers
,
2719 unsigned writable_bitmask
)
2721 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2722 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2723 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2725 unsigned modified_bits
= u_bit_consecutive(start_slot
, count
);
2727 shs
->bound_ssbos
&= ~modified_bits
;
2728 shs
->writable_ssbos
&= ~modified_bits
;
2729 shs
->writable_ssbos
|= writable_bitmask
<< start_slot
;
2731 for (unsigned i
= 0; i
< count
; i
++) {
2732 if (buffers
&& buffers
[i
].buffer
) {
2733 struct iris_resource
*res
= (void *) buffers
[i
].buffer
;
2734 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[start_slot
+ i
];
2735 struct iris_state_ref
*surf_state
=
2736 &shs
->ssbo_surf_state
[start_slot
+ i
];
2737 pipe_resource_reference(&ssbo
->buffer
, &res
->base
);
2738 ssbo
->buffer_offset
= buffers
[i
].buffer_offset
;
2740 MIN2(buffers
[i
].buffer_size
, res
->bo
->size
- ssbo
->buffer_offset
);
2742 shs
->bound_ssbos
|= 1 << (start_slot
+ i
);
2744 iris_upload_ubo_ssbo_surf_state(ice
, ssbo
, surf_state
, true);
2746 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2748 util_range_add(&res
->valid_buffer_range
, ssbo
->buffer_offset
,
2749 ssbo
->buffer_offset
+ ssbo
->buffer_size
);
2751 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
].buffer
, NULL
);
2752 pipe_resource_reference(&shs
->ssbo_surf_state
[start_slot
+ i
].res
,
2757 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2761 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2767 * The pipe->set_vertex_buffers() driver hook.
2769 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2772 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2773 unsigned start_slot
, unsigned count
,
2774 const struct pipe_vertex_buffer
*buffers
)
2776 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2777 struct iris_genx_state
*genx
= ice
->state
.genx
;
2779 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
2781 for (unsigned i
= 0; i
< count
; i
++) {
2782 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
2783 struct iris_vertex_buffer_state
*state
=
2784 &genx
->vertex_buffers
[start_slot
+ i
];
2787 pipe_resource_reference(&state
->resource
, NULL
);
2791 /* We may see user buffers that are NULL bindings. */
2792 assert(!(buffer
->is_user_buffer
&& buffer
->buffer
.user
!= NULL
));
2794 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
2795 struct iris_resource
*res
= (void *) state
->resource
;
2798 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
2799 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2802 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
2803 vb
.VertexBufferIndex
= start_slot
+ i
;
2804 vb
.AddressModifyEnable
= true;
2805 vb
.BufferPitch
= buffer
->stride
;
2807 vb
.BufferSize
= res
->bo
->size
- (int) buffer
->buffer_offset
;
2808 vb
.BufferStartingAddress
=
2809 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
2810 vb
.MOCS
= mocs(res
->bo
);
2812 vb
.NullVertexBuffer
= true;
2817 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2821 * Gallium CSO for vertex elements.
2823 struct iris_vertex_element_state
{
2824 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2825 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2826 uint32_t edgeflag_ve
[GENX(VERTEX_ELEMENT_STATE_length
)];
2827 uint32_t edgeflag_vfi
[GENX(3DSTATE_VF_INSTANCING_length
)];
2832 * The pipe->create_vertex_elements() driver hook.
2834 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2835 * and 3DSTATE_VF_INSTANCING commands. The vertex_elements and vf_instancing
2836 * arrays are ready to be emitted at draw time if no EdgeFlag or SGVs are
2837 * needed. In these cases we will need information available at draw time.
2838 * We setup edgeflag_ve and edgeflag_vfi as alternatives last
2839 * 3DSTATE_VERTEX_ELEMENT and 3DSTATE_VF_INSTANCING that can be used at
2840 * draw time if we detect that EdgeFlag is needed by the Vertex Shader.
2843 iris_create_vertex_elements(struct pipe_context
*ctx
,
2845 const struct pipe_vertex_element
*state
)
2847 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2848 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2849 struct iris_vertex_element_state
*cso
=
2850 malloc(sizeof(struct iris_vertex_element_state
));
2854 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2856 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2859 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2860 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2863 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2865 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2866 ve
.Component0Control
= VFCOMP_STORE_0
;
2867 ve
.Component1Control
= VFCOMP_STORE_0
;
2868 ve
.Component2Control
= VFCOMP_STORE_0
;
2869 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2872 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2876 for (int i
= 0; i
< count
; i
++) {
2877 const struct iris_format_info fmt
=
2878 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2879 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2880 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2882 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2883 case 0: comp
[0] = VFCOMP_STORE_0
; /* fallthrough */
2884 case 1: comp
[1] = VFCOMP_STORE_0
; /* fallthrough */
2885 case 2: comp
[2] = VFCOMP_STORE_0
; /* fallthrough */
2887 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2888 : VFCOMP_STORE_1_FP
;
2891 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2892 ve
.EdgeFlagEnable
= false;
2893 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2895 ve
.SourceElementOffset
= state
[i
].src_offset
;
2896 ve
.SourceElementFormat
= fmt
.fmt
;
2897 ve
.Component0Control
= comp
[0];
2898 ve
.Component1Control
= comp
[1];
2899 ve
.Component2Control
= comp
[2];
2900 ve
.Component3Control
= comp
[3];
2903 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2904 vi
.VertexElementIndex
= i
;
2905 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2906 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2909 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2910 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2913 /* An alternative version of the last VE and VFI is stored so it
2914 * can be used at draw time in case Vertex Shader uses EdgeFlag
2917 const unsigned edgeflag_index
= count
- 1;
2918 const struct iris_format_info fmt
=
2919 iris_format_for_usage(devinfo
, state
[edgeflag_index
].src_format
, 0);
2920 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), cso
->edgeflag_ve
, ve
) {
2921 ve
.EdgeFlagEnable
= true ;
2922 ve
.VertexBufferIndex
= state
[edgeflag_index
].vertex_buffer_index
;
2924 ve
.SourceElementOffset
= state
[edgeflag_index
].src_offset
;
2925 ve
.SourceElementFormat
= fmt
.fmt
;
2926 ve
.Component0Control
= VFCOMP_STORE_SRC
;
2927 ve
.Component1Control
= VFCOMP_STORE_0
;
2928 ve
.Component2Control
= VFCOMP_STORE_0
;
2929 ve
.Component3Control
= VFCOMP_STORE_0
;
2931 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->edgeflag_vfi
, vi
) {
2932 /* The vi.VertexElementIndex of the EdgeFlag Vertex Element is filled
2933 * at draw time, as it should change if SGVs are emitted.
2935 vi
.InstancingEnable
= state
[edgeflag_index
].instance_divisor
> 0;
2936 vi
.InstanceDataStepRate
= state
[edgeflag_index
].instance_divisor
;
2944 * The pipe->bind_vertex_elements_state() driver hook.
2947 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2949 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2950 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2951 struct iris_vertex_element_state
*new_cso
= state
;
2953 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2954 * we need to re-emit it to ensure we're overriding the right one.
2956 if (new_cso
&& cso_changed(count
))
2957 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2959 ice
->state
.cso_vertex_elements
= state
;
2960 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2964 * The pipe->create_stream_output_target() driver hook.
2966 * "Target" here refers to a destination buffer. We translate this into
2967 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2968 * know which buffer this represents, or whether we ought to zero the
2969 * write-offsets, or append. Those are handled in the set() hook.
2971 static struct pipe_stream_output_target
*
2972 iris_create_stream_output_target(struct pipe_context
*ctx
,
2973 struct pipe_resource
*p_res
,
2974 unsigned buffer_offset
,
2975 unsigned buffer_size
)
2977 struct iris_resource
*res
= (void *) p_res
;
2978 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2982 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
2984 pipe_reference_init(&cso
->base
.reference
, 1);
2985 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
2986 cso
->base
.buffer_offset
= buffer_offset
;
2987 cso
->base
.buffer_size
= buffer_size
;
2988 cso
->base
.context
= ctx
;
2990 util_range_add(&res
->valid_buffer_range
, buffer_offset
,
2991 buffer_offset
+ buffer_size
);
2993 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
2999 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
3000 struct pipe_stream_output_target
*state
)
3002 struct iris_stream_output_target
*cso
= (void *) state
;
3004 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
3005 pipe_resource_reference(&cso
->offset
.res
, NULL
);
3011 * The pipe->set_stream_output_targets() driver hook.
3013 * At this point, we know which targets are bound to a particular index,
3014 * and also whether we want to append or start over. We can finish the
3015 * 3DSTATE_SO_BUFFER packets we started earlier.
3018 iris_set_stream_output_targets(struct pipe_context
*ctx
,
3019 unsigned num_targets
,
3020 struct pipe_stream_output_target
**targets
,
3021 const unsigned *offsets
)
3023 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3024 struct iris_genx_state
*genx
= ice
->state
.genx
;
3025 uint32_t *so_buffers
= genx
->so_buffers
;
3027 const bool active
= num_targets
> 0;
3028 if (ice
->state
.streamout_active
!= active
) {
3029 ice
->state
.streamout_active
= active
;
3030 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
3032 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
3033 * it's a non-pipelined command. If we're switching streamout on, we
3034 * may have missed emitting it earlier, so do so now. (We're already
3035 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
3038 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
3041 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3042 struct iris_stream_output_target
*tgt
=
3043 (void *) ice
->state
.so_target
[i
];
3045 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3047 flush
|= iris_flush_bits_for_history(res
);
3048 iris_dirty_for_history(ice
, res
);
3051 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
], flush
);
3055 for (int i
= 0; i
< 4; i
++) {
3056 pipe_so_target_reference(&ice
->state
.so_target
[i
],
3057 i
< num_targets
? targets
[i
] : NULL
);
3060 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
3064 for (unsigned i
= 0; i
< 4; i
++,
3065 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
3067 struct iris_stream_output_target
*tgt
= (void *) ice
->state
.so_target
[i
];
3068 unsigned offset
= offsets
[i
];
3071 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
3072 sob
.SOBufferIndex
= i
;
3076 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3078 /* Note that offsets[i] will either be 0, causing us to zero
3079 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
3080 * "continue appending at the existing offset."
3082 assert(offset
== 0 || offset
== 0xFFFFFFFF);
3084 /* We might be called by Begin (offset = 0), Pause, then Resume
3085 * (offset = 0xFFFFFFFF) before ever drawing (where these commands
3086 * will actually be sent to the GPU). In this case, we don't want
3087 * to append - we still want to do our initial zeroing.
3092 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
3093 sob
.SurfaceBaseAddress
=
3094 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
3095 sob
.SOBufferEnable
= true;
3096 sob
.StreamOffsetWriteEnable
= true;
3097 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3098 sob
.MOCS
= mocs(res
->bo
);
3100 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
3102 sob
.SOBufferIndex
= i
;
3103 sob
.StreamOffset
= offset
;
3104 sob
.StreamOutputBufferOffsetAddress
=
3105 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
3106 tgt
->offset
.offset
);
3110 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
3114 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
3115 * 3DSTATE_STREAMOUT packets.
3117 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
3118 * hardware to record. We can create it entirely based on the shader, with
3119 * no dynamic state dependencies.
3121 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
3122 * state-based settings. We capture the shader-related ones here, and merge
3123 * the rest in at draw time.
3126 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
3127 const struct brw_vue_map
*vue_map
)
3129 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3130 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3131 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3132 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3134 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3136 memset(so_decl
, 0, sizeof(so_decl
));
3138 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3139 * command feels strange -- each dword pair contains a SO_DECL per stream.
3141 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
3142 const struct pipe_stream_output
*output
= &info
->output
[i
];
3143 const int buffer
= output
->output_buffer
;
3144 const int varying
= output
->register_index
;
3145 const unsigned stream_id
= output
->stream
;
3146 assert(stream_id
< MAX_VERTEX_STREAMS
);
3148 buffer_mask
[stream_id
] |= 1 << buffer
;
3150 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3152 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3153 * array. Instead, it simply increments DstOffset for the following
3154 * input by the number of components that should be skipped.
3156 * Our hardware is unusual in that it requires us to program SO_DECLs
3157 * for fake "hole" components, rather than simply taking the offset
3158 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3159 * program as many size = 4 holes as we can, then a final hole to
3160 * accommodate the final 1, 2, or 3 remaining.
3162 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
3164 while (skip_components
> 0) {
3165 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3167 .OutputBufferSlot
= output
->output_buffer
,
3168 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3170 skip_components
-= 4;
3173 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
3175 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3176 .OutputBufferSlot
= output
->output_buffer
,
3177 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3179 ((1 << output
->num_components
) - 1) << output
->start_component
,
3182 if (decls
[stream_id
] > max_decls
)
3183 max_decls
= decls
[stream_id
];
3186 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
3187 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
3188 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
3190 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
3191 int urb_entry_read_offset
= 0;
3192 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3193 urb_entry_read_offset
;
3195 /* We always read the whole vertex. This could be reduced at some
3196 * point by reading less and offsetting the register index in the
3199 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3200 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3201 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3202 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3203 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3204 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3205 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3206 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3208 /* Set buffer pitches; 0 means unbound. */
3209 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
3210 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
3211 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
3212 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
3215 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
3216 list
.DWordLength
= 3 + 2 * max_decls
- 2;
3217 list
.StreamtoBufferSelects0
= buffer_mask
[0];
3218 list
.StreamtoBufferSelects1
= buffer_mask
[1];
3219 list
.StreamtoBufferSelects2
= buffer_mask
[2];
3220 list
.StreamtoBufferSelects3
= buffer_mask
[3];
3221 list
.NumEntries0
= decls
[0];
3222 list
.NumEntries1
= decls
[1];
3223 list
.NumEntries2
= decls
[2];
3224 list
.NumEntries3
= decls
[3];
3227 for (int i
= 0; i
< max_decls
; i
++) {
3228 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
3229 entry
.Stream0Decl
= so_decl
[0][i
];
3230 entry
.Stream1Decl
= so_decl
[1][i
];
3231 entry
.Stream2Decl
= so_decl
[2][i
];
3232 entry
.Stream3Decl
= so_decl
[3][i
];
3240 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
3241 const struct brw_vue_map
*last_vue_map
,
3242 bool two_sided_color
,
3243 unsigned *out_offset
,
3244 unsigned *out_length
)
3246 /* The compiler computes the first URB slot without considering COL/BFC
3247 * swizzling (because it doesn't know whether it's enabled), so we need
3248 * to do that here too. This may result in a smaller offset, which
3251 const unsigned first_slot
=
3252 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
3254 /* This becomes the URB read offset (counted in pairs of slots). */
3255 assert(first_slot
% 2 == 0);
3256 *out_offset
= first_slot
/ 2;
3258 /* We need to adjust the inputs read to account for front/back color
3259 * swizzling, as it can make the URB length longer.
3261 for (int c
= 0; c
<= 1; c
++) {
3262 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
3263 /* If two sided color is enabled, the fragment shader's gl_Color
3264 * (COL0) input comes from either the gl_FrontColor (COL0) or
3265 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
3267 if (two_sided_color
)
3268 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3270 /* If front color isn't written, we opt to give them back color
3271 * instead of an undefined value. Switch from COL to BFC.
3273 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
3274 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
3275 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3280 /* Compute the minimum URB Read Length necessary for the FS inputs.
3282 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
3283 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
3285 * "This field should be set to the minimum length required to read the
3286 * maximum source attribute. The maximum source attribute is indicated
3287 * by the maximum value of the enabled Attribute # Source Attribute if
3288 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
3289 * enable is not set.
3290 * read_length = ceiling((max_source_attr + 1) / 2)
3292 * [errata] Corruption/Hang possible if length programmed larger than
3295 * Similar text exists for Ivy Bridge.
3297 * We find the last URB slot that's actually read by the FS.
3299 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
3300 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
3301 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
3304 /* The URB read length is the difference of the two, counted in pairs. */
3305 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
3309 iris_emit_sbe_swiz(struct iris_batch
*batch
,
3310 const struct iris_context
*ice
,
3311 unsigned urb_read_offset
,
3312 unsigned sprite_coord_enables
)
3314 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
3315 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3316 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3317 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
3318 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3320 /* XXX: this should be generated when putting programs in place */
3322 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
3323 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
3324 if (input_index
< 0 || input_index
>= 16)
3327 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
3328 &attr_overrides
[input_index
];
3329 int slot
= vue_map
->varying_to_slot
[fs_attr
];
3331 /* Viewport and Layer are stored in the VUE header. We need to override
3332 * them to zero if earlier stages didn't write them, as GL requires that
3333 * they read back as zero when not explicitly set.
3336 case VARYING_SLOT_VIEWPORT
:
3337 case VARYING_SLOT_LAYER
:
3338 attr
->ComponentOverrideX
= true;
3339 attr
->ComponentOverrideW
= true;
3340 attr
->ConstantSource
= CONST_0000
;
3342 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
3343 attr
->ComponentOverrideY
= true;
3344 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
3345 attr
->ComponentOverrideZ
= true;
3348 case VARYING_SLOT_PRIMITIVE_ID
:
3349 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
3351 attr
->ComponentOverrideX
= true;
3352 attr
->ComponentOverrideY
= true;
3353 attr
->ComponentOverrideZ
= true;
3354 attr
->ComponentOverrideW
= true;
3355 attr
->ConstantSource
= PRIM_ID
;
3363 if (sprite_coord_enables
& (1 << input_index
))
3366 /* If there was only a back color written but not front, use back
3367 * as the color instead of undefined.
3369 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
3370 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
3371 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
3372 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
3374 /* Not written by the previous stage - undefined. */
3376 attr
->ComponentOverrideX
= true;
3377 attr
->ComponentOverrideY
= true;
3378 attr
->ComponentOverrideZ
= true;
3379 attr
->ComponentOverrideW
= true;
3380 attr
->ConstantSource
= CONST_0001_FLOAT
;
3384 /* Compute the location of the attribute relative to the read offset,
3385 * which is counted in 256-bit increments (two 128-bit VUE slots).
3387 const int source_attr
= slot
- 2 * urb_read_offset
;
3388 assert(source_attr
>= 0 && source_attr
<= 32);
3389 attr
->SourceAttribute
= source_attr
;
3391 /* If we are doing two-sided color, and the VUE slot following this one
3392 * represents a back-facing color, then we need to instruct the SF unit
3393 * to do back-facing swizzling.
3395 if (cso_rast
->light_twoside
&&
3396 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3397 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3398 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3399 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3400 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3403 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3404 for (int i
= 0; i
< 16; i
++)
3405 sbes
.Attribute
[i
] = attr_overrides
[i
];
3410 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3411 const struct iris_rasterizer_state
*cso
)
3413 unsigned overrides
= 0;
3415 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
3416 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
3418 for (int i
= 0; i
< 8; i
++) {
3419 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
3420 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
3421 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
3428 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
3430 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3431 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3432 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3433 const struct shader_info
*fs_info
=
3434 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
3436 unsigned urb_read_offset
, urb_read_length
;
3437 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
3438 ice
->shaders
.last_vue_map
,
3439 cso_rast
->light_twoside
,
3440 &urb_read_offset
, &urb_read_length
);
3442 unsigned sprite_coord_overrides
=
3443 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3445 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
3446 sbe
.AttributeSwizzleEnable
= true;
3447 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3448 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3449 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3450 sbe
.VertexURBEntryReadLength
= urb_read_length
;
3451 sbe
.ForceVertexURBEntryReadOffset
= true;
3452 sbe
.ForceVertexURBEntryReadLength
= true;
3453 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3454 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
3456 for (int i
= 0; i
< 32; i
++) {
3457 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3462 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
3465 /* ------------------------------------------------------------------- */
3468 * Populate VS program key fields based on the current state.
3471 iris_populate_vs_key(const struct iris_context
*ice
,
3472 const struct shader_info
*info
,
3473 struct brw_vs_prog_key
*key
)
3475 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3477 if (info
->clip_distance_array_size
== 0 &&
3478 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)))
3479 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3483 * Populate TCS program key fields based on the current state.
3486 iris_populate_tcs_key(const struct iris_context
*ice
,
3487 struct brw_tcs_prog_key
*key
)
3492 * Populate TES program key fields based on the current state.
3495 iris_populate_tes_key(const struct iris_context
*ice
,
3496 struct brw_tes_prog_key
*key
)
3501 * Populate GS program key fields based on the current state.
3504 iris_populate_gs_key(const struct iris_context
*ice
,
3505 struct brw_gs_prog_key
*key
)
3510 * Populate FS program key fields based on the current state.
3513 iris_populate_fs_key(const struct iris_context
*ice
,
3514 struct brw_wm_prog_key
*key
)
3516 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3517 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3518 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3519 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3520 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3522 key
->nr_color_regions
= fb
->nr_cbufs
;
3524 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3526 key
->alpha_to_coverage
= blend
->alpha_to_coverage
;
3528 key
->alpha_test_replicate_alpha
= fb
->nr_cbufs
> 1 && zsa
->alpha
.enabled
;
3530 /* XXX: only bother if COL0/1 are read */
3531 key
->flat_shade
= rast
->flatshade
;
3533 key
->persample_interp
= rast
->force_persample_interp
;
3534 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3536 key
->coherent_fb_fetch
= true;
3538 key
->force_dual_color_blend
=
3539 screen
->driconf
.dual_color_blend_by_location
&&
3540 (blend
->blend_enables
& 1) && blend
->dual_color_blending
;
3542 /* TODO: support key->force_dual_color_blend for Unigine */
3543 /* TODO: Respect glHint for key->high_quality_derivatives */
3547 iris_populate_cs_key(const struct iris_context
*ice
,
3548 struct brw_cs_prog_key
*key
)
3553 KSP(const struct iris_compiled_shader
*shader
)
3555 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3556 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3559 /* Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3560 * prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3561 * this WA on C0 stepping.
3563 * TODO: Fill out SamplerCount for prefetching?
3566 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3567 pkt.KernelStartPointer = KSP(shader); \
3568 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3569 shader->bt.size_bytes / 4; \
3570 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3572 pkt.DispatchGRFStartRegisterForURBData = \
3573 prog_data->dispatch_grf_start_reg; \
3574 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3575 pkt.prefix##URBEntryReadOffset = 0; \
3577 pkt.StatisticsEnable = true; \
3578 pkt.Enable = true; \
3580 if (prog_data->total_scratch) { \
3581 struct iris_bo *bo = \
3582 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3583 uint32_t scratch_addr = bo->gtt_offset; \
3584 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3585 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3589 * Encode most of 3DSTATE_VS based on the compiled shader.
3592 iris_store_vs_state(struct iris_context
*ice
,
3593 const struct gen_device_info
*devinfo
,
3594 struct iris_compiled_shader
*shader
)
3596 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3597 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3599 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3600 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3601 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3602 vs
.SIMD8DispatchEnable
= true;
3603 vs
.UserClipDistanceCullTestEnableBitmask
=
3604 vue_prog_data
->cull_distance_mask
;
3609 * Encode most of 3DSTATE_HS based on the compiled shader.
3612 iris_store_tcs_state(struct iris_context
*ice
,
3613 const struct gen_device_info
*devinfo
,
3614 struct iris_compiled_shader
*shader
)
3616 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3617 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3618 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3620 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3621 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3623 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3624 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3625 hs
.IncludeVertexHandles
= true;
3628 hs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
3629 hs
.IncludePrimitiveID
= tcs_prog_data
->include_primitive_id
;
3635 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3638 iris_store_tes_state(struct iris_context
*ice
,
3639 const struct gen_device_info
*devinfo
,
3640 struct iris_compiled_shader
*shader
)
3642 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3643 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3644 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3646 uint32_t *te_state
= (void *) shader
->derived_data
;
3647 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3649 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3650 te
.Partitioning
= tes_prog_data
->partitioning
;
3651 te
.OutputTopology
= tes_prog_data
->output_topology
;
3652 te
.TEDomain
= tes_prog_data
->domain
;
3654 te
.MaximumTessellationFactorOdd
= 63.0;
3655 te
.MaximumTessellationFactorNotOdd
= 64.0;
3658 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3659 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3661 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3662 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3663 ds
.ComputeWCoordinateEnable
=
3664 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3666 ds
.UserClipDistanceCullTestEnableBitmask
=
3667 vue_prog_data
->cull_distance_mask
;
3673 * Encode most of 3DSTATE_GS based on the compiled shader.
3676 iris_store_gs_state(struct iris_context
*ice
,
3677 const struct gen_device_info
*devinfo
,
3678 struct iris_compiled_shader
*shader
)
3680 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3681 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3682 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3684 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3685 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3687 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3688 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3689 gs
.ControlDataHeaderSize
=
3690 gs_prog_data
->control_data_header_size_hwords
;
3691 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3692 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3693 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3694 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3695 gs
.ReorderMode
= TRAILING
;
3696 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3697 gs
.MaximumNumberofThreads
=
3698 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3699 : (devinfo
->max_gs_threads
- 1);
3701 if (gs_prog_data
->static_vertex_count
!= -1) {
3702 gs
.StaticOutput
= true;
3703 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3705 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3707 gs
.UserClipDistanceCullTestEnableBitmask
=
3708 vue_prog_data
->cull_distance_mask
;
3710 const int urb_entry_write_offset
= 1;
3711 const uint32_t urb_entry_output_length
=
3712 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3713 urb_entry_write_offset
;
3715 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3716 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3721 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3724 iris_store_fs_state(struct iris_context
*ice
,
3725 const struct gen_device_info
*devinfo
,
3726 struct iris_compiled_shader
*shader
)
3728 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3729 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3731 uint32_t *ps_state
= (void *) shader
->derived_data
;
3732 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3734 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3735 ps
.VectorMaskEnable
= true;
3736 // XXX: WABTPPrefetchDisable, see above, drop at C0
3737 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3738 shader
->bt
.size_bytes
/ 4;
3739 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3740 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3742 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
3744 /* From the documentation for this packet:
3745 * "If the PS kernel does not need the Position XY Offsets to
3746 * compute a Position Value, then this field should be programmed
3747 * to POSOFFSET_NONE."
3749 * "SW Recommendation: If the PS kernel needs the Position Offsets
3750 * to compute a Position XY value, this field should match Position
3751 * ZW Interpolation Mode to ensure a consistent position.xyzw
3754 * We only require XY sample offsets. So, this recommendation doesn't
3755 * look useful at the moment. We might need this in future.
3757 ps
.PositionXYOffsetSelect
=
3758 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3759 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
3760 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
3761 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
3763 // XXX: Disable SIMD32 with 16x MSAA
3765 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3766 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
3767 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
3768 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
3769 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3770 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
3772 ps
.KernelStartPointer0
=
3773 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
3774 ps
.KernelStartPointer1
=
3775 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
3776 ps
.KernelStartPointer2
=
3777 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
3779 if (prog_data
->total_scratch
) {
3780 struct iris_bo
*bo
=
3781 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3782 MESA_SHADER_FRAGMENT
);
3783 uint32_t scratch_addr
= bo
->gtt_offset
;
3784 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3785 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3789 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3790 psx
.PixelShaderValid
= true;
3791 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3792 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
3793 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3794 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3795 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3796 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3797 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3800 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3801 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3803 psx
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
3810 * Compute the size of the derived data (shader command packets).
3812 * This must match the data written by the iris_store_xs_state() functions.
3815 iris_store_cs_state(struct iris_context
*ice
,
3816 const struct gen_device_info
*devinfo
,
3817 struct iris_compiled_shader
*shader
)
3819 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3820 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3821 void *map
= shader
->derived_data
;
3823 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3824 desc
.KernelStartPointer
= KSP(shader
);
3825 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3826 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3827 desc
.SharedLocalMemorySize
=
3828 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3829 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3830 desc
.CrossThreadConstantDataReadLength
=
3831 cs_prog_data
->push
.cross_thread
.regs
;
3836 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3838 assert(cache_id
<= IRIS_CACHE_BLORP
);
3840 static const unsigned dwords
[] = {
3841 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3842 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3843 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3844 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3846 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3847 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3848 [IRIS_CACHE_BLORP
] = 0,
3851 return sizeof(uint32_t) * dwords
[cache_id
];
3855 * Create any state packets corresponding to the given shader stage
3856 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3857 * This means that we can look up a program in the in-memory cache and
3858 * get most of the state packet without having to reconstruct it.
3861 iris_store_derived_program_state(struct iris_context
*ice
,
3862 enum iris_program_cache_id cache_id
,
3863 struct iris_compiled_shader
*shader
)
3865 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3866 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3870 iris_store_vs_state(ice
, devinfo
, shader
);
3872 case IRIS_CACHE_TCS
:
3873 iris_store_tcs_state(ice
, devinfo
, shader
);
3875 case IRIS_CACHE_TES
:
3876 iris_store_tes_state(ice
, devinfo
, shader
);
3879 iris_store_gs_state(ice
, devinfo
, shader
);
3882 iris_store_fs_state(ice
, devinfo
, shader
);
3885 iris_store_cs_state(ice
, devinfo
, shader
);
3886 case IRIS_CACHE_BLORP
:
3893 /* ------------------------------------------------------------------- */
3895 static const uint32_t push_constant_opcodes
[] = {
3896 [MESA_SHADER_VERTEX
] = 21,
3897 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3898 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3899 [MESA_SHADER_GEOMETRY
] = 22,
3900 [MESA_SHADER_FRAGMENT
] = 23,
3901 [MESA_SHADER_COMPUTE
] = 0,
3905 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3907 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3909 iris_use_pinned_bo(batch
, state_bo
, false);
3911 return ice
->state
.unbound_tex
.offset
;
3915 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3917 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3918 if (!ice
->state
.null_fb
.res
)
3919 return use_null_surface(batch
, ice
);
3921 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3923 iris_use_pinned_bo(batch
, state_bo
, false);
3925 return ice
->state
.null_fb
.offset
;
3929 surf_state_offset_for_aux(struct iris_resource
*res
,
3931 enum isl_aux_usage aux_usage
)
3933 return SURFACE_STATE_ALIGNMENT
*
3934 util_bitcount(res
->aux
.possible_usages
& ((1 << aux_usage
) - 1));
3938 surf_state_update_clear_value(struct iris_batch
*batch
,
3939 struct iris_resource
*res
,
3940 struct iris_state_ref
*state
,
3942 enum isl_aux_usage aux_usage
)
3944 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
3945 struct iris_bo
*state_bo
= iris_resource_bo(state
->res
);
3946 uint64_t real_offset
= state
->offset
+
3947 IRIS_MEMZONE_BINDER_START
;
3948 uint32_t offset_into_bo
= real_offset
- state_bo
->gtt_offset
;
3949 uint32_t clear_offset
= offset_into_bo
+
3950 isl_dev
->ss
.clear_value_offset
+
3951 surf_state_offset_for_aux(res
, aux_modes
, aux_usage
);
3953 batch
->vtbl
->copy_mem_mem(batch
, state_bo
, clear_offset
,
3954 res
->aux
.clear_color_bo
,
3955 res
->aux
.clear_color_offset
,
3956 isl_dev
->ss
.clear_value_size
);
3960 update_clear_value(struct iris_context
*ice
,
3961 struct iris_batch
*batch
,
3962 struct iris_resource
*res
,
3963 struct iris_state_ref
*state
,
3965 struct isl_view
*view
)
3967 struct iris_screen
*screen
= batch
->screen
;
3968 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3970 /* We only need to update the clear color in the surface state for gen8 and
3971 * gen9. Newer gens can read it directly from the clear color state buffer.
3973 if (devinfo
->gen
> 9)
3976 if (devinfo
->gen
== 9) {
3977 /* Skip updating the ISL_AUX_USAGE_NONE surface state */
3978 aux_modes
&= ~(1 << ISL_AUX_USAGE_NONE
);
3981 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
3983 surf_state_update_clear_value(batch
, res
, state
, aux_modes
,
3986 } else if (devinfo
->gen
== 8) {
3987 pipe_resource_reference(&state
->res
, NULL
);
3988 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
3989 state
, res
->aux
.possible_usages
);
3991 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
3992 fill_surface_state(&screen
->isl_dev
, map
, res
, view
, aux_usage
);
3993 map
+= SURFACE_STATE_ALIGNMENT
;
3999 * Add a surface to the validation list, as well as the buffer containing
4000 * the corresponding SURFACE_STATE.
4002 * Returns the binding table entry (offset to SURFACE_STATE).
4005 use_surface(struct iris_context
*ice
,
4006 struct iris_batch
*batch
,
4007 struct pipe_surface
*p_surf
,
4009 enum isl_aux_usage aux_usage
)
4011 struct iris_surface
*surf
= (void *) p_surf
;
4012 struct iris_resource
*res
= (void *) p_surf
->texture
;
4014 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
4015 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
4018 iris_use_pinned_bo(batch
, res
->aux
.bo
, writeable
);
4019 if (res
->aux
.clear_color_bo
)
4020 iris_use_pinned_bo(batch
, res
->aux
.clear_color_bo
, false);
4022 if (memcmp(&res
->aux
.clear_color
, &surf
->clear_color
,
4023 sizeof(surf
->clear_color
)) != 0) {
4024 update_clear_value(ice
, batch
, res
, &surf
->surface_state
,
4025 res
->aux
.possible_usages
, &surf
->view
);
4026 surf
->clear_color
= res
->aux
.clear_color
;
4030 return surf
->surface_state
.offset
+
4031 surf_state_offset_for_aux(res
, res
->aux
.possible_usages
, aux_usage
);
4035 use_sampler_view(struct iris_context
*ice
,
4036 struct iris_batch
*batch
,
4037 struct iris_sampler_view
*isv
)
4040 enum isl_aux_usage aux_usage
=
4041 iris_resource_texture_aux_usage(ice
, isv
->res
, isv
->view
.format
, 0);
4043 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
4044 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
4046 if (isv
->res
->aux
.bo
) {
4047 iris_use_pinned_bo(batch
, isv
->res
->aux
.bo
, false);
4048 if (isv
->res
->aux
.clear_color_bo
)
4049 iris_use_pinned_bo(batch
, isv
->res
->aux
.clear_color_bo
, false);
4050 if (memcmp(&isv
->res
->aux
.clear_color
, &isv
->clear_color
,
4051 sizeof(isv
->clear_color
)) != 0) {
4052 update_clear_value(ice
, batch
, isv
->res
, &isv
->surface_state
,
4053 isv
->res
->aux
.sampler_usages
, &isv
->view
);
4054 isv
->clear_color
= isv
->res
->aux
.clear_color
;
4058 return isv
->surface_state
.offset
+
4059 surf_state_offset_for_aux(isv
->res
, isv
->res
->aux
.sampler_usages
,
4064 use_ubo_ssbo(struct iris_batch
*batch
,
4065 struct iris_context
*ice
,
4066 struct pipe_shader_buffer
*buf
,
4067 struct iris_state_ref
*surf_state
,
4071 return use_null_surface(batch
, ice
);
4073 iris_use_pinned_bo(batch
, iris_resource_bo(buf
->buffer
), writable
);
4074 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
4076 return surf_state
->offset
;
4080 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
4081 struct iris_shader_state
*shs
, int i
)
4083 struct iris_image_view
*iv
= &shs
->image
[i
];
4084 struct iris_resource
*res
= (void *) iv
->base
.resource
;
4087 return use_null_surface(batch
, ice
);
4089 bool write
= iv
->base
.shader_access
& PIPE_IMAGE_ACCESS_WRITE
;
4091 iris_use_pinned_bo(batch
, res
->bo
, write
);
4092 iris_use_pinned_bo(batch
, iris_resource_bo(iv
->surface_state
.res
), false);
4095 iris_use_pinned_bo(batch
, res
->aux
.bo
, write
);
4097 return iv
->surface_state
.offset
;
4100 #define push_bt_entry(addr) \
4101 assert(addr >= binder_addr); \
4102 assert(s < shader->bt.size_bytes / sizeof(uint32_t)); \
4103 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
4105 #define bt_assert(section, exists) \
4106 if (!pin_only) assert(shader->bt.section == (exists) ? s : 0xd0d0d0d0)
4109 * Populate the binding table for a given shader stage.
4111 * This fills out the table of pointers to surfaces required by the shader,
4112 * and also adds those buffers to the validation list so the kernel can make
4113 * resident before running our batch.
4116 iris_populate_binding_table(struct iris_context
*ice
,
4117 struct iris_batch
*batch
,
4118 gl_shader_stage stage
,
4121 const struct iris_binder
*binder
= &ice
->state
.binder
;
4122 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
4123 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4127 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4128 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4129 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
4131 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
4132 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
4135 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
4137 /* TCS passthrough doesn't need a binding table. */
4138 assert(stage
== MESA_SHADER_TESS_CTRL
);
4142 if (stage
== MESA_SHADER_COMPUTE
) {
4143 /* surface for gl_NumWorkGroups */
4144 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
4145 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
4146 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
4147 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
4148 push_bt_entry(grid_state
->offset
);
4151 if (stage
== MESA_SHADER_FRAGMENT
) {
4152 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4153 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
4154 if (cso_fb
->nr_cbufs
) {
4155 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
4157 if (cso_fb
->cbufs
[i
]) {
4158 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
], true,
4159 ice
->state
.draw_aux_usage
[i
]);
4161 addr
= use_null_fb_surface(batch
, ice
);
4163 push_bt_entry(addr
);
4166 uint32_t addr
= use_null_fb_surface(batch
, ice
);
4167 push_bt_entry(addr
);
4171 unsigned num_textures
= util_last_bit(info
->textures_used
);
4173 bt_assert(texture_start
, num_textures
> 0);
4175 for (int i
= 0; i
< num_textures
; i
++) {
4176 struct iris_sampler_view
*view
= shs
->textures
[i
];
4177 uint32_t addr
= view
? use_sampler_view(ice
, batch
, view
)
4178 : use_null_surface(batch
, ice
);
4179 push_bt_entry(addr
);
4182 bt_assert(image_start
, info
->num_images
> 0);
4184 for (int i
= 0; i
< info
->num_images
; i
++) {
4185 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
4186 push_bt_entry(addr
);
4189 bt_assert(ubo_start
, shader
->num_cbufs
> 0);
4191 for (int i
= 0; i
< shader
->num_cbufs
; i
++) {
4192 uint32_t addr
= use_ubo_ssbo(batch
, ice
, &shs
->constbuf
[i
],
4193 &shs
->constbuf_surf_state
[i
], false);
4194 push_bt_entry(addr
);
4197 if (ish
->const_data
) {
4198 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data
), false);
4199 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data_state
.res
),
4201 uint32_t addr
= ish
->const_data_state
.offset
;
4202 push_bt_entry(addr
);
4205 bt_assert(ssbo_start
, info
->num_abos
+ info
->num_ssbos
> 0);
4207 /* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
4208 * for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
4209 * in st_atom_storagebuf.c so it'll compact them into one range, with
4210 * SSBOs starting at info->num_abos. Ideally it'd reset num_abos to 0 too
4212 if (info
->num_abos
+ info
->num_ssbos
> 0) {
4213 for (int i
= 0; i
< IRIS_MAX_ABOS
+ info
->num_ssbos
; i
++) {
4215 use_ubo_ssbo(batch
, ice
, &shs
->ssbo
[i
], &shs
->ssbo_surf_state
[i
],
4216 shs
->writable_ssbos
& (1u << i
));
4217 push_bt_entry(addr
);
4222 /* XXX: YUV surfaces not implemented yet */
4223 bt_assert(plane_start
[1], ...);
4224 bt_assert(plane_start
[2], ...);
4229 iris_use_optional_res(struct iris_batch
*batch
,
4230 struct pipe_resource
*res
,
4234 struct iris_bo
*bo
= iris_resource_bo(res
);
4235 iris_use_pinned_bo(batch
, bo
, writeable
);
4240 pin_depth_and_stencil_buffers(struct iris_batch
*batch
,
4241 struct pipe_surface
*zsbuf
,
4242 struct iris_depth_stencil_alpha_state
*cso_zsa
)
4247 struct iris_resource
*zres
, *sres
;
4248 iris_get_depth_stencil_resources(zsbuf
->texture
, &zres
, &sres
);
4251 iris_use_pinned_bo(batch
, zres
->bo
, cso_zsa
->depth_writes_enabled
);
4253 iris_use_pinned_bo(batch
, zres
->aux
.bo
,
4254 cso_zsa
->depth_writes_enabled
);
4259 iris_use_pinned_bo(batch
, sres
->bo
, cso_zsa
->stencil_writes_enabled
);
4263 /* ------------------------------------------------------------------- */
4266 * Pin any BOs which were installed by a previous batch, and restored
4267 * via the hardware logical context mechanism.
4269 * We don't need to re-emit all state every batch - the hardware context
4270 * mechanism will save and restore it for us. This includes pointers to
4271 * various BOs...which won't exist unless we ask the kernel to pin them
4272 * by adding them to the validation list.
4274 * We can skip buffers if we've re-emitted those packets, as we're
4275 * overwriting those stale pointers with new ones, and don't actually
4276 * refer to the old BOs.
4279 iris_restore_render_saved_bos(struct iris_context
*ice
,
4280 struct iris_batch
*batch
,
4281 const struct pipe_draw_info
*draw
)
4283 struct iris_genx_state
*genx
= ice
->state
.genx
;
4285 const uint64_t clean
= ~ice
->state
.dirty
;
4287 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
4288 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
4291 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4292 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
4295 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
4296 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
4299 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4300 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
4303 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
4304 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
4307 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
4308 for (int i
= 0; i
< 4; i
++) {
4309 struct iris_stream_output_target
*tgt
=
4310 (void *) ice
->state
.so_target
[i
];
4312 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4314 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4320 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4321 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4324 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4325 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4330 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4332 for (int i
= 0; i
< 4; i
++) {
4333 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4335 if (range
->length
== 0)
4338 /* Range block is a binding table index, map back to UBO index. */
4339 unsigned block_index
= range
->block
- shader
->bt
.ubo_start
;
4341 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4342 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4345 iris_use_pinned_bo(batch
, res
->bo
, false);
4347 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4351 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4352 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4353 /* Re-pin any buffers referred to by the binding table. */
4354 iris_populate_binding_table(ice
, batch
, stage
, true);
4358 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4359 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4360 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4362 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4365 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4366 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
4367 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4370 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4371 iris_use_pinned_bo(batch
, bo
, false);
4373 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4375 if (prog_data
->total_scratch
> 0) {
4376 struct iris_bo
*bo
=
4377 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4378 iris_use_pinned_bo(batch
, bo
, true);
4384 if ((clean
& IRIS_DIRTY_DEPTH_BUFFER
) &&
4385 (clean
& IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
4386 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4387 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
4390 if (draw
->index_size
== 0 && ice
->state
.last_res
.index_buffer
) {
4391 /* This draw didn't emit a new index buffer, so we are inheriting the
4392 * older index buffer. This draw didn't need it, but future ones may.
4394 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4395 iris_use_pinned_bo(batch
, bo
, false);
4398 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4399 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4401 const int i
= u_bit_scan64(&bound
);
4402 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
4403 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4409 iris_restore_compute_saved_bos(struct iris_context
*ice
,
4410 struct iris_batch
*batch
,
4411 const struct pipe_grid_info
*grid
)
4413 const uint64_t clean
= ~ice
->state
.dirty
;
4415 const int stage
= MESA_SHADER_COMPUTE
;
4416 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4418 if (clean
& IRIS_DIRTY_CONSTANTS_CS
) {
4419 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4422 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4423 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[0];
4425 if (range
->length
> 0) {
4426 /* Range block is a binding table index, map back to UBO index. */
4427 unsigned block_index
= range
->block
- shader
->bt
.ubo_start
;
4429 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4430 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4433 iris_use_pinned_bo(batch
, res
->bo
, false);
4435 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4440 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
4441 /* Re-pin any buffers referred to by the binding table. */
4442 iris_populate_binding_table(ice
, batch
, stage
, true);
4445 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
4447 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
4449 if (clean
& IRIS_DIRTY_CS
) {
4450 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4453 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4454 iris_use_pinned_bo(batch
, bo
, false);
4456 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4458 if (prog_data
->total_scratch
> 0) {
4459 struct iris_bo
*bo
=
4460 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4461 iris_use_pinned_bo(batch
, bo
, true);
4468 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
4471 iris_update_surface_base_address(struct iris_batch
*batch
,
4472 struct iris_binder
*binder
)
4474 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
4477 flush_for_state_base_change(batch
);
4479 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
4480 sba
.SurfaceStateMOCS
= MOCS_WB
;
4481 sba
.SurfaceStateBaseAddressModifyEnable
= true;
4482 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
4485 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
4489 iris_upload_dirty_render_state(struct iris_context
*ice
,
4490 struct iris_batch
*batch
,
4491 const struct pipe_draw_info
*draw
)
4493 const uint64_t dirty
= ice
->state
.dirty
;
4495 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
4498 struct iris_genx_state
*genx
= ice
->state
.genx
;
4499 struct iris_binder
*binder
= &ice
->state
.binder
;
4500 struct brw_wm_prog_data
*wm_prog_data
= (void *)
4501 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
4503 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
4504 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4505 uint32_t cc_vp_address
;
4507 /* XXX: could avoid streaming for depth_clip [0,1] case. */
4508 uint32_t *cc_vp_map
=
4509 stream_state(batch
, ice
->state
.dynamic_uploader
,
4510 &ice
->state
.last_res
.cc_vp
,
4511 4 * ice
->state
.num_viewports
*
4512 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
4513 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4515 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
4516 cso_rast
->clip_halfz
, &zmin
, &zmax
);
4517 if (cso_rast
->depth_clip_near
)
4519 if (cso_rast
->depth_clip_far
)
4522 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
4523 ccv
.MinimumDepth
= zmin
;
4524 ccv
.MaximumDepth
= zmax
;
4527 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
4530 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
4531 ptr
.CCViewportPointer
= cc_vp_address
;
4535 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4536 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4537 uint32_t sf_cl_vp_address
;
4539 stream_state(batch
, ice
->state
.dynamic_uploader
,
4540 &ice
->state
.last_res
.sf_cl_vp
,
4541 4 * ice
->state
.num_viewports
*
4542 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
4544 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4545 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
4546 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
4548 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
4549 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
4550 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
4551 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
4553 calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
4554 state
->scale
[0], state
->scale
[1],
4555 state
->translate
[0], state
->translate
[1],
4556 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
4558 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
4559 vp
.ViewportMatrixElementm00
= state
->scale
[0];
4560 vp
.ViewportMatrixElementm11
= state
->scale
[1];
4561 vp
.ViewportMatrixElementm22
= state
->scale
[2];
4562 vp
.ViewportMatrixElementm30
= state
->translate
[0];
4563 vp
.ViewportMatrixElementm31
= state
->translate
[1];
4564 vp
.ViewportMatrixElementm32
= state
->translate
[2];
4565 vp
.XMinClipGuardband
= gb_xmin
;
4566 vp
.XMaxClipGuardband
= gb_xmax
;
4567 vp
.YMinClipGuardband
= gb_ymin
;
4568 vp
.YMaxClipGuardband
= gb_ymax
;
4569 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
4570 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
4571 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
4572 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
4575 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
4578 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
4579 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
4583 if (dirty
& IRIS_DIRTY_URB
) {
4586 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
4587 if (!ice
->shaders
.prog
[i
]) {
4590 struct brw_vue_prog_data
*vue_prog_data
=
4591 (void *) ice
->shaders
.prog
[i
]->prog_data
;
4592 size
[i
] = vue_prog_data
->urb_entry_size
;
4594 assert(size
[i
] != 0);
4597 genX(emit_urb_setup
)(ice
, batch
, size
,
4598 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
4599 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
);
4602 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
4603 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4604 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4605 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4606 const int header_dwords
= GENX(BLEND_STATE_length
);
4608 /* Always write at least one BLEND_STATE - the final RT message will
4609 * reference BLEND_STATE[0] even if there aren't color writes. There
4610 * may still be alpha testing, computed depth, and so on.
4612 const int rt_dwords
=
4613 MAX2(cso_fb
->nr_cbufs
, 1) * GENX(BLEND_STATE_ENTRY_length
);
4615 uint32_t blend_offset
;
4616 uint32_t *blend_map
=
4617 stream_state(batch
, ice
->state
.dynamic_uploader
,
4618 &ice
->state
.last_res
.blend
,
4619 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4621 uint32_t blend_state_header
;
4622 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4623 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4624 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4627 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4628 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4630 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4631 ptr
.BlendStatePointer
= blend_offset
;
4632 ptr
.BlendStatePointerValid
= true;
4636 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4637 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4639 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4643 stream_state(batch
, ice
->state
.dynamic_uploader
,
4644 &ice
->state
.last_res
.color_calc
,
4645 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4647 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4648 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4649 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4650 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4651 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4652 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4653 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4655 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4656 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4659 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4660 ptr
.ColorCalcStatePointer
= cc_offset
;
4661 ptr
.ColorCalcStatePointerValid
= true;
4665 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4666 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4669 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4670 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4675 if (shs
->cbuf0_needs_upload
)
4676 upload_uniforms(ice
, stage
);
4678 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4680 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4681 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4683 /* The Skylake PRM contains the following restriction:
4685 * "The driver must ensure The following case does not occur
4686 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4687 * buffer 3 read length equal to zero committed followed by a
4688 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4691 * To avoid this, we program the buffers in the highest slots.
4692 * This way, slot 0 is only used if slot 3 is also used.
4696 for (int i
= 3; i
>= 0; i
--) {
4697 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4699 if (range
->length
== 0)
4702 /* Range block is a binding table index, map back to UBO index. */
4703 unsigned block_index
= range
->block
- shader
->bt
.ubo_start
;
4705 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4706 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4708 assert(cbuf
->buffer_offset
% 32 == 0);
4710 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4711 pkt
.ConstantBody
.Buffer
[n
] =
4712 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->buffer_offset
)
4713 : ro_bo(batch
->screen
->workaround_bo
, 0);
4720 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4721 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4722 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4723 ptr
._3DCommandSubOpcode
= 38 + stage
;
4724 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4729 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4730 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4731 iris_populate_binding_table(ice
, batch
, stage
, false);
4735 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4736 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4737 !ice
->shaders
.prog
[stage
])
4740 iris_upload_sampler_states(ice
, stage
);
4742 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4743 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4745 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4747 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4748 ptr
._3DCommandSubOpcode
= 43 + stage
;
4749 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4753 if (ice
->state
.need_border_colors
)
4754 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4756 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4757 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4759 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4760 if (ice
->state
.framebuffer
.samples
> 0)
4761 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4765 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4766 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4767 ms
.SampleMask
= ice
->state
.sample_mask
;
4771 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4772 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4775 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4778 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4779 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4780 iris_use_pinned_bo(batch
, cache
->bo
, false);
4782 if (prog_data
->total_scratch
> 0) {
4783 struct iris_bo
*bo
=
4784 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4785 iris_use_pinned_bo(batch
, bo
, true);
4788 if (stage
== MESA_SHADER_FRAGMENT
&& wm_prog_data
->uses_sample_mask
) {
4789 uint32_t psx_state
[GENX(3DSTATE_PS_EXTRA_length
)] = {0};
4790 uint32_t *shader_psx
= ((uint32_t*)shader
->derived_data
) +
4791 GENX(3DSTATE_PS_length
);
4792 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4794 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), &psx_state
, psx
) {
4795 if (wm_prog_data
->post_depth_coverage
)
4796 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4797 else if (wm_prog_data
->inner_coverage
&& cso
->conservative_rasterization
)
4798 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4800 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4803 iris_batch_emit(batch
, shader
->derived_data
,
4804 sizeof(uint32_t) * GENX(3DSTATE_PS_length
));
4805 iris_emit_merge(batch
,
4808 GENX(3DSTATE_PS_EXTRA_length
));
4811 iris_batch_emit(batch
, shader
->derived_data
,
4812 iris_derived_program_state_size(stage
));
4814 if (stage
== MESA_SHADER_TESS_EVAL
) {
4815 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4816 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4817 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4818 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4819 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4824 if (ice
->state
.streamout_active
) {
4825 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4826 iris_batch_emit(batch
, genx
->so_buffers
,
4827 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4828 for (int i
= 0; i
< 4; i
++) {
4829 struct iris_stream_output_target
*tgt
=
4830 (void *) ice
->state
.so_target
[i
];
4833 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4835 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4841 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
4842 uint32_t *decl_list
=
4843 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
4844 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
4847 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4848 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4850 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
4851 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
4852 sol
.SOFunctionEnable
= true;
4853 sol
.SOStatisticsEnable
= true;
4855 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
4856 !ice
->state
.prims_generated_query_active
;
4857 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
4860 assert(ice
->state
.streamout
);
4862 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
4863 GENX(3DSTATE_STREAMOUT_length
));
4866 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4867 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
4871 if (dirty
& IRIS_DIRTY_CLIP
) {
4872 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4873 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4875 bool gs_or_tes
= ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] ||
4876 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
4877 bool points_or_lines
= cso_rast
->fill_mode_point_or_line
||
4878 (gs_or_tes
? ice
->shaders
.output_topology_is_points_or_lines
4879 : ice
->state
.prim_is_points_or_lines
);
4881 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
4882 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
4883 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4884 cl
.ClipMode
= cso_rast
->rasterizer_discard
? CLIPMODE_REJECT_ALL
4886 cl
.ViewportXYClipTestEnable
= !points_or_lines
;
4888 if (wm_prog_data
->barycentric_interp_modes
&
4889 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
4890 cl
.NonPerspectiveBarycentricEnable
= true;
4892 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
4893 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
4895 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
4896 ARRAY_SIZE(cso_rast
->clip
));
4899 if (dirty
& IRIS_DIRTY_RASTER
) {
4900 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4901 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
4902 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
4906 if (dirty
& IRIS_DIRTY_WM
) {
4907 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4908 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
4910 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
4911 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4913 wm
.BarycentricInterpolationMode
=
4914 wm_prog_data
->barycentric_interp_modes
;
4916 if (wm_prog_data
->early_fragment_tests
)
4917 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
4918 else if (wm_prog_data
->has_side_effects
)
4919 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
4921 /* We could skip this bit if color writes are enabled. */
4922 if (wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
)
4923 wm
.ForceThreadDispatchEnable
= ForceON
;
4925 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
4928 if (dirty
& IRIS_DIRTY_SBE
) {
4929 iris_emit_sbe(batch
, ice
);
4932 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
4933 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4934 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4935 const struct shader_info
*fs_info
=
4936 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
4938 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
4939 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
4940 pb
.HasWriteableRT
= has_writeable_rt(cso_blend
, fs_info
);
4941 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4943 /* The dual source blending docs caution against using SRC1 factors
4944 * when the shader doesn't use a dual source render target write.
4945 * Empirically, this can lead to GPU hangs, and the results are
4946 * undefined anyway, so simply disable blending to avoid the hang.
4948 pb
.ColorBufferBlendEnable
= (cso_blend
->blend_enables
& 1) &&
4949 (!cso_blend
->dual_color_blending
|| wm_prog_data
->dual_src_blend
);
4952 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
4953 ARRAY_SIZE(cso_blend
->ps_blend
));
4956 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
4957 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4959 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4960 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
4961 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
4962 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4963 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4965 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
4967 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
4971 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
4972 uint32_t scissor_offset
=
4973 emit_state(batch
, ice
->state
.dynamic_uploader
,
4974 &ice
->state
.last_res
.scissor
,
4975 ice
->state
.scissors
,
4976 sizeof(struct pipe_scissor_state
) *
4977 ice
->state
.num_viewports
, 32);
4979 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
4980 ptr
.ScissorRectPointer
= scissor_offset
;
4984 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
4985 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
4987 /* Do not emit the clear params yets. We need to update the clear value
4990 uint32_t clear_length
= GENX(3DSTATE_CLEAR_PARAMS_length
) * 4;
4991 uint32_t cso_z_size
= sizeof(cso_z
->packets
) - clear_length
;
4992 iris_batch_emit(batch
, cso_z
->packets
, cso_z_size
);
4994 union isl_color_value clear_value
= { .f32
= { 0, } };
4996 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4997 if (cso_fb
->zsbuf
) {
4998 struct iris_resource
*zres
, *sres
;
4999 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
5001 if (zres
&& zres
->aux
.bo
)
5002 clear_value
= iris_resource_get_clear_color(zres
, NULL
, NULL
);
5005 uint32_t clear_params
[GENX(3DSTATE_CLEAR_PARAMS_length
)];
5006 iris_pack_command(GENX(3DSTATE_CLEAR_PARAMS
), clear_params
, clear
) {
5007 clear
.DepthClearValueValid
= true;
5008 clear
.DepthClearValue
= clear_value
.f32
[0];
5010 iris_batch_emit(batch
, clear_params
, clear_length
);
5013 if (dirty
& (IRIS_DIRTY_DEPTH_BUFFER
| IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
5014 /* Listen for buffer changes, and also write enable changes. */
5015 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5016 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
5019 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
5020 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
5021 for (int i
= 0; i
< 32; i
++) {
5022 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
5027 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
5028 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5029 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
5032 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
5033 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
5034 topo
.PrimitiveTopologyType
=
5035 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
5039 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
5040 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
5041 int dynamic_bound
= ice
->state
.bound_vertex_buffers
;
5043 if (ice
->state
.vs_uses_draw_params
) {
5044 if (ice
->draw
.draw_params_offset
== 0) {
5045 u_upload_data(ice
->state
.dynamic_uploader
, 0, sizeof(ice
->draw
.params
),
5046 4, &ice
->draw
.params
, &ice
->draw
.draw_params_offset
,
5047 &ice
->draw
.draw_params_res
);
5049 assert(ice
->draw
.draw_params_res
);
5051 struct iris_vertex_buffer_state
*state
=
5052 &(ice
->state
.genx
->vertex_buffers
[count
]);
5053 pipe_resource_reference(&state
->resource
, ice
->draw
.draw_params_res
);
5054 struct iris_resource
*res
= (void *) state
->resource
;
5056 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
5057 vb
.VertexBufferIndex
= count
;
5058 vb
.AddressModifyEnable
= true;
5060 vb
.BufferSize
= res
->bo
->size
- ice
->draw
.draw_params_offset
;
5061 vb
.BufferStartingAddress
=
5062 ro_bo(NULL
, res
->bo
->gtt_offset
+
5063 (int) ice
->draw
.draw_params_offset
);
5064 vb
.MOCS
= mocs(res
->bo
);
5066 dynamic_bound
|= 1ull << count
;
5070 if (ice
->state
.vs_uses_derived_draw_params
) {
5071 u_upload_data(ice
->state
.dynamic_uploader
, 0,
5072 sizeof(ice
->draw
.derived_params
), 4,
5073 &ice
->draw
.derived_params
,
5074 &ice
->draw
.derived_draw_params_offset
,
5075 &ice
->draw
.derived_draw_params_res
);
5077 struct iris_vertex_buffer_state
*state
=
5078 &(ice
->state
.genx
->vertex_buffers
[count
]);
5079 pipe_resource_reference(&state
->resource
,
5080 ice
->draw
.derived_draw_params_res
);
5081 struct iris_resource
*res
= (void *) ice
->draw
.derived_draw_params_res
;
5083 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
5084 vb
.VertexBufferIndex
= count
;
5085 vb
.AddressModifyEnable
= true;
5088 res
->bo
->size
- ice
->draw
.derived_draw_params_offset
;
5089 vb
.BufferStartingAddress
=
5090 ro_bo(NULL
, res
->bo
->gtt_offset
+
5091 (int) ice
->draw
.derived_draw_params_offset
);
5092 vb
.MOCS
= mocs(res
->bo
);
5094 dynamic_bound
|= 1ull << count
;
5099 /* The VF cache designers cut corners, and made the cache key's
5100 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
5101 * 32 bits of the address. If you have two vertex buffers which get
5102 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
5103 * you can get collisions (even within a single batch).
5105 * So, we need to do a VF cache invalidate if the buffer for a VB
5106 * slot slot changes [48:32] address bits from the previous time.
5108 unsigned flush_flags
= 0;
5110 uint64_t bound
= dynamic_bound
;
5112 const int i
= u_bit_scan64(&bound
);
5113 uint16_t high_bits
= 0;
5115 struct iris_resource
*res
=
5116 (void *) genx
->vertex_buffers
[i
].resource
;
5118 iris_use_pinned_bo(batch
, res
->bo
, false);
5120 high_bits
= res
->bo
->gtt_offset
>> 32ull;
5121 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
5122 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5123 PIPE_CONTROL_CS_STALL
;
5124 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
5130 iris_emit_pipe_control_flush(batch
, flush_flags
);
5132 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
5135 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
5136 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
5137 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
5141 bound
= dynamic_bound
;
5143 const int i
= u_bit_scan64(&bound
);
5144 memcpy(map
, genx
->vertex_buffers
[i
].state
,
5145 sizeof(uint32_t) * vb_dwords
);
5151 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
5152 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5153 const unsigned entries
= MAX2(cso
->count
, 1);
5154 if (!(ice
->state
.vs_needs_sgvs_element
||
5155 ice
->state
.vs_uses_derived_draw_params
||
5156 ice
->state
.vs_needs_edge_flag
)) {
5157 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
5158 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
5160 uint32_t dynamic_ves
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
5161 const unsigned dyn_count
= cso
->count
+
5162 ice
->state
.vs_needs_sgvs_element
+
5163 ice
->state
.vs_uses_derived_draw_params
;
5165 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
),
5168 1 + GENX(VERTEX_ELEMENT_STATE_length
) * dyn_count
- 2;
5170 memcpy(&dynamic_ves
[1], &cso
->vertex_elements
[1],
5171 (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5172 GENX(VERTEX_ELEMENT_STATE_length
) * sizeof(uint32_t));
5173 uint32_t *ve_pack_dest
=
5174 &dynamic_ves
[1 + (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5175 GENX(VERTEX_ELEMENT_STATE_length
)];
5177 if (ice
->state
.vs_needs_sgvs_element
) {
5178 uint32_t base_ctrl
= ice
->state
.vs_uses_draw_params
?
5179 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
5180 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5182 ve
.VertexBufferIndex
=
5183 util_bitcount64(ice
->state
.bound_vertex_buffers
);
5184 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5185 ve
.Component0Control
= base_ctrl
;
5186 ve
.Component1Control
= base_ctrl
;
5187 ve
.Component2Control
= VFCOMP_STORE_0
;
5188 ve
.Component3Control
= VFCOMP_STORE_0
;
5190 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5192 if (ice
->state
.vs_uses_derived_draw_params
) {
5193 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5195 ve
.VertexBufferIndex
=
5196 util_bitcount64(ice
->state
.bound_vertex_buffers
) +
5197 ice
->state
.vs_uses_draw_params
;
5198 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5199 ve
.Component0Control
= VFCOMP_STORE_SRC
;
5200 ve
.Component1Control
= VFCOMP_STORE_SRC
;
5201 ve
.Component2Control
= VFCOMP_STORE_0
;
5202 ve
.Component3Control
= VFCOMP_STORE_0
;
5204 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5206 if (ice
->state
.vs_needs_edge_flag
) {
5207 for (int i
= 0; i
< GENX(VERTEX_ELEMENT_STATE_length
); i
++)
5208 ve_pack_dest
[i
] = cso
->edgeflag_ve
[i
];
5211 iris_batch_emit(batch
, &dynamic_ves
, sizeof(uint32_t) *
5212 (1 + dyn_count
* GENX(VERTEX_ELEMENT_STATE_length
)));
5215 if (!ice
->state
.vs_needs_edge_flag
) {
5216 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
5217 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5219 assert(cso
->count
> 0);
5220 const unsigned edgeflag_index
= cso
->count
- 1;
5221 uint32_t dynamic_vfi
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
5222 memcpy(&dynamic_vfi
[0], cso
->vf_instancing
, edgeflag_index
*
5223 GENX(3DSTATE_VF_INSTANCING_length
) * sizeof(uint32_t));
5225 uint32_t *vfi_pack_dest
= &dynamic_vfi
[0] +
5226 edgeflag_index
* GENX(3DSTATE_VF_INSTANCING_length
);
5227 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
5228 vi
.VertexElementIndex
= edgeflag_index
+
5229 ice
->state
.vs_needs_sgvs_element
+
5230 ice
->state
.vs_uses_derived_draw_params
;
5232 for (int i
= 0; i
< GENX(3DSTATE_VF_INSTANCING_length
); i
++)
5233 vfi_pack_dest
[i
] |= cso
->edgeflag_vfi
[i
];
5235 iris_batch_emit(batch
, &dynamic_vfi
[0], sizeof(uint32_t) *
5236 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5240 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
5241 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
5242 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
5243 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5245 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
5246 if (vs_prog_data
->uses_vertexid
) {
5247 sgv
.VertexIDEnable
= true;
5248 sgv
.VertexIDComponentNumber
= 2;
5249 sgv
.VertexIDElementOffset
=
5250 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5253 if (vs_prog_data
->uses_instanceid
) {
5254 sgv
.InstanceIDEnable
= true;
5255 sgv
.InstanceIDComponentNumber
= 3;
5256 sgv
.InstanceIDElementOffset
=
5257 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5262 if (dirty
& IRIS_DIRTY_VF
) {
5263 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
5264 if (draw
->primitive_restart
) {
5265 vf
.IndexedDrawCutIndexEnable
= true;
5266 vf
.CutIndex
= draw
->restart_index
;
5271 if (dirty
& IRIS_DIRTY_VF_STATISTICS
) {
5272 iris_emit_cmd(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
5273 vf
.StatisticsEnable
= true;
5277 /* TODO: Gen8 PMA fix */
5281 iris_upload_render_state(struct iris_context
*ice
,
5282 struct iris_batch
*batch
,
5283 const struct pipe_draw_info
*draw
)
5285 bool use_predicate
= ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
5287 /* Always pin the binder. If we're emitting new binding table pointers,
5288 * we need it. If not, we're probably inheriting old tables via the
5289 * context, and need it anyway. Since true zero-bindings cases are
5290 * practically non-existent, just pin it and avoid last_res tracking.
5292 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5294 if (!batch
->contains_draw
) {
5295 iris_restore_render_saved_bos(ice
, batch
, draw
);
5296 batch
->contains_draw
= true;
5299 iris_upload_dirty_render_state(ice
, batch
, draw
);
5301 if (draw
->index_size
> 0) {
5304 if (draw
->has_user_indices
) {
5305 u_upload_data(ice
->ctx
.stream_uploader
, 0,
5306 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
5307 &offset
, &ice
->state
.last_res
.index_buffer
);
5309 struct iris_resource
*res
= (void *) draw
->index
.resource
;
5310 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
5312 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
5313 draw
->index
.resource
);
5317 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
5319 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
5320 ib
.IndexFormat
= draw
->index_size
>> 1;
5322 ib
.BufferSize
= bo
->size
- offset
;
5323 ib
.BufferStartingAddress
= ro_bo(bo
, offset
);
5326 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
5327 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
5328 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
5329 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5330 PIPE_CONTROL_CS_STALL
);
5331 ice
->state
.last_index_bo_high_bits
= high_bits
;
5335 #define _3DPRIM_END_OFFSET 0x2420
5336 #define _3DPRIM_START_VERTEX 0x2430
5337 #define _3DPRIM_VERTEX_COUNT 0x2434
5338 #define _3DPRIM_INSTANCE_COUNT 0x2438
5339 #define _3DPRIM_START_INSTANCE 0x243C
5340 #define _3DPRIM_BASE_VERTEX 0x2440
5342 if (draw
->indirect
) {
5343 if (draw
->indirect
->indirect_draw_count
) {
5344 use_predicate
= true;
5346 struct iris_bo
*draw_count_bo
=
5347 iris_resource_bo(draw
->indirect
->indirect_draw_count
);
5348 unsigned draw_count_offset
=
5349 draw
->indirect
->indirect_draw_count_offset
;
5351 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_FLUSH_ENABLE
);
5353 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
) {
5354 static const uint32_t math
[] = {
5356 /* Compute (draw index < draw count).
5357 * We do this by subtracting and storing the carry bit.
5359 MI_ALU2(LOAD
, SRCA
, R0
),
5360 MI_ALU2(LOAD
, SRCB
, R1
),
5362 MI_ALU2(STORE
, R3
, CF
),
5363 /* Compute (subtracting result & MI_PREDICATE). */
5364 MI_ALU2(LOAD
, SRCA
, R3
),
5365 MI_ALU2(LOAD
, SRCB
, R2
),
5367 MI_ALU2(STORE
, R3
, ACCU
),
5370 /* Upload the current draw count from the draw parameters
5373 ice
->vtbl
.load_register_mem32(batch
, CS_GPR(1), draw_count_bo
,
5375 /* Zero the top 32-bits of GPR1. */
5376 ice
->vtbl
.load_register_imm32(batch
, CS_GPR(1) + 4, 0);
5377 /* Upload the id of the current primitive to GPR0. */
5378 ice
->vtbl
.load_register_imm64(batch
, CS_GPR(0), draw
->drawid
);
5380 iris_batch_emit(batch
, math
, sizeof(math
));
5382 /* Store result of MI_MATH computations to MI_PREDICATE_RESULT. */
5383 ice
->vtbl
.load_register_reg64(batch
,
5384 MI_PREDICATE_RESULT
, CS_GPR(3));
5386 uint32_t mi_predicate
;
5388 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
5389 ice
->vtbl
.load_register_imm64(batch
, MI_PREDICATE_SRC1
,
5391 /* Upload the current draw count from the draw parameters buffer
5392 * to MI_PREDICATE_SRC0.
5394 ice
->vtbl
.load_register_mem32(batch
, MI_PREDICATE_SRC0
,
5395 draw_count_bo
, draw_count_offset
);
5396 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
5397 ice
->vtbl
.load_register_imm32(batch
, MI_PREDICATE_SRC0
+ 4, 0);
5399 if (draw
->drawid
== 0) {
5400 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
5401 MI_PREDICATE_COMBINEOP_SET
|
5402 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
5404 /* While draw_index < draw_count the predicate's result will be
5405 * (draw_index == draw_count) ^ TRUE = TRUE
5406 * When draw_index == draw_count the result is
5407 * (TRUE) ^ TRUE = FALSE
5408 * After this all results will be:
5409 * (FALSE) ^ FALSE = FALSE
5411 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOAD
|
5412 MI_PREDICATE_COMBINEOP_XOR
|
5413 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
5415 iris_batch_emit(batch
, &mi_predicate
, sizeof(uint32_t));
5418 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
5421 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5422 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
5423 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
5425 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5426 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
5427 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
5429 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5430 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
5431 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
5433 if (draw
->index_size
) {
5434 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5435 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
5436 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5438 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5439 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5440 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
5443 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5444 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5445 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5447 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
5448 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
5452 } else if (draw
->count_from_stream_output
) {
5453 struct iris_stream_output_target
*so
=
5454 (void *) draw
->count_from_stream_output
;
5456 /* XXX: Replace with actual cache tracking */
5457 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
5459 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5460 lrm
.RegisterAddress
= CS_GPR(0);
5462 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
5464 if (so
->base
.buffer_offset
)
5465 iris_math_add32_gpr0(ice
, batch
, -so
->base
.buffer_offset
);
5466 iris_math_div32_gpr0(ice
, batch
, so
->stride
);
5467 _iris_emit_lrr(batch
, _3DPRIM_VERTEX_COUNT
, CS_GPR(0));
5469 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
5470 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
5471 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
5472 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
5475 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
5476 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
5477 prim
.PredicateEnable
= use_predicate
;
5479 if (draw
->indirect
|| draw
->count_from_stream_output
) {
5480 prim
.IndirectParameterEnable
= true;
5482 prim
.StartInstanceLocation
= draw
->start_instance
;
5483 prim
.InstanceCount
= draw
->instance_count
;
5484 prim
.VertexCountPerInstance
= draw
->count
;
5486 // XXX: this is probably bonkers.
5487 prim
.StartVertexLocation
= draw
->start
;
5489 if (draw
->index_size
) {
5490 prim
.BaseVertexLocation
+= draw
->index_bias
;
5492 prim
.StartVertexLocation
+= draw
->index_bias
;
5495 //prim.BaseVertexLocation = ...;
5501 iris_upload_compute_state(struct iris_context
*ice
,
5502 struct iris_batch
*batch
,
5503 const struct pipe_grid_info
*grid
)
5505 const uint64_t dirty
= ice
->state
.dirty
;
5506 struct iris_screen
*screen
= batch
->screen
;
5507 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
5508 struct iris_binder
*binder
= &ice
->state
.binder
;
5509 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
5510 struct iris_compiled_shader
*shader
=
5511 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
5512 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5513 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
5515 /* Always pin the binder. If we're emitting new binding table pointers,
5516 * we need it. If not, we're probably inheriting old tables via the
5517 * context, and need it anyway. Since true zero-bindings cases are
5518 * practically non-existent, just pin it and avoid last_res tracking.
5520 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5522 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->cbuf0_needs_upload
)
5523 upload_uniforms(ice
, MESA_SHADER_COMPUTE
);
5525 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
5526 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
5528 if (dirty
& IRIS_DIRTY_SAMPLER_STATES_CS
)
5529 iris_upload_sampler_states(ice
, MESA_SHADER_COMPUTE
);
5531 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
5532 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
5534 if (ice
->state
.need_border_colors
)
5535 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
5537 if (dirty
& IRIS_DIRTY_CS
) {
5538 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
5540 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
5541 * the only bits that are changed are scoreboard related: Scoreboard
5542 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
5543 * these scoreboard related states, a MEDIA_STATE_FLUSH is
5546 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
5548 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
5549 if (prog_data
->total_scratch
) {
5550 struct iris_bo
*bo
=
5551 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
5552 MESA_SHADER_COMPUTE
);
5553 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
5554 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
5557 vfe
.MaximumNumberofThreads
=
5558 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
5560 vfe
.ResetGatewayTimer
=
5561 Resettingrelativetimerandlatchingtheglobaltimestamp
;
5564 vfe
.BypassGatewayControl
= true;
5566 vfe
.NumberofURBEntries
= 2;
5567 vfe
.URBEntryAllocationSize
= 2;
5569 vfe
.CURBEAllocationSize
=
5570 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
5571 cs_prog_data
->push
.cross_thread
.regs
, 2);
5575 /* TODO: Combine subgroup-id with cbuf0 so we can push regular uniforms */
5576 uint32_t curbe_data_offset
= 0;
5577 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
5578 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
5579 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
5580 struct pipe_resource
*curbe_data_res
= NULL
;
5581 uint32_t *curbe_data_map
=
5582 stream_state(batch
, ice
->state
.dynamic_uploader
, &curbe_data_res
,
5583 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
5584 &curbe_data_offset
);
5585 assert(curbe_data_map
);
5586 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
5587 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
5589 if (dirty
& IRIS_DIRTY_CONSTANTS_CS
) {
5590 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
5591 curbe
.CURBETotalDataLength
=
5592 ALIGN(cs_prog_data
->push
.total
.size
, 64);
5593 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
5597 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
5598 IRIS_DIRTY_BINDINGS_CS
|
5599 IRIS_DIRTY_CONSTANTS_CS
|
5601 struct pipe_resource
*desc_res
= NULL
;
5602 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
5604 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
5605 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
5606 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
5609 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
5610 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
5612 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
5613 load
.InterfaceDescriptorTotalLength
=
5614 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
5615 load
.InterfaceDescriptorDataStartAddress
=
5616 emit_state(batch
, ice
->state
.dynamic_uploader
,
5617 &desc_res
, desc
, sizeof(desc
), 32);
5620 pipe_resource_reference(&desc_res
, NULL
);
5623 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
5624 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
5625 uint32_t right_mask
;
5628 right_mask
= ~0u >> (32 - remainder
);
5630 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
5632 #define GPGPU_DISPATCHDIMX 0x2500
5633 #define GPGPU_DISPATCHDIMY 0x2504
5634 #define GPGPU_DISPATCHDIMZ 0x2508
5636 if (grid
->indirect
) {
5637 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
5638 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
5639 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5640 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
5641 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
5643 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5644 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
5645 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
5647 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5648 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
5649 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
5653 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
5654 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
5655 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
5656 ggw
.ThreadDepthCounterMaximum
= 0;
5657 ggw
.ThreadHeightCounterMaximum
= 0;
5658 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
5659 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
5660 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
5661 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
5662 ggw
.RightExecutionMask
= right_mask
;
5663 ggw
.BottomExecutionMask
= 0xffffffff;
5666 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
5668 if (!batch
->contains_draw
) {
5669 iris_restore_compute_saved_bos(ice
, batch
, grid
);
5670 batch
->contains_draw
= true;
5675 * State module teardown.
5678 iris_destroy_state(struct iris_context
*ice
)
5680 struct iris_genx_state
*genx
= ice
->state
.genx
;
5682 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5684 const int i
= u_bit_scan64(&bound_vbs
);
5685 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
5687 free(ice
->state
.genx
);
5689 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
5690 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
5692 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
5694 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
5695 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5696 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
5697 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
5698 pipe_resource_reference(&shs
->constbuf
[i
].buffer
, NULL
);
5699 pipe_resource_reference(&shs
->constbuf_surf_state
[i
].res
, NULL
);
5701 for (int i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
5702 pipe_resource_reference(&shs
->image
[i
].base
.resource
, NULL
);
5703 pipe_resource_reference(&shs
->image
[i
].surface_state
.res
, NULL
);
5705 for (int i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
5706 pipe_resource_reference(&shs
->ssbo
[i
].buffer
, NULL
);
5707 pipe_resource_reference(&shs
->ssbo_surf_state
[i
].res
, NULL
);
5709 for (int i
= 0; i
< IRIS_MAX_TEXTURE_SAMPLERS
; i
++) {
5710 pipe_sampler_view_reference((struct pipe_sampler_view
**)
5711 &shs
->textures
[i
], NULL
);
5715 pipe_resource_reference(&ice
->state
.grid_size
.res
, NULL
);
5716 pipe_resource_reference(&ice
->state
.grid_surf_state
.res
, NULL
);
5718 pipe_resource_reference(&ice
->state
.null_fb
.res
, NULL
);
5719 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
5721 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
5722 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
5723 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
5724 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
5725 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
5726 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
5729 /* ------------------------------------------------------------------- */
5732 iris_rebind_buffer(struct iris_context
*ice
,
5733 struct iris_resource
*res
,
5734 uint64_t old_address
)
5736 struct pipe_context
*ctx
= &ice
->ctx
;
5737 struct iris_screen
*screen
= (void *) ctx
->screen
;
5738 struct iris_genx_state
*genx
= ice
->state
.genx
;
5740 assert(res
->base
.target
== PIPE_BUFFER
);
5742 /* Buffers can't be framebuffer attachments, nor display related,
5743 * and we don't have upstream Clover support.
5745 assert(!(res
->bind_history
& (PIPE_BIND_DEPTH_STENCIL
|
5746 PIPE_BIND_RENDER_TARGET
|
5747 PIPE_BIND_BLENDABLE
|
5748 PIPE_BIND_DISPLAY_TARGET
|
5750 PIPE_BIND_COMPUTE_RESOURCE
|
5751 PIPE_BIND_GLOBAL
)));
5753 if (res
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
5754 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5756 const int i
= u_bit_scan64(&bound_vbs
);
5757 struct iris_vertex_buffer_state
*state
= &genx
->vertex_buffers
[i
];
5759 /* Update the CPU struct */
5760 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_start
) == 32);
5761 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) == 64);
5762 uint64_t *addr
= (uint64_t *) &state
->state
[1];
5764 if (*addr
== old_address
) {
5765 *addr
= res
->bo
->gtt_offset
;
5766 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
5771 /* No need to handle these:
5772 * - PIPE_BIND_INDEX_BUFFER (emitted for every indexed draw)
5773 * - PIPE_BIND_COMMAND_ARGS_BUFFER (emitted for every indirect draw)
5774 * - PIPE_BIND_QUERY_BUFFER (no persistent state references)
5777 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
5778 /* XXX: be careful about resetting vs appending... */
5782 for (int s
= MESA_SHADER_VERTEX
; s
< MESA_SHADER_STAGES
; s
++) {
5783 struct iris_shader_state
*shs
= &ice
->state
.shaders
[s
];
5784 enum pipe_shader_type p_stage
= stage_to_pipe(s
);
5786 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
5787 /* Skip constant buffer 0, it's for regular uniforms, not UBOs */
5788 uint32_t bound_cbufs
= shs
->bound_cbufs
& ~1u;
5789 while (bound_cbufs
) {
5790 const int i
= u_bit_scan(&bound_cbufs
);
5791 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[i
];
5792 struct iris_state_ref
*surf_state
= &shs
->constbuf_surf_state
[i
];
5794 if (res
->bo
== iris_resource_bo(cbuf
->buffer
)) {
5795 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
, surf_state
, false);
5796 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< s
;
5801 if (res
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
5802 uint32_t bound_ssbos
= shs
->bound_ssbos
;
5803 while (bound_ssbos
) {
5804 const int i
= u_bit_scan(&bound_ssbos
);
5805 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[i
];
5807 if (res
->bo
== iris_resource_bo(ssbo
->buffer
)) {
5808 struct pipe_shader_buffer buf
= {
5809 .buffer
= &res
->base
,
5810 .buffer_offset
= ssbo
->buffer_offset
,
5811 .buffer_size
= ssbo
->buffer_size
,
5813 iris_set_shader_buffers(ctx
, p_stage
, i
, 1, &buf
,
5814 (shs
->writable_ssbos
>> i
) & 1);
5819 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
5820 uint32_t bound_sampler_views
= shs
->bound_sampler_views
;
5821 while (bound_sampler_views
) {
5822 const int i
= u_bit_scan(&bound_sampler_views
);
5823 struct iris_sampler_view
*isv
= shs
->textures
[i
];
5825 if (res
->bo
== iris_resource_bo(isv
->base
.texture
)) {
5826 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
5827 &isv
->surface_state
,
5828 isv
->res
->aux
.sampler_usages
);
5830 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
5831 isv
->view
.format
, isv
->view
.swizzle
,
5832 isv
->base
.u
.buf
.offset
,
5833 isv
->base
.u
.buf
.size
);
5834 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< s
;
5839 if (res
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
5840 uint32_t bound_image_views
= shs
->bound_image_views
;
5841 while (bound_image_views
) {
5842 const int i
= u_bit_scan(&bound_image_views
);
5843 struct iris_image_view
*iv
= &shs
->image
[i
];
5845 if (res
->bo
== iris_resource_bo(iv
->base
.resource
)) {
5846 iris_set_shader_images(ctx
, p_stage
, i
, 1, &iv
->base
);
5853 /* ------------------------------------------------------------------- */
5856 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
5859 _iris_emit_lrr(batch
, dst
, src
);
5863 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
5866 _iris_emit_lrr(batch
, dst
, src
);
5867 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
5871 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
5874 _iris_emit_lri(batch
, reg
, val
);
5878 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
5881 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
5882 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
5886 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
5889 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5890 struct iris_bo
*bo
, uint32_t offset
)
5892 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5893 lrm
.RegisterAddress
= reg
;
5894 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
5899 * Load a 64-bit value from a buffer into a MMIO register via
5900 * two MI_LOAD_REGISTER_MEM commands.
5903 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5904 struct iris_bo
*bo
, uint32_t offset
)
5906 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
5907 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
5911 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5912 struct iris_bo
*bo
, uint32_t offset
,
5915 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
5916 srm
.RegisterAddress
= reg
;
5917 srm
.MemoryAddress
= rw_bo(bo
, offset
);
5918 srm
.PredicateEnable
= predicated
;
5923 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5924 struct iris_bo
*bo
, uint32_t offset
,
5927 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
5928 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
5932 iris_store_data_imm32(struct iris_batch
*batch
,
5933 struct iris_bo
*bo
, uint32_t offset
,
5936 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
5937 sdi
.Address
= rw_bo(bo
, offset
);
5938 sdi
.ImmediateData
= imm
;
5943 iris_store_data_imm64(struct iris_batch
*batch
,
5944 struct iris_bo
*bo
, uint32_t offset
,
5947 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
5948 * 2 in genxml but it's actually variable length and we need 5 DWords.
5950 void *map
= iris_get_command_space(batch
, 4 * 5);
5951 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
5952 sdi
.DWordLength
= 5 - 2;
5953 sdi
.Address
= rw_bo(bo
, offset
);
5954 sdi
.ImmediateData
= imm
;
5959 iris_copy_mem_mem(struct iris_batch
*batch
,
5960 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
5961 struct iris_bo
*src_bo
, uint32_t src_offset
,
5964 /* MI_COPY_MEM_MEM operates on DWords. */
5965 assert(bytes
% 4 == 0);
5966 assert(dst_offset
% 4 == 0);
5967 assert(src_offset
% 4 == 0);
5969 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
5970 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
5971 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
5972 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
5977 /* ------------------------------------------------------------------- */
5980 flags_to_post_sync_op(uint32_t flags
)
5982 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
5983 return WriteImmediateData
;
5985 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
5986 return WritePSDepthCount
;
5988 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
5989 return WriteTimestamp
;
5995 * Do the given flags have a Post Sync or LRI Post Sync operation?
5997 static enum pipe_control_flags
5998 get_post_sync_flags(enum pipe_control_flags flags
)
6000 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
6001 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6002 PIPE_CONTROL_WRITE_TIMESTAMP
|
6003 PIPE_CONTROL_LRI_POST_SYNC_OP
;
6005 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
6006 * "LRI Post Sync Operation". So more than one bit set would be illegal.
6008 assert(util_bitcount(flags
) <= 1);
6013 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
6016 * Emit a series of PIPE_CONTROL commands, taking into account any
6017 * workarounds necessary to actually accomplish the caller's request.
6019 * Unless otherwise noted, spec quotations in this function come from:
6021 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
6022 * Restrictions for PIPE_CONTROL.
6024 * You should not use this function directly. Use the helpers in
6025 * iris_pipe_control.c instead, which may split the pipe control further.
6028 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
6029 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
6031 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6032 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
6033 enum pipe_control_flags non_lri_post_sync_flags
=
6034 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
6036 /* Recursive PIPE_CONTROL workarounds --------------------------------
6037 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
6039 * We do these first because we want to look at the original operation,
6040 * rather than any workarounds we set.
6042 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
6043 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
6044 * lists several workarounds:
6046 * "Project: SKL, KBL, BXT
6048 * If the VF Cache Invalidation Enable is set to a 1 in a
6049 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
6050 * sets to 0, with the VF Cache Invalidation Enable set to 0
6051 * needs to be sent prior to the PIPE_CONTROL with VF Cache
6052 * Invalidation Enable set to a 1."
6054 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
6057 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
6058 /* Project: SKL / Argument: LRI Post Sync Operation [23]
6060 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6061 * programmed prior to programming a PIPECONTROL command with "LRI
6062 * Post Sync Operation" in GPGPU mode of operation (i.e when
6063 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
6065 * The same text exists a few rows below for Post Sync Op.
6067 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
6070 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
6072 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
6073 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
6074 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
6076 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
6080 /* "Flush Types" workarounds ---------------------------------------------
6081 * We do these now because they may add post-sync operations or CS stalls.
6084 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
6085 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
6087 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
6088 * 'Write PS Depth Count' or 'Write Timestamp'."
6091 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6092 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6093 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6094 bo
= batch
->screen
->workaround_bo
;
6098 /* #1130 from Gen10 workarounds page:
6100 * "Enable Depth Stall on every Post Sync Op if Render target Cache
6101 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
6102 * board stall if Render target cache flush is enabled."
6104 * Applicable to CNL B0 and C0 steppings only.
6106 * The wording here is unclear, and this workaround doesn't look anything
6107 * like the internal bug report recommendations, but leave it be for now...
6109 if (GEN_GEN
== 10) {
6110 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
6111 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6112 } else if (flags
& non_lri_post_sync_flags
) {
6113 flags
|= PIPE_CONTROL_DEPTH_STALL
;
6117 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
6118 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
6120 * "This bit must be DISABLED for operations other than writing
6123 * This seems like nonsense. An Ivybridge workaround requires us to
6124 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
6125 * operation. Gen8+ requires us to emit depth stalls and depth cache
6126 * flushes together. So, it's hard to imagine this means anything other
6127 * than "we originally intended this to be used for PS_DEPTH_COUNT".
6129 * We ignore the supposed restriction and do nothing.
6133 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6134 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6135 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
6137 * "This bit must be DISABLED for End-of-pipe (Read) fences,
6138 * PS_DEPTH_COUNT or TIMESTAMP queries."
6140 * TODO: Implement end-of-pipe checking.
6142 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6143 PIPE_CONTROL_WRITE_TIMESTAMP
)));
6146 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6147 /* From the PIPE_CONTROL instruction table, bit 1:
6149 * "This bit is ignored if Depth Stall Enable is set.
6150 * Further, the render cache is not flushed even if Write Cache
6151 * Flush Enable bit is set."
6153 * We assert that the caller doesn't do this combination, to try and
6154 * prevent mistakes. It shouldn't hurt the GPU, though.
6156 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
6157 * and "Render Target Flush" combo is explicitly required for BTI
6158 * update workarounds.
6160 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
6161 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
6164 /* PIPE_CONTROL page workarounds ------------------------------------- */
6166 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
6167 /* From the PIPE_CONTROL page itself:
6170 * Restriction: Pipe_control with CS-stall bit set must be issued
6171 * before a pipe-control command that has the State Cache
6172 * Invalidate bit set."
6174 flags
|= PIPE_CONTROL_CS_STALL
;
6177 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
6178 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
6181 * SW must always program Post-Sync Operation to "Write Immediate
6182 * Data" when Flush LLC is set."
6184 * For now, we just require the caller to do it.
6186 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
6189 /* "Post-Sync Operation" workarounds -------------------------------- */
6191 /* Project: All / Argument: Global Snapshot Count Reset [19]
6193 * "This bit must not be exercised on any product.
6194 * Requires stall bit ([20] of DW1) set."
6196 * We don't use this, so we just assert that it isn't used. The
6197 * PIPE_CONTROL instruction page indicates that they intended this
6198 * as a debug feature and don't think it is useful in production,
6199 * but it may actually be usable, should we ever want to.
6201 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
6203 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
6204 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
6205 /* Project: All / Arguments:
6207 * - Generic Media State Clear [16]
6208 * - Indirect State Pointers Disable [16]
6210 * "Requires stall bit ([20] of DW1) set."
6212 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
6213 * State Clear) says:
6215 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6216 * programmed prior to programming a PIPECONTROL command with "Media
6217 * State Clear" set in GPGPU mode of operation"
6219 * This is a subset of the earlier rule, so there's nothing to do.
6221 flags
|= PIPE_CONTROL_CS_STALL
;
6224 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
6225 /* Project: All / Argument: Store Data Index
6227 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6230 * For now, we just assert that the caller does this. We might want to
6231 * automatically add a write to the workaround BO...
6233 assert(non_lri_post_sync_flags
!= 0);
6236 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
6237 /* Project: All / Argument: Sync GFDT
6239 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6240 * than '0' or 0x2520[13] must be set."
6242 * For now, we just assert that the caller does this.
6244 assert(non_lri_post_sync_flags
!= 0);
6247 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
6248 /* Project: IVB+ / Argument: TLB inv
6250 * "Requires stall bit ([20] of DW1) set."
6252 * Also, from the PIPE_CONTROL instruction table:
6255 * Post Sync Operation or CS stall must be set to ensure a TLB
6256 * invalidation occurs. Otherwise no cycle will occur to the TLB
6257 * cache to invalidate."
6259 * This is not a subset of the earlier rule, so there's nothing to do.
6261 flags
|= PIPE_CONTROL_CS_STALL
;
6264 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
6265 /* TODO: The big Skylake GT4 post sync op workaround */
6268 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
6270 if (IS_COMPUTE_PIPELINE(batch
)) {
6271 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
6272 /* Project: SKL+ / Argument: Tex Invalidate
6273 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
6275 flags
|= PIPE_CONTROL_CS_STALL
;
6278 if (GEN_GEN
== 8 && (post_sync_flags
||
6279 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
6280 PIPE_CONTROL_DEPTH_STALL
|
6281 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6282 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6283 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
6284 /* Project: BDW / Arguments:
6286 * - LRI Post Sync Operation [23]
6287 * - Post Sync Op [15:14]
6289 * - Depth Stall [13]
6290 * - Render Target Cache Flush [12]
6291 * - Depth Cache Flush [0]
6292 * - DC Flush Enable [5]
6294 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
6297 flags
|= PIPE_CONTROL_CS_STALL
;
6299 /* Also, from the PIPE_CONTROL instruction table, bit 20:
6302 * This bit must be always set when PIPE_CONTROL command is
6303 * programmed by GPGPU and MEDIA workloads, except for the cases
6304 * when only Read Only Cache Invalidation bits are set (State
6305 * Cache Invalidation Enable, Instruction cache Invalidation
6306 * Enable, Texture Cache Invalidation Enable, Constant Cache
6307 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
6308 * need not implemented when FF_DOP_CG is disable via "Fixed
6309 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
6311 * It sounds like we could avoid CS stalls in some cases, but we
6312 * don't currently bother. This list isn't exactly the list above,
6318 /* "Stall" workarounds ----------------------------------------------
6319 * These have to come after the earlier ones because we may have added
6320 * some additional CS stalls above.
6323 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
6324 /* Project: PRE-SKL, VLV, CHV
6326 * "[All Stepping][All SKUs]:
6328 * One of the following must also be set:
6330 * - Render Target Cache Flush Enable ([12] of DW1)
6331 * - Depth Cache Flush Enable ([0] of DW1)
6332 * - Stall at Pixel Scoreboard ([1] of DW1)
6333 * - Depth Stall ([13] of DW1)
6334 * - Post-Sync Operation ([13] of DW1)
6335 * - DC Flush Enable ([5] of DW1)"
6337 * If we don't already have one of those bits set, we choose to add
6338 * "Stall at Pixel Scoreboard". Some of the other bits require a
6339 * CS stall as a workaround (see above), which would send us into
6340 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
6341 * appears to be safe, so we choose that.
6343 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6344 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6345 PIPE_CONTROL_WRITE_IMMEDIATE
|
6346 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6347 PIPE_CONTROL_WRITE_TIMESTAMP
|
6348 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
6349 PIPE_CONTROL_DEPTH_STALL
|
6350 PIPE_CONTROL_DATA_CACHE_FLUSH
;
6351 if (!(flags
& wa_bits
))
6352 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6355 /* Emit --------------------------------------------------------------- */
6357 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
6358 pc
.LRIPostSyncOperation
= NoLRIOperation
;
6359 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
6360 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
6361 pc
.StoreDataIndex
= 0;
6362 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
6363 pc
.GlobalSnapshotCountReset
=
6364 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
6365 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
6366 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
6367 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6368 pc
.RenderTargetCacheFlushEnable
=
6369 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
6370 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
6371 pc
.StateCacheInvalidationEnable
=
6372 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
6373 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
6374 pc
.ConstantCacheInvalidationEnable
=
6375 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
6376 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
6377 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
6378 pc
.InstructionCacheInvalidateEnable
=
6379 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
6380 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
6381 pc
.IndirectStatePointersDisable
=
6382 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
6383 pc
.TextureCacheInvalidationEnable
=
6384 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
6385 pc
.Address
= rw_bo(bo
, offset
);
6386 pc
.ImmediateData
= imm
;
6391 genX(emit_urb_setup
)(struct iris_context
*ice
,
6392 struct iris_batch
*batch
,
6393 const unsigned size
[4],
6394 bool tess_present
, bool gs_present
)
6396 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6397 const unsigned push_size_kB
= 32;
6398 unsigned entries
[4];
6401 ice
->shaders
.last_vs_entry_size
= size
[MESA_SHADER_VERTEX
];
6403 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
6404 1024 * ice
->shaders
.urb_size
,
6405 tess_present
, gs_present
,
6406 size
, entries
, start
);
6408 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
6409 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
6410 urb
._3DCommandSubOpcode
+= i
;
6411 urb
.VSURBStartingAddress
= start
[i
];
6412 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
6413 urb
.VSNumberofURBEntries
= entries
[i
];
6420 * Preemption on Gen9 has to be enabled or disabled in various cases.
6422 * See these workarounds for preemption:
6423 * - WaDisableMidObjectPreemptionForGSLineStripAdj
6424 * - WaDisableMidObjectPreemptionForTrifanOrPolygon
6425 * - WaDisableMidObjectPreemptionForLineLoop
6428 * We don't put this in the vtable because it's only used on Gen9.
6431 gen9_toggle_preemption(struct iris_context
*ice
,
6432 struct iris_batch
*batch
,
6433 const struct pipe_draw_info
*draw
)
6435 struct iris_genx_state
*genx
= ice
->state
.genx
;
6436 bool object_preemption
= true;
6438 /* WaDisableMidObjectPreemptionForGSLineStripAdj
6440 * "WA: Disable mid-draw preemption when draw-call is a linestrip_adj
6441 * and GS is enabled."
6443 if (draw
->mode
== PIPE_PRIM_LINE_STRIP_ADJACENCY
&&
6444 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
6445 object_preemption
= false;
6447 /* WaDisableMidObjectPreemptionForTrifanOrPolygon
6449 * "TriFan miscompare in Execlist Preemption test. Cut index that is
6450 * on a previous context. End the previous, the resume another context
6451 * with a tri-fan or polygon, and the vertex count is corrupted. If we
6452 * prempt again we will cause corruption.
6454 * WA: Disable mid-draw preemption when draw-call has a tri-fan."
6456 if (draw
->mode
== PIPE_PRIM_TRIANGLE_FAN
)
6457 object_preemption
= false;
6459 /* WaDisableMidObjectPreemptionForLineLoop
6461 * "VF Stats Counters Missing a vertex when preemption enabled.
6463 * WA: Disable mid-draw preemption when the draw uses a lineloop
6466 if (draw
->mode
== PIPE_PRIM_LINE_LOOP
)
6467 object_preemption
= false;
6471 * "VF is corrupting GAFS data when preempted on an instance boundary
6472 * and replayed with instancing enabled.
6474 * WA: Disable preemption when using instanceing."
6476 if (draw
->instance_count
> 1)
6477 object_preemption
= false;
6479 if (genx
->object_preemption
!= object_preemption
) {
6480 iris_enable_obj_preemption(batch
, object_preemption
);
6481 genx
->object_preemption
= object_preemption
;
6487 genX(init_state
)(struct iris_context
*ice
)
6489 struct pipe_context
*ctx
= &ice
->ctx
;
6490 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
6492 ctx
->create_blend_state
= iris_create_blend_state
;
6493 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
6494 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
6495 ctx
->create_sampler_state
= iris_create_sampler_state
;
6496 ctx
->create_sampler_view
= iris_create_sampler_view
;
6497 ctx
->create_surface
= iris_create_surface
;
6498 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
6499 ctx
->bind_blend_state
= iris_bind_blend_state
;
6500 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
6501 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
6502 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
6503 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
6504 ctx
->delete_blend_state
= iris_delete_state
;
6505 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
6506 ctx
->delete_rasterizer_state
= iris_delete_state
;
6507 ctx
->delete_sampler_state
= iris_delete_state
;
6508 ctx
->delete_vertex_elements_state
= iris_delete_state
;
6509 ctx
->set_blend_color
= iris_set_blend_color
;
6510 ctx
->set_clip_state
= iris_set_clip_state
;
6511 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
6512 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
6513 ctx
->set_shader_images
= iris_set_shader_images
;
6514 ctx
->set_sampler_views
= iris_set_sampler_views
;
6515 ctx
->set_tess_state
= iris_set_tess_state
;
6516 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
6517 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
6518 ctx
->set_sample_mask
= iris_set_sample_mask
;
6519 ctx
->set_scissor_states
= iris_set_scissor_states
;
6520 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
6521 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
6522 ctx
->set_viewport_states
= iris_set_viewport_states
;
6523 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
6524 ctx
->surface_destroy
= iris_surface_destroy
;
6525 ctx
->draw_vbo
= iris_draw_vbo
;
6526 ctx
->launch_grid
= iris_launch_grid
;
6527 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
6528 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
6529 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
6531 ice
->vtbl
.destroy_state
= iris_destroy_state
;
6532 ice
->vtbl
.init_render_context
= iris_init_render_context
;
6533 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
6534 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
6535 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
6536 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
6537 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
6538 ice
->vtbl
.rebind_buffer
= iris_rebind_buffer
;
6539 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
6540 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
6541 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
6542 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
6543 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
6544 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
6545 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
6546 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
6547 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
6548 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
6549 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
6550 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
6551 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
6552 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
6553 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
6554 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
6555 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
6556 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
6557 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
6558 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
6559 ice
->vtbl
.mocs
= mocs
;
6561 ice
->state
.dirty
= ~0ull;
6563 ice
->state
.statistics_counters_enabled
= true;
6565 ice
->state
.sample_mask
= 0xffff;
6566 ice
->state
.num_viewports
= 1;
6567 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
6569 /* Make a 1x1x1 null surface for unbound textures */
6570 void *null_surf_map
=
6571 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
6572 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
6573 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
6574 ice
->state
.unbound_tex
.offset
+=
6575 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
6577 /* Default all scissor rectangles to be empty regions. */
6578 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
6579 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
6580 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,