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289bc1c47118a980db0ae834829b583d2139fded
[mesa.git] / src / gallium / drivers / iris / iris_state.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25
26 #ifdef HAVE_VALGRIND
27 #include <valgrind.h>
28 #include <memcheck.h>
29 #define VG(x) x
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
31 #else
32 #define VG(x)
33 #endif
34
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "i915_drm.h"
42 #include "intel/compiler/brw_compiler.h"
43 #include "intel/common/gen_l3_config.h"
44 #include "intel/common/gen_sample_positions.h"
45 #include "iris_batch.h"
46 #include "iris_context.h"
47 #include "iris_pipe.h"
48 #include "iris_resource.h"
49
50 #define __gen_address_type struct iris_address
51 #define __gen_user_data struct iris_batch
52
53 static uint64_t
54 __gen_combine_address(struct iris_batch *batch, void *location,
55 struct iris_address addr, uint32_t delta)
56 {
57 if (addr.bo == NULL)
58 return addr.offset + delta;
59
60 return iris_batch_reloc(batch, location - batch->cmdbuf.map, addr.bo,
61 addr.offset + delta, addr.reloc_flags);
62 }
63
64 #define __genxml_cmd_length(cmd) cmd ## _length
65 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
66 #define __genxml_cmd_header(cmd) cmd ## _header
67 #define __genxml_cmd_pack(cmd) cmd ## _pack
68
69 static void *
70 get_command_space(struct iris_batch *batch, unsigned bytes)
71 {
72 iris_require_command_space(batch, bytes);
73 void *map = batch->cmdbuf.map_next;
74 batch->cmdbuf.map_next += bytes;
75 return map;
76 }
77
78 #define _iris_pack_command(batch, cmd, dst, name) \
79 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
80 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
81 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
82 _dst = NULL; \
83 }))
84
85 #define iris_pack_command(cmd, dst, name) \
86 _iris_pack_command(NULL, cmd, dst, name)
87
88 #define iris_pack_state(cmd, dst, name) \
89 for (struct cmd name = {}, \
90 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
91 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
92 _dst = NULL)
93
94 #define iris_emit_cmd(batch, cmd, name) \
95 _iris_pack_command(batch, cmd, get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
96
97 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
98 do { \
99 uint32_t *dw = get_command_space(batch, 4 * num_dwords); \
100 for (uint32_t i = 0; i < num_dwords; i++) \
101 dw[i] = (dwords0)[i] | (dwords1)[i]; \
102 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
103 } while (0)
104
105 #define iris_emit_with_addr(batch, dwords, num_dw, addr_field, addr) \
106 do { \
107 STATIC_ASSERT((GENX(addr_field) % 64) == 0); \
108 assert(num_dw <= ARRAY_SIZE(dwords)); \
109 int addr_idx = GENX(addr_field) / 32; \
110 uint32_t *dw = get_command_space(batch, 4 * num_dw); \
111 for (uint32_t i = 0; i < addr_idx; i++) { \
112 dw[i] = (dwords)[i]; \
113 } \
114 uint64_t *qw = (uint64_t *) &dw[addr_idx]; \
115 qw = iris_batch_reloc(batch, qw - batch->cmdbuf.map, addr.bo, \
116 addr.offset + (dwords)[addr_idx + 1], \
117 addr.reloc_flags); \
118 for (uint32_t i = addr_idx + 1; i < num_dw; i++) { \
119 dw[i] = (dwords)[i]; \
120 } \
121 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dw * 4)); \
122 } while (0)
123
124 #include "genxml/genX_pack.h"
125 #include "genxml/gen_macros.h"
126 #include "genxml/genX_bits.h"
127
128 #define MOCS_WB (2 << 1)
129
130 UNUSED static void pipe_asserts()
131 {
132 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
133
134 /* pipe_logicop happens to match the hardware. */
135 PIPE_ASSERT(PIPE_LOGICOP_CLEAR == LOGICOP_CLEAR);
136 PIPE_ASSERT(PIPE_LOGICOP_NOR == LOGICOP_NOR);
137 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED == LOGICOP_AND_INVERTED);
138 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED == LOGICOP_COPY_INVERTED);
139 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE == LOGICOP_AND_REVERSE);
140 PIPE_ASSERT(PIPE_LOGICOP_INVERT == LOGICOP_INVERT);
141 PIPE_ASSERT(PIPE_LOGICOP_XOR == LOGICOP_XOR);
142 PIPE_ASSERT(PIPE_LOGICOP_NAND == LOGICOP_NAND);
143 PIPE_ASSERT(PIPE_LOGICOP_AND == LOGICOP_AND);
144 PIPE_ASSERT(PIPE_LOGICOP_EQUIV == LOGICOP_EQUIV);
145 PIPE_ASSERT(PIPE_LOGICOP_NOOP == LOGICOP_NOOP);
146 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED == LOGICOP_OR_INVERTED);
147 PIPE_ASSERT(PIPE_LOGICOP_COPY == LOGICOP_COPY);
148 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE == LOGICOP_OR_REVERSE);
149 PIPE_ASSERT(PIPE_LOGICOP_OR == LOGICOP_OR);
150 PIPE_ASSERT(PIPE_LOGICOP_SET == LOGICOP_SET);
151
152 /* pipe_blend_func happens to match the hardware. */
153 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE == BLENDFACTOR_ONE);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR == BLENDFACTOR_SRC_COLOR);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA == BLENDFACTOR_SRC_ALPHA);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA == BLENDFACTOR_DST_ALPHA);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR == BLENDFACTOR_DST_COLOR);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE == BLENDFACTOR_SRC_ALPHA_SATURATE);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR == BLENDFACTOR_CONST_COLOR);
160 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA == BLENDFACTOR_CONST_ALPHA);
161 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR == BLENDFACTOR_SRC1_COLOR);
162 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA == BLENDFACTOR_SRC1_ALPHA);
163 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO == BLENDFACTOR_ZERO);
164 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR == BLENDFACTOR_INV_SRC_COLOR);
165 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA == BLENDFACTOR_INV_SRC_ALPHA);
166 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA == BLENDFACTOR_INV_DST_ALPHA);
167 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR == BLENDFACTOR_INV_DST_COLOR);
168 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR == BLENDFACTOR_INV_CONST_COLOR);
169 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA == BLENDFACTOR_INV_CONST_ALPHA);
170 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR == BLENDFACTOR_INV_SRC1_COLOR);
171 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA == BLENDFACTOR_INV_SRC1_ALPHA);
172
173 /* pipe_blend_func happens to match the hardware. */
174 PIPE_ASSERT(PIPE_BLEND_ADD == BLENDFUNCTION_ADD);
175 PIPE_ASSERT(PIPE_BLEND_SUBTRACT == BLENDFUNCTION_SUBTRACT);
176 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT == BLENDFUNCTION_REVERSE_SUBTRACT);
177 PIPE_ASSERT(PIPE_BLEND_MIN == BLENDFUNCTION_MIN);
178 PIPE_ASSERT(PIPE_BLEND_MAX == BLENDFUNCTION_MAX);
179
180 /* pipe_stencil_op happens to match the hardware. */
181 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP == STENCILOP_KEEP);
182 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO == STENCILOP_ZERO);
183 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE == STENCILOP_REPLACE);
184 PIPE_ASSERT(PIPE_STENCIL_OP_INCR == STENCILOP_INCRSAT);
185 PIPE_ASSERT(PIPE_STENCIL_OP_DECR == STENCILOP_DECRSAT);
186 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP == STENCILOP_INCR);
187 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP == STENCILOP_DECR);
188 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT == STENCILOP_INVERT);
189 #undef PIPE_ASSERT
190 }
191
192 static unsigned
193 translate_prim_type(enum pipe_prim_type prim, uint8_t verts_per_patch)
194 {
195 static const unsigned map[] = {
196 [PIPE_PRIM_POINTS] = _3DPRIM_POINTLIST,
197 [PIPE_PRIM_LINES] = _3DPRIM_LINELIST,
198 [PIPE_PRIM_LINE_LOOP] = _3DPRIM_LINELOOP,
199 [PIPE_PRIM_LINE_STRIP] = _3DPRIM_LINESTRIP,
200 [PIPE_PRIM_TRIANGLES] = _3DPRIM_TRILIST,
201 [PIPE_PRIM_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
202 [PIPE_PRIM_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
203 [PIPE_PRIM_QUADS] = _3DPRIM_QUADLIST,
204 [PIPE_PRIM_QUAD_STRIP] = _3DPRIM_QUADSTRIP,
205 [PIPE_PRIM_POLYGON] = _3DPRIM_POLYGON,
206 [PIPE_PRIM_LINES_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
207 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
208 [PIPE_PRIM_TRIANGLES_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
209 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
210 [PIPE_PRIM_PATCHES] = _3DPRIM_PATCHLIST_1 - 1,
211 };
212
213 return map[prim] + (prim == PIPE_PRIM_PATCHES ? verts_per_patch : 0);
214 }
215
216 static unsigned
217 translate_compare_func(enum pipe_compare_func pipe_func)
218 {
219 static const unsigned map[] = {
220 [PIPE_FUNC_NEVER] = COMPAREFUNCTION_NEVER,
221 [PIPE_FUNC_LESS] = COMPAREFUNCTION_LESS,
222 [PIPE_FUNC_EQUAL] = COMPAREFUNCTION_EQUAL,
223 [PIPE_FUNC_LEQUAL] = COMPAREFUNCTION_LEQUAL,
224 [PIPE_FUNC_GREATER] = COMPAREFUNCTION_GREATER,
225 [PIPE_FUNC_NOTEQUAL] = COMPAREFUNCTION_NOTEQUAL,
226 [PIPE_FUNC_GEQUAL] = COMPAREFUNCTION_GEQUAL,
227 [PIPE_FUNC_ALWAYS] = COMPAREFUNCTION_ALWAYS,
228 };
229 return map[pipe_func];
230 }
231
232 static unsigned
233 translate_shadow_func(enum pipe_compare_func pipe_func)
234 {
235 /* Gallium specifies the result of shadow comparisons as:
236 *
237 * 1 if ref <op> texel,
238 * 0 otherwise.
239 *
240 * The hardware does:
241 *
242 * 0 if texel <op> ref,
243 * 1 otherwise.
244 *
245 * So we need to flip the operator and also negate.
246 */
247 static const unsigned map[] = {
248 [PIPE_FUNC_NEVER] = PREFILTEROPALWAYS,
249 [PIPE_FUNC_LESS] = PREFILTEROPLEQUAL,
250 [PIPE_FUNC_EQUAL] = PREFILTEROPNOTEQUAL,
251 [PIPE_FUNC_LEQUAL] = PREFILTEROPLESS,
252 [PIPE_FUNC_GREATER] = PREFILTEROPGEQUAL,
253 [PIPE_FUNC_NOTEQUAL] = PREFILTEROPEQUAL,
254 [PIPE_FUNC_GEQUAL] = PREFILTEROPGREATER,
255 [PIPE_FUNC_ALWAYS] = PREFILTEROPNEVER,
256 };
257 return map[pipe_func];
258 }
259
260 static unsigned
261 translate_cull_mode(unsigned pipe_face)
262 {
263 static const unsigned map[4] = {
264 [PIPE_FACE_NONE] = CULLMODE_NONE,
265 [PIPE_FACE_FRONT] = CULLMODE_FRONT,
266 [PIPE_FACE_BACK] = CULLMODE_BACK,
267 [PIPE_FACE_FRONT_AND_BACK] = CULLMODE_BOTH,
268 };
269 return map[pipe_face];
270 }
271
272 static unsigned
273 translate_fill_mode(unsigned pipe_polymode)
274 {
275 static const unsigned map[4] = {
276 [PIPE_POLYGON_MODE_FILL] = FILL_MODE_SOLID,
277 [PIPE_POLYGON_MODE_LINE] = FILL_MODE_WIREFRAME,
278 [PIPE_POLYGON_MODE_POINT] = FILL_MODE_POINT,
279 [PIPE_POLYGON_MODE_FILL_RECTANGLE] = FILL_MODE_SOLID,
280 };
281 return map[pipe_polymode];
282 }
283
284 static struct iris_address
285 ro_bo(struct iris_bo *bo, uint32_t offset)
286 {
287 return (struct iris_address) { .bo = bo, .offset = offset };
288 }
289
290 static void
291 iris_emit_state_base_address(struct iris_batch *batch)
292 {
293 /* XXX: PIPE_CONTROLs */
294
295 iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
296 #if 0
297 // XXX: MOCS is stupid for this.
298 sba.GeneralStateMemoryObjectControlState = MOCS_WB;
299 sba.StatelessDataPortAccessMemoryObjectControlState = MOCS_WB;
300 sba.SurfaceStateMemoryObjectControlState = MOCS_WB;
301 sba.DynamicStateMemoryObjectControlState = MOCS_WB;
302 sba.IndirectObjectMemoryObjectControlState = MOCS_WB;
303 sba.InstructionMemoryObjectControlState = MOCS_WB;
304 sba.BindlessSurfaceStateMemoryObjectControlState = MOCS_WB;
305 #endif
306
307 sba.GeneralStateBaseAddressModifyEnable = true;
308 sba.SurfaceStateBaseAddressModifyEnable = true;
309 sba.DynamicStateBaseAddressModifyEnable = true;
310 sba.IndirectObjectBaseAddressModifyEnable = true;
311 sba.InstructionBaseAddressModifyEnable = true;
312 sba.GeneralStateBufferSizeModifyEnable = true;
313 sba.DynamicStateBufferSizeModifyEnable = true;
314 sba.BindlessSurfaceStateBaseAddressModifyEnable = true;
315 sba.IndirectObjectBufferSizeModifyEnable = true;
316 sba.InstructionBuffersizeModifyEnable = true;
317
318 sba.SurfaceStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
319 sba.DynamicStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
320
321 sba.GeneralStateBufferSize = 0xfffff;
322 sba.IndirectObjectBufferSize = 0xfffff;
323 sba.InstructionBufferSize = 0xfffff;
324 sba.DynamicStateBufferSize = ALIGN(MAX_STATE_SIZE, 4096);
325 }
326 }
327
328 static void
329 iris_init_render_context(struct iris_screen *screen,
330 struct iris_batch *batch,
331 struct pipe_debug_callback *dbg)
332 {
333 batch->emit_state_base_address = iris_emit_state_base_address;
334 iris_init_batch(batch, screen, dbg, I915_EXEC_RENDER);
335
336 iris_emit_cmd(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
337 rect.ClippedDrawingRectangleXMax = UINT16_MAX;
338 rect.ClippedDrawingRectangleYMax = UINT16_MAX;
339 }
340 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_PATTERN), pat) {
341 GEN_SAMPLE_POS_1X(pat._1xSample);
342 GEN_SAMPLE_POS_2X(pat._2xSample);
343 GEN_SAMPLE_POS_4X(pat._4xSample);
344 GEN_SAMPLE_POS_8X(pat._8xSample);
345 GEN_SAMPLE_POS_16X(pat._16xSample);
346 }
347 iris_emit_cmd(batch, GENX(3DSTATE_AA_LINE_PARAMETERS), foo);
348 iris_emit_cmd(batch, GENX(3DSTATE_WM_CHROMAKEY), foo);
349 iris_emit_cmd(batch, GENX(3DSTATE_WM_HZ_OP), foo);
350 /* XXX: may need to set an offset for origin-UL framebuffers */
351 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_OFFSET), foo);
352
353 /* Just assign a static partitioning. */
354 for (int i = 0; i <= MESA_SHADER_FRAGMENT; i++) {
355 iris_emit_cmd(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) {
356 alloc._3DCommandSubOpcode = 18 + i;
357 alloc.ConstantBufferOffset = 6 * i;
358 alloc.ConstantBufferSize = i == MESA_SHADER_FRAGMENT ? 8 : 6;
359 }
360 }
361 }
362
363 static void
364 iris_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *info)
365 {
366 }
367
368 static void
369 iris_set_blend_color(struct pipe_context *ctx,
370 const struct pipe_blend_color *state)
371 {
372 struct iris_context *ice = (struct iris_context *) ctx;
373
374 memcpy(&ice->state.blend_color, state, sizeof(struct pipe_blend_color));
375 ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE;
376 }
377
378 struct iris_blend_state {
379 uint32_t ps_blend[GENX(3DSTATE_PS_BLEND_length)];
380 uint32_t blend_state[GENX(BLEND_STATE_length)];
381 uint32_t blend_entries[BRW_MAX_DRAW_BUFFERS *
382 GENX(BLEND_STATE_ENTRY_length)];
383
384 bool alpha_to_coverage; /* for shader key */
385 };
386
387 static void *
388 iris_create_blend_state(struct pipe_context *ctx,
389 const struct pipe_blend_state *state)
390 {
391 struct iris_blend_state *cso = malloc(sizeof(struct iris_blend_state));
392
393 cso->alpha_to_coverage = state->alpha_to_coverage;
394
395 iris_pack_state(GENX(BLEND_STATE), cso->blend_state, bs) {
396 bs.AlphaToCoverageEnable = state->alpha_to_coverage;
397 bs.IndependentAlphaBlendEnable = state->independent_blend_enable;
398 bs.AlphaToOneEnable = state->alpha_to_one;
399 bs.AlphaToCoverageDitherEnable = state->alpha_to_coverage;
400 bs.ColorDitherEnable = state->dither;
401 //bs.AlphaTestEnable = <comes from alpha state> :(
402 //bs.AlphaTestFunction = <comes from alpha state> :(
403 }
404
405 iris_pack_command(GENX(3DSTATE_PS_BLEND), cso->ps_blend, pb) {
406 //pb.HasWriteableRT = <comes from somewhere> :(
407 //pb.AlphaTestEnable = <comes from alpha state> :(
408 pb.AlphaToCoverageEnable = state->alpha_to_coverage;
409 pb.IndependentAlphaBlendEnable = state->independent_blend_enable;
410
411 pb.ColorBufferBlendEnable = state->rt[0].blend_enable;
412
413 pb.SourceBlendFactor = state->rt[0].rgb_src_factor;
414 pb.SourceAlphaBlendFactor = state->rt[0].alpha_func;
415 pb.DestinationBlendFactor = state->rt[0].rgb_dst_factor;
416 pb.DestinationAlphaBlendFactor = state->rt[0].alpha_dst_factor;
417 }
418
419 for (int i = 0; i < BRW_MAX_DRAW_BUFFERS; i++) {
420 iris_pack_state(GENX(BLEND_STATE_ENTRY), &cso->blend_entries[i], be) {
421 be.LogicOpEnable = state->logicop_enable;
422 be.LogicOpFunction = state->logicop_func;
423
424 be.PreBlendSourceOnlyClampEnable = false;
425 be.ColorClampRange = COLORCLAMP_RTFORMAT;
426 be.PreBlendColorClampEnable = true;
427 be.PostBlendColorClampEnable = true;
428
429 be.ColorBufferBlendEnable = state->rt[i].blend_enable;
430
431 be.ColorBlendFunction = state->rt[i].rgb_func;
432 be.AlphaBlendFunction = state->rt[i].alpha_func;
433 be.SourceBlendFactor = state->rt[i].rgb_src_factor;
434 be.SourceAlphaBlendFactor = state->rt[i].alpha_func;
435 be.DestinationBlendFactor = state->rt[i].rgb_dst_factor;
436 be.DestinationAlphaBlendFactor = state->rt[i].alpha_dst_factor;
437
438 be.WriteDisableRed = state->rt[i].colormask & PIPE_MASK_R;
439 be.WriteDisableGreen = state->rt[i].colormask & PIPE_MASK_G;
440 be.WriteDisableBlue = state->rt[i].colormask & PIPE_MASK_B;
441 be.WriteDisableAlpha = state->rt[i].colormask & PIPE_MASK_A;
442 }
443 }
444
445 return cso;
446 }
447
448 static void
449 iris_bind_blend_state(struct pipe_context *ctx, void *state)
450 {
451 struct iris_context *ice = (struct iris_context *) ctx;
452 ice->state.cso_blend = state;
453 ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
454 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
455 }
456
457 struct iris_depth_stencil_alpha_state {
458 uint32_t wmds[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
459 uint32_t cc_vp[GENX(CC_VIEWPORT_length)];
460
461 struct pipe_alpha_state alpha; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
462 };
463
464 static void *
465 iris_create_zsa_state(struct pipe_context *ctx,
466 const struct pipe_depth_stencil_alpha_state *state)
467 {
468 struct iris_depth_stencil_alpha_state *cso =
469 malloc(sizeof(struct iris_depth_stencil_alpha_state));
470
471 cso->alpha = state->alpha;
472
473 bool two_sided_stencil = state->stencil[1].enabled;
474
475 /* The state tracker needs to optimize away EQUAL writes for us. */
476 assert(!(state->depth.func == PIPE_FUNC_EQUAL && state->depth.writemask));
477
478 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), cso->wmds, wmds) {
479 wmds.StencilFailOp = state->stencil[0].fail_op;
480 wmds.StencilPassDepthFailOp = state->stencil[0].zfail_op;
481 wmds.StencilPassDepthPassOp = state->stencil[0].zpass_op;
482 wmds.StencilTestFunction =
483 translate_compare_func(state->stencil[0].func);
484 wmds.BackfaceStencilFailOp = state->stencil[1].fail_op;
485 wmds.BackfaceStencilPassDepthFailOp = state->stencil[1].zfail_op;
486 wmds.BackfaceStencilPassDepthPassOp = state->stencil[1].zpass_op;
487 wmds.BackfaceStencilTestFunction =
488 translate_compare_func(state->stencil[1].func);
489 wmds.DepthTestFunction = translate_compare_func(state->depth.func);
490 wmds.DoubleSidedStencilEnable = two_sided_stencil;
491 wmds.StencilTestEnable = state->stencil[0].enabled;
492 wmds.StencilBufferWriteEnable =
493 state->stencil[0].writemask != 0 ||
494 (two_sided_stencil && state->stencil[1].writemask != 0);
495 wmds.DepthTestEnable = state->depth.enabled;
496 wmds.DepthBufferWriteEnable = state->depth.writemask;
497 wmds.StencilTestMask = state->stencil[0].valuemask;
498 wmds.StencilWriteMask = state->stencil[0].writemask;
499 wmds.BackfaceStencilTestMask = state->stencil[1].valuemask;
500 wmds.BackfaceStencilWriteMask = state->stencil[1].writemask;
501 /* wmds.[Backface]StencilReferenceValue are merged later */
502 }
503
504 iris_pack_state(GENX(CC_VIEWPORT), cso->cc_vp, ccvp) {
505 ccvp.MinimumDepth = state->depth.bounds_min;
506 ccvp.MaximumDepth = state->depth.bounds_max;
507 }
508
509 return cso;
510 }
511
512 static void
513 iris_bind_zsa_state(struct pipe_context *ctx, void *state)
514 {
515 struct iris_context *ice = (struct iris_context *) ctx;
516 struct iris_depth_stencil_alpha_state *old_cso = ice->state.cso_zsa;
517 struct iris_depth_stencil_alpha_state *new_cso = state;
518
519 if (new_cso) {
520 if (!old_cso || old_cso->alpha.ref_value != new_cso->alpha.ref_value) {
521 ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE;
522 }
523 }
524
525 ice->state.cso_zsa = new_cso;
526 ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
527 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
528 }
529
530 struct iris_rasterizer_state {
531 uint32_t sf[GENX(3DSTATE_SF_length)];
532 uint32_t clip[GENX(3DSTATE_CLIP_length)];
533 uint32_t raster[GENX(3DSTATE_RASTER_length)];
534 uint32_t wm[GENX(3DSTATE_WM_length)];
535 uint32_t line_stipple[GENX(3DSTATE_LINE_STIPPLE_length)];
536
537 bool flatshade; /* for shader state */
538 bool clamp_fragment_color; /* for shader state */
539 bool light_twoside; /* for shader state */
540 bool rasterizer_discard; /* for 3DSTATE_STREAMOUT */
541 bool half_pixel_center; /* for 3DSTATE_MULTISAMPLE */
542 enum pipe_sprite_coord_mode sprite_coord_mode; /* PIPE_SPRITE_* */
543 };
544
545 static void *
546 iris_create_rasterizer_state(struct pipe_context *ctx,
547 const struct pipe_rasterizer_state *state)
548 {
549 struct iris_rasterizer_state *cso =
550 malloc(sizeof(struct iris_rasterizer_state));
551
552 #if 0
553 sprite_coord_mode -> SBE PointSpriteTextureCoordinateOrigin
554 sprite_coord_enable -> SBE PointSpriteTextureCoordinateEnable
555 point_quad_rasterization -> SBE?
556
557 not necessary?
558 {
559 poly_smooth
560 force_persample_interp - ?
561 bottom_edge_rule
562
563 offset_units_unscaled - cap not exposed
564 }
565 #endif
566
567 cso->flatshade = state->flatshade;
568 cso->clamp_fragment_color = state->clamp_fragment_color;
569 cso->light_twoside = state->light_twoside;
570 cso->rasterizer_discard = state->rasterizer_discard;
571 cso->half_pixel_center = state->half_pixel_center;
572
573 iris_pack_command(GENX(3DSTATE_SF), cso->sf, sf) {
574 sf.StatisticsEnable = true;
575 sf.ViewportTransformEnable = true;
576 sf.AALineDistanceMode = AALINEDISTANCE_TRUE;
577 sf.LineEndCapAntialiasingRegionWidth =
578 state->line_smooth ? _10pixels : _05pixels;
579 sf.LastPixelEnable = state->line_last_pixel;
580 sf.LineWidth = state->line_width;
581 sf.SmoothPointEnable = state->point_smooth;
582 sf.PointWidthSource = state->point_size_per_vertex ? Vertex : State;
583 sf.PointWidth = state->point_size;
584
585 if (state->flatshade_first) {
586 sf.TriangleStripListProvokingVertexSelect = 2;
587 sf.TriangleFanProvokingVertexSelect = 2;
588 sf.LineStripListProvokingVertexSelect = 1;
589 } else {
590 sf.TriangleFanProvokingVertexSelect = 1;
591 }
592 }
593
594 /* COMPLETE! */
595 iris_pack_command(GENX(3DSTATE_RASTER), cso->raster, rr) {
596 rr.FrontWinding = state->front_ccw ? CounterClockwise : Clockwise;
597 rr.CullMode = translate_cull_mode(state->cull_face);
598 rr.FrontFaceFillMode = translate_fill_mode(state->fill_front);
599 rr.BackFaceFillMode = translate_fill_mode(state->fill_back);
600 rr.DXMultisampleRasterizationEnable = state->multisample;
601 rr.GlobalDepthOffsetEnableSolid = state->offset_tri;
602 rr.GlobalDepthOffsetEnableWireframe = state->offset_line;
603 rr.GlobalDepthOffsetEnablePoint = state->offset_point;
604 rr.GlobalDepthOffsetConstant = state->offset_units;
605 rr.GlobalDepthOffsetScale = state->offset_scale;
606 rr.GlobalDepthOffsetClamp = state->offset_clamp;
607 rr.SmoothPointEnable = state->point_smooth;
608 rr.AntialiasingEnable = state->line_smooth;
609 rr.ScissorRectangleEnable = state->scissor;
610 rr.ViewportZNearClipTestEnable = state->depth_clip_near;
611 rr.ViewportZFarClipTestEnable = state->depth_clip_far;
612 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
613 }
614
615 iris_pack_command(GENX(3DSTATE_CLIP), cso->clip, cl) {
616 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
617 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
618 */
619 cl.StatisticsEnable = true;
620 cl.EarlyCullEnable = true;
621 cl.UserClipDistanceClipTestEnableBitmask = state->clip_plane_enable;
622 cl.ForceUserClipDistanceClipTestEnableBitmask = true;
623 cl.APIMode = state->clip_halfz ? APIMODE_D3D : APIMODE_OGL;
624 cl.GuardbandClipTestEnable = true;
625 cl.ClipMode = CLIPMODE_NORMAL;
626 cl.ClipEnable = true;
627 cl.ViewportXYClipTestEnable = state->point_tri_clip;
628 cl.MinimumPointWidth = 0.125;
629 cl.MaximumPointWidth = 255.875;
630
631 if (state->flatshade_first) {
632 cl.TriangleStripListProvokingVertexSelect = 2;
633 cl.TriangleFanProvokingVertexSelect = 2;
634 cl.LineStripListProvokingVertexSelect = 1;
635 } else {
636 cl.TriangleFanProvokingVertexSelect = 1;
637 }
638 }
639
640 iris_pack_command(GENX(3DSTATE_WM), cso->wm, wm) {
641 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
642 * filled in at draw time from the FS program.
643 */
644 wm.LineAntialiasingRegionWidth = _10pixels;
645 wm.LineEndCapAntialiasingRegionWidth = _05pixels;
646 wm.PointRasterizationRule = RASTRULE_UPPER_RIGHT;
647 wm.StatisticsEnable = true;
648 wm.LineStippleEnable = state->line_stipple_enable;
649 wm.PolygonStippleEnable = state->poly_stipple_enable;
650 }
651
652 /* Remap from 0..255 back to 1..256 */
653 const unsigned line_stipple_factor = state->line_stipple_factor + 1;
654
655 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE), cso->line_stipple, line) {
656 line.LineStipplePattern = state->line_stipple_pattern;
657 line.LineStippleInverseRepeatCount = 1.0f / line_stipple_factor;
658 line.LineStippleRepeatCount = line_stipple_factor;
659 }
660
661 return cso;
662 }
663
664 static void
665 iris_bind_rasterizer_state(struct pipe_context *ctx, void *state)
666 {
667 struct iris_context *ice = (struct iris_context *) ctx;
668 struct iris_rasterizer_state *old_cso = ice->state.cso_rast;
669 struct iris_rasterizer_state *new_cso = state;
670
671 if (new_cso) {
672 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
673 if (!old_cso || memcmp(old_cso->line_stipple, new_cso->line_stipple,
674 sizeof(old_cso->line_stipple)) != 0) {
675 ice->state.dirty |= IRIS_DIRTY_LINE_STIPPLE;
676 }
677
678 if (!old_cso ||
679 old_cso->half_pixel_center != new_cso->half_pixel_center) {
680 ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
681 }
682 }
683
684 ice->state.cso_rast = new_cso;
685 ice->state.dirty |= IRIS_DIRTY_RASTER;
686 }
687
688 static uint32_t
689 translate_wrap(unsigned pipe_wrap)
690 {
691 static const unsigned map[] = {
692 [PIPE_TEX_WRAP_REPEAT] = TCM_WRAP,
693 [PIPE_TEX_WRAP_CLAMP] = TCM_HALF_BORDER,
694 [PIPE_TEX_WRAP_CLAMP_TO_EDGE] = TCM_CLAMP,
695 [PIPE_TEX_WRAP_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
696 [PIPE_TEX_WRAP_MIRROR_REPEAT] = TCM_MIRROR,
697 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
698 [PIPE_TEX_WRAP_MIRROR_CLAMP] = -1, // XXX: ???
699 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER] = -1, // XXX: ???
700 };
701 return map[pipe_wrap];
702 }
703
704 /**
705 * Return true if the given wrap mode requires the border color to exist.
706 */
707 static bool
708 wrap_mode_needs_border_color(unsigned wrap_mode)
709 {
710 return wrap_mode == TCM_CLAMP_BORDER || wrap_mode == TCM_HALF_BORDER;
711 }
712
713 static unsigned
714 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip)
715 {
716 static const unsigned map[] = {
717 [PIPE_TEX_MIPFILTER_NEAREST] = MIPFILTER_NEAREST,
718 [PIPE_TEX_MIPFILTER_LINEAR] = MIPFILTER_LINEAR,
719 [PIPE_TEX_MIPFILTER_NONE] = MIPFILTER_NONE,
720 };
721 return map[pipe_mip];
722 }
723
724 struct iris_sampler_state {
725 struct pipe_sampler_state base;
726
727 bool needs_border_color;
728
729 uint32_t sampler_state[GENX(SAMPLER_STATE_length)];
730 };
731
732 static void *
733 iris_create_sampler_state(struct pipe_context *pctx,
734 const struct pipe_sampler_state *state)
735 {
736 struct iris_sampler_state *cso = CALLOC_STRUCT(iris_sampler_state);
737
738 if (!cso)
739 return NULL;
740
741 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST == MAPFILTER_NEAREST);
742 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR == MAPFILTER_LINEAR);
743
744 unsigned wrap_s = translate_wrap(state->wrap_s);
745 unsigned wrap_t = translate_wrap(state->wrap_t);
746 unsigned wrap_r = translate_wrap(state->wrap_r);
747
748 cso->needs_border_color = wrap_mode_needs_border_color(wrap_s) ||
749 wrap_mode_needs_border_color(wrap_t) ||
750 wrap_mode_needs_border_color(wrap_r);
751
752 iris_pack_state(GENX(SAMPLER_STATE), cso->sampler_state, samp) {
753 samp.TCXAddressControlMode = wrap_s;
754 samp.TCYAddressControlMode = wrap_t;
755 samp.TCZAddressControlMode = wrap_r;
756 samp.CubeSurfaceControlMode = state->seamless_cube_map;
757 samp.NonnormalizedCoordinateEnable = !state->normalized_coords;
758 samp.MinModeFilter = state->min_img_filter;
759 samp.MagModeFilter = state->mag_img_filter;
760 samp.MipModeFilter = translate_mip_filter(state->min_mip_filter);
761 samp.MaximumAnisotropy = RATIO21;
762
763 if (state->max_anisotropy >= 2) {
764 if (state->min_img_filter == PIPE_TEX_FILTER_LINEAR) {
765 samp.MinModeFilter = MAPFILTER_ANISOTROPIC;
766 samp.AnisotropicAlgorithm = EWAApproximation;
767 }
768
769 if (state->mag_img_filter == PIPE_TEX_FILTER_LINEAR)
770 samp.MagModeFilter = MAPFILTER_ANISOTROPIC;
771
772 samp.MaximumAnisotropy =
773 MIN2((state->max_anisotropy - 2) / 2, RATIO161);
774 }
775
776 /* Set address rounding bits if not using nearest filtering. */
777 if (state->min_img_filter != PIPE_TEX_FILTER_NEAREST) {
778 samp.UAddressMinFilterRoundingEnable = true;
779 samp.VAddressMinFilterRoundingEnable = true;
780 samp.RAddressMinFilterRoundingEnable = true;
781 }
782
783 if (state->mag_img_filter != PIPE_TEX_FILTER_NEAREST) {
784 samp.UAddressMagFilterRoundingEnable = true;
785 samp.VAddressMagFilterRoundingEnable = true;
786 samp.RAddressMagFilterRoundingEnable = true;
787 }
788
789 if (state->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
790 samp.ShadowFunction = translate_shadow_func(state->compare_func);
791
792 const float hw_max_lod = GEN_GEN >= 7 ? 14 : 13;
793
794 samp.LODPreClampMode = CLAMP_MODE_OGL;
795 samp.MinLOD = CLAMP(state->min_lod, 0, hw_max_lod);
796 samp.MaxLOD = CLAMP(state->max_lod, 0, hw_max_lod);
797 samp.TextureLODBias = CLAMP(state->lod_bias, -16, 15);
798
799 //samp.BorderColorPointer = <<comes from elsewhere>>
800 }
801
802 return cso;
803 }
804
805 static void
806 iris_bind_sampler_states(struct pipe_context *ctx,
807 enum pipe_shader_type p_stage,
808 unsigned start, unsigned count,
809 void **states)
810 {
811 struct iris_context *ice = (struct iris_context *) ctx;
812 gl_shader_stage stage = stage_from_pipe(p_stage);
813
814 assert(start + count <= IRIS_MAX_TEXTURE_SAMPLERS);
815
816 for (int i = 0; i < count; i++) {
817 ice->state.samplers[stage][start + i] = states[i];
818 }
819
820 ice->state.dirty |= IRIS_DIRTY_SAMPLER_STATES_VS << stage;
821 }
822
823 struct iris_sampler_view {
824 struct pipe_sampler_view pipe;
825 struct isl_view view;
826 uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
827 };
828
829 /**
830 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
831 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
832 *
833 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
834 * 0 1 2 3 4 5
835 * 4 5 6 7 0 1
836 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
837 *
838 * which is simply adding 4 then modding by 8 (or anding with 7).
839 *
840 * We then may need to apply workarounds for textureGather hardware bugs.
841 */
842 static enum isl_channel_select
843 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle)
844 {
845 return (swizzle + 4) & 7;
846 }
847
848 static struct pipe_sampler_view *
849 iris_create_sampler_view(struct pipe_context *ctx,
850 struct pipe_resource *tex,
851 const struct pipe_sampler_view *tmpl)
852 {
853 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
854 struct iris_resource *itex = (struct iris_resource *) tex;
855 struct iris_sampler_view *isv = calloc(1, sizeof(struct iris_sampler_view));
856
857 if (!isv)
858 return NULL;
859
860 /* initialize base object */
861 isv->pipe = *tmpl;
862 isv->pipe.context = ctx;
863 isv->pipe.texture = NULL;
864 pipe_reference_init(&isv->pipe.reference, 1);
865 pipe_resource_reference(&isv->pipe.texture, tex);
866
867 /* XXX: do we need brw_get_texture_swizzle hacks here? */
868
869 isv->view = (struct isl_view) {
870 .format = iris_isl_format_for_pipe_format(tmpl->format),
871 .base_level = tmpl->u.tex.first_level,
872 .levels = tmpl->u.tex.last_level - tmpl->u.tex.first_level + 1,
873 .base_array_layer = tmpl->u.tex.first_layer,
874 .array_len = tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1,
875 .swizzle = (struct isl_swizzle) {
876 .r = pipe_swizzle_to_isl_channel(tmpl->swizzle_r),
877 .g = pipe_swizzle_to_isl_channel(tmpl->swizzle_g),
878 .b = pipe_swizzle_to_isl_channel(tmpl->swizzle_b),
879 .a = pipe_swizzle_to_isl_channel(tmpl->swizzle_a),
880 },
881 .usage = ISL_SURF_USAGE_TEXTURE_BIT,
882 };
883
884 isl_surf_fill_state(&screen->isl_dev, isv->surface_state,
885 .surf = &itex->surf, .view = &isv->view,
886 .mocs = MOCS_WB);
887 // .address = ...
888 // .aux_surf =
889 // .clear_color = clear_color,
890
891 return &isv->pipe;
892 }
893
894 struct iris_surface {
895 struct pipe_surface pipe;
896 struct isl_view view;
897 uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
898 };
899
900 static struct pipe_surface *
901 iris_create_surface(struct pipe_context *ctx,
902 struct pipe_resource *tex,
903 const struct pipe_surface *tmpl)
904 {
905 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
906 struct iris_surface *surf = calloc(1, sizeof(struct iris_surface));
907 struct pipe_surface *psurf = &surf->pipe;
908 struct iris_resource *itex = (struct iris_resource *) tex;
909
910 if (!surf)
911 return NULL;
912
913 pipe_reference_init(&psurf->reference, 1);
914 pipe_resource_reference(&psurf->texture, tex);
915 psurf->context = ctx;
916 psurf->format = tmpl->format;
917 psurf->width = tex->width0;
918 psurf->height = tex->height0;
919 psurf->texture = tex;
920 psurf->u.tex.first_layer = tmpl->u.tex.first_layer;
921 psurf->u.tex.last_layer = tmpl->u.tex.last_layer;
922 psurf->u.tex.level = tmpl->u.tex.level;
923
924 surf->view = (struct isl_view) {
925 .format = iris_isl_format_for_pipe_format(tmpl->format),
926 .base_level = tmpl->u.tex.level,
927 .levels = 1,
928 .base_array_layer = tmpl->u.tex.first_layer,
929 .array_len = tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1,
930 .swizzle = ISL_SWIZZLE_IDENTITY,
931 // XXX: DEPTH_BIt, STENCIL_BIT...CUBE_BIT? Other bits?!
932 .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT,
933 };
934
935 isl_surf_fill_state(&screen->isl_dev, surf->surface_state,
936 .surf = &itex->surf, .view = &surf->view,
937 .mocs = MOCS_WB);
938 // .address = ...
939 // .aux_surf =
940 // .clear_color = clear_color,
941
942 return psurf;
943 }
944
945 static void
946 iris_set_sampler_views(struct pipe_context *ctx,
947 enum pipe_shader_type shader,
948 unsigned start, unsigned count,
949 struct pipe_sampler_view **views)
950 {
951 }
952
953 static void
954 iris_set_clip_state(struct pipe_context *ctx,
955 const struct pipe_clip_state *state)
956 {
957 }
958
959 static void
960 iris_set_polygon_stipple(struct pipe_context *ctx,
961 const struct pipe_poly_stipple *state)
962 {
963 struct iris_context *ice = (struct iris_context *) ctx;
964 memcpy(&ice->state.poly_stipple, state, sizeof(*state));
965 ice->state.dirty |= IRIS_DIRTY_POLYGON_STIPPLE;
966 }
967
968 static void
969 iris_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
970 {
971 struct iris_context *ice = (struct iris_context *) ctx;
972
973 ice->state.sample_mask = sample_mask;
974 ice->state.dirty |= IRIS_DIRTY_SAMPLE_MASK;
975 }
976
977 static void
978 iris_set_scissor_states(struct pipe_context *ctx,
979 unsigned start_slot,
980 unsigned num_scissors,
981 const struct pipe_scissor_state *states)
982 {
983 struct iris_context *ice = (struct iris_context *) ctx;
984
985 ice->state.num_scissors = num_scissors;
986
987 for (unsigned i = 0; i < num_scissors; i++) {
988 ice->state.scissors[start_slot + i] = states[i];
989 }
990
991 ice->state.dirty |= IRIS_DIRTY_SCISSOR_RECT;
992 }
993
994 static void
995 iris_set_stencil_ref(struct pipe_context *ctx,
996 const struct pipe_stencil_ref *state)
997 {
998 struct iris_context *ice = (struct iris_context *) ctx;
999 memcpy(&ice->state.stencil_ref, state, sizeof(*state));
1000 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
1001 }
1002
1003
1004 struct iris_viewport_state {
1005 uint32_t sf_cl_vp[GENX(SF_CLIP_VIEWPORT_length)];
1006 };
1007
1008 static float
1009 extent_from_matrix(const struct pipe_viewport_state *state, int axis)
1010 {
1011 return fabsf(state->scale[axis]) * state->translate[axis];
1012 }
1013
1014 #if 0
1015 static void
1016 calculate_guardband_size(uint32_t fb_width, uint32_t fb_height,
1017 float m00, float m11, float m30, float m31,
1018 float *xmin, float *xmax,
1019 float *ymin, float *ymax)
1020 {
1021 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1022 * Strips and Fans documentation:
1023 *
1024 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1025 * fixed-point "guardband" range supported by the rasterization hardware"
1026 *
1027 * and
1028 *
1029 * "In almost all circumstances, if an object’s vertices are actually
1030 * modified by this clamping (i.e., had X or Y coordinates outside of
1031 * the guardband extent the rendered object will not match the intended
1032 * result. Therefore software should take steps to ensure that this does
1033 * not happen - e.g., by clipping objects such that they do not exceed
1034 * these limits after the Drawing Rectangle is applied."
1035 *
1036 * I believe the fundamental restriction is that the rasterizer (in
1037 * the SF/WM stages) have a limit on the number of pixels that can be
1038 * rasterized. We need to ensure any coordinates beyond the rasterizer
1039 * limit are handled by the clipper. So effectively that limit becomes
1040 * the clipper's guardband size.
1041 *
1042 * It goes on to say:
1043 *
1044 * "In addition, in order to be correctly rendered, objects must have a
1045 * screenspace bounding box not exceeding 8K in the X or Y direction.
1046 * This additional restriction must also be comprehended by software,
1047 * i.e., enforced by use of clipping."
1048 *
1049 * This makes no sense. Gen7+ hardware supports 16K render targets,
1050 * and you definitely need to be able to draw polygons that fill the
1051 * surface. Our assumption is that the rasterizer was limited to 8K
1052 * on Sandybridge, which only supports 8K surfaces, and it was actually
1053 * increased to 16K on Ivybridge and later.
1054 *
1055 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1056 */
1057 const float gb_size = GEN_GEN >= 7 ? 16384.0f : 8192.0f;
1058
1059 if (m00 != 0 && m11 != 0) {
1060 /* First, we compute the screen-space render area */
1061 const float ss_ra_xmin = MIN3( 0, m30 + m00, m30 - m00);
1062 const float ss_ra_xmax = MAX3( fb_width, m30 + m00, m30 - m00);
1063 const float ss_ra_ymin = MIN3( 0, m31 + m11, m31 - m11);
1064 const float ss_ra_ymax = MAX3(fb_height, m31 + m11, m31 - m11);
1065
1066 /* We want the guardband to be centered on that */
1067 const float ss_gb_xmin = (ss_ra_xmin + ss_ra_xmax) / 2 - gb_size;
1068 const float ss_gb_xmax = (ss_ra_xmin + ss_ra_xmax) / 2 + gb_size;
1069 const float ss_gb_ymin = (ss_ra_ymin + ss_ra_ymax) / 2 - gb_size;
1070 const float ss_gb_ymax = (ss_ra_ymin + ss_ra_ymax) / 2 + gb_size;
1071
1072 /* Now we need it in native device coordinates */
1073 const float ndc_gb_xmin = (ss_gb_xmin - m30) / m00;
1074 const float ndc_gb_xmax = (ss_gb_xmax - m30) / m00;
1075 const float ndc_gb_ymin = (ss_gb_ymin - m31) / m11;
1076 const float ndc_gb_ymax = (ss_gb_ymax - m31) / m11;
1077
1078 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1079 * flipped upside-down. X should be fine though.
1080 */
1081 assert(ndc_gb_xmin <= ndc_gb_xmax);
1082 *xmin = ndc_gb_xmin;
1083 *xmax = ndc_gb_xmax;
1084 *ymin = MIN2(ndc_gb_ymin, ndc_gb_ymax);
1085 *ymax = MAX2(ndc_gb_ymin, ndc_gb_ymax);
1086 } else {
1087 /* The viewport scales to 0, so nothing will be rendered. */
1088 *xmin = 0.0f;
1089 *xmax = 0.0f;
1090 *ymin = 0.0f;
1091 *ymax = 0.0f;
1092 }
1093 }
1094 #endif
1095
1096 static void
1097 iris_set_viewport_states(struct pipe_context *ctx,
1098 unsigned start_slot,
1099 unsigned num_viewports,
1100 const struct pipe_viewport_state *state)
1101 {
1102 struct iris_context *ice = (struct iris_context *) ctx;
1103 struct iris_viewport_state *cso =
1104 malloc(sizeof(struct iris_viewport_state));
1105
1106 // XXX: sf_cl_vp is only big enough for one slot, we don't iterate right
1107 for (unsigned i = start_slot; i < start_slot + num_viewports; i++) {
1108 float x_extent = extent_from_matrix(&state[i], 0);
1109 float y_extent = extent_from_matrix(&state[i], 1);
1110
1111 iris_pack_state(GENX(SF_CLIP_VIEWPORT), cso->sf_cl_vp, vp) {
1112 vp.ViewportMatrixElementm00 = state[i].scale[0];
1113 vp.ViewportMatrixElementm11 = state[i].scale[1];
1114 vp.ViewportMatrixElementm22 = state[i].scale[2];
1115 vp.ViewportMatrixElementm30 = state[i].translate[0];
1116 vp.ViewportMatrixElementm31 = state[i].translate[1];
1117 vp.ViewportMatrixElementm32 = state[i].translate[2];
1118 /* XXX: in i965 this is computed based on the drawbuffer size,
1119 * but we don't have that here...
1120 */
1121 vp.XMinClipGuardband = -1.0;
1122 vp.XMaxClipGuardband = 1.0;
1123 vp.YMinClipGuardband = -1.0;
1124 vp.YMaxClipGuardband = 1.0;
1125 vp.XMinViewPort = -x_extent;
1126 vp.XMaxViewPort = x_extent;
1127 vp.YMinViewPort = -y_extent;
1128 vp.YMaxViewPort = y_extent;
1129 }
1130 }
1131
1132 ice->state.cso_vp = cso;
1133 // XXX: start_slot
1134 ice->state.num_viewports = num_viewports;
1135 ice->state.dirty |= IRIS_DIRTY_SF_CL_VIEWPORT;
1136 }
1137
1138 struct iris_depth_state
1139 {
1140 uint32_t depth_buffer[GENX(3DSTATE_DEPTH_BUFFER_length)];
1141 uint32_t hier_depth_buffer[GENX(3DSTATE_HIER_DEPTH_BUFFER_length)];
1142 uint32_t stencil_buffer[GENX(3DSTATE_STENCIL_BUFFER_length)];
1143 };
1144
1145 static void
1146 iris_set_framebuffer_state(struct pipe_context *ctx,
1147 const struct pipe_framebuffer_state *state)
1148 {
1149 struct iris_context *ice = (struct iris_context *) ctx;
1150 struct pipe_framebuffer_state *cso = &ice->state.framebuffer;
1151
1152 if (cso->samples != state->samples) {
1153 ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
1154 }
1155
1156 cso->width = state->width;
1157 cso->height = state->height;
1158 cso->layers = state->layers;
1159 cso->samples = state->samples;
1160
1161 unsigned i;
1162 for (i = 0; i < state->nr_cbufs; i++)
1163 pipe_surface_reference(&cso->cbufs[i], state->cbufs[i]);
1164 for (; i < cso->nr_cbufs; i++)
1165 pipe_surface_reference(&cso->cbufs[i], NULL);
1166
1167 cso->nr_cbufs = state->nr_cbufs;
1168
1169 pipe_surface_reference(&cso->zsbuf, state->zsbuf);
1170
1171 struct isl_depth_stencil_hiz_emit_info info = {
1172 .mocs = MOCS_WB,
1173 };
1174
1175 // XXX: depth buffers
1176 }
1177
1178 static void
1179 iris_set_constant_buffer(struct pipe_context *ctx,
1180 enum pipe_shader_type shader, uint index,
1181 const struct pipe_constant_buffer *cb)
1182 {
1183 }
1184
1185
1186 static void
1187 iris_sampler_view_destroy(struct pipe_context *ctx,
1188 struct pipe_sampler_view *state)
1189 {
1190 pipe_resource_reference(&state->texture, NULL);
1191 free(state);
1192 }
1193
1194
1195 static void
1196 iris_surface_destroy(struct pipe_context *ctx, struct pipe_surface *surface)
1197 {
1198 pipe_resource_reference(&surface->texture, NULL);
1199 free(surface);
1200 }
1201
1202 static void
1203 iris_delete_state(struct pipe_context *ctx, void *state)
1204 {
1205 free(state);
1206 }
1207
1208 struct iris_vertex_buffer_state {
1209 uint32_t vertex_buffers[1 + 33 * GENX(VERTEX_BUFFER_STATE_length)];
1210 struct iris_address bos[33];
1211 unsigned num_buffers;
1212 };
1213
1214 static void
1215 iris_free_vertex_buffers(struct iris_vertex_buffer_state *cso)
1216 {
1217 if (cso) {
1218 for (unsigned i = 0; i < cso->num_buffers; i++)
1219 iris_bo_unreference(cso->bos[i].bo);
1220 free(cso);
1221 }
1222 }
1223
1224 static void
1225 iris_set_vertex_buffers(struct pipe_context *ctx,
1226 unsigned start_slot, unsigned count,
1227 const struct pipe_vertex_buffer *buffers)
1228 {
1229 struct iris_context *ice = (struct iris_context *) ctx;
1230 struct iris_vertex_buffer_state *cso =
1231 malloc(sizeof(struct iris_vertex_buffer_state));
1232
1233 /* If there are no buffers, do nothing. We can leave the stale
1234 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1235 * elements that point to them, it should be fine.
1236 */
1237 if (!buffers)
1238 return;
1239
1240 iris_free_vertex_buffers(ice->state.cso_vertex_buffers);
1241
1242 cso->num_buffers = count;
1243
1244 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS), cso->vertex_buffers, vb) {
1245 vb.DWordLength = 4 * cso->num_buffers - 1;
1246 }
1247
1248 uint32_t *vb_pack_dest = &cso->vertex_buffers[1];
1249
1250 for (unsigned i = 0; i < count; i++) {
1251 assert(!buffers[i].is_user_buffer);
1252
1253 struct iris_resource *res = (void *) buffers[i].buffer.resource;
1254 iris_bo_reference(res->bo);
1255 cso->bos[i] = ro_bo(res->bo, buffers[i].buffer_offset);
1256
1257 iris_pack_state(GENX(VERTEX_BUFFER_STATE), vb_pack_dest, vb) {
1258 vb.VertexBufferIndex = start_slot + i;
1259 vb.MOCS = MOCS_WB;
1260 vb.AddressModifyEnable = true;
1261 vb.BufferPitch = buffers[i].stride;
1262 vb.BufferSize = res->bo->size;
1263 /* vb.BufferStartingAddress is filled in at draw time */
1264 }
1265
1266 vb_pack_dest += GENX(VERTEX_BUFFER_STATE_length);
1267 }
1268
1269 ice->state.cso_vertex_buffers = cso;
1270 ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS;
1271 }
1272
1273 struct iris_vertex_element_state {
1274 uint32_t vertex_elements[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length)];
1275 uint32_t vf_instancing[GENX(3DSTATE_VF_INSTANCING_length)][33];
1276 unsigned count;
1277 };
1278
1279 static void *
1280 iris_create_vertex_elements(struct pipe_context *ctx,
1281 unsigned count,
1282 const struct pipe_vertex_element *state)
1283 {
1284 struct iris_vertex_element_state *cso =
1285 malloc(sizeof(struct iris_vertex_element_state));
1286
1287 cso->count = count;
1288
1289 /* TODO:
1290 * - create edge flag one
1291 * - create SGV ones
1292 * - if those are necessary, use count + 1/2/3... OR in the length
1293 */
1294 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS), cso->vertex_elements, ve);
1295
1296 uint32_t *ve_pack_dest = &cso->vertex_elements[1];
1297
1298 for (int i = 0; i < count; i++) {
1299 iris_pack_state(GENX(VERTEX_ELEMENT_STATE), ve_pack_dest, ve) {
1300 ve.VertexBufferIndex = state[i].vertex_buffer_index;
1301 ve.Valid = true;
1302 ve.SourceElementOffset = state[i].src_offset;
1303 ve.SourceElementFormat =
1304 iris_isl_format_for_pipe_format(state[i].src_format);
1305 }
1306
1307 iris_pack_command(GENX(3DSTATE_VF_INSTANCING), cso->vf_instancing[i], vi) {
1308 vi.VertexElementIndex = i;
1309 vi.InstancingEnable = state[i].instance_divisor > 0;
1310 vi.InstanceDataStepRate = state[i].instance_divisor;
1311 }
1312
1313 ve_pack_dest += GENX(VERTEX_ELEMENT_STATE_length);
1314 }
1315
1316 return cso;
1317 }
1318
1319 static void
1320 iris_bind_vertex_elements_state(struct pipe_context *ctx, void *state)
1321 {
1322 struct iris_context *ice = (struct iris_context *) ctx;
1323
1324 ice->state.cso_vertex_elements = state;
1325 ice->state.dirty |= IRIS_DIRTY_VERTEX_ELEMENTS;
1326 }
1327
1328 static void *
1329 iris_create_compute_state(struct pipe_context *ctx,
1330 const struct pipe_compute_state *state)
1331 {
1332 return malloc(1);
1333 }
1334
1335 static struct pipe_stream_output_target *
1336 iris_create_stream_output_target(struct pipe_context *ctx,
1337 struct pipe_resource *res,
1338 unsigned buffer_offset,
1339 unsigned buffer_size)
1340 {
1341 struct pipe_stream_output_target *t =
1342 CALLOC_STRUCT(pipe_stream_output_target);
1343 if (!t)
1344 return NULL;
1345
1346 pipe_reference_init(&t->reference, 1);
1347 pipe_resource_reference(&t->buffer, res);
1348 t->buffer_offset = buffer_offset;
1349 t->buffer_size = buffer_size;
1350 return t;
1351 }
1352
1353 static void
1354 iris_stream_output_target_destroy(struct pipe_context *ctx,
1355 struct pipe_stream_output_target *t)
1356 {
1357 pipe_resource_reference(&t->buffer, NULL);
1358 free(t);
1359 }
1360
1361 static void
1362 iris_set_stream_output_targets(struct pipe_context *ctx,
1363 unsigned num_targets,
1364 struct pipe_stream_output_target **targets,
1365 const unsigned *offsets)
1366 {
1367 }
1368
1369 static void
1370 iris_bind_compute_state(struct pipe_context *ctx, void *state)
1371 {
1372 }
1373
1374 static void
1375 iris_populate_vs_key(const struct iris_context *ice,
1376 struct brw_vs_prog_key *key)
1377 {
1378 memset(key, 0, sizeof(*key));
1379 }
1380
1381 static void
1382 iris_populate_tcs_key(const struct iris_context *ice,
1383 struct brw_tcs_prog_key *key)
1384 {
1385 memset(key, 0, sizeof(*key));
1386 }
1387
1388 static void
1389 iris_populate_tes_key(const struct iris_context *ice,
1390 struct brw_tes_prog_key *key)
1391 {
1392 memset(key, 0, sizeof(*key));
1393 }
1394
1395 static void
1396 iris_populate_gs_key(const struct iris_context *ice,
1397 struct brw_gs_prog_key *key)
1398 {
1399 memset(key, 0, sizeof(*key));
1400 }
1401
1402 static void
1403 iris_populate_fs_key(const struct iris_context *ice,
1404 struct brw_wm_prog_key *key)
1405 {
1406 memset(key, 0, sizeof(*key));
1407
1408 /* XXX: dirty flags? */
1409 struct pipe_framebuffer_state *fb = &ice->state.framebuffer;
1410 struct iris_depth_stencil_alpha_state *zsa = ice->state.cso_zsa;
1411 struct iris_rasterizer_state *rast = ice->state.cso_rast;
1412 struct iris_blend_state *blend = ice->state.cso_blend;
1413
1414 key->nr_color_regions = fb->nr_cbufs;
1415
1416 key->clamp_fragment_color = rast->clamp_fragment_color;
1417
1418 key->replicate_alpha = fb->nr_cbufs > 1 &&
1419 (zsa->alpha.enabled || blend->alpha_to_coverage);
1420
1421 // key->force_dual_color_blend for unigine
1422 #if 0
1423 if (cso_rast->multisample) {
1424 key->persample_interp =
1425 ctx->Multisample.SampleShading &&
1426 (ctx->Multisample.MinSampleShadingValue *
1427 _mesa_geometric_samples(ctx->DrawBuffer) > 1);
1428
1429 key->multisample_fbo = fb->samples > 1;
1430 }
1431 #endif
1432
1433 key->coherent_fb_fetch = true;
1434 }
1435
1436 //pkt.SamplerCount = \
1437 //DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1438 //pkt.PerThreadScratchSpace = prog_data->total_scratch == 0 ? 0 : \
1439 //ffs(stage_state->per_thread_scratch) - 11; \
1440
1441 static uint64_t
1442 KSP(const struct iris_compiled_shader *shader)
1443 {
1444 struct iris_resource *res = (void *) shader->buffer;
1445 return res->bo->gtt_offset + shader->offset;
1446 }
1447
1448 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1449 pkt.KernelStartPointer = KSP(shader); \
1450 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
1451 pkt.FloatingPointMode = prog_data->use_alt_mode; \
1452 \
1453 pkt.DispatchGRFStartRegisterForURBData = \
1454 prog_data->dispatch_grf_start_reg; \
1455 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1456 pkt.prefix##URBEntryReadOffset = 0; \
1457 \
1458 pkt.StatisticsEnable = true; \
1459 pkt.Enable = true;
1460
1461 static void
1462 iris_set_vs_state(const struct gen_device_info *devinfo,
1463 struct iris_compiled_shader *shader)
1464 {
1465 struct brw_stage_prog_data *prog_data = shader->prog_data;
1466 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1467
1468 iris_pack_command(GENX(3DSTATE_VS), shader->derived_data, vs) {
1469 INIT_THREAD_DISPATCH_FIELDS(vs, Vertex);
1470 vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
1471 vs.SIMD8DispatchEnable = true;
1472 vs.UserClipDistanceCullTestEnableBitmask =
1473 vue_prog_data->cull_distance_mask;
1474 }
1475 }
1476
1477 static void
1478 iris_set_tcs_state(const struct gen_device_info *devinfo,
1479 struct iris_compiled_shader *shader)
1480 {
1481 struct brw_stage_prog_data *prog_data = shader->prog_data;
1482 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1483 struct brw_tcs_prog_data *tcs_prog_data = (void *) prog_data;
1484
1485 iris_pack_command(GENX(3DSTATE_HS), shader->derived_data, hs) {
1486 INIT_THREAD_DISPATCH_FIELDS(hs, Vertex);
1487
1488 hs.InstanceCount = tcs_prog_data->instances - 1;
1489 hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
1490 hs.IncludeVertexHandles = true;
1491 }
1492 }
1493
1494 static void
1495 iris_set_tes_state(const struct gen_device_info *devinfo,
1496 struct iris_compiled_shader *shader)
1497 {
1498 struct brw_stage_prog_data *prog_data = shader->prog_data;
1499 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1500 struct brw_tes_prog_data *tes_prog_data = (void *) prog_data;
1501
1502 uint32_t *te_state = (void *) shader->derived_data;
1503 uint32_t *ds_state = te_state + GENX(3DSTATE_TE_length);
1504
1505 iris_pack_command(GENX(3DSTATE_TE), te_state, te) {
1506 te.Partitioning = tes_prog_data->partitioning;
1507 te.OutputTopology = tes_prog_data->output_topology;
1508 te.TEDomain = tes_prog_data->domain;
1509 te.TEEnable = true;
1510 te.MaximumTessellationFactorOdd = 63.0;
1511 te.MaximumTessellationFactorNotOdd = 64.0;
1512 }
1513
1514 iris_pack_command(GENX(3DSTATE_DS), ds_state, ds) {
1515 INIT_THREAD_DISPATCH_FIELDS(ds, Patch);
1516
1517 ds.DispatchMode = DISPATCH_MODE_SIMD8_SINGLE_PATCH;
1518 ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
1519 ds.ComputeWCoordinateEnable =
1520 tes_prog_data->domain == BRW_TESS_DOMAIN_TRI;
1521
1522 ds.UserClipDistanceCullTestEnableBitmask =
1523 vue_prog_data->cull_distance_mask;
1524 }
1525
1526 }
1527
1528 static void
1529 iris_set_gs_state(const struct gen_device_info *devinfo,
1530 struct iris_compiled_shader *shader)
1531 {
1532 struct brw_stage_prog_data *prog_data = shader->prog_data;
1533 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1534 struct brw_gs_prog_data *gs_prog_data = (void *) prog_data;
1535
1536 iris_pack_command(GENX(3DSTATE_GS), shader->derived_data, gs) {
1537 INIT_THREAD_DISPATCH_FIELDS(gs, Vertex);
1538
1539 gs.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1;
1540 gs.OutputTopology = gs_prog_data->output_topology;
1541 gs.ControlDataHeaderSize =
1542 gs_prog_data->control_data_header_size_hwords;
1543 gs.InstanceControl = gs_prog_data->invocations - 1;
1544 gs.DispatchMode = SIMD8;
1545 gs.IncludePrimitiveID = gs_prog_data->include_primitive_id;
1546 gs.ControlDataFormat = gs_prog_data->control_data_format;
1547 gs.ReorderMode = TRAILING;
1548 gs.ExpectedVertexCount = gs_prog_data->vertices_in;
1549 gs.MaximumNumberofThreads =
1550 GEN_GEN == 8 ? (devinfo->max_gs_threads / 2 - 1)
1551 : (devinfo->max_gs_threads - 1);
1552
1553 if (gs_prog_data->static_vertex_count != -1) {
1554 gs.StaticOutput = true;
1555 gs.StaticOutputVertexCount = gs_prog_data->static_vertex_count;
1556 }
1557 gs.IncludeVertexHandles = vue_prog_data->include_vue_handles;
1558
1559 gs.UserClipDistanceCullTestEnableBitmask =
1560 vue_prog_data->cull_distance_mask;
1561
1562 const int urb_entry_write_offset = 1;
1563 const uint32_t urb_entry_output_length =
1564 DIV_ROUND_UP(vue_prog_data->vue_map.num_slots, 2) -
1565 urb_entry_write_offset;
1566
1567 gs.VertexURBEntryOutputReadOffset = urb_entry_write_offset;
1568 gs.VertexURBEntryOutputLength = MAX2(urb_entry_output_length, 1);
1569 }
1570 }
1571
1572 static void
1573 iris_set_fs_state(const struct gen_device_info *devinfo,
1574 struct iris_compiled_shader *shader)
1575 {
1576 struct brw_stage_prog_data *prog_data = shader->prog_data;
1577 struct brw_wm_prog_data *wm_prog_data = (void *) shader->prog_data;
1578
1579 uint32_t *ps_state = (void *) shader->derived_data;
1580 uint32_t *psx_state = ps_state + GENX(3DSTATE_PS_length);
1581
1582 iris_pack_command(GENX(3DSTATE_PS), ps_state, ps) {
1583 ps.VectorMaskEnable = true;
1584 //ps.SamplerCount = ...
1585 ps.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4;
1586 ps.FloatingPointMode = prog_data->use_alt_mode;
1587 ps.MaximumNumberofThreadsPerPSD = 64 - (GEN_GEN == 8 ? 2 : 1);
1588
1589 ps.PushConstantEnable = prog_data->nr_params > 0 ||
1590 prog_data->ubo_ranges[0].length > 0;
1591
1592 /* From the documentation for this packet:
1593 * "If the PS kernel does not need the Position XY Offsets to
1594 * compute a Position Value, then this field should be programmed
1595 * to POSOFFSET_NONE."
1596 *
1597 * "SW Recommendation: If the PS kernel needs the Position Offsets
1598 * to compute a Position XY value, this field should match Position
1599 * ZW Interpolation Mode to ensure a consistent position.xyzw
1600 * computation."
1601 *
1602 * We only require XY sample offsets. So, this recommendation doesn't
1603 * look useful at the moment. We might need this in future.
1604 */
1605 ps.PositionXYOffsetSelect =
1606 wm_prog_data->uses_pos_offset ? POSOFFSET_SAMPLE : POSOFFSET_NONE;
1607 ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
1608 ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
1609 ps._32PixelDispatchEnable = wm_prog_data->dispatch_32;
1610
1611 // XXX: Disable SIMD32 with 16x MSAA
1612
1613 ps.DispatchGRFStartRegisterForConstantSetupData0 =
1614 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 0);
1615 ps.DispatchGRFStartRegisterForConstantSetupData1 =
1616 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 1);
1617 ps.DispatchGRFStartRegisterForConstantSetupData2 =
1618 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 2);
1619
1620 ps.KernelStartPointer0 =
1621 KSP(shader) + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 0);
1622 ps.KernelStartPointer1 =
1623 KSP(shader) + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 1);
1624 ps.KernelStartPointer2 =
1625 KSP(shader) + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 2);
1626 }
1627
1628 iris_pack_command(GENX(3DSTATE_PS_EXTRA), psx_state, psx) {
1629 psx.PixelShaderValid = true;
1630 psx.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode;
1631 psx.PixelShaderKillsPixel = wm_prog_data->uses_kill;
1632 psx.AttributeEnable = wm_prog_data->num_varying_inputs != 0;
1633 psx.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth;
1634 psx.PixelShaderUsesSourceW = wm_prog_data->uses_src_w;
1635 psx.PixelShaderIsPerSample = wm_prog_data->persample_dispatch;
1636
1637 if (wm_prog_data->uses_sample_mask) {
1638 /* TODO: conservative rasterization */
1639 if (wm_prog_data->post_depth_coverage)
1640 psx.InputCoverageMaskState = ICMS_DEPTH_COVERAGE;
1641 else
1642 psx.InputCoverageMaskState = ICMS_NORMAL;
1643 }
1644
1645 psx.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask;
1646 psx.PixelShaderPullsBary = wm_prog_data->pulls_bary;
1647 psx.PixelShaderComputesStencil = wm_prog_data->computed_stencil;
1648
1649 // XXX: UAV bit
1650 }
1651 }
1652
1653 static unsigned
1654 iris_derived_program_state_size(enum iris_program_cache_id cache_id)
1655 {
1656 assert(cache_id <= IRIS_CACHE_CS);
1657
1658 static const unsigned dwords[] = {
1659 [IRIS_CACHE_VS] = GENX(3DSTATE_VS_length),
1660 [IRIS_CACHE_TCS] = GENX(3DSTATE_HS_length),
1661 [IRIS_CACHE_TES] = GENX(3DSTATE_TE_length) + GENX(3DSTATE_DS_length),
1662 [IRIS_CACHE_GS] = GENX(3DSTATE_GS_length),
1663 [IRIS_CACHE_FS] =
1664 GENX(3DSTATE_PS_length) + GENX(3DSTATE_PS_EXTRA_length),
1665 [IRIS_CACHE_CS] = 0,
1666 [IRIS_CACHE_BLORP_BLIT] = 0,
1667 };
1668
1669 return sizeof(uint32_t) * dwords[cache_id];
1670 }
1671
1672 static void
1673 iris_set_derived_program_state(const struct gen_device_info *devinfo,
1674 enum iris_program_cache_id cache_id,
1675 struct iris_compiled_shader *shader)
1676 {
1677 switch (cache_id) {
1678 case IRIS_CACHE_VS:
1679 iris_set_vs_state(devinfo, shader);
1680 break;
1681 case IRIS_CACHE_TCS:
1682 iris_set_tcs_state(devinfo, shader);
1683 break;
1684 case IRIS_CACHE_TES:
1685 iris_set_tes_state(devinfo, shader);
1686 break;
1687 case IRIS_CACHE_GS:
1688 iris_set_gs_state(devinfo, shader);
1689 break;
1690 case IRIS_CACHE_FS:
1691 iris_set_fs_state(devinfo, shader);
1692 break;
1693 case IRIS_CACHE_CS:
1694 break;
1695 default:
1696 break;
1697 }
1698 }
1699
1700 static void
1701 iris_upload_urb_config(struct iris_context *ice, struct iris_batch *batch)
1702 {
1703 const struct gen_device_info *devinfo = &batch->screen->devinfo;
1704 const unsigned push_size_kB = 32;
1705 unsigned entries[4];
1706 unsigned start[4];
1707 unsigned size[4];
1708
1709 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
1710 if (!ice->shaders.prog[i]) {
1711 size[i] = 1;
1712 } else {
1713 struct brw_vue_prog_data *vue_prog_data =
1714 (void *) ice->shaders.prog[i]->prog_data;
1715 size[i] = vue_prog_data->urb_entry_size;
1716 }
1717 assert(size[i] != 0);
1718 }
1719
1720 gen_get_urb_config(devinfo, 1024 * push_size_kB,
1721 1024 * ice->shaders.urb_size,
1722 ice->shaders.prog[MESA_SHADER_TESS_EVAL] != NULL,
1723 ice->shaders.prog[MESA_SHADER_GEOMETRY] != NULL,
1724 size, entries, start);
1725
1726 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
1727 iris_emit_cmd(batch, GENX(3DSTATE_URB_VS), urb) {
1728 urb._3DCommandSubOpcode += i;
1729 urb.VSURBStartingAddress = start[i];
1730 urb.VSURBEntryAllocationSize = size[i] - 1;
1731 urb.VSNumberofURBEntries = entries[i];
1732 }
1733 }
1734 }
1735
1736 static void
1737 iris_upload_render_state(struct iris_context *ice,
1738 struct iris_batch *batch,
1739 const struct pipe_draw_info *draw)
1740 {
1741 const uint64_t dirty = ice->state.dirty;
1742
1743 struct brw_wm_prog_data *wm_prog_data = (void *)
1744 ice->shaders.prog[MESA_SHADER_FRAGMENT]->prog_data;
1745
1746 if (dirty & IRIS_DIRTY_CC_VIEWPORT) {
1747 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1748 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), ptr) {
1749 ptr.CCViewportPointer =
1750 iris_emit_state(batch, cso->cc_vp, sizeof(cso->cc_vp), 32);
1751 }
1752 }
1753
1754 if (dirty & IRIS_DIRTY_SF_CL_VIEWPORT) {
1755 struct iris_viewport_state *cso = ice->state.cso_vp;
1756 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), ptr) {
1757 ptr.SFClipViewportPointer =
1758 iris_emit_state(batch, cso->sf_cl_vp, sizeof(cso->sf_cl_vp), 64);
1759 }
1760 }
1761
1762 /* XXX: L3 State */
1763
1764 if (dirty & IRIS_DIRTY_URB) {
1765 iris_upload_urb_config(ice, batch);
1766 }
1767
1768 if (dirty & IRIS_DIRTY_BLEND_STATE) {
1769 struct iris_blend_state *cso = ice->state.cso_blend;
1770 // XXX: 3DSTATE_BLEND_STATE_POINTERS - BLEND_STATE
1771 // -> from iris_blend_state (most) + iris_depth_stencil_alpha_state
1772 // (alpha test function/enable) + has writeable RT from ???????
1773 }
1774
1775 if (dirty & IRIS_DIRTY_COLOR_CALC_STATE) {
1776 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1777 uint32_t cc_offset;
1778 void *cc_map =
1779 iris_alloc_state(batch,
1780 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length),
1781 64, &cc_offset);
1782 iris_pack_state(GENX(COLOR_CALC_STATE), cc_map, cc) {
1783 cc.AlphaTestFormat = ALPHATEST_FLOAT32;
1784 cc.AlphaReferenceValueAsFLOAT32 = cso->alpha.ref_value;
1785 cc.BlendConstantColorRed = ice->state.blend_color.color[0];
1786 cc.BlendConstantColorGreen = ice->state.blend_color.color[1];
1787 cc.BlendConstantColorBlue = ice->state.blend_color.color[2];
1788 cc.BlendConstantColorAlpha = ice->state.blend_color.color[3];
1789 }
1790 iris_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
1791 ptr.ColorCalcStatePointer = cc_offset;
1792 ptr.ColorCalcStatePointerValid = true;
1793 }
1794 }
1795
1796 // XXX: 3DSTATE_CONSTANT_XS
1797 // Surfaces:
1798 // - pull constants
1799 // - ubos/ssbos/abos
1800 // - images
1801 // - textures
1802 // - render targets - write and read
1803 // XXX: 3DSTATE_BINDING_TABLE_POINTERS_XS
1804
1805 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
1806 if (!(dirty & (IRIS_DIRTY_SAMPLER_STATES_VS << stage)))
1807 continue;
1808
1809 // XXX: get sampler count from shader; don't emit them all...
1810 const int count = IRIS_MAX_TEXTURE_SAMPLERS;
1811
1812 uint32_t offset;
1813 uint32_t *map = iris_alloc_state(batch,
1814 count * 4 * GENX(SAMPLER_STATE_length),
1815 32, &offset);
1816
1817 for (int i = 0; i < count; i++) {
1818 // XXX: when we have a correct count, these better be bound
1819 if (!ice->state.samplers[stage][i])
1820 continue;
1821 memcpy(map, ice->state.samplers[stage][i]->sampler_state,
1822 4 * GENX(SAMPLER_STATE_length));
1823 map += GENX(SAMPLER_STATE_length);
1824 }
1825
1826 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ptr) {
1827 ptr._3DCommandSubOpcode = 43 + stage;
1828 ptr.PointertoVSSamplerState = offset;
1829 }
1830 }
1831
1832 if (dirty & IRIS_DIRTY_MULTISAMPLE) {
1833 iris_emit_cmd(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
1834 ms.PixelLocation =
1835 ice->state.cso_rast->half_pixel_center ? CENTER : UL_CORNER;
1836 if (ice->state.framebuffer.samples > 0)
1837 ms.NumberofMultisamples = ffs(ice->state.framebuffer.samples) - 1;
1838 }
1839 }
1840
1841 if (dirty & IRIS_DIRTY_SAMPLE_MASK) {
1842 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_MASK), ms) {
1843 ms.SampleMask = ice->state.sample_mask;
1844 }
1845 }
1846
1847 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
1848 if (!(dirty & (IRIS_DIRTY_VS << stage)))
1849 continue;
1850
1851 if (ice->shaders.prog[stage]) {
1852 iris_batch_emit(batch, ice->shaders.prog[stage]->derived_data,
1853 iris_derived_program_state_size(stage));
1854 } else {
1855 if (stage == MESA_SHADER_TESS_EVAL) {
1856 iris_emit_cmd(batch, GENX(3DSTATE_HS), hs);
1857 iris_emit_cmd(batch, GENX(3DSTATE_TE), te);
1858 iris_emit_cmd(batch, GENX(3DSTATE_DS), ds);
1859 } else if (stage == MESA_SHADER_GEOMETRY) {
1860 iris_emit_cmd(batch, GENX(3DSTATE_GS), gs);
1861 }
1862 }
1863 }
1864
1865 // XXX: SOL:
1866 // 3DSTATE_STREAMOUT
1867 // 3DSTATE_SO_BUFFER
1868 // 3DSTATE_SO_DECL_LIST
1869
1870 if (dirty & IRIS_DIRTY_CLIP) {
1871 struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
1872 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
1873
1874 uint32_t dynamic_clip[GENX(3DSTATE_CLIP_length)];
1875 iris_pack_command(GENX(3DSTATE_CLIP), &dynamic_clip, cl) {
1876 if (wm_prog_data->barycentric_interp_modes &
1877 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS)
1878 cl.NonPerspectiveBarycentricEnable = true;
1879
1880 cl.ForceZeroRTAIndexEnable = cso_fb->layers == 0;
1881 }
1882 iris_emit_merge(batch, cso_rast->clip, dynamic_clip,
1883 ARRAY_SIZE(cso_rast->clip));
1884 }
1885
1886 if (dirty & IRIS_DIRTY_RASTER) {
1887 struct iris_rasterizer_state *cso = ice->state.cso_rast;
1888 iris_batch_emit(batch, cso->raster, sizeof(cso->raster));
1889 iris_batch_emit(batch, cso->sf, sizeof(cso->sf));
1890
1891 }
1892
1893 if (dirty & (IRIS_DIRTY_RASTER | IRIS_DIRTY_FS)) {
1894 struct iris_rasterizer_state *cso = ice->state.cso_rast;
1895 uint32_t dynamic_wm[GENX(3DSTATE_WM_length)];
1896
1897 iris_pack_command(GENX(3DSTATE_WM), &dynamic_wm, wm) {
1898 wm.BarycentricInterpolationMode =
1899 wm_prog_data->barycentric_interp_modes;
1900
1901 if (wm_prog_data->early_fragment_tests)
1902 wm.EarlyDepthStencilControl = EDSC_PREPS;
1903 else if (wm_prog_data->has_side_effects)
1904 wm.EarlyDepthStencilControl = EDSC_PSEXEC;
1905 }
1906 iris_emit_merge(batch, cso->wm, dynamic_wm, ARRAY_SIZE(cso->wm));
1907 }
1908
1909 // XXX: 3DSTATE_SBE, 3DSTATE_SBE_SWIZ
1910 // -> iris_raster_state (point sprite texture coordinate origin)
1911 // -> bunch of shader state...
1912
1913 if (dirty & IRIS_DIRTY_PS_BLEND) {
1914 struct iris_blend_state *cso = ice->state.cso_blend;
1915 iris_batch_emit(batch, cso->ps_blend, sizeof(cso->ps_blend));
1916 }
1917
1918 if (dirty & IRIS_DIRTY_WM_DEPTH_STENCIL) {
1919 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1920 struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref;
1921
1922 uint32_t stencil_refs[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
1923 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), &stencil_refs, wmds) {
1924 wmds.StencilReferenceValue = p_stencil_refs->ref_value[0];
1925 wmds.BackfaceStencilReferenceValue = p_stencil_refs->ref_value[1];
1926 }
1927 iris_emit_merge(batch, cso->wmds, stencil_refs, ARRAY_SIZE(cso->wmds));
1928 }
1929
1930 if (dirty & IRIS_DIRTY_SCISSOR) {
1931 uint32_t scissor_offset =
1932 iris_emit_state(batch, ice->state.scissors,
1933 sizeof(struct pipe_scissor_state) *
1934 ice->state.num_scissors, 32);
1935
1936 iris_emit_cmd(batch, GENX(3DSTATE_SCISSOR_STATE_POINTERS), ptr) {
1937 ptr.ScissorRectPointer = scissor_offset;
1938 }
1939 }
1940
1941 // XXX: 3DSTATE_DEPTH_BUFFER
1942 // XXX: 3DSTATE_HIER_DEPTH_BUFFER
1943 // XXX: 3DSTATE_STENCIL_BUFFER
1944 // XXX: 3DSTATE_CLEAR_PARAMS
1945
1946 if (dirty & IRIS_DIRTY_POLYGON_STIPPLE) {
1947 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
1948 for (int i = 0; i < 32; i++) {
1949 poly.PatternRow[i] = ice->state.poly_stipple.stipple[i];
1950 }
1951 }
1952 }
1953
1954 if (dirty & IRIS_DIRTY_LINE_STIPPLE) {
1955 struct iris_rasterizer_state *cso = ice->state.cso_rast;
1956 iris_batch_emit(batch, cso->line_stipple, sizeof(cso->line_stipple));
1957 }
1958
1959 if (1) {
1960 iris_emit_cmd(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
1961 topo.PrimitiveTopologyType =
1962 translate_prim_type(draw->mode, draw->vertices_per_patch);
1963 }
1964 }
1965
1966 if (draw->index_size > 0) {
1967 struct iris_resource *res = (struct iris_resource *)draw->index.resource;
1968
1969 assert(!draw->has_user_indices);
1970
1971 iris_emit_cmd(batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
1972 ib.IndexFormat = draw->index_size;
1973 ib.MOCS = MOCS_WB;
1974 ib.BufferSize = res->bo->size;
1975 ib.BufferStartingAddress = ro_bo(res->bo, 0);
1976 }
1977 }
1978
1979 if (dirty & IRIS_DIRTY_VERTEX_BUFFERS) {
1980 struct iris_vertex_buffer_state *cso = ice->state.cso_vertex_buffers;
1981
1982 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_length) == 4);
1983 STATIC_ASSERT((GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) % 32) == 0);
1984
1985 uint64_t *addr = batch->cmdbuf.map_next + sizeof(uint32_t) *
1986 (GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) / 32);
1987 uint32_t *delta = cso->vertex_buffers +
1988 (1 + GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) / 32);
1989
1990 iris_batch_emit(batch, cso->vertex_buffers,
1991 sizeof(uint32_t) * (1 + 4 * cso->num_buffers));
1992
1993 for (unsigned i = 0; i < cso->num_buffers; i++) {
1994 *addr = iris_batch_reloc(batch, (void *) addr - batch->cmdbuf.map,
1995 cso->bos[i].bo, cso->bos[i].offset +
1996 *delta, cso->bos[i].reloc_flags);
1997 addr = (void *) addr + 16;
1998 delta = (void *) delta + 16;
1999 }
2000 }
2001
2002 if (dirty & IRIS_DIRTY_VERTEX_ELEMENTS) {
2003 struct iris_vertex_element_state *cso = ice->state.cso_vertex_elements;
2004 iris_batch_emit(batch, cso->vertex_elements, sizeof(uint32_t) *
2005 (1 + cso->count * GENX(VERTEX_ELEMENT_STATE_length)));
2006 for (int i = 0; i < cso->count; i++) {
2007 iris_batch_emit(batch, cso->vf_instancing[i], sizeof(uint32_t) *
2008 (cso->count * GENX(3DSTATE_VF_INSTANCING_length)));
2009 }
2010 for (int i = 0; i < cso->count; i++) {
2011 /* TODO: vertexid, instanceid support */
2012 iris_emit_cmd(batch, GENX(3DSTATE_VF_SGVS), sgvs);
2013 }
2014 }
2015
2016 if (1) {
2017 iris_emit_cmd(batch, GENX(3DSTATE_VF), vf) {
2018 if (draw->primitive_restart) {
2019 vf.IndexedDrawCutIndexEnable = true;
2020 vf.CutIndex = draw->restart_index;
2021 }
2022 }
2023 }
2024
2025 // XXX: Gen8 - PMA fix
2026
2027 assert(!draw->indirect); // XXX: indirect support
2028
2029 iris_emit_cmd(batch, GENX(3DPRIMITIVE), prim) {
2030 prim.StartInstanceLocation = draw->start_instance;
2031 prim.InstanceCount = draw->instance_count;
2032 prim.VertexCountPerInstance = draw->count;
2033 prim.VertexAccessType = draw->index_size > 0 ? RANDOM : SEQUENTIAL;
2034
2035 // XXX: this is probably bonkers.
2036 prim.StartVertexLocation = draw->start;
2037
2038 if (draw->index_size) {
2039 prim.BaseVertexLocation += draw->index_bias;
2040 } else {
2041 prim.StartVertexLocation += draw->index_bias;
2042 }
2043
2044 //prim.BaseVertexLocation = ...;
2045 }
2046 }
2047
2048 static void
2049 iris_destroy_state(struct iris_context *ice)
2050 {
2051 // XXX: unreference resources/surfaces.
2052 for (unsigned i = 0; i < ice->state.framebuffer.nr_cbufs; i++) {
2053 pipe_surface_reference(&ice->state.framebuffer.cbufs[i], NULL);
2054 }
2055 pipe_surface_reference(&ice->state.framebuffer.zsbuf, NULL);
2056 }
2057
2058 void
2059 genX(init_state)(struct iris_context *ice)
2060 {
2061 struct pipe_context *ctx = &ice->ctx;
2062
2063 ctx->create_blend_state = iris_create_blend_state;
2064 ctx->create_depth_stencil_alpha_state = iris_create_zsa_state;
2065 ctx->create_rasterizer_state = iris_create_rasterizer_state;
2066 ctx->create_sampler_state = iris_create_sampler_state;
2067 ctx->create_sampler_view = iris_create_sampler_view;
2068 ctx->create_surface = iris_create_surface;
2069 ctx->create_vertex_elements_state = iris_create_vertex_elements;
2070 ctx->create_compute_state = iris_create_compute_state;
2071 ctx->bind_blend_state = iris_bind_blend_state;
2072 ctx->bind_depth_stencil_alpha_state = iris_bind_zsa_state;
2073 ctx->bind_sampler_states = iris_bind_sampler_states;
2074 ctx->bind_rasterizer_state = iris_bind_rasterizer_state;
2075 ctx->bind_vertex_elements_state = iris_bind_vertex_elements_state;
2076 ctx->bind_compute_state = iris_bind_compute_state;
2077 ctx->delete_blend_state = iris_delete_state;
2078 ctx->delete_depth_stencil_alpha_state = iris_delete_state;
2079 ctx->delete_fs_state = iris_delete_state;
2080 ctx->delete_rasterizer_state = iris_delete_state;
2081 ctx->delete_sampler_state = iris_delete_state;
2082 ctx->delete_vertex_elements_state = iris_delete_state;
2083 ctx->delete_compute_state = iris_delete_state;
2084 ctx->delete_tcs_state = iris_delete_state;
2085 ctx->delete_tes_state = iris_delete_state;
2086 ctx->delete_gs_state = iris_delete_state;
2087 ctx->delete_vs_state = iris_delete_state;
2088 ctx->set_blend_color = iris_set_blend_color;
2089 ctx->set_clip_state = iris_set_clip_state;
2090 ctx->set_constant_buffer = iris_set_constant_buffer;
2091 ctx->set_sampler_views = iris_set_sampler_views;
2092 ctx->set_framebuffer_state = iris_set_framebuffer_state;
2093 ctx->set_polygon_stipple = iris_set_polygon_stipple;
2094 ctx->set_sample_mask = iris_set_sample_mask;
2095 ctx->set_scissor_states = iris_set_scissor_states;
2096 ctx->set_stencil_ref = iris_set_stencil_ref;
2097 ctx->set_vertex_buffers = iris_set_vertex_buffers;
2098 ctx->set_viewport_states = iris_set_viewport_states;
2099 ctx->sampler_view_destroy = iris_sampler_view_destroy;
2100 ctx->surface_destroy = iris_surface_destroy;
2101 ctx->draw_vbo = iris_draw_vbo;
2102 ctx->launch_grid = iris_launch_grid;
2103 ctx->create_stream_output_target = iris_create_stream_output_target;
2104 ctx->stream_output_target_destroy = iris_stream_output_target_destroy;
2105 ctx->set_stream_output_targets = iris_set_stream_output_targets;
2106
2107 ice->state.destroy_state = iris_destroy_state;
2108 ice->state.init_render_context = iris_init_render_context;
2109 ice->state.upload_render_state = iris_upload_render_state;
2110 ice->state.derived_program_state_size = iris_derived_program_state_size;
2111 ice->state.set_derived_program_state = iris_set_derived_program_state;
2112 ice->state.populate_vs_key = iris_populate_vs_key;
2113 ice->state.populate_tcs_key = iris_populate_tcs_key;
2114 ice->state.populate_tes_key = iris_populate_tes_key;
2115 ice->state.populate_gs_key = iris_populate_gs_key;
2116 ice->state.populate_fs_key = iris_populate_fs_key;
2117
2118
2119 ice->state.dirty = ~0ull;
2120 }