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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_dual_blend.h"
92 #include "util/u_inlines.h"
93 #include "util/u_format.h"
94 #include "util/u_framebuffer.h"
95 #include "util/u_transfer.h"
96 #include "util/u_upload_mgr.h"
97 #include "util/u_viewport.h"
98 #include "drm-uapi/i915_drm.h"
100 #include "intel/compiler/brw_compiler.h"
101 #include "intel/common/gen_l3_config.h"
102 #include "intel/common/gen_sample_positions.h"
103 #include "iris_batch.h"
104 #include "iris_context.h"
105 #include "iris_defines.h"
106 #include "iris_pipe.h"
107 #include "iris_resource.h"
109 #include "iris_genx_macros.h"
110 #include "intel/common/gen_guardband.h"
113 #define MOCS_PTE 0x18
116 #define MOCS_PTE (1 << 1)
117 #define MOCS_WB (2 << 1)
121 mocs(const struct iris_bo
*bo
)
123 return bo
&& bo
->external
? MOCS_PTE
: MOCS_WB
;
127 * Statically assert that PIPE_* enums match the hardware packets.
128 * (As long as they match, we don't need to translate them.)
130 UNUSED
static void pipe_asserts()
132 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
134 /* pipe_logicop happens to match the hardware. */
135 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
136 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
137 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
138 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
139 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
140 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
141 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
142 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
143 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
144 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
145 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
146 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
147 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
148 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
149 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
150 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
152 /* pipe_blend_func happens to match the hardware. */
153 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
160 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
161 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
162 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
163 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
164 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
165 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
166 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
167 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
168 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
169 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
170 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
171 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
173 /* pipe_blend_func happens to match the hardware. */
174 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
175 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
176 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
177 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
178 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
180 /* pipe_stencil_op happens to match the hardware. */
181 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
182 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
183 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
184 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
185 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
186 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
187 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
188 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
190 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
191 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
192 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
197 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
199 static const unsigned map
[] = {
200 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
201 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
202 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
203 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
204 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
205 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
206 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
207 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
208 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
209 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
210 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
211 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
212 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
213 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
214 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
217 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
221 translate_compare_func(enum pipe_compare_func pipe_func
)
223 static const unsigned map
[] = {
224 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
225 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
226 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
227 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
228 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
229 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
230 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
231 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
233 return map
[pipe_func
];
237 translate_shadow_func(enum pipe_compare_func pipe_func
)
239 /* Gallium specifies the result of shadow comparisons as:
241 * 1 if ref <op> texel,
246 * 0 if texel <op> ref,
249 * So we need to flip the operator and also negate.
251 static const unsigned map
[] = {
252 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
253 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
254 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
255 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
256 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
257 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
258 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
259 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
261 return map
[pipe_func
];
265 translate_cull_mode(unsigned pipe_face
)
267 static const unsigned map
[4] = {
268 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
269 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
270 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
271 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
273 return map
[pipe_face
];
277 translate_fill_mode(unsigned pipe_polymode
)
279 static const unsigned map
[4] = {
280 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
281 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
282 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
283 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
285 return map
[pipe_polymode
];
289 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
291 static const unsigned map
[] = {
292 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
293 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
294 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
296 return map
[pipe_mip
];
300 translate_wrap(unsigned pipe_wrap
)
302 static const unsigned map
[] = {
303 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
304 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
305 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
306 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
307 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
308 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
310 /* These are unsupported. */
311 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
312 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
314 return map
[pipe_wrap
];
318 * Allocate space for some indirect state.
320 * Return a pointer to the map (to fill it out) and a state ref (for
321 * referring to the state in GPU commands).
324 upload_state(struct u_upload_mgr
*uploader
,
325 struct iris_state_ref
*ref
,
330 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
335 * Stream out temporary/short-lived state.
337 * This allocates space, pins the BO, and includes the BO address in the
338 * returned offset (which works because all state lives in 32-bit memory
342 stream_state(struct iris_batch
*batch
,
343 struct u_upload_mgr
*uploader
,
344 struct pipe_resource
**out_res
,
347 uint32_t *out_offset
)
351 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
353 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
354 iris_use_pinned_bo(batch
, bo
, false);
356 *out_offset
+= iris_bo_offset_from_base_address(bo
);
358 iris_record_state_size(batch
->state_sizes
, *out_offset
, size
);
364 * stream_state() + memcpy.
367 emit_state(struct iris_batch
*batch
,
368 struct u_upload_mgr
*uploader
,
369 struct pipe_resource
**out_res
,
376 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
379 memcpy(map
, data
, size
);
385 * Did field 'x' change between 'old_cso' and 'new_cso'?
387 * (If so, we may want to set some dirty flags.)
389 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
390 #define cso_changed_memcmp(x) \
391 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
394 flush_before_state_base_change(struct iris_batch
*batch
)
396 /* Flush before emitting STATE_BASE_ADDRESS.
398 * This isn't documented anywhere in the PRM. However, it seems to be
399 * necessary prior to changing the surface state base adress. We've
400 * seen issues in Vulkan where we get GPU hangs when using multi-level
401 * command buffers which clear depth, reset state base address, and then
404 * Normally, in GL, we would trust the kernel to do sufficient stalls
405 * and flushes prior to executing our batch. However, it doesn't seem
406 * as if the kernel's flushing is always sufficient and we don't want to
409 * We make this an end-of-pipe sync instead of a normal flush because we
410 * do not know the current status of the GPU. On Haswell at least,
411 * having a fast-clear operation in flight at the same time as a normal
412 * rendering operation can cause hangs. Since the kernel's flushing is
413 * insufficient, we need to ensure that any rendering operations from
414 * other processes are definitely complete before we try to do our own
415 * rendering. It's a bit of a big hammer but it appears to work.
417 iris_emit_end_of_pipe_sync(batch
,
418 "change STATE_BASE_ADDRESS (flushes)",
419 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
420 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
421 PIPE_CONTROL_DATA_CACHE_FLUSH
);
425 flush_after_state_base_change(struct iris_batch
*batch
)
427 /* After re-setting the surface state base address, we have to do some
428 * cache flusing so that the sampler engine will pick up the new
429 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
430 * Shared Function > 3D Sampler > State > State Caching (page 96):
432 * Coherency with system memory in the state cache, like the texture
433 * cache is handled partially by software. It is expected that the
434 * command stream or shader will issue Cache Flush operation or
435 * Cache_Flush sampler message to ensure that the L1 cache remains
436 * coherent with system memory.
440 * Whenever the value of the Dynamic_State_Base_Addr,
441 * Surface_State_Base_Addr are altered, the L1 state cache must be
442 * invalidated to ensure the new surface or sampler state is fetched
443 * from system memory.
445 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
446 * which, according the PIPE_CONTROL instruction documentation in the
449 * Setting this bit is independent of any other bit in this packet.
450 * This bit controls the invalidation of the L1 and L2 state caches
451 * at the top of the pipe i.e. at the parsing time.
453 * Unfortunately, experimentation seems to indicate that state cache
454 * invalidation through a PIPE_CONTROL does nothing whatsoever in
455 * regards to surface state and binding tables. In stead, it seems that
456 * invalidating the texture cache is what is actually needed.
458 * XXX: As far as we have been able to determine through
459 * experimentation, shows that flush the texture cache appears to be
460 * sufficient. The theory here is that all of the sampling/rendering
461 * units cache the binding table in the texture cache. However, we have
462 * yet to be able to actually confirm this.
464 iris_emit_end_of_pipe_sync(batch
,
465 "change STATE_BASE_ADDRESS (invalidates)",
466 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
467 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
468 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
472 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
474 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
475 lri
.RegisterOffset
= reg
;
479 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
482 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
484 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
485 lrr
.SourceRegisterAddress
= src
;
486 lrr
.DestinationRegisterAddress
= dst
;
491 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
493 #if GEN_GEN >= 8 && GEN_GEN < 10
494 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
496 * Software must clear the COLOR_CALC_STATE Valid field in
497 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
498 * with Pipeline Select set to GPGPU.
500 * The internal hardware docs recommend the same workaround for Gen9
503 if (pipeline
== GPGPU
)
504 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
508 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
509 * PIPELINE_SELECT [DevBWR+]":
513 * Software must ensure all the write caches are flushed through a
514 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
515 * command to invalidate read only caches prior to programming
516 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
518 iris_emit_pipe_control_flush(batch
,
519 "workaround: PIPELINE_SELECT flushes (1/2)",
520 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
521 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
522 PIPE_CONTROL_DATA_CACHE_FLUSH
|
523 PIPE_CONTROL_CS_STALL
);
525 iris_emit_pipe_control_flush(batch
,
526 "workaround: PIPELINE_SELECT flushes (2/2)",
527 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
528 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
529 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
530 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
532 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
536 sel
.PipelineSelection
= pipeline
;
541 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
546 * "This chicken bit works around a hardware issue with barrier
547 * logic encountered when switching between GPGPU and 3D pipelines.
548 * To workaround the issue, this mode bit should be set after a
549 * pipeline is selected."
552 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
553 reg
.GLKBarrierMode
= value
;
554 reg
.GLKBarrierModeMask
= 1;
556 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
561 init_state_base_address(struct iris_batch
*batch
)
563 flush_before_state_base_change(batch
);
565 /* We program most base addresses once at context initialization time.
566 * Each base address points at a 4GB memory zone, and never needs to
567 * change. See iris_bufmgr.h for a description of the memory zones.
569 * The one exception is Surface State Base Address, which needs to be
570 * updated occasionally. See iris_binder.c for the details there.
572 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
573 sba
.GeneralStateMOCS
= MOCS_WB
;
574 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
575 sba
.DynamicStateMOCS
= MOCS_WB
;
576 sba
.IndirectObjectMOCS
= MOCS_WB
;
577 sba
.InstructionMOCS
= MOCS_WB
;
578 sba
.SurfaceStateMOCS
= MOCS_WB
;
580 sba
.GeneralStateBaseAddressModifyEnable
= true;
581 sba
.DynamicStateBaseAddressModifyEnable
= true;
582 sba
.IndirectObjectBaseAddressModifyEnable
= true;
583 sba
.InstructionBaseAddressModifyEnable
= true;
584 sba
.GeneralStateBufferSizeModifyEnable
= true;
585 sba
.DynamicStateBufferSizeModifyEnable
= true;
587 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
588 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
590 sba
.IndirectObjectBufferSizeModifyEnable
= true;
591 sba
.InstructionBuffersizeModifyEnable
= true;
593 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
594 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
596 sba
.GeneralStateBufferSize
= 0xfffff;
597 sba
.IndirectObjectBufferSize
= 0xfffff;
598 sba
.InstructionBufferSize
= 0xfffff;
599 sba
.DynamicStateBufferSize
= 0xfffff;
602 flush_after_state_base_change(batch
);
606 iris_emit_l3_config(struct iris_batch
*batch
, const struct gen_l3_config
*cfg
,
607 bool has_slm
, bool wants_dc_cache
)
612 #define L3_ALLOCATION_REG GENX(L3ALLOC)
613 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
615 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
616 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
619 iris_pack_state(L3_ALLOCATION_REG
, ®_val
, reg
) {
621 reg
.SLMEnable
= has_slm
;
624 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
625 * in L3CNTLREG register. The default setting of the bit is not the
626 * desirable behavior.
628 reg
.ErrorDetectionBehaviorControl
= true;
629 reg
.UseFullWays
= true;
631 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
632 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
633 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
634 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
636 _iris_emit_lri(batch
, L3_ALLOCATION_REG_num
, reg_val
);
640 iris_emit_default_l3_config(struct iris_batch
*batch
,
641 const struct gen_device_info
*devinfo
,
644 bool wants_dc_cache
= true;
645 bool has_slm
= compute
;
646 const struct gen_l3_weights w
=
647 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
648 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
649 iris_emit_l3_config(batch
, cfg
, has_slm
, wants_dc_cache
);
652 #if GEN_GEN == 9 || GEN_GEN == 10
654 iris_enable_obj_preemption(struct iris_batch
*batch
, bool enable
)
658 /* A fixed function pipe flush is required before modifying this field */
659 iris_emit_end_of_pipe_sync(batch
, enable
? "enable preemption"
660 : "disable preemption",
661 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
663 /* enable object level preemption */
664 iris_pack_state(GENX(CS_CHICKEN1
), ®_val
, reg
) {
665 reg
.ReplayMode
= enable
;
666 reg
.ReplayModeMask
= true;
668 iris_emit_lri(batch
, CS_CHICKEN1
, reg_val
);
674 iris_upload_slice_hashing_state(struct iris_batch
*batch
)
676 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
677 int subslices_delta
=
678 devinfo
->ppipe_subslices
[0] - devinfo
->ppipe_subslices
[1];
679 if (subslices_delta
== 0)
682 struct iris_context
*ice
= NULL
;
683 ice
= container_of(batch
, ice
, batches
[IRIS_BATCH_RENDER
]);
684 assert(&ice
->batches
[IRIS_BATCH_RENDER
] == batch
);
686 unsigned size
= GENX(SLICE_HASH_TABLE_length
) * 4;
687 uint32_t hash_address
;
688 struct pipe_resource
*tmp
= NULL
;
690 stream_state(batch
, ice
->state
.dynamic_uploader
, &tmp
,
691 size
, 64, &hash_address
);
692 pipe_resource_reference(&tmp
, NULL
);
694 struct GENX(SLICE_HASH_TABLE
) table0
= {
696 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
697 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
698 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
699 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
700 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
701 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
702 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
703 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
704 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
705 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
706 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
707 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
708 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
709 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
710 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
711 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }
715 struct GENX(SLICE_HASH_TABLE
) table1
= {
717 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
718 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
719 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
720 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
721 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
722 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
723 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
724 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
725 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
726 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
727 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
728 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
729 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
730 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
731 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
732 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }
736 const struct GENX(SLICE_HASH_TABLE
) *table
=
737 subslices_delta
< 0 ? &table0
: &table1
;
738 GENX(SLICE_HASH_TABLE_pack
)(NULL
, map
, table
);
740 iris_emit_cmd(batch
, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS
), ptr
) {
741 ptr
.SliceHashStatePointerValid
= true;
742 ptr
.SliceHashTableStatePointer
= hash_address
;
745 iris_emit_cmd(batch
, GENX(3DSTATE_3D_MODE
), mode
) {
746 mode
.SliceHashingTableEnable
= true;
752 * Upload the initial GPU state for a render context.
754 * This sets some invariant state that needs to be programmed a particular
755 * way, but we never actually change.
758 iris_init_render_context(struct iris_screen
*screen
,
759 struct iris_batch
*batch
,
760 struct iris_vtable
*vtbl
,
761 struct pipe_debug_callback
*dbg
)
763 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
766 emit_pipeline_select(batch
, _3D
);
768 iris_emit_default_l3_config(batch
, devinfo
, false);
770 init_state_base_address(batch
);
773 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
774 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
775 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
777 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
779 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
780 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
781 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
783 iris_emit_lri(batch
, INSTPM
, reg_val
);
787 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
788 reg
.FloatBlendOptimizationEnable
= true;
789 reg
.FloatBlendOptimizationEnableMask
= true;
790 reg
.PartialResolveDisableInVC
= true;
791 reg
.PartialResolveDisableInVCMask
= true;
793 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
795 if (devinfo
->is_geminilake
)
796 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
800 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
801 reg
.HeaderlessMessageforPreemptableContexts
= 1;
802 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
804 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
806 /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
807 iris_pack_state(GENX(HALF_SLICE_CHICKEN7
), ®_val
, reg
) {
808 reg
.EnabledTexelOffsetPrecisionFix
= 1;
809 reg
.EnabledTexelOffsetPrecisionFixMask
= 1;
811 iris_emit_lri(batch
, HALF_SLICE_CHICKEN7
, reg_val
);
813 /* Hardware specification recommends disabling repacking for the
814 * compatibility with decompression mechanism in display controller.
816 if (devinfo
->disable_ccs_repack
) {
817 iris_pack_state(GENX(CACHE_MODE_0
), ®_val
, reg
) {
818 reg
.DisableRepackingforCompression
= true;
819 reg
.DisableRepackingforCompressionMask
= true;
821 iris_emit_lri(batch
, CACHE_MODE_0
, reg_val
);
824 iris_upload_slice_hashing_state(batch
);
828 /* WA_220160979: Enable Hardware filtering of Semi-Pipelined State in WM */
829 iris_pack_state(GENX(COMMON_SLICE_CHICKEN4
), ®_val
, reg
) {
830 reg
.EnableHardwareFilteringinWM
= true;
831 reg
.EnableHardwareFilteringinWMMask
= true;
833 iris_emit_lri(batch
, COMMON_SLICE_CHICKEN4
, reg_val
);
836 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
837 * changing it dynamically. We set it to the maximum size here, and
838 * instead include the render target dimensions in the viewport, so
839 * viewport extents clipping takes care of pruning stray geometry.
841 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
842 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
843 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
846 /* Set the initial MSAA sample positions. */
847 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
848 GEN_SAMPLE_POS_1X(pat
._1xSample
);
849 GEN_SAMPLE_POS_2X(pat
._2xSample
);
850 GEN_SAMPLE_POS_4X(pat
._4xSample
);
851 GEN_SAMPLE_POS_8X(pat
._8xSample
);
853 GEN_SAMPLE_POS_16X(pat
._16xSample
);
857 /* Use the legacy AA line coverage computation. */
858 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
860 /* Disable chromakeying (it's for media) */
861 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
863 /* We want regular rendering, not special HiZ operations. */
864 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
866 /* No polygon stippling offsets are necessary. */
867 /* TODO: may need to set an offset for origin-UL framebuffers */
868 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
870 /* Set a static partitioning of the push constant area. */
871 /* TODO: this may be a bad idea...could starve the push ringbuffers... */
872 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
873 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
874 alloc
._3DCommandSubOpcode
= 18 + i
;
875 alloc
.ConstantBufferOffset
= 6 * i
;
876 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
881 /* Gen11+ is enabled for us by the kernel. */
882 iris_enable_obj_preemption(batch
, true);
887 iris_init_compute_context(struct iris_screen
*screen
,
888 struct iris_batch
*batch
,
889 struct iris_vtable
*vtbl
,
890 struct pipe_debug_callback
*dbg
)
892 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
894 emit_pipeline_select(batch
, GPGPU
);
896 iris_emit_default_l3_config(batch
, devinfo
, true);
898 init_state_base_address(batch
);
901 if (devinfo
->is_geminilake
)
902 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
906 struct iris_vertex_buffer_state
{
907 /** The VERTEX_BUFFER_STATE hardware structure. */
908 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
910 /** The resource to source vertex data from. */
911 struct pipe_resource
*resource
;
914 struct iris_depth_buffer_state
{
915 /* Depth/HiZ/Stencil related hardware packets. */
916 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
917 GENX(3DSTATE_STENCIL_BUFFER_length
) +
918 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
919 GENX(3DSTATE_CLEAR_PARAMS_length
)];
923 * Generation-specific context state (ice->state.genx->...).
925 * Most state can go in iris_context directly, but these encode hardware
926 * packets which vary by generation.
928 struct iris_genx_state
{
929 struct iris_vertex_buffer_state vertex_buffers
[33];
930 uint32_t last_index_buffer
[GENX(3DSTATE_INDEX_BUFFER_length
)];
932 struct iris_depth_buffer_state depth_buffer
;
934 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
937 /* Is object level preemption enabled? */
938 bool object_preemption
;
943 struct brw_image_param image_param
[PIPE_MAX_SHADER_IMAGES
];
945 } shaders
[MESA_SHADER_STAGES
];
949 * The pipe->set_blend_color() driver hook.
951 * This corresponds to our COLOR_CALC_STATE.
954 iris_set_blend_color(struct pipe_context
*ctx
,
955 const struct pipe_blend_color
*state
)
957 struct iris_context
*ice
= (struct iris_context
*) ctx
;
959 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
960 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
961 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
965 * Gallium CSO for blend state (see pipe_blend_state).
967 struct iris_blend_state
{
968 /** Partial 3DSTATE_PS_BLEND */
969 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
971 /** Partial BLEND_STATE */
972 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
973 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
975 bool alpha_to_coverage
; /* for shader key */
977 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
978 uint8_t blend_enables
;
980 /** Bitfield of whether color writes are enabled for RT[i] */
981 uint8_t color_write_enables
;
983 /** Does RT[0] use dual color blending? */
984 bool dual_color_blending
;
987 static enum pipe_blendfactor
988 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
991 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
992 return PIPE_BLENDFACTOR_ONE
;
994 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
995 return PIPE_BLENDFACTOR_ZERO
;
1002 * The pipe->create_blend_state() driver hook.
1004 * Translates a pipe_blend_state into iris_blend_state.
1007 iris_create_blend_state(struct pipe_context
*ctx
,
1008 const struct pipe_blend_state
*state
)
1010 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
1011 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
1013 cso
->blend_enables
= 0;
1014 cso
->color_write_enables
= 0;
1015 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
1017 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
1019 bool indep_alpha_blend
= false;
1021 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
1022 const struct pipe_rt_blend_state
*rt
=
1023 &state
->rt
[state
->independent_blend_enable
? i
: 0];
1025 enum pipe_blendfactor src_rgb
=
1026 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
1027 enum pipe_blendfactor src_alpha
=
1028 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
1029 enum pipe_blendfactor dst_rgb
=
1030 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
1031 enum pipe_blendfactor dst_alpha
=
1032 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
1034 if (rt
->rgb_func
!= rt
->alpha_func
||
1035 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
1036 indep_alpha_blend
= true;
1038 if (rt
->blend_enable
)
1039 cso
->blend_enables
|= 1u << i
;
1042 cso
->color_write_enables
|= 1u << i
;
1044 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
1045 be
.LogicOpEnable
= state
->logicop_enable
;
1046 be
.LogicOpFunction
= state
->logicop_func
;
1048 be
.PreBlendSourceOnlyClampEnable
= false;
1049 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
1050 be
.PreBlendColorClampEnable
= true;
1051 be
.PostBlendColorClampEnable
= true;
1053 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
1055 be
.ColorBlendFunction
= rt
->rgb_func
;
1056 be
.AlphaBlendFunction
= rt
->alpha_func
;
1057 be
.SourceBlendFactor
= src_rgb
;
1058 be
.SourceAlphaBlendFactor
= src_alpha
;
1059 be
.DestinationBlendFactor
= dst_rgb
;
1060 be
.DestinationAlphaBlendFactor
= dst_alpha
;
1062 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
1063 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
1064 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
1065 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
1067 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
1070 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
1071 /* pb.HasWriteableRT is filled in at draw time.
1072 * pb.AlphaTestEnable is filled in at draw time.
1074 * pb.ColorBufferBlendEnable is filled in at draw time so we can avoid
1075 * setting it when dual color blending without an appropriate shader.
1078 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1079 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1081 pb
.SourceBlendFactor
=
1082 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
1083 pb
.SourceAlphaBlendFactor
=
1084 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
1085 pb
.DestinationBlendFactor
=
1086 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
1087 pb
.DestinationAlphaBlendFactor
=
1088 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
1091 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
1092 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1093 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1094 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
1095 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
1096 bs
.ColorDitherEnable
= state
->dither
;
1097 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
1100 cso
->dual_color_blending
= util_blend_state_is_dual(state
, 0);
1106 * The pipe->bind_blend_state() driver hook.
1108 * Bind a blending CSO and flag related dirty bits.
1111 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
1113 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1114 struct iris_blend_state
*cso
= state
;
1116 ice
->state
.cso_blend
= cso
;
1117 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
1119 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1120 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1121 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1122 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
1126 * Return true if the FS writes to any color outputs which are not disabled
1127 * via color masking.
1130 has_writeable_rt(const struct iris_blend_state
*cso_blend
,
1131 const struct shader_info
*fs_info
)
1136 unsigned rt_outputs
= fs_info
->outputs_written
>> FRAG_RESULT_DATA0
;
1138 if (fs_info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
))
1139 rt_outputs
= (1 << BRW_MAX_DRAW_BUFFERS
) - 1;
1141 return cso_blend
->color_write_enables
& rt_outputs
;
1145 * Gallium CSO for depth, stencil, and alpha testing state.
1147 struct iris_depth_stencil_alpha_state
{
1148 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
1149 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1151 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
1152 struct pipe_alpha_state alpha
;
1154 /** Outbound to resolve and cache set tracking. */
1155 bool depth_writes_enabled
;
1156 bool stencil_writes_enabled
;
1160 * The pipe->create_depth_stencil_alpha_state() driver hook.
1162 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
1163 * testing state since we need pieces of it in a variety of places.
1166 iris_create_zsa_state(struct pipe_context
*ctx
,
1167 const struct pipe_depth_stencil_alpha_state
*state
)
1169 struct iris_depth_stencil_alpha_state
*cso
=
1170 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
1172 bool two_sided_stencil
= state
->stencil
[1].enabled
;
1174 cso
->alpha
= state
->alpha
;
1175 cso
->depth_writes_enabled
= state
->depth
.writemask
;
1176 cso
->stencil_writes_enabled
=
1177 state
->stencil
[0].writemask
!= 0 ||
1178 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1180 /* The state tracker needs to optimize away EQUAL writes for us. */
1181 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
1183 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
1184 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1185 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1186 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1187 wmds
.StencilTestFunction
=
1188 translate_compare_func(state
->stencil
[0].func
);
1189 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1190 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1191 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1192 wmds
.BackfaceStencilTestFunction
=
1193 translate_compare_func(state
->stencil
[1].func
);
1194 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1195 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1196 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1197 wmds
.StencilBufferWriteEnable
=
1198 state
->stencil
[0].writemask
!= 0 ||
1199 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1200 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1201 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1202 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1203 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1204 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1205 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1206 /* wmds.[Backface]StencilReferenceValue are merged later */
1213 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1215 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1218 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1220 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1221 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1222 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1225 if (cso_changed(alpha
.ref_value
))
1226 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1228 if (cso_changed(alpha
.enabled
))
1229 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1231 if (cso_changed(alpha
.func
))
1232 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1234 if (cso_changed(depth_writes_enabled
))
1235 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1237 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1238 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1241 ice
->state
.cso_zsa
= new_cso
;
1242 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1243 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1244 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1248 * Gallium CSO for rasterizer state.
1250 struct iris_rasterizer_state
{
1251 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1252 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1253 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1254 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1255 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1257 uint8_t num_clip_plane_consts
;
1258 bool clip_halfz
; /* for CC_VIEWPORT */
1259 bool depth_clip_near
; /* for CC_VIEWPORT */
1260 bool depth_clip_far
; /* for CC_VIEWPORT */
1261 bool flatshade
; /* for shader state */
1262 bool flatshade_first
; /* for stream output */
1263 bool clamp_fragment_color
; /* for shader state */
1264 bool light_twoside
; /* for shader state */
1265 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1266 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1267 bool line_stipple_enable
;
1268 bool poly_stipple_enable
;
1270 bool force_persample_interp
;
1271 bool conservative_rasterization
;
1272 bool fill_mode_point_or_line
;
1273 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1274 uint16_t sprite_coord_enable
;
1278 get_line_width(const struct pipe_rasterizer_state
*state
)
1280 float line_width
= state
->line_width
;
1282 /* From the OpenGL 4.4 spec:
1284 * "The actual width of non-antialiased lines is determined by rounding
1285 * the supplied width to the nearest integer, then clamping it to the
1286 * implementation-dependent maximum non-antialiased line width."
1288 if (!state
->multisample
&& !state
->line_smooth
)
1289 line_width
= roundf(state
->line_width
);
1291 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1292 /* For 1 pixel line thickness or less, the general anti-aliasing
1293 * algorithm gives up, and a garbage line is generated. Setting a
1294 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1295 * (one-pixel-wide), non-antialiased lines.
1297 * Lines rendered with zero Line Width are rasterized using the
1298 * "Grid Intersection Quantization" rules as specified by the
1299 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1308 * The pipe->create_rasterizer_state() driver hook.
1311 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1312 const struct pipe_rasterizer_state
*state
)
1314 struct iris_rasterizer_state
*cso
=
1315 malloc(sizeof(struct iris_rasterizer_state
));
1317 cso
->multisample
= state
->multisample
;
1318 cso
->force_persample_interp
= state
->force_persample_interp
;
1319 cso
->clip_halfz
= state
->clip_halfz
;
1320 cso
->depth_clip_near
= state
->depth_clip_near
;
1321 cso
->depth_clip_far
= state
->depth_clip_far
;
1322 cso
->flatshade
= state
->flatshade
;
1323 cso
->flatshade_first
= state
->flatshade_first
;
1324 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1325 cso
->light_twoside
= state
->light_twoside
;
1326 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1327 cso
->half_pixel_center
= state
->half_pixel_center
;
1328 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1329 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1330 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1331 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1332 cso
->conservative_rasterization
=
1333 state
->conservative_raster_mode
== PIPE_CONSERVATIVE_RASTER_POST_SNAP
;
1335 cso
->fill_mode_point_or_line
=
1336 state
->fill_front
== PIPE_POLYGON_MODE_LINE
||
1337 state
->fill_front
== PIPE_POLYGON_MODE_POINT
||
1338 state
->fill_back
== PIPE_POLYGON_MODE_LINE
||
1339 state
->fill_back
== PIPE_POLYGON_MODE_POINT
;
1341 if (state
->clip_plane_enable
!= 0)
1342 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1344 cso
->num_clip_plane_consts
= 0;
1346 float line_width
= get_line_width(state
);
1348 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1349 sf
.StatisticsEnable
= true;
1350 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1351 sf
.LineEndCapAntialiasingRegionWidth
=
1352 state
->line_smooth
? _10pixels
: _05pixels
;
1353 sf
.LastPixelEnable
= state
->line_last_pixel
;
1354 sf
.LineWidth
= line_width
;
1355 sf
.SmoothPointEnable
= (state
->point_smooth
|| state
->multisample
) &&
1356 !state
->point_quad_rasterization
;
1357 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1358 sf
.PointWidth
= state
->point_size
;
1360 if (state
->flatshade_first
) {
1361 sf
.TriangleFanProvokingVertexSelect
= 1;
1363 sf
.TriangleStripListProvokingVertexSelect
= 2;
1364 sf
.TriangleFanProvokingVertexSelect
= 2;
1365 sf
.LineStripListProvokingVertexSelect
= 1;
1369 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1370 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1371 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1372 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1373 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1374 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1375 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1376 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1377 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1378 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1379 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1380 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1381 rr
.SmoothPointEnable
= state
->point_smooth
;
1382 rr
.AntialiasingEnable
= state
->line_smooth
;
1383 rr
.ScissorRectangleEnable
= state
->scissor
;
1385 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1386 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1387 rr
.ConservativeRasterizationEnable
=
1388 cso
->conservative_rasterization
;
1390 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1394 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1395 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1396 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1398 cl
.EarlyCullEnable
= true;
1399 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1400 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1401 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1402 cl
.GuardbandClipTestEnable
= true;
1403 cl
.ClipEnable
= true;
1404 cl
.MinimumPointWidth
= 0.125;
1405 cl
.MaximumPointWidth
= 255.875;
1407 if (state
->flatshade_first
) {
1408 cl
.TriangleFanProvokingVertexSelect
= 1;
1410 cl
.TriangleStripListProvokingVertexSelect
= 2;
1411 cl
.TriangleFanProvokingVertexSelect
= 2;
1412 cl
.LineStripListProvokingVertexSelect
= 1;
1416 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1417 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1418 * filled in at draw time from the FS program.
1420 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1421 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1422 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1423 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1424 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1427 /* Remap from 0..255 back to 1..256 */
1428 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1430 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1431 if (state
->line_stipple_enable
) {
1432 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1433 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1434 line
.LineStippleRepeatCount
= line_stipple_factor
;
1442 * The pipe->bind_rasterizer_state() driver hook.
1444 * Bind a rasterizer CSO and flag related dirty bits.
1447 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1449 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1450 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1451 struct iris_rasterizer_state
*new_cso
= state
;
1454 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1455 if (cso_changed_memcmp(line_stipple
))
1456 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1458 if (cso_changed(half_pixel_center
))
1459 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1461 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1462 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1464 if (cso_changed(rasterizer_discard
))
1465 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1467 if (cso_changed(flatshade_first
))
1468 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1470 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1471 cso_changed(clip_halfz
))
1472 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1474 if (cso_changed(sprite_coord_enable
) ||
1475 cso_changed(sprite_coord_mode
) ||
1476 cso_changed(light_twoside
))
1477 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1479 if (cso_changed(conservative_rasterization
))
1480 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
1483 ice
->state
.cso_rast
= new_cso
;
1484 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1485 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1486 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1490 * Return true if the given wrap mode requires the border color to exist.
1492 * (We can skip uploading it if the sampler isn't going to use it.)
1495 wrap_mode_needs_border_color(unsigned wrap_mode
)
1497 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1501 * Gallium CSO for sampler state.
1503 struct iris_sampler_state
{
1504 union pipe_color_union border_color
;
1505 bool needs_border_color
;
1507 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1511 * The pipe->create_sampler_state() driver hook.
1513 * We fill out SAMPLER_STATE (except for the border color pointer), and
1514 * store that on the CPU. It doesn't make sense to upload it to a GPU
1515 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1516 * all bound sampler states to be in contiguous memor.
1519 iris_create_sampler_state(struct pipe_context
*ctx
,
1520 const struct pipe_sampler_state
*state
)
1522 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1527 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1528 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1530 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1531 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1532 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1534 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1536 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1537 wrap_mode_needs_border_color(wrap_t
) ||
1538 wrap_mode_needs_border_color(wrap_r
);
1540 float min_lod
= state
->min_lod
;
1541 unsigned mag_img_filter
= state
->mag_img_filter
;
1543 // XXX: explain this code ported from ilo...I don't get it at all...
1544 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1545 state
->min_lod
> 0.0f
) {
1547 mag_img_filter
= state
->min_img_filter
;
1550 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1551 samp
.TCXAddressControlMode
= wrap_s
;
1552 samp
.TCYAddressControlMode
= wrap_t
;
1553 samp
.TCZAddressControlMode
= wrap_r
;
1554 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1555 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1556 samp
.MinModeFilter
= state
->min_img_filter
;
1557 samp
.MagModeFilter
= mag_img_filter
;
1558 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1559 samp
.MaximumAnisotropy
= RATIO21
;
1561 if (state
->max_anisotropy
>= 2) {
1562 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1563 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1564 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1567 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1568 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1570 samp
.MaximumAnisotropy
=
1571 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1574 /* Set address rounding bits if not using nearest filtering. */
1575 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1576 samp
.UAddressMinFilterRoundingEnable
= true;
1577 samp
.VAddressMinFilterRoundingEnable
= true;
1578 samp
.RAddressMinFilterRoundingEnable
= true;
1581 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1582 samp
.UAddressMagFilterRoundingEnable
= true;
1583 samp
.VAddressMagFilterRoundingEnable
= true;
1584 samp
.RAddressMagFilterRoundingEnable
= true;
1587 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1588 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1590 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1592 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1593 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1594 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1595 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1597 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1604 * The pipe->bind_sampler_states() driver hook.
1607 iris_bind_sampler_states(struct pipe_context
*ctx
,
1608 enum pipe_shader_type p_stage
,
1609 unsigned start
, unsigned count
,
1612 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1613 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1614 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1616 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1620 for (int i
= 0; i
< count
; i
++) {
1621 if (shs
->samplers
[start
+ i
] != states
[i
]) {
1622 shs
->samplers
[start
+ i
] = states
[i
];
1628 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1632 * Upload the sampler states into a contiguous area of GPU memory, for
1633 * for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1635 * Also fill out the border color state pointers.
1638 iris_upload_sampler_states(struct iris_context
*ice
, gl_shader_stage stage
)
1640 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1641 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
1643 /* We assume the state tracker will call pipe->bind_sampler_states()
1644 * if the program's number of textures changes.
1646 unsigned count
= info
? util_last_bit(info
->textures_used
) : 0;
1651 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1652 * in the dynamic state memory zone, so we can point to it via the
1653 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1655 unsigned size
= count
* 4 * GENX(SAMPLER_STATE_length
);
1657 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
, size
, 32);
1661 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1662 shs
->sampler_table
.offset
+=
1663 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1665 iris_record_state_size(ice
->state
.sizes
, shs
->sampler_table
.offset
, size
);
1667 /* Make sure all land in the same BO */
1668 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1670 ice
->state
.need_border_colors
&= ~(1 << stage
);
1672 for (int i
= 0; i
< count
; i
++) {
1673 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1674 struct iris_sampler_view
*tex
= shs
->textures
[i
];
1677 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1678 } else if (!state
->needs_border_color
) {
1679 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1681 ice
->state
.need_border_colors
|= 1 << stage
;
1683 /* We may need to swizzle the border color for format faking.
1684 * A/LA formats are faked as R/RG with 000R or R00G swizzles.
1685 * This means we need to move the border color's A channel into
1686 * the R or G channels so that those read swizzles will move it
1689 union pipe_color_union
*color
= &state
->border_color
;
1690 union pipe_color_union tmp
;
1692 enum pipe_format internal_format
= tex
->res
->internal_format
;
1694 if (util_format_is_alpha(internal_format
)) {
1695 unsigned char swz
[4] = {
1696 PIPE_SWIZZLE_W
, PIPE_SWIZZLE_0
,
1697 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1699 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1701 } else if (util_format_is_luminance_alpha(internal_format
) &&
1702 internal_format
!= PIPE_FORMAT_L8A8_SRGB
) {
1703 unsigned char swz
[4] = {
1704 PIPE_SWIZZLE_X
, PIPE_SWIZZLE_W
,
1705 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1707 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1712 /* Stream out the border color and merge the pointer. */
1713 uint32_t offset
= iris_upload_border_color(ice
, color
);
1715 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1716 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1717 dyns
.BorderColorPointer
= offset
;
1720 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1721 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1724 map
+= GENX(SAMPLER_STATE_length
);
1728 static enum isl_channel_select
1729 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1732 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1733 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1734 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1735 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1736 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1737 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1738 default: unreachable("invalid swizzle");
1743 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1744 struct iris_resource
*res
,
1746 enum isl_format format
,
1747 struct isl_swizzle swizzle
,
1751 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1752 const unsigned cpp
= format
== ISL_FORMAT_RAW
? 1 : fmtl
->bpb
/ 8;
1754 /* The ARB_texture_buffer_specification says:
1756 * "The number of texels in the buffer texture's texel array is given by
1758 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1760 * where <buffer_size> is the size of the buffer object, in basic
1761 * machine units and <components> and <base_type> are the element count
1762 * and base data type for elements, as specified in Table X.1. The
1763 * number of texels in the texel array is then clamped to the
1764 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1766 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1767 * so that when ISL divides by stride to obtain the number of texels, that
1768 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1770 unsigned final_size
=
1771 MIN3(size
, res
->bo
->size
- res
->offset
- offset
,
1772 IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1774 isl_buffer_fill_state(isl_dev
, map
,
1775 .address
= res
->bo
->gtt_offset
+ res
->offset
+ offset
,
1776 .size_B
= final_size
,
1780 .mocs
= mocs(res
->bo
));
1783 #define SURFACE_STATE_ALIGNMENT 64
1786 * Allocate several contiguous SURFACE_STATE structures, one for each
1787 * supported auxiliary surface mode.
1790 alloc_surface_states(struct u_upload_mgr
*mgr
,
1791 struct iris_state_ref
*ref
,
1792 unsigned aux_usages
)
1794 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
1796 /* If this changes, update this to explicitly align pointers */
1797 STATIC_ASSERT(surf_size
== SURFACE_STATE_ALIGNMENT
);
1799 assert(aux_usages
!= 0);
1802 upload_state(mgr
, ref
, util_bitcount(aux_usages
) * surf_size
,
1803 SURFACE_STATE_ALIGNMENT
);
1805 ref
->offset
+= iris_bo_offset_from_base_address(iris_resource_bo(ref
->res
));
1812 * Return an ISL surface for use with non-coherent render target reads.
1814 * In a few complex cases, we can't use the SURFACE_STATE for normal render
1815 * target writes. We need to make a separate one for sampling which refers
1816 * to the single slice of the texture being read.
1819 get_rt_read_isl_surf(const struct gen_device_info
*devinfo
,
1820 struct iris_resource
*res
,
1821 enum pipe_texture_target target
,
1822 struct isl_view
*view
,
1823 uint32_t *tile_x_sa
,
1824 uint32_t *tile_y_sa
,
1825 struct isl_surf
*surf
)
1830 const enum isl_dim_layout dim_layout
=
1831 iris_get_isl_dim_layout(devinfo
, res
->surf
.tiling
, target
);
1833 surf
->dim
= target_to_isl_surf_dim(target
);
1835 if (surf
->dim_layout
== dim_layout
)
1838 /* The layout of the specified texture target is not compatible with the
1839 * actual layout of the miptree structure in memory -- You're entering
1840 * dangerous territory, this can only possibly work if you only intended
1841 * to access a single level and slice of the texture, and the hardware
1842 * supports the tile offset feature in order to allow non-tile-aligned
1843 * base offsets, since we'll have to point the hardware to the first
1844 * texel of the level instead of relying on the usual base level/layer
1847 assert(view
->levels
== 1 && view
->array_len
== 1);
1848 assert(*tile_x_sa
== 0 && *tile_y_sa
== 0);
1850 res
->offset
+= iris_resource_get_tile_offsets(res
, view
->base_level
,
1851 view
->base_array_layer
,
1852 tile_x_sa
, tile_y_sa
);
1853 const unsigned l
= view
->base_level
;
1855 surf
->logical_level0_px
.width
= minify(surf
->logical_level0_px
.width
, l
);
1856 surf
->logical_level0_px
.height
= surf
->dim
<= ISL_SURF_DIM_1D
? 1 :
1857 minify(surf
->logical_level0_px
.height
, l
);
1858 surf
->logical_level0_px
.depth
= surf
->dim
<= ISL_SURF_DIM_2D
? 1 :
1859 minify(surf
->logical_level0_px
.depth
, l
);
1861 surf
->logical_level0_px
.array_len
= 1;
1863 surf
->dim_layout
= dim_layout
;
1865 view
->base_level
= 0;
1866 view
->base_array_layer
= 0;
1871 fill_surface_state(struct isl_device
*isl_dev
,
1873 struct iris_resource
*res
,
1874 struct isl_surf
*surf
,
1875 struct isl_view
*view
,
1880 struct isl_surf_fill_state_info f
= {
1883 .mocs
= mocs(res
->bo
),
1884 .address
= res
->bo
->gtt_offset
+ res
->offset
,
1885 .x_offset_sa
= tile_x_sa
,
1886 .y_offset_sa
= tile_y_sa
,
1889 assert(!iris_resource_unfinished_aux_import(res
));
1891 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1892 f
.aux_surf
= &res
->aux
.surf
;
1893 f
.aux_usage
= aux_usage
;
1894 f
.aux_address
= res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
;
1896 struct iris_bo
*clear_bo
= NULL
;
1897 uint64_t clear_offset
= 0;
1899 iris_resource_get_clear_color(res
, &clear_bo
, &clear_offset
);
1901 f
.clear_address
= clear_bo
->gtt_offset
+ clear_offset
;
1902 f
.use_clear_address
= isl_dev
->info
->gen
> 9;
1906 isl_surf_fill_state_s(isl_dev
, map
, &f
);
1910 * The pipe->create_sampler_view() driver hook.
1912 static struct pipe_sampler_view
*
1913 iris_create_sampler_view(struct pipe_context
*ctx
,
1914 struct pipe_resource
*tex
,
1915 const struct pipe_sampler_view
*tmpl
)
1917 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1918 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1919 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1920 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1925 /* initialize base object */
1927 isv
->base
.context
= ctx
;
1928 isv
->base
.texture
= NULL
;
1929 pipe_reference_init(&isv
->base
.reference
, 1);
1930 pipe_resource_reference(&isv
->base
.texture
, tex
);
1932 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1933 struct iris_resource
*zres
, *sres
;
1934 const struct util_format_description
*desc
=
1935 util_format_description(tmpl
->format
);
1937 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1939 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1942 isv
->res
= (struct iris_resource
*) tex
;
1944 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1945 &isv
->surface_state
,
1946 isv
->res
->aux
.sampler_usages
);
1950 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1952 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1953 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1954 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1956 const struct iris_format_info fmt
=
1957 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1959 isv
->clear_color
= isv
->res
->aux
.clear_color
;
1961 isv
->view
= (struct isl_view
) {
1963 .swizzle
= (struct isl_swizzle
) {
1964 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1965 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1966 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1967 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1972 /* Fill out SURFACE_STATE for this view. */
1973 if (tmpl
->target
!= PIPE_BUFFER
) {
1974 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1975 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1976 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1977 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1978 isv
->view
.array_len
=
1979 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1981 if (iris_resource_unfinished_aux_import(isv
->res
))
1982 iris_resource_finish_aux_import(&screen
->base
, isv
->res
);
1984 unsigned aux_modes
= isv
->res
->aux
.sampler_usages
;
1986 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1988 /* If we have a multisampled depth buffer, do not create a sampler
1989 * surface state with HiZ.
1991 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->res
->surf
,
1992 &isv
->view
, aux_usage
, 0, 0);
1994 map
+= SURFACE_STATE_ALIGNMENT
;
1997 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
1998 isv
->view
.format
, isv
->view
.swizzle
,
1999 tmpl
->u
.buf
.offset
, tmpl
->u
.buf
.size
);
2006 iris_sampler_view_destroy(struct pipe_context
*ctx
,
2007 struct pipe_sampler_view
*state
)
2009 struct iris_sampler_view
*isv
= (void *) state
;
2010 pipe_resource_reference(&state
->texture
, NULL
);
2011 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
2016 * The pipe->create_surface() driver hook.
2018 * In Gallium nomenclature, "surfaces" are a view of a resource that
2019 * can be bound as a render target or depth/stencil buffer.
2021 static struct pipe_surface
*
2022 iris_create_surface(struct pipe_context
*ctx
,
2023 struct pipe_resource
*tex
,
2024 const struct pipe_surface
*tmpl
)
2026 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2027 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2028 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2030 isl_surf_usage_flags_t usage
= 0;
2032 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
2033 else if (util_format_is_depth_or_stencil(tmpl
->format
))
2034 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
2036 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
2038 const struct iris_format_info fmt
=
2039 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
2041 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
2042 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
2043 /* Framebuffer validation will reject this invalid case, but it
2044 * hasn't had the opportunity yet. In the meantime, we need to
2045 * avoid hitting ISL asserts about unsupported formats below.
2050 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
2051 struct pipe_surface
*psurf
= &surf
->base
;
2052 struct iris_resource
*res
= (struct iris_resource
*) tex
;
2057 pipe_reference_init(&psurf
->reference
, 1);
2058 pipe_resource_reference(&psurf
->texture
, tex
);
2059 psurf
->context
= ctx
;
2060 psurf
->format
= tmpl
->format
;
2061 psurf
->width
= tex
->width0
;
2062 psurf
->height
= tex
->height0
;
2063 psurf
->texture
= tex
;
2064 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
2065 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
2066 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
2068 uint32_t array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
2070 struct isl_view
*view
= &surf
->view
;
2071 *view
= (struct isl_view
) {
2073 .base_level
= tmpl
->u
.tex
.level
,
2075 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2076 .array_len
= array_len
,
2077 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2082 enum pipe_texture_target target
= (tex
->target
== PIPE_TEXTURE_3D
&&
2083 array_len
== 1) ? PIPE_TEXTURE_2D
:
2084 tex
->target
== PIPE_TEXTURE_1D_ARRAY
?
2085 PIPE_TEXTURE_2D_ARRAY
: tex
->target
;
2087 struct isl_view
*read_view
= &surf
->read_view
;
2088 *read_view
= (struct isl_view
) {
2090 .base_level
= tmpl
->u
.tex
.level
,
2092 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2093 .array_len
= array_len
,
2094 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2095 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
2099 surf
->clear_color
= res
->aux
.clear_color
;
2101 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
2102 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
2103 ISL_SURF_USAGE_STENCIL_BIT
))
2107 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
2108 &surf
->surface_state
,
2109 res
->aux
.possible_usages
);
2110 if (!unlikely(map
)) {
2111 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2116 void *map_read
= alloc_surface_states(ice
->state
.surface_uploader
,
2117 &surf
->surface_state_read
,
2118 res
->aux
.possible_usages
);
2119 if (!unlikely(map_read
)) {
2120 pipe_resource_reference(&surf
->surface_state_read
.res
, NULL
);
2125 if (!isl_format_is_compressed(res
->surf
.format
)) {
2126 if (iris_resource_unfinished_aux_import(res
))
2127 iris_resource_finish_aux_import(&screen
->base
, res
);
2129 /* This is a normal surface. Fill out a SURFACE_STATE for each possible
2130 * auxiliary surface mode and return the pipe_surface.
2132 unsigned aux_modes
= res
->aux
.possible_usages
;
2135 uint32_t offset
= res
->offset
;
2137 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
2138 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2139 view
, aux_usage
, 0, 0);
2140 map
+= SURFACE_STATE_ALIGNMENT
;
2143 struct isl_surf surf
;
2144 uint32_t tile_x_sa
= 0, tile_y_sa
= 0;
2145 get_rt_read_isl_surf(devinfo
, res
, target
, read_view
,
2146 &tile_x_sa
, &tile_y_sa
, &surf
);
2147 fill_surface_state(&screen
->isl_dev
, map_read
, res
, &surf
, read_view
,
2148 aux_usage
, tile_x_sa
, tile_y_sa
);
2149 /* Restore offset because we change offset in case of handling
2150 * non_coherent fb fetch
2152 res
->offset
= offset
;
2153 map_read
+= SURFACE_STATE_ALIGNMENT
;
2160 /* The resource has a compressed format, which is not renderable, but we
2161 * have a renderable view format. We must be attempting to upload blocks
2162 * of compressed data via an uncompressed view.
2164 * In this case, we can assume there are no auxiliary buffers, a single
2165 * miplevel, and that the resource is single-sampled. Gallium may try
2166 * and create an uncompressed view with multiple layers, however.
2168 assert(!isl_format_is_compressed(fmt
.fmt
));
2169 assert(res
->aux
.possible_usages
== 1 << ISL_AUX_USAGE_NONE
);
2170 assert(res
->surf
.samples
== 1);
2171 assert(view
->levels
== 1);
2173 struct isl_surf isl_surf
;
2174 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
2176 if (view
->base_level
> 0) {
2177 /* We can't rely on the hardware's miplevel selection with such
2178 * a substantial lie about the format, so we select a single image
2179 * using the Tile X/Y Offset fields. In this case, we can't handle
2180 * multiple array slices.
2182 * On Broadwell, HALIGN and VALIGN are specified in pixels and are
2183 * hard-coded to align to exactly the block size of the compressed
2184 * texture. This means that, when reinterpreted as a non-compressed
2185 * texture, the tile offsets may be anything and we can't rely on
2188 * Return NULL to force the state tracker to take fallback paths.
2190 if (view
->array_len
> 1 || GEN_GEN
== 8)
2193 const bool is_3d
= res
->surf
.dim
== ISL_SURF_DIM_3D
;
2194 isl_surf_get_image_surf(&screen
->isl_dev
, &res
->surf
,
2196 is_3d
? 0 : view
->base_array_layer
,
2197 is_3d
? view
->base_array_layer
: 0,
2199 &offset_B
, &tile_x_sa
, &tile_y_sa
);
2201 /* We use address and tile offsets to access a single level/layer
2202 * as a subimage, so reset level/layer so it doesn't offset again.
2204 view
->base_array_layer
= 0;
2205 view
->base_level
= 0;
2207 /* Level 0 doesn't require tile offsets, and the hardware can find
2208 * array slices using QPitch even with the format override, so we
2209 * can allow layers in this case. Copy the original ISL surface.
2211 memcpy(&isl_surf
, &res
->surf
, sizeof(isl_surf
));
2214 /* Scale down the image dimensions by the block size. */
2215 const struct isl_format_layout
*fmtl
=
2216 isl_format_get_layout(res
->surf
.format
);
2217 isl_surf
.format
= fmt
.fmt
;
2218 isl_surf
.logical_level0_px
= isl_surf_get_logical_level0_el(&isl_surf
);
2219 isl_surf
.phys_level0_sa
= isl_surf_get_phys_level0_el(&isl_surf
);
2220 tile_x_sa
/= fmtl
->bw
;
2221 tile_y_sa
/= fmtl
->bh
;
2223 psurf
->width
= isl_surf
.logical_level0_px
.width
;
2224 psurf
->height
= isl_surf
.logical_level0_px
.height
;
2226 struct isl_surf_fill_state_info f
= {
2229 .mocs
= mocs(res
->bo
),
2230 .address
= res
->bo
->gtt_offset
+ offset_B
,
2231 .x_offset_sa
= tile_x_sa
,
2232 .y_offset_sa
= tile_y_sa
,
2235 isl_surf_fill_state_s(&screen
->isl_dev
, map
, &f
);
2241 fill_default_image_param(struct brw_image_param
*param
)
2243 memset(param
, 0, sizeof(*param
));
2244 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
2245 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
2246 * detailed explanation of these parameters.
2248 param
->swizzling
[0] = 0xff;
2249 param
->swizzling
[1] = 0xff;
2253 fill_buffer_image_param(struct brw_image_param
*param
,
2254 enum pipe_format pfmt
,
2257 const unsigned cpp
= util_format_get_blocksize(pfmt
);
2259 fill_default_image_param(param
);
2260 param
->size
[0] = size
/ cpp
;
2261 param
->stride
[0] = cpp
;
2264 #define isl_surf_fill_image_param(x, ...)
2265 #define fill_default_image_param(x, ...)
2266 #define fill_buffer_image_param(x, ...)
2270 * The pipe->set_shader_images() driver hook.
2273 iris_set_shader_images(struct pipe_context
*ctx
,
2274 enum pipe_shader_type p_stage
,
2275 unsigned start_slot
, unsigned count
,
2276 const struct pipe_image_view
*p_images
)
2278 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2279 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2280 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2281 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2282 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2284 struct iris_genx_state
*genx
= ice
->state
.genx
;
2285 struct brw_image_param
*image_params
= genx
->shaders
[stage
].image_param
;
2288 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
2290 for (unsigned i
= 0; i
< count
; i
++) {
2291 struct iris_image_view
*iv
= &shs
->image
[start_slot
+ i
];
2293 if (p_images
&& p_images
[i
].resource
) {
2294 const struct pipe_image_view
*img
= &p_images
[i
];
2295 struct iris_resource
*res
= (void *) img
->resource
;
2298 alloc_surface_states(ice
->state
.surface_uploader
,
2299 &iv
->surface_state
, 1 << ISL_AUX_USAGE_NONE
);
2303 util_copy_image_view(&iv
->base
, img
);
2305 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
2307 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
2308 res
->bind_stages
|= 1 << stage
;
2310 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
2311 enum isl_format isl_fmt
=
2312 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
2314 bool untyped_fallback
= false;
2316 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
2317 /* On Gen8, try to use typed surfaces reads (which support a
2318 * limited number of formats), and if not possible, fall back
2321 untyped_fallback
= GEN_GEN
== 8 &&
2322 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
);
2324 if (untyped_fallback
)
2325 isl_fmt
= ISL_FORMAT_RAW
;
2327 isl_fmt
= isl_lower_storage_image_format(devinfo
, isl_fmt
);
2330 if (res
->base
.target
!= PIPE_BUFFER
) {
2331 struct isl_view view
= {
2333 .base_level
= img
->u
.tex
.level
,
2335 .base_array_layer
= img
->u
.tex
.first_layer
,
2336 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
2337 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2341 if (untyped_fallback
) {
2342 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2343 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2346 /* Images don't support compression */
2347 unsigned aux_modes
= 1 << ISL_AUX_USAGE_NONE
;
2349 enum isl_aux_usage usage
= u_bit_scan(&aux_modes
);
2351 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2352 &view
, usage
, 0, 0);
2354 map
+= SURFACE_STATE_ALIGNMENT
;
2358 isl_surf_fill_image_param(&screen
->isl_dev
,
2359 &image_params
[start_slot
+ i
],
2362 util_range_add(&res
->valid_buffer_range
, img
->u
.buf
.offset
,
2363 img
->u
.buf
.offset
+ img
->u
.buf
.size
);
2365 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2366 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2367 img
->u
.buf
.offset
, img
->u
.buf
.size
);
2368 fill_buffer_image_param(&image_params
[start_slot
+ i
],
2369 img
->format
, img
->u
.buf
.size
);
2372 pipe_resource_reference(&iv
->base
.resource
, NULL
);
2373 pipe_resource_reference(&iv
->surface_state
.res
, NULL
);
2374 fill_default_image_param(&image_params
[start_slot
+ i
]);
2378 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2380 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2381 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2383 /* Broadwell also needs brw_image_params re-uploaded */
2385 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2386 shs
->sysvals_need_upload
= true;
2392 * The pipe->set_sampler_views() driver hook.
2395 iris_set_sampler_views(struct pipe_context
*ctx
,
2396 enum pipe_shader_type p_stage
,
2397 unsigned start
, unsigned count
,
2398 struct pipe_sampler_view
**views
)
2400 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2401 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2402 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2404 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
2406 for (unsigned i
= 0; i
< count
; i
++) {
2407 struct pipe_sampler_view
*pview
= views
? views
[i
] : NULL
;
2408 pipe_sampler_view_reference((struct pipe_sampler_view
**)
2409 &shs
->textures
[start
+ i
], pview
);
2410 struct iris_sampler_view
*view
= (void *) pview
;
2412 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
2413 view
->res
->bind_stages
|= 1 << stage
;
2415 shs
->bound_sampler_views
|= 1 << (start
+ i
);
2419 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
2421 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2422 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2426 * The pipe->set_tess_state() driver hook.
2429 iris_set_tess_state(struct pipe_context
*ctx
,
2430 const float default_outer_level
[4],
2431 const float default_inner_level
[2])
2433 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2434 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
2436 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
2437 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
2439 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
2440 shs
->sysvals_need_upload
= true;
2444 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
2446 struct iris_surface
*surf
= (void *) p_surf
;
2447 pipe_resource_reference(&p_surf
->texture
, NULL
);
2448 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2449 pipe_resource_reference(&surf
->surface_state_read
.res
, NULL
);
2454 iris_set_clip_state(struct pipe_context
*ctx
,
2455 const struct pipe_clip_state
*state
)
2457 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2458 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
2459 struct iris_shader_state
*gshs
= &ice
->state
.shaders
[MESA_SHADER_GEOMETRY
];
2460 struct iris_shader_state
*tshs
= &ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
];
2462 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
2464 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
| IRIS_DIRTY_CONSTANTS_GS
|
2465 IRIS_DIRTY_CONSTANTS_TES
;
2466 shs
->sysvals_need_upload
= true;
2467 gshs
->sysvals_need_upload
= true;
2468 tshs
->sysvals_need_upload
= true;
2472 * The pipe->set_polygon_stipple() driver hook.
2475 iris_set_polygon_stipple(struct pipe_context
*ctx
,
2476 const struct pipe_poly_stipple
*state
)
2478 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2479 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
2480 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
2484 * The pipe->set_sample_mask() driver hook.
2487 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2489 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2491 /* We only support 16x MSAA, so we have 16 bits of sample maks.
2492 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
2494 ice
->state
.sample_mask
= sample_mask
& 0xffff;
2495 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
2499 * The pipe->set_scissor_states() driver hook.
2501 * This corresponds to our SCISSOR_RECT state structures. It's an
2502 * exact match, so we just store them, and memcpy them out later.
2505 iris_set_scissor_states(struct pipe_context
*ctx
,
2506 unsigned start_slot
,
2507 unsigned num_scissors
,
2508 const struct pipe_scissor_state
*rects
)
2510 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2512 for (unsigned i
= 0; i
< num_scissors
; i
++) {
2513 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
2514 /* If the scissor was out of bounds and got clamped to 0 width/height
2515 * at the bounds, the subtraction of 1 from maximums could produce a
2516 * negative number and thus not clip anything. Instead, just provide
2517 * a min > max scissor inside the bounds, which produces the expected
2520 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2521 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
2524 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2525 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
2526 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
2531 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
2535 * The pipe->set_stencil_ref() driver hook.
2537 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
2540 iris_set_stencil_ref(struct pipe_context
*ctx
,
2541 const struct pipe_stencil_ref
*state
)
2543 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2544 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2546 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2548 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2552 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2554 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2558 * The pipe->set_viewport_states() driver hook.
2560 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2561 * the guardband yet, as we need the framebuffer dimensions, but we can
2562 * at least fill out the rest.
2565 iris_set_viewport_states(struct pipe_context
*ctx
,
2566 unsigned start_slot
,
2568 const struct pipe_viewport_state
*states
)
2570 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2572 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2574 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2576 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2577 !ice
->state
.cso_rast
->depth_clip_far
))
2578 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2582 * The pipe->set_framebuffer_state() driver hook.
2584 * Sets the current draw FBO, including color render targets, depth,
2585 * and stencil buffers.
2588 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2589 const struct pipe_framebuffer_state
*state
)
2591 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2592 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2593 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2594 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2595 struct iris_resource
*zres
;
2596 struct iris_resource
*stencil_res
;
2598 unsigned samples
= util_framebuffer_get_num_samples(state
);
2599 unsigned layers
= util_framebuffer_get_num_layers(state
);
2601 if (cso
->samples
!= samples
) {
2602 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2604 /* We need to toggle 3DSTATE_PS::32 Pixel Dispatch Enable */
2605 if (GEN_GEN
>= 9 && (cso
->samples
== 16 || samples
== 16))
2606 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
2609 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2610 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2613 if ((cso
->layers
== 0) != (layers
== 0)) {
2614 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2617 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2618 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2621 if (cso
->zsbuf
|| state
->zsbuf
) {
2622 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2625 util_copy_framebuffer_state(cso
, state
);
2626 cso
->samples
= samples
;
2627 cso
->layers
= layers
;
2629 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2631 struct isl_view view
= {
2634 .base_array_layer
= 0,
2636 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2639 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
2642 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2645 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2646 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2648 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2651 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2653 info
.depth_surf
= &zres
->surf
;
2654 info
.depth_address
= zres
->bo
->gtt_offset
+ zres
->offset
;
2655 info
.mocs
= mocs(zres
->bo
);
2657 view
.format
= zres
->surf
.format
;
2659 if (iris_resource_level_has_hiz(zres
, view
.base_level
)) {
2660 info
.hiz_usage
= ISL_AUX_USAGE_HIZ
;
2661 info
.hiz_surf
= &zres
->aux
.surf
;
2662 info
.hiz_address
= zres
->aux
.bo
->gtt_offset
+ zres
->aux
.offset
;
2667 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2668 info
.stencil_surf
= &stencil_res
->surf
;
2669 info
.stencil_address
= stencil_res
->bo
->gtt_offset
+ stencil_res
->offset
;
2671 view
.format
= stencil_res
->surf
.format
;
2672 info
.mocs
= mocs(stencil_res
->bo
);
2677 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2679 /* Make a null surface for unbound buffers */
2680 void *null_surf_map
=
2681 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2682 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2683 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2684 isl_extent3d(MAX2(cso
->width
, 1),
2685 MAX2(cso
->height
, 1),
2686 cso
->layers
? cso
->layers
: 1));
2687 ice
->state
.null_fb
.offset
+=
2688 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2690 /* Render target change */
2691 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2693 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2695 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2698 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2699 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2701 /* The PIPE_CONTROL command description says:
2703 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2704 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2705 * Target Cache Flush by enabling this bit. When render target flush
2706 * is set due to new association of BTI, PS Scoreboard Stall bit must
2707 * be set in this packet."
2709 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2710 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2711 "workaround: RT BTI change [draw]",
2712 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2713 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2718 * The pipe->set_constant_buffer() driver hook.
2720 * This uploads any constant data in user buffers, and references
2721 * any UBO resources containing constant data.
2724 iris_set_constant_buffer(struct pipe_context
*ctx
,
2725 enum pipe_shader_type p_stage
, unsigned index
,
2726 const struct pipe_constant_buffer
*input
)
2728 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2729 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2730 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2731 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[index
];
2733 /* TODO: Only do this if the buffer changes? */
2734 pipe_resource_reference(&shs
->constbuf_surf_state
[index
].res
, NULL
);
2736 if (input
&& input
->buffer_size
&& (input
->buffer
|| input
->user_buffer
)) {
2737 shs
->bound_cbufs
|= 1u << index
;
2739 if (input
->user_buffer
) {
2741 pipe_resource_reference(&cbuf
->buffer
, NULL
);
2742 u_upload_alloc(ice
->ctx
.const_uploader
, 0, input
->buffer_size
, 64,
2743 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
2745 if (!cbuf
->buffer
) {
2746 /* Allocation was unsuccessful - just unbind */
2747 iris_set_constant_buffer(ctx
, p_stage
, index
, NULL
);
2752 memcpy(map
, input
->user_buffer
, input
->buffer_size
);
2753 } else if (input
->buffer
) {
2754 pipe_resource_reference(&cbuf
->buffer
, input
->buffer
);
2756 cbuf
->buffer_offset
= input
->buffer_offset
;
2760 MIN2(input
->buffer_size
,
2761 iris_resource_bo(cbuf
->buffer
)->size
- cbuf
->buffer_offset
);
2763 struct iris_resource
*res
= (void *) cbuf
->buffer
;
2764 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2765 res
->bind_stages
|= 1 << stage
;
2767 shs
->bound_cbufs
&= ~(1u << index
);
2768 pipe_resource_reference(&cbuf
->buffer
, NULL
);
2771 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2775 upload_sysvals(struct iris_context
*ice
,
2776 gl_shader_stage stage
)
2778 UNUSED
struct iris_genx_state
*genx
= ice
->state
.genx
;
2779 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2781 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2782 if (!shader
|| shader
->num_system_values
== 0)
2785 assert(shader
->num_cbufs
> 0);
2787 unsigned sysval_cbuf_index
= shader
->num_cbufs
- 1;
2788 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[sysval_cbuf_index
];
2789 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t);
2790 uint32_t *map
= NULL
;
2792 assert(sysval_cbuf_index
< PIPE_MAX_CONSTANT_BUFFERS
);
2793 u_upload_alloc(ice
->ctx
.const_uploader
, 0, upload_size
, 64,
2794 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
2796 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2797 uint32_t sysval
= shader
->system_values
[i
];
2800 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
2802 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
2803 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
2804 struct brw_image_param
*param
=
2805 &genx
->shaders
[stage
].image_param
[img
];
2807 assert(offset
< sizeof(struct brw_image_param
));
2808 value
= ((uint32_t *) param
)[offset
];
2810 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
2812 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2813 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2814 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2815 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2816 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
2817 if (stage
== MESA_SHADER_TESS_CTRL
) {
2818 value
= ice
->state
.vertices_per_patch
;
2820 assert(stage
== MESA_SHADER_TESS_EVAL
);
2821 const struct shader_info
*tcs_info
=
2822 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
2824 value
= tcs_info
->tess
.tcs_vertices_out
;
2826 value
= ice
->state
.vertices_per_patch
;
2828 } else if (sysval
>= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
&&
2829 sysval
<= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
) {
2830 unsigned i
= sysval
- BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
2831 value
= fui(ice
->state
.default_outer_level
[i
]);
2832 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
) {
2833 value
= fui(ice
->state
.default_inner_level
[0]);
2834 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
) {
2835 value
= fui(ice
->state
.default_inner_level
[1]);
2837 assert(!"unhandled system value");
2843 cbuf
->buffer_size
= upload_size
;
2844 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
2845 &shs
->constbuf_surf_state
[sysval_cbuf_index
], false);
2847 shs
->sysvals_need_upload
= false;
2851 * The pipe->set_shader_buffers() driver hook.
2853 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2854 * SURFACE_STATE here, as the buffer offset may change each time.
2857 iris_set_shader_buffers(struct pipe_context
*ctx
,
2858 enum pipe_shader_type p_stage
,
2859 unsigned start_slot
, unsigned count
,
2860 const struct pipe_shader_buffer
*buffers
,
2861 unsigned writable_bitmask
)
2863 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2864 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2865 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2867 unsigned modified_bits
= u_bit_consecutive(start_slot
, count
);
2869 shs
->bound_ssbos
&= ~modified_bits
;
2870 shs
->writable_ssbos
&= ~modified_bits
;
2871 shs
->writable_ssbos
|= writable_bitmask
<< start_slot
;
2873 for (unsigned i
= 0; i
< count
; i
++) {
2874 if (buffers
&& buffers
[i
].buffer
) {
2875 struct iris_resource
*res
= (void *) buffers
[i
].buffer
;
2876 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[start_slot
+ i
];
2877 struct iris_state_ref
*surf_state
=
2878 &shs
->ssbo_surf_state
[start_slot
+ i
];
2879 pipe_resource_reference(&ssbo
->buffer
, &res
->base
);
2880 ssbo
->buffer_offset
= buffers
[i
].buffer_offset
;
2882 MIN2(buffers
[i
].buffer_size
, res
->bo
->size
- ssbo
->buffer_offset
);
2884 shs
->bound_ssbos
|= 1 << (start_slot
+ i
);
2886 iris_upload_ubo_ssbo_surf_state(ice
, ssbo
, surf_state
, true);
2888 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2889 res
->bind_stages
|= 1 << stage
;
2891 util_range_add(&res
->valid_buffer_range
, ssbo
->buffer_offset
,
2892 ssbo
->buffer_offset
+ ssbo
->buffer_size
);
2894 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
].buffer
, NULL
);
2895 pipe_resource_reference(&shs
->ssbo_surf_state
[start_slot
+ i
].res
,
2900 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2904 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2910 * The pipe->set_vertex_buffers() driver hook.
2912 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2915 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2916 unsigned start_slot
, unsigned count
,
2917 const struct pipe_vertex_buffer
*buffers
)
2919 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2920 struct iris_genx_state
*genx
= ice
->state
.genx
;
2922 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
2924 for (unsigned i
= 0; i
< count
; i
++) {
2925 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
2926 struct iris_vertex_buffer_state
*state
=
2927 &genx
->vertex_buffers
[start_slot
+ i
];
2930 pipe_resource_reference(&state
->resource
, NULL
);
2934 /* We may see user buffers that are NULL bindings. */
2935 assert(!(buffer
->is_user_buffer
&& buffer
->buffer
.user
!= NULL
));
2937 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
2938 struct iris_resource
*res
= (void *) state
->resource
;
2941 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
2942 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2945 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
2946 vb
.VertexBufferIndex
= start_slot
+ i
;
2947 vb
.AddressModifyEnable
= true;
2948 vb
.BufferPitch
= buffer
->stride
;
2950 vb
.BufferSize
= res
->bo
->size
- (int) buffer
->buffer_offset
;
2951 vb
.BufferStartingAddress
=
2952 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
2953 vb
.MOCS
= mocs(res
->bo
);
2955 vb
.NullVertexBuffer
= true;
2960 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2964 * Gallium CSO for vertex elements.
2966 struct iris_vertex_element_state
{
2967 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2968 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2969 uint32_t edgeflag_ve
[GENX(VERTEX_ELEMENT_STATE_length
)];
2970 uint32_t edgeflag_vfi
[GENX(3DSTATE_VF_INSTANCING_length
)];
2975 * The pipe->create_vertex_elements() driver hook.
2977 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2978 * and 3DSTATE_VF_INSTANCING commands. The vertex_elements and vf_instancing
2979 * arrays are ready to be emitted at draw time if no EdgeFlag or SGVs are
2980 * needed. In these cases we will need information available at draw time.
2981 * We setup edgeflag_ve and edgeflag_vfi as alternatives last
2982 * 3DSTATE_VERTEX_ELEMENT and 3DSTATE_VF_INSTANCING that can be used at
2983 * draw time if we detect that EdgeFlag is needed by the Vertex Shader.
2986 iris_create_vertex_elements(struct pipe_context
*ctx
,
2988 const struct pipe_vertex_element
*state
)
2990 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2991 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2992 struct iris_vertex_element_state
*cso
=
2993 malloc(sizeof(struct iris_vertex_element_state
));
2997 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2999 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
3002 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
3003 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
3006 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
3008 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
3009 ve
.Component0Control
= VFCOMP_STORE_0
;
3010 ve
.Component1Control
= VFCOMP_STORE_0
;
3011 ve
.Component2Control
= VFCOMP_STORE_0
;
3012 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
3015 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
3019 for (int i
= 0; i
< count
; i
++) {
3020 const struct iris_format_info fmt
=
3021 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
3022 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
3023 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
3025 switch (isl_format_get_num_channels(fmt
.fmt
)) {
3026 case 0: comp
[0] = VFCOMP_STORE_0
; /* fallthrough */
3027 case 1: comp
[1] = VFCOMP_STORE_0
; /* fallthrough */
3028 case 2: comp
[2] = VFCOMP_STORE_0
; /* fallthrough */
3030 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
3031 : VFCOMP_STORE_1_FP
;
3034 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
3035 ve
.EdgeFlagEnable
= false;
3036 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
3038 ve
.SourceElementOffset
= state
[i
].src_offset
;
3039 ve
.SourceElementFormat
= fmt
.fmt
;
3040 ve
.Component0Control
= comp
[0];
3041 ve
.Component1Control
= comp
[1];
3042 ve
.Component2Control
= comp
[2];
3043 ve
.Component3Control
= comp
[3];
3046 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
3047 vi
.VertexElementIndex
= i
;
3048 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
3049 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
3052 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
3053 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
3056 /* An alternative version of the last VE and VFI is stored so it
3057 * can be used at draw time in case Vertex Shader uses EdgeFlag
3060 const unsigned edgeflag_index
= count
- 1;
3061 const struct iris_format_info fmt
=
3062 iris_format_for_usage(devinfo
, state
[edgeflag_index
].src_format
, 0);
3063 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), cso
->edgeflag_ve
, ve
) {
3064 ve
.EdgeFlagEnable
= true ;
3065 ve
.VertexBufferIndex
= state
[edgeflag_index
].vertex_buffer_index
;
3067 ve
.SourceElementOffset
= state
[edgeflag_index
].src_offset
;
3068 ve
.SourceElementFormat
= fmt
.fmt
;
3069 ve
.Component0Control
= VFCOMP_STORE_SRC
;
3070 ve
.Component1Control
= VFCOMP_STORE_0
;
3071 ve
.Component2Control
= VFCOMP_STORE_0
;
3072 ve
.Component3Control
= VFCOMP_STORE_0
;
3074 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->edgeflag_vfi
, vi
) {
3075 /* The vi.VertexElementIndex of the EdgeFlag Vertex Element is filled
3076 * at draw time, as it should change if SGVs are emitted.
3078 vi
.InstancingEnable
= state
[edgeflag_index
].instance_divisor
> 0;
3079 vi
.InstanceDataStepRate
= state
[edgeflag_index
].instance_divisor
;
3087 * The pipe->bind_vertex_elements_state() driver hook.
3090 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
3092 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3093 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
3094 struct iris_vertex_element_state
*new_cso
= state
;
3096 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
3097 * we need to re-emit it to ensure we're overriding the right one.
3099 if (new_cso
&& cso_changed(count
))
3100 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
3102 ice
->state
.cso_vertex_elements
= state
;
3103 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
3107 * The pipe->create_stream_output_target() driver hook.
3109 * "Target" here refers to a destination buffer. We translate this into
3110 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
3111 * know which buffer this represents, or whether we ought to zero the
3112 * write-offsets, or append. Those are handled in the set() hook.
3114 static struct pipe_stream_output_target
*
3115 iris_create_stream_output_target(struct pipe_context
*ctx
,
3116 struct pipe_resource
*p_res
,
3117 unsigned buffer_offset
,
3118 unsigned buffer_size
)
3120 struct iris_resource
*res
= (void *) p_res
;
3121 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
3125 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
3127 pipe_reference_init(&cso
->base
.reference
, 1);
3128 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
3129 cso
->base
.buffer_offset
= buffer_offset
;
3130 cso
->base
.buffer_size
= buffer_size
;
3131 cso
->base
.context
= ctx
;
3133 util_range_add(&res
->valid_buffer_range
, buffer_offset
,
3134 buffer_offset
+ buffer_size
);
3136 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
3142 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
3143 struct pipe_stream_output_target
*state
)
3145 struct iris_stream_output_target
*cso
= (void *) state
;
3147 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
3148 pipe_resource_reference(&cso
->offset
.res
, NULL
);
3154 * The pipe->set_stream_output_targets() driver hook.
3156 * At this point, we know which targets are bound to a particular index,
3157 * and also whether we want to append or start over. We can finish the
3158 * 3DSTATE_SO_BUFFER packets we started earlier.
3161 iris_set_stream_output_targets(struct pipe_context
*ctx
,
3162 unsigned num_targets
,
3163 struct pipe_stream_output_target
**targets
,
3164 const unsigned *offsets
)
3166 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3167 struct iris_genx_state
*genx
= ice
->state
.genx
;
3168 uint32_t *so_buffers
= genx
->so_buffers
;
3170 const bool active
= num_targets
> 0;
3171 if (ice
->state
.streamout_active
!= active
) {
3172 ice
->state
.streamout_active
= active
;
3173 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
3175 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
3176 * it's a non-pipelined command. If we're switching streamout on, we
3177 * may have missed emitting it earlier, so do so now. (We're already
3178 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
3181 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
3184 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3185 struct iris_stream_output_target
*tgt
=
3186 (void *) ice
->state
.so_target
[i
];
3188 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3190 flush
|= iris_flush_bits_for_history(res
);
3191 iris_dirty_for_history(ice
, res
);
3194 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
3195 "make streamout results visible", flush
);
3199 for (int i
= 0; i
< 4; i
++) {
3200 pipe_so_target_reference(&ice
->state
.so_target
[i
],
3201 i
< num_targets
? targets
[i
] : NULL
);
3204 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
3208 for (unsigned i
= 0; i
< 4; i
++,
3209 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
3211 struct iris_stream_output_target
*tgt
= (void *) ice
->state
.so_target
[i
];
3212 unsigned offset
= offsets
[i
];
3215 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
3216 sob
.SOBufferIndex
= i
;
3220 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3222 /* Note that offsets[i] will either be 0, causing us to zero
3223 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
3224 * "continue appending at the existing offset."
3226 assert(offset
== 0 || offset
== 0xFFFFFFFF);
3228 /* We might be called by Begin (offset = 0), Pause, then Resume
3229 * (offset = 0xFFFFFFFF) before ever drawing (where these commands
3230 * will actually be sent to the GPU). In this case, we don't want
3231 * to append - we still want to do our initial zeroing.
3236 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
3237 sob
.SurfaceBaseAddress
=
3238 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
3239 sob
.SOBufferEnable
= true;
3240 sob
.StreamOffsetWriteEnable
= true;
3241 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3242 sob
.MOCS
= mocs(res
->bo
);
3244 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
3246 sob
.SOBufferIndex
= i
;
3247 sob
.StreamOffset
= offset
;
3248 sob
.StreamOutputBufferOffsetAddress
=
3249 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
3250 tgt
->offset
.offset
);
3254 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
3258 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
3259 * 3DSTATE_STREAMOUT packets.
3261 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
3262 * hardware to record. We can create it entirely based on the shader, with
3263 * no dynamic state dependencies.
3265 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
3266 * state-based settings. We capture the shader-related ones here, and merge
3267 * the rest in at draw time.
3270 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
3271 const struct brw_vue_map
*vue_map
)
3273 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3274 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3275 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3276 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3278 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3280 memset(so_decl
, 0, sizeof(so_decl
));
3282 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3283 * command feels strange -- each dword pair contains a SO_DECL per stream.
3285 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
3286 const struct pipe_stream_output
*output
= &info
->output
[i
];
3287 const int buffer
= output
->output_buffer
;
3288 const int varying
= output
->register_index
;
3289 const unsigned stream_id
= output
->stream
;
3290 assert(stream_id
< MAX_VERTEX_STREAMS
);
3292 buffer_mask
[stream_id
] |= 1 << buffer
;
3294 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3296 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3297 * array. Instead, it simply increments DstOffset for the following
3298 * input by the number of components that should be skipped.
3300 * Our hardware is unusual in that it requires us to program SO_DECLs
3301 * for fake "hole" components, rather than simply taking the offset
3302 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3303 * program as many size = 4 holes as we can, then a final hole to
3304 * accommodate the final 1, 2, or 3 remaining.
3306 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
3308 while (skip_components
> 0) {
3309 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3311 .OutputBufferSlot
= output
->output_buffer
,
3312 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3314 skip_components
-= 4;
3317 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
3319 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3320 .OutputBufferSlot
= output
->output_buffer
,
3321 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3323 ((1 << output
->num_components
) - 1) << output
->start_component
,
3326 if (decls
[stream_id
] > max_decls
)
3327 max_decls
= decls
[stream_id
];
3330 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
3331 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
3332 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
3334 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
3335 int urb_entry_read_offset
= 0;
3336 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3337 urb_entry_read_offset
;
3339 /* We always read the whole vertex. This could be reduced at some
3340 * point by reading less and offsetting the register index in the
3343 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3344 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3345 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3346 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3347 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3348 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3349 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3350 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3352 /* Set buffer pitches; 0 means unbound. */
3353 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
3354 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
3355 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
3356 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
3359 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
3360 list
.DWordLength
= 3 + 2 * max_decls
- 2;
3361 list
.StreamtoBufferSelects0
= buffer_mask
[0];
3362 list
.StreamtoBufferSelects1
= buffer_mask
[1];
3363 list
.StreamtoBufferSelects2
= buffer_mask
[2];
3364 list
.StreamtoBufferSelects3
= buffer_mask
[3];
3365 list
.NumEntries0
= decls
[0];
3366 list
.NumEntries1
= decls
[1];
3367 list
.NumEntries2
= decls
[2];
3368 list
.NumEntries3
= decls
[3];
3371 for (int i
= 0; i
< max_decls
; i
++) {
3372 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
3373 entry
.Stream0Decl
= so_decl
[0][i
];
3374 entry
.Stream1Decl
= so_decl
[1][i
];
3375 entry
.Stream2Decl
= so_decl
[2][i
];
3376 entry
.Stream3Decl
= so_decl
[3][i
];
3384 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
3385 const struct brw_vue_map
*last_vue_map
,
3386 bool two_sided_color
,
3387 unsigned *out_offset
,
3388 unsigned *out_length
)
3390 /* The compiler computes the first URB slot without considering COL/BFC
3391 * swizzling (because it doesn't know whether it's enabled), so we need
3392 * to do that here too. This may result in a smaller offset, which
3395 const unsigned first_slot
=
3396 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
3398 /* This becomes the URB read offset (counted in pairs of slots). */
3399 assert(first_slot
% 2 == 0);
3400 *out_offset
= first_slot
/ 2;
3402 /* We need to adjust the inputs read to account for front/back color
3403 * swizzling, as it can make the URB length longer.
3405 for (int c
= 0; c
<= 1; c
++) {
3406 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
3407 /* If two sided color is enabled, the fragment shader's gl_Color
3408 * (COL0) input comes from either the gl_FrontColor (COL0) or
3409 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
3411 if (two_sided_color
)
3412 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3414 /* If front color isn't written, we opt to give them back color
3415 * instead of an undefined value. Switch from COL to BFC.
3417 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
3418 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
3419 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3424 /* Compute the minimum URB Read Length necessary for the FS inputs.
3426 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
3427 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
3429 * "This field should be set to the minimum length required to read the
3430 * maximum source attribute. The maximum source attribute is indicated
3431 * by the maximum value of the enabled Attribute # Source Attribute if
3432 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
3433 * enable is not set.
3434 * read_length = ceiling((max_source_attr + 1) / 2)
3436 * [errata] Corruption/Hang possible if length programmed larger than
3439 * Similar text exists for Ivy Bridge.
3441 * We find the last URB slot that's actually read by the FS.
3443 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
3444 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
3445 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
3448 /* The URB read length is the difference of the two, counted in pairs. */
3449 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
3453 iris_emit_sbe_swiz(struct iris_batch
*batch
,
3454 const struct iris_context
*ice
,
3455 unsigned urb_read_offset
,
3456 unsigned sprite_coord_enables
)
3458 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
3459 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3460 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3461 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
3462 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3464 /* XXX: this should be generated when putting programs in place */
3466 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
3467 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
3468 if (input_index
< 0 || input_index
>= 16)
3471 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
3472 &attr_overrides
[input_index
];
3473 int slot
= vue_map
->varying_to_slot
[fs_attr
];
3475 /* Viewport and Layer are stored in the VUE header. We need to override
3476 * them to zero if earlier stages didn't write them, as GL requires that
3477 * they read back as zero when not explicitly set.
3480 case VARYING_SLOT_VIEWPORT
:
3481 case VARYING_SLOT_LAYER
:
3482 attr
->ComponentOverrideX
= true;
3483 attr
->ComponentOverrideW
= true;
3484 attr
->ConstantSource
= CONST_0000
;
3486 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
3487 attr
->ComponentOverrideY
= true;
3488 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
3489 attr
->ComponentOverrideZ
= true;
3492 case VARYING_SLOT_PRIMITIVE_ID
:
3493 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
3495 attr
->ComponentOverrideX
= true;
3496 attr
->ComponentOverrideY
= true;
3497 attr
->ComponentOverrideZ
= true;
3498 attr
->ComponentOverrideW
= true;
3499 attr
->ConstantSource
= PRIM_ID
;
3507 if (sprite_coord_enables
& (1 << input_index
))
3510 /* If there was only a back color written but not front, use back
3511 * as the color instead of undefined.
3513 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
3514 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
3515 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
3516 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
3518 /* Not written by the previous stage - undefined. */
3520 attr
->ComponentOverrideX
= true;
3521 attr
->ComponentOverrideY
= true;
3522 attr
->ComponentOverrideZ
= true;
3523 attr
->ComponentOverrideW
= true;
3524 attr
->ConstantSource
= CONST_0001_FLOAT
;
3528 /* Compute the location of the attribute relative to the read offset,
3529 * which is counted in 256-bit increments (two 128-bit VUE slots).
3531 const int source_attr
= slot
- 2 * urb_read_offset
;
3532 assert(source_attr
>= 0 && source_attr
<= 32);
3533 attr
->SourceAttribute
= source_attr
;
3535 /* If we are doing two-sided color, and the VUE slot following this one
3536 * represents a back-facing color, then we need to instruct the SF unit
3537 * to do back-facing swizzling.
3539 if (cso_rast
->light_twoside
&&
3540 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3541 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3542 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3543 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3544 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3547 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3548 for (int i
= 0; i
< 16; i
++)
3549 sbes
.Attribute
[i
] = attr_overrides
[i
];
3554 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3555 const struct iris_rasterizer_state
*cso
)
3557 unsigned overrides
= 0;
3559 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
3560 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
3562 for (int i
= 0; i
< 8; i
++) {
3563 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
3564 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
3565 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
3572 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
3574 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3575 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3576 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3577 const struct shader_info
*fs_info
=
3578 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
3580 unsigned urb_read_offset
, urb_read_length
;
3581 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
3582 ice
->shaders
.last_vue_map
,
3583 cso_rast
->light_twoside
,
3584 &urb_read_offset
, &urb_read_length
);
3586 unsigned sprite_coord_overrides
=
3587 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3589 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
3590 sbe
.AttributeSwizzleEnable
= true;
3591 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3592 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3593 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3594 sbe
.VertexURBEntryReadLength
= urb_read_length
;
3595 sbe
.ForceVertexURBEntryReadOffset
= true;
3596 sbe
.ForceVertexURBEntryReadLength
= true;
3597 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3598 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
3600 for (int i
= 0; i
< 32; i
++) {
3601 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3606 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
3609 /* ------------------------------------------------------------------- */
3612 * Populate VS program key fields based on the current state.
3615 iris_populate_vs_key(const struct iris_context
*ice
,
3616 const struct shader_info
*info
,
3617 gl_shader_stage last_stage
,
3618 struct brw_vs_prog_key
*key
)
3620 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3622 if (info
->clip_distance_array_size
== 0 &&
3623 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
3624 last_stage
== MESA_SHADER_VERTEX
)
3625 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3629 * Populate TCS program key fields based on the current state.
3632 iris_populate_tcs_key(const struct iris_context
*ice
,
3633 struct brw_tcs_prog_key
*key
)
3638 * Populate TES program key fields based on the current state.
3641 iris_populate_tes_key(const struct iris_context
*ice
,
3642 const struct shader_info
*info
,
3643 gl_shader_stage last_stage
,
3644 struct brw_tes_prog_key
*key
)
3646 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3648 if (info
->clip_distance_array_size
== 0 &&
3649 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
3650 last_stage
== MESA_SHADER_TESS_EVAL
)
3651 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3655 * Populate GS program key fields based on the current state.
3658 iris_populate_gs_key(const struct iris_context
*ice
,
3659 const struct shader_info
*info
,
3660 gl_shader_stage last_stage
,
3661 struct brw_gs_prog_key
*key
)
3663 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3665 if (info
->clip_distance_array_size
== 0 &&
3666 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
3667 last_stage
== MESA_SHADER_GEOMETRY
)
3668 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3672 * Populate FS program key fields based on the current state.
3675 iris_populate_fs_key(const struct iris_context
*ice
,
3676 const struct shader_info
*info
,
3677 struct brw_wm_prog_key
*key
)
3679 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3680 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3681 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3682 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3683 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3685 key
->nr_color_regions
= fb
->nr_cbufs
;
3687 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3689 key
->alpha_to_coverage
= blend
->alpha_to_coverage
;
3691 key
->alpha_test_replicate_alpha
= fb
->nr_cbufs
> 1 && zsa
->alpha
.enabled
;
3693 key
->flat_shade
= rast
->flatshade
&&
3694 (info
->inputs_read
& (VARYING_BIT_COL0
| VARYING_BIT_COL1
));
3696 key
->persample_interp
= rast
->force_persample_interp
;
3697 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3699 key
->coherent_fb_fetch
= GEN_GEN
>= 9;
3701 key
->force_dual_color_blend
=
3702 screen
->driconf
.dual_color_blend_by_location
&&
3703 (blend
->blend_enables
& 1) && blend
->dual_color_blending
;
3705 /* TODO: Respect glHint for key->high_quality_derivatives */
3709 iris_populate_cs_key(const struct iris_context
*ice
,
3710 struct brw_cs_prog_key
*key
)
3715 KSP(const struct iris_compiled_shader
*shader
)
3717 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3718 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3721 /* Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3722 * prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3723 * this WA on C0 stepping.
3725 * TODO: Fill out SamplerCount for prefetching?
3728 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3729 pkt.KernelStartPointer = KSP(shader); \
3730 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3731 shader->bt.size_bytes / 4; \
3732 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3734 pkt.DispatchGRFStartRegisterForURBData = \
3735 prog_data->dispatch_grf_start_reg; \
3736 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3737 pkt.prefix##URBEntryReadOffset = 0; \
3739 pkt.StatisticsEnable = true; \
3740 pkt.Enable = true; \
3742 if (prog_data->total_scratch) { \
3743 struct iris_bo *bo = \
3744 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3745 uint32_t scratch_addr = bo->gtt_offset; \
3746 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3747 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3751 * Encode most of 3DSTATE_VS based on the compiled shader.
3754 iris_store_vs_state(struct iris_context
*ice
,
3755 const struct gen_device_info
*devinfo
,
3756 struct iris_compiled_shader
*shader
)
3758 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3759 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3761 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3762 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3763 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3764 vs
.SIMD8DispatchEnable
= true;
3765 vs
.UserClipDistanceCullTestEnableBitmask
=
3766 vue_prog_data
->cull_distance_mask
;
3771 * Encode most of 3DSTATE_HS based on the compiled shader.
3774 iris_store_tcs_state(struct iris_context
*ice
,
3775 const struct gen_device_info
*devinfo
,
3776 struct iris_compiled_shader
*shader
)
3778 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3779 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3780 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3782 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3783 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3785 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3786 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3787 hs
.IncludeVertexHandles
= true;
3790 hs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
3791 hs
.IncludePrimitiveID
= tcs_prog_data
->include_primitive_id
;
3797 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3800 iris_store_tes_state(struct iris_context
*ice
,
3801 const struct gen_device_info
*devinfo
,
3802 struct iris_compiled_shader
*shader
)
3804 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3805 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3806 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3808 uint32_t *te_state
= (void *) shader
->derived_data
;
3809 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3811 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3812 te
.Partitioning
= tes_prog_data
->partitioning
;
3813 te
.OutputTopology
= tes_prog_data
->output_topology
;
3814 te
.TEDomain
= tes_prog_data
->domain
;
3816 te
.MaximumTessellationFactorOdd
= 63.0;
3817 te
.MaximumTessellationFactorNotOdd
= 64.0;
3820 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3821 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3823 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3824 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3825 ds
.ComputeWCoordinateEnable
=
3826 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3828 ds
.UserClipDistanceCullTestEnableBitmask
=
3829 vue_prog_data
->cull_distance_mask
;
3835 * Encode most of 3DSTATE_GS based on the compiled shader.
3838 iris_store_gs_state(struct iris_context
*ice
,
3839 const struct gen_device_info
*devinfo
,
3840 struct iris_compiled_shader
*shader
)
3842 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3843 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3844 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3846 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3847 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3849 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3850 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3851 gs
.ControlDataHeaderSize
=
3852 gs_prog_data
->control_data_header_size_hwords
;
3853 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3854 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3855 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3856 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3857 gs
.ReorderMode
= TRAILING
;
3858 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3859 gs
.MaximumNumberofThreads
=
3860 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3861 : (devinfo
->max_gs_threads
- 1);
3863 if (gs_prog_data
->static_vertex_count
!= -1) {
3864 gs
.StaticOutput
= true;
3865 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3867 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3869 gs
.UserClipDistanceCullTestEnableBitmask
=
3870 vue_prog_data
->cull_distance_mask
;
3872 const int urb_entry_write_offset
= 1;
3873 const uint32_t urb_entry_output_length
=
3874 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3875 urb_entry_write_offset
;
3877 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3878 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3883 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3886 iris_store_fs_state(struct iris_context
*ice
,
3887 const struct gen_device_info
*devinfo
,
3888 struct iris_compiled_shader
*shader
)
3890 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3891 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3893 uint32_t *ps_state
= (void *) shader
->derived_data
;
3894 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3896 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3897 ps
.VectorMaskEnable
= true;
3898 // XXX: WABTPPrefetchDisable, see above, drop at C0
3899 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3900 shader
->bt
.size_bytes
/ 4;
3901 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3902 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3904 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
3906 /* From the documentation for this packet:
3907 * "If the PS kernel does not need the Position XY Offsets to
3908 * compute a Position Value, then this field should be programmed
3909 * to POSOFFSET_NONE."
3911 * "SW Recommendation: If the PS kernel needs the Position Offsets
3912 * to compute a Position XY value, this field should match Position
3913 * ZW Interpolation Mode to ensure a consistent position.xyzw
3916 * We only require XY sample offsets. So, this recommendation doesn't
3917 * look useful at the moment. We might need this in future.
3919 ps
.PositionXYOffsetSelect
=
3920 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3922 if (prog_data
->total_scratch
) {
3923 struct iris_bo
*bo
=
3924 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3925 MESA_SHADER_FRAGMENT
);
3926 uint32_t scratch_addr
= bo
->gtt_offset
;
3927 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3928 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3932 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3933 psx
.PixelShaderValid
= true;
3934 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3935 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
3936 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3937 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3938 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3939 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3940 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3943 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3944 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3950 * Compute the size of the derived data (shader command packets).
3952 * This must match the data written by the iris_store_xs_state() functions.
3955 iris_store_cs_state(struct iris_context
*ice
,
3956 const struct gen_device_info
*devinfo
,
3957 struct iris_compiled_shader
*shader
)
3959 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3960 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3961 void *map
= shader
->derived_data
;
3963 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3964 desc
.KernelStartPointer
= KSP(shader
);
3965 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3966 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3967 desc
.SharedLocalMemorySize
=
3968 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3969 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3970 desc
.CrossThreadConstantDataReadLength
=
3971 cs_prog_data
->push
.cross_thread
.regs
;
3976 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3978 assert(cache_id
<= IRIS_CACHE_BLORP
);
3980 static const unsigned dwords
[] = {
3981 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3982 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3983 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3984 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3986 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3987 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3988 [IRIS_CACHE_BLORP
] = 0,
3991 return sizeof(uint32_t) * dwords
[cache_id
];
3995 * Create any state packets corresponding to the given shader stage
3996 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3997 * This means that we can look up a program in the in-memory cache and
3998 * get most of the state packet without having to reconstruct it.
4001 iris_store_derived_program_state(struct iris_context
*ice
,
4002 enum iris_program_cache_id cache_id
,
4003 struct iris_compiled_shader
*shader
)
4005 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
4006 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
4010 iris_store_vs_state(ice
, devinfo
, shader
);
4012 case IRIS_CACHE_TCS
:
4013 iris_store_tcs_state(ice
, devinfo
, shader
);
4015 case IRIS_CACHE_TES
:
4016 iris_store_tes_state(ice
, devinfo
, shader
);
4019 iris_store_gs_state(ice
, devinfo
, shader
);
4022 iris_store_fs_state(ice
, devinfo
, shader
);
4025 iris_store_cs_state(ice
, devinfo
, shader
);
4026 case IRIS_CACHE_BLORP
:
4033 /* ------------------------------------------------------------------- */
4035 static const uint32_t push_constant_opcodes
[] = {
4036 [MESA_SHADER_VERTEX
] = 21,
4037 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
4038 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
4039 [MESA_SHADER_GEOMETRY
] = 22,
4040 [MESA_SHADER_FRAGMENT
] = 23,
4041 [MESA_SHADER_COMPUTE
] = 0,
4045 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
4047 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
4049 iris_use_pinned_bo(batch
, state_bo
, false);
4051 return ice
->state
.unbound_tex
.offset
;
4055 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
4057 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
4058 if (!ice
->state
.null_fb
.res
)
4059 return use_null_surface(batch
, ice
);
4061 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
4063 iris_use_pinned_bo(batch
, state_bo
, false);
4065 return ice
->state
.null_fb
.offset
;
4069 surf_state_offset_for_aux(struct iris_resource
*res
,
4071 enum isl_aux_usage aux_usage
)
4073 return SURFACE_STATE_ALIGNMENT
*
4074 util_bitcount(aux_modes
& ((1 << aux_usage
) - 1));
4079 surf_state_update_clear_value(struct iris_batch
*batch
,
4080 struct iris_resource
*res
,
4081 struct iris_state_ref
*state
,
4083 enum isl_aux_usage aux_usage
)
4085 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
4086 struct iris_bo
*state_bo
= iris_resource_bo(state
->res
);
4087 uint64_t real_offset
= state
->offset
+ IRIS_MEMZONE_BINDER_START
;
4088 uint32_t offset_into_bo
= real_offset
- state_bo
->gtt_offset
;
4089 uint32_t clear_offset
= offset_into_bo
+
4090 isl_dev
->ss
.clear_value_offset
+
4091 surf_state_offset_for_aux(res
, aux_modes
, aux_usage
);
4092 uint32_t *color
= res
->aux
.clear_color
.u32
;
4094 assert(isl_dev
->ss
.clear_value_size
== 16);
4096 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
4097 iris_emit_pipe_control_write(batch
, "update fast clear value (Z)",
4098 PIPE_CONTROL_WRITE_IMMEDIATE
,
4099 state_bo
, clear_offset
, color
[0]);
4101 iris_emit_pipe_control_write(batch
, "update fast clear color (RG__)",
4102 PIPE_CONTROL_WRITE_IMMEDIATE
,
4103 state_bo
, clear_offset
,
4104 (uint64_t) color
[0] |
4105 (uint64_t) color
[1] << 32);
4106 iris_emit_pipe_control_write(batch
, "update fast clear color (__BA)",
4107 PIPE_CONTROL_WRITE_IMMEDIATE
,
4108 state_bo
, clear_offset
+ 8,
4109 (uint64_t) color
[2] |
4110 (uint64_t) color
[3] << 32);
4113 iris_emit_pipe_control_flush(batch
,
4114 "update fast clear: state cache invalidate",
4115 PIPE_CONTROL_FLUSH_ENABLE
|
4116 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
4121 update_clear_value(struct iris_context
*ice
,
4122 struct iris_batch
*batch
,
4123 struct iris_resource
*res
,
4124 struct iris_state_ref
*state
,
4125 unsigned all_aux_modes
,
4126 struct isl_view
*view
)
4128 UNUSED
struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
4129 UNUSED
unsigned aux_modes
= all_aux_modes
;
4131 /* We only need to update the clear color in the surface state for gen8 and
4132 * gen9. Newer gens can read it directly from the clear color state buffer.
4135 /* Skip updating the ISL_AUX_USAGE_NONE surface state */
4136 aux_modes
&= ~(1 << ISL_AUX_USAGE_NONE
);
4139 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4141 surf_state_update_clear_value(batch
, res
, state
, all_aux_modes
,
4145 pipe_resource_reference(&state
->res
, NULL
);
4147 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
4148 state
, all_aux_modes
);
4150 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4151 fill_surface_state(isl_dev
, map
, res
, &res
->surf
, view
, aux_usage
, 0, 0);
4152 map
+= SURFACE_STATE_ALIGNMENT
;
4158 * Add a surface to the validation list, as well as the buffer containing
4159 * the corresponding SURFACE_STATE.
4161 * Returns the binding table entry (offset to SURFACE_STATE).
4164 use_surface(struct iris_context
*ice
,
4165 struct iris_batch
*batch
,
4166 struct pipe_surface
*p_surf
,
4168 enum isl_aux_usage aux_usage
,
4169 bool is_read_surface
)
4171 struct iris_surface
*surf
= (void *) p_surf
;
4172 struct iris_resource
*res
= (void *) p_surf
->texture
;
4173 uint32_t offset
= 0;
4175 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
4176 if (GEN_GEN
== 8 && is_read_surface
) {
4177 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state_read
.res
), false);
4179 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
4183 iris_use_pinned_bo(batch
, res
->aux
.bo
, writeable
);
4184 if (res
->aux
.clear_color_bo
)
4185 iris_use_pinned_bo(batch
, res
->aux
.clear_color_bo
, false);
4187 if (memcmp(&res
->aux
.clear_color
, &surf
->clear_color
,
4188 sizeof(surf
->clear_color
)) != 0) {
4189 update_clear_value(ice
, batch
, res
, &surf
->surface_state
,
4190 res
->aux
.possible_usages
, &surf
->view
);
4192 update_clear_value(ice
, batch
, res
, &surf
->surface_state_read
,
4193 res
->aux
.possible_usages
, &surf
->read_view
);
4195 surf
->clear_color
= res
->aux
.clear_color
;
4199 offset
= (GEN_GEN
== 8 && is_read_surface
) ? surf
->surface_state_read
.offset
4200 : surf
->surface_state
.offset
;
4203 surf_state_offset_for_aux(res
, res
->aux
.possible_usages
, aux_usage
);
4207 use_sampler_view(struct iris_context
*ice
,
4208 struct iris_batch
*batch
,
4209 struct iris_sampler_view
*isv
)
4212 enum isl_aux_usage aux_usage
=
4213 iris_resource_texture_aux_usage(ice
, isv
->res
, isv
->view
.format
, 0);
4215 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
4216 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
4218 if (isv
->res
->aux
.bo
) {
4219 iris_use_pinned_bo(batch
, isv
->res
->aux
.bo
, false);
4220 if (isv
->res
->aux
.clear_color_bo
)
4221 iris_use_pinned_bo(batch
, isv
->res
->aux
.clear_color_bo
, false);
4222 if (memcmp(&isv
->res
->aux
.clear_color
, &isv
->clear_color
,
4223 sizeof(isv
->clear_color
)) != 0) {
4224 update_clear_value(ice
, batch
, isv
->res
, &isv
->surface_state
,
4225 isv
->res
->aux
.sampler_usages
, &isv
->view
);
4226 isv
->clear_color
= isv
->res
->aux
.clear_color
;
4230 return isv
->surface_state
.offset
+
4231 surf_state_offset_for_aux(isv
->res
, isv
->res
->aux
.sampler_usages
,
4236 use_ubo_ssbo(struct iris_batch
*batch
,
4237 struct iris_context
*ice
,
4238 struct pipe_shader_buffer
*buf
,
4239 struct iris_state_ref
*surf_state
,
4242 if (!buf
->buffer
|| !surf_state
->res
)
4243 return use_null_surface(batch
, ice
);
4245 iris_use_pinned_bo(batch
, iris_resource_bo(buf
->buffer
), writable
);
4246 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
4248 return surf_state
->offset
;
4252 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
4253 struct iris_shader_state
*shs
, int i
)
4255 struct iris_image_view
*iv
= &shs
->image
[i
];
4256 struct iris_resource
*res
= (void *) iv
->base
.resource
;
4259 return use_null_surface(batch
, ice
);
4261 bool write
= iv
->base
.shader_access
& PIPE_IMAGE_ACCESS_WRITE
;
4263 iris_use_pinned_bo(batch
, res
->bo
, write
);
4264 iris_use_pinned_bo(batch
, iris_resource_bo(iv
->surface_state
.res
), false);
4267 iris_use_pinned_bo(batch
, res
->aux
.bo
, write
);
4269 return iv
->surface_state
.offset
;
4272 #define push_bt_entry(addr) \
4273 assert(addr >= binder_addr); \
4274 assert(s < shader->bt.size_bytes / sizeof(uint32_t)); \
4275 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
4277 #define bt_assert(section) \
4278 if (!pin_only && shader->bt.used_mask[section] != 0) \
4279 assert(shader->bt.offsets[section] == s);
4282 * Populate the binding table for a given shader stage.
4284 * This fills out the table of pointers to surfaces required by the shader,
4285 * and also adds those buffers to the validation list so the kernel can make
4286 * resident before running our batch.
4289 iris_populate_binding_table(struct iris_context
*ice
,
4290 struct iris_batch
*batch
,
4291 gl_shader_stage stage
,
4294 const struct iris_binder
*binder
= &ice
->state
.binder
;
4295 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
4296 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4300 struct iris_binding_table
*bt
= &shader
->bt
;
4301 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4302 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4303 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
4305 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
4308 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
4310 /* TCS passthrough doesn't need a binding table. */
4311 assert(stage
== MESA_SHADER_TESS_CTRL
);
4315 if (stage
== MESA_SHADER_COMPUTE
&&
4316 shader
->bt
.used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
]) {
4317 /* surface for gl_NumWorkGroups */
4318 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
4319 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
4320 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
4321 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
4322 push_bt_entry(grid_state
->offset
);
4325 if (stage
== MESA_SHADER_FRAGMENT
) {
4326 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4327 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
4328 if (cso_fb
->nr_cbufs
) {
4329 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
4331 if (cso_fb
->cbufs
[i
]) {
4332 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
], true,
4333 ice
->state
.draw_aux_usage
[i
], false);
4335 addr
= use_null_fb_surface(batch
, ice
);
4337 push_bt_entry(addr
);
4339 } else if (GEN_GEN
< 11) {
4340 uint32_t addr
= use_null_fb_surface(batch
, ice
);
4341 push_bt_entry(addr
);
4345 #define foreach_surface_used(index, group) \
4347 for (int index = 0; index < bt->sizes[group]; index++) \
4348 if (iris_group_index_to_bti(bt, group, index) != \
4349 IRIS_SURFACE_NOT_USED)
4351 foreach_surface_used(i
, IRIS_SURFACE_GROUP_RENDER_TARGET_READ
) {
4352 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4354 if (cso_fb
->cbufs
[i
]) {
4355 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
],
4356 true, ice
->state
.draw_aux_usage
[i
], true);
4357 push_bt_entry(addr
);
4361 foreach_surface_used(i
, IRIS_SURFACE_GROUP_TEXTURE
) {
4362 struct iris_sampler_view
*view
= shs
->textures
[i
];
4363 uint32_t addr
= view
? use_sampler_view(ice
, batch
, view
)
4364 : use_null_surface(batch
, ice
);
4365 push_bt_entry(addr
);
4368 foreach_surface_used(i
, IRIS_SURFACE_GROUP_IMAGE
) {
4369 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
4370 push_bt_entry(addr
);
4373 foreach_surface_used(i
, IRIS_SURFACE_GROUP_UBO
) {
4376 if (i
== bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] - 1) {
4377 if (ish
->const_data
) {
4378 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data
), false);
4379 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data_state
.res
),
4381 addr
= ish
->const_data_state
.offset
;
4383 /* This can only happen with INTEL_DISABLE_COMPACT_BINDING_TABLE=1. */
4384 addr
= use_null_surface(batch
, ice
);
4387 addr
= use_ubo_ssbo(batch
, ice
, &shs
->constbuf
[i
],
4388 &shs
->constbuf_surf_state
[i
], false);
4391 push_bt_entry(addr
);
4394 foreach_surface_used(i
, IRIS_SURFACE_GROUP_SSBO
) {
4396 use_ubo_ssbo(batch
, ice
, &shs
->ssbo
[i
], &shs
->ssbo_surf_state
[i
],
4397 shs
->writable_ssbos
& (1u << i
));
4398 push_bt_entry(addr
);
4402 /* XXX: YUV surfaces not implemented yet */
4403 bt_assert(plane_start
[1], ...);
4404 bt_assert(plane_start
[2], ...);
4409 iris_use_optional_res(struct iris_batch
*batch
,
4410 struct pipe_resource
*res
,
4414 struct iris_bo
*bo
= iris_resource_bo(res
);
4415 iris_use_pinned_bo(batch
, bo
, writeable
);
4420 pin_depth_and_stencil_buffers(struct iris_batch
*batch
,
4421 struct pipe_surface
*zsbuf
,
4422 struct iris_depth_stencil_alpha_state
*cso_zsa
)
4427 struct iris_resource
*zres
, *sres
;
4428 iris_get_depth_stencil_resources(zsbuf
->texture
, &zres
, &sres
);
4431 iris_use_pinned_bo(batch
, zres
->bo
, cso_zsa
->depth_writes_enabled
);
4433 iris_use_pinned_bo(batch
, zres
->aux
.bo
,
4434 cso_zsa
->depth_writes_enabled
);
4439 iris_use_pinned_bo(batch
, sres
->bo
, cso_zsa
->stencil_writes_enabled
);
4443 /* ------------------------------------------------------------------- */
4446 * Pin any BOs which were installed by a previous batch, and restored
4447 * via the hardware logical context mechanism.
4449 * We don't need to re-emit all state every batch - the hardware context
4450 * mechanism will save and restore it for us. This includes pointers to
4451 * various BOs...which won't exist unless we ask the kernel to pin them
4452 * by adding them to the validation list.
4454 * We can skip buffers if we've re-emitted those packets, as we're
4455 * overwriting those stale pointers with new ones, and don't actually
4456 * refer to the old BOs.
4459 iris_restore_render_saved_bos(struct iris_context
*ice
,
4460 struct iris_batch
*batch
,
4461 const struct pipe_draw_info
*draw
)
4463 struct iris_genx_state
*genx
= ice
->state
.genx
;
4465 const uint64_t clean
= ~ice
->state
.dirty
;
4467 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
4468 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
4471 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4472 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
4475 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
4476 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
4479 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4480 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
4483 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
4484 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
4487 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
4488 for (int i
= 0; i
< 4; i
++) {
4489 struct iris_stream_output_target
*tgt
=
4490 (void *) ice
->state
.so_target
[i
];
4492 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4494 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4500 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4501 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4504 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4505 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4510 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4512 for (int i
= 0; i
< 4; i
++) {
4513 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4515 if (range
->length
== 0)
4518 /* Range block is a binding table index, map back to UBO index. */
4519 unsigned block_index
= iris_bti_to_group_index(
4520 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
4521 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
4523 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4524 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4527 iris_use_pinned_bo(batch
, res
->bo
, false);
4529 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4533 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4534 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4535 /* Re-pin any buffers referred to by the binding table. */
4536 iris_populate_binding_table(ice
, batch
, stage
, true);
4540 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4541 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4542 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4544 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4547 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4548 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
4549 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4552 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4553 iris_use_pinned_bo(batch
, bo
, false);
4555 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4557 if (prog_data
->total_scratch
> 0) {
4558 struct iris_bo
*bo
=
4559 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4560 iris_use_pinned_bo(batch
, bo
, true);
4566 if ((clean
& IRIS_DIRTY_DEPTH_BUFFER
) &&
4567 (clean
& IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
4568 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4569 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
4572 iris_use_optional_res(batch
, ice
->state
.last_res
.index_buffer
, false);
4574 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4575 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4577 const int i
= u_bit_scan64(&bound
);
4578 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
4579 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4585 iris_restore_compute_saved_bos(struct iris_context
*ice
,
4586 struct iris_batch
*batch
,
4587 const struct pipe_grid_info
*grid
)
4589 const uint64_t clean
= ~ice
->state
.dirty
;
4591 const int stage
= MESA_SHADER_COMPUTE
;
4592 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4594 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
4595 /* Re-pin any buffers referred to by the binding table. */
4596 iris_populate_binding_table(ice
, batch
, stage
, true);
4599 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
4601 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
4603 if ((clean
& IRIS_DIRTY_SAMPLER_STATES_CS
) &&
4604 (clean
& IRIS_DIRTY_BINDINGS_CS
) &&
4605 (clean
& IRIS_DIRTY_CONSTANTS_CS
) &&
4606 (clean
& IRIS_DIRTY_CS
)) {
4607 iris_use_optional_res(batch
, ice
->state
.last_res
.cs_desc
, false);
4610 if (clean
& IRIS_DIRTY_CS
) {
4611 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4614 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4615 iris_use_pinned_bo(batch
, bo
, false);
4617 struct iris_bo
*curbe_bo
=
4618 iris_resource_bo(ice
->state
.last_res
.cs_thread_ids
);
4619 iris_use_pinned_bo(batch
, curbe_bo
, false);
4621 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4623 if (prog_data
->total_scratch
> 0) {
4624 struct iris_bo
*bo
=
4625 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4626 iris_use_pinned_bo(batch
, bo
, true);
4633 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
4636 iris_update_surface_base_address(struct iris_batch
*batch
,
4637 struct iris_binder
*binder
)
4639 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
4642 flush_before_state_base_change(batch
);
4644 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
4645 sba
.SurfaceStateBaseAddressModifyEnable
= true;
4646 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
4648 /* The hardware appears to pay attention to the MOCS fields even
4649 * if you don't set the "Address Modify Enable" bit for the base.
4651 sba
.GeneralStateMOCS
= MOCS_WB
;
4652 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
4653 sba
.DynamicStateMOCS
= MOCS_WB
;
4654 sba
.IndirectObjectMOCS
= MOCS_WB
;
4655 sba
.InstructionMOCS
= MOCS_WB
;
4656 sba
.SurfaceStateMOCS
= MOCS_WB
;
4658 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
4662 flush_after_state_base_change(batch
);
4664 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
4668 iris_viewport_zmin_zmax(const struct pipe_viewport_state
*vp
, bool halfz
,
4669 bool window_space_position
, float *zmin
, float *zmax
)
4671 if (window_space_position
) {
4676 util_viewport_zmin_zmax(vp
, halfz
, zmin
, zmax
);
4680 iris_upload_dirty_render_state(struct iris_context
*ice
,
4681 struct iris_batch
*batch
,
4682 const struct pipe_draw_info
*draw
)
4684 const uint64_t dirty
= ice
->state
.dirty
;
4686 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
4689 struct iris_genx_state
*genx
= ice
->state
.genx
;
4690 struct iris_binder
*binder
= &ice
->state
.binder
;
4691 struct brw_wm_prog_data
*wm_prog_data
= (void *)
4692 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
4694 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
4695 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4696 uint32_t cc_vp_address
;
4698 /* XXX: could avoid streaming for depth_clip [0,1] case. */
4699 uint32_t *cc_vp_map
=
4700 stream_state(batch
, ice
->state
.dynamic_uploader
,
4701 &ice
->state
.last_res
.cc_vp
,
4702 4 * ice
->state
.num_viewports
*
4703 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
4704 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4706 iris_viewport_zmin_zmax(&ice
->state
.viewports
[i
], cso_rast
->clip_halfz
,
4707 ice
->state
.window_space_position
,
4709 if (cso_rast
->depth_clip_near
)
4711 if (cso_rast
->depth_clip_far
)
4714 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
4715 ccv
.MinimumDepth
= zmin
;
4716 ccv
.MaximumDepth
= zmax
;
4719 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
4722 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
4723 ptr
.CCViewportPointer
= cc_vp_address
;
4727 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4728 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4729 uint32_t sf_cl_vp_address
;
4731 stream_state(batch
, ice
->state
.dynamic_uploader
,
4732 &ice
->state
.last_res
.sf_cl_vp
,
4733 4 * ice
->state
.num_viewports
*
4734 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
4736 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4737 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
4738 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
4740 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
4741 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
4742 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
4743 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
4745 gen_calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
4746 state
->scale
[0], state
->scale
[1],
4747 state
->translate
[0], state
->translate
[1],
4748 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
4750 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
4751 vp
.ViewportMatrixElementm00
= state
->scale
[0];
4752 vp
.ViewportMatrixElementm11
= state
->scale
[1];
4753 vp
.ViewportMatrixElementm22
= state
->scale
[2];
4754 vp
.ViewportMatrixElementm30
= state
->translate
[0];
4755 vp
.ViewportMatrixElementm31
= state
->translate
[1];
4756 vp
.ViewportMatrixElementm32
= state
->translate
[2];
4757 vp
.XMinClipGuardband
= gb_xmin
;
4758 vp
.XMaxClipGuardband
= gb_xmax
;
4759 vp
.YMinClipGuardband
= gb_ymin
;
4760 vp
.YMaxClipGuardband
= gb_ymax
;
4761 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
4762 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
4763 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
4764 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
4767 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
4770 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
4771 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
4775 if (dirty
& IRIS_DIRTY_URB
) {
4778 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
4779 if (!ice
->shaders
.prog
[i
]) {
4782 struct brw_vue_prog_data
*vue_prog_data
=
4783 (void *) ice
->shaders
.prog
[i
]->prog_data
;
4784 size
[i
] = vue_prog_data
->urb_entry_size
;
4786 assert(size
[i
] != 0);
4789 genX(emit_urb_setup
)(ice
, batch
, size
,
4790 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
4791 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
);
4794 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
4795 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4796 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4797 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4798 const int header_dwords
= GENX(BLEND_STATE_length
);
4800 /* Always write at least one BLEND_STATE - the final RT message will
4801 * reference BLEND_STATE[0] even if there aren't color writes. There
4802 * may still be alpha testing, computed depth, and so on.
4804 const int rt_dwords
=
4805 MAX2(cso_fb
->nr_cbufs
, 1) * GENX(BLEND_STATE_ENTRY_length
);
4807 uint32_t blend_offset
;
4808 uint32_t *blend_map
=
4809 stream_state(batch
, ice
->state
.dynamic_uploader
,
4810 &ice
->state
.last_res
.blend
,
4811 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4813 uint32_t blend_state_header
;
4814 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4815 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4816 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4819 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4820 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4822 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4823 ptr
.BlendStatePointer
= blend_offset
;
4824 ptr
.BlendStatePointerValid
= true;
4828 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4829 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4831 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4835 stream_state(batch
, ice
->state
.dynamic_uploader
,
4836 &ice
->state
.last_res
.color_calc
,
4837 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4839 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4840 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4841 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4842 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4843 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4844 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4845 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4847 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4848 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4851 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4852 ptr
.ColorCalcStatePointer
= cc_offset
;
4853 ptr
.ColorCalcStatePointerValid
= true;
4857 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4858 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4861 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4862 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4867 if (shs
->sysvals_need_upload
)
4868 upload_sysvals(ice
, stage
);
4870 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4872 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4873 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4875 /* The Skylake PRM contains the following restriction:
4877 * "The driver must ensure The following case does not occur
4878 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4879 * buffer 3 read length equal to zero committed followed by a
4880 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4883 * To avoid this, we program the buffers in the highest slots.
4884 * This way, slot 0 is only used if slot 3 is also used.
4888 for (int i
= 3; i
>= 0; i
--) {
4889 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4891 if (range
->length
== 0)
4894 /* Range block is a binding table index, map back to UBO index. */
4895 unsigned block_index
= iris_bti_to_group_index(
4896 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
4897 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
4899 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4900 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4902 assert(cbuf
->buffer_offset
% 32 == 0);
4904 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4905 pkt
.ConstantBody
.Buffer
[n
] =
4906 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->buffer_offset
)
4907 : ro_bo(batch
->screen
->workaround_bo
, 0);
4914 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4915 /* Gen9 requires 3DSTATE_BINDING_TABLE_POINTERS_XS to be re-emitted
4916 * in order to commit constants. TODO: Investigate "Disable Gather
4917 * at Set Shader" to go back to legacy mode...
4919 if (dirty
& ((IRIS_DIRTY_BINDINGS_VS
|
4920 (GEN_GEN
== 9 ? IRIS_DIRTY_CONSTANTS_VS
: 0)) << stage
)) {
4921 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4922 ptr
._3DCommandSubOpcode
= 38 + stage
;
4923 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4928 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4929 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4930 iris_populate_binding_table(ice
, batch
, stage
, false);
4934 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4935 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4936 !ice
->shaders
.prog
[stage
])
4939 iris_upload_sampler_states(ice
, stage
);
4941 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4942 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4944 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4946 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4947 ptr
._3DCommandSubOpcode
= 43 + stage
;
4948 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4952 if (ice
->state
.need_border_colors
)
4953 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4955 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4956 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4958 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4959 if (ice
->state
.framebuffer
.samples
> 0)
4960 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4964 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4965 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4966 ms
.SampleMask
= ice
->state
.sample_mask
;
4970 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4971 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4974 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4977 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4978 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4979 iris_use_pinned_bo(batch
, cache
->bo
, false);
4981 if (prog_data
->total_scratch
> 0) {
4982 struct iris_bo
*bo
=
4983 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4984 iris_use_pinned_bo(batch
, bo
, true);
4987 if (stage
== MESA_SHADER_FRAGMENT
) {
4988 UNUSED
struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4989 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4991 uint32_t ps_state
[GENX(3DSTATE_PS_length
)] = {0};
4992 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
4993 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
4994 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
4995 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
4997 /* The docs for 3DSTATE_PS::32 Pixel Dispatch Enable say:
4999 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16,
5000 * SIMD32 Dispatch must not be enabled for PER_PIXEL dispatch
5003 * 16x MSAA only exists on Gen9+, so we can skip this on Gen8.
5005 if (GEN_GEN
>= 9 && cso_fb
->samples
== 16 &&
5006 !wm_prog_data
->persample_dispatch
) {
5007 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
5008 ps
._32PixelDispatchEnable
= false;
5011 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
5012 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
5013 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
5014 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
5015 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
5016 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
5018 ps
.KernelStartPointer0
= KSP(shader
) +
5019 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
5020 ps
.KernelStartPointer1
= KSP(shader
) +
5021 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
5022 ps
.KernelStartPointer2
= KSP(shader
) +
5023 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
5026 uint32_t psx_state
[GENX(3DSTATE_PS_EXTRA_length
)] = {0};
5027 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
5029 if (!wm_prog_data
->uses_sample_mask
)
5030 psx
.InputCoverageMaskState
= ICMS_NONE
;
5031 else if (wm_prog_data
->post_depth_coverage
)
5032 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
5033 else if (wm_prog_data
->inner_coverage
&&
5034 cso
->conservative_rasterization
)
5035 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
5037 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
5039 psx
.PixelShaderUsesInputCoverageMask
=
5040 wm_prog_data
->uses_sample_mask
;
5044 uint32_t *shader_ps
= (uint32_t *) shader
->derived_data
;
5045 uint32_t *shader_psx
= shader_ps
+ GENX(3DSTATE_PS_length
);
5046 iris_emit_merge(batch
, shader_ps
, ps_state
,
5047 GENX(3DSTATE_PS_length
));
5048 iris_emit_merge(batch
, shader_psx
, psx_state
,
5049 GENX(3DSTATE_PS_EXTRA_length
));
5051 iris_batch_emit(batch
, shader
->derived_data
,
5052 iris_derived_program_state_size(stage
));
5055 if (stage
== MESA_SHADER_TESS_EVAL
) {
5056 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
5057 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
5058 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
5059 } else if (stage
== MESA_SHADER_GEOMETRY
) {
5060 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
5065 if (ice
->state
.streamout_active
) {
5066 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
5067 iris_batch_emit(batch
, genx
->so_buffers
,
5068 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
5069 for (int i
= 0; i
< 4; i
++) {
5070 struct iris_stream_output_target
*tgt
=
5071 (void *) ice
->state
.so_target
[i
];
5074 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
5076 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
5082 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
5083 uint32_t *decl_list
=
5084 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
5085 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
5088 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
5089 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5091 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
5092 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
5093 sol
.SOFunctionEnable
= true;
5094 sol
.SOStatisticsEnable
= true;
5096 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
5097 !ice
->state
.prims_generated_query_active
;
5098 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
5101 assert(ice
->state
.streamout
);
5103 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
5104 GENX(3DSTATE_STREAMOUT_length
));
5107 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
5108 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
5112 if (dirty
& IRIS_DIRTY_CLIP
) {
5113 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5114 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5116 bool gs_or_tes
= ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] ||
5117 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
5118 bool points_or_lines
= cso_rast
->fill_mode_point_or_line
||
5119 (gs_or_tes
? ice
->shaders
.output_topology_is_points_or_lines
5120 : ice
->state
.prim_is_points_or_lines
);
5122 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
5123 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
5124 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5125 if (cso_rast
->rasterizer_discard
)
5126 cl
.ClipMode
= CLIPMODE_REJECT_ALL
;
5127 else if (ice
->state
.window_space_position
)
5128 cl
.ClipMode
= CLIPMODE_ACCEPT_ALL
;
5130 cl
.ClipMode
= CLIPMODE_NORMAL
;
5132 cl
.PerspectiveDivideDisable
= ice
->state
.window_space_position
;
5133 cl
.ViewportXYClipTestEnable
= !points_or_lines
;
5135 if (wm_prog_data
->barycentric_interp_modes
&
5136 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
5137 cl
.NonPerspectiveBarycentricEnable
= true;
5139 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
5140 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
5142 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
5143 ARRAY_SIZE(cso_rast
->clip
));
5146 if (dirty
& IRIS_DIRTY_RASTER
) {
5147 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5148 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
5150 uint32_t dynamic_sf
[GENX(3DSTATE_SF_length
)];
5151 iris_pack_command(GENX(3DSTATE_SF
), &dynamic_sf
, sf
) {
5152 sf
.ViewportTransformEnable
= !ice
->state
.window_space_position
;
5154 iris_emit_merge(batch
, cso
->sf
, dynamic_sf
,
5155 ARRAY_SIZE(dynamic_sf
));
5158 if (dirty
& IRIS_DIRTY_WM
) {
5159 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5160 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
5162 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
5163 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5165 wm
.BarycentricInterpolationMode
=
5166 wm_prog_data
->barycentric_interp_modes
;
5168 if (wm_prog_data
->early_fragment_tests
)
5169 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
5170 else if (wm_prog_data
->has_side_effects
)
5171 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
5173 /* We could skip this bit if color writes are enabled. */
5174 if (wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
)
5175 wm
.ForceThreadDispatchEnable
= ForceON
;
5177 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
5180 if (dirty
& IRIS_DIRTY_SBE
) {
5181 iris_emit_sbe(batch
, ice
);
5184 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
5185 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
5186 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
5187 const struct shader_info
*fs_info
=
5188 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
5190 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
5191 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
5192 pb
.HasWriteableRT
= has_writeable_rt(cso_blend
, fs_info
);
5193 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
5195 /* The dual source blending docs caution against using SRC1 factors
5196 * when the shader doesn't use a dual source render target write.
5197 * Empirically, this can lead to GPU hangs, and the results are
5198 * undefined anyway, so simply disable blending to avoid the hang.
5200 pb
.ColorBufferBlendEnable
= (cso_blend
->blend_enables
& 1) &&
5201 (!cso_blend
->dual_color_blending
|| wm_prog_data
->dual_src_blend
);
5204 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
5205 ARRAY_SIZE(cso_blend
->ps_blend
));
5208 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
5209 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
5211 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
5212 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
5213 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
5214 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
5215 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
5217 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
5219 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
5223 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
5224 uint32_t scissor_offset
=
5225 emit_state(batch
, ice
->state
.dynamic_uploader
,
5226 &ice
->state
.last_res
.scissor
,
5227 ice
->state
.scissors
,
5228 sizeof(struct pipe_scissor_state
) *
5229 ice
->state
.num_viewports
, 32);
5231 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
5232 ptr
.ScissorRectPointer
= scissor_offset
;
5236 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
5237 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
5239 /* Do not emit the clear params yets. We need to update the clear value
5242 uint32_t clear_length
= GENX(3DSTATE_CLEAR_PARAMS_length
) * 4;
5243 uint32_t cso_z_size
= sizeof(cso_z
->packets
) - clear_length
;
5244 iris_batch_emit(batch
, cso_z
->packets
, cso_z_size
);
5246 union isl_color_value clear_value
= { .f32
= { 0, } };
5248 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5249 if (cso_fb
->zsbuf
) {
5250 struct iris_resource
*zres
, *sres
;
5251 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
5253 if (zres
&& zres
->aux
.bo
)
5254 clear_value
= iris_resource_get_clear_color(zres
, NULL
, NULL
);
5257 uint32_t clear_params
[GENX(3DSTATE_CLEAR_PARAMS_length
)];
5258 iris_pack_command(GENX(3DSTATE_CLEAR_PARAMS
), clear_params
, clear
) {
5259 clear
.DepthClearValueValid
= true;
5260 clear
.DepthClearValue
= clear_value
.f32
[0];
5262 iris_batch_emit(batch
, clear_params
, clear_length
);
5265 if (dirty
& (IRIS_DIRTY_DEPTH_BUFFER
| IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
5266 /* Listen for buffer changes, and also write enable changes. */
5267 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5268 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
5271 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
5272 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
5273 for (int i
= 0; i
< 32; i
++) {
5274 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
5279 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
5280 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5281 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
5284 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
5285 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
5286 topo
.PrimitiveTopologyType
=
5287 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
5291 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
5292 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
5293 int dynamic_bound
= ice
->state
.bound_vertex_buffers
;
5295 if (ice
->state
.vs_uses_draw_params
) {
5296 assert(ice
->draw
.draw_params
.res
);
5298 struct iris_vertex_buffer_state
*state
=
5299 &(ice
->state
.genx
->vertex_buffers
[count
]);
5300 pipe_resource_reference(&state
->resource
, ice
->draw
.draw_params
.res
);
5301 struct iris_resource
*res
= (void *) state
->resource
;
5303 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
5304 vb
.VertexBufferIndex
= count
;
5305 vb
.AddressModifyEnable
= true;
5307 vb
.BufferSize
= res
->bo
->size
- ice
->draw
.draw_params
.offset
;
5308 vb
.BufferStartingAddress
=
5309 ro_bo(NULL
, res
->bo
->gtt_offset
+
5310 (int) ice
->draw
.draw_params
.offset
);
5311 vb
.MOCS
= mocs(res
->bo
);
5313 dynamic_bound
|= 1ull << count
;
5317 if (ice
->state
.vs_uses_derived_draw_params
) {
5318 struct iris_vertex_buffer_state
*state
=
5319 &(ice
->state
.genx
->vertex_buffers
[count
]);
5320 pipe_resource_reference(&state
->resource
,
5321 ice
->draw
.derived_draw_params
.res
);
5322 struct iris_resource
*res
= (void *) ice
->draw
.derived_draw_params
.res
;
5324 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
5325 vb
.VertexBufferIndex
= count
;
5326 vb
.AddressModifyEnable
= true;
5329 res
->bo
->size
- ice
->draw
.derived_draw_params
.offset
;
5330 vb
.BufferStartingAddress
=
5331 ro_bo(NULL
, res
->bo
->gtt_offset
+
5332 (int) ice
->draw
.derived_draw_params
.offset
);
5333 vb
.MOCS
= mocs(res
->bo
);
5335 dynamic_bound
|= 1ull << count
;
5340 /* The VF cache designers cut corners, and made the cache key's
5341 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
5342 * 32 bits of the address. If you have two vertex buffers which get
5343 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
5344 * you can get collisions (even within a single batch).
5346 * So, we need to do a VF cache invalidate if the buffer for a VB
5347 * slot slot changes [48:32] address bits from the previous time.
5349 unsigned flush_flags
= 0;
5351 uint64_t bound
= dynamic_bound
;
5353 const int i
= u_bit_scan64(&bound
);
5354 uint16_t high_bits
= 0;
5356 struct iris_resource
*res
=
5357 (void *) genx
->vertex_buffers
[i
].resource
;
5359 iris_use_pinned_bo(batch
, res
->bo
, false);
5361 high_bits
= res
->bo
->gtt_offset
>> 32ull;
5362 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
5363 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5364 PIPE_CONTROL_CS_STALL
;
5365 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
5371 iris_emit_pipe_control_flush(batch
,
5372 "workaround: VF cache 32-bit key [VB]",
5376 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
5379 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
5380 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
5381 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
5385 bound
= dynamic_bound
;
5387 const int i
= u_bit_scan64(&bound
);
5388 memcpy(map
, genx
->vertex_buffers
[i
].state
,
5389 sizeof(uint32_t) * vb_dwords
);
5395 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
5396 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5397 const unsigned entries
= MAX2(cso
->count
, 1);
5398 if (!(ice
->state
.vs_needs_sgvs_element
||
5399 ice
->state
.vs_uses_derived_draw_params
||
5400 ice
->state
.vs_needs_edge_flag
)) {
5401 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
5402 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
5404 uint32_t dynamic_ves
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
5405 const unsigned dyn_count
= cso
->count
+
5406 ice
->state
.vs_needs_sgvs_element
+
5407 ice
->state
.vs_uses_derived_draw_params
;
5409 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
),
5412 1 + GENX(VERTEX_ELEMENT_STATE_length
) * dyn_count
- 2;
5414 memcpy(&dynamic_ves
[1], &cso
->vertex_elements
[1],
5415 (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5416 GENX(VERTEX_ELEMENT_STATE_length
) * sizeof(uint32_t));
5417 uint32_t *ve_pack_dest
=
5418 &dynamic_ves
[1 + (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5419 GENX(VERTEX_ELEMENT_STATE_length
)];
5421 if (ice
->state
.vs_needs_sgvs_element
) {
5422 uint32_t base_ctrl
= ice
->state
.vs_uses_draw_params
?
5423 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
5424 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5426 ve
.VertexBufferIndex
=
5427 util_bitcount64(ice
->state
.bound_vertex_buffers
);
5428 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5429 ve
.Component0Control
= base_ctrl
;
5430 ve
.Component1Control
= base_ctrl
;
5431 ve
.Component2Control
= VFCOMP_STORE_0
;
5432 ve
.Component3Control
= VFCOMP_STORE_0
;
5434 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5436 if (ice
->state
.vs_uses_derived_draw_params
) {
5437 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5439 ve
.VertexBufferIndex
=
5440 util_bitcount64(ice
->state
.bound_vertex_buffers
) +
5441 ice
->state
.vs_uses_draw_params
;
5442 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5443 ve
.Component0Control
= VFCOMP_STORE_SRC
;
5444 ve
.Component1Control
= VFCOMP_STORE_SRC
;
5445 ve
.Component2Control
= VFCOMP_STORE_0
;
5446 ve
.Component3Control
= VFCOMP_STORE_0
;
5448 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5450 if (ice
->state
.vs_needs_edge_flag
) {
5451 for (int i
= 0; i
< GENX(VERTEX_ELEMENT_STATE_length
); i
++)
5452 ve_pack_dest
[i
] = cso
->edgeflag_ve
[i
];
5455 iris_batch_emit(batch
, &dynamic_ves
, sizeof(uint32_t) *
5456 (1 + dyn_count
* GENX(VERTEX_ELEMENT_STATE_length
)));
5459 if (!ice
->state
.vs_needs_edge_flag
) {
5460 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
5461 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5463 assert(cso
->count
> 0);
5464 const unsigned edgeflag_index
= cso
->count
- 1;
5465 uint32_t dynamic_vfi
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
5466 memcpy(&dynamic_vfi
[0], cso
->vf_instancing
, edgeflag_index
*
5467 GENX(3DSTATE_VF_INSTANCING_length
) * sizeof(uint32_t));
5469 uint32_t *vfi_pack_dest
= &dynamic_vfi
[0] +
5470 edgeflag_index
* GENX(3DSTATE_VF_INSTANCING_length
);
5471 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
5472 vi
.VertexElementIndex
= edgeflag_index
+
5473 ice
->state
.vs_needs_sgvs_element
+
5474 ice
->state
.vs_uses_derived_draw_params
;
5476 for (int i
= 0; i
< GENX(3DSTATE_VF_INSTANCING_length
); i
++)
5477 vfi_pack_dest
[i
] |= cso
->edgeflag_vfi
[i
];
5479 iris_batch_emit(batch
, &dynamic_vfi
[0], sizeof(uint32_t) *
5480 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5484 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
5485 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
5486 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
5487 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5489 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
5490 if (vs_prog_data
->uses_vertexid
) {
5491 sgv
.VertexIDEnable
= true;
5492 sgv
.VertexIDComponentNumber
= 2;
5493 sgv
.VertexIDElementOffset
=
5494 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5497 if (vs_prog_data
->uses_instanceid
) {
5498 sgv
.InstanceIDEnable
= true;
5499 sgv
.InstanceIDComponentNumber
= 3;
5500 sgv
.InstanceIDElementOffset
=
5501 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5506 if (dirty
& IRIS_DIRTY_VF
) {
5507 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
5508 if (draw
->primitive_restart
) {
5509 vf
.IndexedDrawCutIndexEnable
= true;
5510 vf
.CutIndex
= draw
->restart_index
;
5515 if (dirty
& IRIS_DIRTY_VF_STATISTICS
) {
5516 iris_emit_cmd(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
5517 vf
.StatisticsEnable
= true;
5521 if (ice
->state
.current_hash_scale
!= 1)
5522 genX(emit_hashing_mode
)(ice
, batch
, UINT_MAX
, UINT_MAX
, 1);
5524 /* TODO: Gen8 PMA fix */
5528 iris_upload_render_state(struct iris_context
*ice
,
5529 struct iris_batch
*batch
,
5530 const struct pipe_draw_info
*draw
)
5532 bool use_predicate
= ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
5534 /* Always pin the binder. If we're emitting new binding table pointers,
5535 * we need it. If not, we're probably inheriting old tables via the
5536 * context, and need it anyway. Since true zero-bindings cases are
5537 * practically non-existent, just pin it and avoid last_res tracking.
5539 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5541 if (!batch
->contains_draw
) {
5542 iris_restore_render_saved_bos(ice
, batch
, draw
);
5543 batch
->contains_draw
= true;
5546 iris_upload_dirty_render_state(ice
, batch
, draw
);
5548 if (draw
->index_size
> 0) {
5551 if (draw
->has_user_indices
) {
5552 u_upload_data(ice
->ctx
.stream_uploader
, 0,
5553 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
5554 &offset
, &ice
->state
.last_res
.index_buffer
);
5556 struct iris_resource
*res
= (void *) draw
->index
.resource
;
5557 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
5559 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
5560 draw
->index
.resource
);
5564 struct iris_genx_state
*genx
= ice
->state
.genx
;
5565 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
5567 uint32_t ib_packet
[GENX(3DSTATE_INDEX_BUFFER_length
)];
5568 iris_pack_command(GENX(3DSTATE_INDEX_BUFFER
), ib_packet
, ib
) {
5569 ib
.IndexFormat
= draw
->index_size
>> 1;
5571 ib
.BufferSize
= bo
->size
- offset
;
5572 ib
.BufferStartingAddress
= ro_bo(NULL
, bo
->gtt_offset
+ offset
);
5575 if (memcmp(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
)) != 0) {
5576 memcpy(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
));
5577 iris_batch_emit(batch
, ib_packet
, sizeof(ib_packet
));
5578 iris_use_pinned_bo(batch
, bo
, false);
5581 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
5582 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
5583 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
5584 iris_emit_pipe_control_flush(batch
,
5585 "workaround: VF cache 32-bit key [IB]",
5586 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5587 PIPE_CONTROL_CS_STALL
);
5588 ice
->state
.last_index_bo_high_bits
= high_bits
;
5592 #define _3DPRIM_END_OFFSET 0x2420
5593 #define _3DPRIM_START_VERTEX 0x2430
5594 #define _3DPRIM_VERTEX_COUNT 0x2434
5595 #define _3DPRIM_INSTANCE_COUNT 0x2438
5596 #define _3DPRIM_START_INSTANCE 0x243C
5597 #define _3DPRIM_BASE_VERTEX 0x2440
5599 if (draw
->indirect
) {
5600 if (draw
->indirect
->indirect_draw_count
) {
5601 use_predicate
= true;
5603 struct iris_bo
*draw_count_bo
=
5604 iris_resource_bo(draw
->indirect
->indirect_draw_count
);
5605 unsigned draw_count_offset
=
5606 draw
->indirect
->indirect_draw_count_offset
;
5608 iris_emit_pipe_control_flush(batch
,
5609 "ensure indirect draw buffer is flushed",
5610 PIPE_CONTROL_FLUSH_ENABLE
);
5612 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
) {
5613 struct gen_mi_builder b
;
5614 gen_mi_builder_init(&b
, batch
);
5616 /* comparison = draw id < draw count */
5617 struct gen_mi_value comparison
=
5618 gen_mi_ult(&b
, gen_mi_imm(draw
->drawid
),
5619 gen_mi_mem32(ro_bo(draw_count_bo
,
5620 draw_count_offset
)));
5622 /* predicate = comparison & conditional rendering predicate */
5623 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_RESULT
),
5624 gen_mi_iand(&b
, comparison
,
5625 gen_mi_reg32(CS_GPR(15))));
5627 uint32_t mi_predicate
;
5629 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
5630 ice
->vtbl
.load_register_imm64(batch
, MI_PREDICATE_SRC1
,
5632 /* Upload the current draw count from the draw parameters buffer
5633 * to MI_PREDICATE_SRC0.
5635 ice
->vtbl
.load_register_mem32(batch
, MI_PREDICATE_SRC0
,
5636 draw_count_bo
, draw_count_offset
);
5637 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
5638 ice
->vtbl
.load_register_imm32(batch
, MI_PREDICATE_SRC0
+ 4, 0);
5640 if (draw
->drawid
== 0) {
5641 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
5642 MI_PREDICATE_COMBINEOP_SET
|
5643 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
5645 /* While draw_index < draw_count the predicate's result will be
5646 * (draw_index == draw_count) ^ TRUE = TRUE
5647 * When draw_index == draw_count the result is
5648 * (TRUE) ^ TRUE = FALSE
5649 * After this all results will be:
5650 * (FALSE) ^ FALSE = FALSE
5652 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOAD
|
5653 MI_PREDICATE_COMBINEOP_XOR
|
5654 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
5656 iris_batch_emit(batch
, &mi_predicate
, sizeof(uint32_t));
5659 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
5662 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5663 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
5664 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
5666 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5667 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
5668 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
5670 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5671 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
5672 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
5674 if (draw
->index_size
) {
5675 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5676 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
5677 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5679 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5680 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5681 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
5684 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5685 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5686 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5688 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
5689 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
5693 } else if (draw
->count_from_stream_output
) {
5694 struct iris_stream_output_target
*so
=
5695 (void *) draw
->count_from_stream_output
;
5697 /* XXX: Replace with actual cache tracking */
5698 iris_emit_pipe_control_flush(batch
,
5699 "draw count from stream output stall",
5700 PIPE_CONTROL_CS_STALL
);
5702 struct gen_mi_builder b
;
5703 gen_mi_builder_init(&b
, batch
);
5705 struct iris_address addr
=
5706 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
5707 struct gen_mi_value offset
=
5708 gen_mi_iadd_imm(&b
, gen_mi_mem32(addr
), -so
->base
.buffer_offset
);
5710 gen_mi_store(&b
, gen_mi_reg32(_3DPRIM_VERTEX_COUNT
),
5711 gen_mi_udiv32_imm(&b
, offset
, so
->stride
));
5713 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
5714 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
5715 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
5716 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
5719 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
5720 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
5721 prim
.PredicateEnable
= use_predicate
;
5723 if (draw
->indirect
|| draw
->count_from_stream_output
) {
5724 prim
.IndirectParameterEnable
= true;
5726 prim
.StartInstanceLocation
= draw
->start_instance
;
5727 prim
.InstanceCount
= draw
->instance_count
;
5728 prim
.VertexCountPerInstance
= draw
->count
;
5730 prim
.StartVertexLocation
= draw
->start
;
5732 if (draw
->index_size
) {
5733 prim
.BaseVertexLocation
+= draw
->index_bias
;
5735 prim
.StartVertexLocation
+= draw
->index_bias
;
5742 iris_upload_compute_state(struct iris_context
*ice
,
5743 struct iris_batch
*batch
,
5744 const struct pipe_grid_info
*grid
)
5746 const uint64_t dirty
= ice
->state
.dirty
;
5747 struct iris_screen
*screen
= batch
->screen
;
5748 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
5749 struct iris_binder
*binder
= &ice
->state
.binder
;
5750 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
5751 struct iris_compiled_shader
*shader
=
5752 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
5753 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5754 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
5756 /* Always pin the binder. If we're emitting new binding table pointers,
5757 * we need it. If not, we're probably inheriting old tables via the
5758 * context, and need it anyway. Since true zero-bindings cases are
5759 * practically non-existent, just pin it and avoid last_res tracking.
5761 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5763 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->sysvals_need_upload
)
5764 upload_sysvals(ice
, MESA_SHADER_COMPUTE
);
5766 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
5767 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
5769 if (dirty
& IRIS_DIRTY_SAMPLER_STATES_CS
)
5770 iris_upload_sampler_states(ice
, MESA_SHADER_COMPUTE
);
5772 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
5773 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
5775 if (ice
->state
.need_border_colors
)
5776 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
5778 if (dirty
& IRIS_DIRTY_CS
) {
5779 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
5781 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
5782 * the only bits that are changed are scoreboard related: Scoreboard
5783 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
5784 * these scoreboard related states, a MEDIA_STATE_FLUSH is
5787 iris_emit_pipe_control_flush(batch
,
5788 "workaround: stall before MEDIA_VFE_STATE",
5789 PIPE_CONTROL_CS_STALL
);
5791 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
5792 if (prog_data
->total_scratch
) {
5793 struct iris_bo
*bo
=
5794 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
5795 MESA_SHADER_COMPUTE
);
5796 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
5797 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
5800 vfe
.MaximumNumberofThreads
=
5801 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
5803 vfe
.ResetGatewayTimer
=
5804 Resettingrelativetimerandlatchingtheglobaltimestamp
;
5807 vfe
.BypassGatewayControl
= true;
5809 vfe
.NumberofURBEntries
= 2;
5810 vfe
.URBEntryAllocationSize
= 2;
5812 vfe
.CURBEAllocationSize
=
5813 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
5814 cs_prog_data
->push
.cross_thread
.regs
, 2);
5818 /* TODO: Combine subgroup-id with cbuf0 so we can push regular uniforms */
5819 if (dirty
& IRIS_DIRTY_CS
) {
5820 uint32_t curbe_data_offset
= 0;
5821 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
5822 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
5823 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
5824 uint32_t *curbe_data_map
=
5825 stream_state(batch
, ice
->state
.dynamic_uploader
,
5826 &ice
->state
.last_res
.cs_thread_ids
,
5827 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
5828 &curbe_data_offset
);
5829 assert(curbe_data_map
);
5830 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
5831 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
5833 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
5834 curbe
.CURBETotalDataLength
=
5835 ALIGN(cs_prog_data
->push
.total
.size
, 64);
5836 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
5840 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
5841 IRIS_DIRTY_BINDINGS_CS
|
5842 IRIS_DIRTY_CONSTANTS_CS
|
5844 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
5846 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
5847 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
5848 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
5851 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
5852 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
5854 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
5855 load
.InterfaceDescriptorTotalLength
=
5856 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
5857 load
.InterfaceDescriptorDataStartAddress
=
5858 emit_state(batch
, ice
->state
.dynamic_uploader
,
5859 &ice
->state
.last_res
.cs_desc
, desc
, sizeof(desc
), 64);
5863 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
5864 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
5865 uint32_t right_mask
;
5868 right_mask
= ~0u >> (32 - remainder
);
5870 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
5872 #define GPGPU_DISPATCHDIMX 0x2500
5873 #define GPGPU_DISPATCHDIMY 0x2504
5874 #define GPGPU_DISPATCHDIMZ 0x2508
5876 if (grid
->indirect
) {
5877 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
5878 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
5879 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5880 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
5881 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
5883 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5884 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
5885 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
5887 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5888 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
5889 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
5893 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
5894 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
5895 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
5896 ggw
.ThreadDepthCounterMaximum
= 0;
5897 ggw
.ThreadHeightCounterMaximum
= 0;
5898 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
5899 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
5900 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
5901 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
5902 ggw
.RightExecutionMask
= right_mask
;
5903 ggw
.BottomExecutionMask
= 0xffffffff;
5906 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
5908 if (!batch
->contains_draw
) {
5909 iris_restore_compute_saved_bos(ice
, batch
, grid
);
5910 batch
->contains_draw
= true;
5915 * State module teardown.
5918 iris_destroy_state(struct iris_context
*ice
)
5920 struct iris_genx_state
*genx
= ice
->state
.genx
;
5922 pipe_resource_reference(&ice
->draw
.draw_params
.res
, NULL
);
5923 pipe_resource_reference(&ice
->draw
.derived_draw_params
.res
, NULL
);
5925 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5927 const int i
= u_bit_scan64(&bound_vbs
);
5928 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
5930 free(ice
->state
.genx
);
5932 for (int i
= 0; i
< 4; i
++) {
5933 pipe_so_target_reference(&ice
->state
.so_target
[i
], NULL
);
5936 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
5937 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
5939 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
5941 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
5942 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5943 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
5944 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
5945 pipe_resource_reference(&shs
->constbuf
[i
].buffer
, NULL
);
5946 pipe_resource_reference(&shs
->constbuf_surf_state
[i
].res
, NULL
);
5948 for (int i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
5949 pipe_resource_reference(&shs
->image
[i
].base
.resource
, NULL
);
5950 pipe_resource_reference(&shs
->image
[i
].surface_state
.res
, NULL
);
5952 for (int i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
5953 pipe_resource_reference(&shs
->ssbo
[i
].buffer
, NULL
);
5954 pipe_resource_reference(&shs
->ssbo_surf_state
[i
].res
, NULL
);
5956 for (int i
= 0; i
< IRIS_MAX_TEXTURE_SAMPLERS
; i
++) {
5957 pipe_sampler_view_reference((struct pipe_sampler_view
**)
5958 &shs
->textures
[i
], NULL
);
5962 pipe_resource_reference(&ice
->state
.grid_size
.res
, NULL
);
5963 pipe_resource_reference(&ice
->state
.grid_surf_state
.res
, NULL
);
5965 pipe_resource_reference(&ice
->state
.null_fb
.res
, NULL
);
5966 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
5968 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
5969 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
5970 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
5971 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
5972 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
5973 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
5974 pipe_resource_reference(&ice
->state
.last_res
.cs_thread_ids
, NULL
);
5975 pipe_resource_reference(&ice
->state
.last_res
.cs_desc
, NULL
);
5978 /* ------------------------------------------------------------------- */
5981 iris_rebind_buffer(struct iris_context
*ice
,
5982 struct iris_resource
*res
,
5983 uint64_t old_address
)
5985 struct pipe_context
*ctx
= &ice
->ctx
;
5986 struct iris_screen
*screen
= (void *) ctx
->screen
;
5987 struct iris_genx_state
*genx
= ice
->state
.genx
;
5989 assert(res
->base
.target
== PIPE_BUFFER
);
5991 /* Buffers can't be framebuffer attachments, nor display related,
5992 * and we don't have upstream Clover support.
5994 assert(!(res
->bind_history
& (PIPE_BIND_DEPTH_STENCIL
|
5995 PIPE_BIND_RENDER_TARGET
|
5996 PIPE_BIND_BLENDABLE
|
5997 PIPE_BIND_DISPLAY_TARGET
|
5999 PIPE_BIND_COMPUTE_RESOURCE
|
6000 PIPE_BIND_GLOBAL
)));
6002 if (res
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
6003 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
6005 const int i
= u_bit_scan64(&bound_vbs
);
6006 struct iris_vertex_buffer_state
*state
= &genx
->vertex_buffers
[i
];
6008 /* Update the CPU struct */
6009 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_start
) == 32);
6010 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) == 64);
6011 uint64_t *addr
= (uint64_t *) &state
->state
[1];
6013 if (*addr
== old_address
) {
6014 *addr
= res
->bo
->gtt_offset
;
6015 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
6020 /* We don't need to handle PIPE_BIND_INDEX_BUFFER here: we re-emit
6021 * the 3DSTATE_INDEX_BUFFER packet whenever the address changes.
6023 * There is also no need to handle these:
6024 * - PIPE_BIND_COMMAND_ARGS_BUFFER (emitted for every indirect draw)
6025 * - PIPE_BIND_QUERY_BUFFER (no persistent state references)
6028 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
6029 /* XXX: be careful about resetting vs appending... */
6033 for (int s
= MESA_SHADER_VERTEX
; s
< MESA_SHADER_STAGES
; s
++) {
6034 struct iris_shader_state
*shs
= &ice
->state
.shaders
[s
];
6035 enum pipe_shader_type p_stage
= stage_to_pipe(s
);
6037 if (!(res
->bind_stages
& (1 << s
)))
6040 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
6041 /* Skip constant buffer 0, it's for regular uniforms, not UBOs */
6042 uint32_t bound_cbufs
= shs
->bound_cbufs
& ~1u;
6043 while (bound_cbufs
) {
6044 const int i
= u_bit_scan(&bound_cbufs
);
6045 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[i
];
6046 struct iris_state_ref
*surf_state
= &shs
->constbuf_surf_state
[i
];
6048 if (res
->bo
== iris_resource_bo(cbuf
->buffer
)) {
6049 pipe_resource_reference(&surf_state
->res
, NULL
);
6050 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< s
;
6055 if (res
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
6056 uint32_t bound_ssbos
= shs
->bound_ssbos
;
6057 while (bound_ssbos
) {
6058 const int i
= u_bit_scan(&bound_ssbos
);
6059 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[i
];
6061 if (res
->bo
== iris_resource_bo(ssbo
->buffer
)) {
6062 struct pipe_shader_buffer buf
= {
6063 .buffer
= &res
->base
,
6064 .buffer_offset
= ssbo
->buffer_offset
,
6065 .buffer_size
= ssbo
->buffer_size
,
6067 iris_set_shader_buffers(ctx
, p_stage
, i
, 1, &buf
,
6068 (shs
->writable_ssbos
>> i
) & 1);
6073 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
6074 uint32_t bound_sampler_views
= shs
->bound_sampler_views
;
6075 while (bound_sampler_views
) {
6076 const int i
= u_bit_scan(&bound_sampler_views
);
6077 struct iris_sampler_view
*isv
= shs
->textures
[i
];
6079 if (res
->bo
== iris_resource_bo(isv
->base
.texture
)) {
6080 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
6081 &isv
->surface_state
,
6082 isv
->res
->aux
.sampler_usages
);
6084 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
6085 isv
->view
.format
, isv
->view
.swizzle
,
6086 isv
->base
.u
.buf
.offset
,
6087 isv
->base
.u
.buf
.size
);
6088 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< s
;
6093 if (res
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
6094 uint32_t bound_image_views
= shs
->bound_image_views
;
6095 while (bound_image_views
) {
6096 const int i
= u_bit_scan(&bound_image_views
);
6097 struct iris_image_view
*iv
= &shs
->image
[i
];
6099 if (res
->bo
== iris_resource_bo(iv
->base
.resource
)) {
6100 iris_set_shader_images(ctx
, p_stage
, i
, 1, &iv
->base
);
6107 /* ------------------------------------------------------------------- */
6110 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
6113 _iris_emit_lrr(batch
, dst
, src
);
6117 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
6120 _iris_emit_lrr(batch
, dst
, src
);
6121 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
6125 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
6128 _iris_emit_lri(batch
, reg
, val
);
6132 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
6135 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
6136 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
6140 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
6143 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
6144 struct iris_bo
*bo
, uint32_t offset
)
6146 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6147 lrm
.RegisterAddress
= reg
;
6148 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
6153 * Load a 64-bit value from a buffer into a MMIO register via
6154 * two MI_LOAD_REGISTER_MEM commands.
6157 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
6158 struct iris_bo
*bo
, uint32_t offset
)
6160 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
6161 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
6165 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
6166 struct iris_bo
*bo
, uint32_t offset
,
6169 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
6170 srm
.RegisterAddress
= reg
;
6171 srm
.MemoryAddress
= rw_bo(bo
, offset
);
6172 srm
.PredicateEnable
= predicated
;
6177 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
6178 struct iris_bo
*bo
, uint32_t offset
,
6181 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
6182 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
6186 iris_store_data_imm32(struct iris_batch
*batch
,
6187 struct iris_bo
*bo
, uint32_t offset
,
6190 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
6191 sdi
.Address
= rw_bo(bo
, offset
);
6192 sdi
.ImmediateData
= imm
;
6197 iris_store_data_imm64(struct iris_batch
*batch
,
6198 struct iris_bo
*bo
, uint32_t offset
,
6201 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
6202 * 2 in genxml but it's actually variable length and we need 5 DWords.
6204 void *map
= iris_get_command_space(batch
, 4 * 5);
6205 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
6206 sdi
.DWordLength
= 5 - 2;
6207 sdi
.Address
= rw_bo(bo
, offset
);
6208 sdi
.ImmediateData
= imm
;
6213 iris_copy_mem_mem(struct iris_batch
*batch
,
6214 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
6215 struct iris_bo
*src_bo
, uint32_t src_offset
,
6218 /* MI_COPY_MEM_MEM operates on DWords. */
6219 assert(bytes
% 4 == 0);
6220 assert(dst_offset
% 4 == 0);
6221 assert(src_offset
% 4 == 0);
6223 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
6224 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
6225 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
6226 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
6231 /* ------------------------------------------------------------------- */
6234 flags_to_post_sync_op(uint32_t flags
)
6236 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
6237 return WriteImmediateData
;
6239 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
6240 return WritePSDepthCount
;
6242 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
6243 return WriteTimestamp
;
6249 * Do the given flags have a Post Sync or LRI Post Sync operation?
6251 static enum pipe_control_flags
6252 get_post_sync_flags(enum pipe_control_flags flags
)
6254 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
6255 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6256 PIPE_CONTROL_WRITE_TIMESTAMP
|
6257 PIPE_CONTROL_LRI_POST_SYNC_OP
;
6259 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
6260 * "LRI Post Sync Operation". So more than one bit set would be illegal.
6262 assert(util_bitcount(flags
) <= 1);
6267 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
6270 * Emit a series of PIPE_CONTROL commands, taking into account any
6271 * workarounds necessary to actually accomplish the caller's request.
6273 * Unless otherwise noted, spec quotations in this function come from:
6275 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
6276 * Restrictions for PIPE_CONTROL.
6278 * You should not use this function directly. Use the helpers in
6279 * iris_pipe_control.c instead, which may split the pipe control further.
6282 iris_emit_raw_pipe_control(struct iris_batch
*batch
,
6289 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6290 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
6291 enum pipe_control_flags non_lri_post_sync_flags
=
6292 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
6294 /* Recursive PIPE_CONTROL workarounds --------------------------------
6295 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
6297 * We do these first because we want to look at the original operation,
6298 * rather than any workarounds we set.
6300 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
6301 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
6302 * lists several workarounds:
6304 * "Project: SKL, KBL, BXT
6306 * If the VF Cache Invalidation Enable is set to a 1 in a
6307 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
6308 * sets to 0, with the VF Cache Invalidation Enable set to 0
6309 * needs to be sent prior to the PIPE_CONTROL with VF Cache
6310 * Invalidation Enable set to a 1."
6312 iris_emit_raw_pipe_control(batch
,
6313 "workaround: recursive VF cache invalidate",
6317 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
6318 /* Project: SKL / Argument: LRI Post Sync Operation [23]
6320 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6321 * programmed prior to programming a PIPECONTROL command with "LRI
6322 * Post Sync Operation" in GPGPU mode of operation (i.e when
6323 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
6325 * The same text exists a few rows below for Post Sync Op.
6327 iris_emit_raw_pipe_control(batch
,
6328 "workaround: CS stall before gpgpu post-sync",
6329 PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
6332 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
6334 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
6335 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
6336 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
6338 iris_emit_raw_pipe_control(batch
,
6339 "workaround: PC flush before RT flush",
6340 PIPE_CONTROL_FLUSH_ENABLE
, bo
, offset
, imm
);
6343 /* "Flush Types" workarounds ---------------------------------------------
6344 * We do these now because they may add post-sync operations or CS stalls.
6347 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
6348 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
6350 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
6351 * 'Write PS Depth Count' or 'Write Timestamp'."
6354 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6355 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6356 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6357 bo
= batch
->screen
->workaround_bo
;
6361 /* #1130 from Gen10 workarounds page:
6363 * "Enable Depth Stall on every Post Sync Op if Render target Cache
6364 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
6365 * board stall if Render target cache flush is enabled."
6367 * Applicable to CNL B0 and C0 steppings only.
6369 * The wording here is unclear, and this workaround doesn't look anything
6370 * like the internal bug report recommendations, but leave it be for now...
6372 if (GEN_GEN
== 10) {
6373 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
6374 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6375 } else if (flags
& non_lri_post_sync_flags
) {
6376 flags
|= PIPE_CONTROL_DEPTH_STALL
;
6380 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
6381 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
6383 * "This bit must be DISABLED for operations other than writing
6386 * This seems like nonsense. An Ivybridge workaround requires us to
6387 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
6388 * operation. Gen8+ requires us to emit depth stalls and depth cache
6389 * flushes together. So, it's hard to imagine this means anything other
6390 * than "we originally intended this to be used for PS_DEPTH_COUNT".
6392 * We ignore the supposed restriction and do nothing.
6396 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6397 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6398 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
6400 * "This bit must be DISABLED for End-of-pipe (Read) fences,
6401 * PS_DEPTH_COUNT or TIMESTAMP queries."
6403 * TODO: Implement end-of-pipe checking.
6405 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6406 PIPE_CONTROL_WRITE_TIMESTAMP
)));
6409 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6410 /* From the PIPE_CONTROL instruction table, bit 1:
6412 * "This bit is ignored if Depth Stall Enable is set.
6413 * Further, the render cache is not flushed even if Write Cache
6414 * Flush Enable bit is set."
6416 * We assert that the caller doesn't do this combination, to try and
6417 * prevent mistakes. It shouldn't hurt the GPU, though.
6419 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
6420 * and "Render Target Flush" combo is explicitly required for BTI
6421 * update workarounds.
6423 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
6424 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
6427 /* PIPE_CONTROL page workarounds ------------------------------------- */
6429 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
6430 /* From the PIPE_CONTROL page itself:
6433 * Restriction: Pipe_control with CS-stall bit set must be issued
6434 * before a pipe-control command that has the State Cache
6435 * Invalidate bit set."
6437 flags
|= PIPE_CONTROL_CS_STALL
;
6440 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
6441 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
6444 * SW must always program Post-Sync Operation to "Write Immediate
6445 * Data" when Flush LLC is set."
6447 * For now, we just require the caller to do it.
6449 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
6452 /* "Post-Sync Operation" workarounds -------------------------------- */
6454 /* Project: All / Argument: Global Snapshot Count Reset [19]
6456 * "This bit must not be exercised on any product.
6457 * Requires stall bit ([20] of DW1) set."
6459 * We don't use this, so we just assert that it isn't used. The
6460 * PIPE_CONTROL instruction page indicates that they intended this
6461 * as a debug feature and don't think it is useful in production,
6462 * but it may actually be usable, should we ever want to.
6464 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
6466 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
6467 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
6468 /* Project: All / Arguments:
6470 * - Generic Media State Clear [16]
6471 * - Indirect State Pointers Disable [16]
6473 * "Requires stall bit ([20] of DW1) set."
6475 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
6476 * State Clear) says:
6478 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6479 * programmed prior to programming a PIPECONTROL command with "Media
6480 * State Clear" set in GPGPU mode of operation"
6482 * This is a subset of the earlier rule, so there's nothing to do.
6484 flags
|= PIPE_CONTROL_CS_STALL
;
6487 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
6488 /* Project: All / Argument: Store Data Index
6490 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6493 * For now, we just assert that the caller does this. We might want to
6494 * automatically add a write to the workaround BO...
6496 assert(non_lri_post_sync_flags
!= 0);
6499 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
6500 /* Project: All / Argument: Sync GFDT
6502 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6503 * than '0' or 0x2520[13] must be set."
6505 * For now, we just assert that the caller does this.
6507 assert(non_lri_post_sync_flags
!= 0);
6510 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
6511 /* Project: IVB+ / Argument: TLB inv
6513 * "Requires stall bit ([20] of DW1) set."
6515 * Also, from the PIPE_CONTROL instruction table:
6518 * Post Sync Operation or CS stall must be set to ensure a TLB
6519 * invalidation occurs. Otherwise no cycle will occur to the TLB
6520 * cache to invalidate."
6522 * This is not a subset of the earlier rule, so there's nothing to do.
6524 flags
|= PIPE_CONTROL_CS_STALL
;
6527 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
6528 /* TODO: The big Skylake GT4 post sync op workaround */
6531 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
6533 if (IS_COMPUTE_PIPELINE(batch
)) {
6534 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
6535 /* Project: SKL+ / Argument: Tex Invalidate
6536 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
6538 flags
|= PIPE_CONTROL_CS_STALL
;
6541 if (GEN_GEN
== 8 && (post_sync_flags
||
6542 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
6543 PIPE_CONTROL_DEPTH_STALL
|
6544 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6545 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6546 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
6547 /* Project: BDW / Arguments:
6549 * - LRI Post Sync Operation [23]
6550 * - Post Sync Op [15:14]
6552 * - Depth Stall [13]
6553 * - Render Target Cache Flush [12]
6554 * - Depth Cache Flush [0]
6555 * - DC Flush Enable [5]
6557 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
6560 flags
|= PIPE_CONTROL_CS_STALL
;
6562 /* Also, from the PIPE_CONTROL instruction table, bit 20:
6565 * This bit must be always set when PIPE_CONTROL command is
6566 * programmed by GPGPU and MEDIA workloads, except for the cases
6567 * when only Read Only Cache Invalidation bits are set (State
6568 * Cache Invalidation Enable, Instruction cache Invalidation
6569 * Enable, Texture Cache Invalidation Enable, Constant Cache
6570 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
6571 * need not implemented when FF_DOP_CG is disable via "Fixed
6572 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
6574 * It sounds like we could avoid CS stalls in some cases, but we
6575 * don't currently bother. This list isn't exactly the list above,
6581 /* "Stall" workarounds ----------------------------------------------
6582 * These have to come after the earlier ones because we may have added
6583 * some additional CS stalls above.
6586 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
6587 /* Project: PRE-SKL, VLV, CHV
6589 * "[All Stepping][All SKUs]:
6591 * One of the following must also be set:
6593 * - Render Target Cache Flush Enable ([12] of DW1)
6594 * - Depth Cache Flush Enable ([0] of DW1)
6595 * - Stall at Pixel Scoreboard ([1] of DW1)
6596 * - Depth Stall ([13] of DW1)
6597 * - Post-Sync Operation ([13] of DW1)
6598 * - DC Flush Enable ([5] of DW1)"
6600 * If we don't already have one of those bits set, we choose to add
6601 * "Stall at Pixel Scoreboard". Some of the other bits require a
6602 * CS stall as a workaround (see above), which would send us into
6603 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
6604 * appears to be safe, so we choose that.
6606 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6607 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6608 PIPE_CONTROL_WRITE_IMMEDIATE
|
6609 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6610 PIPE_CONTROL_WRITE_TIMESTAMP
|
6611 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
6612 PIPE_CONTROL_DEPTH_STALL
|
6613 PIPE_CONTROL_DATA_CACHE_FLUSH
;
6614 if (!(flags
& wa_bits
))
6615 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6618 /* Emit --------------------------------------------------------------- */
6620 if (INTEL_DEBUG
& DEBUG_PIPE_CONTROL
) {
6622 " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64
"]: %s\n",
6623 (flags
& PIPE_CONTROL_FLUSH_ENABLE
) ? "PipeCon " : "",
6624 (flags
& PIPE_CONTROL_CS_STALL
) ? "CS " : "",
6625 (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) ? "Scoreboard " : "",
6626 (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) ? "VF " : "",
6627 (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) ? "RT " : "",
6628 (flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
) ? "Const " : "",
6629 (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
) ? "TC " : "",
6630 (flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
) ? "DC " : "",
6631 (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
) ? "ZFlush " : "",
6632 (flags
& PIPE_CONTROL_DEPTH_STALL
) ? "ZStall " : "",
6633 (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
) ? "State " : "",
6634 (flags
& PIPE_CONTROL_TLB_INVALIDATE
) ? "TLB " : "",
6635 (flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
) ? "Inst " : "",
6636 (flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
) ? "MediaClear " : "",
6637 (flags
& PIPE_CONTROL_NOTIFY_ENABLE
) ? "Notify " : "",
6638 (flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) ?
6640 (flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
) ?
6642 (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
) ? "WriteImm " : "",
6643 (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
) ? "WriteZCount " : "",
6644 (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
) ? "WriteTimestamp " : "",
6648 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
6649 pc
.LRIPostSyncOperation
= NoLRIOperation
;
6650 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
6651 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
6652 pc
.StoreDataIndex
= 0;
6653 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
6654 pc
.GlobalSnapshotCountReset
=
6655 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
6656 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
6657 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
6658 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6659 pc
.RenderTargetCacheFlushEnable
=
6660 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
6661 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
6662 pc
.StateCacheInvalidationEnable
=
6663 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
6664 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
6665 pc
.ConstantCacheInvalidationEnable
=
6666 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
6667 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
6668 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
6669 pc
.InstructionCacheInvalidateEnable
=
6670 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
6671 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
6672 pc
.IndirectStatePointersDisable
=
6673 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
6674 pc
.TextureCacheInvalidationEnable
=
6675 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
6676 pc
.Address
= rw_bo(bo
, offset
);
6677 pc
.ImmediateData
= imm
;
6682 genX(emit_urb_setup
)(struct iris_context
*ice
,
6683 struct iris_batch
*batch
,
6684 const unsigned size
[4],
6685 bool tess_present
, bool gs_present
)
6687 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6688 const unsigned push_size_kB
= 32;
6689 unsigned entries
[4];
6692 ice
->shaders
.last_vs_entry_size
= size
[MESA_SHADER_VERTEX
];
6694 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
6695 1024 * ice
->shaders
.urb_size
,
6696 tess_present
, gs_present
,
6697 size
, entries
, start
);
6699 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
6700 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
6701 urb
._3DCommandSubOpcode
+= i
;
6702 urb
.VSURBStartingAddress
= start
[i
];
6703 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
6704 urb
.VSNumberofURBEntries
= entries
[i
];
6711 * Preemption on Gen9 has to be enabled or disabled in various cases.
6713 * See these workarounds for preemption:
6714 * - WaDisableMidObjectPreemptionForGSLineStripAdj
6715 * - WaDisableMidObjectPreemptionForTrifanOrPolygon
6716 * - WaDisableMidObjectPreemptionForLineLoop
6719 * We don't put this in the vtable because it's only used on Gen9.
6722 gen9_toggle_preemption(struct iris_context
*ice
,
6723 struct iris_batch
*batch
,
6724 const struct pipe_draw_info
*draw
)
6726 struct iris_genx_state
*genx
= ice
->state
.genx
;
6727 bool object_preemption
= true;
6729 /* WaDisableMidObjectPreemptionForGSLineStripAdj
6731 * "WA: Disable mid-draw preemption when draw-call is a linestrip_adj
6732 * and GS is enabled."
6734 if (draw
->mode
== PIPE_PRIM_LINE_STRIP_ADJACENCY
&&
6735 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
6736 object_preemption
= false;
6738 /* WaDisableMidObjectPreemptionForTrifanOrPolygon
6740 * "TriFan miscompare in Execlist Preemption test. Cut index that is
6741 * on a previous context. End the previous, the resume another context
6742 * with a tri-fan or polygon, and the vertex count is corrupted. If we
6743 * prempt again we will cause corruption.
6745 * WA: Disable mid-draw preemption when draw-call has a tri-fan."
6747 if (draw
->mode
== PIPE_PRIM_TRIANGLE_FAN
)
6748 object_preemption
= false;
6750 /* WaDisableMidObjectPreemptionForLineLoop
6752 * "VF Stats Counters Missing a vertex when preemption enabled.
6754 * WA: Disable mid-draw preemption when the draw uses a lineloop
6757 if (draw
->mode
== PIPE_PRIM_LINE_LOOP
)
6758 object_preemption
= false;
6762 * "VF is corrupting GAFS data when preempted on an instance boundary
6763 * and replayed with instancing enabled.
6765 * WA: Disable preemption when using instanceing."
6767 if (draw
->instance_count
> 1)
6768 object_preemption
= false;
6770 if (genx
->object_preemption
!= object_preemption
) {
6771 iris_enable_obj_preemption(batch
, object_preemption
);
6772 genx
->object_preemption
= object_preemption
;
6778 iris_lost_genx_state(struct iris_context
*ice
, struct iris_batch
*batch
)
6780 struct iris_genx_state
*genx
= ice
->state
.genx
;
6782 memset(genx
->last_index_buffer
, 0, sizeof(genx
->last_index_buffer
));
6786 iris_emit_mi_report_perf_count(struct iris_batch
*batch
,
6788 uint32_t offset_in_bytes
,
6791 iris_emit_cmd(batch
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
6792 mi_rpc
.MemoryAddress
= rw_bo(bo
, offset_in_bytes
);
6793 mi_rpc
.ReportID
= report_id
;
6798 * Update the pixel hashing modes that determine the balancing of PS threads
6799 * across subslices and slices.
6801 * \param width Width bound of the rendering area (already scaled down if \p
6802 * scale is greater than 1).
6803 * \param height Height bound of the rendering area (already scaled down if \p
6804 * scale is greater than 1).
6805 * \param scale The number of framebuffer samples that could potentially be
6806 * affected by an individual channel of the PS thread. This is
6807 * typically one for single-sampled rendering, but for operations
6808 * like CCS resolves and fast clears a single PS invocation may
6809 * update a huge number of pixels, in which case a finer
6810 * balancing is desirable in order to maximally utilize the
6811 * bandwidth available. UINT_MAX can be used as shorthand for
6812 * "finest hashing mode available".
6815 genX(emit_hashing_mode
)(struct iris_context
*ice
, struct iris_batch
*batch
,
6816 unsigned width
, unsigned height
, unsigned scale
)
6819 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6820 const unsigned slice_hashing
[] = {
6821 /* Because all Gen9 platforms with more than one slice require
6822 * three-way subslice hashing, a single "normal" 16x16 slice hashing
6823 * block is guaranteed to suffer from substantial imbalance, with one
6824 * subslice receiving twice as much work as the other two in the
6827 * The performance impact of that would be particularly severe when
6828 * three-way hashing is also in use for slice balancing (which is the
6829 * case for all Gen9 GT4 platforms), because one of the slices
6830 * receives one every three 16x16 blocks in either direction, which
6831 * is roughly the periodicity of the underlying subslice imbalance
6832 * pattern ("roughly" because in reality the hardware's
6833 * implementation of three-way hashing doesn't do exact modulo 3
6834 * arithmetic, which somewhat decreases the magnitude of this effect
6835 * in practice). This leads to a systematic subslice imbalance
6836 * within that slice regardless of the size of the primitive. The
6837 * 32x32 hashing mode guarantees that the subslice imbalance within a
6838 * single slice hashing block is minimal, largely eliminating this
6842 /* Finest slice hashing mode available. */
6845 const unsigned subslice_hashing
[] = {
6846 /* 16x16 would provide a slight cache locality benefit especially
6847 * visible in the sampler L1 cache efficiency of low-bandwidth
6848 * non-LLC platforms, but it comes at the cost of greater subslice
6849 * imbalance for primitives of dimensions approximately intermediate
6850 * between 16x4 and 16x16.
6853 /* Finest subslice hashing mode available. */
6856 /* Dimensions of the smallest hashing block of a given hashing mode. If
6857 * the rendering area is smaller than this there can't possibly be any
6858 * benefit from switching to this mode, so we optimize out the
6861 const unsigned min_size
[][2] = {
6865 const unsigned idx
= scale
> 1;
6867 if (width
> min_size
[idx
][0] || height
> min_size
[idx
][1]) {
6870 iris_pack_state(GENX(GT_MODE
), >_mode
, reg
) {
6871 reg
.SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0);
6872 reg
.SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0);
6873 reg
.SubsliceHashing
= subslice_hashing
[idx
];
6874 reg
.SubsliceHashingMask
= -1;
6877 iris_emit_raw_pipe_control(batch
,
6878 "workaround: CS stall before GT_MODE LRI",
6879 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
6880 PIPE_CONTROL_CS_STALL
,
6883 iris_emit_lri(batch
, GT_MODE
, gt_mode
);
6885 ice
->state
.current_hash_scale
= scale
;
6891 genX(init_state
)(struct iris_context
*ice
)
6893 struct pipe_context
*ctx
= &ice
->ctx
;
6894 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
6896 ctx
->create_blend_state
= iris_create_blend_state
;
6897 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
6898 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
6899 ctx
->create_sampler_state
= iris_create_sampler_state
;
6900 ctx
->create_sampler_view
= iris_create_sampler_view
;
6901 ctx
->create_surface
= iris_create_surface
;
6902 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
6903 ctx
->bind_blend_state
= iris_bind_blend_state
;
6904 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
6905 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
6906 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
6907 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
6908 ctx
->delete_blend_state
= iris_delete_state
;
6909 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
6910 ctx
->delete_rasterizer_state
= iris_delete_state
;
6911 ctx
->delete_sampler_state
= iris_delete_state
;
6912 ctx
->delete_vertex_elements_state
= iris_delete_state
;
6913 ctx
->set_blend_color
= iris_set_blend_color
;
6914 ctx
->set_clip_state
= iris_set_clip_state
;
6915 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
6916 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
6917 ctx
->set_shader_images
= iris_set_shader_images
;
6918 ctx
->set_sampler_views
= iris_set_sampler_views
;
6919 ctx
->set_tess_state
= iris_set_tess_state
;
6920 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
6921 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
6922 ctx
->set_sample_mask
= iris_set_sample_mask
;
6923 ctx
->set_scissor_states
= iris_set_scissor_states
;
6924 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
6925 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
6926 ctx
->set_viewport_states
= iris_set_viewport_states
;
6927 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
6928 ctx
->surface_destroy
= iris_surface_destroy
;
6929 ctx
->draw_vbo
= iris_draw_vbo
;
6930 ctx
->launch_grid
= iris_launch_grid
;
6931 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
6932 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
6933 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
6935 ice
->vtbl
.destroy_state
= iris_destroy_state
;
6936 ice
->vtbl
.init_render_context
= iris_init_render_context
;
6937 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
6938 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
6939 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
6940 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
6941 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
6942 ice
->vtbl
.emit_mi_report_perf_count
= iris_emit_mi_report_perf_count
;
6943 ice
->vtbl
.rebind_buffer
= iris_rebind_buffer
;
6944 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
6945 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
6946 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
6947 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
6948 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
6949 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
6950 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
6951 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
6952 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
6953 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
6954 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
6955 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
6956 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
6957 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
6958 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
6959 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
6960 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
6961 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
6962 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
6963 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
6964 ice
->vtbl
.mocs
= mocs
;
6965 ice
->vtbl
.lost_genx_state
= iris_lost_genx_state
;
6967 ice
->state
.dirty
= ~0ull;
6969 ice
->state
.statistics_counters_enabled
= true;
6971 ice
->state
.sample_mask
= 0xffff;
6972 ice
->state
.num_viewports
= 1;
6973 ice
->state
.prim_mode
= PIPE_PRIM_MAX
;
6974 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
6975 ice
->draw
.derived_params
.drawid
= -1;
6977 /* Make a 1x1x1 null surface for unbound textures */
6978 void *null_surf_map
=
6979 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
6980 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
6981 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
6982 ice
->state
.unbound_tex
.offset
+=
6983 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
6985 /* Default all scissor rectangles to be empty regions. */
6986 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
6987 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
6988 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,