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20 * DEALINGS IN THE SOFTWARE.
26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_dual_blend.h"
92 #include "util/u_inlines.h"
93 #include "util/format/u_format.h"
94 #include "util/u_framebuffer.h"
95 #include "util/u_transfer.h"
96 #include "util/u_upload_mgr.h"
97 #include "util/u_viewport.h"
98 #include "util/u_memory.h"
99 #include "drm-uapi/i915_drm.h"
101 #include "intel/compiler/brw_compiler.h"
102 #include "intel/common/gen_aux_map.h"
103 #include "intel/common/gen_l3_config.h"
104 #include "intel/common/gen_sample_positions.h"
105 #include "iris_batch.h"
106 #include "iris_context.h"
107 #include "iris_defines.h"
108 #include "iris_pipe.h"
109 #include "iris_resource.h"
111 #include "iris_genx_macros.h"
112 #include "intel/common/gen_guardband.h"
115 * Statically assert that PIPE_* enums match the hardware packets.
116 * (As long as they match, we don't need to translate them.)
118 UNUSED
static void pipe_asserts()
120 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
122 /* pipe_logicop happens to match the hardware. */
123 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
124 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
125 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
126 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
127 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
128 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
129 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
130 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
131 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
132 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
133 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
134 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
135 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
136 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
137 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
138 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
140 /* pipe_blend_func happens to match the hardware. */
141 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
142 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
143 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
144 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
145 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
146 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
147 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
148 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
149 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
150 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
151 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
152 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
153 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
161 /* pipe_blend_func happens to match the hardware. */
162 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
163 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
164 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
165 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
166 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
168 /* pipe_stencil_op happens to match the hardware. */
169 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
170 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
171 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
172 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
173 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
174 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
175 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
176 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
178 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
179 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
180 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
185 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
187 static const unsigned map
[] = {
188 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
189 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
190 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
191 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
192 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
193 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
194 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
195 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
196 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
197 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
198 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
199 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
200 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
201 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
202 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
205 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
209 translate_compare_func(enum pipe_compare_func pipe_func
)
211 static const unsigned map
[] = {
212 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
213 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
214 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
215 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
216 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
217 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
218 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
219 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
221 return map
[pipe_func
];
225 translate_shadow_func(enum pipe_compare_func pipe_func
)
227 /* Gallium specifies the result of shadow comparisons as:
229 * 1 if ref <op> texel,
234 * 0 if texel <op> ref,
237 * So we need to flip the operator and also negate.
239 static const unsigned map
[] = {
240 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
241 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
242 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
243 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
244 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
245 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
246 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
247 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
249 return map
[pipe_func
];
253 translate_cull_mode(unsigned pipe_face
)
255 static const unsigned map
[4] = {
256 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
257 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
258 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
259 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
261 return map
[pipe_face
];
265 translate_fill_mode(unsigned pipe_polymode
)
267 static const unsigned map
[4] = {
268 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
269 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
270 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
271 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
273 return map
[pipe_polymode
];
277 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
279 static const unsigned map
[] = {
280 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
281 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
282 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
284 return map
[pipe_mip
];
288 translate_wrap(unsigned pipe_wrap
)
290 static const unsigned map
[] = {
291 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
292 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
293 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
294 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
295 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
296 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
298 /* These are unsupported. */
299 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
300 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
302 return map
[pipe_wrap
];
306 * Allocate space for some indirect state.
308 * Return a pointer to the map (to fill it out) and a state ref (for
309 * referring to the state in GPU commands).
312 upload_state(struct u_upload_mgr
*uploader
,
313 struct iris_state_ref
*ref
,
318 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
323 * Stream out temporary/short-lived state.
325 * This allocates space, pins the BO, and includes the BO address in the
326 * returned offset (which works because all state lives in 32-bit memory
330 stream_state(struct iris_batch
*batch
,
331 struct u_upload_mgr
*uploader
,
332 struct pipe_resource
**out_res
,
335 uint32_t *out_offset
)
339 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
341 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
342 iris_use_pinned_bo(batch
, bo
, false);
344 iris_record_state_size(batch
->state_sizes
,
345 bo
->gtt_offset
+ *out_offset
, size
);
347 *out_offset
+= iris_bo_offset_from_base_address(bo
);
353 * stream_state() + memcpy.
356 emit_state(struct iris_batch
*batch
,
357 struct u_upload_mgr
*uploader
,
358 struct pipe_resource
**out_res
,
365 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
368 memcpy(map
, data
, size
);
374 * Did field 'x' change between 'old_cso' and 'new_cso'?
376 * (If so, we may want to set some dirty flags.)
378 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
379 #define cso_changed_memcmp(x) \
380 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
383 flush_before_state_base_change(struct iris_batch
*batch
)
385 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
387 /* Flush before emitting STATE_BASE_ADDRESS.
389 * This isn't documented anywhere in the PRM. However, it seems to be
390 * necessary prior to changing the surface state base adress. We've
391 * seen issues in Vulkan where we get GPU hangs when using multi-level
392 * command buffers which clear depth, reset state base address, and then
395 * Normally, in GL, we would trust the kernel to do sufficient stalls
396 * and flushes prior to executing our batch. However, it doesn't seem
397 * as if the kernel's flushing is always sufficient and we don't want to
400 * We make this an end-of-pipe sync instead of a normal flush because we
401 * do not know the current status of the GPU. On Haswell at least,
402 * having a fast-clear operation in flight at the same time as a normal
403 * rendering operation can cause hangs. Since the kernel's flushing is
404 * insufficient, we need to ensure that any rendering operations from
405 * other processes are definitely complete before we try to do our own
406 * rendering. It's a bit of a big hammer but it appears to work.
408 iris_emit_end_of_pipe_sync(batch
,
409 "change STATE_BASE_ADDRESS (flushes)",
410 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
411 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
412 PIPE_CONTROL_DATA_CACHE_FLUSH
|
413 /* GEN:BUG:1606662791:
415 * Software must program PIPE_CONTROL command
416 * with "HDC Pipeline Flush" prior to
417 * programming of the below two non-pipeline
419 * * STATE_BASE_ADDRESS
420 * * 3DSTATE_BINDING_TABLE_POOL_ALLOC
422 ((GEN_GEN
== 12 && devinfo
->revision
== 0 /* A0 */ ?
423 PIPE_CONTROL_FLUSH_HDC
: 0)));
427 flush_after_state_base_change(struct iris_batch
*batch
)
429 /* After re-setting the surface state base address, we have to do some
430 * cache flusing so that the sampler engine will pick up the new
431 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
432 * Shared Function > 3D Sampler > State > State Caching (page 96):
434 * Coherency with system memory in the state cache, like the texture
435 * cache is handled partially by software. It is expected that the
436 * command stream or shader will issue Cache Flush operation or
437 * Cache_Flush sampler message to ensure that the L1 cache remains
438 * coherent with system memory.
442 * Whenever the value of the Dynamic_State_Base_Addr,
443 * Surface_State_Base_Addr are altered, the L1 state cache must be
444 * invalidated to ensure the new surface or sampler state is fetched
445 * from system memory.
447 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
448 * which, according the PIPE_CONTROL instruction documentation in the
451 * Setting this bit is independent of any other bit in this packet.
452 * This bit controls the invalidation of the L1 and L2 state caches
453 * at the top of the pipe i.e. at the parsing time.
455 * Unfortunately, experimentation seems to indicate that state cache
456 * invalidation through a PIPE_CONTROL does nothing whatsoever in
457 * regards to surface state and binding tables. In stead, it seems that
458 * invalidating the texture cache is what is actually needed.
460 * XXX: As far as we have been able to determine through
461 * experimentation, shows that flush the texture cache appears to be
462 * sufficient. The theory here is that all of the sampling/rendering
463 * units cache the binding table in the texture cache. However, we have
464 * yet to be able to actually confirm this.
466 iris_emit_end_of_pipe_sync(batch
,
467 "change STATE_BASE_ADDRESS (invalidates)",
468 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
469 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
470 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
474 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
476 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
477 lri
.RegisterOffset
= reg
;
481 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
484 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
486 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
487 lrr
.SourceRegisterAddress
= src
;
488 lrr
.DestinationRegisterAddress
= dst
;
493 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
496 _iris_emit_lrr(batch
, dst
, src
);
500 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
503 _iris_emit_lrr(batch
, dst
, src
);
504 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
508 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
511 _iris_emit_lri(batch
, reg
, val
);
515 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
518 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
519 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
523 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
526 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
527 struct iris_bo
*bo
, uint32_t offset
)
529 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
530 lrm
.RegisterAddress
= reg
;
531 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
536 * Load a 64-bit value from a buffer into a MMIO register via
537 * two MI_LOAD_REGISTER_MEM commands.
540 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
541 struct iris_bo
*bo
, uint32_t offset
)
543 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
544 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
548 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
549 struct iris_bo
*bo
, uint32_t offset
,
552 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
553 srm
.RegisterAddress
= reg
;
554 srm
.MemoryAddress
= rw_bo(bo
, offset
);
555 srm
.PredicateEnable
= predicated
;
560 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
561 struct iris_bo
*bo
, uint32_t offset
,
564 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
565 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
569 iris_store_data_imm32(struct iris_batch
*batch
,
570 struct iris_bo
*bo
, uint32_t offset
,
573 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
574 sdi
.Address
= rw_bo(bo
, offset
);
575 sdi
.ImmediateData
= imm
;
580 iris_store_data_imm64(struct iris_batch
*batch
,
581 struct iris_bo
*bo
, uint32_t offset
,
584 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
585 * 2 in genxml but it's actually variable length and we need 5 DWords.
587 void *map
= iris_get_command_space(batch
, 4 * 5);
588 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
589 sdi
.DWordLength
= 5 - 2;
590 sdi
.Address
= rw_bo(bo
, offset
);
591 sdi
.ImmediateData
= imm
;
596 iris_copy_mem_mem(struct iris_batch
*batch
,
597 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
598 struct iris_bo
*src_bo
, uint32_t src_offset
,
601 /* MI_COPY_MEM_MEM operates on DWords. */
602 assert(bytes
% 4 == 0);
603 assert(dst_offset
% 4 == 0);
604 assert(src_offset
% 4 == 0);
606 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
607 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
608 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
609 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
615 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
617 #if GEN_GEN >= 8 && GEN_GEN < 10
618 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
620 * Software must clear the COLOR_CALC_STATE Valid field in
621 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
622 * with Pipeline Select set to GPGPU.
624 * The internal hardware docs recommend the same workaround for Gen9
627 if (pipeline
== GPGPU
)
628 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
632 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
633 * PIPELINE_SELECT [DevBWR+]":
637 * Software must ensure all the write caches are flushed through a
638 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
639 * command to invalidate read only caches prior to programming
640 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
642 iris_emit_pipe_control_flush(batch
,
643 "workaround: PIPELINE_SELECT flushes (1/2)",
644 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
645 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
646 PIPE_CONTROL_DATA_CACHE_FLUSH
|
647 PIPE_CONTROL_CS_STALL
);
649 iris_emit_pipe_control_flush(batch
,
650 "workaround: PIPELINE_SELECT flushes (2/2)",
651 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
652 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
653 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
654 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
656 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
660 sel
.PipelineSelection
= pipeline
;
665 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
670 * "This chicken bit works around a hardware issue with barrier
671 * logic encountered when switching between GPGPU and 3D pipelines.
672 * To workaround the issue, this mode bit should be set after a
673 * pipeline is selected."
676 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
677 reg
.GLKBarrierMode
= value
;
678 reg
.GLKBarrierModeMask
= 1;
680 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
685 init_state_base_address(struct iris_batch
*batch
)
687 uint32_t mocs
= batch
->screen
->isl_dev
.mocs
.internal
;
688 flush_before_state_base_change(batch
);
690 /* We program most base addresses once at context initialization time.
691 * Each base address points at a 4GB memory zone, and never needs to
692 * change. See iris_bufmgr.h for a description of the memory zones.
694 * The one exception is Surface State Base Address, which needs to be
695 * updated occasionally. See iris_binder.c for the details there.
697 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
698 sba
.GeneralStateMOCS
= mocs
;
699 sba
.StatelessDataPortAccessMOCS
= mocs
;
700 sba
.DynamicStateMOCS
= mocs
;
701 sba
.IndirectObjectMOCS
= mocs
;
702 sba
.InstructionMOCS
= mocs
;
703 sba
.SurfaceStateMOCS
= mocs
;
705 sba
.GeneralStateBaseAddressModifyEnable
= true;
706 sba
.DynamicStateBaseAddressModifyEnable
= true;
707 sba
.IndirectObjectBaseAddressModifyEnable
= true;
708 sba
.InstructionBaseAddressModifyEnable
= true;
709 sba
.GeneralStateBufferSizeModifyEnable
= true;
710 sba
.DynamicStateBufferSizeModifyEnable
= true;
712 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
713 sba
.BindlessSurfaceStateMOCS
= mocs
;
715 sba
.IndirectObjectBufferSizeModifyEnable
= true;
716 sba
.InstructionBuffersizeModifyEnable
= true;
718 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
719 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
721 sba
.GeneralStateBufferSize
= 0xfffff;
722 sba
.IndirectObjectBufferSize
= 0xfffff;
723 sba
.InstructionBufferSize
= 0xfffff;
724 sba
.DynamicStateBufferSize
= 0xfffff;
727 flush_after_state_base_change(batch
);
731 iris_emit_l3_config(struct iris_batch
*batch
,
732 const struct gen_l3_config
*cfg
)
737 #define L3_ALLOCATION_REG GENX(L3ALLOC)
738 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
740 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
741 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
744 iris_pack_state(L3_ALLOCATION_REG
, ®_val
, reg
) {
746 reg
.SLMEnable
= cfg
->n
[GEN_L3P_SLM
] > 0;
749 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
750 * in L3CNTLREG register. The default setting of the bit is not the
751 * desirable behavior.
753 reg
.ErrorDetectionBehaviorControl
= true;
754 reg
.UseFullWays
= true;
756 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
757 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
758 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
759 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
761 _iris_emit_lri(batch
, L3_ALLOCATION_REG_num
, reg_val
);
766 iris_enable_obj_preemption(struct iris_batch
*batch
, bool enable
)
770 /* A fixed function pipe flush is required before modifying this field */
771 iris_emit_end_of_pipe_sync(batch
, enable
? "enable preemption"
772 : "disable preemption",
773 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
775 /* enable object level preemption */
776 iris_pack_state(GENX(CS_CHICKEN1
), ®_val
, reg
) {
777 reg
.ReplayMode
= enable
;
778 reg
.ReplayModeMask
= true;
780 iris_emit_lri(batch
, CS_CHICKEN1
, reg_val
);
786 iris_upload_slice_hashing_state(struct iris_batch
*batch
)
788 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
789 int subslices_delta
=
790 devinfo
->ppipe_subslices
[0] - devinfo
->ppipe_subslices
[1];
791 if (subslices_delta
== 0)
794 struct iris_context
*ice
= NULL
;
795 ice
= container_of(batch
, ice
, batches
[IRIS_BATCH_RENDER
]);
796 assert(&ice
->batches
[IRIS_BATCH_RENDER
] == batch
);
798 unsigned size
= GENX(SLICE_HASH_TABLE_length
) * 4;
799 uint32_t hash_address
;
800 struct pipe_resource
*tmp
= NULL
;
802 stream_state(batch
, ice
->state
.dynamic_uploader
, &tmp
,
803 size
, 64, &hash_address
);
804 pipe_resource_reference(&tmp
, NULL
);
806 struct GENX(SLICE_HASH_TABLE
) table0
= {
808 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
809 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
810 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
811 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
812 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
813 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
814 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
815 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
816 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
817 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
818 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
819 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
820 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
821 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
822 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
823 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }
827 struct GENX(SLICE_HASH_TABLE
) table1
= {
829 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
830 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
831 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
832 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
833 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
834 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
835 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
836 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
837 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
838 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
839 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
840 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
841 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
842 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
843 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
844 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }
848 const struct GENX(SLICE_HASH_TABLE
) *table
=
849 subslices_delta
< 0 ? &table0
: &table1
;
850 GENX(SLICE_HASH_TABLE_pack
)(NULL
, map
, table
);
852 iris_emit_cmd(batch
, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS
), ptr
) {
853 ptr
.SliceHashStatePointerValid
= true;
854 ptr
.SliceHashTableStatePointer
= hash_address
;
857 iris_emit_cmd(batch
, GENX(3DSTATE_3D_MODE
), mode
) {
858 mode
.SliceHashingTableEnable
= true;
864 iris_alloc_push_constants(struct iris_batch
*batch
)
866 /* For now, we set a static partitioning of the push constant area,
867 * assuming that all stages could be in use.
869 * TODO: Try lazily allocating the HS/DS/GS sections as needed, and
870 * see if that improves performance by offering more space to
871 * the VS/FS when those aren't in use. Also, try dynamically
872 * enabling/disabling it like i965 does. This would be more
873 * stalls and may not actually help; we don't know yet.
875 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
876 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
877 alloc
._3DCommandSubOpcode
= 18 + i
;
878 alloc
.ConstantBufferOffset
= 6 * i
;
879 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
886 init_aux_map_state(struct iris_batch
*batch
);
890 * Upload the initial GPU state for a render context.
892 * This sets some invariant state that needs to be programmed a particular
893 * way, but we never actually change.
896 iris_init_render_context(struct iris_batch
*batch
)
898 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
901 emit_pipeline_select(batch
, _3D
);
903 iris_emit_l3_config(batch
, batch
->screen
->l3_config_3d
);
905 init_state_base_address(batch
);
908 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
909 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
910 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
912 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
914 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
915 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
916 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
918 iris_emit_lri(batch
, INSTPM
, reg_val
);
922 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
923 reg
.FloatBlendOptimizationEnable
= true;
924 reg
.FloatBlendOptimizationEnableMask
= true;
925 reg
.PartialResolveDisableInVC
= true;
926 reg
.PartialResolveDisableInVCMask
= true;
928 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
930 if (devinfo
->is_geminilake
)
931 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
935 iris_pack_state(GENX(TCCNTLREG
), ®_val
, reg
) {
936 reg
.L3DataPartialWriteMergingEnable
= true;
937 reg
.ColorZPartialWriteMergingEnable
= true;
938 reg
.URBPartialWriteMergingEnable
= true;
939 reg
.TCDisable
= true;
941 iris_emit_lri(batch
, TCCNTLREG
, reg_val
);
943 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
944 reg
.HeaderlessMessageforPreemptableContexts
= 1;
945 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
947 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
949 /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
950 iris_pack_state(GENX(HALF_SLICE_CHICKEN7
), ®_val
, reg
) {
951 reg
.EnabledTexelOffsetPrecisionFix
= 1;
952 reg
.EnabledTexelOffsetPrecisionFixMask
= 1;
954 iris_emit_lri(batch
, HALF_SLICE_CHICKEN7
, reg_val
);
956 /* Hardware specification recommends disabling repacking for the
957 * compatibility with decompression mechanism in display controller.
959 if (devinfo
->disable_ccs_repack
) {
960 iris_pack_state(GENX(CACHE_MODE_0
), ®_val
, reg
) {
961 reg
.DisableRepackingforCompression
= true;
962 reg
.DisableRepackingforCompressionMask
= true;
964 iris_emit_lri(batch
, CACHE_MODE_0
, reg_val
);
967 iris_upload_slice_hashing_state(batch
);
970 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
971 * changing it dynamically. We set it to the maximum size here, and
972 * instead include the render target dimensions in the viewport, so
973 * viewport extents clipping takes care of pruning stray geometry.
975 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
976 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
977 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
980 /* Set the initial MSAA sample positions. */
981 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
982 GEN_SAMPLE_POS_1X(pat
._1xSample
);
983 GEN_SAMPLE_POS_2X(pat
._2xSample
);
984 GEN_SAMPLE_POS_4X(pat
._4xSample
);
985 GEN_SAMPLE_POS_8X(pat
._8xSample
);
987 GEN_SAMPLE_POS_16X(pat
._16xSample
);
991 /* Use the legacy AA line coverage computation. */
992 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
994 /* Disable chromakeying (it's for media) */
995 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
997 /* We want regular rendering, not special HiZ operations. */
998 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
1000 /* No polygon stippling offsets are necessary. */
1001 /* TODO: may need to set an offset for origin-UL framebuffers */
1002 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
1004 iris_alloc_push_constants(batch
);
1007 init_aux_map_state(batch
);
1012 iris_init_compute_context(struct iris_batch
*batch
)
1014 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
1016 /* GEN:BUG:1607854226:
1018 * Start with pipeline in 3D mode to set the STATE_BASE_ADDRESS.
1021 emit_pipeline_select(batch
, _3D
);
1023 emit_pipeline_select(batch
, GPGPU
);
1026 iris_emit_l3_config(batch
, batch
->screen
->l3_config_cs
);
1028 init_state_base_address(batch
);
1031 emit_pipeline_select(batch
, GPGPU
);
1035 if (devinfo
->is_geminilake
)
1036 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
1040 init_aux_map_state(batch
);
1045 struct iris_vertex_buffer_state
{
1046 /** The VERTEX_BUFFER_STATE hardware structure. */
1047 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
1049 /** The resource to source vertex data from. */
1050 struct pipe_resource
*resource
;
1055 struct iris_depth_buffer_state
{
1056 /* Depth/HiZ/Stencil related hardware packets. */
1057 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
1058 GENX(3DSTATE_STENCIL_BUFFER_length
) +
1059 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
1060 GENX(3DSTATE_CLEAR_PARAMS_length
) +
1061 GENX(MI_LOAD_REGISTER_IMM_length
) * 2];
1065 * Generation-specific context state (ice->state.genx->...).
1067 * Most state can go in iris_context directly, but these encode hardware
1068 * packets which vary by generation.
1070 struct iris_genx_state
{
1071 struct iris_vertex_buffer_state vertex_buffers
[33];
1072 uint32_t last_index_buffer
[GENX(3DSTATE_INDEX_BUFFER_length
)];
1074 struct iris_depth_buffer_state depth_buffer
;
1076 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
1079 bool pma_fix_enabled
;
1083 /* Is object level preemption enabled? */
1084 bool object_preemption
;
1089 struct brw_image_param image_param
[PIPE_MAX_SHADER_IMAGES
];
1091 } shaders
[MESA_SHADER_STAGES
];
1095 * The pipe->set_blend_color() driver hook.
1097 * This corresponds to our COLOR_CALC_STATE.
1100 iris_set_blend_color(struct pipe_context
*ctx
,
1101 const struct pipe_blend_color
*state
)
1103 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1105 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
1106 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
1107 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1111 * Gallium CSO for blend state (see pipe_blend_state).
1113 struct iris_blend_state
{
1114 /** Partial 3DSTATE_PS_BLEND */
1115 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
1117 /** Partial BLEND_STATE */
1118 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
1119 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
1121 bool alpha_to_coverage
; /* for shader key */
1123 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
1124 uint8_t blend_enables
;
1126 /** Bitfield of whether color writes are enabled for RT[i] */
1127 uint8_t color_write_enables
;
1129 /** Does RT[0] use dual color blending? */
1130 bool dual_color_blending
;
1133 static enum pipe_blendfactor
1134 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
1137 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
1138 return PIPE_BLENDFACTOR_ONE
;
1140 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
1141 return PIPE_BLENDFACTOR_ZERO
;
1148 * The pipe->create_blend_state() driver hook.
1150 * Translates a pipe_blend_state into iris_blend_state.
1153 iris_create_blend_state(struct pipe_context
*ctx
,
1154 const struct pipe_blend_state
*state
)
1156 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
1157 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
1159 cso
->blend_enables
= 0;
1160 cso
->color_write_enables
= 0;
1161 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
1163 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
1165 bool indep_alpha_blend
= false;
1167 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
1168 const struct pipe_rt_blend_state
*rt
=
1169 &state
->rt
[state
->independent_blend_enable
? i
: 0];
1171 enum pipe_blendfactor src_rgb
=
1172 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
1173 enum pipe_blendfactor src_alpha
=
1174 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
1175 enum pipe_blendfactor dst_rgb
=
1176 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
1177 enum pipe_blendfactor dst_alpha
=
1178 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
1180 if (rt
->rgb_func
!= rt
->alpha_func
||
1181 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
1182 indep_alpha_blend
= true;
1184 if (rt
->blend_enable
)
1185 cso
->blend_enables
|= 1u << i
;
1188 cso
->color_write_enables
|= 1u << i
;
1190 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
1191 be
.LogicOpEnable
= state
->logicop_enable
;
1192 be
.LogicOpFunction
= state
->logicop_func
;
1194 be
.PreBlendSourceOnlyClampEnable
= false;
1195 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
1196 be
.PreBlendColorClampEnable
= true;
1197 be
.PostBlendColorClampEnable
= true;
1199 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
1201 be
.ColorBlendFunction
= rt
->rgb_func
;
1202 be
.AlphaBlendFunction
= rt
->alpha_func
;
1203 be
.SourceBlendFactor
= src_rgb
;
1204 be
.SourceAlphaBlendFactor
= src_alpha
;
1205 be
.DestinationBlendFactor
= dst_rgb
;
1206 be
.DestinationAlphaBlendFactor
= dst_alpha
;
1208 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
1209 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
1210 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
1211 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
1213 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
1216 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
1217 /* pb.HasWriteableRT is filled in at draw time.
1218 * pb.AlphaTestEnable is filled in at draw time.
1220 * pb.ColorBufferBlendEnable is filled in at draw time so we can avoid
1221 * setting it when dual color blending without an appropriate shader.
1224 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1225 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1227 pb
.SourceBlendFactor
=
1228 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
1229 pb
.SourceAlphaBlendFactor
=
1230 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
1231 pb
.DestinationBlendFactor
=
1232 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
1233 pb
.DestinationAlphaBlendFactor
=
1234 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
1237 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
1238 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1239 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1240 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
1241 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
1242 bs
.ColorDitherEnable
= state
->dither
;
1243 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
1246 cso
->dual_color_blending
= util_blend_state_is_dual(state
, 0);
1252 * The pipe->bind_blend_state() driver hook.
1254 * Bind a blending CSO and flag related dirty bits.
1257 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
1259 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1260 struct iris_blend_state
*cso
= state
;
1262 ice
->state
.cso_blend
= cso
;
1263 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
1265 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1266 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1267 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1268 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
1271 ice
->state
.dirty
|= IRIS_DIRTY_PMA_FIX
;
1275 * Return true if the FS writes to any color outputs which are not disabled
1276 * via color masking.
1279 has_writeable_rt(const struct iris_blend_state
*cso_blend
,
1280 const struct shader_info
*fs_info
)
1285 unsigned rt_outputs
= fs_info
->outputs_written
>> FRAG_RESULT_DATA0
;
1287 if (fs_info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
))
1288 rt_outputs
= (1 << BRW_MAX_DRAW_BUFFERS
) - 1;
1290 return cso_blend
->color_write_enables
& rt_outputs
;
1294 * Gallium CSO for depth, stencil, and alpha testing state.
1296 struct iris_depth_stencil_alpha_state
{
1297 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
1298 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1301 uint32_t depth_bounds
[GENX(3DSTATE_DEPTH_BOUNDS_length
)];
1304 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
1305 struct pipe_alpha_state alpha
;
1307 /** Outbound to resolve and cache set tracking. */
1308 bool depth_writes_enabled
;
1309 bool stencil_writes_enabled
;
1311 /** Outbound to Gen8-9 PMA stall equations */
1312 bool depth_test_enabled
;
1316 * The pipe->create_depth_stencil_alpha_state() driver hook.
1318 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
1319 * testing state since we need pieces of it in a variety of places.
1322 iris_create_zsa_state(struct pipe_context
*ctx
,
1323 const struct pipe_depth_stencil_alpha_state
*state
)
1325 struct iris_depth_stencil_alpha_state
*cso
=
1326 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
1328 bool two_sided_stencil
= state
->stencil
[1].enabled
;
1330 cso
->alpha
= state
->alpha
;
1331 cso
->depth_writes_enabled
= state
->depth
.writemask
;
1332 cso
->depth_test_enabled
= state
->depth
.enabled
;
1333 cso
->stencil_writes_enabled
=
1334 state
->stencil
[0].writemask
!= 0 ||
1335 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1337 /* gallium frontends need to optimize away EQUAL writes for us. */
1338 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
1340 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
1341 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1342 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1343 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1344 wmds
.StencilTestFunction
=
1345 translate_compare_func(state
->stencil
[0].func
);
1346 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1347 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1348 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1349 wmds
.BackfaceStencilTestFunction
=
1350 translate_compare_func(state
->stencil
[1].func
);
1351 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1352 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1353 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1354 wmds
.StencilBufferWriteEnable
=
1355 state
->stencil
[0].writemask
!= 0 ||
1356 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1357 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1358 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1359 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1360 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1361 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1362 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1363 /* wmds.[Backface]StencilReferenceValue are merged later */
1365 wmds
.StencilReferenceValueModifyDisable
= true;
1370 iris_pack_command(GENX(3DSTATE_DEPTH_BOUNDS
), cso
->depth_bounds
, depth_bounds
) {
1371 depth_bounds
.DepthBoundsTestValueModifyDisable
= false;
1372 depth_bounds
.DepthBoundsTestEnableModifyDisable
= false;
1373 depth_bounds
.DepthBoundsTestEnable
= state
->depth
.bounds_test
;
1374 depth_bounds
.DepthBoundsTestMinValue
= state
->depth
.bounds_min
;
1375 depth_bounds
.DepthBoundsTestMaxValue
= state
->depth
.bounds_max
;
1383 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1385 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1388 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1390 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1391 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1392 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1395 if (cso_changed(alpha
.ref_value
))
1396 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1398 if (cso_changed(alpha
.enabled
))
1399 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1401 if (cso_changed(alpha
.func
))
1402 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1404 if (cso_changed(depth_writes_enabled
))
1405 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1407 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1408 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1411 if (cso_changed(depth_bounds
))
1412 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BOUNDS
;
1416 ice
->state
.cso_zsa
= new_cso
;
1417 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1418 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1419 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1422 ice
->state
.dirty
|= IRIS_DIRTY_PMA_FIX
;
1427 want_pma_fix(struct iris_context
*ice
)
1429 UNUSED
struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1430 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1431 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
1432 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
1433 const struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
1434 const struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
1435 const struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
1437 /* In very specific combinations of state, we can instruct Gen8-9 hardware
1438 * to avoid stalling at the pixel mask array. The state equations are
1439 * documented in these places:
1441 * - Gen8 Depth PMA Fix: CACHE_MODE_1::NP_PMA_FIX_ENABLE
1442 * - Gen9 Stencil PMA Fix: CACHE_MODE_0::STC PMA Optimization Enable
1444 * Both equations share some common elements:
1447 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
1448 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
1449 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
1450 * 3DSTATE_WM_HZ_OP::StencilBufferClear) &&
1453 * 3DSTATE_WM::ForceKillPix != ForceOff &&
1454 * (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
1455 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
1456 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
1457 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
1458 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable)
1460 * (Technically the stencil PMA treats ForceKillPix differently,
1461 * but I think this is a documentation oversight, and we don't
1462 * ever use it in this way, so it doesn't matter).
1465 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
1466 * 3DSTATE_RASTER::ForceSampleCount == NUMRASTSAMPLES_0 &&
1467 * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
1468 * 3DSTATE_DEPTH_BUFFER::HIZ Enable &&
1469 * 3DSTATE_WM::EDSC_Mode != EDSC_PREPS &&
1470 * 3DSTATE_PS_EXTRA::PixelShaderValid &&
1473 * These are always true:
1475 * 3DSTATE_RASTER::ForceSampleCount == NUMRASTSAMPLES_0
1476 * 3DSTATE_PS_EXTRA::PixelShaderValid
1478 * Also, we never use the normal drawing path for HiZ ops; these are true:
1480 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
1481 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
1482 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
1483 * 3DSTATE_WM_HZ_OP::StencilBufferClear)
1485 * This happens sometimes:
1487 * 3DSTATE_WM::ForceThreadDispatch != 1
1489 * However, we choose to ignore it as it either agrees with the signal
1490 * (dispatch was already enabled, so nothing out of the ordinary), or
1491 * there are no framebuffer attachments (so no depth or HiZ anyway,
1492 * meaning the PMA signal will already be disabled).
1498 struct iris_resource
*zres
, *sres
;
1499 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
, &zres
, &sres
);
1501 /* 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
1502 * 3DSTATE_DEPTH_BUFFER::HIZ Enable &&
1504 if (!zres
|| !iris_resource_level_has_hiz(zres
, cso_fb
->zsbuf
->u
.tex
.level
))
1507 /* 3DSTATE_WM::EDSC_Mode != EDSC_PREPS */
1508 if (wm_prog_data
->early_fragment_tests
)
1511 /* 3DSTATE_WM::ForceKillPix != ForceOff &&
1512 * (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
1513 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
1514 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
1515 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
1516 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable)
1518 bool killpixels
= wm_prog_data
->uses_kill
|| wm_prog_data
->uses_omask
||
1519 cso_blend
->alpha_to_coverage
|| cso_zsa
->alpha
.enabled
;
1521 /* The Gen8 depth PMA equation becomes:
1524 * 3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
1525 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE
1528 * 3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
1529 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
1530 * 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE
1534 * 3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable &&
1535 * ((killpixels && (depth_writes || stencil_writes)) ||
1536 * 3DSTATE_PS_EXTRA::PixelShaderComputedDepthMode != PSCDEPTH_OFF)
1539 if (!cso_zsa
->depth_test_enabled
)
1542 return wm_prog_data
->computed_depth_mode
!= PSCDEPTH_OFF
||
1543 (killpixels
&& (cso_zsa
->depth_writes_enabled
||
1544 (sres
&& cso_zsa
->stencil_writes_enabled
)));
1549 genX(update_pma_fix
)(struct iris_context
*ice
,
1550 struct iris_batch
*batch
,
1554 struct iris_genx_state
*genx
= ice
->state
.genx
;
1556 if (genx
->pma_fix_enabled
== enable
)
1559 genx
->pma_fix_enabled
= enable
;
1561 /* According to the Broadwell PIPE_CONTROL documentation, software should
1562 * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
1563 * prior to the LRI. If stencil buffer writes are enabled, then a Render * Cache Flush is also necessary.
1565 * The Gen9 docs say to use a depth stall rather than a command streamer
1566 * stall. However, the hardware seems to violently disagree. A full
1567 * command streamer stall seems to be needed in both cases.
1569 iris_emit_pipe_control_flush(batch
, "PMA fix change (1/2)",
1570 PIPE_CONTROL_CS_STALL
|
1571 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1572 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1575 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
1576 reg
.NPPMAFixEnable
= enable
;
1577 reg
.NPEarlyZFailsDisable
= enable
;
1578 reg
.NPPMAFixEnableMask
= true;
1579 reg
.NPEarlyZFailsDisableMask
= true;
1581 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
1583 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
1584 * Flush bits is often necessary. We do it regardless because it's easier.
1585 * The render cache flush is also necessary if stencil writes are enabled.
1587 * Again, the Gen9 docs give a different set of flushes but the Broadwell
1588 * flushes seem to work just as well.
1590 iris_emit_pipe_control_flush(batch
, "PMA fix change (1/2)",
1591 PIPE_CONTROL_DEPTH_STALL
|
1592 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1593 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1598 * Gallium CSO for rasterizer state.
1600 struct iris_rasterizer_state
{
1601 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1602 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1603 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1604 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1605 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1607 uint8_t num_clip_plane_consts
;
1608 bool clip_halfz
; /* for CC_VIEWPORT */
1609 bool depth_clip_near
; /* for CC_VIEWPORT */
1610 bool depth_clip_far
; /* for CC_VIEWPORT */
1611 bool flatshade
; /* for shader state */
1612 bool flatshade_first
; /* for stream output */
1613 bool clamp_fragment_color
; /* for shader state */
1614 bool light_twoside
; /* for shader state */
1615 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1616 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1617 bool line_stipple_enable
;
1618 bool poly_stipple_enable
;
1620 bool force_persample_interp
;
1621 bool conservative_rasterization
;
1622 bool fill_mode_point_or_line
;
1623 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1624 uint16_t sprite_coord_enable
;
1628 get_line_width(const struct pipe_rasterizer_state
*state
)
1630 float line_width
= state
->line_width
;
1632 /* From the OpenGL 4.4 spec:
1634 * "The actual width of non-antialiased lines is determined by rounding
1635 * the supplied width to the nearest integer, then clamping it to the
1636 * implementation-dependent maximum non-antialiased line width."
1638 if (!state
->multisample
&& !state
->line_smooth
)
1639 line_width
= roundf(state
->line_width
);
1641 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1642 /* For 1 pixel line thickness or less, the general anti-aliasing
1643 * algorithm gives up, and a garbage line is generated. Setting a
1644 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1645 * (one-pixel-wide), non-antialiased lines.
1647 * Lines rendered with zero Line Width are rasterized using the
1648 * "Grid Intersection Quantization" rules as specified by the
1649 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1658 * The pipe->create_rasterizer_state() driver hook.
1661 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1662 const struct pipe_rasterizer_state
*state
)
1664 struct iris_rasterizer_state
*cso
=
1665 malloc(sizeof(struct iris_rasterizer_state
));
1667 cso
->multisample
= state
->multisample
;
1668 cso
->force_persample_interp
= state
->force_persample_interp
;
1669 cso
->clip_halfz
= state
->clip_halfz
;
1670 cso
->depth_clip_near
= state
->depth_clip_near
;
1671 cso
->depth_clip_far
= state
->depth_clip_far
;
1672 cso
->flatshade
= state
->flatshade
;
1673 cso
->flatshade_first
= state
->flatshade_first
;
1674 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1675 cso
->light_twoside
= state
->light_twoside
;
1676 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1677 cso
->half_pixel_center
= state
->half_pixel_center
;
1678 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1679 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1680 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1681 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1682 cso
->conservative_rasterization
=
1683 state
->conservative_raster_mode
== PIPE_CONSERVATIVE_RASTER_POST_SNAP
;
1685 cso
->fill_mode_point_or_line
=
1686 state
->fill_front
== PIPE_POLYGON_MODE_LINE
||
1687 state
->fill_front
== PIPE_POLYGON_MODE_POINT
||
1688 state
->fill_back
== PIPE_POLYGON_MODE_LINE
||
1689 state
->fill_back
== PIPE_POLYGON_MODE_POINT
;
1691 if (state
->clip_plane_enable
!= 0)
1692 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1694 cso
->num_clip_plane_consts
= 0;
1696 float line_width
= get_line_width(state
);
1698 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1699 sf
.StatisticsEnable
= true;
1700 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1701 sf
.LineEndCapAntialiasingRegionWidth
=
1702 state
->line_smooth
? _10pixels
: _05pixels
;
1703 sf
.LastPixelEnable
= state
->line_last_pixel
;
1704 sf
.LineWidth
= line_width
;
1705 sf
.SmoothPointEnable
= (state
->point_smooth
|| state
->multisample
) &&
1706 !state
->point_quad_rasterization
;
1707 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1708 sf
.PointWidth
= state
->point_size
;
1710 if (state
->flatshade_first
) {
1711 sf
.TriangleFanProvokingVertexSelect
= 1;
1713 sf
.TriangleStripListProvokingVertexSelect
= 2;
1714 sf
.TriangleFanProvokingVertexSelect
= 2;
1715 sf
.LineStripListProvokingVertexSelect
= 1;
1719 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1720 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1721 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1722 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1723 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1724 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1725 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1726 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1727 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1728 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1729 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1730 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1731 rr
.SmoothPointEnable
= state
->point_smooth
;
1732 rr
.AntialiasingEnable
= state
->line_smooth
;
1733 rr
.ScissorRectangleEnable
= state
->scissor
;
1735 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1736 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1737 rr
.ConservativeRasterizationEnable
=
1738 cso
->conservative_rasterization
;
1740 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1744 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1745 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1746 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1748 cl
.EarlyCullEnable
= true;
1749 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1750 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1751 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1752 cl
.GuardbandClipTestEnable
= true;
1753 cl
.ClipEnable
= true;
1754 cl
.MinimumPointWidth
= 0.125;
1755 cl
.MaximumPointWidth
= 255.875;
1757 if (state
->flatshade_first
) {
1758 cl
.TriangleFanProvokingVertexSelect
= 1;
1760 cl
.TriangleStripListProvokingVertexSelect
= 2;
1761 cl
.TriangleFanProvokingVertexSelect
= 2;
1762 cl
.LineStripListProvokingVertexSelect
= 1;
1766 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1767 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1768 * filled in at draw time from the FS program.
1770 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1771 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1772 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1773 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1774 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1777 /* Remap from 0..255 back to 1..256 */
1778 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1780 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1781 if (state
->line_stipple_enable
) {
1782 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1783 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1784 line
.LineStippleRepeatCount
= line_stipple_factor
;
1792 * The pipe->bind_rasterizer_state() driver hook.
1794 * Bind a rasterizer CSO and flag related dirty bits.
1797 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1799 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1800 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1801 struct iris_rasterizer_state
*new_cso
= state
;
1804 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1805 if (cso_changed_memcmp(line_stipple
))
1806 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1808 if (cso_changed(half_pixel_center
))
1809 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1811 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1812 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1814 if (cso_changed(rasterizer_discard
))
1815 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1817 if (cso_changed(flatshade_first
))
1818 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1820 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1821 cso_changed(clip_halfz
))
1822 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1824 if (cso_changed(sprite_coord_enable
) ||
1825 cso_changed(sprite_coord_mode
) ||
1826 cso_changed(light_twoside
))
1827 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1829 if (cso_changed(conservative_rasterization
))
1830 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
1833 ice
->state
.cso_rast
= new_cso
;
1834 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1835 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1836 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1840 * Return true if the given wrap mode requires the border color to exist.
1842 * (We can skip uploading it if the sampler isn't going to use it.)
1845 wrap_mode_needs_border_color(unsigned wrap_mode
)
1847 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1851 * Gallium CSO for sampler state.
1853 struct iris_sampler_state
{
1854 union pipe_color_union border_color
;
1855 bool needs_border_color
;
1857 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1861 * The pipe->create_sampler_state() driver hook.
1863 * We fill out SAMPLER_STATE (except for the border color pointer), and
1864 * store that on the CPU. It doesn't make sense to upload it to a GPU
1865 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1866 * all bound sampler states to be in contiguous memor.
1869 iris_create_sampler_state(struct pipe_context
*ctx
,
1870 const struct pipe_sampler_state
*state
)
1872 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1877 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1878 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1880 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1881 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1882 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1884 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1886 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1887 wrap_mode_needs_border_color(wrap_t
) ||
1888 wrap_mode_needs_border_color(wrap_r
);
1890 float min_lod
= state
->min_lod
;
1891 unsigned mag_img_filter
= state
->mag_img_filter
;
1893 // XXX: explain this code ported from ilo...I don't get it at all...
1894 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1895 state
->min_lod
> 0.0f
) {
1897 mag_img_filter
= state
->min_img_filter
;
1900 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1901 samp
.TCXAddressControlMode
= wrap_s
;
1902 samp
.TCYAddressControlMode
= wrap_t
;
1903 samp
.TCZAddressControlMode
= wrap_r
;
1904 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1905 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1906 samp
.MinModeFilter
= state
->min_img_filter
;
1907 samp
.MagModeFilter
= mag_img_filter
;
1908 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1909 samp
.MaximumAnisotropy
= RATIO21
;
1911 if (state
->max_anisotropy
>= 2) {
1912 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1913 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1914 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1917 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1918 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1920 samp
.MaximumAnisotropy
=
1921 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1924 /* Set address rounding bits if not using nearest filtering. */
1925 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1926 samp
.UAddressMinFilterRoundingEnable
= true;
1927 samp
.VAddressMinFilterRoundingEnable
= true;
1928 samp
.RAddressMinFilterRoundingEnable
= true;
1931 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1932 samp
.UAddressMagFilterRoundingEnable
= true;
1933 samp
.VAddressMagFilterRoundingEnable
= true;
1934 samp
.RAddressMagFilterRoundingEnable
= true;
1937 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1938 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1940 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1942 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1943 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1944 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1945 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1947 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1954 * The pipe->bind_sampler_states() driver hook.
1957 iris_bind_sampler_states(struct pipe_context
*ctx
,
1958 enum pipe_shader_type p_stage
,
1959 unsigned start
, unsigned count
,
1962 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1963 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1964 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1966 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1970 for (int i
= 0; i
< count
; i
++) {
1971 if (shs
->samplers
[start
+ i
] != states
[i
]) {
1972 shs
->samplers
[start
+ i
] = states
[i
];
1978 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1982 * Upload the sampler states into a contiguous area of GPU memory, for
1983 * for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1985 * Also fill out the border color state pointers.
1988 iris_upload_sampler_states(struct iris_context
*ice
, gl_shader_stage stage
)
1990 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1991 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
1993 /* We assume gallium frontends will call pipe->bind_sampler_states()
1994 * if the program's number of textures changes.
1996 unsigned count
= info
? util_last_bit(info
->textures_used
) : 0;
2001 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
2002 * in the dynamic state memory zone, so we can point to it via the
2003 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
2005 unsigned size
= count
* 4 * GENX(SAMPLER_STATE_length
);
2007 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
, size
, 32);
2011 struct pipe_resource
*res
= shs
->sampler_table
.res
;
2012 struct iris_bo
*bo
= iris_resource_bo(res
);
2014 iris_record_state_size(ice
->state
.sizes
,
2015 bo
->gtt_offset
+ shs
->sampler_table
.offset
, size
);
2017 shs
->sampler_table
.offset
+= iris_bo_offset_from_base_address(bo
);
2019 /* Make sure all land in the same BO */
2020 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
2022 ice
->state
.need_border_colors
&= ~(1 << stage
);
2024 for (int i
= 0; i
< count
; i
++) {
2025 struct iris_sampler_state
*state
= shs
->samplers
[i
];
2026 struct iris_sampler_view
*tex
= shs
->textures
[i
];
2029 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
2030 } else if (!state
->needs_border_color
) {
2031 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
2033 ice
->state
.need_border_colors
|= 1 << stage
;
2035 /* We may need to swizzle the border color for format faking.
2036 * A/LA formats are faked as R/RG with 000R or R00G swizzles.
2037 * This means we need to move the border color's A channel into
2038 * the R or G channels so that those read swizzles will move it
2041 union pipe_color_union
*color
= &state
->border_color
;
2042 union pipe_color_union tmp
;
2044 enum pipe_format internal_format
= tex
->res
->internal_format
;
2046 if (util_format_is_alpha(internal_format
)) {
2047 unsigned char swz
[4] = {
2048 PIPE_SWIZZLE_W
, PIPE_SWIZZLE_0
,
2049 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
2051 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
2053 } else if (util_format_is_luminance_alpha(internal_format
) &&
2054 internal_format
!= PIPE_FORMAT_L8A8_SRGB
) {
2055 unsigned char swz
[4] = {
2056 PIPE_SWIZZLE_X
, PIPE_SWIZZLE_W
,
2057 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
2059 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
2064 /* Stream out the border color and merge the pointer. */
2065 uint32_t offset
= iris_upload_border_color(ice
, color
);
2067 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
2068 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
2069 dyns
.BorderColorPointer
= offset
;
2072 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
2073 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
2076 map
+= GENX(SAMPLER_STATE_length
);
2080 static enum isl_channel_select
2081 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
2084 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
2085 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
2086 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
2087 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
2088 case PIPE_SWIZZLE_1
: return SCS_ONE
;
2089 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
2090 default: unreachable("invalid swizzle");
2095 fill_buffer_surface_state(struct isl_device
*isl_dev
,
2096 struct iris_resource
*res
,
2098 enum isl_format format
,
2099 struct isl_swizzle swizzle
,
2103 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
2104 const unsigned cpp
= format
== ISL_FORMAT_RAW
? 1 : fmtl
->bpb
/ 8;
2106 /* The ARB_texture_buffer_specification says:
2108 * "The number of texels in the buffer texture's texel array is given by
2110 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
2112 * where <buffer_size> is the size of the buffer object, in basic
2113 * machine units and <components> and <base_type> are the element count
2114 * and base data type for elements, as specified in Table X.1. The
2115 * number of texels in the texel array is then clamped to the
2116 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
2118 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
2119 * so that when ISL divides by stride to obtain the number of texels, that
2120 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
2122 unsigned final_size
=
2123 MIN3(size
, res
->bo
->size
- res
->offset
- offset
,
2124 IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
2126 isl_buffer_fill_state(isl_dev
, map
,
2127 .address
= res
->bo
->gtt_offset
+ res
->offset
+ offset
,
2128 .size_B
= final_size
,
2132 .mocs
= iris_mocs(res
->bo
, isl_dev
));
2135 #define SURFACE_STATE_ALIGNMENT 64
2138 * Allocate several contiguous SURFACE_STATE structures, one for each
2139 * supported auxiliary surface mode. This only allocates the CPU-side
2140 * copy, they will need to be uploaded later after they're filled in.
2143 alloc_surface_states(struct iris_surface_state
*surf_state
,
2144 unsigned aux_usages
)
2146 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
2148 /* If this changes, update this to explicitly align pointers */
2149 STATIC_ASSERT(surf_size
== SURFACE_STATE_ALIGNMENT
);
2151 assert(aux_usages
!= 0);
2153 /* In case we're re-allocating them... */
2154 free(surf_state
->cpu
);
2156 surf_state
->num_states
= util_bitcount(aux_usages
);
2157 surf_state
->cpu
= calloc(surf_state
->num_states
, surf_size
);
2158 surf_state
->ref
.offset
= 0;
2159 pipe_resource_reference(&surf_state
->ref
.res
, NULL
);
2161 assert(surf_state
->cpu
);
2165 * Upload the CPU side SURFACE_STATEs into a GPU buffer.
2168 upload_surface_states(struct u_upload_mgr
*mgr
,
2169 struct iris_surface_state
*surf_state
)
2171 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
2172 const unsigned bytes
= surf_state
->num_states
* surf_size
;
2175 upload_state(mgr
, &surf_state
->ref
, bytes
, SURFACE_STATE_ALIGNMENT
);
2177 surf_state
->ref
.offset
+=
2178 iris_bo_offset_from_base_address(iris_resource_bo(surf_state
->ref
.res
));
2181 memcpy(map
, surf_state
->cpu
, bytes
);
2185 * Update resource addresses in a set of SURFACE_STATE descriptors,
2186 * and re-upload them if necessary.
2189 update_surface_state_addrs(struct u_upload_mgr
*mgr
,
2190 struct iris_surface_state
*surf_state
,
2193 if (surf_state
->bo_address
== bo
->gtt_offset
)
2196 STATIC_ASSERT(GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_start
) % 64 == 0);
2197 STATIC_ASSERT(GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_bits
) == 64);
2199 uint64_t *ss_addr
= (uint64_t *) &surf_state
->cpu
[GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_start
) / 32];
2201 /* First, update the CPU copies. We assume no other fields exist in
2202 * the QWord containing Surface Base Address.
2204 for (unsigned i
= 0; i
< surf_state
->num_states
; i
++) {
2205 *ss_addr
= *ss_addr
- surf_state
->bo_address
+ bo
->gtt_offset
;
2206 ss_addr
= ((void *) ss_addr
) + SURFACE_STATE_ALIGNMENT
;
2209 /* Next, upload the updated copies to a GPU buffer. */
2210 upload_surface_states(mgr
, surf_state
);
2212 surf_state
->bo_address
= bo
->gtt_offset
;
2219 * Return an ISL surface for use with non-coherent render target reads.
2221 * In a few complex cases, we can't use the SURFACE_STATE for normal render
2222 * target writes. We need to make a separate one for sampling which refers
2223 * to the single slice of the texture being read.
2226 get_rt_read_isl_surf(const struct gen_device_info
*devinfo
,
2227 struct iris_resource
*res
,
2228 enum pipe_texture_target target
,
2229 struct isl_view
*view
,
2230 uint32_t *offset_to_tile
,
2231 uint32_t *tile_x_sa
,
2232 uint32_t *tile_y_sa
,
2233 struct isl_surf
*surf
)
2237 const enum isl_dim_layout dim_layout
=
2238 iris_get_isl_dim_layout(devinfo
, res
->surf
.tiling
, target
);
2240 surf
->dim
= target_to_isl_surf_dim(target
);
2242 if (surf
->dim_layout
== dim_layout
)
2245 /* The layout of the specified texture target is not compatible with the
2246 * actual layout of the miptree structure in memory -- You're entering
2247 * dangerous territory, this can only possibly work if you only intended
2248 * to access a single level and slice of the texture, and the hardware
2249 * supports the tile offset feature in order to allow non-tile-aligned
2250 * base offsets, since we'll have to point the hardware to the first
2251 * texel of the level instead of relying on the usual base level/layer
2254 assert(view
->levels
== 1 && view
->array_len
== 1);
2255 assert(*tile_x_sa
== 0 && *tile_y_sa
== 0);
2257 *offset_to_tile
= iris_resource_get_tile_offsets(res
, view
->base_level
,
2258 view
->base_array_layer
,
2259 tile_x_sa
, tile_y_sa
);
2260 const unsigned l
= view
->base_level
;
2262 surf
->logical_level0_px
.width
= minify(surf
->logical_level0_px
.width
, l
);
2263 surf
->logical_level0_px
.height
= surf
->dim
<= ISL_SURF_DIM_1D
? 1 :
2264 minify(surf
->logical_level0_px
.height
, l
);
2265 surf
->logical_level0_px
.depth
= surf
->dim
<= ISL_SURF_DIM_2D
? 1 :
2266 minify(surf
->logical_level0_px
.depth
, l
);
2268 surf
->logical_level0_px
.array_len
= 1;
2270 surf
->dim_layout
= dim_layout
;
2272 view
->base_level
= 0;
2273 view
->base_array_layer
= 0;
2278 fill_surface_state(struct isl_device
*isl_dev
,
2280 struct iris_resource
*res
,
2281 struct isl_surf
*surf
,
2282 struct isl_view
*view
,
2284 uint32_t extra_main_offset
,
2288 struct isl_surf_fill_state_info f
= {
2291 .mocs
= iris_mocs(res
->bo
, isl_dev
),
2292 .address
= res
->bo
->gtt_offset
+ res
->offset
+ extra_main_offset
,
2293 .x_offset_sa
= tile_x_sa
,
2294 .y_offset_sa
= tile_y_sa
,
2297 assert(!iris_resource_unfinished_aux_import(res
));
2299 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
2300 f
.aux_surf
= &res
->aux
.surf
;
2301 f
.aux_usage
= aux_usage
;
2302 f
.aux_address
= res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
;
2304 struct iris_bo
*clear_bo
= NULL
;
2305 uint64_t clear_offset
= 0;
2307 iris_resource_get_clear_color(res
, &clear_bo
, &clear_offset
);
2309 f
.clear_address
= clear_bo
->gtt_offset
+ clear_offset
;
2310 f
.use_clear_address
= isl_dev
->info
->gen
> 9;
2314 isl_surf_fill_state_s(isl_dev
, map
, &f
);
2318 * The pipe->create_sampler_view() driver hook.
2320 static struct pipe_sampler_view
*
2321 iris_create_sampler_view(struct pipe_context
*ctx
,
2322 struct pipe_resource
*tex
,
2323 const struct pipe_sampler_view
*tmpl
)
2325 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2326 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2327 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2328 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
2333 /* initialize base object */
2335 isv
->base
.context
= ctx
;
2336 isv
->base
.texture
= NULL
;
2337 pipe_reference_init(&isv
->base
.reference
, 1);
2338 pipe_resource_reference(&isv
->base
.texture
, tex
);
2340 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
2341 struct iris_resource
*zres
, *sres
;
2342 const struct util_format_description
*desc
=
2343 util_format_description(tmpl
->format
);
2345 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
2347 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
2350 isv
->res
= (struct iris_resource
*) tex
;
2352 alloc_surface_states(&isv
->surface_state
, isv
->res
->aux
.sampler_usages
);
2354 isv
->surface_state
.bo_address
= isv
->res
->bo
->gtt_offset
;
2356 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
2358 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
2359 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
2360 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
2362 const struct iris_format_info fmt
=
2363 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
2365 isv
->clear_color
= isv
->res
->aux
.clear_color
;
2367 isv
->view
= (struct isl_view
) {
2369 .swizzle
= (struct isl_swizzle
) {
2370 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
2371 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
2372 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
2373 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
2378 void *map
= isv
->surface_state
.cpu
;
2380 /* Fill out SURFACE_STATE for this view. */
2381 if (tmpl
->target
!= PIPE_BUFFER
) {
2382 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
2383 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
2384 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
2385 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
2386 isv
->view
.array_len
=
2387 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
2389 if (iris_resource_unfinished_aux_import(isv
->res
))
2390 iris_resource_finish_aux_import(&screen
->base
, isv
->res
);
2392 unsigned aux_modes
= isv
->res
->aux
.sampler_usages
;
2394 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
2396 /* If we have a multisampled depth buffer, do not create a sampler
2397 * surface state with HiZ.
2399 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->res
->surf
,
2400 &isv
->view
, aux_usage
, 0, 0, 0);
2402 map
+= SURFACE_STATE_ALIGNMENT
;
2405 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
2406 isv
->view
.format
, isv
->view
.swizzle
,
2407 tmpl
->u
.buf
.offset
, tmpl
->u
.buf
.size
);
2410 upload_surface_states(ice
->state
.surface_uploader
, &isv
->surface_state
);
2416 iris_sampler_view_destroy(struct pipe_context
*ctx
,
2417 struct pipe_sampler_view
*state
)
2419 struct iris_sampler_view
*isv
= (void *) state
;
2420 pipe_resource_reference(&state
->texture
, NULL
);
2421 pipe_resource_reference(&isv
->surface_state
.ref
.res
, NULL
);
2422 free(isv
->surface_state
.cpu
);
2427 * The pipe->create_surface() driver hook.
2429 * In Gallium nomenclature, "surfaces" are a view of a resource that
2430 * can be bound as a render target or depth/stencil buffer.
2432 static struct pipe_surface
*
2433 iris_create_surface(struct pipe_context
*ctx
,
2434 struct pipe_resource
*tex
,
2435 const struct pipe_surface
*tmpl
)
2437 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2438 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2439 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2441 isl_surf_usage_flags_t usage
= 0;
2443 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
2444 else if (util_format_is_depth_or_stencil(tmpl
->format
))
2445 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
2447 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
2449 const struct iris_format_info fmt
=
2450 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
2452 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
2453 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
2454 /* Framebuffer validation will reject this invalid case, but it
2455 * hasn't had the opportunity yet. In the meantime, we need to
2456 * avoid hitting ISL asserts about unsupported formats below.
2461 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
2462 struct pipe_surface
*psurf
= &surf
->base
;
2463 struct iris_resource
*res
= (struct iris_resource
*) tex
;
2468 pipe_reference_init(&psurf
->reference
, 1);
2469 pipe_resource_reference(&psurf
->texture
, tex
);
2470 psurf
->context
= ctx
;
2471 psurf
->format
= tmpl
->format
;
2472 psurf
->width
= tex
->width0
;
2473 psurf
->height
= tex
->height0
;
2474 psurf
->texture
= tex
;
2475 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
2476 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
2477 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
2479 uint32_t array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
2481 struct isl_view
*view
= &surf
->view
;
2482 *view
= (struct isl_view
) {
2484 .base_level
= tmpl
->u
.tex
.level
,
2486 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2487 .array_len
= array_len
,
2488 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2493 enum pipe_texture_target target
= (tex
->target
== PIPE_TEXTURE_3D
&&
2494 array_len
== 1) ? PIPE_TEXTURE_2D
:
2495 tex
->target
== PIPE_TEXTURE_1D_ARRAY
?
2496 PIPE_TEXTURE_2D_ARRAY
: tex
->target
;
2498 struct isl_view
*read_view
= &surf
->read_view
;
2499 *read_view
= (struct isl_view
) {
2501 .base_level
= tmpl
->u
.tex
.level
,
2503 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2504 .array_len
= array_len
,
2505 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2506 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
2510 surf
->clear_color
= res
->aux
.clear_color
;
2512 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
2513 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
2514 ISL_SURF_USAGE_STENCIL_BIT
))
2518 alloc_surface_states(&surf
->surface_state
, res
->aux
.possible_usages
);
2519 surf
->surface_state
.bo_address
= res
->bo
->gtt_offset
;
2522 alloc_surface_states(&surf
->surface_state_read
, res
->aux
.possible_usages
);
2523 surf
->surface_state_read
.bo_address
= res
->bo
->gtt_offset
;
2526 if (!isl_format_is_compressed(res
->surf
.format
)) {
2527 if (iris_resource_unfinished_aux_import(res
))
2528 iris_resource_finish_aux_import(&screen
->base
, res
);
2530 void *map
= surf
->surface_state
.cpu
;
2531 UNUSED
void *map_read
= surf
->surface_state_read
.cpu
;
2533 /* This is a normal surface. Fill out a SURFACE_STATE for each possible
2534 * auxiliary surface mode and return the pipe_surface.
2536 unsigned aux_modes
= res
->aux
.possible_usages
;
2538 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
2539 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2540 view
, aux_usage
, 0, 0, 0);
2541 map
+= SURFACE_STATE_ALIGNMENT
;
2544 struct isl_surf surf
;
2545 uint32_t offset_to_tile
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
2546 get_rt_read_isl_surf(devinfo
, res
, target
, read_view
,
2547 &offset_to_tile
, &tile_x_sa
, &tile_y_sa
, &surf
);
2548 fill_surface_state(&screen
->isl_dev
, map_read
, res
, &surf
, read_view
,
2549 aux_usage
, offset_to_tile
, tile_x_sa
, tile_y_sa
);
2550 map_read
+= SURFACE_STATE_ALIGNMENT
;
2554 upload_surface_states(ice
->state
.surface_uploader
, &surf
->surface_state
);
2557 upload_surface_states(ice
->state
.surface_uploader
,
2558 &surf
->surface_state_read
);
2564 /* The resource has a compressed format, which is not renderable, but we
2565 * have a renderable view format. We must be attempting to upload blocks
2566 * of compressed data via an uncompressed view.
2568 * In this case, we can assume there are no auxiliary buffers, a single
2569 * miplevel, and that the resource is single-sampled. Gallium may try
2570 * and create an uncompressed view with multiple layers, however.
2572 assert(!isl_format_is_compressed(fmt
.fmt
));
2573 assert(res
->aux
.possible_usages
== 1 << ISL_AUX_USAGE_NONE
);
2574 assert(res
->surf
.samples
== 1);
2575 assert(view
->levels
== 1);
2577 struct isl_surf isl_surf
;
2578 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
2580 if (view
->base_level
> 0) {
2581 /* We can't rely on the hardware's miplevel selection with such
2582 * a substantial lie about the format, so we select a single image
2583 * using the Tile X/Y Offset fields. In this case, we can't handle
2584 * multiple array slices.
2586 * On Broadwell, HALIGN and VALIGN are specified in pixels and are
2587 * hard-coded to align to exactly the block size of the compressed
2588 * texture. This means that, when reinterpreted as a non-compressed
2589 * texture, the tile offsets may be anything and we can't rely on
2592 * Return NULL to force gallium frontends to take fallback paths.
2594 if (view
->array_len
> 1 || GEN_GEN
== 8)
2597 const bool is_3d
= res
->surf
.dim
== ISL_SURF_DIM_3D
;
2598 isl_surf_get_image_surf(&screen
->isl_dev
, &res
->surf
,
2600 is_3d
? 0 : view
->base_array_layer
,
2601 is_3d
? view
->base_array_layer
: 0,
2603 &offset_B
, &tile_x_sa
, &tile_y_sa
);
2605 /* We use address and tile offsets to access a single level/layer
2606 * as a subimage, so reset level/layer so it doesn't offset again.
2608 view
->base_array_layer
= 0;
2609 view
->base_level
= 0;
2611 /* Level 0 doesn't require tile offsets, and the hardware can find
2612 * array slices using QPitch even with the format override, so we
2613 * can allow layers in this case. Copy the original ISL surface.
2615 memcpy(&isl_surf
, &res
->surf
, sizeof(isl_surf
));
2618 /* Scale down the image dimensions by the block size. */
2619 const struct isl_format_layout
*fmtl
=
2620 isl_format_get_layout(res
->surf
.format
);
2621 isl_surf
.format
= fmt
.fmt
;
2622 isl_surf
.logical_level0_px
= isl_surf_get_logical_level0_el(&isl_surf
);
2623 isl_surf
.phys_level0_sa
= isl_surf_get_phys_level0_el(&isl_surf
);
2624 tile_x_sa
/= fmtl
->bw
;
2625 tile_y_sa
/= fmtl
->bh
;
2627 psurf
->width
= isl_surf
.logical_level0_px
.width
;
2628 psurf
->height
= isl_surf
.logical_level0_px
.height
;
2630 struct isl_surf_fill_state_info f
= {
2633 .mocs
= iris_mocs(res
->bo
, &screen
->isl_dev
),
2634 .address
= res
->bo
->gtt_offset
+ offset_B
,
2635 .x_offset_sa
= tile_x_sa
,
2636 .y_offset_sa
= tile_y_sa
,
2639 isl_surf_fill_state_s(&screen
->isl_dev
, surf
->surface_state
.cpu
, &f
);
2641 upload_surface_states(ice
->state
.surface_uploader
, &surf
->surface_state
);
2648 fill_default_image_param(struct brw_image_param
*param
)
2650 memset(param
, 0, sizeof(*param
));
2651 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
2652 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
2653 * detailed explanation of these parameters.
2655 param
->swizzling
[0] = 0xff;
2656 param
->swizzling
[1] = 0xff;
2660 fill_buffer_image_param(struct brw_image_param
*param
,
2661 enum pipe_format pfmt
,
2664 const unsigned cpp
= util_format_get_blocksize(pfmt
);
2666 fill_default_image_param(param
);
2667 param
->size
[0] = size
/ cpp
;
2668 param
->stride
[0] = cpp
;
2671 #define isl_surf_fill_image_param(x, ...)
2672 #define fill_default_image_param(x, ...)
2673 #define fill_buffer_image_param(x, ...)
2677 * The pipe->set_shader_images() driver hook.
2680 iris_set_shader_images(struct pipe_context
*ctx
,
2681 enum pipe_shader_type p_stage
,
2682 unsigned start_slot
, unsigned count
,
2683 const struct pipe_image_view
*p_images
)
2685 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2686 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2687 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2688 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2690 struct iris_genx_state
*genx
= ice
->state
.genx
;
2691 struct brw_image_param
*image_params
= genx
->shaders
[stage
].image_param
;
2694 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
2696 for (unsigned i
= 0; i
< count
; i
++) {
2697 struct iris_image_view
*iv
= &shs
->image
[start_slot
+ i
];
2699 if (p_images
&& p_images
[i
].resource
) {
2700 const struct pipe_image_view
*img
= &p_images
[i
];
2701 struct iris_resource
*res
= (void *) img
->resource
;
2703 util_copy_image_view(&iv
->base
, img
);
2705 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
2707 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
2708 res
->bind_stages
|= 1 << stage
;
2710 enum isl_format isl_fmt
= iris_image_view_get_format(ice
, img
);
2712 /* Render compression with images supported on gen12+ only. */
2713 unsigned aux_usages
= GEN_GEN
>= 12 ? res
->aux
.possible_usages
:
2714 1 << ISL_AUX_USAGE_NONE
;
2716 alloc_surface_states(&iv
->surface_state
, aux_usages
);
2717 iv
->surface_state
.bo_address
= res
->bo
->gtt_offset
;
2719 void *map
= iv
->surface_state
.cpu
;
2721 if (res
->base
.target
!= PIPE_BUFFER
) {
2722 struct isl_view view
= {
2724 .base_level
= img
->u
.tex
.level
,
2726 .base_array_layer
= img
->u
.tex
.first_layer
,
2727 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
2728 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2729 .usage
= ISL_SURF_USAGE_STORAGE_BIT
,
2732 /* If using untyped fallback. */
2733 if (isl_fmt
== ISL_FORMAT_RAW
) {
2734 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2735 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2738 unsigned aux_modes
= aux_usages
;
2740 enum isl_aux_usage usage
= u_bit_scan(&aux_modes
);
2742 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2743 &view
, usage
, 0, 0, 0);
2745 map
+= SURFACE_STATE_ALIGNMENT
;
2749 isl_surf_fill_image_param(&screen
->isl_dev
,
2750 &image_params
[start_slot
+ i
],
2753 util_range_add(&res
->base
, &res
->valid_buffer_range
, img
->u
.buf
.offset
,
2754 img
->u
.buf
.offset
+ img
->u
.buf
.size
);
2756 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2757 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2758 img
->u
.buf
.offset
, img
->u
.buf
.size
);
2759 fill_buffer_image_param(&image_params
[start_slot
+ i
],
2760 img
->format
, img
->u
.buf
.size
);
2763 upload_surface_states(ice
->state
.surface_uploader
, &iv
->surface_state
);
2765 pipe_resource_reference(&iv
->base
.resource
, NULL
);
2766 pipe_resource_reference(&iv
->surface_state
.ref
.res
, NULL
);
2767 fill_default_image_param(&image_params
[start_slot
+ i
]);
2771 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2773 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2774 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2776 /* Broadwell also needs brw_image_params re-uploaded */
2778 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2779 shs
->sysvals_need_upload
= true;
2785 * The pipe->set_sampler_views() driver hook.
2788 iris_set_sampler_views(struct pipe_context
*ctx
,
2789 enum pipe_shader_type p_stage
,
2790 unsigned start
, unsigned count
,
2791 struct pipe_sampler_view
**views
)
2793 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2794 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2795 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2797 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
2799 for (unsigned i
= 0; i
< count
; i
++) {
2800 struct pipe_sampler_view
*pview
= views
? views
[i
] : NULL
;
2801 pipe_sampler_view_reference((struct pipe_sampler_view
**)
2802 &shs
->textures
[start
+ i
], pview
);
2803 struct iris_sampler_view
*view
= (void *) pview
;
2805 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
2806 view
->res
->bind_stages
|= 1 << stage
;
2808 shs
->bound_sampler_views
|= 1 << (start
+ i
);
2810 update_surface_state_addrs(ice
->state
.surface_uploader
,
2811 &view
->surface_state
, view
->res
->bo
);
2815 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
2817 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2818 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2822 * The pipe->set_tess_state() driver hook.
2825 iris_set_tess_state(struct pipe_context
*ctx
,
2826 const float default_outer_level
[4],
2827 const float default_inner_level
[2])
2829 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2830 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
2832 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
2833 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
2835 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
2836 shs
->sysvals_need_upload
= true;
2840 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
2842 struct iris_surface
*surf
= (void *) p_surf
;
2843 pipe_resource_reference(&p_surf
->texture
, NULL
);
2844 pipe_resource_reference(&surf
->surface_state
.ref
.res
, NULL
);
2845 pipe_resource_reference(&surf
->surface_state_read
.ref
.res
, NULL
);
2846 free(surf
->surface_state
.cpu
);
2851 iris_set_clip_state(struct pipe_context
*ctx
,
2852 const struct pipe_clip_state
*state
)
2854 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2855 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
2856 struct iris_shader_state
*gshs
= &ice
->state
.shaders
[MESA_SHADER_GEOMETRY
];
2857 struct iris_shader_state
*tshs
= &ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
];
2859 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
2861 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
| IRIS_DIRTY_CONSTANTS_GS
|
2862 IRIS_DIRTY_CONSTANTS_TES
;
2863 shs
->sysvals_need_upload
= true;
2864 gshs
->sysvals_need_upload
= true;
2865 tshs
->sysvals_need_upload
= true;
2869 * The pipe->set_polygon_stipple() driver hook.
2872 iris_set_polygon_stipple(struct pipe_context
*ctx
,
2873 const struct pipe_poly_stipple
*state
)
2875 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2876 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
2877 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
2881 * The pipe->set_sample_mask() driver hook.
2884 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2886 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2888 /* We only support 16x MSAA, so we have 16 bits of sample maks.
2889 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
2891 ice
->state
.sample_mask
= sample_mask
& 0xffff;
2892 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
2896 * The pipe->set_scissor_states() driver hook.
2898 * This corresponds to our SCISSOR_RECT state structures. It's an
2899 * exact match, so we just store them, and memcpy them out later.
2902 iris_set_scissor_states(struct pipe_context
*ctx
,
2903 unsigned start_slot
,
2904 unsigned num_scissors
,
2905 const struct pipe_scissor_state
*rects
)
2907 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2909 for (unsigned i
= 0; i
< num_scissors
; i
++) {
2910 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
2911 /* If the scissor was out of bounds and got clamped to 0 width/height
2912 * at the bounds, the subtraction of 1 from maximums could produce a
2913 * negative number and thus not clip anything. Instead, just provide
2914 * a min > max scissor inside the bounds, which produces the expected
2917 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2918 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
2921 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2922 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
2923 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
2928 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
2932 * The pipe->set_stencil_ref() driver hook.
2934 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
2937 iris_set_stencil_ref(struct pipe_context
*ctx
,
2938 const struct pipe_stencil_ref
*state
)
2940 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2941 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2943 ice
->state
.dirty
|= IRIS_DIRTY_STENCIL_REF
;
2944 else if (GEN_GEN
>= 9)
2945 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2947 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2951 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2953 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2957 * The pipe->set_viewport_states() driver hook.
2959 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2960 * the guardband yet, as we need the framebuffer dimensions, but we can
2961 * at least fill out the rest.
2964 iris_set_viewport_states(struct pipe_context
*ctx
,
2965 unsigned start_slot
,
2967 const struct pipe_viewport_state
*states
)
2969 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2971 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2973 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2975 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2976 !ice
->state
.cso_rast
->depth_clip_far
))
2977 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2981 * The pipe->set_framebuffer_state() driver hook.
2983 * Sets the current draw FBO, including color render targets, depth,
2984 * and stencil buffers.
2987 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2988 const struct pipe_framebuffer_state
*state
)
2990 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2991 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2992 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2993 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2994 struct iris_resource
*zres
;
2995 struct iris_resource
*stencil_res
;
2997 unsigned samples
= util_framebuffer_get_num_samples(state
);
2998 unsigned layers
= util_framebuffer_get_num_layers(state
);
3000 if (cso
->samples
!= samples
) {
3001 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
3003 /* We need to toggle 3DSTATE_PS::32 Pixel Dispatch Enable */
3004 if (GEN_GEN
>= 9 && (cso
->samples
== 16 || samples
== 16))
3005 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
3008 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
3009 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
3012 if ((cso
->layers
== 0) != (layers
== 0)) {
3013 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
3016 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
3017 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
3020 if (cso
->zsbuf
|| state
->zsbuf
) {
3021 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
3024 util_copy_framebuffer_state(cso
, state
);
3025 cso
->samples
= samples
;
3026 cso
->layers
= layers
;
3028 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
3030 struct isl_view view
= {
3033 .base_array_layer
= 0,
3035 .swizzle
= ISL_SWIZZLE_IDENTITY
,
3038 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
3041 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
3044 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
3045 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
3047 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
3050 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
3052 info
.depth_surf
= &zres
->surf
;
3053 info
.depth_address
= zres
->bo
->gtt_offset
+ zres
->offset
;
3054 info
.mocs
= iris_mocs(zres
->bo
, isl_dev
);
3056 view
.format
= zres
->surf
.format
;
3058 if (iris_resource_level_has_hiz(zres
, view
.base_level
)) {
3059 info
.hiz_usage
= zres
->aux
.usage
;
3060 info
.hiz_surf
= &zres
->aux
.surf
;
3061 info
.hiz_address
= zres
->aux
.bo
->gtt_offset
+ zres
->aux
.offset
;
3066 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
3067 info
.stencil_aux_usage
= stencil_res
->aux
.usage
;
3068 info
.stencil_surf
= &stencil_res
->surf
;
3069 info
.stencil_address
= stencil_res
->bo
->gtt_offset
+ stencil_res
->offset
;
3071 view
.format
= stencil_res
->surf
.format
;
3072 info
.mocs
= iris_mocs(stencil_res
->bo
, isl_dev
);
3077 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
3079 /* Make a null surface for unbound buffers */
3080 void *null_surf_map
=
3081 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
3082 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
3083 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
3084 isl_extent3d(MAX2(cso
->width
, 1),
3085 MAX2(cso
->height
, 1),
3086 cso
->layers
? cso
->layers
: 1));
3087 ice
->state
.null_fb
.offset
+=
3088 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
3090 /* Render target change */
3091 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
3093 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_BUFFER
;
3095 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
3097 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
3100 ice
->state
.dirty
|= IRIS_DIRTY_PMA_FIX
;
3104 * The pipe->set_constant_buffer() driver hook.
3106 * This uploads any constant data in user buffers, and references
3107 * any UBO resources containing constant data.
3110 iris_set_constant_buffer(struct pipe_context
*ctx
,
3111 enum pipe_shader_type p_stage
, unsigned index
,
3112 const struct pipe_constant_buffer
*input
)
3114 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3115 gl_shader_stage stage
= stage_from_pipe(p_stage
);
3116 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3117 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[index
];
3119 /* TODO: Only do this if the buffer changes? */
3120 pipe_resource_reference(&shs
->constbuf_surf_state
[index
].res
, NULL
);
3122 if (input
&& input
->buffer_size
&& (input
->buffer
|| input
->user_buffer
)) {
3123 shs
->bound_cbufs
|= 1u << index
;
3125 if (input
->user_buffer
) {
3127 pipe_resource_reference(&cbuf
->buffer
, NULL
);
3128 u_upload_alloc(ice
->ctx
.const_uploader
, 0, input
->buffer_size
, 64,
3129 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
3131 if (!cbuf
->buffer
) {
3132 /* Allocation was unsuccessful - just unbind */
3133 iris_set_constant_buffer(ctx
, p_stage
, index
, NULL
);
3138 memcpy(map
, input
->user_buffer
, input
->buffer_size
);
3139 } else if (input
->buffer
) {
3140 pipe_resource_reference(&cbuf
->buffer
, input
->buffer
);
3142 cbuf
->buffer_offset
= input
->buffer_offset
;
3146 MIN2(input
->buffer_size
,
3147 iris_resource_bo(cbuf
->buffer
)->size
- cbuf
->buffer_offset
);
3149 struct iris_resource
*res
= (void *) cbuf
->buffer
;
3150 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
3151 res
->bind_stages
|= 1 << stage
;
3153 shs
->bound_cbufs
&= ~(1u << index
);
3154 pipe_resource_reference(&cbuf
->buffer
, NULL
);
3157 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
3161 upload_sysvals(struct iris_context
*ice
,
3162 gl_shader_stage stage
)
3164 UNUSED
struct iris_genx_state
*genx
= ice
->state
.genx
;
3165 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3167 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3168 if (!shader
|| shader
->num_system_values
== 0)
3171 assert(shader
->num_cbufs
> 0);
3173 unsigned sysval_cbuf_index
= shader
->num_cbufs
- 1;
3174 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[sysval_cbuf_index
];
3175 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t);
3176 uint32_t *map
= NULL
;
3178 assert(sysval_cbuf_index
< PIPE_MAX_CONSTANT_BUFFERS
);
3179 u_upload_alloc(ice
->ctx
.const_uploader
, 0, upload_size
, 64,
3180 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
3182 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
3183 uint32_t sysval
= shader
->system_values
[i
];
3186 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
3188 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
3189 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
3190 struct brw_image_param
*param
=
3191 &genx
->shaders
[stage
].image_param
[img
];
3193 assert(offset
< sizeof(struct brw_image_param
));
3194 value
= ((uint32_t *) param
)[offset
];
3196 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
3198 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
3199 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
3200 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
3201 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
3202 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
3203 if (stage
== MESA_SHADER_TESS_CTRL
) {
3204 value
= ice
->state
.vertices_per_patch
;
3206 assert(stage
== MESA_SHADER_TESS_EVAL
);
3207 const struct shader_info
*tcs_info
=
3208 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
3210 value
= tcs_info
->tess
.tcs_vertices_out
;
3212 value
= ice
->state
.vertices_per_patch
;
3214 } else if (sysval
>= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
&&
3215 sysval
<= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
) {
3216 unsigned i
= sysval
- BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
3217 value
= fui(ice
->state
.default_outer_level
[i
]);
3218 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
) {
3219 value
= fui(ice
->state
.default_inner_level
[0]);
3220 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
) {
3221 value
= fui(ice
->state
.default_inner_level
[1]);
3222 } else if (sysval
>= BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X
&&
3223 sysval
<= BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Z
) {
3224 unsigned i
= sysval
- BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X
;
3225 value
= ice
->state
.last_block
[i
];
3227 assert(!"unhandled system value");
3233 cbuf
->buffer_size
= upload_size
;
3234 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
3235 &shs
->constbuf_surf_state
[sysval_cbuf_index
], false);
3237 shs
->sysvals_need_upload
= false;
3241 * The pipe->set_shader_buffers() driver hook.
3243 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
3244 * SURFACE_STATE here, as the buffer offset may change each time.
3247 iris_set_shader_buffers(struct pipe_context
*ctx
,
3248 enum pipe_shader_type p_stage
,
3249 unsigned start_slot
, unsigned count
,
3250 const struct pipe_shader_buffer
*buffers
,
3251 unsigned writable_bitmask
)
3253 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3254 gl_shader_stage stage
= stage_from_pipe(p_stage
);
3255 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3257 unsigned modified_bits
= u_bit_consecutive(start_slot
, count
);
3259 shs
->bound_ssbos
&= ~modified_bits
;
3260 shs
->writable_ssbos
&= ~modified_bits
;
3261 shs
->writable_ssbos
|= writable_bitmask
<< start_slot
;
3263 for (unsigned i
= 0; i
< count
; i
++) {
3264 if (buffers
&& buffers
[i
].buffer
) {
3265 struct iris_resource
*res
= (void *) buffers
[i
].buffer
;
3266 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[start_slot
+ i
];
3267 struct iris_state_ref
*surf_state
=
3268 &shs
->ssbo_surf_state
[start_slot
+ i
];
3269 pipe_resource_reference(&ssbo
->buffer
, &res
->base
);
3270 ssbo
->buffer_offset
= buffers
[i
].buffer_offset
;
3272 MIN2(buffers
[i
].buffer_size
, res
->bo
->size
- ssbo
->buffer_offset
);
3274 shs
->bound_ssbos
|= 1 << (start_slot
+ i
);
3276 iris_upload_ubo_ssbo_surf_state(ice
, ssbo
, surf_state
, true);
3278 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
3279 res
->bind_stages
|= 1 << stage
;
3281 util_range_add(&res
->base
, &res
->valid_buffer_range
, ssbo
->buffer_offset
,
3282 ssbo
->buffer_offset
+ ssbo
->buffer_size
);
3284 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
].buffer
, NULL
);
3285 pipe_resource_reference(&shs
->ssbo_surf_state
[start_slot
+ i
].res
,
3290 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
3294 iris_delete_state(struct pipe_context
*ctx
, void *state
)
3300 * The pipe->set_vertex_buffers() driver hook.
3302 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
3305 iris_set_vertex_buffers(struct pipe_context
*ctx
,
3306 unsigned start_slot
, unsigned count
,
3307 const struct pipe_vertex_buffer
*buffers
)
3309 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3310 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
3311 struct iris_genx_state
*genx
= ice
->state
.genx
;
3313 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
3315 for (unsigned i
= 0; i
< count
; i
++) {
3316 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
3317 struct iris_vertex_buffer_state
*state
=
3318 &genx
->vertex_buffers
[start_slot
+ i
];
3321 pipe_resource_reference(&state
->resource
, NULL
);
3325 /* We may see user buffers that are NULL bindings. */
3326 assert(!(buffer
->is_user_buffer
&& buffer
->buffer
.user
!= NULL
));
3328 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
3329 struct iris_resource
*res
= (void *) state
->resource
;
3331 state
->offset
= (int) buffer
->buffer_offset
;
3334 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
3335 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
3338 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
3339 vb
.VertexBufferIndex
= start_slot
+ i
;
3340 vb
.AddressModifyEnable
= true;
3341 vb
.BufferPitch
= buffer
->stride
;
3343 vb
.BufferSize
= res
->base
.width0
- (int) buffer
->buffer_offset
;
3344 vb
.BufferStartingAddress
=
3345 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
3346 vb
.MOCS
= iris_mocs(res
->bo
, &screen
->isl_dev
);
3348 vb
.NullVertexBuffer
= true;
3353 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
3357 * Gallium CSO for vertex elements.
3359 struct iris_vertex_element_state
{
3360 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
3361 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
3362 uint32_t edgeflag_ve
[GENX(VERTEX_ELEMENT_STATE_length
)];
3363 uint32_t edgeflag_vfi
[GENX(3DSTATE_VF_INSTANCING_length
)];
3368 * The pipe->create_vertex_elements() driver hook.
3370 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
3371 * and 3DSTATE_VF_INSTANCING commands. The vertex_elements and vf_instancing
3372 * arrays are ready to be emitted at draw time if no EdgeFlag or SGVs are
3373 * needed. In these cases we will need information available at draw time.
3374 * We setup edgeflag_ve and edgeflag_vfi as alternatives last
3375 * 3DSTATE_VERTEX_ELEMENT and 3DSTATE_VF_INSTANCING that can be used at
3376 * draw time if we detect that EdgeFlag is needed by the Vertex Shader.
3379 iris_create_vertex_elements(struct pipe_context
*ctx
,
3381 const struct pipe_vertex_element
*state
)
3383 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
3384 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3385 struct iris_vertex_element_state
*cso
=
3386 malloc(sizeof(struct iris_vertex_element_state
));
3390 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
3392 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
3395 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
3396 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
3399 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
3401 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
3402 ve
.Component0Control
= VFCOMP_STORE_0
;
3403 ve
.Component1Control
= VFCOMP_STORE_0
;
3404 ve
.Component2Control
= VFCOMP_STORE_0
;
3405 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
3408 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
3412 for (int i
= 0; i
< count
; i
++) {
3413 const struct iris_format_info fmt
=
3414 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
3415 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
3416 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
3418 switch (isl_format_get_num_channels(fmt
.fmt
)) {
3419 case 0: comp
[0] = VFCOMP_STORE_0
; /* fallthrough */
3420 case 1: comp
[1] = VFCOMP_STORE_0
; /* fallthrough */
3421 case 2: comp
[2] = VFCOMP_STORE_0
; /* fallthrough */
3423 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
3424 : VFCOMP_STORE_1_FP
;
3427 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
3428 ve
.EdgeFlagEnable
= false;
3429 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
3431 ve
.SourceElementOffset
= state
[i
].src_offset
;
3432 ve
.SourceElementFormat
= fmt
.fmt
;
3433 ve
.Component0Control
= comp
[0];
3434 ve
.Component1Control
= comp
[1];
3435 ve
.Component2Control
= comp
[2];
3436 ve
.Component3Control
= comp
[3];
3439 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
3440 vi
.VertexElementIndex
= i
;
3441 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
3442 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
3445 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
3446 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
3449 /* An alternative version of the last VE and VFI is stored so it
3450 * can be used at draw time in case Vertex Shader uses EdgeFlag
3453 const unsigned edgeflag_index
= count
- 1;
3454 const struct iris_format_info fmt
=
3455 iris_format_for_usage(devinfo
, state
[edgeflag_index
].src_format
, 0);
3456 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), cso
->edgeflag_ve
, ve
) {
3457 ve
.EdgeFlagEnable
= true ;
3458 ve
.VertexBufferIndex
= state
[edgeflag_index
].vertex_buffer_index
;
3460 ve
.SourceElementOffset
= state
[edgeflag_index
].src_offset
;
3461 ve
.SourceElementFormat
= fmt
.fmt
;
3462 ve
.Component0Control
= VFCOMP_STORE_SRC
;
3463 ve
.Component1Control
= VFCOMP_STORE_0
;
3464 ve
.Component2Control
= VFCOMP_STORE_0
;
3465 ve
.Component3Control
= VFCOMP_STORE_0
;
3467 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->edgeflag_vfi
, vi
) {
3468 /* The vi.VertexElementIndex of the EdgeFlag Vertex Element is filled
3469 * at draw time, as it should change if SGVs are emitted.
3471 vi
.InstancingEnable
= state
[edgeflag_index
].instance_divisor
> 0;
3472 vi
.InstanceDataStepRate
= state
[edgeflag_index
].instance_divisor
;
3480 * The pipe->bind_vertex_elements_state() driver hook.
3483 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
3485 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3486 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
3487 struct iris_vertex_element_state
*new_cso
= state
;
3489 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
3490 * we need to re-emit it to ensure we're overriding the right one.
3492 if (new_cso
&& cso_changed(count
))
3493 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
3495 ice
->state
.cso_vertex_elements
= state
;
3496 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
3500 * The pipe->create_stream_output_target() driver hook.
3502 * "Target" here refers to a destination buffer. We translate this into
3503 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
3504 * know which buffer this represents, or whether we ought to zero the
3505 * write-offsets, or append. Those are handled in the set() hook.
3507 static struct pipe_stream_output_target
*
3508 iris_create_stream_output_target(struct pipe_context
*ctx
,
3509 struct pipe_resource
*p_res
,
3510 unsigned buffer_offset
,
3511 unsigned buffer_size
)
3513 struct iris_resource
*res
= (void *) p_res
;
3514 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
3518 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
3520 pipe_reference_init(&cso
->base
.reference
, 1);
3521 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
3522 cso
->base
.buffer_offset
= buffer_offset
;
3523 cso
->base
.buffer_size
= buffer_size
;
3524 cso
->base
.context
= ctx
;
3526 util_range_add(&res
->base
, &res
->valid_buffer_range
, buffer_offset
,
3527 buffer_offset
+ buffer_size
);
3529 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
3535 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
3536 struct pipe_stream_output_target
*state
)
3538 struct iris_stream_output_target
*cso
= (void *) state
;
3540 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
3541 pipe_resource_reference(&cso
->offset
.res
, NULL
);
3547 * The pipe->set_stream_output_targets() driver hook.
3549 * At this point, we know which targets are bound to a particular index,
3550 * and also whether we want to append or start over. We can finish the
3551 * 3DSTATE_SO_BUFFER packets we started earlier.
3554 iris_set_stream_output_targets(struct pipe_context
*ctx
,
3555 unsigned num_targets
,
3556 struct pipe_stream_output_target
**targets
,
3557 const unsigned *offsets
)
3559 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3560 struct iris_genx_state
*genx
= ice
->state
.genx
;
3561 uint32_t *so_buffers
= genx
->so_buffers
;
3562 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
3564 const bool active
= num_targets
> 0;
3565 if (ice
->state
.streamout_active
!= active
) {
3566 ice
->state
.streamout_active
= active
;
3567 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
3569 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
3570 * it's a non-pipelined command. If we're switching streamout on, we
3571 * may have missed emitting it earlier, so do so now. (We're already
3572 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
3575 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
3578 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3579 struct iris_stream_output_target
*tgt
=
3580 (void *) ice
->state
.so_target
[i
];
3582 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3584 flush
|= iris_flush_bits_for_history(res
);
3585 iris_dirty_for_history(ice
, res
);
3588 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
3589 "make streamout results visible", flush
);
3593 for (int i
= 0; i
< 4; i
++) {
3594 pipe_so_target_reference(&ice
->state
.so_target
[i
],
3595 i
< num_targets
? targets
[i
] : NULL
);
3598 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
3602 for (unsigned i
= 0; i
< 4; i
++,
3603 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
3605 struct iris_stream_output_target
*tgt
= (void *) ice
->state
.so_target
[i
];
3606 unsigned offset
= offsets
[i
];
3609 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
3611 sob
.SOBufferIndex
= i
;
3613 sob
._3DCommandOpcode
= 0;
3614 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ i
;
3620 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3622 /* Note that offsets[i] will either be 0, causing us to zero
3623 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
3624 * "continue appending at the existing offset."
3626 assert(offset
== 0 || offset
== 0xFFFFFFFF);
3628 /* We might be called by Begin (offset = 0), Pause, then Resume
3629 * (offset = 0xFFFFFFFF) before ever drawing (where these commands
3630 * will actually be sent to the GPU). In this case, we don't want
3631 * to append - we still want to do our initial zeroing.
3636 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
3638 sob
.SOBufferIndex
= i
;
3640 sob
._3DCommandOpcode
= 0;
3641 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ i
;
3643 sob
.SurfaceBaseAddress
=
3644 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
3645 sob
.SOBufferEnable
= true;
3646 sob
.StreamOffsetWriteEnable
= true;
3647 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3648 sob
.MOCS
= iris_mocs(res
->bo
, &screen
->isl_dev
);
3650 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
3651 sob
.StreamOffset
= offset
;
3652 sob
.StreamOutputBufferOffsetAddress
=
3653 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
3654 tgt
->offset
.offset
);
3658 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
3662 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
3663 * 3DSTATE_STREAMOUT packets.
3665 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
3666 * hardware to record. We can create it entirely based on the shader, with
3667 * no dynamic state dependencies.
3669 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
3670 * state-based settings. We capture the shader-related ones here, and merge
3671 * the rest in at draw time.
3674 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
3675 const struct brw_vue_map
*vue_map
)
3677 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3678 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3679 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3680 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3682 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3684 memset(so_decl
, 0, sizeof(so_decl
));
3686 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3687 * command feels strange -- each dword pair contains a SO_DECL per stream.
3689 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
3690 const struct pipe_stream_output
*output
= &info
->output
[i
];
3691 const int buffer
= output
->output_buffer
;
3692 const int varying
= output
->register_index
;
3693 const unsigned stream_id
= output
->stream
;
3694 assert(stream_id
< MAX_VERTEX_STREAMS
);
3696 buffer_mask
[stream_id
] |= 1 << buffer
;
3698 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3700 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3701 * array. Instead, it simply increments DstOffset for the following
3702 * input by the number of components that should be skipped.
3704 * Our hardware is unusual in that it requires us to program SO_DECLs
3705 * for fake "hole" components, rather than simply taking the offset
3706 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3707 * program as many size = 4 holes as we can, then a final hole to
3708 * accommodate the final 1, 2, or 3 remaining.
3710 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
3712 while (skip_components
> 0) {
3713 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3715 .OutputBufferSlot
= output
->output_buffer
,
3716 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3718 skip_components
-= 4;
3721 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
3723 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3724 .OutputBufferSlot
= output
->output_buffer
,
3725 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3727 ((1 << output
->num_components
) - 1) << output
->start_component
,
3730 if (decls
[stream_id
] > max_decls
)
3731 max_decls
= decls
[stream_id
];
3734 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
3735 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
3736 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
3738 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
3739 int urb_entry_read_offset
= 0;
3740 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3741 urb_entry_read_offset
;
3743 /* We always read the whole vertex. This could be reduced at some
3744 * point by reading less and offsetting the register index in the
3747 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3748 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3749 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3750 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3751 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3752 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3753 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3754 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3756 /* Set buffer pitches; 0 means unbound. */
3757 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
3758 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
3759 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
3760 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
3763 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
3764 list
.DWordLength
= 3 + 2 * max_decls
- 2;
3765 list
.StreamtoBufferSelects0
= buffer_mask
[0];
3766 list
.StreamtoBufferSelects1
= buffer_mask
[1];
3767 list
.StreamtoBufferSelects2
= buffer_mask
[2];
3768 list
.StreamtoBufferSelects3
= buffer_mask
[3];
3769 list
.NumEntries0
= decls
[0];
3770 list
.NumEntries1
= decls
[1];
3771 list
.NumEntries2
= decls
[2];
3772 list
.NumEntries3
= decls
[3];
3775 for (int i
= 0; i
< max_decls
; i
++) {
3776 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
3777 entry
.Stream0Decl
= so_decl
[0][i
];
3778 entry
.Stream1Decl
= so_decl
[1][i
];
3779 entry
.Stream2Decl
= so_decl
[2][i
];
3780 entry
.Stream3Decl
= so_decl
[3][i
];
3788 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
3789 const struct brw_vue_map
*last_vue_map
,
3790 bool two_sided_color
,
3791 unsigned *out_offset
,
3792 unsigned *out_length
)
3794 /* The compiler computes the first URB slot without considering COL/BFC
3795 * swizzling (because it doesn't know whether it's enabled), so we need
3796 * to do that here too. This may result in a smaller offset, which
3799 const unsigned first_slot
=
3800 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
3802 /* This becomes the URB read offset (counted in pairs of slots). */
3803 assert(first_slot
% 2 == 0);
3804 *out_offset
= first_slot
/ 2;
3806 /* We need to adjust the inputs read to account for front/back color
3807 * swizzling, as it can make the URB length longer.
3809 for (int c
= 0; c
<= 1; c
++) {
3810 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
3811 /* If two sided color is enabled, the fragment shader's gl_Color
3812 * (COL0) input comes from either the gl_FrontColor (COL0) or
3813 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
3815 if (two_sided_color
)
3816 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3818 /* If front color isn't written, we opt to give them back color
3819 * instead of an undefined value. Switch from COL to BFC.
3821 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
3822 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
3823 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3828 /* Compute the minimum URB Read Length necessary for the FS inputs.
3830 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
3831 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
3833 * "This field should be set to the minimum length required to read the
3834 * maximum source attribute. The maximum source attribute is indicated
3835 * by the maximum value of the enabled Attribute # Source Attribute if
3836 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
3837 * enable is not set.
3838 * read_length = ceiling((max_source_attr + 1) / 2)
3840 * [errata] Corruption/Hang possible if length programmed larger than
3843 * Similar text exists for Ivy Bridge.
3845 * We find the last URB slot that's actually read by the FS.
3847 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
3848 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
3849 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
3852 /* The URB read length is the difference of the two, counted in pairs. */
3853 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
3857 iris_emit_sbe_swiz(struct iris_batch
*batch
,
3858 const struct iris_context
*ice
,
3859 unsigned urb_read_offset
,
3860 unsigned sprite_coord_enables
)
3862 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
3863 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3864 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3865 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
3866 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3868 /* XXX: this should be generated when putting programs in place */
3870 for (uint8_t idx
= 0; idx
< wm_prog_data
->urb_setup_attribs_count
; idx
++) {
3871 const uint8_t fs_attr
= wm_prog_data
->urb_setup_attribs
[idx
];
3872 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
3873 if (input_index
< 0 || input_index
>= 16)
3876 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
3877 &attr_overrides
[input_index
];
3878 int slot
= vue_map
->varying_to_slot
[fs_attr
];
3880 /* Viewport and Layer are stored in the VUE header. We need to override
3881 * them to zero if earlier stages didn't write them, as GL requires that
3882 * they read back as zero when not explicitly set.
3885 case VARYING_SLOT_VIEWPORT
:
3886 case VARYING_SLOT_LAYER
:
3887 attr
->ComponentOverrideX
= true;
3888 attr
->ComponentOverrideW
= true;
3889 attr
->ConstantSource
= CONST_0000
;
3891 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
3892 attr
->ComponentOverrideY
= true;
3893 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
3894 attr
->ComponentOverrideZ
= true;
3897 case VARYING_SLOT_PRIMITIVE_ID
:
3898 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
3900 attr
->ComponentOverrideX
= true;
3901 attr
->ComponentOverrideY
= true;
3902 attr
->ComponentOverrideZ
= true;
3903 attr
->ComponentOverrideW
= true;
3904 attr
->ConstantSource
= PRIM_ID
;
3912 if (sprite_coord_enables
& (1 << input_index
))
3915 /* If there was only a back color written but not front, use back
3916 * as the color instead of undefined.
3918 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
3919 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
3920 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
3921 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
3923 /* Not written by the previous stage - undefined. */
3925 attr
->ComponentOverrideX
= true;
3926 attr
->ComponentOverrideY
= true;
3927 attr
->ComponentOverrideZ
= true;
3928 attr
->ComponentOverrideW
= true;
3929 attr
->ConstantSource
= CONST_0001_FLOAT
;
3933 /* Compute the location of the attribute relative to the read offset,
3934 * which is counted in 256-bit increments (two 128-bit VUE slots).
3936 const int source_attr
= slot
- 2 * urb_read_offset
;
3937 assert(source_attr
>= 0 && source_attr
<= 32);
3938 attr
->SourceAttribute
= source_attr
;
3940 /* If we are doing two-sided color, and the VUE slot following this one
3941 * represents a back-facing color, then we need to instruct the SF unit
3942 * to do back-facing swizzling.
3944 if (cso_rast
->light_twoside
&&
3945 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3946 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3947 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3948 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3949 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3952 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3953 for (int i
= 0; i
< 16; i
++)
3954 sbes
.Attribute
[i
] = attr_overrides
[i
];
3959 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3960 const struct iris_rasterizer_state
*cso
)
3962 unsigned overrides
= 0;
3964 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
3965 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
3967 for (int i
= 0; i
< 8; i
++) {
3968 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
3969 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
3970 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
3977 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
3979 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3980 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3981 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3982 const struct shader_info
*fs_info
=
3983 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
3985 unsigned urb_read_offset
, urb_read_length
;
3986 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
3987 ice
->shaders
.last_vue_map
,
3988 cso_rast
->light_twoside
,
3989 &urb_read_offset
, &urb_read_length
);
3991 unsigned sprite_coord_overrides
=
3992 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3994 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
3995 sbe
.AttributeSwizzleEnable
= true;
3996 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3997 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3998 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3999 sbe
.VertexURBEntryReadLength
= urb_read_length
;
4000 sbe
.ForceVertexURBEntryReadOffset
= true;
4001 sbe
.ForceVertexURBEntryReadLength
= true;
4002 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
4003 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
4005 for (int i
= 0; i
< 32; i
++) {
4006 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
4011 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
4014 /* ------------------------------------------------------------------- */
4017 * Populate VS program key fields based on the current state.
4020 iris_populate_vs_key(const struct iris_context
*ice
,
4021 const struct shader_info
*info
,
4022 gl_shader_stage last_stage
,
4023 struct iris_vs_prog_key
*key
)
4025 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4027 if (info
->clip_distance_array_size
== 0 &&
4028 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
4029 last_stage
== MESA_SHADER_VERTEX
)
4030 key
->vue
.nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
4034 * Populate TCS program key fields based on the current state.
4037 iris_populate_tcs_key(const struct iris_context
*ice
,
4038 struct iris_tcs_prog_key
*key
)
4043 * Populate TES program key fields based on the current state.
4046 iris_populate_tes_key(const struct iris_context
*ice
,
4047 const struct shader_info
*info
,
4048 gl_shader_stage last_stage
,
4049 struct iris_tes_prog_key
*key
)
4051 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4053 if (info
->clip_distance_array_size
== 0 &&
4054 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
4055 last_stage
== MESA_SHADER_TESS_EVAL
)
4056 key
->vue
.nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
4060 * Populate GS program key fields based on the current state.
4063 iris_populate_gs_key(const struct iris_context
*ice
,
4064 const struct shader_info
*info
,
4065 gl_shader_stage last_stage
,
4066 struct iris_gs_prog_key
*key
)
4068 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4070 if (info
->clip_distance_array_size
== 0 &&
4071 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
4072 last_stage
== MESA_SHADER_GEOMETRY
)
4073 key
->vue
.nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
4077 * Populate FS program key fields based on the current state.
4080 iris_populate_fs_key(const struct iris_context
*ice
,
4081 const struct shader_info
*info
,
4082 struct iris_fs_prog_key
*key
)
4084 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
4085 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
4086 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
4087 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
4088 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
4090 key
->nr_color_regions
= fb
->nr_cbufs
;
4092 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
4094 key
->alpha_to_coverage
= blend
->alpha_to_coverage
;
4096 key
->alpha_test_replicate_alpha
= fb
->nr_cbufs
> 1 && zsa
->alpha
.enabled
;
4098 key
->flat_shade
= rast
->flatshade
&&
4099 (info
->inputs_read
& (VARYING_BIT_COL0
| VARYING_BIT_COL1
));
4101 key
->persample_interp
= rast
->force_persample_interp
;
4102 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
4104 key
->coherent_fb_fetch
= GEN_GEN
>= 9;
4106 key
->force_dual_color_blend
=
4107 screen
->driconf
.dual_color_blend_by_location
&&
4108 (blend
->blend_enables
& 1) && blend
->dual_color_blending
;
4110 /* TODO: Respect glHint for key->high_quality_derivatives */
4114 iris_populate_cs_key(const struct iris_context
*ice
,
4115 struct iris_cs_prog_key
*key
)
4120 KSP(const struct iris_compiled_shader
*shader
)
4122 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
4123 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
4126 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
4127 pkt.KernelStartPointer = KSP(shader); \
4128 pkt.BindingTableEntryCount = shader->bt.size_bytes / 4; \
4129 pkt.FloatingPointMode = prog_data->use_alt_mode; \
4131 pkt.DispatchGRFStartRegisterForURBData = \
4132 prog_data->dispatch_grf_start_reg; \
4133 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
4134 pkt.prefix##URBEntryReadOffset = 0; \
4136 pkt.StatisticsEnable = true; \
4137 pkt.Enable = true; \
4139 if (prog_data->total_scratch) { \
4140 struct iris_bo *bo = \
4141 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
4142 uint32_t scratch_addr = bo->gtt_offset; \
4143 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
4144 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
4148 * Encode most of 3DSTATE_VS based on the compiled shader.
4151 iris_store_vs_state(struct iris_context
*ice
,
4152 const struct gen_device_info
*devinfo
,
4153 struct iris_compiled_shader
*shader
)
4155 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4156 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4158 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
4159 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
4160 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
4161 vs
.SIMD8DispatchEnable
= true;
4162 vs
.UserClipDistanceCullTestEnableBitmask
=
4163 vue_prog_data
->cull_distance_mask
;
4168 * Encode most of 3DSTATE_HS based on the compiled shader.
4171 iris_store_tcs_state(struct iris_context
*ice
,
4172 const struct gen_device_info
*devinfo
,
4173 struct iris_compiled_shader
*shader
)
4175 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4176 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4177 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
4179 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
4180 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
4183 /* GEN:BUG:1604578095:
4185 * Hang occurs when the number of max threads is less than 2 times
4186 * the number of instance count. The number of max threads must be
4187 * more than 2 times the number of instance count.
4189 assert((devinfo
->max_tcs_threads
/ 2) > tcs_prog_data
->instances
);
4190 hs
.DispatchGRFStartRegisterForURBData
= prog_data
->dispatch_grf_start_reg
& 0x1f;
4191 hs
.DispatchGRFStartRegisterForURBData5
= prog_data
->dispatch_grf_start_reg
>> 5;
4194 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
4195 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
4196 hs
.IncludeVertexHandles
= true;
4199 /* Patch Count threshold specifies the maximum number of patches that
4200 * will be accumulated before a thread dispatch is forced.
4202 hs
.PatchCountThreshold
= tcs_prog_data
->patch_count_threshold
;
4206 hs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
4207 hs
.IncludePrimitiveID
= tcs_prog_data
->include_primitive_id
;
4213 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
4216 iris_store_tes_state(struct iris_context
*ice
,
4217 const struct gen_device_info
*devinfo
,
4218 struct iris_compiled_shader
*shader
)
4220 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4221 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4222 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
4224 uint32_t *te_state
= (void *) shader
->derived_data
;
4225 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
4227 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
4228 te
.Partitioning
= tes_prog_data
->partitioning
;
4229 te
.OutputTopology
= tes_prog_data
->output_topology
;
4230 te
.TEDomain
= tes_prog_data
->domain
;
4232 te
.MaximumTessellationFactorOdd
= 63.0;
4233 te
.MaximumTessellationFactorNotOdd
= 64.0;
4236 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
4237 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
4239 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
4240 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
4241 ds
.ComputeWCoordinateEnable
=
4242 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
4244 ds
.UserClipDistanceCullTestEnableBitmask
=
4245 vue_prog_data
->cull_distance_mask
;
4251 * Encode most of 3DSTATE_GS based on the compiled shader.
4254 iris_store_gs_state(struct iris_context
*ice
,
4255 const struct gen_device_info
*devinfo
,
4256 struct iris_compiled_shader
*shader
)
4258 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4259 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4260 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
4262 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
4263 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
4265 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
4266 gs
.OutputTopology
= gs_prog_data
->output_topology
;
4267 gs
.ControlDataHeaderSize
=
4268 gs_prog_data
->control_data_header_size_hwords
;
4269 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
4270 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
4271 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
4272 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
4273 gs
.ReorderMode
= TRAILING
;
4274 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
4275 gs
.MaximumNumberofThreads
=
4276 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
4277 : (devinfo
->max_gs_threads
- 1);
4279 if (gs_prog_data
->static_vertex_count
!= -1) {
4280 gs
.StaticOutput
= true;
4281 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
4283 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
4285 gs
.UserClipDistanceCullTestEnableBitmask
=
4286 vue_prog_data
->cull_distance_mask
;
4288 const int urb_entry_write_offset
= 1;
4289 const uint32_t urb_entry_output_length
=
4290 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
4291 urb_entry_write_offset
;
4293 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
4294 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
4299 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
4302 iris_store_fs_state(struct iris_context
*ice
,
4303 const struct gen_device_info
*devinfo
,
4304 struct iris_compiled_shader
*shader
)
4306 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4307 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
4309 uint32_t *ps_state
= (void *) shader
->derived_data
;
4310 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
4312 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
4313 ps
.VectorMaskEnable
= true;
4314 ps
.BindingTableEntryCount
= shader
->bt
.size_bytes
/ 4;
4315 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
4316 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
4318 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
4320 /* From the documentation for this packet:
4321 * "If the PS kernel does not need the Position XY Offsets to
4322 * compute a Position Value, then this field should be programmed
4323 * to POSOFFSET_NONE."
4325 * "SW Recommendation: If the PS kernel needs the Position Offsets
4326 * to compute a Position XY value, this field should match Position
4327 * ZW Interpolation Mode to ensure a consistent position.xyzw
4330 * We only require XY sample offsets. So, this recommendation doesn't
4331 * look useful at the moment. We might need this in future.
4333 ps
.PositionXYOffsetSelect
=
4334 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
4336 if (prog_data
->total_scratch
) {
4337 struct iris_bo
*bo
=
4338 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
4339 MESA_SHADER_FRAGMENT
);
4340 uint32_t scratch_addr
= bo
->gtt_offset
;
4341 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
4342 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
4346 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
4347 psx
.PixelShaderValid
= true;
4348 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
4349 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
4350 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
4351 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
4352 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
4353 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
4354 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
4357 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
4358 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
4364 * Compute the size of the derived data (shader command packets).
4366 * This must match the data written by the iris_store_xs_state() functions.
4369 iris_store_cs_state(struct iris_context
*ice
,
4370 const struct gen_device_info
*devinfo
,
4371 struct iris_compiled_shader
*shader
)
4373 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4374 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
4375 void *map
= shader
->derived_data
;
4377 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
4378 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
4379 desc
.SharedLocalMemorySize
=
4380 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
4381 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
4382 desc
.CrossThreadConstantDataReadLength
=
4383 cs_prog_data
->push
.cross_thread
.regs
;
4385 /* TODO: Check if we are missing workarounds and enable mid-thread
4388 * We still have issues with mid-thread preemption (it was already
4389 * disabled by the kernel on gen11, due to missing workarounds). It's
4390 * possible that we are just missing some workarounds, and could enable
4391 * it later, but for now let's disable it to fix a GPU in compute in Car
4392 * Chase (and possibly more).
4394 desc
.ThreadPreemptionDisable
= true;
4400 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
4402 assert(cache_id
<= IRIS_CACHE_BLORP
);
4404 static const unsigned dwords
[] = {
4405 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
4406 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
4407 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
4408 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
4410 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
4411 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
4412 [IRIS_CACHE_BLORP
] = 0,
4415 return sizeof(uint32_t) * dwords
[cache_id
];
4419 * Create any state packets corresponding to the given shader stage
4420 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
4421 * This means that we can look up a program in the in-memory cache and
4422 * get most of the state packet without having to reconstruct it.
4425 iris_store_derived_program_state(struct iris_context
*ice
,
4426 enum iris_program_cache_id cache_id
,
4427 struct iris_compiled_shader
*shader
)
4429 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
4430 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
4434 iris_store_vs_state(ice
, devinfo
, shader
);
4436 case IRIS_CACHE_TCS
:
4437 iris_store_tcs_state(ice
, devinfo
, shader
);
4439 case IRIS_CACHE_TES
:
4440 iris_store_tes_state(ice
, devinfo
, shader
);
4443 iris_store_gs_state(ice
, devinfo
, shader
);
4446 iris_store_fs_state(ice
, devinfo
, shader
);
4449 iris_store_cs_state(ice
, devinfo
, shader
);
4450 case IRIS_CACHE_BLORP
:
4457 /* ------------------------------------------------------------------- */
4459 static const uint32_t push_constant_opcodes
[] = {
4460 [MESA_SHADER_VERTEX
] = 21,
4461 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
4462 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
4463 [MESA_SHADER_GEOMETRY
] = 22,
4464 [MESA_SHADER_FRAGMENT
] = 23,
4465 [MESA_SHADER_COMPUTE
] = 0,
4469 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
4471 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
4473 iris_use_pinned_bo(batch
, state_bo
, false);
4475 return ice
->state
.unbound_tex
.offset
;
4479 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
4481 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
4482 if (!ice
->state
.null_fb
.res
)
4483 return use_null_surface(batch
, ice
);
4485 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
4487 iris_use_pinned_bo(batch
, state_bo
, false);
4489 return ice
->state
.null_fb
.offset
;
4493 surf_state_offset_for_aux(struct iris_resource
*res
,
4495 enum isl_aux_usage aux_usage
)
4497 return SURFACE_STATE_ALIGNMENT
*
4498 util_bitcount(aux_modes
& ((1 << aux_usage
) - 1));
4503 surf_state_update_clear_value(struct iris_batch
*batch
,
4504 struct iris_resource
*res
,
4505 struct iris_state_ref
*state
,
4507 enum isl_aux_usage aux_usage
)
4509 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
4510 struct iris_bo
*state_bo
= iris_resource_bo(state
->res
);
4511 uint64_t real_offset
= state
->offset
+ IRIS_MEMZONE_BINDER_START
;
4512 uint32_t offset_into_bo
= real_offset
- state_bo
->gtt_offset
;
4513 uint32_t clear_offset
= offset_into_bo
+
4514 isl_dev
->ss
.clear_value_offset
+
4515 surf_state_offset_for_aux(res
, aux_modes
, aux_usage
);
4516 uint32_t *color
= res
->aux
.clear_color
.u32
;
4518 assert(isl_dev
->ss
.clear_value_size
== 16);
4520 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
4521 iris_emit_pipe_control_write(batch
, "update fast clear value (Z)",
4522 PIPE_CONTROL_WRITE_IMMEDIATE
,
4523 state_bo
, clear_offset
, color
[0]);
4525 iris_emit_pipe_control_write(batch
, "update fast clear color (RG__)",
4526 PIPE_CONTROL_WRITE_IMMEDIATE
,
4527 state_bo
, clear_offset
,
4528 (uint64_t) color
[0] |
4529 (uint64_t) color
[1] << 32);
4530 iris_emit_pipe_control_write(batch
, "update fast clear color (__BA)",
4531 PIPE_CONTROL_WRITE_IMMEDIATE
,
4532 state_bo
, clear_offset
+ 8,
4533 (uint64_t) color
[2] |
4534 (uint64_t) color
[3] << 32);
4537 iris_emit_pipe_control_flush(batch
,
4538 "update fast clear: state cache invalidate",
4539 PIPE_CONTROL_FLUSH_ENABLE
|
4540 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
4545 update_clear_value(struct iris_context
*ice
,
4546 struct iris_batch
*batch
,
4547 struct iris_resource
*res
,
4548 struct iris_surface_state
*surf_state
,
4549 unsigned all_aux_modes
,
4550 struct isl_view
*view
)
4552 UNUSED
struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
4553 UNUSED
unsigned aux_modes
= all_aux_modes
;
4555 /* We only need to update the clear color in the surface state for gen8 and
4556 * gen9. Newer gens can read it directly from the clear color state buffer.
4559 /* Skip updating the ISL_AUX_USAGE_NONE surface state */
4560 aux_modes
&= ~(1 << ISL_AUX_USAGE_NONE
);
4563 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4565 surf_state_update_clear_value(batch
, res
, &surf_state
->ref
,
4566 all_aux_modes
, aux_usage
);
4569 /* TODO: Could update rather than re-filling */
4570 alloc_surface_states(surf_state
, all_aux_modes
);
4572 void *map
= surf_state
->cpu
;
4575 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4576 fill_surface_state(isl_dev
, map
, res
, &res
->surf
, view
, aux_usage
,
4578 map
+= SURFACE_STATE_ALIGNMENT
;
4581 upload_surface_states(ice
->state
.surface_uploader
, surf_state
);
4586 * Add a surface to the validation list, as well as the buffer containing
4587 * the corresponding SURFACE_STATE.
4589 * Returns the binding table entry (offset to SURFACE_STATE).
4592 use_surface(struct iris_context
*ice
,
4593 struct iris_batch
*batch
,
4594 struct pipe_surface
*p_surf
,
4596 enum isl_aux_usage aux_usage
,
4597 bool is_read_surface
)
4599 struct iris_surface
*surf
= (void *) p_surf
;
4600 struct iris_resource
*res
= (void *) p_surf
->texture
;
4601 uint32_t offset
= 0;
4603 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
4604 if (GEN_GEN
== 8 && is_read_surface
) {
4605 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state_read
.ref
.res
), false);
4607 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.ref
.res
), false);
4611 iris_use_pinned_bo(batch
, res
->aux
.bo
, writeable
);
4612 if (res
->aux
.clear_color_bo
)
4613 iris_use_pinned_bo(batch
, res
->aux
.clear_color_bo
, false);
4615 if (memcmp(&res
->aux
.clear_color
, &surf
->clear_color
,
4616 sizeof(surf
->clear_color
)) != 0) {
4617 update_clear_value(ice
, batch
, res
, &surf
->surface_state
,
4618 res
->aux
.possible_usages
, &surf
->view
);
4620 update_clear_value(ice
, batch
, res
, &surf
->surface_state_read
,
4621 res
->aux
.possible_usages
, &surf
->read_view
);
4623 surf
->clear_color
= res
->aux
.clear_color
;
4627 offset
= (GEN_GEN
== 8 && is_read_surface
)
4628 ? surf
->surface_state_read
.ref
.offset
4629 : surf
->surface_state
.ref
.offset
;
4632 surf_state_offset_for_aux(res
, res
->aux
.possible_usages
, aux_usage
);
4636 use_sampler_view(struct iris_context
*ice
,
4637 struct iris_batch
*batch
,
4638 struct iris_sampler_view
*isv
)
4640 enum isl_aux_usage aux_usage
=
4641 iris_resource_texture_aux_usage(ice
, isv
->res
, isv
->view
.format
);
4643 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
4644 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.ref
.res
), false);
4646 if (isv
->res
->aux
.bo
) {
4647 iris_use_pinned_bo(batch
, isv
->res
->aux
.bo
, false);
4648 if (isv
->res
->aux
.clear_color_bo
)
4649 iris_use_pinned_bo(batch
, isv
->res
->aux
.clear_color_bo
, false);
4650 if (memcmp(&isv
->res
->aux
.clear_color
, &isv
->clear_color
,
4651 sizeof(isv
->clear_color
)) != 0) {
4652 update_clear_value(ice
, batch
, isv
->res
, &isv
->surface_state
,
4653 isv
->res
->aux
.sampler_usages
, &isv
->view
);
4654 isv
->clear_color
= isv
->res
->aux
.clear_color
;
4658 return isv
->surface_state
.ref
.offset
+
4659 surf_state_offset_for_aux(isv
->res
, isv
->res
->aux
.sampler_usages
,
4664 use_ubo_ssbo(struct iris_batch
*batch
,
4665 struct iris_context
*ice
,
4666 struct pipe_shader_buffer
*buf
,
4667 struct iris_state_ref
*surf_state
,
4670 if (!buf
->buffer
|| !surf_state
->res
)
4671 return use_null_surface(batch
, ice
);
4673 iris_use_pinned_bo(batch
, iris_resource_bo(buf
->buffer
), writable
);
4674 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
4676 return surf_state
->offset
;
4680 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
4681 struct iris_shader_state
*shs
, const struct shader_info
*info
,
4684 struct iris_image_view
*iv
= &shs
->image
[i
];
4685 struct iris_resource
*res
= (void *) iv
->base
.resource
;
4688 return use_null_surface(batch
, ice
);
4690 bool write
= iv
->base
.shader_access
& PIPE_IMAGE_ACCESS_WRITE
;
4692 iris_use_pinned_bo(batch
, res
->bo
, write
);
4693 iris_use_pinned_bo(batch
, iris_resource_bo(iv
->surface_state
.ref
.res
), false);
4696 iris_use_pinned_bo(batch
, res
->aux
.bo
, write
);
4698 enum isl_aux_usage aux_usage
=
4699 iris_image_view_aux_usage(ice
, &iv
->base
, info
);
4701 return iv
->surface_state
.ref
.offset
+
4702 surf_state_offset_for_aux(res
, res
->aux
.possible_usages
, aux_usage
);
4705 #define push_bt_entry(addr) \
4706 assert(addr >= binder_addr); \
4707 assert(s < shader->bt.size_bytes / sizeof(uint32_t)); \
4708 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
4710 #define bt_assert(section) \
4711 if (!pin_only && shader->bt.used_mask[section] != 0) \
4712 assert(shader->bt.offsets[section] == s);
4715 * Populate the binding table for a given shader stage.
4717 * This fills out the table of pointers to surfaces required by the shader,
4718 * and also adds those buffers to the validation list so the kernel can make
4719 * resident before running our batch.
4722 iris_populate_binding_table(struct iris_context
*ice
,
4723 struct iris_batch
*batch
,
4724 gl_shader_stage stage
,
4727 const struct iris_binder
*binder
= &ice
->state
.binder
;
4728 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
4729 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4733 struct iris_binding_table
*bt
= &shader
->bt
;
4734 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4735 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4736 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
4738 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
4741 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
4743 /* TCS passthrough doesn't need a binding table. */
4744 assert(stage
== MESA_SHADER_TESS_CTRL
);
4748 if (stage
== MESA_SHADER_COMPUTE
&&
4749 shader
->bt
.used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
]) {
4750 /* surface for gl_NumWorkGroups */
4751 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
4752 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
4753 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
4754 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
4755 push_bt_entry(grid_state
->offset
);
4758 if (stage
== MESA_SHADER_FRAGMENT
) {
4759 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4760 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
4761 if (cso_fb
->nr_cbufs
) {
4762 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
4764 if (cso_fb
->cbufs
[i
]) {
4765 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
], true,
4766 ice
->state
.draw_aux_usage
[i
], false);
4768 addr
= use_null_fb_surface(batch
, ice
);
4770 push_bt_entry(addr
);
4772 } else if (GEN_GEN
< 11) {
4773 uint32_t addr
= use_null_fb_surface(batch
, ice
);
4774 push_bt_entry(addr
);
4778 #define foreach_surface_used(index, group) \
4780 for (int index = 0; index < bt->sizes[group]; index++) \
4781 if (iris_group_index_to_bti(bt, group, index) != \
4782 IRIS_SURFACE_NOT_USED)
4784 foreach_surface_used(i
, IRIS_SURFACE_GROUP_RENDER_TARGET_READ
) {
4785 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4787 if (cso_fb
->cbufs
[i
]) {
4788 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
],
4789 true, ice
->state
.draw_aux_usage
[i
], true);
4790 push_bt_entry(addr
);
4794 foreach_surface_used(i
, IRIS_SURFACE_GROUP_TEXTURE
) {
4795 struct iris_sampler_view
*view
= shs
->textures
[i
];
4796 uint32_t addr
= view
? use_sampler_view(ice
, batch
, view
)
4797 : use_null_surface(batch
, ice
);
4798 push_bt_entry(addr
);
4801 foreach_surface_used(i
, IRIS_SURFACE_GROUP_IMAGE
) {
4802 uint32_t addr
= use_image(batch
, ice
, shs
, info
, i
);
4803 push_bt_entry(addr
);
4806 foreach_surface_used(i
, IRIS_SURFACE_GROUP_UBO
) {
4809 if (i
== bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] - 1) {
4810 if (ish
->const_data
) {
4811 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data
), false);
4812 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data_state
.res
),
4814 addr
= ish
->const_data_state
.offset
;
4816 /* This can only happen with INTEL_DISABLE_COMPACT_BINDING_TABLE=1. */
4817 addr
= use_null_surface(batch
, ice
);
4820 addr
= use_ubo_ssbo(batch
, ice
, &shs
->constbuf
[i
],
4821 &shs
->constbuf_surf_state
[i
], false);
4824 push_bt_entry(addr
);
4827 foreach_surface_used(i
, IRIS_SURFACE_GROUP_SSBO
) {
4829 use_ubo_ssbo(batch
, ice
, &shs
->ssbo
[i
], &shs
->ssbo_surf_state
[i
],
4830 shs
->writable_ssbos
& (1u << i
));
4831 push_bt_entry(addr
);
4835 /* XXX: YUV surfaces not implemented yet */
4836 bt_assert(plane_start
[1], ...);
4837 bt_assert(plane_start
[2], ...);
4842 iris_use_optional_res(struct iris_batch
*batch
,
4843 struct pipe_resource
*res
,
4847 struct iris_bo
*bo
= iris_resource_bo(res
);
4848 iris_use_pinned_bo(batch
, bo
, writeable
);
4853 pin_depth_and_stencil_buffers(struct iris_batch
*batch
,
4854 struct pipe_surface
*zsbuf
,
4855 struct iris_depth_stencil_alpha_state
*cso_zsa
)
4860 struct iris_resource
*zres
, *sres
;
4861 iris_get_depth_stencil_resources(zsbuf
->texture
, &zres
, &sres
);
4864 iris_use_pinned_bo(batch
, zres
->bo
, cso_zsa
->depth_writes_enabled
);
4866 iris_use_pinned_bo(batch
, zres
->aux
.bo
,
4867 cso_zsa
->depth_writes_enabled
);
4872 iris_use_pinned_bo(batch
, sres
->bo
, cso_zsa
->stencil_writes_enabled
);
4876 /* ------------------------------------------------------------------- */
4879 * Pin any BOs which were installed by a previous batch, and restored
4880 * via the hardware logical context mechanism.
4882 * We don't need to re-emit all state every batch - the hardware context
4883 * mechanism will save and restore it for us. This includes pointers to
4884 * various BOs...which won't exist unless we ask the kernel to pin them
4885 * by adding them to the validation list.
4887 * We can skip buffers if we've re-emitted those packets, as we're
4888 * overwriting those stale pointers with new ones, and don't actually
4889 * refer to the old BOs.
4892 iris_restore_render_saved_bos(struct iris_context
*ice
,
4893 struct iris_batch
*batch
,
4894 const struct pipe_draw_info
*draw
)
4896 struct iris_genx_state
*genx
= ice
->state
.genx
;
4898 const uint64_t clean
= ~ice
->state
.dirty
;
4900 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
4901 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
4904 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4905 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
4908 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
4909 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
4912 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4913 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
4916 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
4917 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
4920 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
4921 for (int i
= 0; i
< 4; i
++) {
4922 struct iris_stream_output_target
*tgt
=
4923 (void *) ice
->state
.so_target
[i
];
4925 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4927 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4933 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4934 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4937 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4938 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4943 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4945 for (int i
= 0; i
< 4; i
++) {
4946 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4948 if (range
->length
== 0)
4951 /* Range block is a binding table index, map back to UBO index. */
4952 unsigned block_index
= iris_bti_to_group_index(
4953 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
4954 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
4956 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4957 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4960 iris_use_pinned_bo(batch
, res
->bo
, false);
4962 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4966 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4967 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4968 /* Re-pin any buffers referred to by the binding table. */
4969 iris_populate_binding_table(ice
, batch
, stage
, true);
4973 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4974 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4975 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4977 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4980 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4981 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
4982 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4985 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4986 iris_use_pinned_bo(batch
, bo
, false);
4988 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4990 if (prog_data
->total_scratch
> 0) {
4991 struct iris_bo
*bo
=
4992 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4993 iris_use_pinned_bo(batch
, bo
, true);
4999 if ((clean
& IRIS_DIRTY_DEPTH_BUFFER
) &&
5000 (clean
& IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
5001 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5002 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
5005 iris_use_optional_res(batch
, ice
->state
.last_res
.index_buffer
, false);
5007 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
5008 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
5010 const int i
= u_bit_scan64(&bound
);
5011 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
5012 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
5018 iris_restore_compute_saved_bos(struct iris_context
*ice
,
5019 struct iris_batch
*batch
,
5020 const struct pipe_grid_info
*grid
)
5022 const uint64_t clean
= ~ice
->state
.dirty
;
5024 const int stage
= MESA_SHADER_COMPUTE
;
5025 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5027 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
5028 /* Re-pin any buffers referred to by the binding table. */
5029 iris_populate_binding_table(ice
, batch
, stage
, true);
5032 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
5034 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
5036 if ((clean
& IRIS_DIRTY_SAMPLER_STATES_CS
) &&
5037 (clean
& IRIS_DIRTY_BINDINGS_CS
) &&
5038 (clean
& IRIS_DIRTY_CONSTANTS_CS
) &&
5039 (clean
& IRIS_DIRTY_CS
)) {
5040 iris_use_optional_res(batch
, ice
->state
.last_res
.cs_desc
, false);
5043 if (clean
& IRIS_DIRTY_CS
) {
5044 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5047 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
5048 iris_use_pinned_bo(batch
, bo
, false);
5050 struct iris_bo
*curbe_bo
=
5051 iris_resource_bo(ice
->state
.last_res
.cs_thread_ids
);
5052 iris_use_pinned_bo(batch
, curbe_bo
, false);
5054 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5056 if (prog_data
->total_scratch
> 0) {
5057 struct iris_bo
*bo
=
5058 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
5059 iris_use_pinned_bo(batch
, bo
, true);
5066 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
5069 iris_update_surface_base_address(struct iris_batch
*batch
,
5070 struct iris_binder
*binder
)
5072 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
5075 uint32_t mocs
= batch
->screen
->isl_dev
.mocs
.internal
;
5077 flush_before_state_base_change(batch
);
5080 /* GEN:BUG:1607854226:
5082 * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
5083 * mode by putting the pipeline temporarily in 3D mode..
5085 if (batch
->name
== IRIS_BATCH_COMPUTE
)
5086 emit_pipeline_select(batch
, _3D
);
5089 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
5090 sba
.SurfaceStateBaseAddressModifyEnable
= true;
5091 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
5093 /* The hardware appears to pay attention to the MOCS fields even
5094 * if you don't set the "Address Modify Enable" bit for the base.
5096 sba
.GeneralStateMOCS
= mocs
;
5097 sba
.StatelessDataPortAccessMOCS
= mocs
;
5098 sba
.DynamicStateMOCS
= mocs
;
5099 sba
.IndirectObjectMOCS
= mocs
;
5100 sba
.InstructionMOCS
= mocs
;
5101 sba
.SurfaceStateMOCS
= mocs
;
5103 sba
.BindlessSurfaceStateMOCS
= mocs
;
5108 /* GEN:BUG:1607854226:
5110 * Put the pipeline back into compute mode.
5112 if (batch
->name
== IRIS_BATCH_COMPUTE
)
5113 emit_pipeline_select(batch
, GPGPU
);
5116 flush_after_state_base_change(batch
);
5118 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
5122 iris_viewport_zmin_zmax(const struct pipe_viewport_state
*vp
, bool halfz
,
5123 bool window_space_position
, float *zmin
, float *zmax
)
5125 if (window_space_position
) {
5130 util_viewport_zmin_zmax(vp
, halfz
, zmin
, zmax
);
5135 genX(invalidate_aux_map_state
)(struct iris_batch
*batch
)
5137 struct iris_screen
*screen
= batch
->screen
;
5138 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
5141 uint32_t aux_map_state_num
= gen_aux_map_get_state_num(aux_map_ctx
);
5142 if (batch
->last_aux_map_state
!= aux_map_state_num
) {
5143 /* HSD 1209978178: docs say that before programming the aux table:
5145 * "Driver must ensure that the engine is IDLE but ensure it doesn't
5146 * add extra flushes in the case it knows that the engine is already
5149 * An end of pipe sync is needed here, otherwise we see GPU hangs in
5150 * dEQP-GLES31.functional.copy_image.* tests.
5152 iris_emit_end_of_pipe_sync(batch
, "Invalidate aux map table",
5153 PIPE_CONTROL_CS_STALL
);
5155 /* If the aux-map state number increased, then we need to rewrite the
5156 * register. Rewriting the register is used to both set the aux-map
5157 * translation table address, and also to invalidate any previously
5158 * cached translations.
5160 iris_load_register_imm32(batch
, GENX(GFX_CCS_AUX_INV_num
), 1);
5161 batch
->last_aux_map_state
= aux_map_state_num
;
5166 init_aux_map_state(struct iris_batch
*batch
)
5168 struct iris_screen
*screen
= batch
->screen
;
5169 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
5173 uint64_t base_addr
= gen_aux_map_get_base(aux_map_ctx
);
5174 assert(base_addr
!= 0 && align64(base_addr
, 32 * 1024) == base_addr
);
5175 iris_load_register_imm64(batch
, GENX(GFX_AUX_TABLE_BASE_ADDR_num
),
5182 struct iris_address addr
;
5186 uint32_t max_length
;
5190 setup_constant_buffers(struct iris_context
*ice
,
5191 struct iris_batch
*batch
,
5193 struct push_bos
*push_bos
)
5195 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5196 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5197 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
5199 uint32_t push_range_sum
= 0;
5202 for (int i
= 0; i
< 4; i
++) {
5203 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
5205 if (range
->length
== 0)
5208 push_range_sum
+= range
->length
;
5210 if (range
->length
> push_bos
->max_length
)
5211 push_bos
->max_length
= range
->length
;
5213 /* Range block is a binding table index, map back to UBO index. */
5214 unsigned block_index
= iris_bti_to_group_index(
5215 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
5216 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
5218 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
5219 struct iris_resource
*res
= (void *) cbuf
->buffer
;
5221 assert(cbuf
->buffer_offset
% 32 == 0);
5223 push_bos
->buffers
[n
].length
= range
->length
;
5224 push_bos
->buffers
[n
].addr
=
5225 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->buffer_offset
)
5226 : batch
->screen
->workaround_address
;
5230 /* From the 3DSTATE_CONSTANT_XS and 3DSTATE_CONSTANT_ALL programming notes:
5232 * "The sum of all four read length fields must be less than or
5233 * equal to the size of 64."
5235 assert(push_range_sum
<= 64);
5237 push_bos
->buffer_count
= n
;
5241 emit_push_constant_packets(struct iris_context
*ice
,
5242 struct iris_batch
*batch
,
5244 const struct push_bos
*push_bos
)
5246 UNUSED
struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
5247 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5248 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
5250 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
5251 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
5253 pkt
.MOCS
= isl_dev
->mocs
.internal
;
5256 /* The Skylake PRM contains the following restriction:
5258 * "The driver must ensure The following case does not occur
5259 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
5260 * buffer 3 read length equal to zero committed followed by a
5261 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
5264 * To avoid this, we program the buffers in the highest slots.
5265 * This way, slot 0 is only used if slot 3 is also used.
5267 int n
= push_bos
->buffer_count
;
5269 const unsigned shift
= 4 - n
;
5270 for (int i
= 0; i
< n
; i
++) {
5271 pkt
.ConstantBody
.ReadLength
[i
+ shift
] =
5272 push_bos
->buffers
[i
].length
;
5273 pkt
.ConstantBody
.Buffer
[i
+ shift
] = push_bos
->buffers
[i
].addr
;
5281 emit_push_constant_packet_all(struct iris_context
*ice
,
5282 struct iris_batch
*batch
,
5283 uint32_t shader_mask
,
5284 const struct push_bos
*push_bos
)
5286 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
5289 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_ALL
), pc
) {
5290 pc
.ShaderUpdateEnable
= shader_mask
;
5295 const uint32_t n
= push_bos
->buffer_count
;
5296 const uint32_t max_pointers
= 4;
5297 const uint32_t num_dwords
= 2 + 2 * n
;
5298 uint32_t const_all
[2 + 2 * max_pointers
];
5299 uint32_t *dw
= &const_all
[0];
5301 assert(n
<= max_pointers
);
5302 iris_pack_command(GENX(3DSTATE_CONSTANT_ALL
), dw
, all
) {
5303 all
.DWordLength
= num_dwords
- 2;
5304 all
.MOCS
= isl_dev
->mocs
.internal
;
5305 all
.ShaderUpdateEnable
= shader_mask
;
5306 all
.PointerBufferMask
= (1 << n
) - 1;
5310 for (int i
= 0; i
< n
; i
++) {
5311 _iris_pack_state(batch
, GENX(3DSTATE_CONSTANT_ALL_DATA
),
5313 data
.PointerToConstantBuffer
= push_bos
->buffers
[i
].addr
;
5314 data
.ConstantBufferReadLength
= push_bos
->buffers
[i
].length
;
5317 iris_batch_emit(batch
, const_all
, sizeof(uint32_t) * num_dwords
);
5322 iris_upload_dirty_render_state(struct iris_context
*ice
,
5323 struct iris_batch
*batch
,
5324 const struct pipe_draw_info
*draw
)
5326 const uint64_t dirty
= ice
->state
.dirty
;
5328 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
5331 struct iris_genx_state
*genx
= ice
->state
.genx
;
5332 struct iris_binder
*binder
= &ice
->state
.binder
;
5333 struct brw_wm_prog_data
*wm_prog_data
= (void *)
5334 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
5336 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
5337 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5338 uint32_t cc_vp_address
;
5340 /* XXX: could avoid streaming for depth_clip [0,1] case. */
5341 uint32_t *cc_vp_map
=
5342 stream_state(batch
, ice
->state
.dynamic_uploader
,
5343 &ice
->state
.last_res
.cc_vp
,
5344 4 * ice
->state
.num_viewports
*
5345 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
5346 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
5348 iris_viewport_zmin_zmax(&ice
->state
.viewports
[i
], cso_rast
->clip_halfz
,
5349 ice
->state
.window_space_position
,
5351 if (cso_rast
->depth_clip_near
)
5353 if (cso_rast
->depth_clip_far
)
5356 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
5357 ccv
.MinimumDepth
= zmin
;
5358 ccv
.MaximumDepth
= zmax
;
5361 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
5364 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
5365 ptr
.CCViewportPointer
= cc_vp_address
;
5369 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
5370 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5371 uint32_t sf_cl_vp_address
;
5373 stream_state(batch
, ice
->state
.dynamic_uploader
,
5374 &ice
->state
.last_res
.sf_cl_vp
,
5375 4 * ice
->state
.num_viewports
*
5376 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
5378 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
5379 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
5380 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
5382 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
5383 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
5384 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
5385 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
5387 gen_calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
5388 state
->scale
[0], state
->scale
[1],
5389 state
->translate
[0], state
->translate
[1],
5390 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
5392 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
5393 vp
.ViewportMatrixElementm00
= state
->scale
[0];
5394 vp
.ViewportMatrixElementm11
= state
->scale
[1];
5395 vp
.ViewportMatrixElementm22
= state
->scale
[2];
5396 vp
.ViewportMatrixElementm30
= state
->translate
[0];
5397 vp
.ViewportMatrixElementm31
= state
->translate
[1];
5398 vp
.ViewportMatrixElementm32
= state
->translate
[2];
5399 vp
.XMinClipGuardband
= gb_xmin
;
5400 vp
.XMaxClipGuardband
= gb_xmax
;
5401 vp
.YMinClipGuardband
= gb_ymin
;
5402 vp
.YMaxClipGuardband
= gb_ymax
;
5403 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
5404 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
5405 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
5406 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
5409 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
5412 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
5413 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
5417 if (dirty
& IRIS_DIRTY_URB
) {
5420 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
5421 if (!ice
->shaders
.prog
[i
]) {
5424 struct brw_vue_prog_data
*vue_prog_data
=
5425 (void *) ice
->shaders
.prog
[i
]->prog_data
;
5426 size
[i
] = vue_prog_data
->urb_entry_size
;
5428 assert(size
[i
] != 0);
5431 unsigned entries
[4], start
[4];
5432 gen_get_urb_config(&batch
->screen
->devinfo
,
5433 batch
->screen
->l3_config_3d
,
5434 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
5435 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
5436 size
, entries
, start
,
5437 &ice
->state
.urb_deref_block_size
);
5439 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
5440 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
5441 urb
._3DCommandSubOpcode
+= i
;
5442 urb
.VSURBStartingAddress
= start
[i
];
5443 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
5444 urb
.VSNumberofURBEntries
= entries
[i
];
5449 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
5450 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
5451 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5452 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
5453 const int header_dwords
= GENX(BLEND_STATE_length
);
5455 /* Always write at least one BLEND_STATE - the final RT message will
5456 * reference BLEND_STATE[0] even if there aren't color writes. There
5457 * may still be alpha testing, computed depth, and so on.
5459 const int rt_dwords
=
5460 MAX2(cso_fb
->nr_cbufs
, 1) * GENX(BLEND_STATE_ENTRY_length
);
5462 uint32_t blend_offset
;
5463 uint32_t *blend_map
=
5464 stream_state(batch
, ice
->state
.dynamic_uploader
,
5465 &ice
->state
.last_res
.blend
,
5466 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
5468 uint32_t blend_state_header
;
5469 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
5470 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
5471 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
5474 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
5475 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
5477 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
5478 ptr
.BlendStatePointer
= blend_offset
;
5479 ptr
.BlendStatePointerValid
= true;
5483 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
5484 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
5486 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
5490 stream_state(batch
, ice
->state
.dynamic_uploader
,
5491 &ice
->state
.last_res
.color_calc
,
5492 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
5494 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
5495 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
5496 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
5497 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
5498 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
5499 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
5500 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
5502 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
5503 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
5506 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
5507 ptr
.ColorCalcStatePointer
= cc_offset
;
5508 ptr
.ColorCalcStatePointerValid
= true;
5512 /* GEN:BUG:1604061319
5514 * 3DSTATE_CONSTANT_* needs to be programmed before BTP_*
5516 * Testing shows that all the 3DSTATE_CONSTANT_XS need to be emitted if
5517 * any stage has a dirty binding table.
5519 const bool emit_const_wa
= GEN_GEN
>= 11 &&
5520 (dirty
& IRIS_ALL_DIRTY_BINDINGS
) != 0;
5523 uint32_t nobuffer_stages
= 0;
5526 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5527 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)) &&
5531 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5532 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5537 if (shs
->sysvals_need_upload
)
5538 upload_sysvals(ice
, stage
);
5540 struct push_bos push_bos
= {};
5541 setup_constant_buffers(ice
, batch
, stage
, &push_bos
);
5544 /* If this stage doesn't have any push constants, emit it later in a
5545 * single CONSTANT_ALL packet with all the other stages.
5547 if (push_bos
.buffer_count
== 0) {
5548 nobuffer_stages
|= 1 << stage
;
5552 /* The Constant Buffer Read Length field from 3DSTATE_CONSTANT_ALL
5553 * contains only 5 bits, so we can only use it for buffers smaller than
5556 if (push_bos
.max_length
< 32) {
5557 emit_push_constant_packet_all(ice
, batch
, 1 << stage
, &push_bos
);
5561 emit_push_constant_packets(ice
, batch
, stage
, &push_bos
);
5565 if (nobuffer_stages
)
5566 emit_push_constant_packet_all(ice
, batch
, nobuffer_stages
, NULL
);
5569 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5570 /* Gen9 requires 3DSTATE_BINDING_TABLE_POINTERS_XS to be re-emitted
5571 * in order to commit constants. TODO: Investigate "Disable Gather
5572 * at Set Shader" to go back to legacy mode...
5574 if (dirty
& ((IRIS_DIRTY_BINDINGS_VS
|
5575 (GEN_GEN
== 9 ? IRIS_DIRTY_CONSTANTS_VS
: 0)) << stage
)) {
5576 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
5577 ptr
._3DCommandSubOpcode
= 38 + stage
;
5578 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
5583 if (GEN_GEN
>= 11 && (dirty
& IRIS_DIRTY_RENDER_BUFFER
)) {
5584 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
5585 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
5587 /* The PIPE_CONTROL command description says:
5589 * "Whenever a Binding Table Index (BTI) used by a Render Target
5590 * Message points to a different RENDER_SURFACE_STATE, SW must issue a
5591 * Render Target Cache Flush by enabling this bit. When render target
5592 * flush is set due to new association of BTI, PS Scoreboard Stall bit
5593 * must be set in this packet."
5595 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
5596 iris_emit_pipe_control_flush(batch
, "workaround: RT BTI change [draw]",
5597 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5598 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
5601 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5602 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
5603 iris_populate_binding_table(ice
, batch
, stage
, false);
5607 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5608 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
5609 !ice
->shaders
.prog
[stage
])
5612 iris_upload_sampler_states(ice
, stage
);
5614 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5615 struct pipe_resource
*res
= shs
->sampler_table
.res
;
5617 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
5619 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
5620 ptr
._3DCommandSubOpcode
= 43 + stage
;
5621 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
5625 if (ice
->state
.need_border_colors
)
5626 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
5628 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
5629 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
5631 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
5632 if (ice
->state
.framebuffer
.samples
> 0)
5633 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
5637 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
5638 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
5639 ms
.SampleMask
= ice
->state
.sample_mask
;
5643 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5644 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
5647 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5650 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5651 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
5652 iris_use_pinned_bo(batch
, cache
->bo
, false);
5654 if (prog_data
->total_scratch
> 0) {
5655 struct iris_bo
*bo
=
5656 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
5657 iris_use_pinned_bo(batch
, bo
, true);
5660 if (stage
== MESA_SHADER_FRAGMENT
) {
5661 UNUSED
struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5662 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5664 uint32_t ps_state
[GENX(3DSTATE_PS_length
)] = {0};
5665 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
5666 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
5667 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
5668 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
5670 /* The docs for 3DSTATE_PS::32 Pixel Dispatch Enable say:
5672 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16,
5673 * SIMD32 Dispatch must not be enabled for PER_PIXEL dispatch
5676 * 16x MSAA only exists on Gen9+, so we can skip this on Gen8.
5678 if (GEN_GEN
>= 9 && cso_fb
->samples
== 16 &&
5679 !wm_prog_data
->persample_dispatch
) {
5680 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
5681 ps
._32PixelDispatchEnable
= false;
5684 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
5685 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
5686 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
5687 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
5688 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
5689 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
5691 ps
.KernelStartPointer0
= KSP(shader
) +
5692 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
5693 ps
.KernelStartPointer1
= KSP(shader
) +
5694 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
5695 ps
.KernelStartPointer2
= KSP(shader
) +
5696 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
5699 uint32_t psx_state
[GENX(3DSTATE_PS_EXTRA_length
)] = {0};
5700 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
5702 if (!wm_prog_data
->uses_sample_mask
)
5703 psx
.InputCoverageMaskState
= ICMS_NONE
;
5704 else if (wm_prog_data
->post_depth_coverage
)
5705 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
5706 else if (wm_prog_data
->inner_coverage
&&
5707 cso
->conservative_rasterization
)
5708 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
5710 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
5712 psx
.PixelShaderUsesInputCoverageMask
=
5713 wm_prog_data
->uses_sample_mask
;
5717 uint32_t *shader_ps
= (uint32_t *) shader
->derived_data
;
5718 uint32_t *shader_psx
= shader_ps
+ GENX(3DSTATE_PS_length
);
5719 iris_emit_merge(batch
, shader_ps
, ps_state
,
5720 GENX(3DSTATE_PS_length
));
5721 iris_emit_merge(batch
, shader_psx
, psx_state
,
5722 GENX(3DSTATE_PS_EXTRA_length
));
5724 iris_batch_emit(batch
, shader
->derived_data
,
5725 iris_derived_program_state_size(stage
));
5728 if (stage
== MESA_SHADER_TESS_EVAL
) {
5729 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
5730 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
5731 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
5732 } else if (stage
== MESA_SHADER_GEOMETRY
) {
5733 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
5738 if (ice
->state
.streamout_active
) {
5739 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
5740 iris_batch_emit(batch
, genx
->so_buffers
,
5741 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
5742 for (int i
= 0; i
< 4; i
++) {
5743 struct iris_stream_output_target
*tgt
=
5744 (void *) ice
->state
.so_target
[i
];
5747 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
5749 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
5755 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
5756 uint32_t *decl_list
=
5757 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
5758 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
5761 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
5762 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5764 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
5765 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
5766 sol
.SOFunctionEnable
= true;
5767 sol
.SOStatisticsEnable
= true;
5769 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
5770 !ice
->state
.prims_generated_query_active
;
5771 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
5774 assert(ice
->state
.streamout
);
5776 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
5777 GENX(3DSTATE_STREAMOUT_length
));
5780 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
5781 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
5785 if (dirty
& IRIS_DIRTY_CLIP
) {
5786 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5787 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5789 bool gs_or_tes
= ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] ||
5790 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
5791 bool points_or_lines
= cso_rast
->fill_mode_point_or_line
||
5792 (gs_or_tes
? ice
->shaders
.output_topology_is_points_or_lines
5793 : ice
->state
.prim_is_points_or_lines
);
5795 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
5796 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
5797 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5798 if (cso_rast
->rasterizer_discard
)
5799 cl
.ClipMode
= CLIPMODE_REJECT_ALL
;
5800 else if (ice
->state
.window_space_position
)
5801 cl
.ClipMode
= CLIPMODE_ACCEPT_ALL
;
5803 cl
.ClipMode
= CLIPMODE_NORMAL
;
5805 cl
.PerspectiveDivideDisable
= ice
->state
.window_space_position
;
5806 cl
.ViewportXYClipTestEnable
= !points_or_lines
;
5808 if (wm_prog_data
->barycentric_interp_modes
&
5809 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
5810 cl
.NonPerspectiveBarycentricEnable
= true;
5812 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
<= 1;
5813 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
5815 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
5816 ARRAY_SIZE(cso_rast
->clip
));
5819 if (dirty
& (IRIS_DIRTY_RASTER
| IRIS_DIRTY_URB
)) {
5820 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5821 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
5823 uint32_t dynamic_sf
[GENX(3DSTATE_SF_length
)];
5824 iris_pack_command(GENX(3DSTATE_SF
), &dynamic_sf
, sf
) {
5825 sf
.ViewportTransformEnable
= !ice
->state
.window_space_position
;
5828 sf
.DerefBlockSize
= ice
->state
.urb_deref_block_size
;
5831 iris_emit_merge(batch
, cso
->sf
, dynamic_sf
,
5832 ARRAY_SIZE(dynamic_sf
));
5835 if (dirty
& IRIS_DIRTY_WM
) {
5836 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5837 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
5839 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
5840 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5842 wm
.BarycentricInterpolationMode
=
5843 wm_prog_data
->barycentric_interp_modes
;
5845 if (wm_prog_data
->early_fragment_tests
)
5846 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
5847 else if (wm_prog_data
->has_side_effects
)
5848 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
5850 /* We could skip this bit if color writes are enabled. */
5851 if (wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
)
5852 wm
.ForceThreadDispatchEnable
= ForceON
;
5854 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
5857 if (dirty
& IRIS_DIRTY_SBE
) {
5858 iris_emit_sbe(batch
, ice
);
5861 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
5862 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
5863 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
5864 const struct shader_info
*fs_info
=
5865 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
5867 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
5868 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
5869 pb
.HasWriteableRT
= has_writeable_rt(cso_blend
, fs_info
);
5870 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
5872 /* The dual source blending docs caution against using SRC1 factors
5873 * when the shader doesn't use a dual source render target write.
5874 * Empirically, this can lead to GPU hangs, and the results are
5875 * undefined anyway, so simply disable blending to avoid the hang.
5877 pb
.ColorBufferBlendEnable
= (cso_blend
->blend_enables
& 1) &&
5878 (!cso_blend
->dual_color_blending
|| wm_prog_data
->dual_src_blend
);
5881 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
5882 ARRAY_SIZE(cso_blend
->ps_blend
));
5885 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
5886 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
5887 #if GEN_GEN >= 9 && GEN_GEN < 12
5888 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
5889 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
5890 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
5891 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
5892 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
5894 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
5896 /* Use modify disable fields which allow us to emit packets
5897 * directly instead of merging them later.
5899 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
5903 iris_batch_emit(batch
, cso
->depth_bounds
, sizeof(cso
->depth_bounds
));
5907 if (dirty
& IRIS_DIRTY_STENCIL_REF
) {
5909 /* Use modify disable fields which allow us to emit packets
5910 * directly instead of merging them later.
5912 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
5913 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
5914 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
5915 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
5916 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
5917 wmds
.StencilTestMaskModifyDisable
= true;
5918 wmds
.StencilWriteMaskModifyDisable
= true;
5919 wmds
.StencilStateModifyDisable
= true;
5920 wmds
.DepthStateModifyDisable
= true;
5922 iris_batch_emit(batch
, stencil_refs
, sizeof(stencil_refs
));
5926 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
5927 uint32_t scissor_offset
=
5928 emit_state(batch
, ice
->state
.dynamic_uploader
,
5929 &ice
->state
.last_res
.scissor
,
5930 ice
->state
.scissors
,
5931 sizeof(struct pipe_scissor_state
) *
5932 ice
->state
.num_viewports
, 32);
5934 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
5935 ptr
.ScissorRectPointer
= scissor_offset
;
5939 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
5940 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
5942 /* Do not emit the clear params yets. We need to update the clear value
5945 uint32_t clear_length
= GENX(3DSTATE_CLEAR_PARAMS_length
) * 4;
5946 uint32_t cso_z_size
= batch
->screen
->isl_dev
.ds
.size
- clear_length
;;
5949 /* GEN:BUG:14010455700
5951 * ISL will change some CHICKEN registers depending on the depth surface
5952 * format, along with emitting the depth and stencil packets. In that
5953 * case, we want to do a depth flush and stall, so the pipeline is not
5954 * using these settings while we change the registers.
5956 iris_emit_end_of_pipe_sync(batch
,
5957 "Workaround: Stop pipeline for 14010455700",
5958 PIPE_CONTROL_DEPTH_STALL
|
5959 PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
5962 iris_batch_emit(batch
, cso_z
->packets
, cso_z_size
);
5963 if (GEN_GEN
>= 12) {
5964 /* GEN:BUG:1408224581
5966 * Workaround: Gen12LP Astep only An additional pipe control with
5967 * post-sync = store dword operation would be required.( w/a is to
5968 * have an additional pipe control after the stencil state whenever
5969 * the surface state bits of this state is changing).
5971 iris_emit_pipe_control_write(batch
, "WA for stencil state",
5972 PIPE_CONTROL_WRITE_IMMEDIATE
,
5973 batch
->screen
->workaround_address
.bo
,
5974 batch
->screen
->workaround_address
.offset
, 0);
5977 union isl_color_value clear_value
= { .f32
= { 0, } };
5979 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5980 if (cso_fb
->zsbuf
) {
5981 struct iris_resource
*zres
, *sres
;
5982 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
5984 if (zres
&& zres
->aux
.bo
)
5985 clear_value
= iris_resource_get_clear_color(zres
, NULL
, NULL
);
5988 uint32_t clear_params
[GENX(3DSTATE_CLEAR_PARAMS_length
)];
5989 iris_pack_command(GENX(3DSTATE_CLEAR_PARAMS
), clear_params
, clear
) {
5990 clear
.DepthClearValueValid
= true;
5991 clear
.DepthClearValue
= clear_value
.f32
[0];
5993 iris_batch_emit(batch
, clear_params
, clear_length
);
5996 if (dirty
& (IRIS_DIRTY_DEPTH_BUFFER
| IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
5997 /* Listen for buffer changes, and also write enable changes. */
5998 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5999 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
6002 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
6003 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
6004 for (int i
= 0; i
< 32; i
++) {
6005 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
6010 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
6011 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
6012 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
6015 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
6016 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
6017 topo
.PrimitiveTopologyType
=
6018 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
6022 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
6023 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
6024 uint64_t dynamic_bound
= ice
->state
.bound_vertex_buffers
;
6026 if (ice
->state
.vs_uses_draw_params
) {
6027 assert(ice
->draw
.draw_params
.res
);
6029 struct iris_vertex_buffer_state
*state
=
6030 &(ice
->state
.genx
->vertex_buffers
[count
]);
6031 pipe_resource_reference(&state
->resource
, ice
->draw
.draw_params
.res
);
6032 struct iris_resource
*res
= (void *) state
->resource
;
6034 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
6035 vb
.VertexBufferIndex
= count
;
6036 vb
.AddressModifyEnable
= true;
6038 vb
.BufferSize
= res
->bo
->size
- ice
->draw
.draw_params
.offset
;
6039 vb
.BufferStartingAddress
=
6040 ro_bo(NULL
, res
->bo
->gtt_offset
+
6041 (int) ice
->draw
.draw_params
.offset
);
6042 vb
.MOCS
= iris_mocs(res
->bo
, &batch
->screen
->isl_dev
);
6044 dynamic_bound
|= 1ull << count
;
6048 if (ice
->state
.vs_uses_derived_draw_params
) {
6049 struct iris_vertex_buffer_state
*state
=
6050 &(ice
->state
.genx
->vertex_buffers
[count
]);
6051 pipe_resource_reference(&state
->resource
,
6052 ice
->draw
.derived_draw_params
.res
);
6053 struct iris_resource
*res
= (void *) ice
->draw
.derived_draw_params
.res
;
6055 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
6056 vb
.VertexBufferIndex
= count
;
6057 vb
.AddressModifyEnable
= true;
6060 res
->bo
->size
- ice
->draw
.derived_draw_params
.offset
;
6061 vb
.BufferStartingAddress
=
6062 ro_bo(NULL
, res
->bo
->gtt_offset
+
6063 (int) ice
->draw
.derived_draw_params
.offset
);
6064 vb
.MOCS
= iris_mocs(res
->bo
, &batch
->screen
->isl_dev
);
6066 dynamic_bound
|= 1ull << count
;
6072 /* Gen11+ doesn't need the cache workaround below */
6073 uint64_t bound
= dynamic_bound
;
6075 const int i
= u_bit_scan64(&bound
);
6076 iris_use_optional_res(batch
, genx
->vertex_buffers
[i
].resource
,
6080 /* The VF cache designers cut corners, and made the cache key's
6081 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
6082 * 32 bits of the address. If you have two vertex buffers which get
6083 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
6084 * you can get collisions (even within a single batch).
6086 * So, we need to do a VF cache invalidate if the buffer for a VB
6087 * slot slot changes [48:32] address bits from the previous time.
6089 unsigned flush_flags
= 0;
6091 uint64_t bound
= dynamic_bound
;
6093 const int i
= u_bit_scan64(&bound
);
6094 uint16_t high_bits
= 0;
6096 struct iris_resource
*res
=
6097 (void *) genx
->vertex_buffers
[i
].resource
;
6099 iris_use_pinned_bo(batch
, res
->bo
, false);
6101 high_bits
= res
->bo
->gtt_offset
>> 32ull;
6102 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
6103 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
|
6104 PIPE_CONTROL_CS_STALL
;
6105 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
6111 iris_emit_pipe_control_flush(batch
,
6112 "workaround: VF cache 32-bit key [VB]",
6117 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
6120 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
6121 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
6122 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
6126 bound
= dynamic_bound
;
6128 const int i
= u_bit_scan64(&bound
);
6129 memcpy(map
, genx
->vertex_buffers
[i
].state
,
6130 sizeof(uint32_t) * vb_dwords
);
6136 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
6137 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
6138 const unsigned entries
= MAX2(cso
->count
, 1);
6139 if (!(ice
->state
.vs_needs_sgvs_element
||
6140 ice
->state
.vs_uses_derived_draw_params
||
6141 ice
->state
.vs_needs_edge_flag
)) {
6142 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
6143 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
6145 uint32_t dynamic_ves
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
6146 const unsigned dyn_count
= cso
->count
+
6147 ice
->state
.vs_needs_sgvs_element
+
6148 ice
->state
.vs_uses_derived_draw_params
;
6150 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
),
6153 1 + GENX(VERTEX_ELEMENT_STATE_length
) * dyn_count
- 2;
6155 memcpy(&dynamic_ves
[1], &cso
->vertex_elements
[1],
6156 (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
6157 GENX(VERTEX_ELEMENT_STATE_length
) * sizeof(uint32_t));
6158 uint32_t *ve_pack_dest
=
6159 &dynamic_ves
[1 + (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
6160 GENX(VERTEX_ELEMENT_STATE_length
)];
6162 if (ice
->state
.vs_needs_sgvs_element
) {
6163 uint32_t base_ctrl
= ice
->state
.vs_uses_draw_params
?
6164 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
6165 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
6167 ve
.VertexBufferIndex
=
6168 util_bitcount64(ice
->state
.bound_vertex_buffers
);
6169 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
6170 ve
.Component0Control
= base_ctrl
;
6171 ve
.Component1Control
= base_ctrl
;
6172 ve
.Component2Control
= VFCOMP_STORE_0
;
6173 ve
.Component3Control
= VFCOMP_STORE_0
;
6175 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
6177 if (ice
->state
.vs_uses_derived_draw_params
) {
6178 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
6180 ve
.VertexBufferIndex
=
6181 util_bitcount64(ice
->state
.bound_vertex_buffers
) +
6182 ice
->state
.vs_uses_draw_params
;
6183 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
6184 ve
.Component0Control
= VFCOMP_STORE_SRC
;
6185 ve
.Component1Control
= VFCOMP_STORE_SRC
;
6186 ve
.Component2Control
= VFCOMP_STORE_0
;
6187 ve
.Component3Control
= VFCOMP_STORE_0
;
6189 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
6191 if (ice
->state
.vs_needs_edge_flag
) {
6192 for (int i
= 0; i
< GENX(VERTEX_ELEMENT_STATE_length
); i
++)
6193 ve_pack_dest
[i
] = cso
->edgeflag_ve
[i
];
6196 iris_batch_emit(batch
, &dynamic_ves
, sizeof(uint32_t) *
6197 (1 + dyn_count
* GENX(VERTEX_ELEMENT_STATE_length
)));
6200 if (!ice
->state
.vs_needs_edge_flag
) {
6201 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
6202 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
6204 assert(cso
->count
> 0);
6205 const unsigned edgeflag_index
= cso
->count
- 1;
6206 uint32_t dynamic_vfi
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
6207 memcpy(&dynamic_vfi
[0], cso
->vf_instancing
, edgeflag_index
*
6208 GENX(3DSTATE_VF_INSTANCING_length
) * sizeof(uint32_t));
6210 uint32_t *vfi_pack_dest
= &dynamic_vfi
[0] +
6211 edgeflag_index
* GENX(3DSTATE_VF_INSTANCING_length
);
6212 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
6213 vi
.VertexElementIndex
= edgeflag_index
+
6214 ice
->state
.vs_needs_sgvs_element
+
6215 ice
->state
.vs_uses_derived_draw_params
;
6217 for (int i
= 0; i
< GENX(3DSTATE_VF_INSTANCING_length
); i
++)
6218 vfi_pack_dest
[i
] |= cso
->edgeflag_vfi
[i
];
6220 iris_batch_emit(batch
, &dynamic_vfi
[0], sizeof(uint32_t) *
6221 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
6225 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
6226 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
6227 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
6228 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
6230 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
6231 if (vs_prog_data
->uses_vertexid
) {
6232 sgv
.VertexIDEnable
= true;
6233 sgv
.VertexIDComponentNumber
= 2;
6234 sgv
.VertexIDElementOffset
=
6235 cso
->count
- ice
->state
.vs_needs_edge_flag
;
6238 if (vs_prog_data
->uses_instanceid
) {
6239 sgv
.InstanceIDEnable
= true;
6240 sgv
.InstanceIDComponentNumber
= 3;
6241 sgv
.InstanceIDElementOffset
=
6242 cso
->count
- ice
->state
.vs_needs_edge_flag
;
6247 if (dirty
& IRIS_DIRTY_VF
) {
6248 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
6249 if (draw
->primitive_restart
) {
6250 vf
.IndexedDrawCutIndexEnable
= true;
6251 vf
.CutIndex
= draw
->restart_index
;
6256 if (dirty
& IRIS_DIRTY_VF_STATISTICS
) {
6257 iris_emit_cmd(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
6258 vf
.StatisticsEnable
= true;
6263 if (dirty
& IRIS_DIRTY_PMA_FIX
) {
6264 bool enable
= want_pma_fix(ice
);
6265 genX(update_pma_fix
)(ice
, batch
, enable
);
6269 if (ice
->state
.current_hash_scale
!= 1)
6270 genX(emit_hashing_mode
)(ice
, batch
, UINT_MAX
, UINT_MAX
, 1);
6273 genX(invalidate_aux_map_state
)(batch
);
6278 iris_upload_render_state(struct iris_context
*ice
,
6279 struct iris_batch
*batch
,
6280 const struct pipe_draw_info
*draw
)
6282 bool use_predicate
= ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
6284 /* Always pin the binder. If we're emitting new binding table pointers,
6285 * we need it. If not, we're probably inheriting old tables via the
6286 * context, and need it anyway. Since true zero-bindings cases are
6287 * practically non-existent, just pin it and avoid last_res tracking.
6289 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
6291 if (!batch
->contains_draw
) {
6292 iris_restore_render_saved_bos(ice
, batch
, draw
);
6293 batch
->contains_draw
= true;
6296 iris_upload_dirty_render_state(ice
, batch
, draw
);
6298 if (draw
->index_size
> 0) {
6301 if (draw
->has_user_indices
) {
6302 u_upload_data(ice
->ctx
.stream_uploader
, 0,
6303 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
6304 &offset
, &ice
->state
.last_res
.index_buffer
);
6306 struct iris_resource
*res
= (void *) draw
->index
.resource
;
6307 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
6309 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
6310 draw
->index
.resource
);
6314 struct iris_genx_state
*genx
= ice
->state
.genx
;
6315 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
6317 uint32_t ib_packet
[GENX(3DSTATE_INDEX_BUFFER_length
)];
6318 iris_pack_command(GENX(3DSTATE_INDEX_BUFFER
), ib_packet
, ib
) {
6319 ib
.IndexFormat
= draw
->index_size
>> 1;
6320 ib
.MOCS
= iris_mocs(bo
, &batch
->screen
->isl_dev
);
6321 ib
.BufferSize
= bo
->size
- offset
;
6322 ib
.BufferStartingAddress
= ro_bo(NULL
, bo
->gtt_offset
+ offset
);
6325 if (memcmp(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
)) != 0) {
6326 memcpy(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
));
6327 iris_batch_emit(batch
, ib_packet
, sizeof(ib_packet
));
6328 iris_use_pinned_bo(batch
, bo
, false);
6332 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
6333 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
6334 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
6335 iris_emit_pipe_control_flush(batch
,
6336 "workaround: VF cache 32-bit key [IB]",
6337 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
6338 PIPE_CONTROL_CS_STALL
);
6339 ice
->state
.last_index_bo_high_bits
= high_bits
;
6344 #define _3DPRIM_END_OFFSET 0x2420
6345 #define _3DPRIM_START_VERTEX 0x2430
6346 #define _3DPRIM_VERTEX_COUNT 0x2434
6347 #define _3DPRIM_INSTANCE_COUNT 0x2438
6348 #define _3DPRIM_START_INSTANCE 0x243C
6349 #define _3DPRIM_BASE_VERTEX 0x2440
6351 if (draw
->indirect
) {
6352 if (draw
->indirect
->indirect_draw_count
) {
6353 use_predicate
= true;
6355 struct iris_bo
*draw_count_bo
=
6356 iris_resource_bo(draw
->indirect
->indirect_draw_count
);
6357 unsigned draw_count_offset
=
6358 draw
->indirect
->indirect_draw_count_offset
;
6360 iris_emit_pipe_control_flush(batch
,
6361 "ensure indirect draw buffer is flushed",
6362 PIPE_CONTROL_FLUSH_ENABLE
);
6364 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
) {
6365 struct gen_mi_builder b
;
6366 gen_mi_builder_init(&b
, batch
);
6368 /* comparison = draw id < draw count */
6369 struct gen_mi_value comparison
=
6370 gen_mi_ult(&b
, gen_mi_imm(draw
->drawid
),
6371 gen_mi_mem32(ro_bo(draw_count_bo
,
6372 draw_count_offset
)));
6374 /* predicate = comparison & conditional rendering predicate */
6375 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_RESULT
),
6376 gen_mi_iand(&b
, comparison
,
6377 gen_mi_reg32(CS_GPR(15))));
6379 uint32_t mi_predicate
;
6381 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
6382 iris_load_register_imm64(batch
, MI_PREDICATE_SRC1
, draw
->drawid
);
6383 /* Upload the current draw count from the draw parameters buffer
6384 * to MI_PREDICATE_SRC0.
6386 iris_load_register_mem32(batch
, MI_PREDICATE_SRC0
,
6387 draw_count_bo
, draw_count_offset
);
6388 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
6389 iris_load_register_imm32(batch
, MI_PREDICATE_SRC0
+ 4, 0);
6391 if (draw
->drawid
== 0) {
6392 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
6393 MI_PREDICATE_COMBINEOP_SET
|
6394 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
6396 /* While draw_index < draw_count the predicate's result will be
6397 * (draw_index == draw_count) ^ TRUE = TRUE
6398 * When draw_index == draw_count the result is
6399 * (TRUE) ^ TRUE = FALSE
6400 * After this all results will be:
6401 * (FALSE) ^ FALSE = FALSE
6403 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOAD
|
6404 MI_PREDICATE_COMBINEOP_XOR
|
6405 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
6407 iris_batch_emit(batch
, &mi_predicate
, sizeof(uint32_t));
6410 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
6413 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6414 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
6415 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
6417 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6418 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
6419 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
6421 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6422 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
6423 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
6425 if (draw
->index_size
) {
6426 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6427 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
6428 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
6430 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6431 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
6432 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
6435 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6436 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
6437 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
6439 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
6440 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
6444 } else if (draw
->count_from_stream_output
) {
6445 struct iris_stream_output_target
*so
=
6446 (void *) draw
->count_from_stream_output
;
6448 /* XXX: Replace with actual cache tracking */
6449 iris_emit_pipe_control_flush(batch
,
6450 "draw count from stream output stall",
6451 PIPE_CONTROL_CS_STALL
);
6453 struct gen_mi_builder b
;
6454 gen_mi_builder_init(&b
, batch
);
6456 struct iris_address addr
=
6457 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
6458 struct gen_mi_value offset
=
6459 gen_mi_iadd_imm(&b
, gen_mi_mem32(addr
), -so
->base
.buffer_offset
);
6461 gen_mi_store(&b
, gen_mi_reg32(_3DPRIM_VERTEX_COUNT
),
6462 gen_mi_udiv32_imm(&b
, offset
, so
->stride
));
6464 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
6465 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
6466 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
6467 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
6470 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
6471 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
6472 prim
.PredicateEnable
= use_predicate
;
6474 if (draw
->indirect
|| draw
->count_from_stream_output
) {
6475 prim
.IndirectParameterEnable
= true;
6477 prim
.StartInstanceLocation
= draw
->start_instance
;
6478 prim
.InstanceCount
= draw
->instance_count
;
6479 prim
.VertexCountPerInstance
= draw
->count
;
6481 prim
.StartVertexLocation
= draw
->start
;
6483 if (draw
->index_size
) {
6484 prim
.BaseVertexLocation
+= draw
->index_bias
;
6486 prim
.StartVertexLocation
+= draw
->index_bias
;
6493 iris_upload_compute_state(struct iris_context
*ice
,
6494 struct iris_batch
*batch
,
6495 const struct pipe_grid_info
*grid
)
6497 const uint64_t dirty
= ice
->state
.dirty
;
6498 struct iris_screen
*screen
= batch
->screen
;
6499 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
6500 struct iris_binder
*binder
= &ice
->state
.binder
;
6501 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
6502 struct iris_compiled_shader
*shader
=
6503 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
6504 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
6505 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
6507 const uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
6508 const unsigned simd_size
=
6509 brw_cs_simd_size_for_group_size(devinfo
, cs_prog_data
, group_size
);
6510 const unsigned threads
= DIV_ROUND_UP(group_size
, simd_size
);
6512 /* Always pin the binder. If we're emitting new binding table pointers,
6513 * we need it. If not, we're probably inheriting old tables via the
6514 * context, and need it anyway. Since true zero-bindings cases are
6515 * practically non-existent, just pin it and avoid last_res tracking.
6517 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
6519 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->sysvals_need_upload
)
6520 upload_sysvals(ice
, MESA_SHADER_COMPUTE
);
6522 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
6523 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
6525 if (dirty
& IRIS_DIRTY_SAMPLER_STATES_CS
)
6526 iris_upload_sampler_states(ice
, MESA_SHADER_COMPUTE
);
6528 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
6529 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
6531 if (ice
->state
.need_border_colors
)
6532 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
6535 genX(invalidate_aux_map_state
)(batch
);
6538 if (dirty
& IRIS_DIRTY_CS
) {
6539 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
6541 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
6542 * the only bits that are changed are scoreboard related: Scoreboard
6543 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
6544 * these scoreboard related states, a MEDIA_STATE_FLUSH is
6547 iris_emit_pipe_control_flush(batch
,
6548 "workaround: stall before MEDIA_VFE_STATE",
6549 PIPE_CONTROL_CS_STALL
);
6551 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
6552 if (prog_data
->total_scratch
) {
6553 struct iris_bo
*bo
=
6554 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
6555 MESA_SHADER_COMPUTE
);
6556 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
6557 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
6560 vfe
.MaximumNumberofThreads
=
6561 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
6563 vfe
.ResetGatewayTimer
=
6564 Resettingrelativetimerandlatchingtheglobaltimestamp
;
6567 vfe
.BypassGatewayControl
= true;
6569 vfe
.NumberofURBEntries
= 2;
6570 vfe
.URBEntryAllocationSize
= 2;
6572 vfe
.CURBEAllocationSize
=
6573 ALIGN(cs_prog_data
->push
.per_thread
.regs
* threads
+
6574 cs_prog_data
->push
.cross_thread
.regs
, 2);
6578 /* TODO: Combine subgroup-id with cbuf0 so we can push regular uniforms */
6579 if (dirty
& IRIS_DIRTY_CS
) {
6580 uint32_t curbe_data_offset
= 0;
6581 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
6582 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
6583 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
6584 const unsigned push_const_size
=
6585 brw_cs_push_const_total_size(cs_prog_data
, threads
);
6586 uint32_t *curbe_data_map
=
6587 stream_state(batch
, ice
->state
.dynamic_uploader
,
6588 &ice
->state
.last_res
.cs_thread_ids
,
6589 ALIGN(push_const_size
, 64), 64,
6590 &curbe_data_offset
);
6591 assert(curbe_data_map
);
6592 memset(curbe_data_map
, 0x5a, ALIGN(push_const_size
, 64));
6593 iris_fill_cs_push_const_buffer(cs_prog_data
, threads
, curbe_data_map
);
6595 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
6596 curbe
.CURBETotalDataLength
= ALIGN(push_const_size
, 64);
6597 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
6601 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
6602 IRIS_DIRTY_BINDINGS_CS
|
6603 IRIS_DIRTY_CONSTANTS_CS
|
6605 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
6607 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
6608 idd
.KernelStartPointer
=
6609 KSP(shader
) + brw_cs_prog_data_prog_offset(cs_prog_data
, simd_size
);
6610 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
6611 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
6612 idd
.NumberofThreadsinGPGPUThreadGroup
= threads
;
6615 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
6616 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
6618 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
6619 load
.InterfaceDescriptorTotalLength
=
6620 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
6621 load
.InterfaceDescriptorDataStartAddress
=
6622 emit_state(batch
, ice
->state
.dynamic_uploader
,
6623 &ice
->state
.last_res
.cs_desc
, desc
, sizeof(desc
), 64);
6627 uint32_t remainder
= group_size
& (simd_size
- 1);
6628 uint32_t right_mask
;
6631 right_mask
= ~0u >> (32 - remainder
);
6633 right_mask
= ~0u >> (32 - simd_size
);
6635 #define GPGPU_DISPATCHDIMX 0x2500
6636 #define GPGPU_DISPATCHDIMY 0x2504
6637 #define GPGPU_DISPATCHDIMZ 0x2508
6639 if (grid
->indirect
) {
6640 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
6641 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
6642 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6643 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
6644 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
6646 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6647 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
6648 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
6650 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6651 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
6652 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
6656 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
6657 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
6658 ggw
.SIMDSize
= simd_size
/ 16;
6659 ggw
.ThreadDepthCounterMaximum
= 0;
6660 ggw
.ThreadHeightCounterMaximum
= 0;
6661 ggw
.ThreadWidthCounterMaximum
= threads
- 1;
6662 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
6663 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
6664 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
6665 ggw
.RightExecutionMask
= right_mask
;
6666 ggw
.BottomExecutionMask
= 0xffffffff;
6669 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
6671 if (!batch
->contains_draw
) {
6672 iris_restore_compute_saved_bos(ice
, batch
, grid
);
6673 batch
->contains_draw
= true;
6678 * State module teardown.
6681 iris_destroy_state(struct iris_context
*ice
)
6683 struct iris_genx_state
*genx
= ice
->state
.genx
;
6685 pipe_resource_reference(&ice
->draw
.draw_params
.res
, NULL
);
6686 pipe_resource_reference(&ice
->draw
.derived_draw_params
.res
, NULL
);
6688 /* Loop over all VBOs, including ones for draw parameters */
6689 for (unsigned i
= 0; i
< ARRAY_SIZE(genx
->vertex_buffers
); i
++) {
6690 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
6693 free(ice
->state
.genx
);
6695 for (int i
= 0; i
< 4; i
++) {
6696 pipe_so_target_reference(&ice
->state
.so_target
[i
], NULL
);
6699 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
6700 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
6702 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
6704 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
6705 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
6706 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
6707 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
6708 pipe_resource_reference(&shs
->constbuf
[i
].buffer
, NULL
);
6709 pipe_resource_reference(&shs
->constbuf_surf_state
[i
].res
, NULL
);
6711 for (int i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
6712 pipe_resource_reference(&shs
->image
[i
].base
.resource
, NULL
);
6713 pipe_resource_reference(&shs
->image
[i
].surface_state
.ref
.res
, NULL
);
6714 free(shs
->image
[i
].surface_state
.cpu
);
6716 for (int i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
6717 pipe_resource_reference(&shs
->ssbo
[i
].buffer
, NULL
);
6718 pipe_resource_reference(&shs
->ssbo_surf_state
[i
].res
, NULL
);
6720 for (int i
= 0; i
< IRIS_MAX_TEXTURE_SAMPLERS
; i
++) {
6721 pipe_sampler_view_reference((struct pipe_sampler_view
**)
6722 &shs
->textures
[i
], NULL
);
6726 pipe_resource_reference(&ice
->state
.grid_size
.res
, NULL
);
6727 pipe_resource_reference(&ice
->state
.grid_surf_state
.res
, NULL
);
6729 pipe_resource_reference(&ice
->state
.null_fb
.res
, NULL
);
6730 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
6732 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
6733 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
6734 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
6735 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
6736 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
6737 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
6738 pipe_resource_reference(&ice
->state
.last_res
.cs_thread_ids
, NULL
);
6739 pipe_resource_reference(&ice
->state
.last_res
.cs_desc
, NULL
);
6742 /* ------------------------------------------------------------------- */
6745 iris_rebind_buffer(struct iris_context
*ice
,
6746 struct iris_resource
*res
)
6748 struct pipe_context
*ctx
= &ice
->ctx
;
6749 struct iris_genx_state
*genx
= ice
->state
.genx
;
6751 assert(res
->base
.target
== PIPE_BUFFER
);
6753 /* Buffers can't be framebuffer attachments, nor display related,
6754 * and we don't have upstream Clover support.
6756 assert(!(res
->bind_history
& (PIPE_BIND_DEPTH_STENCIL
|
6757 PIPE_BIND_RENDER_TARGET
|
6758 PIPE_BIND_BLENDABLE
|
6759 PIPE_BIND_DISPLAY_TARGET
|
6761 PIPE_BIND_COMPUTE_RESOURCE
|
6762 PIPE_BIND_GLOBAL
)));
6764 if (res
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
6765 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
6767 const int i
= u_bit_scan64(&bound_vbs
);
6768 struct iris_vertex_buffer_state
*state
= &genx
->vertex_buffers
[i
];
6770 /* Update the CPU struct */
6771 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_start
) == 32);
6772 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) == 64);
6773 uint64_t *addr
= (uint64_t *) &state
->state
[1];
6774 struct iris_bo
*bo
= iris_resource_bo(state
->resource
);
6776 if (*addr
!= bo
->gtt_offset
+ state
->offset
) {
6777 *addr
= bo
->gtt_offset
+ state
->offset
;
6778 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
6783 /* We don't need to handle PIPE_BIND_INDEX_BUFFER here: we re-emit
6784 * the 3DSTATE_INDEX_BUFFER packet whenever the address changes.
6786 * There is also no need to handle these:
6787 * - PIPE_BIND_COMMAND_ARGS_BUFFER (emitted for every indirect draw)
6788 * - PIPE_BIND_QUERY_BUFFER (no persistent state references)
6791 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
6792 /* XXX: be careful about resetting vs appending... */
6796 for (int s
= MESA_SHADER_VERTEX
; s
< MESA_SHADER_STAGES
; s
++) {
6797 struct iris_shader_state
*shs
= &ice
->state
.shaders
[s
];
6798 enum pipe_shader_type p_stage
= stage_to_pipe(s
);
6800 if (!(res
->bind_stages
& (1 << s
)))
6803 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
6804 /* Skip constant buffer 0, it's for regular uniforms, not UBOs */
6805 uint32_t bound_cbufs
= shs
->bound_cbufs
& ~1u;
6806 while (bound_cbufs
) {
6807 const int i
= u_bit_scan(&bound_cbufs
);
6808 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[i
];
6809 struct iris_state_ref
*surf_state
= &shs
->constbuf_surf_state
[i
];
6811 if (res
->bo
== iris_resource_bo(cbuf
->buffer
)) {
6812 pipe_resource_reference(&surf_state
->res
, NULL
);
6813 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< s
;
6818 if (res
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
6819 uint32_t bound_ssbos
= shs
->bound_ssbos
;
6820 while (bound_ssbos
) {
6821 const int i
= u_bit_scan(&bound_ssbos
);
6822 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[i
];
6824 if (res
->bo
== iris_resource_bo(ssbo
->buffer
)) {
6825 struct pipe_shader_buffer buf
= {
6826 .buffer
= &res
->base
,
6827 .buffer_offset
= ssbo
->buffer_offset
,
6828 .buffer_size
= ssbo
->buffer_size
,
6830 iris_set_shader_buffers(ctx
, p_stage
, i
, 1, &buf
,
6831 (shs
->writable_ssbos
>> i
) & 1);
6836 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
6837 uint32_t bound_sampler_views
= shs
->bound_sampler_views
;
6838 while (bound_sampler_views
) {
6839 const int i
= u_bit_scan(&bound_sampler_views
);
6840 struct iris_sampler_view
*isv
= shs
->textures
[i
];
6841 struct iris_bo
*bo
= isv
->res
->bo
;
6843 if (update_surface_state_addrs(ice
->state
.surface_uploader
,
6844 &isv
->surface_state
, bo
)) {
6845 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< s
;
6850 if (res
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
6851 uint32_t bound_image_views
= shs
->bound_image_views
;
6852 while (bound_image_views
) {
6853 const int i
= u_bit_scan(&bound_image_views
);
6854 struct iris_image_view
*iv
= &shs
->image
[i
];
6855 struct iris_bo
*bo
= iris_resource_bo(iv
->base
.resource
);
6857 if (update_surface_state_addrs(ice
->state
.surface_uploader
,
6858 &iv
->surface_state
, bo
)) {
6859 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< s
;
6866 /* ------------------------------------------------------------------- */
6869 flags_to_post_sync_op(uint32_t flags
)
6871 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
6872 return WriteImmediateData
;
6874 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
6875 return WritePSDepthCount
;
6877 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
6878 return WriteTimestamp
;
6884 * Do the given flags have a Post Sync or LRI Post Sync operation?
6886 static enum pipe_control_flags
6887 get_post_sync_flags(enum pipe_control_flags flags
)
6889 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
6890 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6891 PIPE_CONTROL_WRITE_TIMESTAMP
|
6892 PIPE_CONTROL_LRI_POST_SYNC_OP
;
6894 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
6895 * "LRI Post Sync Operation". So more than one bit set would be illegal.
6897 assert(util_bitcount(flags
) <= 1);
6902 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
6905 * Emit a series of PIPE_CONTROL commands, taking into account any
6906 * workarounds necessary to actually accomplish the caller's request.
6908 * Unless otherwise noted, spec quotations in this function come from:
6910 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
6911 * Restrictions for PIPE_CONTROL.
6913 * You should not use this function directly. Use the helpers in
6914 * iris_pipe_control.c instead, which may split the pipe control further.
6917 iris_emit_raw_pipe_control(struct iris_batch
*batch
,
6924 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6925 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
6926 enum pipe_control_flags non_lri_post_sync_flags
=
6927 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
6929 /* Recursive PIPE_CONTROL workarounds --------------------------------
6930 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
6932 * We do these first because we want to look at the original operation,
6933 * rather than any workarounds we set.
6935 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
6936 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
6937 * lists several workarounds:
6939 * "Project: SKL, KBL, BXT
6941 * If the VF Cache Invalidation Enable is set to a 1 in a
6942 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
6943 * sets to 0, with the VF Cache Invalidation Enable set to 0
6944 * needs to be sent prior to the PIPE_CONTROL with VF Cache
6945 * Invalidation Enable set to a 1."
6947 iris_emit_raw_pipe_control(batch
,
6948 "workaround: recursive VF cache invalidate",
6952 /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
6953 * invalidates the instruction cache
6955 if (GEN_GEN
== 12 && (flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
)) {
6956 iris_emit_raw_pipe_control(batch
,
6957 "workaround: CS stall before instruction "
6959 PIPE_CONTROL_CS_STALL
|
6960 PIPE_CONTROL_STALL_AT_SCOREBOARD
, bo
, offset
,
6964 if ((GEN_GEN
== 9 || (GEN_GEN
== 12 && devinfo
->revision
== 0 /* A0*/)) &&
6965 IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
6966 /* Project: SKL / Argument: LRI Post Sync Operation [23]
6968 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6969 * programmed prior to programming a PIPECONTROL command with "LRI
6970 * Post Sync Operation" in GPGPU mode of operation (i.e when
6971 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
6973 * The same text exists a few rows below for Post Sync Op.
6975 * On Gen12 this is GEN:BUG:1607156449.
6977 iris_emit_raw_pipe_control(batch
,
6978 "workaround: CS stall before gpgpu post-sync",
6979 PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
6982 /* "Flush Types" workarounds ---------------------------------------------
6983 * We do these now because they may add post-sync operations or CS stalls.
6986 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
6987 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
6989 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
6990 * 'Write PS Depth Count' or 'Write Timestamp'."
6993 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6994 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6995 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6996 bo
= batch
->screen
->workaround_address
.bo
;
6997 offset
= batch
->screen
->workaround_address
.offset
;
7001 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
7002 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
7004 * "This bit must be DISABLED for operations other than writing
7007 * This seems like nonsense. An Ivybridge workaround requires us to
7008 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
7009 * operation. Gen8+ requires us to emit depth stalls and depth cache
7010 * flushes together. So, it's hard to imagine this means anything other
7011 * than "we originally intended this to be used for PS_DEPTH_COUNT".
7013 * We ignore the supposed restriction and do nothing.
7017 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
7018 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
7019 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
7021 * "This bit must be DISABLED for End-of-pipe (Read) fences,
7022 * PS_DEPTH_COUNT or TIMESTAMP queries."
7024 * TODO: Implement end-of-pipe checking.
7026 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
7027 PIPE_CONTROL_WRITE_TIMESTAMP
)));
7030 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
7031 /* From the PIPE_CONTROL instruction table, bit 1:
7033 * "This bit is ignored if Depth Stall Enable is set.
7034 * Further, the render cache is not flushed even if Write Cache
7035 * Flush Enable bit is set."
7037 * We assert that the caller doesn't do this combination, to try and
7038 * prevent mistakes. It shouldn't hurt the GPU, though.
7040 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
7041 * and "Render Target Flush" combo is explicitly required for BTI
7042 * update workarounds.
7044 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
7045 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
7048 /* PIPE_CONTROL page workarounds ------------------------------------- */
7050 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
7051 /* From the PIPE_CONTROL page itself:
7054 * Restriction: Pipe_control with CS-stall bit set must be issued
7055 * before a pipe-control command that has the State Cache
7056 * Invalidate bit set."
7058 flags
|= PIPE_CONTROL_CS_STALL
;
7061 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
7062 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
7065 * SW must always program Post-Sync Operation to "Write Immediate
7066 * Data" when Flush LLC is set."
7068 * For now, we just require the caller to do it.
7070 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
7073 /* "Post-Sync Operation" workarounds -------------------------------- */
7075 /* Project: All / Argument: Global Snapshot Count Reset [19]
7077 * "This bit must not be exercised on any product.
7078 * Requires stall bit ([20] of DW1) set."
7080 * We don't use this, so we just assert that it isn't used. The
7081 * PIPE_CONTROL instruction page indicates that they intended this
7082 * as a debug feature and don't think it is useful in production,
7083 * but it may actually be usable, should we ever want to.
7085 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
7087 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
7088 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
7089 /* Project: All / Arguments:
7091 * - Generic Media State Clear [16]
7092 * - Indirect State Pointers Disable [16]
7094 * "Requires stall bit ([20] of DW1) set."
7096 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
7097 * State Clear) says:
7099 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
7100 * programmed prior to programming a PIPECONTROL command with "Media
7101 * State Clear" set in GPGPU mode of operation"
7103 * This is a subset of the earlier rule, so there's nothing to do.
7105 flags
|= PIPE_CONTROL_CS_STALL
;
7108 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
7109 /* Project: All / Argument: Store Data Index
7111 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
7114 * For now, we just assert that the caller does this. We might want to
7115 * automatically add a write to the workaround BO...
7117 assert(non_lri_post_sync_flags
!= 0);
7120 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
7121 /* Project: All / Argument: Sync GFDT
7123 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
7124 * than '0' or 0x2520[13] must be set."
7126 * For now, we just assert that the caller does this.
7128 assert(non_lri_post_sync_flags
!= 0);
7131 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
7132 /* Project: IVB+ / Argument: TLB inv
7134 * "Requires stall bit ([20] of DW1) set."
7136 * Also, from the PIPE_CONTROL instruction table:
7139 * Post Sync Operation or CS stall must be set to ensure a TLB
7140 * invalidation occurs. Otherwise no cycle will occur to the TLB
7141 * cache to invalidate."
7143 * This is not a subset of the earlier rule, so there's nothing to do.
7145 flags
|= PIPE_CONTROL_CS_STALL
;
7148 if (GEN_GEN
>= 12 && ((flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) ||
7149 (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
))) {
7150 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
7153 * Unified Cache (Tile Cache Disabled):
7155 * When the Color and Depth (Z) streams are enabled to be cached in
7156 * the DC space of L2, Software must use "Render Target Cache Flush
7157 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
7158 * Flush" for getting the color and depth (Z) write data to be
7159 * globally observable. In this mode of operation it is not required
7160 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
7162 flags
|= PIPE_CONTROL_TILE_CACHE_FLUSH
;
7165 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
7166 /* TODO: The big Skylake GT4 post sync op workaround */
7169 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
7171 if (IS_COMPUTE_PIPELINE(batch
)) {
7172 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
7173 /* Project: SKL+ / Argument: Tex Invalidate
7174 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
7176 flags
|= PIPE_CONTROL_CS_STALL
;
7179 if (GEN_GEN
== 8 && (post_sync_flags
||
7180 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
7181 PIPE_CONTROL_DEPTH_STALL
|
7182 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
7183 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
7184 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
7185 /* Project: BDW / Arguments:
7187 * - LRI Post Sync Operation [23]
7188 * - Post Sync Op [15:14]
7190 * - Depth Stall [13]
7191 * - Render Target Cache Flush [12]
7192 * - Depth Cache Flush [0]
7193 * - DC Flush Enable [5]
7195 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
7198 flags
|= PIPE_CONTROL_CS_STALL
;
7200 /* Also, from the PIPE_CONTROL instruction table, bit 20:
7203 * This bit must be always set when PIPE_CONTROL command is
7204 * programmed by GPGPU and MEDIA workloads, except for the cases
7205 * when only Read Only Cache Invalidation bits are set (State
7206 * Cache Invalidation Enable, Instruction cache Invalidation
7207 * Enable, Texture Cache Invalidation Enable, Constant Cache
7208 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
7209 * need not implemented when FF_DOP_CG is disable via "Fixed
7210 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
7212 * It sounds like we could avoid CS stalls in some cases, but we
7213 * don't currently bother. This list isn't exactly the list above,
7219 /* "Stall" workarounds ----------------------------------------------
7220 * These have to come after the earlier ones because we may have added
7221 * some additional CS stalls above.
7224 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
7225 /* Project: PRE-SKL, VLV, CHV
7227 * "[All Stepping][All SKUs]:
7229 * One of the following must also be set:
7231 * - Render Target Cache Flush Enable ([12] of DW1)
7232 * - Depth Cache Flush Enable ([0] of DW1)
7233 * - Stall at Pixel Scoreboard ([1] of DW1)
7234 * - Depth Stall ([13] of DW1)
7235 * - Post-Sync Operation ([13] of DW1)
7236 * - DC Flush Enable ([5] of DW1)"
7238 * If we don't already have one of those bits set, we choose to add
7239 * "Stall at Pixel Scoreboard". Some of the other bits require a
7240 * CS stall as a workaround (see above), which would send us into
7241 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
7242 * appears to be safe, so we choose that.
7244 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
7245 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
7246 PIPE_CONTROL_WRITE_IMMEDIATE
|
7247 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
7248 PIPE_CONTROL_WRITE_TIMESTAMP
|
7249 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
7250 PIPE_CONTROL_DEPTH_STALL
|
7251 PIPE_CONTROL_DATA_CACHE_FLUSH
;
7252 if (!(flags
& wa_bits
))
7253 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
7256 if (GEN_GEN
>= 12 && (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
)) {
7257 /* GEN:BUG:1409600907:
7259 * "PIPE_CONTROL with Depth Stall Enable bit must be set
7260 * with any PIPE_CONTROL with Depth Flush Enable bit set.
7262 flags
|= PIPE_CONTROL_DEPTH_STALL
;
7265 /* Emit --------------------------------------------------------------- */
7267 if (INTEL_DEBUG
& DEBUG_PIPE_CONTROL
) {
7269 " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64
"]: %s\n",
7270 (flags
& PIPE_CONTROL_FLUSH_ENABLE
) ? "PipeCon " : "",
7271 (flags
& PIPE_CONTROL_CS_STALL
) ? "CS " : "",
7272 (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) ? "Scoreboard " : "",
7273 (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) ? "VF " : "",
7274 (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) ? "RT " : "",
7275 (flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
) ? "Const " : "",
7276 (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
) ? "TC " : "",
7277 (flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
) ? "DC " : "",
7278 (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
) ? "ZFlush " : "",
7279 (flags
& PIPE_CONTROL_DEPTH_STALL
) ? "ZStall " : "",
7280 (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
) ? "State " : "",
7281 (flags
& PIPE_CONTROL_TLB_INVALIDATE
) ? "TLB " : "",
7282 (flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
) ? "Inst " : "",
7283 (flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
) ? "MediaClear " : "",
7284 (flags
& PIPE_CONTROL_NOTIFY_ENABLE
) ? "Notify " : "",
7285 (flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) ?
7287 (flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
) ?
7289 (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
) ? "WriteImm " : "",
7290 (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
) ? "WriteZCount " : "",
7291 (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
) ? "WriteTimestamp " : "",
7292 (flags
& PIPE_CONTROL_FLUSH_HDC
) ? "HDC " : "",
7296 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
7298 pc
.TileCacheFlushEnable
= flags
& PIPE_CONTROL_TILE_CACHE_FLUSH
;
7301 pc
.HDCPipelineFlushEnable
= flags
& PIPE_CONTROL_FLUSH_HDC
;
7303 pc
.LRIPostSyncOperation
= NoLRIOperation
;
7304 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
7305 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
7306 pc
.StoreDataIndex
= 0;
7307 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
7308 pc
.GlobalSnapshotCountReset
=
7309 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
7310 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
7311 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
7312 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
7313 pc
.RenderTargetCacheFlushEnable
=
7314 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
7315 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
7316 pc
.StateCacheInvalidationEnable
=
7317 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
7318 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
7319 pc
.ConstantCacheInvalidationEnable
=
7320 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
7321 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
7322 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
7323 pc
.InstructionCacheInvalidateEnable
=
7324 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
7325 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
7326 pc
.IndirectStatePointersDisable
=
7327 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
7328 pc
.TextureCacheInvalidationEnable
=
7329 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
7330 pc
.Address
= rw_bo(bo
, offset
);
7331 pc
.ImmediateData
= imm
;
7337 * Preemption on Gen9 has to be enabled or disabled in various cases.
7339 * See these workarounds for preemption:
7340 * - WaDisableMidObjectPreemptionForGSLineStripAdj
7341 * - WaDisableMidObjectPreemptionForTrifanOrPolygon
7342 * - WaDisableMidObjectPreemptionForLineLoop
7345 * We don't put this in the vtable because it's only used on Gen9.
7348 gen9_toggle_preemption(struct iris_context
*ice
,
7349 struct iris_batch
*batch
,
7350 const struct pipe_draw_info
*draw
)
7352 struct iris_genx_state
*genx
= ice
->state
.genx
;
7353 bool object_preemption
= true;
7355 /* WaDisableMidObjectPreemptionForGSLineStripAdj
7357 * "WA: Disable mid-draw preemption when draw-call is a linestrip_adj
7358 * and GS is enabled."
7360 if (draw
->mode
== PIPE_PRIM_LINE_STRIP_ADJACENCY
&&
7361 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
7362 object_preemption
= false;
7364 /* WaDisableMidObjectPreemptionForTrifanOrPolygon
7366 * "TriFan miscompare in Execlist Preemption test. Cut index that is
7367 * on a previous context. End the previous, the resume another context
7368 * with a tri-fan or polygon, and the vertex count is corrupted. If we
7369 * prempt again we will cause corruption.
7371 * WA: Disable mid-draw preemption when draw-call has a tri-fan."
7373 if (draw
->mode
== PIPE_PRIM_TRIANGLE_FAN
)
7374 object_preemption
= false;
7376 /* WaDisableMidObjectPreemptionForLineLoop
7378 * "VF Stats Counters Missing a vertex when preemption enabled.
7380 * WA: Disable mid-draw preemption when the draw uses a lineloop
7383 if (draw
->mode
== PIPE_PRIM_LINE_LOOP
)
7384 object_preemption
= false;
7388 * "VF is corrupting GAFS data when preempted on an instance boundary
7389 * and replayed with instancing enabled.
7391 * WA: Disable preemption when using instanceing."
7393 if (draw
->instance_count
> 1)
7394 object_preemption
= false;
7396 if (genx
->object_preemption
!= object_preemption
) {
7397 iris_enable_obj_preemption(batch
, object_preemption
);
7398 genx
->object_preemption
= object_preemption
;
7404 iris_lost_genx_state(struct iris_context
*ice
, struct iris_batch
*batch
)
7406 struct iris_genx_state
*genx
= ice
->state
.genx
;
7408 memset(genx
->last_index_buffer
, 0, sizeof(genx
->last_index_buffer
));
7412 iris_emit_mi_report_perf_count(struct iris_batch
*batch
,
7414 uint32_t offset_in_bytes
,
7417 iris_emit_cmd(batch
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
7418 mi_rpc
.MemoryAddress
= rw_bo(bo
, offset_in_bytes
);
7419 mi_rpc
.ReportID
= report_id
;
7424 * Update the pixel hashing modes that determine the balancing of PS threads
7425 * across subslices and slices.
7427 * \param width Width bound of the rendering area (already scaled down if \p
7428 * scale is greater than 1).
7429 * \param height Height bound of the rendering area (already scaled down if \p
7430 * scale is greater than 1).
7431 * \param scale The number of framebuffer samples that could potentially be
7432 * affected by an individual channel of the PS thread. This is
7433 * typically one for single-sampled rendering, but for operations
7434 * like CCS resolves and fast clears a single PS invocation may
7435 * update a huge number of pixels, in which case a finer
7436 * balancing is desirable in order to maximally utilize the
7437 * bandwidth available. UINT_MAX can be used as shorthand for
7438 * "finest hashing mode available".
7441 genX(emit_hashing_mode
)(struct iris_context
*ice
, struct iris_batch
*batch
,
7442 unsigned width
, unsigned height
, unsigned scale
)
7445 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
7446 const unsigned slice_hashing
[] = {
7447 /* Because all Gen9 platforms with more than one slice require
7448 * three-way subslice hashing, a single "normal" 16x16 slice hashing
7449 * block is guaranteed to suffer from substantial imbalance, with one
7450 * subslice receiving twice as much work as the other two in the
7453 * The performance impact of that would be particularly severe when
7454 * three-way hashing is also in use for slice balancing (which is the
7455 * case for all Gen9 GT4 platforms), because one of the slices
7456 * receives one every three 16x16 blocks in either direction, which
7457 * is roughly the periodicity of the underlying subslice imbalance
7458 * pattern ("roughly" because in reality the hardware's
7459 * implementation of three-way hashing doesn't do exact modulo 3
7460 * arithmetic, which somewhat decreases the magnitude of this effect
7461 * in practice). This leads to a systematic subslice imbalance
7462 * within that slice regardless of the size of the primitive. The
7463 * 32x32 hashing mode guarantees that the subslice imbalance within a
7464 * single slice hashing block is minimal, largely eliminating this
7468 /* Finest slice hashing mode available. */
7471 const unsigned subslice_hashing
[] = {
7472 /* 16x16 would provide a slight cache locality benefit especially
7473 * visible in the sampler L1 cache efficiency of low-bandwidth
7474 * non-LLC platforms, but it comes at the cost of greater subslice
7475 * imbalance for primitives of dimensions approximately intermediate
7476 * between 16x4 and 16x16.
7479 /* Finest subslice hashing mode available. */
7482 /* Dimensions of the smallest hashing block of a given hashing mode. If
7483 * the rendering area is smaller than this there can't possibly be any
7484 * benefit from switching to this mode, so we optimize out the
7487 const unsigned min_size
[][2] = {
7491 const unsigned idx
= scale
> 1;
7493 if (width
> min_size
[idx
][0] || height
> min_size
[idx
][1]) {
7496 iris_pack_state(GENX(GT_MODE
), >_mode
, reg
) {
7497 reg
.SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0);
7498 reg
.SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0);
7499 reg
.SubsliceHashing
= subslice_hashing
[idx
];
7500 reg
.SubsliceHashingMask
= -1;
7503 iris_emit_raw_pipe_control(batch
,
7504 "workaround: CS stall before GT_MODE LRI",
7505 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
7506 PIPE_CONTROL_CS_STALL
,
7509 iris_emit_lri(batch
, GT_MODE
, gt_mode
);
7511 ice
->state
.current_hash_scale
= scale
;
7517 iris_set_frontend_noop(struct pipe_context
*ctx
, bool enable
)
7519 struct iris_context
*ice
= (struct iris_context
*) ctx
;
7521 ice
->state
.dirty
|= iris_batch_prepare_noop(&ice
->batches
[IRIS_BATCH_RENDER
],
7523 IRIS_ALL_DIRTY_FOR_RENDER
);
7524 ice
->state
.dirty
|= iris_batch_prepare_noop(&ice
->batches
[IRIS_BATCH_COMPUTE
],
7526 IRIS_ALL_DIRTY_FOR_COMPUTE
);
7530 genX(init_state
)(struct iris_context
*ice
)
7532 struct pipe_context
*ctx
= &ice
->ctx
;
7533 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
7535 ctx
->create_blend_state
= iris_create_blend_state
;
7536 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
7537 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
7538 ctx
->create_sampler_state
= iris_create_sampler_state
;
7539 ctx
->create_sampler_view
= iris_create_sampler_view
;
7540 ctx
->create_surface
= iris_create_surface
;
7541 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
7542 ctx
->bind_blend_state
= iris_bind_blend_state
;
7543 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
7544 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
7545 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
7546 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
7547 ctx
->delete_blend_state
= iris_delete_state
;
7548 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
7549 ctx
->delete_rasterizer_state
= iris_delete_state
;
7550 ctx
->delete_sampler_state
= iris_delete_state
;
7551 ctx
->delete_vertex_elements_state
= iris_delete_state
;
7552 ctx
->set_blend_color
= iris_set_blend_color
;
7553 ctx
->set_clip_state
= iris_set_clip_state
;
7554 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
7555 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
7556 ctx
->set_shader_images
= iris_set_shader_images
;
7557 ctx
->set_sampler_views
= iris_set_sampler_views
;
7558 ctx
->set_tess_state
= iris_set_tess_state
;
7559 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
7560 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
7561 ctx
->set_sample_mask
= iris_set_sample_mask
;
7562 ctx
->set_scissor_states
= iris_set_scissor_states
;
7563 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
7564 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
7565 ctx
->set_viewport_states
= iris_set_viewport_states
;
7566 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
7567 ctx
->surface_destroy
= iris_surface_destroy
;
7568 ctx
->draw_vbo
= iris_draw_vbo
;
7569 ctx
->launch_grid
= iris_launch_grid
;
7570 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
7571 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
7572 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
7573 ctx
->set_frontend_noop
= iris_set_frontend_noop
;
7575 screen
->vtbl
.destroy_state
= iris_destroy_state
;
7576 screen
->vtbl
.init_render_context
= iris_init_render_context
;
7577 screen
->vtbl
.init_compute_context
= iris_init_compute_context
;
7578 screen
->vtbl
.upload_render_state
= iris_upload_render_state
;
7579 screen
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
7580 screen
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
7581 screen
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
7582 screen
->vtbl
.emit_mi_report_perf_count
= iris_emit_mi_report_perf_count
;
7583 screen
->vtbl
.rebind_buffer
= iris_rebind_buffer
;
7584 screen
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
7585 screen
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
7586 screen
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
7587 screen
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
7588 screen
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
7589 screen
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
7590 screen
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
7591 screen
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
7592 screen
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
7593 screen
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
7594 screen
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
7595 screen
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
7596 screen
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
7597 screen
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
7598 screen
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
7599 screen
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
7600 screen
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
7601 screen
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
7602 screen
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
7603 screen
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
7604 screen
->vtbl
.lost_genx_state
= iris_lost_genx_state
;
7606 ice
->state
.dirty
= ~0ull;
7608 ice
->state
.statistics_counters_enabled
= true;
7610 ice
->state
.sample_mask
= 0xffff;
7611 ice
->state
.num_viewports
= 1;
7612 ice
->state
.prim_mode
= PIPE_PRIM_MAX
;
7613 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
7614 ice
->draw
.derived_params
.drawid
= -1;
7616 /* Make a 1x1x1 null surface for unbound textures */
7617 void *null_surf_map
=
7618 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
7619 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
7620 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
7621 ice
->state
.unbound_tex
.offset
+=
7622 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
7624 /* Default all scissor rectangles to be empty regions. */
7625 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
7626 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
7627 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,