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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_dual_blend.h"
92 #include "util/u_inlines.h"
93 #include "util/u_format.h"
94 #include "util/u_framebuffer.h"
95 #include "util/u_transfer.h"
96 #include "util/u_upload_mgr.h"
97 #include "util/u_viewport.h"
98 #include "drm-uapi/i915_drm.h"
100 #include "intel/compiler/brw_compiler.h"
101 #include "intel/common/gen_l3_config.h"
102 #include "intel/common/gen_sample_positions.h"
103 #include "iris_batch.h"
104 #include "iris_context.h"
105 #include "iris_defines.h"
106 #include "iris_pipe.h"
107 #include "iris_resource.h"
109 #include "iris_genx_macros.h"
110 #include "intel/common/gen_guardband.h"
113 #define MOCS_PTE 0x18
116 #define MOCS_PTE (1 << 1)
117 #define MOCS_WB (2 << 1)
121 mocs(const struct iris_bo
*bo
)
123 return bo
&& bo
->external
? MOCS_PTE
: MOCS_WB
;
127 * Statically assert that PIPE_* enums match the hardware packets.
128 * (As long as they match, we don't need to translate them.)
130 UNUSED
static void pipe_asserts()
132 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
134 /* pipe_logicop happens to match the hardware. */
135 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
136 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
137 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
138 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
139 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
140 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
141 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
142 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
143 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
144 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
145 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
146 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
147 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
148 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
149 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
150 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
152 /* pipe_blend_func happens to match the hardware. */
153 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
160 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
161 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
162 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
163 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
164 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
165 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
166 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
167 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
168 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
169 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
170 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
171 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
173 /* pipe_blend_func happens to match the hardware. */
174 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
175 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
176 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
177 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
178 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
180 /* pipe_stencil_op happens to match the hardware. */
181 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
182 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
183 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
184 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
185 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
186 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
187 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
188 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
190 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
191 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
192 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
197 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
199 static const unsigned map
[] = {
200 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
201 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
202 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
203 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
204 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
205 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
206 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
207 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
208 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
209 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
210 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
211 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
212 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
213 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
214 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
217 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
221 translate_compare_func(enum pipe_compare_func pipe_func
)
223 static const unsigned map
[] = {
224 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
225 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
226 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
227 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
228 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
229 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
230 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
231 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
233 return map
[pipe_func
];
237 translate_shadow_func(enum pipe_compare_func pipe_func
)
239 /* Gallium specifies the result of shadow comparisons as:
241 * 1 if ref <op> texel,
246 * 0 if texel <op> ref,
249 * So we need to flip the operator and also negate.
251 static const unsigned map
[] = {
252 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
253 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
254 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
255 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
256 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
257 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
258 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
259 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
261 return map
[pipe_func
];
265 translate_cull_mode(unsigned pipe_face
)
267 static const unsigned map
[4] = {
268 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
269 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
270 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
271 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
273 return map
[pipe_face
];
277 translate_fill_mode(unsigned pipe_polymode
)
279 static const unsigned map
[4] = {
280 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
281 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
282 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
283 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
285 return map
[pipe_polymode
];
289 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
291 static const unsigned map
[] = {
292 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
293 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
294 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
296 return map
[pipe_mip
];
300 translate_wrap(unsigned pipe_wrap
)
302 static const unsigned map
[] = {
303 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
304 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
305 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
306 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
307 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
308 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
310 /* These are unsupported. */
311 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
312 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
314 return map
[pipe_wrap
];
318 * Allocate space for some indirect state.
320 * Return a pointer to the map (to fill it out) and a state ref (for
321 * referring to the state in GPU commands).
324 upload_state(struct u_upload_mgr
*uploader
,
325 struct iris_state_ref
*ref
,
330 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
335 * Stream out temporary/short-lived state.
337 * This allocates space, pins the BO, and includes the BO address in the
338 * returned offset (which works because all state lives in 32-bit memory
342 stream_state(struct iris_batch
*batch
,
343 struct u_upload_mgr
*uploader
,
344 struct pipe_resource
**out_res
,
347 uint32_t *out_offset
)
351 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
353 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
354 iris_use_pinned_bo(batch
, bo
, false);
356 *out_offset
+= iris_bo_offset_from_base_address(bo
);
358 iris_record_state_size(batch
->state_sizes
, *out_offset
, size
);
364 * stream_state() + memcpy.
367 emit_state(struct iris_batch
*batch
,
368 struct u_upload_mgr
*uploader
,
369 struct pipe_resource
**out_res
,
376 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
379 memcpy(map
, data
, size
);
385 * Did field 'x' change between 'old_cso' and 'new_cso'?
387 * (If so, we may want to set some dirty flags.)
389 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
390 #define cso_changed_memcmp(x) \
391 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
394 flush_for_state_base_change(struct iris_batch
*batch
)
396 /* Flush before emitting STATE_BASE_ADDRESS.
398 * This isn't documented anywhere in the PRM. However, it seems to be
399 * necessary prior to changing the surface state base adress. We've
400 * seen issues in Vulkan where we get GPU hangs when using multi-level
401 * command buffers which clear depth, reset state base address, and then
404 * Normally, in GL, we would trust the kernel to do sufficient stalls
405 * and flushes prior to executing our batch. However, it doesn't seem
406 * as if the kernel's flushing is always sufficient and we don't want to
409 * We make this an end-of-pipe sync instead of a normal flush because we
410 * do not know the current status of the GPU. On Haswell at least,
411 * having a fast-clear operation in flight at the same time as a normal
412 * rendering operation can cause hangs. Since the kernel's flushing is
413 * insufficient, we need to ensure that any rendering operations from
414 * other processes are definitely complete before we try to do our own
415 * rendering. It's a bit of a big hammer but it appears to work.
417 iris_emit_end_of_pipe_sync(batch
,
418 "change STATE_BASE_ADDRESS",
419 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
420 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
421 PIPE_CONTROL_DATA_CACHE_FLUSH
);
425 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
427 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
428 lri
.RegisterOffset
= reg
;
432 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
435 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
437 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
438 lrr
.SourceRegisterAddress
= src
;
439 lrr
.DestinationRegisterAddress
= dst
;
444 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
446 #if GEN_GEN >= 8 && GEN_GEN < 10
447 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
449 * Software must clear the COLOR_CALC_STATE Valid field in
450 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
451 * with Pipeline Select set to GPGPU.
453 * The internal hardware docs recommend the same workaround for Gen9
456 if (pipeline
== GPGPU
)
457 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
461 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
462 * PIPELINE_SELECT [DevBWR+]":
466 * Software must ensure all the write caches are flushed through a
467 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
468 * command to invalidate read only caches prior to programming
469 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
471 iris_emit_pipe_control_flush(batch
,
472 "workaround: PIPELINE_SELECT flushes (1/2)",
473 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
474 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
475 PIPE_CONTROL_DATA_CACHE_FLUSH
|
476 PIPE_CONTROL_CS_STALL
);
478 iris_emit_pipe_control_flush(batch
,
479 "workaround: PIPELINE_SELECT flushes (2/2)",
480 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
481 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
482 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
483 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
485 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
489 sel
.PipelineSelection
= pipeline
;
494 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
499 * "This chicken bit works around a hardware issue with barrier
500 * logic encountered when switching between GPGPU and 3D pipelines.
501 * To workaround the issue, this mode bit should be set after a
502 * pipeline is selected."
505 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
506 reg
.GLKBarrierMode
= value
;
507 reg
.GLKBarrierModeMask
= 1;
509 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
514 init_state_base_address(struct iris_batch
*batch
)
516 flush_for_state_base_change(batch
);
518 /* We program most base addresses once at context initialization time.
519 * Each base address points at a 4GB memory zone, and never needs to
520 * change. See iris_bufmgr.h for a description of the memory zones.
522 * The one exception is Surface State Base Address, which needs to be
523 * updated occasionally. See iris_binder.c for the details there.
525 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
526 sba
.GeneralStateMOCS
= MOCS_WB
;
527 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
528 sba
.DynamicStateMOCS
= MOCS_WB
;
529 sba
.IndirectObjectMOCS
= MOCS_WB
;
530 sba
.InstructionMOCS
= MOCS_WB
;
532 sba
.GeneralStateBaseAddressModifyEnable
= true;
533 sba
.DynamicStateBaseAddressModifyEnable
= true;
534 sba
.IndirectObjectBaseAddressModifyEnable
= true;
535 sba
.InstructionBaseAddressModifyEnable
= true;
536 sba
.GeneralStateBufferSizeModifyEnable
= true;
537 sba
.DynamicStateBufferSizeModifyEnable
= true;
539 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
540 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
542 sba
.IndirectObjectBufferSizeModifyEnable
= true;
543 sba
.InstructionBuffersizeModifyEnable
= true;
545 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
546 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
548 sba
.GeneralStateBufferSize
= 0xfffff;
549 sba
.IndirectObjectBufferSize
= 0xfffff;
550 sba
.InstructionBufferSize
= 0xfffff;
551 sba
.DynamicStateBufferSize
= 0xfffff;
556 iris_emit_l3_config(struct iris_batch
*batch
, const struct gen_l3_config
*cfg
,
557 bool has_slm
, bool wants_dc_cache
)
560 iris_pack_state(GENX(L3CNTLREG
), ®_val
, reg
) {
561 reg
.SLMEnable
= has_slm
;
563 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
564 * in L3CNTLREG register. The default setting of the bit is not the
565 * desirable behavior.
567 reg
.ErrorDetectionBehaviorControl
= true;
568 reg
.UseFullWays
= true;
570 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
571 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
572 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
573 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
575 iris_emit_lri(batch
, L3CNTLREG
, reg_val
);
579 iris_emit_default_l3_config(struct iris_batch
*batch
,
580 const struct gen_device_info
*devinfo
,
583 bool wants_dc_cache
= true;
584 bool has_slm
= compute
;
585 const struct gen_l3_weights w
=
586 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
587 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
588 iris_emit_l3_config(batch
, cfg
, has_slm
, wants_dc_cache
);
591 #if GEN_GEN == 9 || GEN_GEN == 10
593 iris_enable_obj_preemption(struct iris_batch
*batch
, bool enable
)
597 /* A fixed function pipe flush is required before modifying this field */
598 iris_emit_end_of_pipe_sync(batch
, enable
? "enable preemption"
599 : "disable preemption",
600 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
602 /* enable object level preemption */
603 iris_pack_state(GENX(CS_CHICKEN1
), ®_val
, reg
) {
604 reg
.ReplayMode
= enable
;
605 reg
.ReplayModeMask
= true;
607 iris_emit_lri(batch
, CS_CHICKEN1
, reg_val
);
613 iris_upload_slice_hashing_state(struct iris_batch
*batch
)
615 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
616 int subslices_delta
=
617 devinfo
->ppipe_subslices
[0] - devinfo
->ppipe_subslices
[1];
618 if (subslices_delta
== 0)
621 struct iris_context
*ice
= NULL
;
622 ice
= container_of(batch
, ice
, batches
[IRIS_BATCH_RENDER
]);
623 assert(&ice
->batches
[IRIS_BATCH_RENDER
] == batch
);
625 unsigned size
= GENX(SLICE_HASH_TABLE_length
) * 4;
626 uint32_t hash_address
;
627 struct pipe_resource
*tmp
= NULL
;
629 stream_state(batch
, ice
->state
.dynamic_uploader
, &tmp
,
630 size
, 64, &hash_address
);
631 pipe_resource_reference(&tmp
, NULL
);
633 struct GENX(SLICE_HASH_TABLE
) table0
= {
635 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
636 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
637 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
638 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
639 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
640 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
641 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
642 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
643 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
644 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
645 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
646 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
647 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
648 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
649 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
650 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }
654 struct GENX(SLICE_HASH_TABLE
) table1
= {
656 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
657 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
658 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
659 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
660 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
661 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
662 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
663 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
664 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
665 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
666 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
667 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
668 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
669 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
670 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
671 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }
675 const struct GENX(SLICE_HASH_TABLE
) *table
=
676 subslices_delta
< 0 ? &table0
: &table1
;
677 GENX(SLICE_HASH_TABLE_pack
)(NULL
, map
, table
);
679 iris_emit_cmd(batch
, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS
), ptr
) {
680 ptr
.SliceHashStatePointerValid
= true;
681 ptr
.SliceHashTableStatePointer
= hash_address
;
684 iris_emit_cmd(batch
, GENX(3DSTATE_3D_MODE
), mode
) {
685 mode
.SliceHashingTableEnable
= true;
691 * Upload the initial GPU state for a render context.
693 * This sets some invariant state that needs to be programmed a particular
694 * way, but we never actually change.
697 iris_init_render_context(struct iris_screen
*screen
,
698 struct iris_batch
*batch
,
699 struct iris_vtable
*vtbl
,
700 struct pipe_debug_callback
*dbg
)
702 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
705 emit_pipeline_select(batch
, _3D
);
707 iris_emit_default_l3_config(batch
, devinfo
, false);
709 init_state_base_address(batch
);
712 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
713 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
714 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
716 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
718 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
719 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
720 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
722 iris_emit_lri(batch
, INSTPM
, reg_val
);
726 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
727 reg
.FloatBlendOptimizationEnable
= true;
728 reg
.FloatBlendOptimizationEnableMask
= true;
729 reg
.PartialResolveDisableInVC
= true;
730 reg
.PartialResolveDisableInVCMask
= true;
732 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
734 if (devinfo
->is_geminilake
)
735 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
739 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
740 reg
.HeaderlessMessageforPreemptableContexts
= 1;
741 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
743 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
745 /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
746 iris_pack_state(GENX(HALF_SLICE_CHICKEN7
), ®_val
, reg
) {
747 reg
.EnabledTexelOffsetPrecisionFix
= 1;
748 reg
.EnabledTexelOffsetPrecisionFixMask
= 1;
750 iris_emit_lri(batch
, HALF_SLICE_CHICKEN7
, reg_val
);
752 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
753 reg
.StateCacheRedirectToCSSectionEnable
= true;
754 reg
.StateCacheRedirectToCSSectionEnableMask
= true;
756 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
758 /* Hardware specification recommends disabling repacking for the
759 * compatibility with decompression mechanism in display controller.
761 if (devinfo
->disable_ccs_repack
) {
762 iris_pack_state(GENX(CACHE_MODE_0
), ®_val
, reg
) {
763 reg
.DisableRepackingforCompression
= true;
764 reg
.DisableRepackingforCompressionMask
= true;
766 iris_emit_lri(batch
, CACHE_MODE_0
, reg_val
);
769 iris_upload_slice_hashing_state(batch
);
772 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
773 * changing it dynamically. We set it to the maximum size here, and
774 * instead include the render target dimensions in the viewport, so
775 * viewport extents clipping takes care of pruning stray geometry.
777 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
778 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
779 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
782 /* Set the initial MSAA sample positions. */
783 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
784 GEN_SAMPLE_POS_1X(pat
._1xSample
);
785 GEN_SAMPLE_POS_2X(pat
._2xSample
);
786 GEN_SAMPLE_POS_4X(pat
._4xSample
);
787 GEN_SAMPLE_POS_8X(pat
._8xSample
);
789 GEN_SAMPLE_POS_16X(pat
._16xSample
);
793 /* Use the legacy AA line coverage computation. */
794 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
796 /* Disable chromakeying (it's for media) */
797 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
799 /* We want regular rendering, not special HiZ operations. */
800 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
802 /* No polygon stippling offsets are necessary. */
803 /* TODO: may need to set an offset for origin-UL framebuffers */
804 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
806 /* Set a static partitioning of the push constant area. */
807 /* TODO: this may be a bad idea...could starve the push ringbuffers... */
808 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
809 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
810 alloc
._3DCommandSubOpcode
= 18 + i
;
811 alloc
.ConstantBufferOffset
= 6 * i
;
812 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
817 /* Gen11+ is enabled for us by the kernel. */
818 iris_enable_obj_preemption(batch
, true);
823 iris_init_compute_context(struct iris_screen
*screen
,
824 struct iris_batch
*batch
,
825 struct iris_vtable
*vtbl
,
826 struct pipe_debug_callback
*dbg
)
828 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
830 emit_pipeline_select(batch
, GPGPU
);
832 iris_emit_default_l3_config(batch
, devinfo
, true);
834 init_state_base_address(batch
);
837 if (devinfo
->is_geminilake
)
838 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
842 struct iris_vertex_buffer_state
{
843 /** The VERTEX_BUFFER_STATE hardware structure. */
844 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
846 /** The resource to source vertex data from. */
847 struct pipe_resource
*resource
;
850 struct iris_depth_buffer_state
{
851 /* Depth/HiZ/Stencil related hardware packets. */
852 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
853 GENX(3DSTATE_STENCIL_BUFFER_length
) +
854 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
855 GENX(3DSTATE_CLEAR_PARAMS_length
)];
859 * Generation-specific context state (ice->state.genx->...).
861 * Most state can go in iris_context directly, but these encode hardware
862 * packets which vary by generation.
864 struct iris_genx_state
{
865 struct iris_vertex_buffer_state vertex_buffers
[33];
866 uint32_t last_index_buffer
[GENX(3DSTATE_INDEX_BUFFER_length
)];
868 struct iris_depth_buffer_state depth_buffer
;
870 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
873 /* Is object level preemption enabled? */
874 bool object_preemption
;
879 struct brw_image_param image_param
[PIPE_MAX_SHADER_IMAGES
];
881 } shaders
[MESA_SHADER_STAGES
];
885 * The pipe->set_blend_color() driver hook.
887 * This corresponds to our COLOR_CALC_STATE.
890 iris_set_blend_color(struct pipe_context
*ctx
,
891 const struct pipe_blend_color
*state
)
893 struct iris_context
*ice
= (struct iris_context
*) ctx
;
895 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
896 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
897 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
901 * Gallium CSO for blend state (see pipe_blend_state).
903 struct iris_blend_state
{
904 /** Partial 3DSTATE_PS_BLEND */
905 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
907 /** Partial BLEND_STATE */
908 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
909 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
911 bool alpha_to_coverage
; /* for shader key */
913 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
914 uint8_t blend_enables
;
916 /** Bitfield of whether color writes are enabled for RT[i] */
917 uint8_t color_write_enables
;
919 /** Does RT[0] use dual color blending? */
920 bool dual_color_blending
;
923 static enum pipe_blendfactor
924 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
927 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
928 return PIPE_BLENDFACTOR_ONE
;
930 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
931 return PIPE_BLENDFACTOR_ZERO
;
938 * The pipe->create_blend_state() driver hook.
940 * Translates a pipe_blend_state into iris_blend_state.
943 iris_create_blend_state(struct pipe_context
*ctx
,
944 const struct pipe_blend_state
*state
)
946 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
947 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
949 cso
->blend_enables
= 0;
950 cso
->color_write_enables
= 0;
951 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
953 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
955 bool indep_alpha_blend
= false;
957 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
958 const struct pipe_rt_blend_state
*rt
=
959 &state
->rt
[state
->independent_blend_enable
? i
: 0];
961 enum pipe_blendfactor src_rgb
=
962 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
963 enum pipe_blendfactor src_alpha
=
964 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
965 enum pipe_blendfactor dst_rgb
=
966 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
967 enum pipe_blendfactor dst_alpha
=
968 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
970 if (rt
->rgb_func
!= rt
->alpha_func
||
971 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
972 indep_alpha_blend
= true;
974 if (rt
->blend_enable
)
975 cso
->blend_enables
|= 1u << i
;
978 cso
->color_write_enables
|= 1u << i
;
980 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
981 be
.LogicOpEnable
= state
->logicop_enable
;
982 be
.LogicOpFunction
= state
->logicop_func
;
984 be
.PreBlendSourceOnlyClampEnable
= false;
985 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
986 be
.PreBlendColorClampEnable
= true;
987 be
.PostBlendColorClampEnable
= true;
989 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
991 be
.ColorBlendFunction
= rt
->rgb_func
;
992 be
.AlphaBlendFunction
= rt
->alpha_func
;
993 be
.SourceBlendFactor
= src_rgb
;
994 be
.SourceAlphaBlendFactor
= src_alpha
;
995 be
.DestinationBlendFactor
= dst_rgb
;
996 be
.DestinationAlphaBlendFactor
= dst_alpha
;
998 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
999 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
1000 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
1001 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
1003 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
1006 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
1007 /* pb.HasWriteableRT is filled in at draw time.
1008 * pb.AlphaTestEnable is filled in at draw time.
1010 * pb.ColorBufferBlendEnable is filled in at draw time so we can avoid
1011 * setting it when dual color blending without an appropriate shader.
1014 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1015 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1017 pb
.SourceBlendFactor
=
1018 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
1019 pb
.SourceAlphaBlendFactor
=
1020 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
1021 pb
.DestinationBlendFactor
=
1022 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
1023 pb
.DestinationAlphaBlendFactor
=
1024 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
1027 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
1028 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1029 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1030 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
1031 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
1032 bs
.ColorDitherEnable
= state
->dither
;
1033 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
1036 cso
->dual_color_blending
= util_blend_state_is_dual(state
, 0);
1042 * The pipe->bind_blend_state() driver hook.
1044 * Bind a blending CSO and flag related dirty bits.
1047 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
1049 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1050 struct iris_blend_state
*cso
= state
;
1052 ice
->state
.cso_blend
= cso
;
1053 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
1055 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1056 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1057 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1058 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
1062 * Return true if the FS writes to any color outputs which are not disabled
1063 * via color masking.
1066 has_writeable_rt(const struct iris_blend_state
*cso_blend
,
1067 const struct shader_info
*fs_info
)
1072 unsigned rt_outputs
= fs_info
->outputs_written
>> FRAG_RESULT_DATA0
;
1074 if (fs_info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
))
1075 rt_outputs
= (1 << BRW_MAX_DRAW_BUFFERS
) - 1;
1077 return cso_blend
->color_write_enables
& rt_outputs
;
1081 * Gallium CSO for depth, stencil, and alpha testing state.
1083 struct iris_depth_stencil_alpha_state
{
1084 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
1085 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1087 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
1088 struct pipe_alpha_state alpha
;
1090 /** Outbound to resolve and cache set tracking. */
1091 bool depth_writes_enabled
;
1092 bool stencil_writes_enabled
;
1096 * The pipe->create_depth_stencil_alpha_state() driver hook.
1098 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
1099 * testing state since we need pieces of it in a variety of places.
1102 iris_create_zsa_state(struct pipe_context
*ctx
,
1103 const struct pipe_depth_stencil_alpha_state
*state
)
1105 struct iris_depth_stencil_alpha_state
*cso
=
1106 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
1108 bool two_sided_stencil
= state
->stencil
[1].enabled
;
1110 cso
->alpha
= state
->alpha
;
1111 cso
->depth_writes_enabled
= state
->depth
.writemask
;
1112 cso
->stencil_writes_enabled
=
1113 state
->stencil
[0].writemask
!= 0 ||
1114 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1116 /* The state tracker needs to optimize away EQUAL writes for us. */
1117 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
1119 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
1120 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1121 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1122 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1123 wmds
.StencilTestFunction
=
1124 translate_compare_func(state
->stencil
[0].func
);
1125 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1126 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1127 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1128 wmds
.BackfaceStencilTestFunction
=
1129 translate_compare_func(state
->stencil
[1].func
);
1130 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1131 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1132 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1133 wmds
.StencilBufferWriteEnable
=
1134 state
->stencil
[0].writemask
!= 0 ||
1135 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1136 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1137 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1138 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1139 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1140 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1141 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1142 /* wmds.[Backface]StencilReferenceValue are merged later */
1149 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1151 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1154 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1156 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1157 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1158 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1161 if (cso_changed(alpha
.ref_value
))
1162 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1164 if (cso_changed(alpha
.enabled
))
1165 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1167 if (cso_changed(alpha
.func
))
1168 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1170 if (cso_changed(depth_writes_enabled
))
1171 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1173 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1174 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1177 ice
->state
.cso_zsa
= new_cso
;
1178 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1179 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1180 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1184 * Gallium CSO for rasterizer state.
1186 struct iris_rasterizer_state
{
1187 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1188 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1189 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1190 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1191 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1193 uint8_t num_clip_plane_consts
;
1194 bool clip_halfz
; /* for CC_VIEWPORT */
1195 bool depth_clip_near
; /* for CC_VIEWPORT */
1196 bool depth_clip_far
; /* for CC_VIEWPORT */
1197 bool flatshade
; /* for shader state */
1198 bool flatshade_first
; /* for stream output */
1199 bool clamp_fragment_color
; /* for shader state */
1200 bool light_twoside
; /* for shader state */
1201 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1202 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1203 bool line_stipple_enable
;
1204 bool poly_stipple_enable
;
1206 bool force_persample_interp
;
1207 bool conservative_rasterization
;
1208 bool fill_mode_point_or_line
;
1209 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1210 uint16_t sprite_coord_enable
;
1214 get_line_width(const struct pipe_rasterizer_state
*state
)
1216 float line_width
= state
->line_width
;
1218 /* From the OpenGL 4.4 spec:
1220 * "The actual width of non-antialiased lines is determined by rounding
1221 * the supplied width to the nearest integer, then clamping it to the
1222 * implementation-dependent maximum non-antialiased line width."
1224 if (!state
->multisample
&& !state
->line_smooth
)
1225 line_width
= roundf(state
->line_width
);
1227 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1228 /* For 1 pixel line thickness or less, the general anti-aliasing
1229 * algorithm gives up, and a garbage line is generated. Setting a
1230 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1231 * (one-pixel-wide), non-antialiased lines.
1233 * Lines rendered with zero Line Width are rasterized using the
1234 * "Grid Intersection Quantization" rules as specified by the
1235 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1244 * The pipe->create_rasterizer_state() driver hook.
1247 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1248 const struct pipe_rasterizer_state
*state
)
1250 struct iris_rasterizer_state
*cso
=
1251 malloc(sizeof(struct iris_rasterizer_state
));
1253 cso
->multisample
= state
->multisample
;
1254 cso
->force_persample_interp
= state
->force_persample_interp
;
1255 cso
->clip_halfz
= state
->clip_halfz
;
1256 cso
->depth_clip_near
= state
->depth_clip_near
;
1257 cso
->depth_clip_far
= state
->depth_clip_far
;
1258 cso
->flatshade
= state
->flatshade
;
1259 cso
->flatshade_first
= state
->flatshade_first
;
1260 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1261 cso
->light_twoside
= state
->light_twoside
;
1262 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1263 cso
->half_pixel_center
= state
->half_pixel_center
;
1264 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1265 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1266 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1267 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1268 cso
->conservative_rasterization
=
1269 state
->conservative_raster_mode
== PIPE_CONSERVATIVE_RASTER_POST_SNAP
;
1271 cso
->fill_mode_point_or_line
=
1272 state
->fill_front
== PIPE_POLYGON_MODE_LINE
||
1273 state
->fill_front
== PIPE_POLYGON_MODE_POINT
||
1274 state
->fill_back
== PIPE_POLYGON_MODE_LINE
||
1275 state
->fill_back
== PIPE_POLYGON_MODE_POINT
;
1277 if (state
->clip_plane_enable
!= 0)
1278 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1280 cso
->num_clip_plane_consts
= 0;
1282 float line_width
= get_line_width(state
);
1284 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1285 sf
.StatisticsEnable
= true;
1286 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1287 sf
.LineEndCapAntialiasingRegionWidth
=
1288 state
->line_smooth
? _10pixels
: _05pixels
;
1289 sf
.LastPixelEnable
= state
->line_last_pixel
;
1290 sf
.LineWidth
= line_width
;
1291 sf
.SmoothPointEnable
= (state
->point_smooth
|| state
->multisample
) &&
1292 !state
->point_quad_rasterization
;
1293 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1294 sf
.PointWidth
= state
->point_size
;
1296 if (state
->flatshade_first
) {
1297 sf
.TriangleFanProvokingVertexSelect
= 1;
1299 sf
.TriangleStripListProvokingVertexSelect
= 2;
1300 sf
.TriangleFanProvokingVertexSelect
= 2;
1301 sf
.LineStripListProvokingVertexSelect
= 1;
1305 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1306 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1307 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1308 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1309 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1310 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1311 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1312 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1313 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1314 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1315 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1316 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1317 rr
.SmoothPointEnable
= state
->point_smooth
;
1318 rr
.AntialiasingEnable
= state
->line_smooth
;
1319 rr
.ScissorRectangleEnable
= state
->scissor
;
1321 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1322 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1323 rr
.ConservativeRasterizationEnable
=
1324 cso
->conservative_rasterization
;
1326 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1330 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1331 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1332 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1334 cl
.EarlyCullEnable
= true;
1335 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1336 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1337 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1338 cl
.GuardbandClipTestEnable
= true;
1339 cl
.ClipEnable
= true;
1340 cl
.MinimumPointWidth
= 0.125;
1341 cl
.MaximumPointWidth
= 255.875;
1343 if (state
->flatshade_first
) {
1344 cl
.TriangleFanProvokingVertexSelect
= 1;
1346 cl
.TriangleStripListProvokingVertexSelect
= 2;
1347 cl
.TriangleFanProvokingVertexSelect
= 2;
1348 cl
.LineStripListProvokingVertexSelect
= 1;
1352 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1353 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1354 * filled in at draw time from the FS program.
1356 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1357 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1358 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1359 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1360 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1363 /* Remap from 0..255 back to 1..256 */
1364 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1366 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1367 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1368 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1369 line
.LineStippleRepeatCount
= line_stipple_factor
;
1376 * The pipe->bind_rasterizer_state() driver hook.
1378 * Bind a rasterizer CSO and flag related dirty bits.
1381 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1383 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1384 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1385 struct iris_rasterizer_state
*new_cso
= state
;
1388 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1389 if (cso_changed_memcmp(line_stipple
))
1390 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1392 if (cso_changed(half_pixel_center
))
1393 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1395 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1396 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1398 if (cso_changed(rasterizer_discard
))
1399 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1401 if (cso_changed(flatshade_first
))
1402 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1404 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1405 cso_changed(clip_halfz
))
1406 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1408 if (cso_changed(sprite_coord_enable
) ||
1409 cso_changed(sprite_coord_mode
) ||
1410 cso_changed(light_twoside
))
1411 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1413 if (cso_changed(conservative_rasterization
))
1414 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
1417 ice
->state
.cso_rast
= new_cso
;
1418 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1419 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1420 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1424 * Return true if the given wrap mode requires the border color to exist.
1426 * (We can skip uploading it if the sampler isn't going to use it.)
1429 wrap_mode_needs_border_color(unsigned wrap_mode
)
1431 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1435 * Gallium CSO for sampler state.
1437 struct iris_sampler_state
{
1438 union pipe_color_union border_color
;
1439 bool needs_border_color
;
1441 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1445 * The pipe->create_sampler_state() driver hook.
1447 * We fill out SAMPLER_STATE (except for the border color pointer), and
1448 * store that on the CPU. It doesn't make sense to upload it to a GPU
1449 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1450 * all bound sampler states to be in contiguous memor.
1453 iris_create_sampler_state(struct pipe_context
*ctx
,
1454 const struct pipe_sampler_state
*state
)
1456 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1461 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1462 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1464 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1465 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1466 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1468 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1470 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1471 wrap_mode_needs_border_color(wrap_t
) ||
1472 wrap_mode_needs_border_color(wrap_r
);
1474 float min_lod
= state
->min_lod
;
1475 unsigned mag_img_filter
= state
->mag_img_filter
;
1477 // XXX: explain this code ported from ilo...I don't get it at all...
1478 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1479 state
->min_lod
> 0.0f
) {
1481 mag_img_filter
= state
->min_img_filter
;
1484 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1485 samp
.TCXAddressControlMode
= wrap_s
;
1486 samp
.TCYAddressControlMode
= wrap_t
;
1487 samp
.TCZAddressControlMode
= wrap_r
;
1488 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1489 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1490 samp
.MinModeFilter
= state
->min_img_filter
;
1491 samp
.MagModeFilter
= mag_img_filter
;
1492 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1493 samp
.MaximumAnisotropy
= RATIO21
;
1495 if (state
->max_anisotropy
>= 2) {
1496 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1497 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1498 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1501 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1502 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1504 samp
.MaximumAnisotropy
=
1505 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1508 /* Set address rounding bits if not using nearest filtering. */
1509 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1510 samp
.UAddressMinFilterRoundingEnable
= true;
1511 samp
.VAddressMinFilterRoundingEnable
= true;
1512 samp
.RAddressMinFilterRoundingEnable
= true;
1515 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1516 samp
.UAddressMagFilterRoundingEnable
= true;
1517 samp
.VAddressMagFilterRoundingEnable
= true;
1518 samp
.RAddressMagFilterRoundingEnable
= true;
1521 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1522 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1524 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1526 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1527 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1528 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1529 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1531 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1538 * The pipe->bind_sampler_states() driver hook.
1541 iris_bind_sampler_states(struct pipe_context
*ctx
,
1542 enum pipe_shader_type p_stage
,
1543 unsigned start
, unsigned count
,
1546 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1547 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1548 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1550 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1552 for (int i
= 0; i
< count
; i
++) {
1553 shs
->samplers
[start
+ i
] = states
[i
];
1556 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1560 * Upload the sampler states into a contiguous area of GPU memory, for
1561 * for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1563 * Also fill out the border color state pointers.
1566 iris_upload_sampler_states(struct iris_context
*ice
, gl_shader_stage stage
)
1568 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1569 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
1571 /* We assume the state tracker will call pipe->bind_sampler_states()
1572 * if the program's number of textures changes.
1574 unsigned count
= info
? util_last_bit(info
->textures_used
) : 0;
1579 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1580 * in the dynamic state memory zone, so we can point to it via the
1581 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1583 unsigned size
= count
* 4 * GENX(SAMPLER_STATE_length
);
1585 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
, size
, 32);
1589 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1590 shs
->sampler_table
.offset
+=
1591 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1593 iris_record_state_size(ice
->state
.sizes
, shs
->sampler_table
.offset
, size
);
1595 /* Make sure all land in the same BO */
1596 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1598 ice
->state
.need_border_colors
&= ~(1 << stage
);
1600 for (int i
= 0; i
< count
; i
++) {
1601 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1602 struct iris_sampler_view
*tex
= shs
->textures
[i
];
1605 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1606 } else if (!state
->needs_border_color
) {
1607 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1609 ice
->state
.need_border_colors
|= 1 << stage
;
1611 /* We may need to swizzle the border color for format faking.
1612 * A/LA formats are faked as R/RG with 000R or R00G swizzles.
1613 * This means we need to move the border color's A channel into
1614 * the R or G channels so that those read swizzles will move it
1617 union pipe_color_union
*color
= &state
->border_color
;
1618 union pipe_color_union tmp
;
1620 enum pipe_format internal_format
= tex
->res
->internal_format
;
1622 if (util_format_is_alpha(internal_format
)) {
1623 unsigned char swz
[4] = {
1624 PIPE_SWIZZLE_W
, PIPE_SWIZZLE_0
,
1625 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1627 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1629 } else if (util_format_is_luminance_alpha(internal_format
) &&
1630 internal_format
!= PIPE_FORMAT_L8A8_SRGB
) {
1631 unsigned char swz
[4] = {
1632 PIPE_SWIZZLE_X
, PIPE_SWIZZLE_W
,
1633 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1635 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1640 /* Stream out the border color and merge the pointer. */
1641 uint32_t offset
= iris_upload_border_color(ice
, color
);
1643 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1644 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1645 dyns
.BorderColorPointer
= offset
;
1648 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1649 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1652 map
+= GENX(SAMPLER_STATE_length
);
1656 static enum isl_channel_select
1657 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1660 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1661 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1662 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1663 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1664 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1665 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1666 default: unreachable("invalid swizzle");
1671 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1672 struct iris_resource
*res
,
1674 enum isl_format format
,
1675 struct isl_swizzle swizzle
,
1679 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1680 const unsigned cpp
= format
== ISL_FORMAT_RAW
? 1 : fmtl
->bpb
/ 8;
1682 /* The ARB_texture_buffer_specification says:
1684 * "The number of texels in the buffer texture's texel array is given by
1686 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1688 * where <buffer_size> is the size of the buffer object, in basic
1689 * machine units and <components> and <base_type> are the element count
1690 * and base data type for elements, as specified in Table X.1. The
1691 * number of texels in the texel array is then clamped to the
1692 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1694 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1695 * so that when ISL divides by stride to obtain the number of texels, that
1696 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1698 unsigned final_size
=
1699 MIN3(size
, res
->bo
->size
- res
->offset
- offset
,
1700 IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1702 isl_buffer_fill_state(isl_dev
, map
,
1703 .address
= res
->bo
->gtt_offset
+ res
->offset
+ offset
,
1704 .size_B
= final_size
,
1708 .mocs
= mocs(res
->bo
));
1711 #define SURFACE_STATE_ALIGNMENT 64
1714 * Allocate several contiguous SURFACE_STATE structures, one for each
1715 * supported auxiliary surface mode.
1718 alloc_surface_states(struct u_upload_mgr
*mgr
,
1719 struct iris_state_ref
*ref
,
1720 unsigned aux_usages
)
1722 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
1724 /* If this changes, update this to explicitly align pointers */
1725 STATIC_ASSERT(surf_size
== SURFACE_STATE_ALIGNMENT
);
1727 assert(aux_usages
!= 0);
1730 upload_state(mgr
, ref
, util_bitcount(aux_usages
) * surf_size
,
1731 SURFACE_STATE_ALIGNMENT
);
1733 ref
->offset
+= iris_bo_offset_from_base_address(iris_resource_bo(ref
->res
));
1740 * Return an ISL surface for use with non-coherent render target reads.
1742 * In a few complex cases, we can't use the SURFACE_STATE for normal render
1743 * target writes. We need to make a separate one for sampling which refers
1744 * to the single slice of the texture being read.
1747 get_rt_read_isl_surf(const struct gen_device_info
*devinfo
,
1748 struct iris_resource
*res
,
1749 enum pipe_texture_target target
,
1750 struct isl_view
*view
,
1751 uint32_t *tile_x_sa
,
1752 uint32_t *tile_y_sa
,
1753 struct isl_surf
*surf
)
1758 const enum isl_dim_layout dim_layout
=
1759 iris_get_isl_dim_layout(devinfo
, res
->surf
.tiling
, target
);
1761 surf
->dim
= target_to_isl_surf_dim(target
);
1763 if (surf
->dim_layout
== dim_layout
)
1766 /* The layout of the specified texture target is not compatible with the
1767 * actual layout of the miptree structure in memory -- You're entering
1768 * dangerous territory, this can only possibly work if you only intended
1769 * to access a single level and slice of the texture, and the hardware
1770 * supports the tile offset feature in order to allow non-tile-aligned
1771 * base offsets, since we'll have to point the hardware to the first
1772 * texel of the level instead of relying on the usual base level/layer
1775 assert(view
->levels
== 1 && view
->array_len
== 1);
1776 assert(*tile_x_sa
== 0 && *tile_y_sa
== 0);
1778 res
->offset
+= iris_resource_get_tile_offsets(res
, view
->base_level
,
1779 view
->base_array_layer
,
1780 tile_x_sa
, tile_y_sa
);
1781 const unsigned l
= view
->base_level
;
1783 surf
->logical_level0_px
.width
= minify(surf
->logical_level0_px
.width
, l
);
1784 surf
->logical_level0_px
.height
= surf
->dim
<= ISL_SURF_DIM_1D
? 1 :
1785 minify(surf
->logical_level0_px
.height
, l
);
1786 surf
->logical_level0_px
.depth
= surf
->dim
<= ISL_SURF_DIM_2D
? 1 :
1787 minify(surf
->logical_level0_px
.depth
, l
);
1789 surf
->logical_level0_px
.array_len
= 1;
1791 surf
->dim_layout
= dim_layout
;
1793 view
->base_level
= 0;
1794 view
->base_array_layer
= 0;
1799 fill_surface_state(struct isl_device
*isl_dev
,
1801 struct iris_resource
*res
,
1802 struct isl_surf
*surf
,
1803 struct isl_view
*view
,
1808 struct isl_surf_fill_state_info f
= {
1811 .mocs
= mocs(res
->bo
),
1812 .address
= res
->bo
->gtt_offset
+ res
->offset
,
1813 .x_offset_sa
= tile_x_sa
,
1814 .y_offset_sa
= tile_y_sa
,
1817 assert(!iris_resource_unfinished_aux_import(res
));
1819 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1820 f
.aux_surf
= &res
->aux
.surf
;
1821 f
.aux_usage
= aux_usage
;
1822 f
.aux_address
= res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
;
1824 struct iris_bo
*clear_bo
= NULL
;
1825 uint64_t clear_offset
= 0;
1827 iris_resource_get_clear_color(res
, &clear_bo
, &clear_offset
);
1829 f
.clear_address
= clear_bo
->gtt_offset
+ clear_offset
;
1830 f
.use_clear_address
= isl_dev
->info
->gen
> 9;
1834 isl_surf_fill_state_s(isl_dev
, map
, &f
);
1838 * The pipe->create_sampler_view() driver hook.
1840 static struct pipe_sampler_view
*
1841 iris_create_sampler_view(struct pipe_context
*ctx
,
1842 struct pipe_resource
*tex
,
1843 const struct pipe_sampler_view
*tmpl
)
1845 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1846 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1847 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1848 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1853 /* initialize base object */
1855 isv
->base
.context
= ctx
;
1856 isv
->base
.texture
= NULL
;
1857 pipe_reference_init(&isv
->base
.reference
, 1);
1858 pipe_resource_reference(&isv
->base
.texture
, tex
);
1860 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1861 struct iris_resource
*zres
, *sres
;
1862 const struct util_format_description
*desc
=
1863 util_format_description(tmpl
->format
);
1865 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1867 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1870 isv
->res
= (struct iris_resource
*) tex
;
1872 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1873 &isv
->surface_state
,
1874 isv
->res
->aux
.sampler_usages
);
1878 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1880 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1881 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1882 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1884 const struct iris_format_info fmt
=
1885 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1887 isv
->clear_color
= isv
->res
->aux
.clear_color
;
1889 isv
->view
= (struct isl_view
) {
1891 .swizzle
= (struct isl_swizzle
) {
1892 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1893 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1894 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1895 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1900 /* Fill out SURFACE_STATE for this view. */
1901 if (tmpl
->target
!= PIPE_BUFFER
) {
1902 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1903 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1904 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1905 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1906 isv
->view
.array_len
=
1907 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1909 if (iris_resource_unfinished_aux_import(isv
->res
))
1910 iris_resource_finish_aux_import(&screen
->base
, isv
->res
);
1912 unsigned aux_modes
= isv
->res
->aux
.sampler_usages
;
1914 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1916 /* If we have a multisampled depth buffer, do not create a sampler
1917 * surface state with HiZ.
1919 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->res
->surf
,
1920 &isv
->view
, aux_usage
, 0, 0);
1922 map
+= SURFACE_STATE_ALIGNMENT
;
1925 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
1926 isv
->view
.format
, isv
->view
.swizzle
,
1927 tmpl
->u
.buf
.offset
, tmpl
->u
.buf
.size
);
1934 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1935 struct pipe_sampler_view
*state
)
1937 struct iris_sampler_view
*isv
= (void *) state
;
1938 pipe_resource_reference(&state
->texture
, NULL
);
1939 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1944 * The pipe->create_surface() driver hook.
1946 * In Gallium nomenclature, "surfaces" are a view of a resource that
1947 * can be bound as a render target or depth/stencil buffer.
1949 static struct pipe_surface
*
1950 iris_create_surface(struct pipe_context
*ctx
,
1951 struct pipe_resource
*tex
,
1952 const struct pipe_surface
*tmpl
)
1954 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1955 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1956 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1958 isl_surf_usage_flags_t usage
= 0;
1960 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1961 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1962 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1964 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1966 const struct iris_format_info fmt
=
1967 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1969 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1970 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1971 /* Framebuffer validation will reject this invalid case, but it
1972 * hasn't had the opportunity yet. In the meantime, we need to
1973 * avoid hitting ISL asserts about unsupported formats below.
1978 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1979 struct pipe_surface
*psurf
= &surf
->base
;
1980 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1985 pipe_reference_init(&psurf
->reference
, 1);
1986 pipe_resource_reference(&psurf
->texture
, tex
);
1987 psurf
->context
= ctx
;
1988 psurf
->format
= tmpl
->format
;
1989 psurf
->width
= tex
->width0
;
1990 psurf
->height
= tex
->height0
;
1991 psurf
->texture
= tex
;
1992 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1993 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1994 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1996 uint32_t array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1998 struct isl_view
*view
= &surf
->view
;
1999 *view
= (struct isl_view
) {
2001 .base_level
= tmpl
->u
.tex
.level
,
2003 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2004 .array_len
= array_len
,
2005 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2010 enum pipe_texture_target target
= (tex
->target
== PIPE_TEXTURE_3D
&&
2011 array_len
== 1) ? PIPE_TEXTURE_2D
:
2012 tex
->target
== PIPE_TEXTURE_1D_ARRAY
?
2013 PIPE_TEXTURE_2D_ARRAY
: tex
->target
;
2015 struct isl_view
*read_view
= &surf
->read_view
;
2016 *read_view
= (struct isl_view
) {
2018 .base_level
= tmpl
->u
.tex
.level
,
2020 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2021 .array_len
= array_len
,
2022 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2023 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
2027 surf
->clear_color
= res
->aux
.clear_color
;
2029 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
2030 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
2031 ISL_SURF_USAGE_STENCIL_BIT
))
2035 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
2036 &surf
->surface_state
,
2037 res
->aux
.possible_usages
);
2038 if (!unlikely(map
)) {
2039 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2044 void *map_read
= alloc_surface_states(ice
->state
.surface_uploader
,
2045 &surf
->surface_state_read
,
2046 res
->aux
.possible_usages
);
2047 if (!unlikely(map_read
)) {
2048 pipe_resource_reference(&surf
->surface_state_read
.res
, NULL
);
2053 if (!isl_format_is_compressed(res
->surf
.format
)) {
2054 if (iris_resource_unfinished_aux_import(res
))
2055 iris_resource_finish_aux_import(&screen
->base
, res
);
2057 /* This is a normal surface. Fill out a SURFACE_STATE for each possible
2058 * auxiliary surface mode and return the pipe_surface.
2060 unsigned aux_modes
= res
->aux
.possible_usages
;
2063 uint32_t offset
= res
->offset
;
2065 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
2066 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2067 view
, aux_usage
, 0, 0);
2068 map
+= SURFACE_STATE_ALIGNMENT
;
2071 struct isl_surf surf
;
2072 uint32_t tile_x_sa
= 0, tile_y_sa
= 0;
2073 get_rt_read_isl_surf(devinfo
, res
, target
, read_view
,
2074 &tile_x_sa
, &tile_y_sa
, &surf
);
2075 fill_surface_state(&screen
->isl_dev
, map_read
, res
, &surf
, read_view
,
2076 aux_usage
, tile_x_sa
, tile_y_sa
);
2077 /* Restore offset because we change offset in case of handling
2078 * non_coherent fb fetch
2080 res
->offset
= offset
;
2081 map_read
+= SURFACE_STATE_ALIGNMENT
;
2088 /* The resource has a compressed format, which is not renderable, but we
2089 * have a renderable view format. We must be attempting to upload blocks
2090 * of compressed data via an uncompressed view.
2092 * In this case, we can assume there are no auxiliary buffers, a single
2093 * miplevel, and that the resource is single-sampled. Gallium may try
2094 * and create an uncompressed view with multiple layers, however.
2096 assert(!isl_format_is_compressed(fmt
.fmt
));
2097 assert(res
->aux
.possible_usages
== 1 << ISL_AUX_USAGE_NONE
);
2098 assert(res
->surf
.samples
== 1);
2099 assert(view
->levels
== 1);
2101 struct isl_surf isl_surf
;
2102 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
2104 if (view
->base_level
> 0) {
2105 /* We can't rely on the hardware's miplevel selection with such
2106 * a substantial lie about the format, so we select a single image
2107 * using the Tile X/Y Offset fields. In this case, we can't handle
2108 * multiple array slices.
2110 * On Broadwell, HALIGN and VALIGN are specified in pixels and are
2111 * hard-coded to align to exactly the block size of the compressed
2112 * texture. This means that, when reinterpreted as a non-compressed
2113 * texture, the tile offsets may be anything and we can't rely on
2116 * Return NULL to force the state tracker to take fallback paths.
2118 if (view
->array_len
> 1 || GEN_GEN
== 8)
2121 const bool is_3d
= res
->surf
.dim
== ISL_SURF_DIM_3D
;
2122 isl_surf_get_image_surf(&screen
->isl_dev
, &res
->surf
,
2124 is_3d
? 0 : view
->base_array_layer
,
2125 is_3d
? view
->base_array_layer
: 0,
2127 &offset_B
, &tile_x_sa
, &tile_y_sa
);
2129 /* We use address and tile offsets to access a single level/layer
2130 * as a subimage, so reset level/layer so it doesn't offset again.
2132 view
->base_array_layer
= 0;
2133 view
->base_level
= 0;
2135 /* Level 0 doesn't require tile offsets, and the hardware can find
2136 * array slices using QPitch even with the format override, so we
2137 * can allow layers in this case. Copy the original ISL surface.
2139 memcpy(&isl_surf
, &res
->surf
, sizeof(isl_surf
));
2142 /* Scale down the image dimensions by the block size. */
2143 const struct isl_format_layout
*fmtl
=
2144 isl_format_get_layout(res
->surf
.format
);
2145 isl_surf
.format
= fmt
.fmt
;
2146 isl_surf
.logical_level0_px
= isl_surf_get_logical_level0_el(&isl_surf
);
2147 isl_surf
.phys_level0_sa
= isl_surf_get_phys_level0_el(&isl_surf
);
2148 tile_x_sa
/= fmtl
->bw
;
2149 tile_y_sa
/= fmtl
->bh
;
2151 psurf
->width
= isl_surf
.logical_level0_px
.width
;
2152 psurf
->height
= isl_surf
.logical_level0_px
.height
;
2154 struct isl_surf_fill_state_info f
= {
2157 .mocs
= mocs(res
->bo
),
2158 .address
= res
->bo
->gtt_offset
+ offset_B
,
2159 .x_offset_sa
= tile_x_sa
,
2160 .y_offset_sa
= tile_y_sa
,
2163 isl_surf_fill_state_s(&screen
->isl_dev
, map
, &f
);
2169 fill_default_image_param(struct brw_image_param
*param
)
2171 memset(param
, 0, sizeof(*param
));
2172 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
2173 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
2174 * detailed explanation of these parameters.
2176 param
->swizzling
[0] = 0xff;
2177 param
->swizzling
[1] = 0xff;
2181 fill_buffer_image_param(struct brw_image_param
*param
,
2182 enum pipe_format pfmt
,
2185 const unsigned cpp
= util_format_get_blocksize(pfmt
);
2187 fill_default_image_param(param
);
2188 param
->size
[0] = size
/ cpp
;
2189 param
->stride
[0] = cpp
;
2192 #define isl_surf_fill_image_param(x, ...)
2193 #define fill_default_image_param(x, ...)
2194 #define fill_buffer_image_param(x, ...)
2198 * The pipe->set_shader_images() driver hook.
2201 iris_set_shader_images(struct pipe_context
*ctx
,
2202 enum pipe_shader_type p_stage
,
2203 unsigned start_slot
, unsigned count
,
2204 const struct pipe_image_view
*p_images
)
2206 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2207 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2208 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2209 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2210 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2212 struct iris_genx_state
*genx
= ice
->state
.genx
;
2213 struct brw_image_param
*image_params
= genx
->shaders
[stage
].image_param
;
2216 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
2218 for (unsigned i
= 0; i
< count
; i
++) {
2219 struct iris_image_view
*iv
= &shs
->image
[start_slot
+ i
];
2221 if (p_images
&& p_images
[i
].resource
) {
2222 const struct pipe_image_view
*img
= &p_images
[i
];
2223 struct iris_resource
*res
= (void *) img
->resource
;
2226 alloc_surface_states(ice
->state
.surface_uploader
,
2227 &iv
->surface_state
, 1 << ISL_AUX_USAGE_NONE
);
2231 util_copy_image_view(&iv
->base
, img
);
2233 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
2235 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
2237 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
2238 enum isl_format isl_fmt
=
2239 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
2241 bool untyped_fallback
= false;
2243 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
2244 /* On Gen8, try to use typed surfaces reads (which support a
2245 * limited number of formats), and if not possible, fall back
2248 untyped_fallback
= GEN_GEN
== 8 &&
2249 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
);
2251 if (untyped_fallback
)
2252 isl_fmt
= ISL_FORMAT_RAW
;
2254 isl_fmt
= isl_lower_storage_image_format(devinfo
, isl_fmt
);
2257 if (res
->base
.target
!= PIPE_BUFFER
) {
2258 struct isl_view view
= {
2260 .base_level
= img
->u
.tex
.level
,
2262 .base_array_layer
= img
->u
.tex
.first_layer
,
2263 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
2264 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2268 if (untyped_fallback
) {
2269 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2270 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2273 /* Images don't support compression */
2274 unsigned aux_modes
= 1 << ISL_AUX_USAGE_NONE
;
2276 enum isl_aux_usage usage
= u_bit_scan(&aux_modes
);
2278 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2279 &view
, usage
, 0, 0);
2281 map
+= SURFACE_STATE_ALIGNMENT
;
2285 isl_surf_fill_image_param(&screen
->isl_dev
,
2286 &image_params
[start_slot
+ i
],
2289 util_range_add(&res
->valid_buffer_range
, img
->u
.buf
.offset
,
2290 img
->u
.buf
.offset
+ img
->u
.buf
.size
);
2292 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2293 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2294 img
->u
.buf
.offset
, img
->u
.buf
.size
);
2295 fill_buffer_image_param(&image_params
[start_slot
+ i
],
2296 img
->format
, img
->u
.buf
.size
);
2299 pipe_resource_reference(&iv
->base
.resource
, NULL
);
2300 pipe_resource_reference(&iv
->surface_state
.res
, NULL
);
2301 fill_default_image_param(&image_params
[start_slot
+ i
]);
2305 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2307 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2308 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2310 /* Broadwell also needs brw_image_params re-uploaded */
2312 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2313 shs
->sysvals_need_upload
= true;
2319 * The pipe->set_sampler_views() driver hook.
2322 iris_set_sampler_views(struct pipe_context
*ctx
,
2323 enum pipe_shader_type p_stage
,
2324 unsigned start
, unsigned count
,
2325 struct pipe_sampler_view
**views
)
2327 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2328 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2329 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2331 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
2333 for (unsigned i
= 0; i
< count
; i
++) {
2334 struct pipe_sampler_view
*pview
= views
? views
[i
] : NULL
;
2335 pipe_sampler_view_reference((struct pipe_sampler_view
**)
2336 &shs
->textures
[start
+ i
], pview
);
2337 struct iris_sampler_view
*view
= (void *) pview
;
2339 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
2340 shs
->bound_sampler_views
|= 1 << (start
+ i
);
2344 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
2346 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2347 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2351 * The pipe->set_tess_state() driver hook.
2354 iris_set_tess_state(struct pipe_context
*ctx
,
2355 const float default_outer_level
[4],
2356 const float default_inner_level
[2])
2358 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2359 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
2361 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
2362 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
2364 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
2365 shs
->sysvals_need_upload
= true;
2369 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
2371 struct iris_surface
*surf
= (void *) p_surf
;
2372 pipe_resource_reference(&p_surf
->texture
, NULL
);
2373 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2374 pipe_resource_reference(&surf
->surface_state_read
.res
, NULL
);
2379 iris_set_clip_state(struct pipe_context
*ctx
,
2380 const struct pipe_clip_state
*state
)
2382 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2383 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
2384 struct iris_shader_state
*gshs
= &ice
->state
.shaders
[MESA_SHADER_GEOMETRY
];
2385 struct iris_shader_state
*tshs
= &ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
];
2387 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
2389 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
| IRIS_DIRTY_CONSTANTS_GS
|
2390 IRIS_DIRTY_CONSTANTS_TES
;
2391 shs
->sysvals_need_upload
= true;
2392 gshs
->sysvals_need_upload
= true;
2393 tshs
->sysvals_need_upload
= true;
2397 * The pipe->set_polygon_stipple() driver hook.
2400 iris_set_polygon_stipple(struct pipe_context
*ctx
,
2401 const struct pipe_poly_stipple
*state
)
2403 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2404 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
2405 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
2409 * The pipe->set_sample_mask() driver hook.
2412 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2414 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2416 /* We only support 16x MSAA, so we have 16 bits of sample maks.
2417 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
2419 ice
->state
.sample_mask
= sample_mask
& 0xffff;
2420 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
2424 * The pipe->set_scissor_states() driver hook.
2426 * This corresponds to our SCISSOR_RECT state structures. It's an
2427 * exact match, so we just store them, and memcpy them out later.
2430 iris_set_scissor_states(struct pipe_context
*ctx
,
2431 unsigned start_slot
,
2432 unsigned num_scissors
,
2433 const struct pipe_scissor_state
*rects
)
2435 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2437 for (unsigned i
= 0; i
< num_scissors
; i
++) {
2438 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
2439 /* If the scissor was out of bounds and got clamped to 0 width/height
2440 * at the bounds, the subtraction of 1 from maximums could produce a
2441 * negative number and thus not clip anything. Instead, just provide
2442 * a min > max scissor inside the bounds, which produces the expected
2445 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2446 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
2449 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2450 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
2451 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
2456 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
2460 * The pipe->set_stencil_ref() driver hook.
2462 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
2465 iris_set_stencil_ref(struct pipe_context
*ctx
,
2466 const struct pipe_stencil_ref
*state
)
2468 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2469 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2471 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2473 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2477 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2479 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2483 * The pipe->set_viewport_states() driver hook.
2485 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2486 * the guardband yet, as we need the framebuffer dimensions, but we can
2487 * at least fill out the rest.
2490 iris_set_viewport_states(struct pipe_context
*ctx
,
2491 unsigned start_slot
,
2493 const struct pipe_viewport_state
*states
)
2495 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2497 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2499 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2501 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2502 !ice
->state
.cso_rast
->depth_clip_far
))
2503 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2507 * The pipe->set_framebuffer_state() driver hook.
2509 * Sets the current draw FBO, including color render targets, depth,
2510 * and stencil buffers.
2513 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2514 const struct pipe_framebuffer_state
*state
)
2516 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2517 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2518 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2519 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2520 struct iris_resource
*zres
;
2521 struct iris_resource
*stencil_res
;
2523 unsigned samples
= util_framebuffer_get_num_samples(state
);
2524 unsigned layers
= util_framebuffer_get_num_layers(state
);
2526 if (cso
->samples
!= samples
) {
2527 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2529 /* We need to toggle 3DSTATE_PS::32 Pixel Dispatch Enable */
2530 if (GEN_GEN
>= 9 && (cso
->samples
== 16 || samples
== 16))
2531 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
2534 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2535 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2538 if ((cso
->layers
== 0) != (layers
== 0)) {
2539 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2542 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2543 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2546 if (cso
->zsbuf
|| state
->zsbuf
) {
2547 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2550 util_copy_framebuffer_state(cso
, state
);
2551 cso
->samples
= samples
;
2552 cso
->layers
= layers
;
2554 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2556 struct isl_view view
= {
2559 .base_array_layer
= 0,
2561 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2564 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
2567 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2570 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2571 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2573 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2576 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2578 info
.depth_surf
= &zres
->surf
;
2579 info
.depth_address
= zres
->bo
->gtt_offset
+ zres
->offset
;
2580 info
.mocs
= mocs(zres
->bo
);
2582 view
.format
= zres
->surf
.format
;
2584 if (iris_resource_level_has_hiz(zres
, view
.base_level
)) {
2585 info
.hiz_usage
= ISL_AUX_USAGE_HIZ
;
2586 info
.hiz_surf
= &zres
->aux
.surf
;
2587 info
.hiz_address
= zres
->aux
.bo
->gtt_offset
+ zres
->aux
.offset
;
2592 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2593 info
.stencil_surf
= &stencil_res
->surf
;
2594 info
.stencil_address
= stencil_res
->bo
->gtt_offset
+ stencil_res
->offset
;
2596 view
.format
= stencil_res
->surf
.format
;
2597 info
.mocs
= mocs(stencil_res
->bo
);
2602 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2604 /* Make a null surface for unbound buffers */
2605 void *null_surf_map
=
2606 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2607 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2608 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2609 isl_extent3d(MAX2(cso
->width
, 1),
2610 MAX2(cso
->height
, 1),
2611 cso
->layers
? cso
->layers
: 1));
2612 ice
->state
.null_fb
.offset
+=
2613 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2615 /* Render target change */
2616 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2618 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2620 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2623 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2624 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2626 /* The PIPE_CONTROL command description says:
2628 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2629 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2630 * Target Cache Flush by enabling this bit. When render target flush
2631 * is set due to new association of BTI, PS Scoreboard Stall bit must
2632 * be set in this packet."
2634 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2635 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2636 "workaround: RT BTI change [draw]",
2637 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2638 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2643 * The pipe->set_constant_buffer() driver hook.
2645 * This uploads any constant data in user buffers, and references
2646 * any UBO resources containing constant data.
2649 iris_set_constant_buffer(struct pipe_context
*ctx
,
2650 enum pipe_shader_type p_stage
, unsigned index
,
2651 const struct pipe_constant_buffer
*input
)
2653 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2654 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2655 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2656 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[index
];
2658 if (input
&& input
->buffer_size
&& (input
->buffer
|| input
->user_buffer
)) {
2659 shs
->bound_cbufs
|= 1u << index
;
2661 if (input
->user_buffer
) {
2663 pipe_resource_reference(&cbuf
->buffer
, NULL
);
2664 u_upload_alloc(ice
->ctx
.const_uploader
, 0, input
->buffer_size
, 64,
2665 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
2667 if (!cbuf
->buffer
) {
2668 /* Allocation was unsuccessful - just unbind */
2669 iris_set_constant_buffer(ctx
, p_stage
, index
, NULL
);
2674 memcpy(map
, input
->user_buffer
, input
->buffer_size
);
2675 } else if (input
->buffer
) {
2676 pipe_resource_reference(&cbuf
->buffer
, input
->buffer
);
2678 cbuf
->buffer_offset
= input
->buffer_offset
;
2680 MIN2(input
->buffer_size
,
2681 iris_resource_bo(cbuf
->buffer
)->size
- cbuf
->buffer_offset
);
2684 struct iris_resource
*res
= (void *) cbuf
->buffer
;
2685 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2687 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
2688 &shs
->constbuf_surf_state
[index
],
2691 shs
->bound_cbufs
&= ~(1u << index
);
2692 pipe_resource_reference(&cbuf
->buffer
, NULL
);
2693 pipe_resource_reference(&shs
->constbuf_surf_state
[index
].res
, NULL
);
2696 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2697 // XXX: maybe not necessary all the time...?
2698 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2699 // XXX: pull model we may need actual new bindings...
2700 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2704 upload_sysvals(struct iris_context
*ice
,
2705 gl_shader_stage stage
)
2707 UNUSED
struct iris_genx_state
*genx
= ice
->state
.genx
;
2708 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2710 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2711 if (!shader
|| shader
->num_system_values
== 0)
2714 assert(shader
->num_cbufs
> 0);
2716 unsigned sysval_cbuf_index
= shader
->num_cbufs
- 1;
2717 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[sysval_cbuf_index
];
2718 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t);
2719 uint32_t *map
= NULL
;
2721 assert(sysval_cbuf_index
< PIPE_MAX_CONSTANT_BUFFERS
);
2722 u_upload_alloc(ice
->ctx
.const_uploader
, 0, upload_size
, 64,
2723 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
2725 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2726 uint32_t sysval
= shader
->system_values
[i
];
2729 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
2731 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
2732 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
2733 struct brw_image_param
*param
=
2734 &genx
->shaders
[stage
].image_param
[img
];
2736 assert(offset
< sizeof(struct brw_image_param
));
2737 value
= ((uint32_t *) param
)[offset
];
2739 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
2741 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2742 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2743 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2744 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2745 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
2746 if (stage
== MESA_SHADER_TESS_CTRL
) {
2747 value
= ice
->state
.vertices_per_patch
;
2749 assert(stage
== MESA_SHADER_TESS_EVAL
);
2750 const struct shader_info
*tcs_info
=
2751 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
2753 value
= tcs_info
->tess
.tcs_vertices_out
;
2755 value
= ice
->state
.vertices_per_patch
;
2757 } else if (sysval
>= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
&&
2758 sysval
<= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
) {
2759 unsigned i
= sysval
- BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
2760 value
= fui(ice
->state
.default_outer_level
[i
]);
2761 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
) {
2762 value
= fui(ice
->state
.default_inner_level
[0]);
2763 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
) {
2764 value
= fui(ice
->state
.default_inner_level
[1]);
2766 assert(!"unhandled system value");
2772 cbuf
->buffer_size
= upload_size
;
2773 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
2774 &shs
->constbuf_surf_state
[sysval_cbuf_index
], false);
2776 shs
->sysvals_need_upload
= false;
2780 * The pipe->set_shader_buffers() driver hook.
2782 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2783 * SURFACE_STATE here, as the buffer offset may change each time.
2786 iris_set_shader_buffers(struct pipe_context
*ctx
,
2787 enum pipe_shader_type p_stage
,
2788 unsigned start_slot
, unsigned count
,
2789 const struct pipe_shader_buffer
*buffers
,
2790 unsigned writable_bitmask
)
2792 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2793 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2794 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2796 unsigned modified_bits
= u_bit_consecutive(start_slot
, count
);
2798 shs
->bound_ssbos
&= ~modified_bits
;
2799 shs
->writable_ssbos
&= ~modified_bits
;
2800 shs
->writable_ssbos
|= writable_bitmask
<< start_slot
;
2802 for (unsigned i
= 0; i
< count
; i
++) {
2803 if (buffers
&& buffers
[i
].buffer
) {
2804 struct iris_resource
*res
= (void *) buffers
[i
].buffer
;
2805 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[start_slot
+ i
];
2806 struct iris_state_ref
*surf_state
=
2807 &shs
->ssbo_surf_state
[start_slot
+ i
];
2808 pipe_resource_reference(&ssbo
->buffer
, &res
->base
);
2809 ssbo
->buffer_offset
= buffers
[i
].buffer_offset
;
2811 MIN2(buffers
[i
].buffer_size
, res
->bo
->size
- ssbo
->buffer_offset
);
2813 shs
->bound_ssbos
|= 1 << (start_slot
+ i
);
2815 iris_upload_ubo_ssbo_surf_state(ice
, ssbo
, surf_state
, true);
2817 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2819 util_range_add(&res
->valid_buffer_range
, ssbo
->buffer_offset
,
2820 ssbo
->buffer_offset
+ ssbo
->buffer_size
);
2822 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
].buffer
, NULL
);
2823 pipe_resource_reference(&shs
->ssbo_surf_state
[start_slot
+ i
].res
,
2828 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2832 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2838 * The pipe->set_vertex_buffers() driver hook.
2840 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2843 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2844 unsigned start_slot
, unsigned count
,
2845 const struct pipe_vertex_buffer
*buffers
)
2847 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2848 struct iris_genx_state
*genx
= ice
->state
.genx
;
2850 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
2852 for (unsigned i
= 0; i
< count
; i
++) {
2853 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
2854 struct iris_vertex_buffer_state
*state
=
2855 &genx
->vertex_buffers
[start_slot
+ i
];
2858 pipe_resource_reference(&state
->resource
, NULL
);
2862 /* We may see user buffers that are NULL bindings. */
2863 assert(!(buffer
->is_user_buffer
&& buffer
->buffer
.user
!= NULL
));
2865 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
2866 struct iris_resource
*res
= (void *) state
->resource
;
2869 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
2870 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2873 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
2874 vb
.VertexBufferIndex
= start_slot
+ i
;
2875 vb
.AddressModifyEnable
= true;
2876 vb
.BufferPitch
= buffer
->stride
;
2878 vb
.BufferSize
= res
->bo
->size
- (int) buffer
->buffer_offset
;
2879 vb
.BufferStartingAddress
=
2880 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
2881 vb
.MOCS
= mocs(res
->bo
);
2883 vb
.NullVertexBuffer
= true;
2888 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2892 * Gallium CSO for vertex elements.
2894 struct iris_vertex_element_state
{
2895 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2896 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2897 uint32_t edgeflag_ve
[GENX(VERTEX_ELEMENT_STATE_length
)];
2898 uint32_t edgeflag_vfi
[GENX(3DSTATE_VF_INSTANCING_length
)];
2903 * The pipe->create_vertex_elements() driver hook.
2905 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2906 * and 3DSTATE_VF_INSTANCING commands. The vertex_elements and vf_instancing
2907 * arrays are ready to be emitted at draw time if no EdgeFlag or SGVs are
2908 * needed. In these cases we will need information available at draw time.
2909 * We setup edgeflag_ve and edgeflag_vfi as alternatives last
2910 * 3DSTATE_VERTEX_ELEMENT and 3DSTATE_VF_INSTANCING that can be used at
2911 * draw time if we detect that EdgeFlag is needed by the Vertex Shader.
2914 iris_create_vertex_elements(struct pipe_context
*ctx
,
2916 const struct pipe_vertex_element
*state
)
2918 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2919 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2920 struct iris_vertex_element_state
*cso
=
2921 malloc(sizeof(struct iris_vertex_element_state
));
2925 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2927 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2930 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2931 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2934 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2936 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2937 ve
.Component0Control
= VFCOMP_STORE_0
;
2938 ve
.Component1Control
= VFCOMP_STORE_0
;
2939 ve
.Component2Control
= VFCOMP_STORE_0
;
2940 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2943 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2947 for (int i
= 0; i
< count
; i
++) {
2948 const struct iris_format_info fmt
=
2949 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2950 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2951 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2953 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2954 case 0: comp
[0] = VFCOMP_STORE_0
; /* fallthrough */
2955 case 1: comp
[1] = VFCOMP_STORE_0
; /* fallthrough */
2956 case 2: comp
[2] = VFCOMP_STORE_0
; /* fallthrough */
2958 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2959 : VFCOMP_STORE_1_FP
;
2962 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2963 ve
.EdgeFlagEnable
= false;
2964 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2966 ve
.SourceElementOffset
= state
[i
].src_offset
;
2967 ve
.SourceElementFormat
= fmt
.fmt
;
2968 ve
.Component0Control
= comp
[0];
2969 ve
.Component1Control
= comp
[1];
2970 ve
.Component2Control
= comp
[2];
2971 ve
.Component3Control
= comp
[3];
2974 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2975 vi
.VertexElementIndex
= i
;
2976 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2977 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2980 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2981 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2984 /* An alternative version of the last VE and VFI is stored so it
2985 * can be used at draw time in case Vertex Shader uses EdgeFlag
2988 const unsigned edgeflag_index
= count
- 1;
2989 const struct iris_format_info fmt
=
2990 iris_format_for_usage(devinfo
, state
[edgeflag_index
].src_format
, 0);
2991 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), cso
->edgeflag_ve
, ve
) {
2992 ve
.EdgeFlagEnable
= true ;
2993 ve
.VertexBufferIndex
= state
[edgeflag_index
].vertex_buffer_index
;
2995 ve
.SourceElementOffset
= state
[edgeflag_index
].src_offset
;
2996 ve
.SourceElementFormat
= fmt
.fmt
;
2997 ve
.Component0Control
= VFCOMP_STORE_SRC
;
2998 ve
.Component1Control
= VFCOMP_STORE_0
;
2999 ve
.Component2Control
= VFCOMP_STORE_0
;
3000 ve
.Component3Control
= VFCOMP_STORE_0
;
3002 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->edgeflag_vfi
, vi
) {
3003 /* The vi.VertexElementIndex of the EdgeFlag Vertex Element is filled
3004 * at draw time, as it should change if SGVs are emitted.
3006 vi
.InstancingEnable
= state
[edgeflag_index
].instance_divisor
> 0;
3007 vi
.InstanceDataStepRate
= state
[edgeflag_index
].instance_divisor
;
3015 * The pipe->bind_vertex_elements_state() driver hook.
3018 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
3020 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3021 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
3022 struct iris_vertex_element_state
*new_cso
= state
;
3024 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
3025 * we need to re-emit it to ensure we're overriding the right one.
3027 if (new_cso
&& cso_changed(count
))
3028 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
3030 ice
->state
.cso_vertex_elements
= state
;
3031 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
3035 * The pipe->create_stream_output_target() driver hook.
3037 * "Target" here refers to a destination buffer. We translate this into
3038 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
3039 * know which buffer this represents, or whether we ought to zero the
3040 * write-offsets, or append. Those are handled in the set() hook.
3042 static struct pipe_stream_output_target
*
3043 iris_create_stream_output_target(struct pipe_context
*ctx
,
3044 struct pipe_resource
*p_res
,
3045 unsigned buffer_offset
,
3046 unsigned buffer_size
)
3048 struct iris_resource
*res
= (void *) p_res
;
3049 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
3053 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
3055 pipe_reference_init(&cso
->base
.reference
, 1);
3056 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
3057 cso
->base
.buffer_offset
= buffer_offset
;
3058 cso
->base
.buffer_size
= buffer_size
;
3059 cso
->base
.context
= ctx
;
3061 util_range_add(&res
->valid_buffer_range
, buffer_offset
,
3062 buffer_offset
+ buffer_size
);
3064 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
3070 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
3071 struct pipe_stream_output_target
*state
)
3073 struct iris_stream_output_target
*cso
= (void *) state
;
3075 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
3076 pipe_resource_reference(&cso
->offset
.res
, NULL
);
3082 * The pipe->set_stream_output_targets() driver hook.
3084 * At this point, we know which targets are bound to a particular index,
3085 * and also whether we want to append or start over. We can finish the
3086 * 3DSTATE_SO_BUFFER packets we started earlier.
3089 iris_set_stream_output_targets(struct pipe_context
*ctx
,
3090 unsigned num_targets
,
3091 struct pipe_stream_output_target
**targets
,
3092 const unsigned *offsets
)
3094 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3095 struct iris_genx_state
*genx
= ice
->state
.genx
;
3096 uint32_t *so_buffers
= genx
->so_buffers
;
3098 const bool active
= num_targets
> 0;
3099 if (ice
->state
.streamout_active
!= active
) {
3100 ice
->state
.streamout_active
= active
;
3101 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
3103 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
3104 * it's a non-pipelined command. If we're switching streamout on, we
3105 * may have missed emitting it earlier, so do so now. (We're already
3106 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
3109 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
3112 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3113 struct iris_stream_output_target
*tgt
=
3114 (void *) ice
->state
.so_target
[i
];
3116 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3118 flush
|= iris_flush_bits_for_history(res
);
3119 iris_dirty_for_history(ice
, res
);
3122 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
3123 "make streamout results visible", flush
);
3127 for (int i
= 0; i
< 4; i
++) {
3128 pipe_so_target_reference(&ice
->state
.so_target
[i
],
3129 i
< num_targets
? targets
[i
] : NULL
);
3132 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
3136 for (unsigned i
= 0; i
< 4; i
++,
3137 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
3139 struct iris_stream_output_target
*tgt
= (void *) ice
->state
.so_target
[i
];
3140 unsigned offset
= offsets
[i
];
3143 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
3144 sob
.SOBufferIndex
= i
;
3148 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3150 /* Note that offsets[i] will either be 0, causing us to zero
3151 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
3152 * "continue appending at the existing offset."
3154 assert(offset
== 0 || offset
== 0xFFFFFFFF);
3156 /* We might be called by Begin (offset = 0), Pause, then Resume
3157 * (offset = 0xFFFFFFFF) before ever drawing (where these commands
3158 * will actually be sent to the GPU). In this case, we don't want
3159 * to append - we still want to do our initial zeroing.
3164 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
3165 sob
.SurfaceBaseAddress
=
3166 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
3167 sob
.SOBufferEnable
= true;
3168 sob
.StreamOffsetWriteEnable
= true;
3169 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3170 sob
.MOCS
= mocs(res
->bo
);
3172 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
3174 sob
.SOBufferIndex
= i
;
3175 sob
.StreamOffset
= offset
;
3176 sob
.StreamOutputBufferOffsetAddress
=
3177 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
3178 tgt
->offset
.offset
);
3182 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
3186 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
3187 * 3DSTATE_STREAMOUT packets.
3189 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
3190 * hardware to record. We can create it entirely based on the shader, with
3191 * no dynamic state dependencies.
3193 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
3194 * state-based settings. We capture the shader-related ones here, and merge
3195 * the rest in at draw time.
3198 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
3199 const struct brw_vue_map
*vue_map
)
3201 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3202 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3203 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3204 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3206 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3208 memset(so_decl
, 0, sizeof(so_decl
));
3210 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3211 * command feels strange -- each dword pair contains a SO_DECL per stream.
3213 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
3214 const struct pipe_stream_output
*output
= &info
->output
[i
];
3215 const int buffer
= output
->output_buffer
;
3216 const int varying
= output
->register_index
;
3217 const unsigned stream_id
= output
->stream
;
3218 assert(stream_id
< MAX_VERTEX_STREAMS
);
3220 buffer_mask
[stream_id
] |= 1 << buffer
;
3222 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3224 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3225 * array. Instead, it simply increments DstOffset for the following
3226 * input by the number of components that should be skipped.
3228 * Our hardware is unusual in that it requires us to program SO_DECLs
3229 * for fake "hole" components, rather than simply taking the offset
3230 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3231 * program as many size = 4 holes as we can, then a final hole to
3232 * accommodate the final 1, 2, or 3 remaining.
3234 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
3236 while (skip_components
> 0) {
3237 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3239 .OutputBufferSlot
= output
->output_buffer
,
3240 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3242 skip_components
-= 4;
3245 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
3247 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3248 .OutputBufferSlot
= output
->output_buffer
,
3249 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3251 ((1 << output
->num_components
) - 1) << output
->start_component
,
3254 if (decls
[stream_id
] > max_decls
)
3255 max_decls
= decls
[stream_id
];
3258 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
3259 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
3260 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
3262 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
3263 int urb_entry_read_offset
= 0;
3264 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3265 urb_entry_read_offset
;
3267 /* We always read the whole vertex. This could be reduced at some
3268 * point by reading less and offsetting the register index in the
3271 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3272 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3273 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3274 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3275 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3276 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3277 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3278 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3280 /* Set buffer pitches; 0 means unbound. */
3281 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
3282 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
3283 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
3284 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
3287 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
3288 list
.DWordLength
= 3 + 2 * max_decls
- 2;
3289 list
.StreamtoBufferSelects0
= buffer_mask
[0];
3290 list
.StreamtoBufferSelects1
= buffer_mask
[1];
3291 list
.StreamtoBufferSelects2
= buffer_mask
[2];
3292 list
.StreamtoBufferSelects3
= buffer_mask
[3];
3293 list
.NumEntries0
= decls
[0];
3294 list
.NumEntries1
= decls
[1];
3295 list
.NumEntries2
= decls
[2];
3296 list
.NumEntries3
= decls
[3];
3299 for (int i
= 0; i
< max_decls
; i
++) {
3300 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
3301 entry
.Stream0Decl
= so_decl
[0][i
];
3302 entry
.Stream1Decl
= so_decl
[1][i
];
3303 entry
.Stream2Decl
= so_decl
[2][i
];
3304 entry
.Stream3Decl
= so_decl
[3][i
];
3312 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
3313 const struct brw_vue_map
*last_vue_map
,
3314 bool two_sided_color
,
3315 unsigned *out_offset
,
3316 unsigned *out_length
)
3318 /* The compiler computes the first URB slot without considering COL/BFC
3319 * swizzling (because it doesn't know whether it's enabled), so we need
3320 * to do that here too. This may result in a smaller offset, which
3323 const unsigned first_slot
=
3324 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
3326 /* This becomes the URB read offset (counted in pairs of slots). */
3327 assert(first_slot
% 2 == 0);
3328 *out_offset
= first_slot
/ 2;
3330 /* We need to adjust the inputs read to account for front/back color
3331 * swizzling, as it can make the URB length longer.
3333 for (int c
= 0; c
<= 1; c
++) {
3334 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
3335 /* If two sided color is enabled, the fragment shader's gl_Color
3336 * (COL0) input comes from either the gl_FrontColor (COL0) or
3337 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
3339 if (two_sided_color
)
3340 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3342 /* If front color isn't written, we opt to give them back color
3343 * instead of an undefined value. Switch from COL to BFC.
3345 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
3346 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
3347 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3352 /* Compute the minimum URB Read Length necessary for the FS inputs.
3354 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
3355 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
3357 * "This field should be set to the minimum length required to read the
3358 * maximum source attribute. The maximum source attribute is indicated
3359 * by the maximum value of the enabled Attribute # Source Attribute if
3360 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
3361 * enable is not set.
3362 * read_length = ceiling((max_source_attr + 1) / 2)
3364 * [errata] Corruption/Hang possible if length programmed larger than
3367 * Similar text exists for Ivy Bridge.
3369 * We find the last URB slot that's actually read by the FS.
3371 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
3372 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
3373 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
3376 /* The URB read length is the difference of the two, counted in pairs. */
3377 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
3381 iris_emit_sbe_swiz(struct iris_batch
*batch
,
3382 const struct iris_context
*ice
,
3383 unsigned urb_read_offset
,
3384 unsigned sprite_coord_enables
)
3386 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
3387 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3388 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3389 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
3390 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3392 /* XXX: this should be generated when putting programs in place */
3394 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
3395 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
3396 if (input_index
< 0 || input_index
>= 16)
3399 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
3400 &attr_overrides
[input_index
];
3401 int slot
= vue_map
->varying_to_slot
[fs_attr
];
3403 /* Viewport and Layer are stored in the VUE header. We need to override
3404 * them to zero if earlier stages didn't write them, as GL requires that
3405 * they read back as zero when not explicitly set.
3408 case VARYING_SLOT_VIEWPORT
:
3409 case VARYING_SLOT_LAYER
:
3410 attr
->ComponentOverrideX
= true;
3411 attr
->ComponentOverrideW
= true;
3412 attr
->ConstantSource
= CONST_0000
;
3414 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
3415 attr
->ComponentOverrideY
= true;
3416 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
3417 attr
->ComponentOverrideZ
= true;
3420 case VARYING_SLOT_PRIMITIVE_ID
:
3421 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
3423 attr
->ComponentOverrideX
= true;
3424 attr
->ComponentOverrideY
= true;
3425 attr
->ComponentOverrideZ
= true;
3426 attr
->ComponentOverrideW
= true;
3427 attr
->ConstantSource
= PRIM_ID
;
3435 if (sprite_coord_enables
& (1 << input_index
))
3438 /* If there was only a back color written but not front, use back
3439 * as the color instead of undefined.
3441 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
3442 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
3443 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
3444 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
3446 /* Not written by the previous stage - undefined. */
3448 attr
->ComponentOverrideX
= true;
3449 attr
->ComponentOverrideY
= true;
3450 attr
->ComponentOverrideZ
= true;
3451 attr
->ComponentOverrideW
= true;
3452 attr
->ConstantSource
= CONST_0001_FLOAT
;
3456 /* Compute the location of the attribute relative to the read offset,
3457 * which is counted in 256-bit increments (two 128-bit VUE slots).
3459 const int source_attr
= slot
- 2 * urb_read_offset
;
3460 assert(source_attr
>= 0 && source_attr
<= 32);
3461 attr
->SourceAttribute
= source_attr
;
3463 /* If we are doing two-sided color, and the VUE slot following this one
3464 * represents a back-facing color, then we need to instruct the SF unit
3465 * to do back-facing swizzling.
3467 if (cso_rast
->light_twoside
&&
3468 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3469 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3470 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3471 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3472 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3475 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3476 for (int i
= 0; i
< 16; i
++)
3477 sbes
.Attribute
[i
] = attr_overrides
[i
];
3482 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3483 const struct iris_rasterizer_state
*cso
)
3485 unsigned overrides
= 0;
3487 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
3488 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
3490 for (int i
= 0; i
< 8; i
++) {
3491 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
3492 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
3493 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
3500 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
3502 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3503 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3504 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3505 const struct shader_info
*fs_info
=
3506 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
3508 unsigned urb_read_offset
, urb_read_length
;
3509 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
3510 ice
->shaders
.last_vue_map
,
3511 cso_rast
->light_twoside
,
3512 &urb_read_offset
, &urb_read_length
);
3514 unsigned sprite_coord_overrides
=
3515 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3517 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
3518 sbe
.AttributeSwizzleEnable
= true;
3519 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3520 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3521 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3522 sbe
.VertexURBEntryReadLength
= urb_read_length
;
3523 sbe
.ForceVertexURBEntryReadOffset
= true;
3524 sbe
.ForceVertexURBEntryReadLength
= true;
3525 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3526 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
3528 for (int i
= 0; i
< 32; i
++) {
3529 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3534 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
3537 /* ------------------------------------------------------------------- */
3540 * Populate VS program key fields based on the current state.
3543 iris_populate_vs_key(const struct iris_context
*ice
,
3544 const struct shader_info
*info
,
3545 gl_shader_stage last_stage
,
3546 struct brw_vs_prog_key
*key
)
3548 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3550 if (info
->clip_distance_array_size
== 0 &&
3551 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
3552 last_stage
== MESA_SHADER_VERTEX
)
3553 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3557 * Populate TCS program key fields based on the current state.
3560 iris_populate_tcs_key(const struct iris_context
*ice
,
3561 struct brw_tcs_prog_key
*key
)
3566 * Populate TES program key fields based on the current state.
3569 iris_populate_tes_key(const struct iris_context
*ice
,
3570 const struct shader_info
*info
,
3571 gl_shader_stage last_stage
,
3572 struct brw_tes_prog_key
*key
)
3574 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3576 if (info
->clip_distance_array_size
== 0 &&
3577 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
3578 last_stage
== MESA_SHADER_TESS_EVAL
)
3579 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3583 * Populate GS program key fields based on the current state.
3586 iris_populate_gs_key(const struct iris_context
*ice
,
3587 const struct shader_info
*info
,
3588 gl_shader_stage last_stage
,
3589 struct brw_gs_prog_key
*key
)
3591 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3593 if (info
->clip_distance_array_size
== 0 &&
3594 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
3595 last_stage
== MESA_SHADER_GEOMETRY
)
3596 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3600 * Populate FS program key fields based on the current state.
3603 iris_populate_fs_key(const struct iris_context
*ice
,
3604 const struct shader_info
*info
,
3605 struct brw_wm_prog_key
*key
)
3607 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3608 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3609 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3610 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3611 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3613 key
->nr_color_regions
= fb
->nr_cbufs
;
3615 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3617 key
->alpha_to_coverage
= blend
->alpha_to_coverage
;
3619 key
->alpha_test_replicate_alpha
= fb
->nr_cbufs
> 1 && zsa
->alpha
.enabled
;
3621 key
->flat_shade
= rast
->flatshade
&&
3622 (info
->inputs_read
& (VARYING_BIT_COL0
| VARYING_BIT_COL1
));
3624 key
->persample_interp
= rast
->force_persample_interp
;
3625 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3627 key
->coherent_fb_fetch
= true;
3629 key
->force_dual_color_blend
=
3630 screen
->driconf
.dual_color_blend_by_location
&&
3631 (blend
->blend_enables
& 1) && blend
->dual_color_blending
;
3633 /* TODO: Respect glHint for key->high_quality_derivatives */
3637 iris_populate_cs_key(const struct iris_context
*ice
,
3638 struct brw_cs_prog_key
*key
)
3643 KSP(const struct iris_compiled_shader
*shader
)
3645 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3646 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3649 /* Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3650 * prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3651 * this WA on C0 stepping.
3653 * TODO: Fill out SamplerCount for prefetching?
3656 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3657 pkt.KernelStartPointer = KSP(shader); \
3658 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3659 shader->bt.size_bytes / 4; \
3660 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3662 pkt.DispatchGRFStartRegisterForURBData = \
3663 prog_data->dispatch_grf_start_reg; \
3664 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3665 pkt.prefix##URBEntryReadOffset = 0; \
3667 pkt.StatisticsEnable = true; \
3668 pkt.Enable = true; \
3670 if (prog_data->total_scratch) { \
3671 struct iris_bo *bo = \
3672 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3673 uint32_t scratch_addr = bo->gtt_offset; \
3674 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3675 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3679 * Encode most of 3DSTATE_VS based on the compiled shader.
3682 iris_store_vs_state(struct iris_context
*ice
,
3683 const struct gen_device_info
*devinfo
,
3684 struct iris_compiled_shader
*shader
)
3686 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3687 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3689 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3690 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3691 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3692 vs
.SIMD8DispatchEnable
= true;
3693 vs
.UserClipDistanceCullTestEnableBitmask
=
3694 vue_prog_data
->cull_distance_mask
;
3699 * Encode most of 3DSTATE_HS based on the compiled shader.
3702 iris_store_tcs_state(struct iris_context
*ice
,
3703 const struct gen_device_info
*devinfo
,
3704 struct iris_compiled_shader
*shader
)
3706 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3707 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3708 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3710 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3711 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3713 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3714 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3715 hs
.IncludeVertexHandles
= true;
3718 hs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
3719 hs
.IncludePrimitiveID
= tcs_prog_data
->include_primitive_id
;
3725 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3728 iris_store_tes_state(struct iris_context
*ice
,
3729 const struct gen_device_info
*devinfo
,
3730 struct iris_compiled_shader
*shader
)
3732 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3733 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3734 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3736 uint32_t *te_state
= (void *) shader
->derived_data
;
3737 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3739 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3740 te
.Partitioning
= tes_prog_data
->partitioning
;
3741 te
.OutputTopology
= tes_prog_data
->output_topology
;
3742 te
.TEDomain
= tes_prog_data
->domain
;
3744 te
.MaximumTessellationFactorOdd
= 63.0;
3745 te
.MaximumTessellationFactorNotOdd
= 64.0;
3748 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3749 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3751 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3752 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3753 ds
.ComputeWCoordinateEnable
=
3754 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3756 ds
.UserClipDistanceCullTestEnableBitmask
=
3757 vue_prog_data
->cull_distance_mask
;
3763 * Encode most of 3DSTATE_GS based on the compiled shader.
3766 iris_store_gs_state(struct iris_context
*ice
,
3767 const struct gen_device_info
*devinfo
,
3768 struct iris_compiled_shader
*shader
)
3770 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3771 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3772 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3774 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3775 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3777 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3778 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3779 gs
.ControlDataHeaderSize
=
3780 gs_prog_data
->control_data_header_size_hwords
;
3781 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3782 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3783 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3784 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3785 gs
.ReorderMode
= TRAILING
;
3786 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3787 gs
.MaximumNumberofThreads
=
3788 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3789 : (devinfo
->max_gs_threads
- 1);
3791 if (gs_prog_data
->static_vertex_count
!= -1) {
3792 gs
.StaticOutput
= true;
3793 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3795 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3797 gs
.UserClipDistanceCullTestEnableBitmask
=
3798 vue_prog_data
->cull_distance_mask
;
3800 const int urb_entry_write_offset
= 1;
3801 const uint32_t urb_entry_output_length
=
3802 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3803 urb_entry_write_offset
;
3805 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3806 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3811 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3814 iris_store_fs_state(struct iris_context
*ice
,
3815 const struct gen_device_info
*devinfo
,
3816 struct iris_compiled_shader
*shader
)
3818 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3819 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3821 uint32_t *ps_state
= (void *) shader
->derived_data
;
3822 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3824 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3825 ps
.VectorMaskEnable
= true;
3826 // XXX: WABTPPrefetchDisable, see above, drop at C0
3827 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3828 shader
->bt
.size_bytes
/ 4;
3829 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3830 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3832 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
3834 /* From the documentation for this packet:
3835 * "If the PS kernel does not need the Position XY Offsets to
3836 * compute a Position Value, then this field should be programmed
3837 * to POSOFFSET_NONE."
3839 * "SW Recommendation: If the PS kernel needs the Position Offsets
3840 * to compute a Position XY value, this field should match Position
3841 * ZW Interpolation Mode to ensure a consistent position.xyzw
3844 * We only require XY sample offsets. So, this recommendation doesn't
3845 * look useful at the moment. We might need this in future.
3847 ps
.PositionXYOffsetSelect
=
3848 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3850 if (prog_data
->total_scratch
) {
3851 struct iris_bo
*bo
=
3852 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3853 MESA_SHADER_FRAGMENT
);
3854 uint32_t scratch_addr
= bo
->gtt_offset
;
3855 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3856 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3860 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3861 psx
.PixelShaderValid
= true;
3862 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3863 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
3864 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3865 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3866 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3867 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3868 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3871 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3872 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3878 * Compute the size of the derived data (shader command packets).
3880 * This must match the data written by the iris_store_xs_state() functions.
3883 iris_store_cs_state(struct iris_context
*ice
,
3884 const struct gen_device_info
*devinfo
,
3885 struct iris_compiled_shader
*shader
)
3887 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3888 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3889 void *map
= shader
->derived_data
;
3891 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3892 desc
.KernelStartPointer
= KSP(shader
);
3893 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3894 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3895 desc
.SharedLocalMemorySize
=
3896 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3897 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3898 desc
.CrossThreadConstantDataReadLength
=
3899 cs_prog_data
->push
.cross_thread
.regs
;
3904 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3906 assert(cache_id
<= IRIS_CACHE_BLORP
);
3908 static const unsigned dwords
[] = {
3909 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3910 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3911 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3912 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3914 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3915 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3916 [IRIS_CACHE_BLORP
] = 0,
3919 return sizeof(uint32_t) * dwords
[cache_id
];
3923 * Create any state packets corresponding to the given shader stage
3924 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3925 * This means that we can look up a program in the in-memory cache and
3926 * get most of the state packet without having to reconstruct it.
3929 iris_store_derived_program_state(struct iris_context
*ice
,
3930 enum iris_program_cache_id cache_id
,
3931 struct iris_compiled_shader
*shader
)
3933 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3934 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3938 iris_store_vs_state(ice
, devinfo
, shader
);
3940 case IRIS_CACHE_TCS
:
3941 iris_store_tcs_state(ice
, devinfo
, shader
);
3943 case IRIS_CACHE_TES
:
3944 iris_store_tes_state(ice
, devinfo
, shader
);
3947 iris_store_gs_state(ice
, devinfo
, shader
);
3950 iris_store_fs_state(ice
, devinfo
, shader
);
3953 iris_store_cs_state(ice
, devinfo
, shader
);
3954 case IRIS_CACHE_BLORP
:
3961 /* ------------------------------------------------------------------- */
3963 static const uint32_t push_constant_opcodes
[] = {
3964 [MESA_SHADER_VERTEX
] = 21,
3965 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3966 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3967 [MESA_SHADER_GEOMETRY
] = 22,
3968 [MESA_SHADER_FRAGMENT
] = 23,
3969 [MESA_SHADER_COMPUTE
] = 0,
3973 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3975 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3977 iris_use_pinned_bo(batch
, state_bo
, false);
3979 return ice
->state
.unbound_tex
.offset
;
3983 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3985 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3986 if (!ice
->state
.null_fb
.res
)
3987 return use_null_surface(batch
, ice
);
3989 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3991 iris_use_pinned_bo(batch
, state_bo
, false);
3993 return ice
->state
.null_fb
.offset
;
3997 surf_state_offset_for_aux(struct iris_resource
*res
,
3999 enum isl_aux_usage aux_usage
)
4001 return SURFACE_STATE_ALIGNMENT
*
4002 util_bitcount(res
->aux
.possible_usages
& ((1 << aux_usage
) - 1));
4006 surf_state_update_clear_value(struct iris_batch
*batch
,
4007 struct iris_resource
*res
,
4008 struct iris_state_ref
*state
,
4010 enum isl_aux_usage aux_usage
)
4012 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
4013 struct iris_bo
*state_bo
= iris_resource_bo(state
->res
);
4014 uint64_t real_offset
= state
->offset
+
4015 IRIS_MEMZONE_BINDER_START
;
4016 uint32_t offset_into_bo
= real_offset
- state_bo
->gtt_offset
;
4017 uint32_t clear_offset
= offset_into_bo
+
4018 isl_dev
->ss
.clear_value_offset
+
4019 surf_state_offset_for_aux(res
, aux_modes
, aux_usage
);
4021 batch
->vtbl
->copy_mem_mem(batch
, state_bo
, clear_offset
,
4022 res
->aux
.clear_color_bo
,
4023 res
->aux
.clear_color_offset
,
4024 isl_dev
->ss
.clear_value_size
);
4028 update_clear_value(struct iris_context
*ice
,
4029 struct iris_batch
*batch
,
4030 struct iris_resource
*res
,
4031 struct iris_state_ref
*state
,
4033 struct isl_view
*view
)
4035 struct iris_screen
*screen
= batch
->screen
;
4036 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
4038 /* We only need to update the clear color in the surface state for gen8 and
4039 * gen9. Newer gens can read it directly from the clear color state buffer.
4041 if (devinfo
->gen
> 9)
4044 if (devinfo
->gen
== 9) {
4045 /* Skip updating the ISL_AUX_USAGE_NONE surface state */
4046 aux_modes
&= ~(1 << ISL_AUX_USAGE_NONE
);
4049 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4051 surf_state_update_clear_value(batch
, res
, state
, aux_modes
,
4054 } else if (devinfo
->gen
== 8) {
4055 pipe_resource_reference(&state
->res
, NULL
);
4056 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
4057 state
, res
->aux
.possible_usages
);
4059 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4060 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
, view
,
4062 map
+= SURFACE_STATE_ALIGNMENT
;
4068 * Add a surface to the validation list, as well as the buffer containing
4069 * the corresponding SURFACE_STATE.
4071 * Returns the binding table entry (offset to SURFACE_STATE).
4074 use_surface(struct iris_context
*ice
,
4075 struct iris_batch
*batch
,
4076 struct pipe_surface
*p_surf
,
4078 enum isl_aux_usage aux_usage
,
4079 bool is_read_surface
)
4081 struct iris_surface
*surf
= (void *) p_surf
;
4082 struct iris_resource
*res
= (void *) p_surf
->texture
;
4083 uint32_t offset
= 0;
4085 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
4086 if (GEN_GEN
== 8 && is_read_surface
) {
4087 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state_read
.res
), false);
4089 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
4093 iris_use_pinned_bo(batch
, res
->aux
.bo
, writeable
);
4094 if (res
->aux
.clear_color_bo
)
4095 iris_use_pinned_bo(batch
, res
->aux
.clear_color_bo
, false);
4097 if (memcmp(&res
->aux
.clear_color
, &surf
->clear_color
,
4098 sizeof(surf
->clear_color
)) != 0) {
4099 update_clear_value(ice
, batch
, res
, &surf
->surface_state
,
4100 res
->aux
.possible_usages
, &surf
->view
);
4102 update_clear_value(ice
, batch
, res
, &surf
->surface_state_read
,
4103 res
->aux
.possible_usages
, &surf
->read_view
);
4105 surf
->clear_color
= res
->aux
.clear_color
;
4109 offset
= (GEN_GEN
== 8 && is_read_surface
) ? surf
->surface_state_read
.offset
4110 : surf
->surface_state
.offset
;
4113 surf_state_offset_for_aux(res
, res
->aux
.possible_usages
, aux_usage
);
4117 use_sampler_view(struct iris_context
*ice
,
4118 struct iris_batch
*batch
,
4119 struct iris_sampler_view
*isv
)
4122 enum isl_aux_usage aux_usage
=
4123 iris_resource_texture_aux_usage(ice
, isv
->res
, isv
->view
.format
, 0);
4125 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
4126 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
4128 if (isv
->res
->aux
.bo
) {
4129 iris_use_pinned_bo(batch
, isv
->res
->aux
.bo
, false);
4130 if (isv
->res
->aux
.clear_color_bo
)
4131 iris_use_pinned_bo(batch
, isv
->res
->aux
.clear_color_bo
, false);
4132 if (memcmp(&isv
->res
->aux
.clear_color
, &isv
->clear_color
,
4133 sizeof(isv
->clear_color
)) != 0) {
4134 update_clear_value(ice
, batch
, isv
->res
, &isv
->surface_state
,
4135 isv
->res
->aux
.sampler_usages
, &isv
->view
);
4136 isv
->clear_color
= isv
->res
->aux
.clear_color
;
4140 return isv
->surface_state
.offset
+
4141 surf_state_offset_for_aux(isv
->res
, isv
->res
->aux
.sampler_usages
,
4146 use_ubo_ssbo(struct iris_batch
*batch
,
4147 struct iris_context
*ice
,
4148 struct pipe_shader_buffer
*buf
,
4149 struct iris_state_ref
*surf_state
,
4153 return use_null_surface(batch
, ice
);
4155 iris_use_pinned_bo(batch
, iris_resource_bo(buf
->buffer
), writable
);
4156 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
4158 return surf_state
->offset
;
4162 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
4163 struct iris_shader_state
*shs
, int i
)
4165 struct iris_image_view
*iv
= &shs
->image
[i
];
4166 struct iris_resource
*res
= (void *) iv
->base
.resource
;
4169 return use_null_surface(batch
, ice
);
4171 bool write
= iv
->base
.shader_access
& PIPE_IMAGE_ACCESS_WRITE
;
4173 iris_use_pinned_bo(batch
, res
->bo
, write
);
4174 iris_use_pinned_bo(batch
, iris_resource_bo(iv
->surface_state
.res
), false);
4177 iris_use_pinned_bo(batch
, res
->aux
.bo
, write
);
4179 return iv
->surface_state
.offset
;
4182 #define push_bt_entry(addr) \
4183 assert(addr >= binder_addr); \
4184 assert(s < shader->bt.size_bytes / sizeof(uint32_t)); \
4185 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
4187 #define bt_assert(section) \
4188 if (!pin_only && shader->bt.used_mask[section] != 0) \
4189 assert(shader->bt.offsets[section] == s);
4192 * Populate the binding table for a given shader stage.
4194 * This fills out the table of pointers to surfaces required by the shader,
4195 * and also adds those buffers to the validation list so the kernel can make
4196 * resident before running our batch.
4199 iris_populate_binding_table(struct iris_context
*ice
,
4200 struct iris_batch
*batch
,
4201 gl_shader_stage stage
,
4204 const struct iris_binder
*binder
= &ice
->state
.binder
;
4205 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
4206 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4210 struct iris_binding_table
*bt
= &shader
->bt
;
4211 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4212 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4213 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
4215 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
4218 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
4220 /* TCS passthrough doesn't need a binding table. */
4221 assert(stage
== MESA_SHADER_TESS_CTRL
);
4225 if (stage
== MESA_SHADER_COMPUTE
&&
4226 shader
->bt
.used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
]) {
4227 /* surface for gl_NumWorkGroups */
4228 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
4229 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
4230 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
4231 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
4232 push_bt_entry(grid_state
->offset
);
4235 if (stage
== MESA_SHADER_FRAGMENT
) {
4236 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4237 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
4238 if (cso_fb
->nr_cbufs
) {
4239 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
4241 if (cso_fb
->cbufs
[i
]) {
4242 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
], true,
4243 ice
->state
.draw_aux_usage
[i
], false);
4245 addr
= use_null_fb_surface(batch
, ice
);
4247 push_bt_entry(addr
);
4250 uint32_t addr
= use_null_fb_surface(batch
, ice
);
4251 push_bt_entry(addr
);
4255 #define foreach_surface_used(index, group) \
4257 for (int index = 0; index < bt->sizes[group]; index++) \
4258 if (iris_group_index_to_bti(bt, group, index) != \
4259 IRIS_SURFACE_NOT_USED)
4261 foreach_surface_used(i
, IRIS_SURFACE_GROUP_RENDER_TARGET_READ
) {
4262 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4264 if (cso_fb
->cbufs
[i
]) {
4265 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
],
4266 true, ice
->state
.draw_aux_usage
[i
], true);
4267 push_bt_entry(addr
);
4271 foreach_surface_used(i
, IRIS_SURFACE_GROUP_TEXTURE
) {
4272 struct iris_sampler_view
*view
= shs
->textures
[i
];
4273 uint32_t addr
= view
? use_sampler_view(ice
, batch
, view
)
4274 : use_null_surface(batch
, ice
);
4275 push_bt_entry(addr
);
4278 foreach_surface_used(i
, IRIS_SURFACE_GROUP_IMAGE
) {
4279 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
4280 push_bt_entry(addr
);
4283 foreach_surface_used(i
, IRIS_SURFACE_GROUP_UBO
) {
4286 if (i
== bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] - 1) {
4287 if (ish
->const_data
) {
4288 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data
), false);
4289 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data_state
.res
),
4291 addr
= ish
->const_data_state
.offset
;
4293 /* This can only happen with INTEL_DISABLE_COMPACT_BINDING_TABLE=1. */
4294 addr
= use_null_surface(batch
, ice
);
4297 addr
= use_ubo_ssbo(batch
, ice
, &shs
->constbuf
[i
],
4298 &shs
->constbuf_surf_state
[i
], false);
4301 push_bt_entry(addr
);
4304 foreach_surface_used(i
, IRIS_SURFACE_GROUP_SSBO
) {
4306 use_ubo_ssbo(batch
, ice
, &shs
->ssbo
[i
], &shs
->ssbo_surf_state
[i
],
4307 shs
->writable_ssbos
& (1u << i
));
4308 push_bt_entry(addr
);
4312 /* XXX: YUV surfaces not implemented yet */
4313 bt_assert(plane_start
[1], ...);
4314 bt_assert(plane_start
[2], ...);
4319 iris_use_optional_res(struct iris_batch
*batch
,
4320 struct pipe_resource
*res
,
4324 struct iris_bo
*bo
= iris_resource_bo(res
);
4325 iris_use_pinned_bo(batch
, bo
, writeable
);
4330 pin_depth_and_stencil_buffers(struct iris_batch
*batch
,
4331 struct pipe_surface
*zsbuf
,
4332 struct iris_depth_stencil_alpha_state
*cso_zsa
)
4337 struct iris_resource
*zres
, *sres
;
4338 iris_get_depth_stencil_resources(zsbuf
->texture
, &zres
, &sres
);
4341 iris_use_pinned_bo(batch
, zres
->bo
, cso_zsa
->depth_writes_enabled
);
4343 iris_use_pinned_bo(batch
, zres
->aux
.bo
,
4344 cso_zsa
->depth_writes_enabled
);
4349 iris_use_pinned_bo(batch
, sres
->bo
, cso_zsa
->stencil_writes_enabled
);
4353 /* ------------------------------------------------------------------- */
4356 * Pin any BOs which were installed by a previous batch, and restored
4357 * via the hardware logical context mechanism.
4359 * We don't need to re-emit all state every batch - the hardware context
4360 * mechanism will save and restore it for us. This includes pointers to
4361 * various BOs...which won't exist unless we ask the kernel to pin them
4362 * by adding them to the validation list.
4364 * We can skip buffers if we've re-emitted those packets, as we're
4365 * overwriting those stale pointers with new ones, and don't actually
4366 * refer to the old BOs.
4369 iris_restore_render_saved_bos(struct iris_context
*ice
,
4370 struct iris_batch
*batch
,
4371 const struct pipe_draw_info
*draw
)
4373 struct iris_genx_state
*genx
= ice
->state
.genx
;
4375 const uint64_t clean
= ~ice
->state
.dirty
;
4377 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
4378 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
4381 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4382 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
4385 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
4386 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
4389 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4390 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
4393 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
4394 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
4397 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
4398 for (int i
= 0; i
< 4; i
++) {
4399 struct iris_stream_output_target
*tgt
=
4400 (void *) ice
->state
.so_target
[i
];
4402 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4404 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4410 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4411 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4414 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4415 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4420 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4422 for (int i
= 0; i
< 4; i
++) {
4423 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4425 if (range
->length
== 0)
4428 /* Range block is a binding table index, map back to UBO index. */
4429 unsigned block_index
= iris_bti_to_group_index(
4430 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
4431 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
4433 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4434 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4437 iris_use_pinned_bo(batch
, res
->bo
, false);
4439 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4443 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4444 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4445 /* Re-pin any buffers referred to by the binding table. */
4446 iris_populate_binding_table(ice
, batch
, stage
, true);
4450 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4451 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4452 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4454 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4457 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4458 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
4459 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4462 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4463 iris_use_pinned_bo(batch
, bo
, false);
4465 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4467 if (prog_data
->total_scratch
> 0) {
4468 struct iris_bo
*bo
=
4469 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4470 iris_use_pinned_bo(batch
, bo
, true);
4476 if ((clean
& IRIS_DIRTY_DEPTH_BUFFER
) &&
4477 (clean
& IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
4478 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4479 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
4482 iris_use_optional_res(batch
, ice
->state
.last_res
.index_buffer
, false);
4484 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4485 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4487 const int i
= u_bit_scan64(&bound
);
4488 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
4489 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4495 iris_restore_compute_saved_bos(struct iris_context
*ice
,
4496 struct iris_batch
*batch
,
4497 const struct pipe_grid_info
*grid
)
4499 const uint64_t clean
= ~ice
->state
.dirty
;
4501 const int stage
= MESA_SHADER_COMPUTE
;
4502 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4504 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
4505 /* Re-pin any buffers referred to by the binding table. */
4506 iris_populate_binding_table(ice
, batch
, stage
, true);
4509 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
4511 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
4513 if ((clean
& IRIS_DIRTY_SAMPLER_STATES_CS
) &&
4514 (clean
& IRIS_DIRTY_BINDINGS_CS
) &&
4515 (clean
& IRIS_DIRTY_CONSTANTS_CS
) &&
4516 (clean
& IRIS_DIRTY_CS
)) {
4517 iris_use_optional_res(batch
, ice
->state
.last_res
.cs_desc
, false);
4520 if (clean
& IRIS_DIRTY_CS
) {
4521 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4524 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4525 iris_use_pinned_bo(batch
, bo
, false);
4527 struct iris_bo
*curbe_bo
=
4528 iris_resource_bo(ice
->state
.last_res
.cs_thread_ids
);
4529 iris_use_pinned_bo(batch
, curbe_bo
, false);
4531 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4533 if (prog_data
->total_scratch
> 0) {
4534 struct iris_bo
*bo
=
4535 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4536 iris_use_pinned_bo(batch
, bo
, true);
4543 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
4546 iris_update_surface_base_address(struct iris_batch
*batch
,
4547 struct iris_binder
*binder
)
4549 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
4552 flush_for_state_base_change(batch
);
4554 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
4555 sba
.SurfaceStateMOCS
= MOCS_WB
;
4556 sba
.SurfaceStateBaseAddressModifyEnable
= true;
4557 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
4560 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
4564 iris_viewport_zmin_zmax(const struct pipe_viewport_state
*vp
, bool halfz
,
4565 bool window_space_position
, float *zmin
, float *zmax
)
4567 if (window_space_position
) {
4572 util_viewport_zmin_zmax(vp
, halfz
, zmin
, zmax
);
4576 iris_upload_dirty_render_state(struct iris_context
*ice
,
4577 struct iris_batch
*batch
,
4578 const struct pipe_draw_info
*draw
)
4580 const uint64_t dirty
= ice
->state
.dirty
;
4582 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
4585 struct iris_genx_state
*genx
= ice
->state
.genx
;
4586 struct iris_binder
*binder
= &ice
->state
.binder
;
4587 struct brw_wm_prog_data
*wm_prog_data
= (void *)
4588 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
4590 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
4591 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4592 uint32_t cc_vp_address
;
4594 /* XXX: could avoid streaming for depth_clip [0,1] case. */
4595 uint32_t *cc_vp_map
=
4596 stream_state(batch
, ice
->state
.dynamic_uploader
,
4597 &ice
->state
.last_res
.cc_vp
,
4598 4 * ice
->state
.num_viewports
*
4599 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
4600 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4602 iris_viewport_zmin_zmax(&ice
->state
.viewports
[i
], cso_rast
->clip_halfz
,
4603 ice
->state
.window_space_position
,
4605 if (cso_rast
->depth_clip_near
)
4607 if (cso_rast
->depth_clip_far
)
4610 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
4611 ccv
.MinimumDepth
= zmin
;
4612 ccv
.MaximumDepth
= zmax
;
4615 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
4618 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
4619 ptr
.CCViewportPointer
= cc_vp_address
;
4623 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4624 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4625 uint32_t sf_cl_vp_address
;
4627 stream_state(batch
, ice
->state
.dynamic_uploader
,
4628 &ice
->state
.last_res
.sf_cl_vp
,
4629 4 * ice
->state
.num_viewports
*
4630 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
4632 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4633 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
4634 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
4636 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
4637 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
4638 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
4639 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
4641 gen_calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
4642 state
->scale
[0], state
->scale
[1],
4643 state
->translate
[0], state
->translate
[1],
4644 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
4646 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
4647 vp
.ViewportMatrixElementm00
= state
->scale
[0];
4648 vp
.ViewportMatrixElementm11
= state
->scale
[1];
4649 vp
.ViewportMatrixElementm22
= state
->scale
[2];
4650 vp
.ViewportMatrixElementm30
= state
->translate
[0];
4651 vp
.ViewportMatrixElementm31
= state
->translate
[1];
4652 vp
.ViewportMatrixElementm32
= state
->translate
[2];
4653 vp
.XMinClipGuardband
= gb_xmin
;
4654 vp
.XMaxClipGuardband
= gb_xmax
;
4655 vp
.YMinClipGuardband
= gb_ymin
;
4656 vp
.YMaxClipGuardband
= gb_ymax
;
4657 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
4658 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
4659 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
4660 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
4663 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
4666 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
4667 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
4671 if (dirty
& IRIS_DIRTY_URB
) {
4674 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
4675 if (!ice
->shaders
.prog
[i
]) {
4678 struct brw_vue_prog_data
*vue_prog_data
=
4679 (void *) ice
->shaders
.prog
[i
]->prog_data
;
4680 size
[i
] = vue_prog_data
->urb_entry_size
;
4682 assert(size
[i
] != 0);
4685 genX(emit_urb_setup
)(ice
, batch
, size
,
4686 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
4687 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
);
4690 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
4691 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4692 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4693 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4694 const int header_dwords
= GENX(BLEND_STATE_length
);
4696 /* Always write at least one BLEND_STATE - the final RT message will
4697 * reference BLEND_STATE[0] even if there aren't color writes. There
4698 * may still be alpha testing, computed depth, and so on.
4700 const int rt_dwords
=
4701 MAX2(cso_fb
->nr_cbufs
, 1) * GENX(BLEND_STATE_ENTRY_length
);
4703 uint32_t blend_offset
;
4704 uint32_t *blend_map
=
4705 stream_state(batch
, ice
->state
.dynamic_uploader
,
4706 &ice
->state
.last_res
.blend
,
4707 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4709 uint32_t blend_state_header
;
4710 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4711 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4712 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4715 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4716 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4718 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4719 ptr
.BlendStatePointer
= blend_offset
;
4720 ptr
.BlendStatePointerValid
= true;
4724 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4725 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4727 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4731 stream_state(batch
, ice
->state
.dynamic_uploader
,
4732 &ice
->state
.last_res
.color_calc
,
4733 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4735 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4736 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4737 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4738 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4739 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4740 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4741 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4743 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4744 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4747 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4748 ptr
.ColorCalcStatePointer
= cc_offset
;
4749 ptr
.ColorCalcStatePointerValid
= true;
4753 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4754 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4757 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4758 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4763 if (shs
->sysvals_need_upload
)
4764 upload_sysvals(ice
, stage
);
4766 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4768 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4769 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4771 /* The Skylake PRM contains the following restriction:
4773 * "The driver must ensure The following case does not occur
4774 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4775 * buffer 3 read length equal to zero committed followed by a
4776 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4779 * To avoid this, we program the buffers in the highest slots.
4780 * This way, slot 0 is only used if slot 3 is also used.
4784 for (int i
= 3; i
>= 0; i
--) {
4785 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4787 if (range
->length
== 0)
4790 /* Range block is a binding table index, map back to UBO index. */
4791 unsigned block_index
= iris_bti_to_group_index(
4792 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
4793 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
4795 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4796 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4798 assert(cbuf
->buffer_offset
% 32 == 0);
4800 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4801 pkt
.ConstantBody
.Buffer
[n
] =
4802 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->buffer_offset
)
4803 : ro_bo(batch
->screen
->workaround_bo
, 0);
4810 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4811 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4812 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4813 ptr
._3DCommandSubOpcode
= 38 + stage
;
4814 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4819 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4820 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4821 iris_populate_binding_table(ice
, batch
, stage
, false);
4825 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4826 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4827 !ice
->shaders
.prog
[stage
])
4830 iris_upload_sampler_states(ice
, stage
);
4832 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4833 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4835 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4837 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4838 ptr
._3DCommandSubOpcode
= 43 + stage
;
4839 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4843 if (ice
->state
.need_border_colors
)
4844 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4846 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4847 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4849 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4850 if (ice
->state
.framebuffer
.samples
> 0)
4851 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4855 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4856 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4857 ms
.SampleMask
= ice
->state
.sample_mask
;
4861 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4862 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4865 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4868 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4869 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4870 iris_use_pinned_bo(batch
, cache
->bo
, false);
4872 if (prog_data
->total_scratch
> 0) {
4873 struct iris_bo
*bo
=
4874 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4875 iris_use_pinned_bo(batch
, bo
, true);
4878 if (stage
== MESA_SHADER_FRAGMENT
) {
4879 UNUSED
struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4880 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4882 uint32_t ps_state
[GENX(3DSTATE_PS_length
)] = {0};
4883 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
4884 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
4885 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
4886 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
4888 /* The docs for 3DSTATE_PS::32 Pixel Dispatch Enable say:
4890 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16,
4891 * SIMD32 Dispatch must not be enabled for PER_PIXEL dispatch
4894 * 16x MSAA only exists on Gen9+, so we can skip this on Gen8.
4896 if (GEN_GEN
>= 9 && cso_fb
->samples
== 16 &&
4897 !wm_prog_data
->persample_dispatch
) {
4898 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
4899 ps
._32PixelDispatchEnable
= false;
4902 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
4903 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
4904 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
4905 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
4906 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
4907 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
4909 ps
.KernelStartPointer0
= KSP(shader
) +
4910 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
4911 ps
.KernelStartPointer1
= KSP(shader
) +
4912 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
4913 ps
.KernelStartPointer2
= KSP(shader
) +
4914 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
4917 uint32_t psx_state
[GENX(3DSTATE_PS_EXTRA_length
)] = {0};
4918 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
4920 if (!wm_prog_data
->uses_sample_mask
)
4921 psx
.InputCoverageMaskState
= ICMS_NONE
;
4922 else if (wm_prog_data
->post_depth_coverage
)
4923 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4924 else if (wm_prog_data
->inner_coverage
&&
4925 cso
->conservative_rasterization
)
4926 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4928 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4930 psx
.PixelShaderUsesInputCoverageMask
=
4931 wm_prog_data
->uses_sample_mask
;
4935 uint32_t *shader_ps
= (uint32_t *) shader
->derived_data
;
4936 uint32_t *shader_psx
= shader_ps
+ GENX(3DSTATE_PS_length
);
4937 iris_emit_merge(batch
, shader_ps
, ps_state
,
4938 GENX(3DSTATE_PS_length
));
4939 iris_emit_merge(batch
, shader_psx
, psx_state
,
4940 GENX(3DSTATE_PS_EXTRA_length
));
4942 iris_batch_emit(batch
, shader
->derived_data
,
4943 iris_derived_program_state_size(stage
));
4946 if (stage
== MESA_SHADER_TESS_EVAL
) {
4947 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4948 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4949 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4950 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4951 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4956 if (ice
->state
.streamout_active
) {
4957 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4958 iris_batch_emit(batch
, genx
->so_buffers
,
4959 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4960 for (int i
= 0; i
< 4; i
++) {
4961 struct iris_stream_output_target
*tgt
=
4962 (void *) ice
->state
.so_target
[i
];
4965 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4967 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4973 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
4974 uint32_t *decl_list
=
4975 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
4976 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
4979 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4980 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4982 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
4983 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
4984 sol
.SOFunctionEnable
= true;
4985 sol
.SOStatisticsEnable
= true;
4987 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
4988 !ice
->state
.prims_generated_query_active
;
4989 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
4992 assert(ice
->state
.streamout
);
4994 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
4995 GENX(3DSTATE_STREAMOUT_length
));
4998 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4999 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
5003 if (dirty
& IRIS_DIRTY_CLIP
) {
5004 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5005 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5007 bool gs_or_tes
= ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] ||
5008 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
5009 bool points_or_lines
= cso_rast
->fill_mode_point_or_line
||
5010 (gs_or_tes
? ice
->shaders
.output_topology_is_points_or_lines
5011 : ice
->state
.prim_is_points_or_lines
);
5013 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
5014 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
5015 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5016 if (cso_rast
->rasterizer_discard
)
5017 cl
.ClipMode
= CLIPMODE_REJECT_ALL
;
5018 else if (ice
->state
.window_space_position
)
5019 cl
.ClipMode
= CLIPMODE_ACCEPT_ALL
;
5021 cl
.ClipMode
= CLIPMODE_NORMAL
;
5023 cl
.PerspectiveDivideDisable
= ice
->state
.window_space_position
;
5024 cl
.ViewportXYClipTestEnable
= !points_or_lines
;
5026 if (wm_prog_data
->barycentric_interp_modes
&
5027 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
5028 cl
.NonPerspectiveBarycentricEnable
= true;
5030 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
5031 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
5033 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
5034 ARRAY_SIZE(cso_rast
->clip
));
5037 if (dirty
& IRIS_DIRTY_RASTER
) {
5038 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5039 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
5041 uint32_t dynamic_sf
[GENX(3DSTATE_SF_length
)];
5042 iris_pack_command(GENX(3DSTATE_SF
), &dynamic_sf
, sf
) {
5043 sf
.ViewportTransformEnable
= !ice
->state
.window_space_position
;
5045 iris_emit_merge(batch
, cso
->sf
, dynamic_sf
,
5046 ARRAY_SIZE(dynamic_sf
));
5049 if (dirty
& IRIS_DIRTY_WM
) {
5050 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5051 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
5053 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
5054 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5056 wm
.BarycentricInterpolationMode
=
5057 wm_prog_data
->barycentric_interp_modes
;
5059 if (wm_prog_data
->early_fragment_tests
)
5060 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
5061 else if (wm_prog_data
->has_side_effects
)
5062 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
5064 /* We could skip this bit if color writes are enabled. */
5065 if (wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
)
5066 wm
.ForceThreadDispatchEnable
= ForceON
;
5068 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
5071 if (dirty
& IRIS_DIRTY_SBE
) {
5072 iris_emit_sbe(batch
, ice
);
5075 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
5076 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
5077 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
5078 const struct shader_info
*fs_info
=
5079 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
5081 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
5082 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
5083 pb
.HasWriteableRT
= has_writeable_rt(cso_blend
, fs_info
);
5084 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
5086 /* The dual source blending docs caution against using SRC1 factors
5087 * when the shader doesn't use a dual source render target write.
5088 * Empirically, this can lead to GPU hangs, and the results are
5089 * undefined anyway, so simply disable blending to avoid the hang.
5091 pb
.ColorBufferBlendEnable
= (cso_blend
->blend_enables
& 1) &&
5092 (!cso_blend
->dual_color_blending
|| wm_prog_data
->dual_src_blend
);
5095 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
5096 ARRAY_SIZE(cso_blend
->ps_blend
));
5099 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
5100 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
5102 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
5103 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
5104 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
5105 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
5106 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
5108 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
5110 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
5114 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
5115 uint32_t scissor_offset
=
5116 emit_state(batch
, ice
->state
.dynamic_uploader
,
5117 &ice
->state
.last_res
.scissor
,
5118 ice
->state
.scissors
,
5119 sizeof(struct pipe_scissor_state
) *
5120 ice
->state
.num_viewports
, 32);
5122 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
5123 ptr
.ScissorRectPointer
= scissor_offset
;
5127 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
5128 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
5130 /* Do not emit the clear params yets. We need to update the clear value
5133 uint32_t clear_length
= GENX(3DSTATE_CLEAR_PARAMS_length
) * 4;
5134 uint32_t cso_z_size
= sizeof(cso_z
->packets
) - clear_length
;
5135 iris_batch_emit(batch
, cso_z
->packets
, cso_z_size
);
5137 union isl_color_value clear_value
= { .f32
= { 0, } };
5139 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5140 if (cso_fb
->zsbuf
) {
5141 struct iris_resource
*zres
, *sres
;
5142 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
5144 if (zres
&& zres
->aux
.bo
)
5145 clear_value
= iris_resource_get_clear_color(zres
, NULL
, NULL
);
5148 uint32_t clear_params
[GENX(3DSTATE_CLEAR_PARAMS_length
)];
5149 iris_pack_command(GENX(3DSTATE_CLEAR_PARAMS
), clear_params
, clear
) {
5150 clear
.DepthClearValueValid
= true;
5151 clear
.DepthClearValue
= clear_value
.f32
[0];
5153 iris_batch_emit(batch
, clear_params
, clear_length
);
5156 if (dirty
& (IRIS_DIRTY_DEPTH_BUFFER
| IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
5157 /* Listen for buffer changes, and also write enable changes. */
5158 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5159 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
5162 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
5163 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
5164 for (int i
= 0; i
< 32; i
++) {
5165 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
5170 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
5171 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5172 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
5175 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
5176 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
5177 topo
.PrimitiveTopologyType
=
5178 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
5182 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
5183 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
5184 int dynamic_bound
= ice
->state
.bound_vertex_buffers
;
5186 if (ice
->state
.vs_uses_draw_params
) {
5187 if (ice
->draw
.draw_params_offset
== 0) {
5188 u_upload_data(ice
->ctx
.stream_uploader
, 0, sizeof(ice
->draw
.params
),
5189 4, &ice
->draw
.params
, &ice
->draw
.draw_params_offset
,
5190 &ice
->draw
.draw_params_res
);
5192 assert(ice
->draw
.draw_params_res
);
5194 struct iris_vertex_buffer_state
*state
=
5195 &(ice
->state
.genx
->vertex_buffers
[count
]);
5196 pipe_resource_reference(&state
->resource
, ice
->draw
.draw_params_res
);
5197 struct iris_resource
*res
= (void *) state
->resource
;
5199 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
5200 vb
.VertexBufferIndex
= count
;
5201 vb
.AddressModifyEnable
= true;
5203 vb
.BufferSize
= res
->bo
->size
- ice
->draw
.draw_params_offset
;
5204 vb
.BufferStartingAddress
=
5205 ro_bo(NULL
, res
->bo
->gtt_offset
+
5206 (int) ice
->draw
.draw_params_offset
);
5207 vb
.MOCS
= mocs(res
->bo
);
5209 dynamic_bound
|= 1ull << count
;
5213 if (ice
->state
.vs_uses_derived_draw_params
) {
5214 u_upload_data(ice
->ctx
.stream_uploader
, 0,
5215 sizeof(ice
->draw
.derived_params
), 4,
5216 &ice
->draw
.derived_params
,
5217 &ice
->draw
.derived_draw_params_offset
,
5218 &ice
->draw
.derived_draw_params_res
);
5220 struct iris_vertex_buffer_state
*state
=
5221 &(ice
->state
.genx
->vertex_buffers
[count
]);
5222 pipe_resource_reference(&state
->resource
,
5223 ice
->draw
.derived_draw_params_res
);
5224 struct iris_resource
*res
= (void *) ice
->draw
.derived_draw_params_res
;
5226 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
5227 vb
.VertexBufferIndex
= count
;
5228 vb
.AddressModifyEnable
= true;
5231 res
->bo
->size
- ice
->draw
.derived_draw_params_offset
;
5232 vb
.BufferStartingAddress
=
5233 ro_bo(NULL
, res
->bo
->gtt_offset
+
5234 (int) ice
->draw
.derived_draw_params_offset
);
5235 vb
.MOCS
= mocs(res
->bo
);
5237 dynamic_bound
|= 1ull << count
;
5242 /* The VF cache designers cut corners, and made the cache key's
5243 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
5244 * 32 bits of the address. If you have two vertex buffers which get
5245 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
5246 * you can get collisions (even within a single batch).
5248 * So, we need to do a VF cache invalidate if the buffer for a VB
5249 * slot slot changes [48:32] address bits from the previous time.
5251 unsigned flush_flags
= 0;
5253 uint64_t bound
= dynamic_bound
;
5255 const int i
= u_bit_scan64(&bound
);
5256 uint16_t high_bits
= 0;
5258 struct iris_resource
*res
=
5259 (void *) genx
->vertex_buffers
[i
].resource
;
5261 iris_use_pinned_bo(batch
, res
->bo
, false);
5263 high_bits
= res
->bo
->gtt_offset
>> 32ull;
5264 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
5265 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5266 PIPE_CONTROL_CS_STALL
;
5267 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
5273 iris_emit_pipe_control_flush(batch
,
5274 "workaround: VF cache 32-bit key [VB]",
5278 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
5281 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
5282 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
5283 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
5287 bound
= dynamic_bound
;
5289 const int i
= u_bit_scan64(&bound
);
5290 memcpy(map
, genx
->vertex_buffers
[i
].state
,
5291 sizeof(uint32_t) * vb_dwords
);
5297 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
5298 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5299 const unsigned entries
= MAX2(cso
->count
, 1);
5300 if (!(ice
->state
.vs_needs_sgvs_element
||
5301 ice
->state
.vs_uses_derived_draw_params
||
5302 ice
->state
.vs_needs_edge_flag
)) {
5303 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
5304 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
5306 uint32_t dynamic_ves
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
5307 const unsigned dyn_count
= cso
->count
+
5308 ice
->state
.vs_needs_sgvs_element
+
5309 ice
->state
.vs_uses_derived_draw_params
;
5311 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
),
5314 1 + GENX(VERTEX_ELEMENT_STATE_length
) * dyn_count
- 2;
5316 memcpy(&dynamic_ves
[1], &cso
->vertex_elements
[1],
5317 (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5318 GENX(VERTEX_ELEMENT_STATE_length
) * sizeof(uint32_t));
5319 uint32_t *ve_pack_dest
=
5320 &dynamic_ves
[1 + (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5321 GENX(VERTEX_ELEMENT_STATE_length
)];
5323 if (ice
->state
.vs_needs_sgvs_element
) {
5324 uint32_t base_ctrl
= ice
->state
.vs_uses_draw_params
?
5325 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
5326 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5328 ve
.VertexBufferIndex
=
5329 util_bitcount64(ice
->state
.bound_vertex_buffers
);
5330 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5331 ve
.Component0Control
= base_ctrl
;
5332 ve
.Component1Control
= base_ctrl
;
5333 ve
.Component2Control
= VFCOMP_STORE_0
;
5334 ve
.Component3Control
= VFCOMP_STORE_0
;
5336 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5338 if (ice
->state
.vs_uses_derived_draw_params
) {
5339 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5341 ve
.VertexBufferIndex
=
5342 util_bitcount64(ice
->state
.bound_vertex_buffers
) +
5343 ice
->state
.vs_uses_draw_params
;
5344 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5345 ve
.Component0Control
= VFCOMP_STORE_SRC
;
5346 ve
.Component1Control
= VFCOMP_STORE_SRC
;
5347 ve
.Component2Control
= VFCOMP_STORE_0
;
5348 ve
.Component3Control
= VFCOMP_STORE_0
;
5350 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5352 if (ice
->state
.vs_needs_edge_flag
) {
5353 for (int i
= 0; i
< GENX(VERTEX_ELEMENT_STATE_length
); i
++)
5354 ve_pack_dest
[i
] = cso
->edgeflag_ve
[i
];
5357 iris_batch_emit(batch
, &dynamic_ves
, sizeof(uint32_t) *
5358 (1 + dyn_count
* GENX(VERTEX_ELEMENT_STATE_length
)));
5361 if (!ice
->state
.vs_needs_edge_flag
) {
5362 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
5363 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5365 assert(cso
->count
> 0);
5366 const unsigned edgeflag_index
= cso
->count
- 1;
5367 uint32_t dynamic_vfi
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
5368 memcpy(&dynamic_vfi
[0], cso
->vf_instancing
, edgeflag_index
*
5369 GENX(3DSTATE_VF_INSTANCING_length
) * sizeof(uint32_t));
5371 uint32_t *vfi_pack_dest
= &dynamic_vfi
[0] +
5372 edgeflag_index
* GENX(3DSTATE_VF_INSTANCING_length
);
5373 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
5374 vi
.VertexElementIndex
= edgeflag_index
+
5375 ice
->state
.vs_needs_sgvs_element
+
5376 ice
->state
.vs_uses_derived_draw_params
;
5378 for (int i
= 0; i
< GENX(3DSTATE_VF_INSTANCING_length
); i
++)
5379 vfi_pack_dest
[i
] |= cso
->edgeflag_vfi
[i
];
5381 iris_batch_emit(batch
, &dynamic_vfi
[0], sizeof(uint32_t) *
5382 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5386 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
5387 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
5388 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
5389 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5391 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
5392 if (vs_prog_data
->uses_vertexid
) {
5393 sgv
.VertexIDEnable
= true;
5394 sgv
.VertexIDComponentNumber
= 2;
5395 sgv
.VertexIDElementOffset
=
5396 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5399 if (vs_prog_data
->uses_instanceid
) {
5400 sgv
.InstanceIDEnable
= true;
5401 sgv
.InstanceIDComponentNumber
= 3;
5402 sgv
.InstanceIDElementOffset
=
5403 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5408 if (dirty
& IRIS_DIRTY_VF
) {
5409 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
5410 if (draw
->primitive_restart
) {
5411 vf
.IndexedDrawCutIndexEnable
= true;
5412 vf
.CutIndex
= draw
->restart_index
;
5417 if (dirty
& IRIS_DIRTY_VF_STATISTICS
) {
5418 iris_emit_cmd(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
5419 vf
.StatisticsEnable
= true;
5423 if (ice
->state
.current_hash_scale
!= 1)
5424 genX(emit_hashing_mode
)(ice
, batch
, UINT_MAX
, UINT_MAX
, 1);
5426 /* TODO: Gen8 PMA fix */
5430 iris_upload_render_state(struct iris_context
*ice
,
5431 struct iris_batch
*batch
,
5432 const struct pipe_draw_info
*draw
)
5434 bool use_predicate
= ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
5436 /* Always pin the binder. If we're emitting new binding table pointers,
5437 * we need it. If not, we're probably inheriting old tables via the
5438 * context, and need it anyway. Since true zero-bindings cases are
5439 * practically non-existent, just pin it and avoid last_res tracking.
5441 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5443 if (!batch
->contains_draw
) {
5444 iris_restore_render_saved_bos(ice
, batch
, draw
);
5445 batch
->contains_draw
= true;
5448 iris_upload_dirty_render_state(ice
, batch
, draw
);
5450 if (draw
->index_size
> 0) {
5453 if (draw
->has_user_indices
) {
5454 u_upload_data(ice
->ctx
.stream_uploader
, 0,
5455 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
5456 &offset
, &ice
->state
.last_res
.index_buffer
);
5458 struct iris_resource
*res
= (void *) draw
->index
.resource
;
5459 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
5461 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
5462 draw
->index
.resource
);
5466 struct iris_genx_state
*genx
= ice
->state
.genx
;
5467 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
5469 uint32_t ib_packet
[GENX(3DSTATE_INDEX_BUFFER_length
)];
5470 iris_pack_command(GENX(3DSTATE_INDEX_BUFFER
), ib_packet
, ib
) {
5471 ib
.IndexFormat
= draw
->index_size
>> 1;
5473 ib
.BufferSize
= bo
->size
- offset
;
5474 ib
.BufferStartingAddress
= ro_bo(NULL
, bo
->gtt_offset
+ offset
);
5477 if (memcmp(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
)) != 0) {
5478 memcpy(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
));
5479 iris_batch_emit(batch
, ib_packet
, sizeof(ib_packet
));
5480 iris_use_pinned_bo(batch
, bo
, false);
5483 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
5484 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
5485 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
5486 iris_emit_pipe_control_flush(batch
,
5487 "workaround: VF cache 32-bit key [IB]",
5488 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5489 PIPE_CONTROL_CS_STALL
);
5490 ice
->state
.last_index_bo_high_bits
= high_bits
;
5494 #define _3DPRIM_END_OFFSET 0x2420
5495 #define _3DPRIM_START_VERTEX 0x2430
5496 #define _3DPRIM_VERTEX_COUNT 0x2434
5497 #define _3DPRIM_INSTANCE_COUNT 0x2438
5498 #define _3DPRIM_START_INSTANCE 0x243C
5499 #define _3DPRIM_BASE_VERTEX 0x2440
5501 if (draw
->indirect
) {
5502 if (draw
->indirect
->indirect_draw_count
) {
5503 use_predicate
= true;
5505 struct iris_bo
*draw_count_bo
=
5506 iris_resource_bo(draw
->indirect
->indirect_draw_count
);
5507 unsigned draw_count_offset
=
5508 draw
->indirect
->indirect_draw_count_offset
;
5510 iris_emit_pipe_control_flush(batch
,
5511 "ensure indirect draw buffer is flushed",
5512 PIPE_CONTROL_FLUSH_ENABLE
);
5514 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
) {
5515 struct gen_mi_builder b
;
5516 gen_mi_builder_init(&b
, batch
);
5518 /* comparison = draw id < draw count */
5519 struct gen_mi_value comparison
=
5520 gen_mi_ult(&b
, gen_mi_imm(draw
->drawid
),
5521 gen_mi_mem32(ro_bo(draw_count_bo
,
5522 draw_count_offset
)));
5524 /* predicate = comparison & conditional rendering predicate */
5525 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_RESULT
),
5526 gen_mi_iand(&b
, comparison
,
5527 gen_mi_reg32(CS_GPR(15))));
5529 uint32_t mi_predicate
;
5531 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
5532 ice
->vtbl
.load_register_imm64(batch
, MI_PREDICATE_SRC1
,
5534 /* Upload the current draw count from the draw parameters buffer
5535 * to MI_PREDICATE_SRC0.
5537 ice
->vtbl
.load_register_mem32(batch
, MI_PREDICATE_SRC0
,
5538 draw_count_bo
, draw_count_offset
);
5539 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
5540 ice
->vtbl
.load_register_imm32(batch
, MI_PREDICATE_SRC0
+ 4, 0);
5542 if (draw
->drawid
== 0) {
5543 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
5544 MI_PREDICATE_COMBINEOP_SET
|
5545 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
5547 /* While draw_index < draw_count the predicate's result will be
5548 * (draw_index == draw_count) ^ TRUE = TRUE
5549 * When draw_index == draw_count the result is
5550 * (TRUE) ^ TRUE = FALSE
5551 * After this all results will be:
5552 * (FALSE) ^ FALSE = FALSE
5554 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOAD
|
5555 MI_PREDICATE_COMBINEOP_XOR
|
5556 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
5558 iris_batch_emit(batch
, &mi_predicate
, sizeof(uint32_t));
5561 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
5564 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5565 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
5566 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
5568 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5569 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
5570 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
5572 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5573 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
5574 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
5576 if (draw
->index_size
) {
5577 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5578 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
5579 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5581 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5582 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5583 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
5586 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5587 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5588 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5590 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
5591 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
5595 } else if (draw
->count_from_stream_output
) {
5596 struct iris_stream_output_target
*so
=
5597 (void *) draw
->count_from_stream_output
;
5599 /* XXX: Replace with actual cache tracking */
5600 iris_emit_pipe_control_flush(batch
,
5601 "draw count from stream output stall",
5602 PIPE_CONTROL_CS_STALL
);
5604 struct gen_mi_builder b
;
5605 gen_mi_builder_init(&b
, batch
);
5607 struct iris_address addr
=
5608 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
5609 struct gen_mi_value offset
=
5610 gen_mi_iadd_imm(&b
, gen_mi_mem32(addr
), -so
->base
.buffer_offset
);
5612 gen_mi_store(&b
, gen_mi_reg32(_3DPRIM_VERTEX_COUNT
),
5613 gen_mi_udiv32_imm(&b
, offset
, so
->stride
));
5615 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
5616 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
5617 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
5618 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
5621 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
5622 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
5623 prim
.PredicateEnable
= use_predicate
;
5625 if (draw
->indirect
|| draw
->count_from_stream_output
) {
5626 prim
.IndirectParameterEnable
= true;
5628 prim
.StartInstanceLocation
= draw
->start_instance
;
5629 prim
.InstanceCount
= draw
->instance_count
;
5630 prim
.VertexCountPerInstance
= draw
->count
;
5632 prim
.StartVertexLocation
= draw
->start
;
5634 if (draw
->index_size
) {
5635 prim
.BaseVertexLocation
+= draw
->index_bias
;
5637 prim
.StartVertexLocation
+= draw
->index_bias
;
5644 iris_upload_compute_state(struct iris_context
*ice
,
5645 struct iris_batch
*batch
,
5646 const struct pipe_grid_info
*grid
)
5648 const uint64_t dirty
= ice
->state
.dirty
;
5649 struct iris_screen
*screen
= batch
->screen
;
5650 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
5651 struct iris_binder
*binder
= &ice
->state
.binder
;
5652 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
5653 struct iris_compiled_shader
*shader
=
5654 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
5655 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5656 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
5658 /* Always pin the binder. If we're emitting new binding table pointers,
5659 * we need it. If not, we're probably inheriting old tables via the
5660 * context, and need it anyway. Since true zero-bindings cases are
5661 * practically non-existent, just pin it and avoid last_res tracking.
5663 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5665 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->sysvals_need_upload
)
5666 upload_sysvals(ice
, MESA_SHADER_COMPUTE
);
5668 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
5669 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
5671 if (dirty
& IRIS_DIRTY_SAMPLER_STATES_CS
)
5672 iris_upload_sampler_states(ice
, MESA_SHADER_COMPUTE
);
5674 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
5675 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
5677 if (ice
->state
.need_border_colors
)
5678 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
5680 if (dirty
& IRIS_DIRTY_CS
) {
5681 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
5683 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
5684 * the only bits that are changed are scoreboard related: Scoreboard
5685 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
5686 * these scoreboard related states, a MEDIA_STATE_FLUSH is
5689 iris_emit_pipe_control_flush(batch
,
5690 "workaround: stall before MEDIA_VFE_STATE",
5691 PIPE_CONTROL_CS_STALL
);
5693 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
5694 if (prog_data
->total_scratch
) {
5695 struct iris_bo
*bo
=
5696 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
5697 MESA_SHADER_COMPUTE
);
5698 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
5699 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
5702 vfe
.MaximumNumberofThreads
=
5703 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
5705 vfe
.ResetGatewayTimer
=
5706 Resettingrelativetimerandlatchingtheglobaltimestamp
;
5709 vfe
.BypassGatewayControl
= true;
5711 vfe
.NumberofURBEntries
= 2;
5712 vfe
.URBEntryAllocationSize
= 2;
5714 vfe
.CURBEAllocationSize
=
5715 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
5716 cs_prog_data
->push
.cross_thread
.regs
, 2);
5720 /* TODO: Combine subgroup-id with cbuf0 so we can push regular uniforms */
5721 if (dirty
& IRIS_DIRTY_CS
) {
5722 uint32_t curbe_data_offset
= 0;
5723 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
5724 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
5725 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
5726 uint32_t *curbe_data_map
=
5727 stream_state(batch
, ice
->state
.dynamic_uploader
,
5728 &ice
->state
.last_res
.cs_thread_ids
,
5729 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
5730 &curbe_data_offset
);
5731 assert(curbe_data_map
);
5732 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
5733 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
5735 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
5736 curbe
.CURBETotalDataLength
=
5737 ALIGN(cs_prog_data
->push
.total
.size
, 64);
5738 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
5742 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
5743 IRIS_DIRTY_BINDINGS_CS
|
5744 IRIS_DIRTY_CONSTANTS_CS
|
5746 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
5748 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
5749 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
5750 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
5753 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
5754 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
5756 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
5757 load
.InterfaceDescriptorTotalLength
=
5758 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
5759 load
.InterfaceDescriptorDataStartAddress
=
5760 emit_state(batch
, ice
->state
.dynamic_uploader
,
5761 &ice
->state
.last_res
.cs_desc
, desc
, sizeof(desc
), 64);
5765 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
5766 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
5767 uint32_t right_mask
;
5770 right_mask
= ~0u >> (32 - remainder
);
5772 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
5774 #define GPGPU_DISPATCHDIMX 0x2500
5775 #define GPGPU_DISPATCHDIMY 0x2504
5776 #define GPGPU_DISPATCHDIMZ 0x2508
5778 if (grid
->indirect
) {
5779 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
5780 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
5781 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5782 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
5783 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
5785 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5786 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
5787 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
5789 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5790 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
5791 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
5795 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
5796 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
5797 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
5798 ggw
.ThreadDepthCounterMaximum
= 0;
5799 ggw
.ThreadHeightCounterMaximum
= 0;
5800 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
5801 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
5802 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
5803 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
5804 ggw
.RightExecutionMask
= right_mask
;
5805 ggw
.BottomExecutionMask
= 0xffffffff;
5808 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
5810 if (!batch
->contains_draw
) {
5811 iris_restore_compute_saved_bos(ice
, batch
, grid
);
5812 batch
->contains_draw
= true;
5817 * State module teardown.
5820 iris_destroy_state(struct iris_context
*ice
)
5822 struct iris_genx_state
*genx
= ice
->state
.genx
;
5824 pipe_resource_reference(&ice
->draw
.draw_params_res
, NULL
);
5825 pipe_resource_reference(&ice
->draw
.derived_draw_params_res
, NULL
);
5827 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5829 const int i
= u_bit_scan64(&bound_vbs
);
5830 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
5832 free(ice
->state
.genx
);
5834 for (int i
= 0; i
< 4; i
++) {
5835 pipe_so_target_reference(&ice
->state
.so_target
[i
], NULL
);
5838 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
5839 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
5841 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
5843 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
5844 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5845 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
5846 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
5847 pipe_resource_reference(&shs
->constbuf
[i
].buffer
, NULL
);
5848 pipe_resource_reference(&shs
->constbuf_surf_state
[i
].res
, NULL
);
5850 for (int i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
5851 pipe_resource_reference(&shs
->image
[i
].base
.resource
, NULL
);
5852 pipe_resource_reference(&shs
->image
[i
].surface_state
.res
, NULL
);
5854 for (int i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
5855 pipe_resource_reference(&shs
->ssbo
[i
].buffer
, NULL
);
5856 pipe_resource_reference(&shs
->ssbo_surf_state
[i
].res
, NULL
);
5858 for (int i
= 0; i
< IRIS_MAX_TEXTURE_SAMPLERS
; i
++) {
5859 pipe_sampler_view_reference((struct pipe_sampler_view
**)
5860 &shs
->textures
[i
], NULL
);
5864 pipe_resource_reference(&ice
->state
.grid_size
.res
, NULL
);
5865 pipe_resource_reference(&ice
->state
.grid_surf_state
.res
, NULL
);
5867 pipe_resource_reference(&ice
->state
.null_fb
.res
, NULL
);
5868 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
5870 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
5871 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
5872 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
5873 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
5874 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
5875 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
5876 pipe_resource_reference(&ice
->state
.last_res
.cs_thread_ids
, NULL
);
5877 pipe_resource_reference(&ice
->state
.last_res
.cs_desc
, NULL
);
5880 /* ------------------------------------------------------------------- */
5883 iris_rebind_buffer(struct iris_context
*ice
,
5884 struct iris_resource
*res
,
5885 uint64_t old_address
)
5887 struct pipe_context
*ctx
= &ice
->ctx
;
5888 struct iris_screen
*screen
= (void *) ctx
->screen
;
5889 struct iris_genx_state
*genx
= ice
->state
.genx
;
5891 assert(res
->base
.target
== PIPE_BUFFER
);
5893 /* Buffers can't be framebuffer attachments, nor display related,
5894 * and we don't have upstream Clover support.
5896 assert(!(res
->bind_history
& (PIPE_BIND_DEPTH_STENCIL
|
5897 PIPE_BIND_RENDER_TARGET
|
5898 PIPE_BIND_BLENDABLE
|
5899 PIPE_BIND_DISPLAY_TARGET
|
5901 PIPE_BIND_COMPUTE_RESOURCE
|
5902 PIPE_BIND_GLOBAL
)));
5904 if (res
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
5905 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5907 const int i
= u_bit_scan64(&bound_vbs
);
5908 struct iris_vertex_buffer_state
*state
= &genx
->vertex_buffers
[i
];
5910 /* Update the CPU struct */
5911 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_start
) == 32);
5912 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) == 64);
5913 uint64_t *addr
= (uint64_t *) &state
->state
[1];
5915 if (*addr
== old_address
) {
5916 *addr
= res
->bo
->gtt_offset
;
5917 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
5922 /* We don't need to handle PIPE_BIND_INDEX_BUFFER here: we re-emit
5923 * the 3DSTATE_INDEX_BUFFER packet whenever the address changes.
5925 * There is also no need to handle these:
5926 * - PIPE_BIND_COMMAND_ARGS_BUFFER (emitted for every indirect draw)
5927 * - PIPE_BIND_QUERY_BUFFER (no persistent state references)
5930 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
5931 /* XXX: be careful about resetting vs appending... */
5935 for (int s
= MESA_SHADER_VERTEX
; s
< MESA_SHADER_STAGES
; s
++) {
5936 struct iris_shader_state
*shs
= &ice
->state
.shaders
[s
];
5937 enum pipe_shader_type p_stage
= stage_to_pipe(s
);
5939 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
5940 /* Skip constant buffer 0, it's for regular uniforms, not UBOs */
5941 uint32_t bound_cbufs
= shs
->bound_cbufs
& ~1u;
5942 while (bound_cbufs
) {
5943 const int i
= u_bit_scan(&bound_cbufs
);
5944 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[i
];
5945 struct iris_state_ref
*surf_state
= &shs
->constbuf_surf_state
[i
];
5947 if (res
->bo
== iris_resource_bo(cbuf
->buffer
)) {
5948 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
, surf_state
, false);
5949 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< s
;
5954 if (res
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
5955 uint32_t bound_ssbos
= shs
->bound_ssbos
;
5956 while (bound_ssbos
) {
5957 const int i
= u_bit_scan(&bound_ssbos
);
5958 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[i
];
5960 if (res
->bo
== iris_resource_bo(ssbo
->buffer
)) {
5961 struct pipe_shader_buffer buf
= {
5962 .buffer
= &res
->base
,
5963 .buffer_offset
= ssbo
->buffer_offset
,
5964 .buffer_size
= ssbo
->buffer_size
,
5966 iris_set_shader_buffers(ctx
, p_stage
, i
, 1, &buf
,
5967 (shs
->writable_ssbos
>> i
) & 1);
5972 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
5973 uint32_t bound_sampler_views
= shs
->bound_sampler_views
;
5974 while (bound_sampler_views
) {
5975 const int i
= u_bit_scan(&bound_sampler_views
);
5976 struct iris_sampler_view
*isv
= shs
->textures
[i
];
5978 if (res
->bo
== iris_resource_bo(isv
->base
.texture
)) {
5979 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
5980 &isv
->surface_state
,
5981 isv
->res
->aux
.sampler_usages
);
5983 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
5984 isv
->view
.format
, isv
->view
.swizzle
,
5985 isv
->base
.u
.buf
.offset
,
5986 isv
->base
.u
.buf
.size
);
5987 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< s
;
5992 if (res
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
5993 uint32_t bound_image_views
= shs
->bound_image_views
;
5994 while (bound_image_views
) {
5995 const int i
= u_bit_scan(&bound_image_views
);
5996 struct iris_image_view
*iv
= &shs
->image
[i
];
5998 if (res
->bo
== iris_resource_bo(iv
->base
.resource
)) {
5999 iris_set_shader_images(ctx
, p_stage
, i
, 1, &iv
->base
);
6006 /* ------------------------------------------------------------------- */
6009 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
6012 _iris_emit_lrr(batch
, dst
, src
);
6016 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
6019 _iris_emit_lrr(batch
, dst
, src
);
6020 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
6024 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
6027 _iris_emit_lri(batch
, reg
, val
);
6031 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
6034 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
6035 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
6039 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
6042 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
6043 struct iris_bo
*bo
, uint32_t offset
)
6045 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6046 lrm
.RegisterAddress
= reg
;
6047 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
6052 * Load a 64-bit value from a buffer into a MMIO register via
6053 * two MI_LOAD_REGISTER_MEM commands.
6056 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
6057 struct iris_bo
*bo
, uint32_t offset
)
6059 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
6060 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
6064 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
6065 struct iris_bo
*bo
, uint32_t offset
,
6068 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
6069 srm
.RegisterAddress
= reg
;
6070 srm
.MemoryAddress
= rw_bo(bo
, offset
);
6071 srm
.PredicateEnable
= predicated
;
6076 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
6077 struct iris_bo
*bo
, uint32_t offset
,
6080 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
6081 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
6085 iris_store_data_imm32(struct iris_batch
*batch
,
6086 struct iris_bo
*bo
, uint32_t offset
,
6089 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
6090 sdi
.Address
= rw_bo(bo
, offset
);
6091 sdi
.ImmediateData
= imm
;
6096 iris_store_data_imm64(struct iris_batch
*batch
,
6097 struct iris_bo
*bo
, uint32_t offset
,
6100 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
6101 * 2 in genxml but it's actually variable length and we need 5 DWords.
6103 void *map
= iris_get_command_space(batch
, 4 * 5);
6104 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
6105 sdi
.DWordLength
= 5 - 2;
6106 sdi
.Address
= rw_bo(bo
, offset
);
6107 sdi
.ImmediateData
= imm
;
6112 iris_copy_mem_mem(struct iris_batch
*batch
,
6113 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
6114 struct iris_bo
*src_bo
, uint32_t src_offset
,
6117 /* MI_COPY_MEM_MEM operates on DWords. */
6118 assert(bytes
% 4 == 0);
6119 assert(dst_offset
% 4 == 0);
6120 assert(src_offset
% 4 == 0);
6122 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
6123 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
6124 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
6125 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
6130 /* ------------------------------------------------------------------- */
6133 flags_to_post_sync_op(uint32_t flags
)
6135 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
6136 return WriteImmediateData
;
6138 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
6139 return WritePSDepthCount
;
6141 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
6142 return WriteTimestamp
;
6148 * Do the given flags have a Post Sync or LRI Post Sync operation?
6150 static enum pipe_control_flags
6151 get_post_sync_flags(enum pipe_control_flags flags
)
6153 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
6154 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6155 PIPE_CONTROL_WRITE_TIMESTAMP
|
6156 PIPE_CONTROL_LRI_POST_SYNC_OP
;
6158 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
6159 * "LRI Post Sync Operation". So more than one bit set would be illegal.
6161 assert(util_bitcount(flags
) <= 1);
6166 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
6169 * Emit a series of PIPE_CONTROL commands, taking into account any
6170 * workarounds necessary to actually accomplish the caller's request.
6172 * Unless otherwise noted, spec quotations in this function come from:
6174 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
6175 * Restrictions for PIPE_CONTROL.
6177 * You should not use this function directly. Use the helpers in
6178 * iris_pipe_control.c instead, which may split the pipe control further.
6181 iris_emit_raw_pipe_control(struct iris_batch
*batch
,
6188 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6189 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
6190 enum pipe_control_flags non_lri_post_sync_flags
=
6191 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
6193 /* Recursive PIPE_CONTROL workarounds --------------------------------
6194 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
6196 * We do these first because we want to look at the original operation,
6197 * rather than any workarounds we set.
6199 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
6200 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
6201 * lists several workarounds:
6203 * "Project: SKL, KBL, BXT
6205 * If the VF Cache Invalidation Enable is set to a 1 in a
6206 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
6207 * sets to 0, with the VF Cache Invalidation Enable set to 0
6208 * needs to be sent prior to the PIPE_CONTROL with VF Cache
6209 * Invalidation Enable set to a 1."
6211 iris_emit_raw_pipe_control(batch
,
6212 "workaround: recursive VF cache invalidate",
6216 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
6217 /* Project: SKL / Argument: LRI Post Sync Operation [23]
6219 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6220 * programmed prior to programming a PIPECONTROL command with "LRI
6221 * Post Sync Operation" in GPGPU mode of operation (i.e when
6222 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
6224 * The same text exists a few rows below for Post Sync Op.
6226 iris_emit_raw_pipe_control(batch
,
6227 "workaround: CS stall before gpgpu post-sync",
6228 PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
6231 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
6233 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
6234 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
6235 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
6237 iris_emit_raw_pipe_control(batch
,
6238 "workaround: PC flush before RT flush",
6239 PIPE_CONTROL_FLUSH_ENABLE
, bo
, offset
, imm
);
6242 /* "Flush Types" workarounds ---------------------------------------------
6243 * We do these now because they may add post-sync operations or CS stalls.
6246 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
6247 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
6249 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
6250 * 'Write PS Depth Count' or 'Write Timestamp'."
6253 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6254 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6255 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6256 bo
= batch
->screen
->workaround_bo
;
6260 /* #1130 from Gen10 workarounds page:
6262 * "Enable Depth Stall on every Post Sync Op if Render target Cache
6263 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
6264 * board stall if Render target cache flush is enabled."
6266 * Applicable to CNL B0 and C0 steppings only.
6268 * The wording here is unclear, and this workaround doesn't look anything
6269 * like the internal bug report recommendations, but leave it be for now...
6271 if (GEN_GEN
== 10) {
6272 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
6273 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6274 } else if (flags
& non_lri_post_sync_flags
) {
6275 flags
|= PIPE_CONTROL_DEPTH_STALL
;
6279 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
6280 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
6282 * "This bit must be DISABLED for operations other than writing
6285 * This seems like nonsense. An Ivybridge workaround requires us to
6286 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
6287 * operation. Gen8+ requires us to emit depth stalls and depth cache
6288 * flushes together. So, it's hard to imagine this means anything other
6289 * than "we originally intended this to be used for PS_DEPTH_COUNT".
6291 * We ignore the supposed restriction and do nothing.
6295 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6296 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6297 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
6299 * "This bit must be DISABLED for End-of-pipe (Read) fences,
6300 * PS_DEPTH_COUNT or TIMESTAMP queries."
6302 * TODO: Implement end-of-pipe checking.
6304 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6305 PIPE_CONTROL_WRITE_TIMESTAMP
)));
6308 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6309 /* From the PIPE_CONTROL instruction table, bit 1:
6311 * "This bit is ignored if Depth Stall Enable is set.
6312 * Further, the render cache is not flushed even if Write Cache
6313 * Flush Enable bit is set."
6315 * We assert that the caller doesn't do this combination, to try and
6316 * prevent mistakes. It shouldn't hurt the GPU, though.
6318 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
6319 * and "Render Target Flush" combo is explicitly required for BTI
6320 * update workarounds.
6322 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
6323 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
6326 /* PIPE_CONTROL page workarounds ------------------------------------- */
6328 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
6329 /* From the PIPE_CONTROL page itself:
6332 * Restriction: Pipe_control with CS-stall bit set must be issued
6333 * before a pipe-control command that has the State Cache
6334 * Invalidate bit set."
6336 flags
|= PIPE_CONTROL_CS_STALL
;
6339 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
6340 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
6343 * SW must always program Post-Sync Operation to "Write Immediate
6344 * Data" when Flush LLC is set."
6346 * For now, we just require the caller to do it.
6348 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
6351 /* "Post-Sync Operation" workarounds -------------------------------- */
6353 /* Project: All / Argument: Global Snapshot Count Reset [19]
6355 * "This bit must not be exercised on any product.
6356 * Requires stall bit ([20] of DW1) set."
6358 * We don't use this, so we just assert that it isn't used. The
6359 * PIPE_CONTROL instruction page indicates that they intended this
6360 * as a debug feature and don't think it is useful in production,
6361 * but it may actually be usable, should we ever want to.
6363 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
6365 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
6366 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
6367 /* Project: All / Arguments:
6369 * - Generic Media State Clear [16]
6370 * - Indirect State Pointers Disable [16]
6372 * "Requires stall bit ([20] of DW1) set."
6374 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
6375 * State Clear) says:
6377 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6378 * programmed prior to programming a PIPECONTROL command with "Media
6379 * State Clear" set in GPGPU mode of operation"
6381 * This is a subset of the earlier rule, so there's nothing to do.
6383 flags
|= PIPE_CONTROL_CS_STALL
;
6386 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
6387 /* Project: All / Argument: Store Data Index
6389 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6392 * For now, we just assert that the caller does this. We might want to
6393 * automatically add a write to the workaround BO...
6395 assert(non_lri_post_sync_flags
!= 0);
6398 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
6399 /* Project: All / Argument: Sync GFDT
6401 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6402 * than '0' or 0x2520[13] must be set."
6404 * For now, we just assert that the caller does this.
6406 assert(non_lri_post_sync_flags
!= 0);
6409 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
6410 /* Project: IVB+ / Argument: TLB inv
6412 * "Requires stall bit ([20] of DW1) set."
6414 * Also, from the PIPE_CONTROL instruction table:
6417 * Post Sync Operation or CS stall must be set to ensure a TLB
6418 * invalidation occurs. Otherwise no cycle will occur to the TLB
6419 * cache to invalidate."
6421 * This is not a subset of the earlier rule, so there's nothing to do.
6423 flags
|= PIPE_CONTROL_CS_STALL
;
6426 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
6427 /* TODO: The big Skylake GT4 post sync op workaround */
6430 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
6432 if (IS_COMPUTE_PIPELINE(batch
)) {
6433 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
6434 /* Project: SKL+ / Argument: Tex Invalidate
6435 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
6437 flags
|= PIPE_CONTROL_CS_STALL
;
6440 if (GEN_GEN
== 8 && (post_sync_flags
||
6441 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
6442 PIPE_CONTROL_DEPTH_STALL
|
6443 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6444 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6445 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
6446 /* Project: BDW / Arguments:
6448 * - LRI Post Sync Operation [23]
6449 * - Post Sync Op [15:14]
6451 * - Depth Stall [13]
6452 * - Render Target Cache Flush [12]
6453 * - Depth Cache Flush [0]
6454 * - DC Flush Enable [5]
6456 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
6459 flags
|= PIPE_CONTROL_CS_STALL
;
6461 /* Also, from the PIPE_CONTROL instruction table, bit 20:
6464 * This bit must be always set when PIPE_CONTROL command is
6465 * programmed by GPGPU and MEDIA workloads, except for the cases
6466 * when only Read Only Cache Invalidation bits are set (State
6467 * Cache Invalidation Enable, Instruction cache Invalidation
6468 * Enable, Texture Cache Invalidation Enable, Constant Cache
6469 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
6470 * need not implemented when FF_DOP_CG is disable via "Fixed
6471 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
6473 * It sounds like we could avoid CS stalls in some cases, but we
6474 * don't currently bother. This list isn't exactly the list above,
6480 /* "Stall" workarounds ----------------------------------------------
6481 * These have to come after the earlier ones because we may have added
6482 * some additional CS stalls above.
6485 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
6486 /* Project: PRE-SKL, VLV, CHV
6488 * "[All Stepping][All SKUs]:
6490 * One of the following must also be set:
6492 * - Render Target Cache Flush Enable ([12] of DW1)
6493 * - Depth Cache Flush Enable ([0] of DW1)
6494 * - Stall at Pixel Scoreboard ([1] of DW1)
6495 * - Depth Stall ([13] of DW1)
6496 * - Post-Sync Operation ([13] of DW1)
6497 * - DC Flush Enable ([5] of DW1)"
6499 * If we don't already have one of those bits set, we choose to add
6500 * "Stall at Pixel Scoreboard". Some of the other bits require a
6501 * CS stall as a workaround (see above), which would send us into
6502 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
6503 * appears to be safe, so we choose that.
6505 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6506 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6507 PIPE_CONTROL_WRITE_IMMEDIATE
|
6508 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6509 PIPE_CONTROL_WRITE_TIMESTAMP
|
6510 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
6511 PIPE_CONTROL_DEPTH_STALL
|
6512 PIPE_CONTROL_DATA_CACHE_FLUSH
;
6513 if (!(flags
& wa_bits
))
6514 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6517 /* Emit --------------------------------------------------------------- */
6519 if (INTEL_DEBUG
& DEBUG_PIPE_CONTROL
) {
6521 " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64
"]: %s\n",
6522 (flags
& PIPE_CONTROL_FLUSH_ENABLE
) ? "PipeCon " : "",
6523 (flags
& PIPE_CONTROL_CS_STALL
) ? "CS " : "",
6524 (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) ? "Scoreboard " : "",
6525 (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) ? "VF " : "",
6526 (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) ? "RT " : "",
6527 (flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
) ? "Const " : "",
6528 (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
) ? "TC " : "",
6529 (flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
) ? "DC " : "",
6530 (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
) ? "ZFlush " : "",
6531 (flags
& PIPE_CONTROL_DEPTH_STALL
) ? "ZStall " : "",
6532 (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
) ? "State " : "",
6533 (flags
& PIPE_CONTROL_TLB_INVALIDATE
) ? "TLB " : "",
6534 (flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
) ? "Inst " : "",
6535 (flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
) ? "MediaClear " : "",
6536 (flags
& PIPE_CONTROL_NOTIFY_ENABLE
) ? "Notify " : "",
6537 (flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) ?
6539 (flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
) ?
6541 (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
) ? "WriteImm " : "",
6542 (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
) ? "WriteZCount " : "",
6543 (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
) ? "WriteTimestamp " : "",
6547 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
6548 pc
.LRIPostSyncOperation
= NoLRIOperation
;
6549 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
6550 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
6551 pc
.StoreDataIndex
= 0;
6552 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
6553 pc
.GlobalSnapshotCountReset
=
6554 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
6555 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
6556 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
6557 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6558 pc
.RenderTargetCacheFlushEnable
=
6559 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
6560 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
6561 pc
.StateCacheInvalidationEnable
=
6562 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
6563 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
6564 pc
.ConstantCacheInvalidationEnable
=
6565 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
6566 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
6567 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
6568 pc
.InstructionCacheInvalidateEnable
=
6569 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
6570 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
6571 pc
.IndirectStatePointersDisable
=
6572 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
6573 pc
.TextureCacheInvalidationEnable
=
6574 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
6575 pc
.Address
= rw_bo(bo
, offset
);
6576 pc
.ImmediateData
= imm
;
6581 genX(emit_urb_setup
)(struct iris_context
*ice
,
6582 struct iris_batch
*batch
,
6583 const unsigned size
[4],
6584 bool tess_present
, bool gs_present
)
6586 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6587 const unsigned push_size_kB
= 32;
6588 unsigned entries
[4];
6591 ice
->shaders
.last_vs_entry_size
= size
[MESA_SHADER_VERTEX
];
6593 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
6594 1024 * ice
->shaders
.urb_size
,
6595 tess_present
, gs_present
,
6596 size
, entries
, start
);
6598 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
6599 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
6600 urb
._3DCommandSubOpcode
+= i
;
6601 urb
.VSURBStartingAddress
= start
[i
];
6602 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
6603 urb
.VSNumberofURBEntries
= entries
[i
];
6610 * Preemption on Gen9 has to be enabled or disabled in various cases.
6612 * See these workarounds for preemption:
6613 * - WaDisableMidObjectPreemptionForGSLineStripAdj
6614 * - WaDisableMidObjectPreemptionForTrifanOrPolygon
6615 * - WaDisableMidObjectPreemptionForLineLoop
6618 * We don't put this in the vtable because it's only used on Gen9.
6621 gen9_toggle_preemption(struct iris_context
*ice
,
6622 struct iris_batch
*batch
,
6623 const struct pipe_draw_info
*draw
)
6625 struct iris_genx_state
*genx
= ice
->state
.genx
;
6626 bool object_preemption
= true;
6628 /* WaDisableMidObjectPreemptionForGSLineStripAdj
6630 * "WA: Disable mid-draw preemption when draw-call is a linestrip_adj
6631 * and GS is enabled."
6633 if (draw
->mode
== PIPE_PRIM_LINE_STRIP_ADJACENCY
&&
6634 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
6635 object_preemption
= false;
6637 /* WaDisableMidObjectPreemptionForTrifanOrPolygon
6639 * "TriFan miscompare in Execlist Preemption test. Cut index that is
6640 * on a previous context. End the previous, the resume another context
6641 * with a tri-fan or polygon, and the vertex count is corrupted. If we
6642 * prempt again we will cause corruption.
6644 * WA: Disable mid-draw preemption when draw-call has a tri-fan."
6646 if (draw
->mode
== PIPE_PRIM_TRIANGLE_FAN
)
6647 object_preemption
= false;
6649 /* WaDisableMidObjectPreemptionForLineLoop
6651 * "VF Stats Counters Missing a vertex when preemption enabled.
6653 * WA: Disable mid-draw preemption when the draw uses a lineloop
6656 if (draw
->mode
== PIPE_PRIM_LINE_LOOP
)
6657 object_preemption
= false;
6661 * "VF is corrupting GAFS data when preempted on an instance boundary
6662 * and replayed with instancing enabled.
6664 * WA: Disable preemption when using instanceing."
6666 if (draw
->instance_count
> 1)
6667 object_preemption
= false;
6669 if (genx
->object_preemption
!= object_preemption
) {
6670 iris_enable_obj_preemption(batch
, object_preemption
);
6671 genx
->object_preemption
= object_preemption
;
6677 iris_lost_genx_state(struct iris_context
*ice
, struct iris_batch
*batch
)
6679 struct iris_genx_state
*genx
= ice
->state
.genx
;
6681 memset(genx
->last_index_buffer
, 0, sizeof(genx
->last_index_buffer
));
6685 iris_emit_mi_report_perf_count(struct iris_batch
*batch
,
6687 uint32_t offset_in_bytes
,
6690 iris_emit_cmd(batch
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
6691 mi_rpc
.MemoryAddress
= rw_bo(bo
, offset_in_bytes
);
6692 mi_rpc
.ReportID
= report_id
;
6697 * Update the pixel hashing modes that determine the balancing of PS threads
6698 * across subslices and slices.
6700 * \param width Width bound of the rendering area (already scaled down if \p
6701 * scale is greater than 1).
6702 * \param height Height bound of the rendering area (already scaled down if \p
6703 * scale is greater than 1).
6704 * \param scale The number of framebuffer samples that could potentially be
6705 * affected by an individual channel of the PS thread. This is
6706 * typically one for single-sampled rendering, but for operations
6707 * like CCS resolves and fast clears a single PS invocation may
6708 * update a huge number of pixels, in which case a finer
6709 * balancing is desirable in order to maximally utilize the
6710 * bandwidth available. UINT_MAX can be used as shorthand for
6711 * "finest hashing mode available".
6714 genX(emit_hashing_mode
)(struct iris_context
*ice
, struct iris_batch
*batch
,
6715 unsigned width
, unsigned height
, unsigned scale
)
6718 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6719 const unsigned slice_hashing
[] = {
6720 /* Because all Gen9 platforms with more than one slice require
6721 * three-way subslice hashing, a single "normal" 16x16 slice hashing
6722 * block is guaranteed to suffer from substantial imbalance, with one
6723 * subslice receiving twice as much work as the other two in the
6726 * The performance impact of that would be particularly severe when
6727 * three-way hashing is also in use for slice balancing (which is the
6728 * case for all Gen9 GT4 platforms), because one of the slices
6729 * receives one every three 16x16 blocks in either direction, which
6730 * is roughly the periodicity of the underlying subslice imbalance
6731 * pattern ("roughly" because in reality the hardware's
6732 * implementation of three-way hashing doesn't do exact modulo 3
6733 * arithmetic, which somewhat decreases the magnitude of this effect
6734 * in practice). This leads to a systematic subslice imbalance
6735 * within that slice regardless of the size of the primitive. The
6736 * 32x32 hashing mode guarantees that the subslice imbalance within a
6737 * single slice hashing block is minimal, largely eliminating this
6741 /* Finest slice hashing mode available. */
6744 const unsigned subslice_hashing
[] = {
6745 /* 16x16 would provide a slight cache locality benefit especially
6746 * visible in the sampler L1 cache efficiency of low-bandwidth
6747 * non-LLC platforms, but it comes at the cost of greater subslice
6748 * imbalance for primitives of dimensions approximately intermediate
6749 * between 16x4 and 16x16.
6752 /* Finest subslice hashing mode available. */
6755 /* Dimensions of the smallest hashing block of a given hashing mode. If
6756 * the rendering area is smaller than this there can't possibly be any
6757 * benefit from switching to this mode, so we optimize out the
6760 const unsigned min_size
[][2] = {
6764 const unsigned idx
= scale
> 1;
6766 if (width
> min_size
[idx
][0] || height
> min_size
[idx
][1]) {
6769 iris_pack_state(GENX(GT_MODE
), >_mode
, reg
) {
6770 reg
.SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0);
6771 reg
.SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0);
6772 reg
.SubsliceHashing
= subslice_hashing
[idx
];
6773 reg
.SubsliceHashingMask
= -1;
6776 iris_emit_raw_pipe_control(batch
,
6777 "workaround: CS stall before GT_MODE LRI",
6778 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
6779 PIPE_CONTROL_CS_STALL
,
6782 iris_emit_lri(batch
, GT_MODE
, gt_mode
);
6784 ice
->state
.current_hash_scale
= scale
;
6790 genX(init_state
)(struct iris_context
*ice
)
6792 struct pipe_context
*ctx
= &ice
->ctx
;
6793 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
6795 ctx
->create_blend_state
= iris_create_blend_state
;
6796 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
6797 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
6798 ctx
->create_sampler_state
= iris_create_sampler_state
;
6799 ctx
->create_sampler_view
= iris_create_sampler_view
;
6800 ctx
->create_surface
= iris_create_surface
;
6801 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
6802 ctx
->bind_blend_state
= iris_bind_blend_state
;
6803 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
6804 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
6805 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
6806 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
6807 ctx
->delete_blend_state
= iris_delete_state
;
6808 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
6809 ctx
->delete_rasterizer_state
= iris_delete_state
;
6810 ctx
->delete_sampler_state
= iris_delete_state
;
6811 ctx
->delete_vertex_elements_state
= iris_delete_state
;
6812 ctx
->set_blend_color
= iris_set_blend_color
;
6813 ctx
->set_clip_state
= iris_set_clip_state
;
6814 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
6815 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
6816 ctx
->set_shader_images
= iris_set_shader_images
;
6817 ctx
->set_sampler_views
= iris_set_sampler_views
;
6818 ctx
->set_tess_state
= iris_set_tess_state
;
6819 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
6820 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
6821 ctx
->set_sample_mask
= iris_set_sample_mask
;
6822 ctx
->set_scissor_states
= iris_set_scissor_states
;
6823 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
6824 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
6825 ctx
->set_viewport_states
= iris_set_viewport_states
;
6826 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
6827 ctx
->surface_destroy
= iris_surface_destroy
;
6828 ctx
->draw_vbo
= iris_draw_vbo
;
6829 ctx
->launch_grid
= iris_launch_grid
;
6830 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
6831 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
6832 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
6834 ice
->vtbl
.destroy_state
= iris_destroy_state
;
6835 ice
->vtbl
.init_render_context
= iris_init_render_context
;
6836 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
6837 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
6838 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
6839 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
6840 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
6841 ice
->vtbl
.emit_mi_report_perf_count
= iris_emit_mi_report_perf_count
;
6842 ice
->vtbl
.rebind_buffer
= iris_rebind_buffer
;
6843 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
6844 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
6845 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
6846 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
6847 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
6848 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
6849 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
6850 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
6851 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
6852 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
6853 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
6854 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
6855 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
6856 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
6857 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
6858 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
6859 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
6860 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
6861 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
6862 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
6863 ice
->vtbl
.mocs
= mocs
;
6864 ice
->vtbl
.lost_genx_state
= iris_lost_genx_state
;
6866 ice
->state
.dirty
= ~0ull;
6868 ice
->state
.statistics_counters_enabled
= true;
6870 ice
->state
.sample_mask
= 0xffff;
6871 ice
->state
.num_viewports
= 1;
6872 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
6874 /* Make a 1x1x1 null surface for unbound textures */
6875 void *null_surf_map
=
6876 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
6877 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
6878 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
6879 ice
->state
.unbound_tex
.offset
+=
6880 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
6882 /* Default all scissor rectangles to be empty regions. */
6883 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
6884 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
6885 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,