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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_inlines.h"
92 #include "util/u_format.h"
93 #include "util/u_framebuffer.h"
94 #include "util/u_transfer.h"
95 #include "util/u_upload_mgr.h"
96 #include "util/u_viewport.h"
99 #include "intel/compiler/brw_compiler.h"
100 #include "intel/common/gen_l3_config.h"
101 #include "intel/common/gen_sample_positions.h"
102 #include "iris_batch.h"
103 #include "iris_context.h"
104 #include "iris_defines.h"
105 #include "iris_pipe.h"
106 #include "iris_resource.h"
108 #define __gen_address_type struct iris_address
109 #define __gen_user_data struct iris_batch
111 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
114 __gen_combine_address(struct iris_batch
*batch
, void *location
,
115 struct iris_address addr
, uint32_t delta
)
117 uint64_t result
= addr
.offset
+ delta
;
120 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
121 /* Assume this is a general address, not relative to a base. */
122 result
+= addr
.bo
->gtt_offset
;
128 #define __genxml_cmd_length(cmd) cmd ## _length
129 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
130 #define __genxml_cmd_header(cmd) cmd ## _header
131 #define __genxml_cmd_pack(cmd) cmd ## _pack
133 #define _iris_pack_command(batch, cmd, dst, name) \
134 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
135 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
136 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
140 #define iris_pack_command(cmd, dst, name) \
141 _iris_pack_command(NULL, cmd, dst, name)
143 #define iris_pack_state(cmd, dst, name) \
144 for (struct cmd name = {}, \
145 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
146 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
149 #define iris_emit_cmd(batch, cmd, name) \
150 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
152 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
154 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
155 for (uint32_t i = 0; i < num_dwords; i++) \
156 dw[i] = (dwords0)[i] | (dwords1)[i]; \
157 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
160 #include "genxml/genX_pack.h"
161 #include "genxml/gen_macros.h"
162 #include "genxml/genX_bits.h"
165 #define MOCS_PTE 0x18
168 #define MOCS_PTE (1 << 1)
169 #define MOCS_WB (2 << 1)
173 mocs(struct iris_bo
*bo
)
175 return bo
&& bo
->external
? MOCS_PTE
: MOCS_WB
;
179 * Statically assert that PIPE_* enums match the hardware packets.
180 * (As long as they match, we don't need to translate them.)
182 UNUSED
static void pipe_asserts()
184 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
186 /* pipe_logicop happens to match the hardware. */
187 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
188 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
189 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
190 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
191 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
192 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
193 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
194 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
195 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
196 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
197 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
198 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
199 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
200 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
201 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
202 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
204 /* pipe_blend_func happens to match the hardware. */
205 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
206 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
207 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
211 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
212 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
213 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
214 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
215 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
216 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
217 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
218 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
219 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
220 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
221 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
222 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
223 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
225 /* pipe_blend_func happens to match the hardware. */
226 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
227 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
228 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
229 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
230 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
232 /* pipe_stencil_op happens to match the hardware. */
233 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
234 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
235 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
236 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
237 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
238 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
239 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
240 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
242 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
243 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
244 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
249 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
251 static const unsigned map
[] = {
252 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
253 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
254 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
255 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
256 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
257 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
258 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
259 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
260 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
261 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
262 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
263 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
264 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
265 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
266 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
269 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
273 translate_compare_func(enum pipe_compare_func pipe_func
)
275 static const unsigned map
[] = {
276 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
277 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
278 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
279 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
280 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
281 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
282 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
283 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
285 return map
[pipe_func
];
289 translate_shadow_func(enum pipe_compare_func pipe_func
)
291 /* Gallium specifies the result of shadow comparisons as:
293 * 1 if ref <op> texel,
298 * 0 if texel <op> ref,
301 * So we need to flip the operator and also negate.
303 static const unsigned map
[] = {
304 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
305 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
306 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
307 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
308 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
309 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
310 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
311 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
313 return map
[pipe_func
];
317 translate_cull_mode(unsigned pipe_face
)
319 static const unsigned map
[4] = {
320 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
321 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
322 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
323 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
325 return map
[pipe_face
];
329 translate_fill_mode(unsigned pipe_polymode
)
331 static const unsigned map
[4] = {
332 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
333 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
334 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
335 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
337 return map
[pipe_polymode
];
341 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
343 static const unsigned map
[] = {
344 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
345 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
346 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
348 return map
[pipe_mip
];
352 translate_wrap(unsigned pipe_wrap
)
354 static const unsigned map
[] = {
355 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
356 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
357 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
358 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
359 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
360 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
362 /* These are unsupported. */
363 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
364 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
366 return map
[pipe_wrap
];
369 static struct iris_address
370 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
372 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
373 * validation list at CSO creation time, instead of draw time.
375 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
378 static struct iris_address
379 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
381 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
382 * validation list at CSO creation time, instead of draw time.
384 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
388 * Allocate space for some indirect state.
390 * Return a pointer to the map (to fill it out) and a state ref (for
391 * referring to the state in GPU commands).
394 upload_state(struct u_upload_mgr
*uploader
,
395 struct iris_state_ref
*ref
,
400 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
405 * Stream out temporary/short-lived state.
407 * This allocates space, pins the BO, and includes the BO address in the
408 * returned offset (which works because all state lives in 32-bit memory
412 stream_state(struct iris_batch
*batch
,
413 struct u_upload_mgr
*uploader
,
414 struct pipe_resource
**out_res
,
417 uint32_t *out_offset
)
421 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
423 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
424 iris_use_pinned_bo(batch
, bo
, false);
426 *out_offset
+= iris_bo_offset_from_base_address(bo
);
432 * stream_state() + memcpy.
435 emit_state(struct iris_batch
*batch
,
436 struct u_upload_mgr
*uploader
,
437 struct pipe_resource
**out_res
,
444 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
447 memcpy(map
, data
, size
);
453 * Did field 'x' change between 'old_cso' and 'new_cso'?
455 * (If so, we may want to set some dirty flags.)
457 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
458 #define cso_changed_memcmp(x) \
459 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
462 flush_for_state_base_change(struct iris_batch
*batch
)
464 /* Flush before emitting STATE_BASE_ADDRESS.
466 * This isn't documented anywhere in the PRM. However, it seems to be
467 * necessary prior to changing the surface state base adress. We've
468 * seen issues in Vulkan where we get GPU hangs when using multi-level
469 * command buffers which clear depth, reset state base address, and then
472 * Normally, in GL, we would trust the kernel to do sufficient stalls
473 * and flushes prior to executing our batch. However, it doesn't seem
474 * as if the kernel's flushing is always sufficient and we don't want to
477 * We make this an end-of-pipe sync instead of a normal flush because we
478 * do not know the current status of the GPU. On Haswell at least,
479 * having a fast-clear operation in flight at the same time as a normal
480 * rendering operation can cause hangs. Since the kernel's flushing is
481 * insufficient, we need to ensure that any rendering operations from
482 * other processes are definitely complete before we try to do our own
483 * rendering. It's a bit of a big hammer but it appears to work.
485 iris_emit_end_of_pipe_sync(batch
,
486 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
487 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
488 PIPE_CONTROL_DATA_CACHE_FLUSH
);
492 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
494 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
495 lri
.RegisterOffset
= reg
;
499 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
502 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
504 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
505 lrr
.SourceRegisterAddress
= src
;
506 lrr
.DestinationRegisterAddress
= dst
;
511 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
513 #if GEN_GEN >= 8 && GEN_GEN < 10
514 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
516 * Software must clear the COLOR_CALC_STATE Valid field in
517 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
518 * with Pipeline Select set to GPGPU.
520 * The internal hardware docs recommend the same workaround for Gen9
523 if (pipeline
== GPGPU
)
524 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
528 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
529 * PIPELINE_SELECT [DevBWR+]":
533 * Software must ensure all the write caches are flushed through a
534 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
535 * command to invalidate read only caches prior to programming
536 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
538 iris_emit_pipe_control_flush(batch
,
539 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
540 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
541 PIPE_CONTROL_DATA_CACHE_FLUSH
|
542 PIPE_CONTROL_CS_STALL
);
544 iris_emit_pipe_control_flush(batch
,
545 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
546 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
547 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
548 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
550 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
554 sel
.PipelineSelection
= pipeline
;
559 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
564 * "This chicken bit works around a hardware issue with barrier
565 * logic encountered when switching between GPGPU and 3D pipelines.
566 * To workaround the issue, this mode bit should be set after a
567 * pipeline is selected."
570 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
571 reg
.GLKBarrierMode
= value
;
572 reg
.GLKBarrierModeMask
= 1;
574 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
579 init_state_base_address(struct iris_batch
*batch
)
581 flush_for_state_base_change(batch
);
583 /* We program most base addresses once at context initialization time.
584 * Each base address points at a 4GB memory zone, and never needs to
585 * change. See iris_bufmgr.h for a description of the memory zones.
587 * The one exception is Surface State Base Address, which needs to be
588 * updated occasionally. See iris_binder.c for the details there.
590 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
591 sba
.GeneralStateMOCS
= MOCS_WB
;
592 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
593 sba
.DynamicStateMOCS
= MOCS_WB
;
594 sba
.IndirectObjectMOCS
= MOCS_WB
;
595 sba
.InstructionMOCS
= MOCS_WB
;
597 sba
.GeneralStateBaseAddressModifyEnable
= true;
598 sba
.DynamicStateBaseAddressModifyEnable
= true;
599 sba
.IndirectObjectBaseAddressModifyEnable
= true;
600 sba
.InstructionBaseAddressModifyEnable
= true;
601 sba
.GeneralStateBufferSizeModifyEnable
= true;
602 sba
.DynamicStateBufferSizeModifyEnable
= true;
604 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
605 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
607 sba
.IndirectObjectBufferSizeModifyEnable
= true;
608 sba
.InstructionBuffersizeModifyEnable
= true;
610 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
611 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
613 sba
.GeneralStateBufferSize
= 0xfffff;
614 sba
.IndirectObjectBufferSize
= 0xfffff;
615 sba
.InstructionBufferSize
= 0xfffff;
616 sba
.DynamicStateBufferSize
= 0xfffff;
621 iris_emit_l3_config(struct iris_batch
*batch
, const struct gen_l3_config
*cfg
,
622 bool has_slm
, bool wants_dc_cache
)
625 iris_pack_state(GENX(L3CNTLREG
), ®_val
, reg
) {
626 reg
.SLMEnable
= has_slm
;
628 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
629 * in L3CNTLREG register. The default setting of the bit is not the
630 * desirable behavior.
632 reg
.ErrorDetectionBehaviorControl
= true;
634 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
635 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
636 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
637 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
639 iris_emit_lri(batch
, L3CNTLREG
, reg_val
);
643 iris_emit_default_l3_config(struct iris_batch
*batch
,
644 const struct gen_device_info
*devinfo
,
647 bool wants_dc_cache
= true;
648 bool has_slm
= compute
;
649 const struct gen_l3_weights w
=
650 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
651 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
652 iris_emit_l3_config(batch
, cfg
, has_slm
, wants_dc_cache
);
656 * Upload the initial GPU state for a render context.
658 * This sets some invariant state that needs to be programmed a particular
659 * way, but we never actually change.
662 iris_init_render_context(struct iris_screen
*screen
,
663 struct iris_batch
*batch
,
664 struct iris_vtable
*vtbl
,
665 struct pipe_debug_callback
*dbg
)
667 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
670 emit_pipeline_select(batch
, _3D
);
672 iris_emit_default_l3_config(batch
, devinfo
, false);
674 init_state_base_address(batch
);
677 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
678 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
679 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
681 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
683 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
684 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
685 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
687 iris_emit_lri(batch
, INSTPM
, reg_val
);
691 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
692 reg
.FloatBlendOptimizationEnable
= true;
693 reg
.FloatBlendOptimizationEnableMask
= true;
694 reg
.PartialResolveDisableInVC
= true;
695 reg
.PartialResolveDisableInVCMask
= true;
697 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
699 if (devinfo
->is_geminilake
)
700 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
704 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
705 reg
.HeaderlessMessageforPreemptableContexts
= 1;
706 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
708 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
713 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
714 * changing it dynamically. We set it to the maximum size here, and
715 * instead include the render target dimensions in the viewport, so
716 * viewport extents clipping takes care of pruning stray geometry.
718 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
719 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
720 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
723 /* Set the initial MSAA sample positions. */
724 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
725 GEN_SAMPLE_POS_1X(pat
._1xSample
);
726 GEN_SAMPLE_POS_2X(pat
._2xSample
);
727 GEN_SAMPLE_POS_4X(pat
._4xSample
);
728 GEN_SAMPLE_POS_8X(pat
._8xSample
);
730 GEN_SAMPLE_POS_16X(pat
._16xSample
);
734 /* Use the legacy AA line coverage computation. */
735 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
737 /* Disable chromakeying (it's for media) */
738 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
740 /* We want regular rendering, not special HiZ operations. */
741 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
743 /* No polygon stippling offsets are necessary. */
744 /* TODO: may need to set an offset for origin-UL framebuffers */
745 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
747 /* Set a static partitioning of the push constant area. */
748 /* TODO: this may be a bad idea...could starve the push ringbuffers... */
749 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
750 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
751 alloc
._3DCommandSubOpcode
= 18 + i
;
752 alloc
.ConstantBufferOffset
= 6 * i
;
753 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
759 iris_init_compute_context(struct iris_screen
*screen
,
760 struct iris_batch
*batch
,
761 struct iris_vtable
*vtbl
,
762 struct pipe_debug_callback
*dbg
)
764 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
766 emit_pipeline_select(batch
, GPGPU
);
768 iris_emit_default_l3_config(batch
, devinfo
, true);
770 init_state_base_address(batch
);
773 if (devinfo
->is_geminilake
)
774 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
778 struct iris_vertex_buffer_state
{
779 /** The VERTEX_BUFFER_STATE hardware structure. */
780 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
782 /** The resource to source vertex data from. */
783 struct pipe_resource
*resource
;
786 struct iris_depth_buffer_state
{
787 /* Depth/HiZ/Stencil related hardware packets. */
788 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
789 GENX(3DSTATE_STENCIL_BUFFER_length
) +
790 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
791 GENX(3DSTATE_CLEAR_PARAMS_length
)];
795 * Generation-specific context state (ice->state.genx->...).
797 * Most state can go in iris_context directly, but these encode hardware
798 * packets which vary by generation.
800 struct iris_genx_state
{
801 struct iris_vertex_buffer_state vertex_buffers
[33];
803 struct iris_depth_buffer_state depth_buffer
;
805 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
809 * The pipe->set_blend_color() driver hook.
811 * This corresponds to our COLOR_CALC_STATE.
814 iris_set_blend_color(struct pipe_context
*ctx
,
815 const struct pipe_blend_color
*state
)
817 struct iris_context
*ice
= (struct iris_context
*) ctx
;
819 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
820 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
821 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
825 * Gallium CSO for blend state (see pipe_blend_state).
827 struct iris_blend_state
{
828 /** Partial 3DSTATE_PS_BLEND */
829 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
831 /** Partial BLEND_STATE */
832 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
833 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
835 bool alpha_to_coverage
; /* for shader key */
837 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
838 uint8_t blend_enables
;
840 /** Bitfield of whether color writes are enabled for RT[i] */
841 uint8_t color_write_enables
;
844 static enum pipe_blendfactor
845 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
848 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
849 return PIPE_BLENDFACTOR_ONE
;
851 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
852 return PIPE_BLENDFACTOR_ZERO
;
859 * The pipe->create_blend_state() driver hook.
861 * Translates a pipe_blend_state into iris_blend_state.
864 iris_create_blend_state(struct pipe_context
*ctx
,
865 const struct pipe_blend_state
*state
)
867 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
868 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
870 cso
->blend_enables
= 0;
871 cso
->color_write_enables
= 0;
872 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
874 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
876 bool indep_alpha_blend
= false;
878 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
879 const struct pipe_rt_blend_state
*rt
=
880 &state
->rt
[state
->independent_blend_enable
? i
: 0];
882 enum pipe_blendfactor src_rgb
=
883 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
884 enum pipe_blendfactor src_alpha
=
885 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
886 enum pipe_blendfactor dst_rgb
=
887 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
888 enum pipe_blendfactor dst_alpha
=
889 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
891 if (rt
->rgb_func
!= rt
->alpha_func
||
892 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
893 indep_alpha_blend
= true;
895 if (rt
->blend_enable
)
896 cso
->blend_enables
|= 1u << i
;
899 cso
->color_write_enables
|= 1u << i
;
901 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
902 be
.LogicOpEnable
= state
->logicop_enable
;
903 be
.LogicOpFunction
= state
->logicop_func
;
905 be
.PreBlendSourceOnlyClampEnable
= false;
906 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
907 be
.PreBlendColorClampEnable
= true;
908 be
.PostBlendColorClampEnable
= true;
910 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
912 be
.ColorBlendFunction
= rt
->rgb_func
;
913 be
.AlphaBlendFunction
= rt
->alpha_func
;
914 be
.SourceBlendFactor
= src_rgb
;
915 be
.SourceAlphaBlendFactor
= src_alpha
;
916 be
.DestinationBlendFactor
= dst_rgb
;
917 be
.DestinationAlphaBlendFactor
= dst_alpha
;
919 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
920 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
921 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
922 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
924 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
927 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
928 /* pb.HasWriteableRT is filled in at draw time. */
929 /* pb.AlphaTestEnable is filled in at draw time. */
930 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
931 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
933 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
935 pb
.SourceBlendFactor
=
936 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
937 pb
.SourceAlphaBlendFactor
=
938 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
939 pb
.DestinationBlendFactor
=
940 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
941 pb
.DestinationAlphaBlendFactor
=
942 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
945 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
946 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
947 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
948 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
949 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
950 bs
.ColorDitherEnable
= state
->dither
;
951 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
959 * The pipe->bind_blend_state() driver hook.
961 * Bind a blending CSO and flag related dirty bits.
964 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
966 struct iris_context
*ice
= (struct iris_context
*) ctx
;
967 struct iris_blend_state
*cso
= state
;
969 ice
->state
.cso_blend
= cso
;
970 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
972 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
973 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
974 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
978 * Return true if the FS writes to any color outputs which are not disabled
982 has_writeable_rt(const struct iris_blend_state
*cso_blend
,
983 const struct shader_info
*fs_info
)
988 unsigned rt_outputs
= fs_info
->outputs_written
>> FRAG_RESULT_DATA0
;
990 if (fs_info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
))
991 rt_outputs
= (1 << BRW_MAX_DRAW_BUFFERS
) - 1;
993 return cso_blend
->color_write_enables
& rt_outputs
;
997 * Gallium CSO for depth, stencil, and alpha testing state.
999 struct iris_depth_stencil_alpha_state
{
1000 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
1001 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1003 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
1004 struct pipe_alpha_state alpha
;
1006 /** Outbound to resolve and cache set tracking. */
1007 bool depth_writes_enabled
;
1008 bool stencil_writes_enabled
;
1012 * The pipe->create_depth_stencil_alpha_state() driver hook.
1014 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
1015 * testing state since we need pieces of it in a variety of places.
1018 iris_create_zsa_state(struct pipe_context
*ctx
,
1019 const struct pipe_depth_stencil_alpha_state
*state
)
1021 struct iris_depth_stencil_alpha_state
*cso
=
1022 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
1024 bool two_sided_stencil
= state
->stencil
[1].enabled
;
1026 cso
->alpha
= state
->alpha
;
1027 cso
->depth_writes_enabled
= state
->depth
.writemask
;
1028 cso
->stencil_writes_enabled
=
1029 state
->stencil
[0].writemask
!= 0 ||
1030 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 1);
1032 /* The state tracker needs to optimize away EQUAL writes for us. */
1033 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
1035 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
1036 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1037 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1038 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1039 wmds
.StencilTestFunction
=
1040 translate_compare_func(state
->stencil
[0].func
);
1041 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1042 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1043 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1044 wmds
.BackfaceStencilTestFunction
=
1045 translate_compare_func(state
->stencil
[1].func
);
1046 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1047 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1048 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1049 wmds
.StencilBufferWriteEnable
=
1050 state
->stencil
[0].writemask
!= 0 ||
1051 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1052 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1053 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1054 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1055 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1056 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1057 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1058 /* wmds.[Backface]StencilReferenceValue are merged later */
1065 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1067 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1070 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1072 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1073 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1074 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1077 if (cso_changed(alpha
.ref_value
))
1078 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1080 if (cso_changed(alpha
.enabled
))
1081 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1083 if (cso_changed(alpha
.func
))
1084 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1086 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1087 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1090 ice
->state
.cso_zsa
= new_cso
;
1091 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1092 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1093 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1097 * Gallium CSO for rasterizer state.
1099 struct iris_rasterizer_state
{
1100 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1101 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1102 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1103 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1104 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1106 uint8_t num_clip_plane_consts
;
1107 bool clip_halfz
; /* for CC_VIEWPORT */
1108 bool depth_clip_near
; /* for CC_VIEWPORT */
1109 bool depth_clip_far
; /* for CC_VIEWPORT */
1110 bool flatshade
; /* for shader state */
1111 bool flatshade_first
; /* for stream output */
1112 bool clamp_fragment_color
; /* for shader state */
1113 bool light_twoside
; /* for shader state */
1114 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1115 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1116 bool line_stipple_enable
;
1117 bool poly_stipple_enable
;
1119 bool force_persample_interp
;
1120 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1121 uint16_t sprite_coord_enable
;
1125 get_line_width(const struct pipe_rasterizer_state
*state
)
1127 float line_width
= state
->line_width
;
1129 /* From the OpenGL 4.4 spec:
1131 * "The actual width of non-antialiased lines is determined by rounding
1132 * the supplied width to the nearest integer, then clamping it to the
1133 * implementation-dependent maximum non-antialiased line width."
1135 if (!state
->multisample
&& !state
->line_smooth
)
1136 line_width
= roundf(state
->line_width
);
1138 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1139 /* For 1 pixel line thickness or less, the general anti-aliasing
1140 * algorithm gives up, and a garbage line is generated. Setting a
1141 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1142 * (one-pixel-wide), non-antialiased lines.
1144 * Lines rendered with zero Line Width are rasterized using the
1145 * "Grid Intersection Quantization" rules as specified by the
1146 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1155 * The pipe->create_rasterizer_state() driver hook.
1158 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1159 const struct pipe_rasterizer_state
*state
)
1161 struct iris_rasterizer_state
*cso
=
1162 malloc(sizeof(struct iris_rasterizer_state
));
1164 cso
->multisample
= state
->multisample
;
1165 cso
->force_persample_interp
= state
->force_persample_interp
;
1166 cso
->clip_halfz
= state
->clip_halfz
;
1167 cso
->depth_clip_near
= state
->depth_clip_near
;
1168 cso
->depth_clip_far
= state
->depth_clip_far
;
1169 cso
->flatshade
= state
->flatshade
;
1170 cso
->flatshade_first
= state
->flatshade_first
;
1171 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1172 cso
->light_twoside
= state
->light_twoside
;
1173 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1174 cso
->half_pixel_center
= state
->half_pixel_center
;
1175 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1176 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1177 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1178 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1180 if (state
->clip_plane_enable
!= 0)
1181 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1183 cso
->num_clip_plane_consts
= 0;
1185 float line_width
= get_line_width(state
);
1187 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1188 sf
.StatisticsEnable
= true;
1189 sf
.ViewportTransformEnable
= true;
1190 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1191 sf
.LineEndCapAntialiasingRegionWidth
=
1192 state
->line_smooth
? _10pixels
: _05pixels
;
1193 sf
.LastPixelEnable
= state
->line_last_pixel
;
1194 sf
.LineWidth
= line_width
;
1195 sf
.SmoothPointEnable
= (state
->point_smooth
|| state
->multisample
) &&
1196 !state
->point_quad_rasterization
;
1197 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1198 sf
.PointWidth
= state
->point_size
;
1200 if (state
->flatshade_first
) {
1201 sf
.TriangleFanProvokingVertexSelect
= 1;
1203 sf
.TriangleStripListProvokingVertexSelect
= 2;
1204 sf
.TriangleFanProvokingVertexSelect
= 2;
1205 sf
.LineStripListProvokingVertexSelect
= 1;
1209 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1210 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1211 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1212 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1213 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1214 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1215 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1216 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1217 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1218 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1219 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1220 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1221 rr
.SmoothPointEnable
= state
->point_smooth
;
1222 rr
.AntialiasingEnable
= state
->line_smooth
;
1223 rr
.ScissorRectangleEnable
= state
->scissor
;
1225 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1226 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1228 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1230 /* TODO: ConservativeRasterizationEnable */
1233 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1234 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1235 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1237 cl
.EarlyCullEnable
= true;
1238 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1239 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1240 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1241 cl
.GuardbandClipTestEnable
= true;
1242 cl
.ClipEnable
= true;
1243 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
1244 cl
.MinimumPointWidth
= 0.125;
1245 cl
.MaximumPointWidth
= 255.875;
1247 if (state
->flatshade_first
) {
1248 cl
.TriangleFanProvokingVertexSelect
= 1;
1250 cl
.TriangleStripListProvokingVertexSelect
= 2;
1251 cl
.TriangleFanProvokingVertexSelect
= 2;
1252 cl
.LineStripListProvokingVertexSelect
= 1;
1256 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1257 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1258 * filled in at draw time from the FS program.
1260 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1261 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1262 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1263 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1264 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1267 /* Remap from 0..255 back to 1..256 */
1268 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1270 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1271 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1272 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1273 line
.LineStippleRepeatCount
= line_stipple_factor
;
1280 * The pipe->bind_rasterizer_state() driver hook.
1282 * Bind a rasterizer CSO and flag related dirty bits.
1285 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1287 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1288 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1289 struct iris_rasterizer_state
*new_cso
= state
;
1292 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1293 if (cso_changed_memcmp(line_stipple
))
1294 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1296 if (cso_changed(half_pixel_center
))
1297 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1299 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1300 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1302 if (cso_changed(rasterizer_discard
))
1303 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1305 if (cso_changed(flatshade_first
))
1306 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1308 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1309 cso_changed(clip_halfz
))
1310 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1312 if (cso_changed(sprite_coord_enable
) ||
1313 cso_changed(sprite_coord_mode
) ||
1314 cso_changed(light_twoside
))
1315 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1318 ice
->state
.cso_rast
= new_cso
;
1319 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1320 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1321 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1325 * Return true if the given wrap mode requires the border color to exist.
1327 * (We can skip uploading it if the sampler isn't going to use it.)
1330 wrap_mode_needs_border_color(unsigned wrap_mode
)
1332 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1336 * Gallium CSO for sampler state.
1338 struct iris_sampler_state
{
1339 union pipe_color_union border_color
;
1340 bool needs_border_color
;
1342 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1346 * The pipe->create_sampler_state() driver hook.
1348 * We fill out SAMPLER_STATE (except for the border color pointer), and
1349 * store that on the CPU. It doesn't make sense to upload it to a GPU
1350 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1351 * all bound sampler states to be in contiguous memor.
1354 iris_create_sampler_state(struct pipe_context
*ctx
,
1355 const struct pipe_sampler_state
*state
)
1357 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1362 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1363 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1365 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1366 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1367 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1369 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1371 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1372 wrap_mode_needs_border_color(wrap_t
) ||
1373 wrap_mode_needs_border_color(wrap_r
);
1375 float min_lod
= state
->min_lod
;
1376 unsigned mag_img_filter
= state
->mag_img_filter
;
1378 // XXX: explain this code ported from ilo...I don't get it at all...
1379 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1380 state
->min_lod
> 0.0f
) {
1382 mag_img_filter
= state
->min_img_filter
;
1385 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1386 samp
.TCXAddressControlMode
= wrap_s
;
1387 samp
.TCYAddressControlMode
= wrap_t
;
1388 samp
.TCZAddressControlMode
= wrap_r
;
1389 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1390 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1391 samp
.MinModeFilter
= state
->min_img_filter
;
1392 samp
.MagModeFilter
= mag_img_filter
;
1393 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1394 samp
.MaximumAnisotropy
= RATIO21
;
1396 if (state
->max_anisotropy
>= 2) {
1397 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1398 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1399 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1402 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1403 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1405 samp
.MaximumAnisotropy
=
1406 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1409 /* Set address rounding bits if not using nearest filtering. */
1410 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1411 samp
.UAddressMinFilterRoundingEnable
= true;
1412 samp
.VAddressMinFilterRoundingEnable
= true;
1413 samp
.RAddressMinFilterRoundingEnable
= true;
1416 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1417 samp
.UAddressMagFilterRoundingEnable
= true;
1418 samp
.VAddressMagFilterRoundingEnable
= true;
1419 samp
.RAddressMagFilterRoundingEnable
= true;
1422 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1423 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1425 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1427 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1428 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1429 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1430 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1432 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1439 * The pipe->bind_sampler_states() driver hook.
1441 * Now that we know all the sampler states, we upload them all into a
1442 * contiguous area of GPU memory, for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1443 * We also fill out the border color state pointers at this point.
1445 * We could defer this work to draw time, but we assume that binding
1446 * will be less frequent than drawing.
1448 // XXX: this may be a bad idea, need to make sure that st/mesa calls us
1449 // XXX: with the complete set of shaders. If it makes multiple calls to
1450 // XXX: things one at a time, we could waste a lot of time assembling things.
1451 // XXX: it doesn't even BUY us anything to do it here, because we only flag
1452 // XXX: IRIS_DIRTY_SAMPLER_STATE when this is called...
1454 iris_bind_sampler_states(struct pipe_context
*ctx
,
1455 enum pipe_shader_type p_stage
,
1456 unsigned start
, unsigned count
,
1459 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1460 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1461 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1463 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1465 for (int i
= 0; i
< count
; i
++) {
1466 shs
->samplers
[start
+ i
] = states
[i
];
1469 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1470 * in the dynamic state memory zone, so we can point to it via the
1471 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1474 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
,
1475 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
1479 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1480 shs
->sampler_table
.offset
+=
1481 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1483 /* Make sure all land in the same BO */
1484 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1486 for (int i
= 0; i
< count
; i
++) {
1487 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1490 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1491 } else if (!state
->needs_border_color
) {
1492 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1494 ice
->state
.need_border_colors
= true;
1496 /* Stream out the border color and merge the pointer. */
1498 iris_upload_border_color(ice
, &state
->border_color
);
1500 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1501 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1502 dyns
.BorderColorPointer
= offset
;
1505 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1506 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1509 map
+= GENX(SAMPLER_STATE_length
);
1512 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1515 static enum isl_channel_select
1516 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1519 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1520 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1521 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1522 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1523 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1524 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1525 default: unreachable("invalid swizzle");
1530 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1533 enum isl_format format
,
1537 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1538 const unsigned cpp
= format
== ISL_FORMAT_RAW
? 1 : fmtl
->bpb
/ 8;
1540 /* The ARB_texture_buffer_specification says:
1542 * "The number of texels in the buffer texture's texel array is given by
1544 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1546 * where <buffer_size> is the size of the buffer object, in basic
1547 * machine units and <components> and <base_type> are the element count
1548 * and base data type for elements, as specified in Table X.1. The
1549 * number of texels in the texel array is then clamped to the
1550 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1552 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1553 * so that when ISL divides by stride to obtain the number of texels, that
1554 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1556 unsigned final_size
=
1557 MIN3(size
, bo
->size
- offset
, IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1559 isl_buffer_fill_state(isl_dev
, map
,
1560 .address
= bo
->gtt_offset
+ offset
,
1561 .size_B
= final_size
,
1567 #define SURFACE_STATE_ALIGNMENT 64
1570 * Allocate several contiguous SURFACE_STATE structures, one for each
1571 * supported auxiliary surface mode.
1574 alloc_surface_states(struct u_upload_mgr
*mgr
,
1575 struct iris_state_ref
*ref
,
1576 unsigned aux_usages
)
1578 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
1580 /* If this changes, update this to explicitly align pointers */
1581 STATIC_ASSERT(surf_size
== SURFACE_STATE_ALIGNMENT
);
1583 assert(aux_usages
!= 0);
1586 upload_state(mgr
, ref
, util_bitcount(aux_usages
) * surf_size
,
1587 SURFACE_STATE_ALIGNMENT
);
1589 ref
->offset
+= iris_bo_offset_from_base_address(iris_resource_bo(ref
->res
));
1595 fill_surface_state(struct isl_device
*isl_dev
,
1597 struct iris_resource
*res
,
1598 struct isl_view
*view
,
1601 struct isl_surf_fill_state_info f
= {
1604 .mocs
= mocs(res
->bo
),
1605 .address
= res
->bo
->gtt_offset
,
1608 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1609 f
.aux_surf
= &res
->aux
.surf
;
1610 f
.aux_usage
= aux_usage
;
1611 f
.aux_address
= res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
;
1615 isl_surf_fill_state_s(isl_dev
, map
, &f
);
1619 * The pipe->create_sampler_view() driver hook.
1621 static struct pipe_sampler_view
*
1622 iris_create_sampler_view(struct pipe_context
*ctx
,
1623 struct pipe_resource
*tex
,
1624 const struct pipe_sampler_view
*tmpl
)
1626 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1627 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1628 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1629 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1634 /* initialize base object */
1636 isv
->base
.context
= ctx
;
1637 isv
->base
.texture
= NULL
;
1638 pipe_reference_init(&isv
->base
.reference
, 1);
1639 pipe_resource_reference(&isv
->base
.texture
, tex
);
1641 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1642 struct iris_resource
*zres
, *sres
;
1643 const struct util_format_description
*desc
=
1644 util_format_description(tmpl
->format
);
1646 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1648 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1651 isv
->res
= (struct iris_resource
*) tex
;
1653 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1654 &isv
->surface_state
,
1655 isv
->res
->aux
.possible_usages
);
1659 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1661 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1662 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1663 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1665 const struct iris_format_info fmt
=
1666 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1668 isv
->view
= (struct isl_view
) {
1670 .swizzle
= (struct isl_swizzle
) {
1671 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1672 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1673 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1674 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1679 /* Fill out SURFACE_STATE for this view. */
1680 if (tmpl
->target
!= PIPE_BUFFER
) {
1681 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1682 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1683 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1684 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1685 isv
->view
.array_len
=
1686 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1688 unsigned aux_modes
= isv
->res
->aux
.possible_usages
;
1690 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1692 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->view
,
1695 map
+= SURFACE_STATE_ALIGNMENT
;
1698 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
->bo
, map
,
1699 isv
->view
.format
, tmpl
->u
.buf
.offset
,
1707 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1708 struct pipe_sampler_view
*state
)
1710 struct iris_sampler_view
*isv
= (void *) state
;
1711 pipe_resource_reference(&state
->texture
, NULL
);
1712 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1717 * The pipe->create_surface() driver hook.
1719 * In Gallium nomenclature, "surfaces" are a view of a resource that
1720 * can be bound as a render target or depth/stencil buffer.
1722 static struct pipe_surface
*
1723 iris_create_surface(struct pipe_context
*ctx
,
1724 struct pipe_resource
*tex
,
1725 const struct pipe_surface
*tmpl
)
1727 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1728 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1729 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1730 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1731 struct pipe_surface
*psurf
= &surf
->base
;
1732 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1737 pipe_reference_init(&psurf
->reference
, 1);
1738 pipe_resource_reference(&psurf
->texture
, tex
);
1739 psurf
->context
= ctx
;
1740 psurf
->format
= tmpl
->format
;
1741 psurf
->width
= tex
->width0
;
1742 psurf
->height
= tex
->height0
;
1743 psurf
->texture
= tex
;
1744 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1745 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1746 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1748 isl_surf_usage_flags_t usage
= 0;
1750 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1751 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1752 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1754 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1756 const struct iris_format_info fmt
=
1757 iris_format_for_usage(devinfo
, psurf
->format
, usage
);
1759 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1760 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1761 /* Framebuffer validation will reject this invalid case, but it
1762 * hasn't had the opportunity yet. In the meantime, we need to
1763 * avoid hitting ISL asserts about unsupported formats below.
1769 surf
->view
= (struct isl_view
) {
1771 .base_level
= tmpl
->u
.tex
.level
,
1773 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1774 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1775 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1779 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1780 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1781 ISL_SURF_USAGE_STENCIL_BIT
))
1785 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1786 &surf
->surface_state
,
1787 res
->aux
.possible_usages
);
1791 unsigned aux_modes
= res
->aux
.possible_usages
;
1793 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1795 fill_surface_state(&screen
->isl_dev
, map
, res
, &surf
->view
, aux_usage
);
1797 map
+= SURFACE_STATE_ALIGNMENT
;
1805 fill_default_image_param(struct brw_image_param
*param
)
1807 memset(param
, 0, sizeof(*param
));
1808 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
1809 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
1810 * detailed explanation of these parameters.
1812 param
->swizzling
[0] = 0xff;
1813 param
->swizzling
[1] = 0xff;
1817 fill_buffer_image_param(struct brw_image_param
*param
,
1818 enum pipe_format pfmt
,
1821 const unsigned cpp
= util_format_get_blocksize(pfmt
);
1823 fill_default_image_param(param
);
1824 param
->size
[0] = size
/ cpp
;
1825 param
->stride
[0] = cpp
;
1828 #define isl_surf_fill_image_param(x, ...)
1829 #define fill_default_image_param(x, ...)
1830 #define fill_buffer_image_param(x, ...)
1834 * The pipe->set_shader_images() driver hook.
1837 iris_set_shader_images(struct pipe_context
*ctx
,
1838 enum pipe_shader_type p_stage
,
1839 unsigned start_slot
, unsigned count
,
1840 const struct pipe_image_view
*p_images
)
1842 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1843 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1844 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1845 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1846 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1848 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
1850 for (unsigned i
= 0; i
< count
; i
++) {
1851 if (p_images
&& p_images
[i
].resource
) {
1852 const struct pipe_image_view
*img
= &p_images
[i
];
1853 struct iris_resource
*res
= (void *) img
->resource
;
1854 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, &res
->base
);
1856 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
1858 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
1860 // XXX: these are not retained forever, use a separate uploader?
1862 alloc_surface_states(ice
->state
.surface_uploader
,
1863 &shs
->image
[start_slot
+ i
].surface_state
,
1864 1 << ISL_AUX_USAGE_NONE
);
1865 if (!unlikely(map
)) {
1866 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1870 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1871 enum isl_format isl_fmt
=
1872 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
1874 bool untyped_fallback
= false;
1876 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
1877 /* On Gen8, try to use typed surfaces reads (which support a
1878 * limited number of formats), and if not possible, fall back
1881 untyped_fallback
= GEN_GEN
== 8 &&
1882 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
);
1884 if (untyped_fallback
)
1885 isl_fmt
= ISL_FORMAT_RAW
;
1887 isl_fmt
= isl_lower_storage_image_format(devinfo
, isl_fmt
);
1890 shs
->image
[start_slot
+ i
].access
= img
->shader_access
;
1892 if (res
->base
.target
!= PIPE_BUFFER
) {
1893 struct isl_view view
= {
1895 .base_level
= img
->u
.tex
.level
,
1897 .base_array_layer
= img
->u
.tex
.first_layer
,
1898 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
1899 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1903 if (untyped_fallback
) {
1904 fill_buffer_surface_state(&screen
->isl_dev
, res
->bo
, map
,
1905 isl_fmt
, 0, res
->bo
->size
);
1907 /* Images don't support compression */
1908 unsigned aux_modes
= 1 << ISL_AUX_USAGE_NONE
;
1910 enum isl_aux_usage usage
= u_bit_scan(&aux_modes
);
1912 fill_surface_state(&screen
->isl_dev
, map
, res
, &view
, usage
);
1914 map
+= SURFACE_STATE_ALIGNMENT
;
1918 isl_surf_fill_image_param(&screen
->isl_dev
,
1919 &shs
->image
[start_slot
+ i
].param
,
1922 fill_buffer_surface_state(&screen
->isl_dev
, res
->bo
, map
,
1923 isl_fmt
, img
->u
.buf
.offset
,
1925 fill_buffer_image_param(&shs
->image
[start_slot
+ i
].param
,
1926 img
->format
, img
->u
.buf
.size
);
1929 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1930 pipe_resource_reference(&shs
->image
[start_slot
+ i
].surface_state
.res
,
1932 fill_default_image_param(&shs
->image
[start_slot
+ i
].param
);
1936 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1938 /* Broadwell also needs brw_image_params re-uploaded */
1940 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
1941 shs
->cbuf0_needs_upload
= true;
1947 * The pipe->set_sampler_views() driver hook.
1950 iris_set_sampler_views(struct pipe_context
*ctx
,
1951 enum pipe_shader_type p_stage
,
1952 unsigned start
, unsigned count
,
1953 struct pipe_sampler_view
**views
)
1955 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1956 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1957 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1959 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
1961 for (unsigned i
= 0; i
< count
; i
++) {
1962 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1963 &shs
->textures
[start
+ i
], views
[i
]);
1964 struct iris_sampler_view
*view
= (void *) views
[i
];
1966 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
1967 shs
->bound_sampler_views
|= 1 << (start
+ i
);
1971 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
1975 * The pipe->set_tess_state() driver hook.
1978 iris_set_tess_state(struct pipe_context
*ctx
,
1979 const float default_outer_level
[4],
1980 const float default_inner_level
[2])
1982 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1984 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
1985 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
1987 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
1991 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1993 struct iris_surface
*surf
= (void *) p_surf
;
1994 pipe_resource_reference(&p_surf
->texture
, NULL
);
1995 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2000 iris_set_clip_state(struct pipe_context
*ctx
,
2001 const struct pipe_clip_state
*state
)
2003 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2004 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
2006 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
2008 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
;
2009 shs
->cbuf0_needs_upload
= true;
2013 * The pipe->set_polygon_stipple() driver hook.
2016 iris_set_polygon_stipple(struct pipe_context
*ctx
,
2017 const struct pipe_poly_stipple
*state
)
2019 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2020 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
2021 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
2025 * The pipe->set_sample_mask() driver hook.
2028 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2030 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2032 /* We only support 16x MSAA, so we have 16 bits of sample maks.
2033 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
2035 ice
->state
.sample_mask
= sample_mask
& 0xffff;
2036 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
2040 * The pipe->set_scissor_states() driver hook.
2042 * This corresponds to our SCISSOR_RECT state structures. It's an
2043 * exact match, so we just store them, and memcpy them out later.
2046 iris_set_scissor_states(struct pipe_context
*ctx
,
2047 unsigned start_slot
,
2048 unsigned num_scissors
,
2049 const struct pipe_scissor_state
*rects
)
2051 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2053 for (unsigned i
= 0; i
< num_scissors
; i
++) {
2054 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
2055 /* If the scissor was out of bounds and got clamped to 0 width/height
2056 * at the bounds, the subtraction of 1 from maximums could produce a
2057 * negative number and thus not clip anything. Instead, just provide
2058 * a min > max scissor inside the bounds, which produces the expected
2061 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2062 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
2065 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2066 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
2067 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
2072 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
2076 * The pipe->set_stencil_ref() driver hook.
2078 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
2081 iris_set_stencil_ref(struct pipe_context
*ctx
,
2082 const struct pipe_stencil_ref
*state
)
2084 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2085 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2087 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2089 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2093 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2095 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2099 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2100 float m00
, float m11
, float m30
, float m31
,
2101 float *xmin
, float *xmax
,
2102 float *ymin
, float *ymax
)
2104 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2105 * Strips and Fans documentation:
2107 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2108 * fixed-point "guardband" range supported by the rasterization hardware"
2112 * "In almost all circumstances, if an object’s vertices are actually
2113 * modified by this clamping (i.e., had X or Y coordinates outside of
2114 * the guardband extent the rendered object will not match the intended
2115 * result. Therefore software should take steps to ensure that this does
2116 * not happen - e.g., by clipping objects such that they do not exceed
2117 * these limits after the Drawing Rectangle is applied."
2119 * I believe the fundamental restriction is that the rasterizer (in
2120 * the SF/WM stages) have a limit on the number of pixels that can be
2121 * rasterized. We need to ensure any coordinates beyond the rasterizer
2122 * limit are handled by the clipper. So effectively that limit becomes
2123 * the clipper's guardband size.
2125 * It goes on to say:
2127 * "In addition, in order to be correctly rendered, objects must have a
2128 * screenspace bounding box not exceeding 8K in the X or Y direction.
2129 * This additional restriction must also be comprehended by software,
2130 * i.e., enforced by use of clipping."
2132 * This makes no sense. Gen7+ hardware supports 16K render targets,
2133 * and you definitely need to be able to draw polygons that fill the
2134 * surface. Our assumption is that the rasterizer was limited to 8K
2135 * on Sandybridge, which only supports 8K surfaces, and it was actually
2136 * increased to 16K on Ivybridge and later.
2138 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2140 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2142 if (m00
!= 0 && m11
!= 0) {
2143 /* First, we compute the screen-space render area */
2144 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2145 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2146 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2147 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2149 /* We want the guardband to be centered on that */
2150 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2151 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2152 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2153 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2155 /* Now we need it in native device coordinates */
2156 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2157 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2158 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2159 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2161 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2162 * flipped upside-down. X should be fine though.
2164 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2165 *xmin
= ndc_gb_xmin
;
2166 *xmax
= ndc_gb_xmax
;
2167 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2168 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2170 /* The viewport scales to 0, so nothing will be rendered. */
2179 * The pipe->set_viewport_states() driver hook.
2181 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2182 * the guardband yet, as we need the framebuffer dimensions, but we can
2183 * at least fill out the rest.
2186 iris_set_viewport_states(struct pipe_context
*ctx
,
2187 unsigned start_slot
,
2189 const struct pipe_viewport_state
*states
)
2191 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2193 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2195 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2197 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2198 !ice
->state
.cso_rast
->depth_clip_far
))
2199 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2203 * The pipe->set_framebuffer_state() driver hook.
2205 * Sets the current draw FBO, including color render targets, depth,
2206 * and stencil buffers.
2209 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2210 const struct pipe_framebuffer_state
*state
)
2212 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2213 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2214 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2215 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2216 struct iris_resource
*zres
;
2217 struct iris_resource
*stencil_res
;
2219 unsigned samples
= util_framebuffer_get_num_samples(state
);
2220 unsigned layers
= util_framebuffer_get_num_layers(state
);
2222 if (cso
->samples
!= samples
) {
2223 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2226 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2227 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2230 if ((cso
->layers
== 0) != (layers
== 0)) {
2231 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2234 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2235 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2238 util_copy_framebuffer_state(cso
, state
);
2239 cso
->samples
= samples
;
2240 cso
->layers
= layers
;
2242 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2244 struct isl_view view
= {
2247 .base_array_layer
= 0,
2249 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2252 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
2255 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2258 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2259 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2261 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2264 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2266 info
.depth_surf
= &zres
->surf
;
2267 info
.depth_address
= zres
->bo
->gtt_offset
;
2268 info
.mocs
= mocs(zres
->bo
);
2270 view
.format
= zres
->surf
.format
;
2274 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2275 info
.stencil_surf
= &stencil_res
->surf
;
2276 info
.stencil_address
= stencil_res
->bo
->gtt_offset
;
2278 view
.format
= stencil_res
->surf
.format
;
2279 info
.mocs
= mocs(stencil_res
->bo
);
2284 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2286 /* Make a null surface for unbound buffers */
2287 void *null_surf_map
=
2288 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2289 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2290 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2291 isl_extent3d(MAX2(cso
->width
, 1),
2292 MAX2(cso
->height
, 1),
2293 cso
->layers
? cso
->layers
: 1));
2294 ice
->state
.null_fb
.offset
+=
2295 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2297 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2299 /* Render target change */
2300 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2302 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2305 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2306 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2308 /* The PIPE_CONTROL command description says:
2310 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2311 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2312 * Target Cache Flush by enabling this bit. When render target flush
2313 * is set due to new association of BTI, PS Scoreboard Stall bit must
2314 * be set in this packet."
2316 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2317 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2318 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2319 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2324 upload_ubo_surf_state(struct iris_context
*ice
,
2325 struct iris_const_buffer
*cbuf
,
2326 unsigned buffer_size
)
2328 struct pipe_context
*ctx
= &ice
->ctx
;
2329 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
2331 // XXX: these are not retained forever, use a separate uploader?
2333 upload_state(ice
->state
.surface_uploader
, &cbuf
->surface_state
,
2334 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2335 if (!unlikely(map
)) {
2336 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2340 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2341 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state
.res
);
2342 cbuf
->surface_state
.offset
+= iris_bo_offset_from_base_address(surf_bo
);
2344 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2345 .address
= res
->bo
->gtt_offset
+ cbuf
->data
.offset
,
2346 .size_B
= MIN2(buffer_size
,
2347 res
->bo
->size
- cbuf
->data
.offset
),
2348 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
2350 .mocs
= mocs(res
->bo
))
2354 * The pipe->set_constant_buffer() driver hook.
2356 * This uploads any constant data in user buffers, and references
2357 * any UBO resources containing constant data.
2360 iris_set_constant_buffer(struct pipe_context
*ctx
,
2361 enum pipe_shader_type p_stage
, unsigned index
,
2362 const struct pipe_constant_buffer
*input
)
2364 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2365 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2366 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2367 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
2369 if (input
&& input
->buffer
) {
2372 pipe_resource_reference(&cbuf
->data
.res
, input
->buffer
);
2373 cbuf
->data
.offset
= input
->buffer_offset
;
2375 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2376 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2378 upload_ubo_surf_state(ice
, cbuf
, input
->buffer_size
);
2380 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2381 pipe_resource_reference(&cbuf
->surface_state
.res
, NULL
);
2386 memcpy(&shs
->cbuf0
, input
, sizeof(shs
->cbuf0
));
2388 memset(&shs
->cbuf0
, 0, sizeof(shs
->cbuf0
));
2390 shs
->cbuf0_needs_upload
= true;
2393 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2394 // XXX: maybe not necessary all the time...?
2395 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2396 // XXX: pull model we may need actual new bindings...
2397 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2401 upload_uniforms(struct iris_context
*ice
,
2402 gl_shader_stage stage
)
2404 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2405 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
2406 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2408 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t) +
2409 shs
->cbuf0
.buffer_size
;
2411 if (upload_size
== 0)
2415 upload_state(ice
->ctx
.const_uploader
, &cbuf
->data
, upload_size
, 64);
2417 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2418 uint32_t sysval
= shader
->system_values
[i
];
2421 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
2422 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
2423 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
2424 struct brw_image_param
*param
= &shs
->image
[img
].param
;
2426 assert(offset
< sizeof(struct brw_image_param
));
2427 value
= ((uint32_t *) param
)[offset
];
2428 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
2430 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2431 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2432 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2433 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2434 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
2435 if (stage
== MESA_SHADER_TESS_CTRL
) {
2436 value
= ice
->state
.vertices_per_patch
;
2438 assert(stage
== MESA_SHADER_TESS_EVAL
);
2439 const struct shader_info
*tcs_info
=
2440 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
2443 value
= tcs_info
->tess
.tcs_vertices_out
;
2446 assert(!"unhandled system value");
2452 if (shs
->cbuf0
.user_buffer
) {
2453 memcpy(map
, shs
->cbuf0
.user_buffer
, shs
->cbuf0
.buffer_size
);
2456 upload_ubo_surf_state(ice
, cbuf
, upload_size
);
2460 * The pipe->set_shader_buffers() driver hook.
2462 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2463 * SURFACE_STATE here, as the buffer offset may change each time.
2466 iris_set_shader_buffers(struct pipe_context
*ctx
,
2467 enum pipe_shader_type p_stage
,
2468 unsigned start_slot
, unsigned count
,
2469 const struct pipe_shader_buffer
*buffers
)
2471 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2472 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2473 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2474 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2476 for (unsigned i
= 0; i
< count
; i
++) {
2477 if (buffers
&& buffers
[i
].buffer
) {
2478 const struct pipe_shader_buffer
*buffer
= &buffers
[i
];
2479 struct iris_resource
*res
= (void *) buffer
->buffer
;
2480 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], &res
->base
);
2482 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2484 // XXX: these are not retained forever, use a separate uploader?
2486 upload_state(ice
->state
.surface_uploader
,
2487 &shs
->ssbo_surface_state
[start_slot
+ i
],
2488 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2489 if (!unlikely(map
)) {
2490 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2494 struct iris_bo
*surf_state_bo
=
2495 iris_resource_bo(shs
->ssbo_surface_state
[start_slot
+ i
].res
);
2496 shs
->ssbo_surface_state
[start_slot
+ i
].offset
+=
2497 iris_bo_offset_from_base_address(surf_state_bo
);
2499 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2501 res
->bo
->gtt_offset
+ buffer
->buffer_offset
,
2503 MIN2(buffer
->buffer_size
,
2504 res
->bo
->size
- buffer
->buffer_offset
),
2505 .format
= ISL_FORMAT_RAW
,
2507 .mocs
= mocs(res
->bo
));
2509 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2510 pipe_resource_reference(&shs
->ssbo_surface_state
[start_slot
+ i
].res
,
2515 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2519 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2525 * The pipe->set_vertex_buffers() driver hook.
2527 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2530 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2531 unsigned start_slot
, unsigned count
,
2532 const struct pipe_vertex_buffer
*buffers
)
2534 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2535 struct iris_genx_state
*genx
= ice
->state
.genx
;
2537 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
2539 for (unsigned i
= 0; i
< count
; i
++) {
2540 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
2541 struct iris_vertex_buffer_state
*state
=
2542 &genx
->vertex_buffers
[start_slot
+ i
];
2545 pipe_resource_reference(&state
->resource
, NULL
);
2549 assert(!buffer
->is_user_buffer
);
2551 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
2552 struct iris_resource
*res
= (void *) state
->resource
;
2555 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
2556 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2559 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
2560 vb
.VertexBufferIndex
= start_slot
+ i
;
2561 vb
.AddressModifyEnable
= true;
2562 vb
.BufferPitch
= buffer
->stride
;
2564 vb
.BufferSize
= res
->bo
->size
;
2565 vb
.BufferStartingAddress
=
2566 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
2567 vb
.MOCS
= mocs(res
->bo
);
2569 vb
.NullVertexBuffer
= true;
2574 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2578 * Gallium CSO for vertex elements.
2580 struct iris_vertex_element_state
{
2581 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2582 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2587 * The pipe->create_vertex_elements() driver hook.
2589 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2590 * and 3DSTATE_VF_INSTANCING commands. SGVs are handled at draw time.
2593 iris_create_vertex_elements(struct pipe_context
*ctx
,
2595 const struct pipe_vertex_element
*state
)
2597 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2598 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2599 struct iris_vertex_element_state
*cso
=
2600 malloc(sizeof(struct iris_vertex_element_state
));
2605 * - create edge flag one
2607 * - if those are necessary, use count + 1/2/3... OR in the length
2609 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2611 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2614 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2615 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2618 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2620 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2621 ve
.Component0Control
= VFCOMP_STORE_0
;
2622 ve
.Component1Control
= VFCOMP_STORE_0
;
2623 ve
.Component2Control
= VFCOMP_STORE_0
;
2624 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2627 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2631 for (int i
= 0; i
< count
; i
++) {
2632 const struct iris_format_info fmt
=
2633 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2634 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2635 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2637 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2638 case 0: comp
[0] = VFCOMP_STORE_0
;
2639 case 1: comp
[1] = VFCOMP_STORE_0
;
2640 case 2: comp
[2] = VFCOMP_STORE_0
;
2642 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2643 : VFCOMP_STORE_1_FP
;
2646 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2647 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2649 ve
.SourceElementOffset
= state
[i
].src_offset
;
2650 ve
.SourceElementFormat
= fmt
.fmt
;
2651 ve
.Component0Control
= comp
[0];
2652 ve
.Component1Control
= comp
[1];
2653 ve
.Component2Control
= comp
[2];
2654 ve
.Component3Control
= comp
[3];
2657 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2658 vi
.VertexElementIndex
= i
;
2659 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2660 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2663 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2664 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2671 * The pipe->bind_vertex_elements_state() driver hook.
2674 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2676 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2677 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2678 struct iris_vertex_element_state
*new_cso
= state
;
2680 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2681 * we need to re-emit it to ensure we're overriding the right one.
2683 if (new_cso
&& cso_changed(count
))
2684 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2686 ice
->state
.cso_vertex_elements
= state
;
2687 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2691 * The pipe->create_stream_output_target() driver hook.
2693 * "Target" here refers to a destination buffer. We translate this into
2694 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2695 * know which buffer this represents, or whether we ought to zero the
2696 * write-offsets, or append. Those are handled in the set() hook.
2698 static struct pipe_stream_output_target
*
2699 iris_create_stream_output_target(struct pipe_context
*ctx
,
2700 struct pipe_resource
*p_res
,
2701 unsigned buffer_offset
,
2702 unsigned buffer_size
)
2704 struct iris_resource
*res
= (void *) p_res
;
2705 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2709 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
2711 pipe_reference_init(&cso
->base
.reference
, 1);
2712 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
2713 cso
->base
.buffer_offset
= buffer_offset
;
2714 cso
->base
.buffer_size
= buffer_size
;
2715 cso
->base
.context
= ctx
;
2717 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
2723 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2724 struct pipe_stream_output_target
*state
)
2726 struct iris_stream_output_target
*cso
= (void *) state
;
2728 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2729 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2735 * The pipe->set_stream_output_targets() driver hook.
2737 * At this point, we know which targets are bound to a particular index,
2738 * and also whether we want to append or start over. We can finish the
2739 * 3DSTATE_SO_BUFFER packets we started earlier.
2742 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2743 unsigned num_targets
,
2744 struct pipe_stream_output_target
**targets
,
2745 const unsigned *offsets
)
2747 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2748 struct iris_genx_state
*genx
= ice
->state
.genx
;
2749 uint32_t *so_buffers
= genx
->so_buffers
;
2751 const bool active
= num_targets
> 0;
2752 if (ice
->state
.streamout_active
!= active
) {
2753 ice
->state
.streamout_active
= active
;
2754 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2756 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
2757 * it's a non-pipelined command. If we're switching streamout on, we
2758 * may have missed emitting it earlier, so do so now. (We're already
2759 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
2762 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
2765 for (int i
= 0; i
< 4; i
++) {
2766 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2767 i
< num_targets
? targets
[i
] : NULL
);
2770 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2774 for (unsigned i
= 0; i
< 4; i
++,
2775 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2777 if (i
>= num_targets
|| !targets
[i
]) {
2778 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
2779 sob
.SOBufferIndex
= i
;
2783 struct iris_stream_output_target
*tgt
= (void *) targets
[i
];
2784 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
2786 /* Note that offsets[i] will either be 0, causing us to zero
2787 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
2788 * "continue appending at the existing offset."
2790 assert(offsets
[i
] == 0 || offsets
[i
] == 0xFFFFFFFF);
2792 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
2793 sob
.SurfaceBaseAddress
=
2794 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
2795 sob
.SOBufferEnable
= true;
2796 sob
.StreamOffsetWriteEnable
= true;
2797 sob
.StreamOutputBufferOffsetAddressEnable
= true;
2798 sob
.MOCS
= mocs(res
->bo
);
2800 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
2802 sob
.SOBufferIndex
= i
;
2803 sob
.StreamOffset
= offsets
[i
];
2804 sob
.StreamOutputBufferOffsetAddress
=
2805 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
2806 tgt
->offset
.offset
);
2810 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
2814 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
2815 * 3DSTATE_STREAMOUT packets.
2817 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
2818 * hardware to record. We can create it entirely based on the shader, with
2819 * no dynamic state dependencies.
2821 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
2822 * state-based settings. We capture the shader-related ones here, and merge
2823 * the rest in at draw time.
2826 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
2827 const struct brw_vue_map
*vue_map
)
2829 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2830 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2831 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2832 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2834 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2836 memset(so_decl
, 0, sizeof(so_decl
));
2838 /* Construct the list of SO_DECLs to be emitted. The formatting of the
2839 * command feels strange -- each dword pair contains a SO_DECL per stream.
2841 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
2842 const struct pipe_stream_output
*output
= &info
->output
[i
];
2843 const int buffer
= output
->output_buffer
;
2844 const int varying
= output
->register_index
;
2845 const unsigned stream_id
= output
->stream
;
2846 assert(stream_id
< MAX_VERTEX_STREAMS
);
2848 buffer_mask
[stream_id
] |= 1 << buffer
;
2850 assert(vue_map
->varying_to_slot
[varying
] >= 0);
2852 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
2853 * array. Instead, it simply increments DstOffset for the following
2854 * input by the number of components that should be skipped.
2856 * Our hardware is unusual in that it requires us to program SO_DECLs
2857 * for fake "hole" components, rather than simply taking the offset
2858 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
2859 * program as many size = 4 holes as we can, then a final hole to
2860 * accommodate the final 1, 2, or 3 remaining.
2862 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
2864 while (skip_components
> 0) {
2865 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2867 .OutputBufferSlot
= output
->output_buffer
,
2868 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
2870 skip_components
-= 4;
2873 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
2875 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2876 .OutputBufferSlot
= output
->output_buffer
,
2877 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
2879 ((1 << output
->num_components
) - 1) << output
->start_component
,
2882 if (decls
[stream_id
] > max_decls
)
2883 max_decls
= decls
[stream_id
];
2886 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
2887 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
2888 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
2890 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
2891 int urb_entry_read_offset
= 0;
2892 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
2893 urb_entry_read_offset
;
2895 /* We always read the whole vertex. This could be reduced at some
2896 * point by reading less and offsetting the register index in the
2899 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
2900 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
2901 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
2902 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
2903 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
2904 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
2905 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
2906 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
2908 /* Set buffer pitches; 0 means unbound. */
2909 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
2910 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
2911 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
2912 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
2915 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
2916 list
.DWordLength
= 3 + 2 * max_decls
- 2;
2917 list
.StreamtoBufferSelects0
= buffer_mask
[0];
2918 list
.StreamtoBufferSelects1
= buffer_mask
[1];
2919 list
.StreamtoBufferSelects2
= buffer_mask
[2];
2920 list
.StreamtoBufferSelects3
= buffer_mask
[3];
2921 list
.NumEntries0
= decls
[0];
2922 list
.NumEntries1
= decls
[1];
2923 list
.NumEntries2
= decls
[2];
2924 list
.NumEntries3
= decls
[3];
2927 for (int i
= 0; i
< max_decls
; i
++) {
2928 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
2929 entry
.Stream0Decl
= so_decl
[0][i
];
2930 entry
.Stream1Decl
= so_decl
[1][i
];
2931 entry
.Stream2Decl
= so_decl
[2][i
];
2932 entry
.Stream3Decl
= so_decl
[3][i
];
2940 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
2941 const struct brw_vue_map
*last_vue_map
,
2942 bool two_sided_color
,
2943 unsigned *out_offset
,
2944 unsigned *out_length
)
2946 /* The compiler computes the first URB slot without considering COL/BFC
2947 * swizzling (because it doesn't know whether it's enabled), so we need
2948 * to do that here too. This may result in a smaller offset, which
2951 const unsigned first_slot
=
2952 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
2954 /* This becomes the URB read offset (counted in pairs of slots). */
2955 assert(first_slot
% 2 == 0);
2956 *out_offset
= first_slot
/ 2;
2958 /* We need to adjust the inputs read to account for front/back color
2959 * swizzling, as it can make the URB length longer.
2961 for (int c
= 0; c
<= 1; c
++) {
2962 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
2963 /* If two sided color is enabled, the fragment shader's gl_Color
2964 * (COL0) input comes from either the gl_FrontColor (COL0) or
2965 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
2967 if (two_sided_color
)
2968 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2970 /* If front color isn't written, we opt to give them back color
2971 * instead of an undefined value. Switch from COL to BFC.
2973 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
2974 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
2975 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2980 /* Compute the minimum URB Read Length necessary for the FS inputs.
2982 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
2983 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
2985 * "This field should be set to the minimum length required to read the
2986 * maximum source attribute. The maximum source attribute is indicated
2987 * by the maximum value of the enabled Attribute # Source Attribute if
2988 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
2989 * enable is not set.
2990 * read_length = ceiling((max_source_attr + 1) / 2)
2992 * [errata] Corruption/Hang possible if length programmed larger than
2995 * Similar text exists for Ivy Bridge.
2997 * We find the last URB slot that's actually read by the FS.
2999 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
3000 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
3001 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
3004 /* The URB read length is the difference of the two, counted in pairs. */
3005 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
3009 iris_emit_sbe_swiz(struct iris_batch
*batch
,
3010 const struct iris_context
*ice
,
3011 unsigned urb_read_offset
,
3012 unsigned sprite_coord_enables
)
3014 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
3015 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3016 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3017 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
3018 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3020 /* XXX: this should be generated when putting programs in place */
3022 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
3023 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
3024 if (input_index
< 0 || input_index
>= 16)
3027 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
3028 &attr_overrides
[input_index
];
3029 int slot
= vue_map
->varying_to_slot
[fs_attr
];
3031 /* Viewport and Layer are stored in the VUE header. We need to override
3032 * them to zero if earlier stages didn't write them, as GL requires that
3033 * they read back as zero when not explicitly set.
3036 case VARYING_SLOT_VIEWPORT
:
3037 case VARYING_SLOT_LAYER
:
3038 attr
->ComponentOverrideX
= true;
3039 attr
->ComponentOverrideW
= true;
3040 attr
->ConstantSource
= CONST_0000
;
3042 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
3043 attr
->ComponentOverrideY
= true;
3044 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
3045 attr
->ComponentOverrideZ
= true;
3048 case VARYING_SLOT_PRIMITIVE_ID
:
3049 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
3051 attr
->ComponentOverrideX
= true;
3052 attr
->ComponentOverrideY
= true;
3053 attr
->ComponentOverrideZ
= true;
3054 attr
->ComponentOverrideW
= true;
3055 attr
->ConstantSource
= PRIM_ID
;
3063 if (sprite_coord_enables
& (1 << input_index
))
3066 /* If there was only a back color written but not front, use back
3067 * as the color instead of undefined.
3069 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
3070 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
3071 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
3072 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
3074 /* Not written by the previous stage - undefined. */
3076 attr
->ComponentOverrideX
= true;
3077 attr
->ComponentOverrideY
= true;
3078 attr
->ComponentOverrideZ
= true;
3079 attr
->ComponentOverrideW
= true;
3080 attr
->ConstantSource
= CONST_0001_FLOAT
;
3084 /* Compute the location of the attribute relative to the read offset,
3085 * which is counted in 256-bit increments (two 128-bit VUE slots).
3087 const int source_attr
= slot
- 2 * urb_read_offset
;
3088 assert(source_attr
>= 0 && source_attr
<= 32);
3089 attr
->SourceAttribute
= source_attr
;
3091 /* If we are doing two-sided color, and the VUE slot following this one
3092 * represents a back-facing color, then we need to instruct the SF unit
3093 * to do back-facing swizzling.
3095 if (cso_rast
->light_twoside
&&
3096 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3097 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3098 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3099 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3100 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3103 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3104 for (int i
= 0; i
< 16; i
++)
3105 sbes
.Attribute
[i
] = attr_overrides
[i
];
3110 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3111 const struct iris_rasterizer_state
*cso
)
3113 unsigned overrides
= 0;
3115 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
3116 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
3118 for (int i
= 0; i
< 8; i
++) {
3119 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
3120 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
3121 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
3128 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
3130 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3131 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3132 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3133 const struct shader_info
*fs_info
=
3134 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
3136 unsigned urb_read_offset
, urb_read_length
;
3137 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
3138 ice
->shaders
.last_vue_map
,
3139 cso_rast
->light_twoside
,
3140 &urb_read_offset
, &urb_read_length
);
3142 unsigned sprite_coord_overrides
=
3143 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3145 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
3146 sbe
.AttributeSwizzleEnable
= true;
3147 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3148 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3149 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3150 sbe
.VertexURBEntryReadLength
= urb_read_length
;
3151 sbe
.ForceVertexURBEntryReadOffset
= true;
3152 sbe
.ForceVertexURBEntryReadLength
= true;
3153 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3154 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
3156 for (int i
= 0; i
< 32; i
++) {
3157 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3162 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
3165 /* ------------------------------------------------------------------- */
3168 * Populate VS program key fields based on the current state.
3171 iris_populate_vs_key(const struct iris_context
*ice
,
3172 const struct shader_info
*info
,
3173 struct brw_vs_prog_key
*key
)
3175 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3177 if (info
->clip_distance_array_size
== 0 &&
3178 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)))
3179 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3183 * Populate TCS program key fields based on the current state.
3186 iris_populate_tcs_key(const struct iris_context
*ice
,
3187 struct brw_tcs_prog_key
*key
)
3192 * Populate TES program key fields based on the current state.
3195 iris_populate_tes_key(const struct iris_context
*ice
,
3196 struct brw_tes_prog_key
*key
)
3201 * Populate GS program key fields based on the current state.
3204 iris_populate_gs_key(const struct iris_context
*ice
,
3205 struct brw_gs_prog_key
*key
)
3210 * Populate FS program key fields based on the current state.
3213 iris_populate_fs_key(const struct iris_context
*ice
,
3214 struct brw_wm_prog_key
*key
)
3216 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3217 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3218 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3219 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3221 key
->nr_color_regions
= fb
->nr_cbufs
;
3223 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3225 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
3226 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
3228 /* XXX: only bother if COL0/1 are read */
3229 key
->flat_shade
= rast
->flatshade
;
3231 key
->persample_interp
= rast
->force_persample_interp
;
3232 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3234 key
->coherent_fb_fetch
= true;
3236 /* TODO: support key->force_dual_color_blend for Unigine */
3237 /* TODO: Respect glHint for key->high_quality_derivatives */
3241 iris_populate_cs_key(const struct iris_context
*ice
,
3242 struct brw_cs_prog_key
*key
)
3247 KSP(const struct iris_compiled_shader
*shader
)
3249 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3250 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3253 /* Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3254 * prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3255 * this WA on C0 stepping.
3257 * TODO: Fill out SamplerCount for prefetching?
3260 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3261 pkt.KernelStartPointer = KSP(shader); \
3262 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3263 prog_data->binding_table.size_bytes / 4; \
3264 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3266 pkt.DispatchGRFStartRegisterForURBData = \
3267 prog_data->dispatch_grf_start_reg; \
3268 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3269 pkt.prefix##URBEntryReadOffset = 0; \
3271 pkt.StatisticsEnable = true; \
3272 pkt.Enable = true; \
3274 if (prog_data->total_scratch) { \
3275 struct iris_bo *bo = \
3276 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3277 uint32_t scratch_addr = bo->gtt_offset; \
3278 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3279 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3283 * Encode most of 3DSTATE_VS based on the compiled shader.
3286 iris_store_vs_state(struct iris_context
*ice
,
3287 const struct gen_device_info
*devinfo
,
3288 struct iris_compiled_shader
*shader
)
3290 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3291 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3293 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3294 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3295 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3296 vs
.SIMD8DispatchEnable
= true;
3297 vs
.UserClipDistanceCullTestEnableBitmask
=
3298 vue_prog_data
->cull_distance_mask
;
3303 * Encode most of 3DSTATE_HS based on the compiled shader.
3306 iris_store_tcs_state(struct iris_context
*ice
,
3307 const struct gen_device_info
*devinfo
,
3308 struct iris_compiled_shader
*shader
)
3310 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3311 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3312 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3314 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3315 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3317 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3318 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3319 hs
.IncludeVertexHandles
= true;
3324 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3327 iris_store_tes_state(struct iris_context
*ice
,
3328 const struct gen_device_info
*devinfo
,
3329 struct iris_compiled_shader
*shader
)
3331 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3332 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3333 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3335 uint32_t *te_state
= (void *) shader
->derived_data
;
3336 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3338 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3339 te
.Partitioning
= tes_prog_data
->partitioning
;
3340 te
.OutputTopology
= tes_prog_data
->output_topology
;
3341 te
.TEDomain
= tes_prog_data
->domain
;
3343 te
.MaximumTessellationFactorOdd
= 63.0;
3344 te
.MaximumTessellationFactorNotOdd
= 64.0;
3347 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3348 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3350 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3351 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3352 ds
.ComputeWCoordinateEnable
=
3353 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3355 ds
.UserClipDistanceCullTestEnableBitmask
=
3356 vue_prog_data
->cull_distance_mask
;
3362 * Encode most of 3DSTATE_GS based on the compiled shader.
3365 iris_store_gs_state(struct iris_context
*ice
,
3366 const struct gen_device_info
*devinfo
,
3367 struct iris_compiled_shader
*shader
)
3369 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3370 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3371 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3373 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3374 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3376 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3377 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3378 gs
.ControlDataHeaderSize
=
3379 gs_prog_data
->control_data_header_size_hwords
;
3380 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3381 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3382 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3383 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3384 gs
.ReorderMode
= TRAILING
;
3385 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3386 gs
.MaximumNumberofThreads
=
3387 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3388 : (devinfo
->max_gs_threads
- 1);
3390 if (gs_prog_data
->static_vertex_count
!= -1) {
3391 gs
.StaticOutput
= true;
3392 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3394 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3396 gs
.UserClipDistanceCullTestEnableBitmask
=
3397 vue_prog_data
->cull_distance_mask
;
3399 const int urb_entry_write_offset
= 1;
3400 const uint32_t urb_entry_output_length
=
3401 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3402 urb_entry_write_offset
;
3404 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3405 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3410 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3413 iris_store_fs_state(struct iris_context
*ice
,
3414 const struct gen_device_info
*devinfo
,
3415 struct iris_compiled_shader
*shader
)
3417 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3418 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3420 uint32_t *ps_state
= (void *) shader
->derived_data
;
3421 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3423 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3424 ps
.VectorMaskEnable
= true;
3425 // XXX: WABTPPrefetchDisable, see above, drop at C0
3426 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3427 prog_data
->binding_table
.size_bytes
/ 4;
3428 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3429 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3431 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
3433 /* From the documentation for this packet:
3434 * "If the PS kernel does not need the Position XY Offsets to
3435 * compute a Position Value, then this field should be programmed
3436 * to POSOFFSET_NONE."
3438 * "SW Recommendation: If the PS kernel needs the Position Offsets
3439 * to compute a Position XY value, this field should match Position
3440 * ZW Interpolation Mode to ensure a consistent position.xyzw
3443 * We only require XY sample offsets. So, this recommendation doesn't
3444 * look useful at the moment. We might need this in future.
3446 ps
.PositionXYOffsetSelect
=
3447 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3448 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
3449 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
3450 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
3452 // XXX: Disable SIMD32 with 16x MSAA
3454 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3455 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
3456 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
3457 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
3458 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3459 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
3461 ps
.KernelStartPointer0
=
3462 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
3463 ps
.KernelStartPointer1
=
3464 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
3465 ps
.KernelStartPointer2
=
3466 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
3468 if (prog_data
->total_scratch
) {
3469 struct iris_bo
*bo
=
3470 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3471 MESA_SHADER_FRAGMENT
);
3472 uint32_t scratch_addr
= bo
->gtt_offset
;
3473 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3474 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3478 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3479 psx
.PixelShaderValid
= true;
3480 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3481 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
3482 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3483 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3484 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3485 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3486 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3489 if (wm_prog_data
->uses_sample_mask
) {
3490 /* TODO: conservative rasterization */
3491 if (wm_prog_data
->post_depth_coverage
)
3492 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
3494 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
3497 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3498 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3500 psx
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
3507 * Compute the size of the derived data (shader command packets).
3509 * This must match the data written by the iris_store_xs_state() functions.
3512 iris_store_cs_state(struct iris_context
*ice
,
3513 const struct gen_device_info
*devinfo
,
3514 struct iris_compiled_shader
*shader
)
3516 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3517 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3518 void *map
= shader
->derived_data
;
3520 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3521 desc
.KernelStartPointer
= KSP(shader
);
3522 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3523 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3524 desc
.SharedLocalMemorySize
=
3525 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3526 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3527 desc
.CrossThreadConstantDataReadLength
=
3528 cs_prog_data
->push
.cross_thread
.regs
;
3533 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3535 assert(cache_id
<= IRIS_CACHE_BLORP
);
3537 static const unsigned dwords
[] = {
3538 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3539 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3540 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3541 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3543 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3544 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3545 [IRIS_CACHE_BLORP
] = 0,
3548 return sizeof(uint32_t) * dwords
[cache_id
];
3552 * Create any state packets corresponding to the given shader stage
3553 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3554 * This means that we can look up a program in the in-memory cache and
3555 * get most of the state packet without having to reconstruct it.
3558 iris_store_derived_program_state(struct iris_context
*ice
,
3559 enum iris_program_cache_id cache_id
,
3560 struct iris_compiled_shader
*shader
)
3562 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3563 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3567 iris_store_vs_state(ice
, devinfo
, shader
);
3569 case IRIS_CACHE_TCS
:
3570 iris_store_tcs_state(ice
, devinfo
, shader
);
3572 case IRIS_CACHE_TES
:
3573 iris_store_tes_state(ice
, devinfo
, shader
);
3576 iris_store_gs_state(ice
, devinfo
, shader
);
3579 iris_store_fs_state(ice
, devinfo
, shader
);
3582 iris_store_cs_state(ice
, devinfo
, shader
);
3583 case IRIS_CACHE_BLORP
:
3590 /* ------------------------------------------------------------------- */
3593 * Configure the URB.
3595 * XXX: write a real comment.
3598 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
3600 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
3601 const unsigned push_size_kB
= 32;
3602 unsigned entries
[4];
3606 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3607 if (!ice
->shaders
.prog
[i
]) {
3610 struct brw_vue_prog_data
*vue_prog_data
=
3611 (void *) ice
->shaders
.prog
[i
]->prog_data
;
3612 size
[i
] = vue_prog_data
->urb_entry_size
;
3614 assert(size
[i
] != 0);
3617 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
3618 1024 * ice
->shaders
.urb_size
,
3619 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
3620 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
3621 size
, entries
, start
);
3623 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3624 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
3625 urb
._3DCommandSubOpcode
+= i
;
3626 urb
.VSURBStartingAddress
= start
[i
];
3627 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
3628 urb
.VSNumberofURBEntries
= entries
[i
];
3633 static const uint32_t push_constant_opcodes
[] = {
3634 [MESA_SHADER_VERTEX
] = 21,
3635 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3636 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3637 [MESA_SHADER_GEOMETRY
] = 22,
3638 [MESA_SHADER_FRAGMENT
] = 23,
3639 [MESA_SHADER_COMPUTE
] = 0,
3643 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3645 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3647 iris_use_pinned_bo(batch
, state_bo
, false);
3649 return ice
->state
.unbound_tex
.offset
;
3653 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3655 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3656 if (!ice
->state
.null_fb
.res
)
3657 return use_null_surface(batch
, ice
);
3659 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3661 iris_use_pinned_bo(batch
, state_bo
, false);
3663 return ice
->state
.null_fb
.offset
;
3667 * Add a surface to the validation list, as well as the buffer containing
3668 * the corresponding SURFACE_STATE.
3670 * Returns the binding table entry (offset to SURFACE_STATE).
3673 use_surface(struct iris_batch
*batch
,
3674 struct pipe_surface
*p_surf
,
3677 struct iris_surface
*surf
= (void *) p_surf
;
3679 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
3680 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
3682 return surf
->surface_state
.offset
;
3686 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
3688 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
3689 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
3691 return isv
->surface_state
.offset
;
3695 use_const_buffer(struct iris_batch
*batch
,
3696 struct iris_context
*ice
,
3697 struct iris_const_buffer
*cbuf
)
3699 if (!cbuf
->surface_state
.res
)
3700 return use_null_surface(batch
, ice
);
3702 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->data
.res
), false);
3703 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->surface_state
.res
), false);
3705 return cbuf
->surface_state
.offset
;
3709 use_ssbo(struct iris_batch
*batch
, struct iris_context
*ice
,
3710 struct iris_shader_state
*shs
, int i
)
3713 return use_null_surface(batch
, ice
);
3715 struct iris_state_ref
*surf_state
= &shs
->ssbo_surface_state
[i
];
3717 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->ssbo
[i
]), true);
3718 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3720 return surf_state
->offset
;
3724 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
3725 struct iris_shader_state
*shs
, int i
)
3727 if (!shs
->image
[i
].res
)
3728 return use_null_surface(batch
, ice
);
3730 struct iris_state_ref
*surf_state
= &shs
->image
[i
].surface_state
;
3732 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->image
[i
].res
),
3733 shs
->image
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
);
3734 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3736 return surf_state
->offset
;
3739 #define push_bt_entry(addr) \
3740 assert(addr >= binder_addr); \
3741 assert(s < prog_data->binding_table.size_bytes / sizeof(uint32_t)); \
3742 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
3744 #define bt_assert(section, exists) \
3745 if (!pin_only) assert(prog_data->binding_table.section == \
3746 (exists) ? s : 0xd0d0d0d0)
3749 * Populate the binding table for a given shader stage.
3751 * This fills out the table of pointers to surfaces required by the shader,
3752 * and also adds those buffers to the validation list so the kernel can make
3753 * resident before running our batch.
3756 iris_populate_binding_table(struct iris_context
*ice
,
3757 struct iris_batch
*batch
,
3758 gl_shader_stage stage
,
3761 const struct iris_binder
*binder
= &ice
->state
.binder
;
3762 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3766 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3767 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3768 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
3770 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
3771 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
3774 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
3776 /* TCS passthrough doesn't need a binding table. */
3777 assert(stage
== MESA_SHADER_TESS_CTRL
);
3781 if (stage
== MESA_SHADER_COMPUTE
) {
3782 /* surface for gl_NumWorkGroups */
3783 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
3784 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
3785 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
3786 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
3787 push_bt_entry(grid_state
->offset
);
3790 if (stage
== MESA_SHADER_FRAGMENT
) {
3791 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3792 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
3793 if (cso_fb
->nr_cbufs
) {
3794 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
3796 cso_fb
->cbufs
[i
] ? use_surface(batch
, cso_fb
->cbufs
[i
], true)
3797 : use_null_fb_surface(batch
, ice
);
3798 push_bt_entry(addr
);
3801 uint32_t addr
= use_null_fb_surface(batch
, ice
);
3802 push_bt_entry(addr
);
3806 unsigned num_textures
= util_last_bit(info
->textures_used
);
3808 bt_assert(texture_start
, num_textures
> 0);
3810 for (int i
= 0; i
< num_textures
; i
++) {
3811 struct iris_sampler_view
*view
= shs
->textures
[i
];
3812 uint32_t addr
= view
? use_sampler_view(batch
, view
)
3813 : use_null_surface(batch
, ice
);
3814 push_bt_entry(addr
);
3817 bt_assert(image_start
, info
->num_images
> 0);
3819 for (int i
= 0; i
< info
->num_images
; i
++) {
3820 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
3821 push_bt_entry(addr
);
3824 bt_assert(ubo_start
, shader
->num_cbufs
> 0);
3826 for (int i
= 0; i
< shader
->num_cbufs
; i
++) {
3827 uint32_t addr
= use_const_buffer(batch
, ice
, &shs
->constbuf
[i
]);
3828 push_bt_entry(addr
);
3831 bt_assert(ssbo_start
, info
->num_abos
+ info
->num_ssbos
> 0);
3833 /* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
3834 * for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
3835 * in st_atom_storagebuf.c so it'll compact them into one range, with
3836 * SSBOs starting at info->num_abos. Ideally it'd reset num_abos to 0 too
3838 if (info
->num_abos
+ info
->num_ssbos
> 0) {
3839 for (int i
= 0; i
< IRIS_MAX_ABOS
+ info
->num_ssbos
; i
++) {
3840 uint32_t addr
= use_ssbo(batch
, ice
, shs
, i
);
3841 push_bt_entry(addr
);
3846 /* XXX: YUV surfaces not implemented yet */
3847 bt_assert(plane_start
[1], ...);
3848 bt_assert(plane_start
[2], ...);
3853 iris_use_optional_res(struct iris_batch
*batch
,
3854 struct pipe_resource
*res
,
3858 struct iris_bo
*bo
= iris_resource_bo(res
);
3859 iris_use_pinned_bo(batch
, bo
, writeable
);
3863 /* ------------------------------------------------------------------- */
3866 * Pin any BOs which were installed by a previous batch, and restored
3867 * via the hardware logical context mechanism.
3869 * We don't need to re-emit all state every batch - the hardware context
3870 * mechanism will save and restore it for us. This includes pointers to
3871 * various BOs...which won't exist unless we ask the kernel to pin them
3872 * by adding them to the validation list.
3874 * We can skip buffers if we've re-emitted those packets, as we're
3875 * overwriting those stale pointers with new ones, and don't actually
3876 * refer to the old BOs.
3879 iris_restore_render_saved_bos(struct iris_context
*ice
,
3880 struct iris_batch
*batch
,
3881 const struct pipe_draw_info
*draw
)
3883 struct iris_genx_state
*genx
= ice
->state
.genx
;
3885 const uint64_t clean
= ~ice
->state
.dirty
;
3887 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
3888 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
3891 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3892 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
3895 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
3896 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
3899 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3900 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
3903 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
3904 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
3907 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
3908 for (int i
= 0; i
< 4; i
++) {
3909 struct iris_stream_output_target
*tgt
=
3910 (void *) ice
->state
.so_target
[i
];
3912 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
3914 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
3920 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3921 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
3924 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3925 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3930 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3932 for (int i
= 0; i
< 4; i
++) {
3933 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3935 if (range
->length
== 0)
3938 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3939 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3942 iris_use_pinned_bo(batch
, res
->bo
, false);
3944 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3948 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3949 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
3950 /* Re-pin any buffers referred to by the binding table. */
3951 iris_populate_binding_table(ice
, batch
, stage
, true);
3955 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3956 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3957 struct pipe_resource
*res
= shs
->sampler_table
.res
;
3959 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3962 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3963 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
3964 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3967 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3968 iris_use_pinned_bo(batch
, bo
, false);
3970 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3972 if (prog_data
->total_scratch
> 0) {
3973 struct iris_bo
*bo
=
3974 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
3975 iris_use_pinned_bo(batch
, bo
, true);
3981 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
3982 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3984 if (cso_fb
->zsbuf
) {
3985 struct iris_resource
*zres
, *sres
;
3986 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
3989 iris_cache_flush_for_depth(batch
, zres
->bo
);
3991 iris_use_pinned_bo(batch
, zres
->bo
,
3992 ice
->state
.depth_writes_enabled
);
3996 iris_cache_flush_for_depth(batch
, sres
->bo
);
3998 iris_use_pinned_bo(batch
, sres
->bo
,
3999 ice
->state
.stencil_writes_enabled
);
4004 if (draw
->index_size
== 0 && ice
->state
.last_res
.index_buffer
) {
4005 /* This draw didn't emit a new index buffer, so we are inheriting the
4006 * older index buffer. This draw didn't need it, but future ones may.
4008 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4009 iris_use_pinned_bo(batch
, bo
, false);
4012 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4013 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4015 const int i
= u_bit_scan64(&bound
);
4016 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
4017 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4023 iris_restore_compute_saved_bos(struct iris_context
*ice
,
4024 struct iris_batch
*batch
,
4025 const struct pipe_grid_info
*grid
)
4027 const uint64_t clean
= ~ice
->state
.dirty
;
4029 const int stage
= MESA_SHADER_COMPUTE
;
4030 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4032 if (clean
& IRIS_DIRTY_CONSTANTS_CS
) {
4033 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4036 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4037 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[0];
4039 if (range
->length
> 0) {
4040 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4041 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
4044 iris_use_pinned_bo(batch
, res
->bo
, false);
4046 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4051 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
4052 /* Re-pin any buffers referred to by the binding table. */
4053 iris_populate_binding_table(ice
, batch
, stage
, true);
4056 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
4058 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
4060 if (clean
& IRIS_DIRTY_CS
) {
4061 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4064 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4065 iris_use_pinned_bo(batch
, bo
, false);
4067 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4069 if (prog_data
->total_scratch
> 0) {
4070 struct iris_bo
*bo
=
4071 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4072 iris_use_pinned_bo(batch
, bo
, true);
4079 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
4082 iris_update_surface_base_address(struct iris_batch
*batch
,
4083 struct iris_binder
*binder
)
4085 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
4088 flush_for_state_base_change(batch
);
4090 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
4091 sba
.SurfaceStateMOCS
= MOCS_WB
;
4092 sba
.SurfaceStateBaseAddressModifyEnable
= true;
4093 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
4096 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
4100 iris_upload_dirty_render_state(struct iris_context
*ice
,
4101 struct iris_batch
*batch
,
4102 const struct pipe_draw_info
*draw
)
4104 const uint64_t dirty
= ice
->state
.dirty
;
4106 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
4109 struct iris_genx_state
*genx
= ice
->state
.genx
;
4110 struct iris_binder
*binder
= &ice
->state
.binder
;
4111 struct brw_wm_prog_data
*wm_prog_data
= (void *)
4112 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
4114 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
4115 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4116 uint32_t cc_vp_address
;
4118 /* XXX: could avoid streaming for depth_clip [0,1] case. */
4119 uint32_t *cc_vp_map
=
4120 stream_state(batch
, ice
->state
.dynamic_uploader
,
4121 &ice
->state
.last_res
.cc_vp
,
4122 4 * ice
->state
.num_viewports
*
4123 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
4124 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4126 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
4127 cso_rast
->clip_halfz
, &zmin
, &zmax
);
4128 if (cso_rast
->depth_clip_near
)
4130 if (cso_rast
->depth_clip_far
)
4133 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
4134 ccv
.MinimumDepth
= zmin
;
4135 ccv
.MaximumDepth
= zmax
;
4138 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
4141 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
4142 ptr
.CCViewportPointer
= cc_vp_address
;
4146 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4147 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4148 uint32_t sf_cl_vp_address
;
4150 stream_state(batch
, ice
->state
.dynamic_uploader
,
4151 &ice
->state
.last_res
.sf_cl_vp
,
4152 4 * ice
->state
.num_viewports
*
4153 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
4155 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4156 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
4157 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
4159 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
4160 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
4161 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
4162 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
4164 calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
4165 state
->scale
[0], state
->scale
[1],
4166 state
->translate
[0], state
->translate
[1],
4167 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
4169 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
4170 vp
.ViewportMatrixElementm00
= state
->scale
[0];
4171 vp
.ViewportMatrixElementm11
= state
->scale
[1];
4172 vp
.ViewportMatrixElementm22
= state
->scale
[2];
4173 vp
.ViewportMatrixElementm30
= state
->translate
[0];
4174 vp
.ViewportMatrixElementm31
= state
->translate
[1];
4175 vp
.ViewportMatrixElementm32
= state
->translate
[2];
4176 vp
.XMinClipGuardband
= gb_xmin
;
4177 vp
.XMaxClipGuardband
= gb_xmax
;
4178 vp
.YMinClipGuardband
= gb_ymin
;
4179 vp
.YMaxClipGuardband
= gb_ymax
;
4180 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
4181 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
4182 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
4183 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
4186 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
4189 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
4190 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
4194 if (dirty
& IRIS_DIRTY_URB
) {
4195 iris_upload_urb_config(ice
, batch
);
4198 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
4199 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4200 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4201 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4202 const int header_dwords
= GENX(BLEND_STATE_length
);
4204 /* Always write at least one BLEND_STATE - the final RT message will
4205 * reference BLEND_STATE[0] even if there aren't color writes. There
4206 * may still be alpha testing, computed depth, and so on.
4208 const int rt_dwords
=
4209 MAX2(cso_fb
->nr_cbufs
, 1) * GENX(BLEND_STATE_ENTRY_length
);
4211 uint32_t blend_offset
;
4212 uint32_t *blend_map
=
4213 stream_state(batch
, ice
->state
.dynamic_uploader
,
4214 &ice
->state
.last_res
.blend
,
4215 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4217 uint32_t blend_state_header
;
4218 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4219 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4220 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4223 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4224 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4226 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4227 ptr
.BlendStatePointer
= blend_offset
;
4228 ptr
.BlendStatePointerValid
= true;
4232 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4233 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4235 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4239 stream_state(batch
, ice
->state
.dynamic_uploader
,
4240 &ice
->state
.last_res
.color_calc
,
4241 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4243 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4244 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4245 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4246 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4247 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4248 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4249 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4251 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4252 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4255 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4256 ptr
.ColorCalcStatePointer
= cc_offset
;
4257 ptr
.ColorCalcStatePointerValid
= true;
4261 /* Upload constants for TCS passthrough. */
4262 if ((dirty
& IRIS_DIRTY_CONSTANTS_TCS
) &&
4263 ice
->shaders
.prog
[MESA_SHADER_TESS_CTRL
] &&
4264 !ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
]) {
4265 struct iris_compiled_shader
*tes_shader
= ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
4268 /* Passthrough always copies 2 vec4s, so when uploading data we ensure
4269 * it is in the right layout for TES.
4272 struct brw_tes_prog_data
*tes_prog_data
= (void *) tes_shader
->prog_data
;
4273 switch (tes_prog_data
->domain
) {
4274 case BRW_TESS_DOMAIN_QUAD
:
4275 for (int i
= 0; i
< 4; i
++)
4276 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4277 hdr
[3] = ice
->state
.default_inner_level
[0];
4278 hdr
[2] = ice
->state
.default_inner_level
[1];
4280 case BRW_TESS_DOMAIN_TRI
:
4281 for (int i
= 0; i
< 3; i
++)
4282 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4283 hdr
[4] = ice
->state
.default_inner_level
[0];
4285 case BRW_TESS_DOMAIN_ISOLINE
:
4286 hdr
[7] = ice
->state
.default_outer_level
[1];
4287 hdr
[6] = ice
->state
.default_outer_level
[0];
4291 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
4292 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
4293 u_upload_data(ice
->ctx
.const_uploader
, 0, sizeof(hdr
), 32,
4294 &hdr
[0], &cbuf
->data
.offset
,
4298 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4299 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4302 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4303 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4308 if (shs
->cbuf0_needs_upload
)
4309 upload_uniforms(ice
, stage
);
4311 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4313 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4314 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4316 /* The Skylake PRM contains the following restriction:
4318 * "The driver must ensure The following case does not occur
4319 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4320 * buffer 3 read length equal to zero committed followed by a
4321 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4324 * To avoid this, we program the buffers in the highest slots.
4325 * This way, slot 0 is only used if slot 3 is also used.
4329 for (int i
= 3; i
>= 0; i
--) {
4330 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4332 if (range
->length
== 0)
4335 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4336 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
4338 assert(cbuf
->data
.offset
% 32 == 0);
4340 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4341 pkt
.ConstantBody
.Buffer
[n
] =
4342 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->data
.offset
)
4343 : ro_bo(batch
->screen
->workaround_bo
, 0);
4350 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4351 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4352 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4353 ptr
._3DCommandSubOpcode
= 38 + stage
;
4354 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4359 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4360 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4361 iris_populate_binding_table(ice
, batch
, stage
, false);
4365 if (ice
->state
.need_border_colors
)
4366 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4368 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4369 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4370 !ice
->shaders
.prog
[stage
])
4373 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4374 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4376 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4378 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4379 ptr
._3DCommandSubOpcode
= 43 + stage
;
4380 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4384 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4385 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4387 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4388 if (ice
->state
.framebuffer
.samples
> 0)
4389 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4393 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4394 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4395 ms
.SampleMask
= ice
->state
.sample_mask
;
4399 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4400 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4403 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4406 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4407 iris_use_pinned_bo(batch
, cache
->bo
, false);
4408 iris_batch_emit(batch
, shader
->derived_data
,
4409 iris_derived_program_state_size(stage
));
4411 if (stage
== MESA_SHADER_TESS_EVAL
) {
4412 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4413 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4414 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4415 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4416 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4421 if (ice
->state
.streamout_active
) {
4422 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4423 iris_batch_emit(batch
, genx
->so_buffers
,
4424 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4425 for (int i
= 0; i
< 4; i
++) {
4426 struct iris_stream_output_target
*tgt
=
4427 (void *) ice
->state
.so_target
[i
];
4429 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4431 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4437 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
4438 uint32_t *decl_list
=
4439 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
4440 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
4443 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4444 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4446 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
4447 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
4448 sol
.SOFunctionEnable
= true;
4449 sol
.SOStatisticsEnable
= true;
4451 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
4452 !ice
->state
.prims_generated_query_active
;
4453 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
4456 assert(ice
->state
.streamout
);
4458 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
4459 GENX(3DSTATE_STREAMOUT_length
));
4462 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4463 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
4467 if (dirty
& IRIS_DIRTY_CLIP
) {
4468 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4469 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4471 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
4472 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
4473 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4474 cl
.ClipMode
= cso_rast
->rasterizer_discard
? CLIPMODE_REJECT_ALL
4476 if (wm_prog_data
->barycentric_interp_modes
&
4477 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
4478 cl
.NonPerspectiveBarycentricEnable
= true;
4480 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
4481 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
4483 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
4484 ARRAY_SIZE(cso_rast
->clip
));
4487 if (dirty
& IRIS_DIRTY_RASTER
) {
4488 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4489 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
4490 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
4494 if (dirty
& IRIS_DIRTY_WM
) {
4495 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4496 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
4498 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
4499 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4501 wm
.BarycentricInterpolationMode
=
4502 wm_prog_data
->barycentric_interp_modes
;
4504 if (wm_prog_data
->early_fragment_tests
)
4505 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
4506 else if (wm_prog_data
->has_side_effects
)
4507 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
4509 /* We could skip this bit if color writes are enabled. */
4510 if (wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
)
4511 wm
.ForceThreadDispatchEnable
= ForceON
;
4513 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
4516 if (dirty
& IRIS_DIRTY_SBE
) {
4517 iris_emit_sbe(batch
, ice
);
4520 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
4521 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4522 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4523 const struct shader_info
*fs_info
=
4524 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
4526 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
4527 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
4528 pb
.HasWriteableRT
= has_writeable_rt(cso_blend
, fs_info
);
4529 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4532 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
4533 ARRAY_SIZE(cso_blend
->ps_blend
));
4536 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
4537 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4539 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4540 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
4541 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
4542 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4543 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4545 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
4547 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
4551 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
4552 uint32_t scissor_offset
=
4553 emit_state(batch
, ice
->state
.dynamic_uploader
,
4554 &ice
->state
.last_res
.scissor
,
4555 ice
->state
.scissors
,
4556 sizeof(struct pipe_scissor_state
) *
4557 ice
->state
.num_viewports
, 32);
4559 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
4560 ptr
.ScissorRectPointer
= scissor_offset
;
4564 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
4565 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4566 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
4568 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
4570 if (cso_fb
->zsbuf
) {
4571 struct iris_resource
*zres
, *sres
;
4572 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
4575 iris_use_pinned_bo(batch
, zres
->bo
,
4576 ice
->state
.depth_writes_enabled
);
4580 iris_use_pinned_bo(batch
, sres
->bo
,
4581 ice
->state
.stencil_writes_enabled
);
4586 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
4587 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
4588 for (int i
= 0; i
< 32; i
++) {
4589 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
4594 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
4595 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4596 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
4599 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
4600 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
4601 topo
.PrimitiveTopologyType
=
4602 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
4606 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4607 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
4610 /* The VF cache designers cut corners, and made the cache key's
4611 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
4612 * 32 bits of the address. If you have two vertex buffers which get
4613 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
4614 * you can get collisions (even within a single batch).
4616 * So, we need to do a VF cache invalidate if the buffer for a VB
4617 * slot slot changes [48:32] address bits from the previous time.
4619 unsigned flush_flags
= 0;
4621 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4623 const int i
= u_bit_scan64(&bound
);
4624 uint16_t high_bits
= 0;
4626 struct iris_resource
*res
=
4627 (void *) genx
->vertex_buffers
[i
].resource
;
4629 iris_use_pinned_bo(batch
, res
->bo
, false);
4631 high_bits
= res
->bo
->gtt_offset
>> 32ull;
4632 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
4633 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
|
4634 PIPE_CONTROL_CS_STALL
;
4635 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
4638 /* If the buffer was written to by streamout, we may need
4639 * to stall so those writes land and become visible to the
4642 * TODO: This may stall more than necessary.
4644 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
4645 flush_flags
|= PIPE_CONTROL_CS_STALL
;
4650 iris_emit_pipe_control_flush(batch
, flush_flags
);
4652 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
4655 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
4656 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
4657 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
4661 bound
= ice
->state
.bound_vertex_buffers
;
4663 const int i
= u_bit_scan64(&bound
);
4664 memcpy(map
, genx
->vertex_buffers
[i
].state
,
4665 sizeof(uint32_t) * vb_dwords
);
4671 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
4672 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4673 const unsigned entries
= MAX2(cso
->count
, 1);
4674 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
4675 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
4676 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
4677 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
4680 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
4681 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
4682 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
4683 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4685 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
4686 if (vs_prog_data
->uses_vertexid
) {
4687 sgv
.VertexIDEnable
= true;
4688 sgv
.VertexIDComponentNumber
= 2;
4689 sgv
.VertexIDElementOffset
= cso
->count
;
4692 if (vs_prog_data
->uses_instanceid
) {
4693 sgv
.InstanceIDEnable
= true;
4694 sgv
.InstanceIDComponentNumber
= 3;
4695 sgv
.InstanceIDElementOffset
= cso
->count
;
4700 if (dirty
& IRIS_DIRTY_VF
) {
4701 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
4702 if (draw
->primitive_restart
) {
4703 vf
.IndexedDrawCutIndexEnable
= true;
4704 vf
.CutIndex
= draw
->restart_index
;
4709 /* TODO: Gen8 PMA fix */
4713 iris_upload_render_state(struct iris_context
*ice
,
4714 struct iris_batch
*batch
,
4715 const struct pipe_draw_info
*draw
)
4717 /* Always pin the binder. If we're emitting new binding table pointers,
4718 * we need it. If not, we're probably inheriting old tables via the
4719 * context, and need it anyway. Since true zero-bindings cases are
4720 * practically non-existent, just pin it and avoid last_res tracking.
4722 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
4724 if (!batch
->contains_draw
) {
4725 iris_restore_render_saved_bos(ice
, batch
, draw
);
4726 batch
->contains_draw
= true;
4729 iris_upload_dirty_render_state(ice
, batch
, draw
);
4731 if (draw
->index_size
> 0) {
4734 if (draw
->has_user_indices
) {
4735 u_upload_data(ice
->ctx
.stream_uploader
, 0,
4736 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
4737 &offset
, &ice
->state
.last_res
.index_buffer
);
4739 struct iris_resource
*res
= (void *) draw
->index
.resource
;
4740 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
4742 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
4743 draw
->index
.resource
);
4747 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4749 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
4750 ib
.IndexFormat
= draw
->index_size
>> 1;
4752 ib
.BufferSize
= bo
->size
;
4753 ib
.BufferStartingAddress
= ro_bo(bo
, offset
);
4756 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
4757 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
4758 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
4759 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_VF_CACHE_INVALIDATE
|
4760 PIPE_CONTROL_CS_STALL
);
4761 ice
->state
.last_index_bo_high_bits
= high_bits
;
4765 #define _3DPRIM_END_OFFSET 0x2420
4766 #define _3DPRIM_START_VERTEX 0x2430
4767 #define _3DPRIM_VERTEX_COUNT 0x2434
4768 #define _3DPRIM_INSTANCE_COUNT 0x2438
4769 #define _3DPRIM_START_INSTANCE 0x243C
4770 #define _3DPRIM_BASE_VERTEX 0x2440
4772 if (draw
->indirect
) {
4773 /* We don't support this MultidrawIndirect. */
4774 assert(!draw
->indirect
->indirect_draw_count
);
4776 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
4779 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4780 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
4781 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
4783 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4784 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
4785 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
4787 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4788 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
4789 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
4791 if (draw
->index_size
) {
4792 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4793 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
4794 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4796 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4797 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4798 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
4801 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4802 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4803 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4805 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
4806 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
4810 } else if (draw
->count_from_stream_output
) {
4811 struct iris_stream_output_target
*so
=
4812 (void *) draw
->count_from_stream_output
;
4814 /* XXX: Replace with actual cache tracking */
4815 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
4817 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4818 lrm
.RegisterAddress
= CS_GPR(0);
4820 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
4822 iris_math_div32_gpr0(ice
, batch
, so
->stride
);
4823 _iris_emit_lrr(batch
, _3DPRIM_VERTEX_COUNT
, CS_GPR(0));
4825 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
4826 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
4827 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
4828 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
4831 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
4832 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
4833 prim
.PredicateEnable
=
4834 ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
4836 if (draw
->indirect
|| draw
->count_from_stream_output
) {
4837 prim
.IndirectParameterEnable
= true;
4839 prim
.StartInstanceLocation
= draw
->start_instance
;
4840 prim
.InstanceCount
= draw
->instance_count
;
4841 prim
.VertexCountPerInstance
= draw
->count
;
4843 // XXX: this is probably bonkers.
4844 prim
.StartVertexLocation
= draw
->start
;
4846 if (draw
->index_size
) {
4847 prim
.BaseVertexLocation
+= draw
->index_bias
;
4849 prim
.StartVertexLocation
+= draw
->index_bias
;
4852 //prim.BaseVertexLocation = ...;
4858 iris_upload_compute_state(struct iris_context
*ice
,
4859 struct iris_batch
*batch
,
4860 const struct pipe_grid_info
*grid
)
4862 const uint64_t dirty
= ice
->state
.dirty
;
4863 struct iris_screen
*screen
= batch
->screen
;
4864 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
4865 struct iris_binder
*binder
= &ice
->state
.binder
;
4866 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
4867 struct iris_compiled_shader
*shader
=
4868 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
4869 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4870 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
4872 /* Always pin the binder. If we're emitting new binding table pointers,
4873 * we need it. If not, we're probably inheriting old tables via the
4874 * context, and need it anyway. Since true zero-bindings cases are
4875 * practically non-existent, just pin it and avoid last_res tracking.
4877 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
4879 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->cbuf0_needs_upload
)
4880 upload_uniforms(ice
, MESA_SHADER_COMPUTE
);
4882 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
4883 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
4885 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
4886 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
4888 if (ice
->state
.need_border_colors
)
4889 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4891 if (dirty
& IRIS_DIRTY_CS
) {
4892 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4894 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4895 * the only bits that are changed are scoreboard related: Scoreboard
4896 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
4897 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4900 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
4902 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4903 if (prog_data
->total_scratch
) {
4904 struct iris_bo
*bo
=
4905 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
4906 MESA_SHADER_COMPUTE
);
4907 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
4908 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
4911 vfe
.MaximumNumberofThreads
=
4912 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
4914 vfe
.ResetGatewayTimer
=
4915 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4918 vfe
.BypassGatewayControl
= true;
4920 vfe
.NumberofURBEntries
= 2;
4921 vfe
.URBEntryAllocationSize
= 2;
4923 vfe
.CURBEAllocationSize
=
4924 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4925 cs_prog_data
->push
.cross_thread
.regs
, 2);
4929 /* TODO: Combine subgroup-id with cbuf0 so we can push regular uniforms */
4930 uint32_t curbe_data_offset
= 0;
4931 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
4932 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
4933 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
4934 struct pipe_resource
*curbe_data_res
= NULL
;
4935 uint32_t *curbe_data_map
=
4936 stream_state(batch
, ice
->state
.dynamic_uploader
, &curbe_data_res
,
4937 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
4938 &curbe_data_offset
);
4939 assert(curbe_data_map
);
4940 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
4941 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
4943 if (dirty
& IRIS_DIRTY_CONSTANTS_CS
) {
4944 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4945 curbe
.CURBETotalDataLength
=
4946 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4947 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
4951 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
4952 IRIS_DIRTY_BINDINGS_CS
|
4953 IRIS_DIRTY_CONSTANTS_CS
|
4955 struct pipe_resource
*desc_res
= NULL
;
4956 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4958 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
4959 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
4960 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
4963 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
4964 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
4966 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4967 load
.InterfaceDescriptorTotalLength
=
4968 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4969 load
.InterfaceDescriptorDataStartAddress
=
4970 emit_state(batch
, ice
->state
.dynamic_uploader
,
4971 &desc_res
, desc
, sizeof(desc
), 32);
4974 pipe_resource_reference(&desc_res
, NULL
);
4977 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
4978 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
4979 uint32_t right_mask
;
4982 right_mask
= ~0u >> (32 - remainder
);
4984 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
4986 #define GPGPU_DISPATCHDIMX 0x2500
4987 #define GPGPU_DISPATCHDIMY 0x2504
4988 #define GPGPU_DISPATCHDIMZ 0x2508
4990 if (grid
->indirect
) {
4991 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
4992 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
4993 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4994 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
4995 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
4997 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4998 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
4999 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
5001 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5002 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
5003 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
5007 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
5008 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
5009 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
5010 ggw
.ThreadDepthCounterMaximum
= 0;
5011 ggw
.ThreadHeightCounterMaximum
= 0;
5012 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
5013 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
5014 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
5015 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
5016 ggw
.RightExecutionMask
= right_mask
;
5017 ggw
.BottomExecutionMask
= 0xffffffff;
5020 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
5022 if (!batch
->contains_draw
) {
5023 iris_restore_compute_saved_bos(ice
, batch
, grid
);
5024 batch
->contains_draw
= true;
5029 * State module teardown.
5032 iris_destroy_state(struct iris_context
*ice
)
5034 struct iris_genx_state
*genx
= ice
->state
.genx
;
5036 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5038 const int i
= u_bit_scan64(&bound_vbs
);
5039 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
5041 free(ice
->state
.genx
);
5043 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
5044 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
5046 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
5048 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
5049 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5050 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
5051 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
5052 pipe_resource_reference(&shs
->constbuf
[i
].data
.res
, NULL
);
5053 pipe_resource_reference(&shs
->constbuf
[i
].surface_state
.res
, NULL
);
5055 for (int i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
5056 pipe_resource_reference(&shs
->image
[i
].res
, NULL
);
5057 pipe_resource_reference(&shs
->image
[i
].surface_state
.res
, NULL
);
5059 for (int i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
5060 pipe_resource_reference(&shs
->ssbo
[i
], NULL
);
5061 pipe_resource_reference(&shs
->ssbo_surface_state
[i
].res
, NULL
);
5063 for (int i
= 0; i
< IRIS_MAX_TEXTURE_SAMPLERS
; i
++) {
5064 pipe_sampler_view_reference((struct pipe_sampler_view
**)
5065 &shs
->textures
[i
], NULL
);
5069 pipe_resource_reference(&ice
->state
.grid_size
.res
, NULL
);
5070 pipe_resource_reference(&ice
->state
.grid_surf_state
.res
, NULL
);
5072 pipe_resource_reference(&ice
->state
.null_fb
.res
, NULL
);
5073 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
5075 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
5076 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
5077 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
5078 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
5079 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
5080 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
5083 /* ------------------------------------------------------------------- */
5086 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
5089 _iris_emit_lrr(batch
, dst
, src
);
5093 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
5096 _iris_emit_lrr(batch
, dst
, src
);
5097 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
5101 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
5104 _iris_emit_lri(batch
, reg
, val
);
5108 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
5111 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
5112 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
5116 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
5119 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5120 struct iris_bo
*bo
, uint32_t offset
)
5122 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5123 lrm
.RegisterAddress
= reg
;
5124 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
5129 * Load a 64-bit value from a buffer into a MMIO register via
5130 * two MI_LOAD_REGISTER_MEM commands.
5133 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5134 struct iris_bo
*bo
, uint32_t offset
)
5136 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
5137 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
5141 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5142 struct iris_bo
*bo
, uint32_t offset
,
5145 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
5146 srm
.RegisterAddress
= reg
;
5147 srm
.MemoryAddress
= rw_bo(bo
, offset
);
5148 srm
.PredicateEnable
= predicated
;
5153 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5154 struct iris_bo
*bo
, uint32_t offset
,
5157 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
5158 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
5162 iris_store_data_imm32(struct iris_batch
*batch
,
5163 struct iris_bo
*bo
, uint32_t offset
,
5166 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
5167 sdi
.Address
= rw_bo(bo
, offset
);
5168 sdi
.ImmediateData
= imm
;
5173 iris_store_data_imm64(struct iris_batch
*batch
,
5174 struct iris_bo
*bo
, uint32_t offset
,
5177 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
5178 * 2 in genxml but it's actually variable length and we need 5 DWords.
5180 void *map
= iris_get_command_space(batch
, 4 * 5);
5181 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
5182 sdi
.DWordLength
= 5 - 2;
5183 sdi
.Address
= rw_bo(bo
, offset
);
5184 sdi
.ImmediateData
= imm
;
5189 iris_copy_mem_mem(struct iris_batch
*batch
,
5190 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
5191 struct iris_bo
*src_bo
, uint32_t src_offset
,
5194 /* MI_COPY_MEM_MEM operates on DWords. */
5195 assert(bytes
% 4 == 0);
5196 assert(dst_offset
% 4 == 0);
5197 assert(src_offset
% 4 == 0);
5199 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
5200 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
5201 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
5202 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
5207 /* ------------------------------------------------------------------- */
5210 flags_to_post_sync_op(uint32_t flags
)
5212 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
5213 return WriteImmediateData
;
5215 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
5216 return WritePSDepthCount
;
5218 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
5219 return WriteTimestamp
;
5225 * Do the given flags have a Post Sync or LRI Post Sync operation?
5227 static enum pipe_control_flags
5228 get_post_sync_flags(enum pipe_control_flags flags
)
5230 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
5231 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5232 PIPE_CONTROL_WRITE_TIMESTAMP
|
5233 PIPE_CONTROL_LRI_POST_SYNC_OP
;
5235 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
5236 * "LRI Post Sync Operation". So more than one bit set would be illegal.
5238 assert(util_bitcount(flags
) <= 1);
5243 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
5246 * Emit a series of PIPE_CONTROL commands, taking into account any
5247 * workarounds necessary to actually accomplish the caller's request.
5249 * Unless otherwise noted, spec quotations in this function come from:
5251 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
5252 * Restrictions for PIPE_CONTROL.
5254 * You should not use this function directly. Use the helpers in
5255 * iris_pipe_control.c instead, which may split the pipe control further.
5258 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
5259 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
5261 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
5262 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
5263 enum pipe_control_flags non_lri_post_sync_flags
=
5264 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
5266 /* Recursive PIPE_CONTROL workarounds --------------------------------
5267 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
5269 * We do these first because we want to look at the original operation,
5270 * rather than any workarounds we set.
5272 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
5273 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
5274 * lists several workarounds:
5276 * "Project: SKL, KBL, BXT
5278 * If the VF Cache Invalidation Enable is set to a 1 in a
5279 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
5280 * sets to 0, with the VF Cache Invalidation Enable set to 0
5281 * needs to be sent prior to the PIPE_CONTROL with VF Cache
5282 * Invalidation Enable set to a 1."
5284 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
5287 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
5288 /* Project: SKL / Argument: LRI Post Sync Operation [23]
5290 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5291 * programmed prior to programming a PIPECONTROL command with "LRI
5292 * Post Sync Operation" in GPGPU mode of operation (i.e when
5293 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
5295 * The same text exists a few rows below for Post Sync Op.
5297 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
5300 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
5302 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
5303 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
5304 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
5306 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
5310 /* "Flush Types" workarounds ---------------------------------------------
5311 * We do these now because they may add post-sync operations or CS stalls.
5314 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
5315 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
5317 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
5318 * 'Write PS Depth Count' or 'Write Timestamp'."
5321 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5322 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5323 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5324 bo
= batch
->screen
->workaround_bo
;
5328 /* #1130 from Gen10 workarounds page:
5330 * "Enable Depth Stall on every Post Sync Op if Render target Cache
5331 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
5332 * board stall if Render target cache flush is enabled."
5334 * Applicable to CNL B0 and C0 steppings only.
5336 * The wording here is unclear, and this workaround doesn't look anything
5337 * like the internal bug report recommendations, but leave it be for now...
5339 if (GEN_GEN
== 10) {
5340 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
5341 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5342 } else if (flags
& non_lri_post_sync_flags
) {
5343 flags
|= PIPE_CONTROL_DEPTH_STALL
;
5347 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
5348 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
5350 * "This bit must be DISABLED for operations other than writing
5353 * This seems like nonsense. An Ivybridge workaround requires us to
5354 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
5355 * operation. Gen8+ requires us to emit depth stalls and depth cache
5356 * flushes together. So, it's hard to imagine this means anything other
5357 * than "we originally intended this to be used for PS_DEPTH_COUNT".
5359 * We ignore the supposed restriction and do nothing.
5363 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5364 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5365 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
5367 * "This bit must be DISABLED for End-of-pipe (Read) fences,
5368 * PS_DEPTH_COUNT or TIMESTAMP queries."
5370 * TODO: Implement end-of-pipe checking.
5372 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5373 PIPE_CONTROL_WRITE_TIMESTAMP
)));
5376 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5377 /* From the PIPE_CONTROL instruction table, bit 1:
5379 * "This bit is ignored if Depth Stall Enable is set.
5380 * Further, the render cache is not flushed even if Write Cache
5381 * Flush Enable bit is set."
5383 * We assert that the caller doesn't do this combination, to try and
5384 * prevent mistakes. It shouldn't hurt the GPU, though.
5386 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
5387 * and "Render Target Flush" combo is explicitly required for BTI
5388 * update workarounds.
5390 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
5391 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
5394 /* PIPE_CONTROL page workarounds ------------------------------------- */
5396 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
5397 /* From the PIPE_CONTROL page itself:
5400 * Restriction: Pipe_control with CS-stall bit set must be issued
5401 * before a pipe-control command that has the State Cache
5402 * Invalidate bit set."
5404 flags
|= PIPE_CONTROL_CS_STALL
;
5407 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
5408 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
5411 * SW must always program Post-Sync Operation to "Write Immediate
5412 * Data" when Flush LLC is set."
5414 * For now, we just require the caller to do it.
5416 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
5419 /* "Post-Sync Operation" workarounds -------------------------------- */
5421 /* Project: All / Argument: Global Snapshot Count Reset [19]
5423 * "This bit must not be exercised on any product.
5424 * Requires stall bit ([20] of DW1) set."
5426 * We don't use this, so we just assert that it isn't used. The
5427 * PIPE_CONTROL instruction page indicates that they intended this
5428 * as a debug feature and don't think it is useful in production,
5429 * but it may actually be usable, should we ever want to.
5431 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
5433 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
5434 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
5435 /* Project: All / Arguments:
5437 * - Generic Media State Clear [16]
5438 * - Indirect State Pointers Disable [16]
5440 * "Requires stall bit ([20] of DW1) set."
5442 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
5443 * State Clear) says:
5445 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5446 * programmed prior to programming a PIPECONTROL command with "Media
5447 * State Clear" set in GPGPU mode of operation"
5449 * This is a subset of the earlier rule, so there's nothing to do.
5451 flags
|= PIPE_CONTROL_CS_STALL
;
5454 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
5455 /* Project: All / Argument: Store Data Index
5457 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5460 * For now, we just assert that the caller does this. We might want to
5461 * automatically add a write to the workaround BO...
5463 assert(non_lri_post_sync_flags
!= 0);
5466 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
5467 /* Project: All / Argument: Sync GFDT
5469 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5470 * than '0' or 0x2520[13] must be set."
5472 * For now, we just assert that the caller does this.
5474 assert(non_lri_post_sync_flags
!= 0);
5477 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
5478 /* Project: IVB+ / Argument: TLB inv
5480 * "Requires stall bit ([20] of DW1) set."
5482 * Also, from the PIPE_CONTROL instruction table:
5485 * Post Sync Operation or CS stall must be set to ensure a TLB
5486 * invalidation occurs. Otherwise no cycle will occur to the TLB
5487 * cache to invalidate."
5489 * This is not a subset of the earlier rule, so there's nothing to do.
5491 flags
|= PIPE_CONTROL_CS_STALL
;
5494 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
5495 /* TODO: The big Skylake GT4 post sync op workaround */
5498 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
5500 if (IS_COMPUTE_PIPELINE(batch
)) {
5501 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
5502 /* Project: SKL+ / Argument: Tex Invalidate
5503 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
5505 flags
|= PIPE_CONTROL_CS_STALL
;
5508 if (GEN_GEN
== 8 && (post_sync_flags
||
5509 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
5510 PIPE_CONTROL_DEPTH_STALL
|
5511 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5512 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5513 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
5514 /* Project: BDW / Arguments:
5516 * - LRI Post Sync Operation [23]
5517 * - Post Sync Op [15:14]
5519 * - Depth Stall [13]
5520 * - Render Target Cache Flush [12]
5521 * - Depth Cache Flush [0]
5522 * - DC Flush Enable [5]
5524 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
5527 flags
|= PIPE_CONTROL_CS_STALL
;
5529 /* Also, from the PIPE_CONTROL instruction table, bit 20:
5532 * This bit must be always set when PIPE_CONTROL command is
5533 * programmed by GPGPU and MEDIA workloads, except for the cases
5534 * when only Read Only Cache Invalidation bits are set (State
5535 * Cache Invalidation Enable, Instruction cache Invalidation
5536 * Enable, Texture Cache Invalidation Enable, Constant Cache
5537 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
5538 * need not implemented when FF_DOP_CG is disable via "Fixed
5539 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
5541 * It sounds like we could avoid CS stalls in some cases, but we
5542 * don't currently bother. This list isn't exactly the list above,
5548 /* "Stall" workarounds ----------------------------------------------
5549 * These have to come after the earlier ones because we may have added
5550 * some additional CS stalls above.
5553 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
5554 /* Project: PRE-SKL, VLV, CHV
5556 * "[All Stepping][All SKUs]:
5558 * One of the following must also be set:
5560 * - Render Target Cache Flush Enable ([12] of DW1)
5561 * - Depth Cache Flush Enable ([0] of DW1)
5562 * - Stall at Pixel Scoreboard ([1] of DW1)
5563 * - Depth Stall ([13] of DW1)
5564 * - Post-Sync Operation ([13] of DW1)
5565 * - DC Flush Enable ([5] of DW1)"
5567 * If we don't already have one of those bits set, we choose to add
5568 * "Stall at Pixel Scoreboard". Some of the other bits require a
5569 * CS stall as a workaround (see above), which would send us into
5570 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
5571 * appears to be safe, so we choose that.
5573 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5574 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5575 PIPE_CONTROL_WRITE_IMMEDIATE
|
5576 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5577 PIPE_CONTROL_WRITE_TIMESTAMP
|
5578 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
5579 PIPE_CONTROL_DEPTH_STALL
|
5580 PIPE_CONTROL_DATA_CACHE_FLUSH
;
5581 if (!(flags
& wa_bits
))
5582 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5585 /* Emit --------------------------------------------------------------- */
5587 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
5588 pc
.LRIPostSyncOperation
= NoLRIOperation
;
5589 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
5590 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
5591 pc
.StoreDataIndex
= 0;
5592 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
5593 pc
.GlobalSnapshotCountReset
=
5594 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
5595 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
5596 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
5597 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5598 pc
.RenderTargetCacheFlushEnable
=
5599 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
5600 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
5601 pc
.StateCacheInvalidationEnable
=
5602 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
5603 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
5604 pc
.ConstantCacheInvalidationEnable
=
5605 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
5606 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
5607 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
5608 pc
.InstructionCacheInvalidateEnable
=
5609 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
5610 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
5611 pc
.IndirectStatePointersDisable
=
5612 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
5613 pc
.TextureCacheInvalidationEnable
=
5614 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
5615 pc
.Address
= rw_bo(bo
, offset
);
5616 pc
.ImmediateData
= imm
;
5621 genX(init_state
)(struct iris_context
*ice
)
5623 struct pipe_context
*ctx
= &ice
->ctx
;
5624 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
5626 ctx
->create_blend_state
= iris_create_blend_state
;
5627 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
5628 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
5629 ctx
->create_sampler_state
= iris_create_sampler_state
;
5630 ctx
->create_sampler_view
= iris_create_sampler_view
;
5631 ctx
->create_surface
= iris_create_surface
;
5632 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
5633 ctx
->bind_blend_state
= iris_bind_blend_state
;
5634 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
5635 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
5636 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
5637 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
5638 ctx
->delete_blend_state
= iris_delete_state
;
5639 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
5640 ctx
->delete_rasterizer_state
= iris_delete_state
;
5641 ctx
->delete_sampler_state
= iris_delete_state
;
5642 ctx
->delete_vertex_elements_state
= iris_delete_state
;
5643 ctx
->set_blend_color
= iris_set_blend_color
;
5644 ctx
->set_clip_state
= iris_set_clip_state
;
5645 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
5646 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
5647 ctx
->set_shader_images
= iris_set_shader_images
;
5648 ctx
->set_sampler_views
= iris_set_sampler_views
;
5649 ctx
->set_tess_state
= iris_set_tess_state
;
5650 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
5651 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
5652 ctx
->set_sample_mask
= iris_set_sample_mask
;
5653 ctx
->set_scissor_states
= iris_set_scissor_states
;
5654 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
5655 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
5656 ctx
->set_viewport_states
= iris_set_viewport_states
;
5657 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
5658 ctx
->surface_destroy
= iris_surface_destroy
;
5659 ctx
->draw_vbo
= iris_draw_vbo
;
5660 ctx
->launch_grid
= iris_launch_grid
;
5661 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
5662 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
5663 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
5665 ice
->vtbl
.destroy_state
= iris_destroy_state
;
5666 ice
->vtbl
.init_render_context
= iris_init_render_context
;
5667 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
5668 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
5669 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
5670 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
5671 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
5672 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
5673 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
5674 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
5675 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
5676 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
5677 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
5678 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
5679 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
5680 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
5681 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
5682 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
5683 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
5684 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
5685 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
5686 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
5687 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
5688 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
5689 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
5690 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
5691 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
5693 ice
->state
.dirty
= ~0ull;
5695 ice
->state
.statistics_counters_enabled
= true;
5697 ice
->state
.sample_mask
= 0xffff;
5698 ice
->state
.num_viewports
= 1;
5699 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
5701 /* Make a 1x1x1 null surface for unbound textures */
5702 void *null_surf_map
=
5703 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
5704 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
5705 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
5706 ice
->state
.unbound_tex
.offset
+=
5707 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
5709 /* Default all scissor rectangles to be empty regions. */
5710 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
5711 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
5712 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,