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[mesa.git] / src / gallium / drivers / iris / iris_state.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25
26 #ifdef HAVE_VALGRIND
27 #include <valgrind.h>
28 #include <memcheck.h>
29 #define VG(x) x
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
31 #else
32 #define VG(x)
33 #endif
34
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "i915_drm.h"
42 #include "intel/compiler/brw_compiler.h"
43 #include "intel/common/gen_l3_config.h"
44 #include "intel/common/gen_sample_positions.h"
45 #include "iris_batch.h"
46 #include "iris_context.h"
47 #include "iris_pipe.h"
48 #include "iris_resource.h"
49
50 #define __gen_address_type struct iris_address
51 #define __gen_user_data struct iris_batch
52
53 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
54
55 static uint64_t
56 __gen_combine_address(struct iris_batch *batch, void *location,
57 struct iris_address addr, uint32_t delta)
58 {
59 if (addr.bo == NULL)
60 return addr.offset + delta;
61
62 return iris_batch_reloc(batch, location - batch->cmdbuf.map, addr.bo,
63 addr.offset + delta, addr.reloc_flags);
64 }
65
66 #define __genxml_cmd_length(cmd) cmd ## _length
67 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
68 #define __genxml_cmd_header(cmd) cmd ## _header
69 #define __genxml_cmd_pack(cmd) cmd ## _pack
70
71 static void *
72 get_command_space(struct iris_batch *batch, unsigned bytes)
73 {
74 iris_require_command_space(batch, bytes);
75 void *map = batch->cmdbuf.map_next;
76 batch->cmdbuf.map_next += bytes;
77 return map;
78 }
79
80 #define _iris_pack_command(batch, cmd, dst, name) \
81 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
82 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
83 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
84 _dst = NULL; \
85 }))
86
87 #define iris_pack_command(cmd, dst, name) \
88 _iris_pack_command(NULL, cmd, dst, name)
89
90 #define iris_pack_state(cmd, dst, name) \
91 for (struct cmd name = {}, \
92 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
93 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
94 _dst = NULL)
95
96 #define iris_emit_cmd(batch, cmd, name) \
97 _iris_pack_command(batch, cmd, get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
98
99 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
100 do { \
101 uint32_t *dw = get_command_space(batch, 4 * num_dwords); \
102 for (uint32_t i = 0; i < num_dwords; i++) \
103 dw[i] = (dwords0)[i] | (dwords1)[i]; \
104 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
105 } while (0)
106
107 #define iris_emit_with_addr(batch, dwords, num_dw, addr_field, addr) \
108 do { \
109 STATIC_ASSERT((GENX(addr_field) % 64) == 0); \
110 assert(num_dw <= ARRAY_SIZE(dwords)); \
111 int addr_idx = GENX(addr_field) / 32; \
112 uint32_t *dw = get_command_space(batch, 4 * num_dw); \
113 for (uint32_t i = 0; i < addr_idx; i++) { \
114 dw[i] = (dwords)[i]; \
115 } \
116 uint64_t *qw = (uint64_t *) &dw[addr_idx]; \
117 qw = iris_batch_reloc(batch, qw - batch->cmdbuf.map, addr.bo, \
118 addr.offset + (dwords)[addr_idx + 1], \
119 addr.reloc_flags); \
120 for (uint32_t i = addr_idx + 1; i < num_dw; i++) { \
121 dw[i] = (dwords)[i]; \
122 } \
123 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dw * 4)); \
124 } while (0)
125
126 #include "genxml/genX_pack.h"
127 #include "genxml/gen_macros.h"
128 #include "genxml/genX_bits.h"
129
130 #define MOCS_WB (2 << 1)
131
132 UNUSED static void pipe_asserts()
133 {
134 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
135
136 /* pipe_logicop happens to match the hardware. */
137 PIPE_ASSERT(PIPE_LOGICOP_CLEAR == LOGICOP_CLEAR);
138 PIPE_ASSERT(PIPE_LOGICOP_NOR == LOGICOP_NOR);
139 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED == LOGICOP_AND_INVERTED);
140 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED == LOGICOP_COPY_INVERTED);
141 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE == LOGICOP_AND_REVERSE);
142 PIPE_ASSERT(PIPE_LOGICOP_INVERT == LOGICOP_INVERT);
143 PIPE_ASSERT(PIPE_LOGICOP_XOR == LOGICOP_XOR);
144 PIPE_ASSERT(PIPE_LOGICOP_NAND == LOGICOP_NAND);
145 PIPE_ASSERT(PIPE_LOGICOP_AND == LOGICOP_AND);
146 PIPE_ASSERT(PIPE_LOGICOP_EQUIV == LOGICOP_EQUIV);
147 PIPE_ASSERT(PIPE_LOGICOP_NOOP == LOGICOP_NOOP);
148 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED == LOGICOP_OR_INVERTED);
149 PIPE_ASSERT(PIPE_LOGICOP_COPY == LOGICOP_COPY);
150 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE == LOGICOP_OR_REVERSE);
151 PIPE_ASSERT(PIPE_LOGICOP_OR == LOGICOP_OR);
152 PIPE_ASSERT(PIPE_LOGICOP_SET == LOGICOP_SET);
153
154 /* pipe_blend_func happens to match the hardware. */
155 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE == BLENDFACTOR_ONE);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR == BLENDFACTOR_SRC_COLOR);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA == BLENDFACTOR_SRC_ALPHA);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA == BLENDFACTOR_DST_ALPHA);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR == BLENDFACTOR_DST_COLOR);
160 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE == BLENDFACTOR_SRC_ALPHA_SATURATE);
161 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR == BLENDFACTOR_CONST_COLOR);
162 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA == BLENDFACTOR_CONST_ALPHA);
163 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR == BLENDFACTOR_SRC1_COLOR);
164 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA == BLENDFACTOR_SRC1_ALPHA);
165 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO == BLENDFACTOR_ZERO);
166 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR == BLENDFACTOR_INV_SRC_COLOR);
167 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA == BLENDFACTOR_INV_SRC_ALPHA);
168 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA == BLENDFACTOR_INV_DST_ALPHA);
169 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR == BLENDFACTOR_INV_DST_COLOR);
170 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR == BLENDFACTOR_INV_CONST_COLOR);
171 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA == BLENDFACTOR_INV_CONST_ALPHA);
172 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR == BLENDFACTOR_INV_SRC1_COLOR);
173 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA == BLENDFACTOR_INV_SRC1_ALPHA);
174
175 /* pipe_blend_func happens to match the hardware. */
176 PIPE_ASSERT(PIPE_BLEND_ADD == BLENDFUNCTION_ADD);
177 PIPE_ASSERT(PIPE_BLEND_SUBTRACT == BLENDFUNCTION_SUBTRACT);
178 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT == BLENDFUNCTION_REVERSE_SUBTRACT);
179 PIPE_ASSERT(PIPE_BLEND_MIN == BLENDFUNCTION_MIN);
180 PIPE_ASSERT(PIPE_BLEND_MAX == BLENDFUNCTION_MAX);
181
182 /* pipe_stencil_op happens to match the hardware. */
183 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP == STENCILOP_KEEP);
184 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO == STENCILOP_ZERO);
185 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE == STENCILOP_REPLACE);
186 PIPE_ASSERT(PIPE_STENCIL_OP_INCR == STENCILOP_INCRSAT);
187 PIPE_ASSERT(PIPE_STENCIL_OP_DECR == STENCILOP_DECRSAT);
188 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP == STENCILOP_INCR);
189 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP == STENCILOP_DECR);
190 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT == STENCILOP_INVERT);
191 #undef PIPE_ASSERT
192 }
193
194 static unsigned
195 translate_prim_type(enum pipe_prim_type prim, uint8_t verts_per_patch)
196 {
197 static const unsigned map[] = {
198 [PIPE_PRIM_POINTS] = _3DPRIM_POINTLIST,
199 [PIPE_PRIM_LINES] = _3DPRIM_LINELIST,
200 [PIPE_PRIM_LINE_LOOP] = _3DPRIM_LINELOOP,
201 [PIPE_PRIM_LINE_STRIP] = _3DPRIM_LINESTRIP,
202 [PIPE_PRIM_TRIANGLES] = _3DPRIM_TRILIST,
203 [PIPE_PRIM_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
204 [PIPE_PRIM_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
205 [PIPE_PRIM_QUADS] = _3DPRIM_QUADLIST,
206 [PIPE_PRIM_QUAD_STRIP] = _3DPRIM_QUADSTRIP,
207 [PIPE_PRIM_POLYGON] = _3DPRIM_POLYGON,
208 [PIPE_PRIM_LINES_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
209 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
210 [PIPE_PRIM_TRIANGLES_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
211 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
212 [PIPE_PRIM_PATCHES] = _3DPRIM_PATCHLIST_1 - 1,
213 };
214
215 return map[prim] + (prim == PIPE_PRIM_PATCHES ? verts_per_patch : 0);
216 }
217
218 static unsigned
219 translate_compare_func(enum pipe_compare_func pipe_func)
220 {
221 static const unsigned map[] = {
222 [PIPE_FUNC_NEVER] = COMPAREFUNCTION_NEVER,
223 [PIPE_FUNC_LESS] = COMPAREFUNCTION_LESS,
224 [PIPE_FUNC_EQUAL] = COMPAREFUNCTION_EQUAL,
225 [PIPE_FUNC_LEQUAL] = COMPAREFUNCTION_LEQUAL,
226 [PIPE_FUNC_GREATER] = COMPAREFUNCTION_GREATER,
227 [PIPE_FUNC_NOTEQUAL] = COMPAREFUNCTION_NOTEQUAL,
228 [PIPE_FUNC_GEQUAL] = COMPAREFUNCTION_GEQUAL,
229 [PIPE_FUNC_ALWAYS] = COMPAREFUNCTION_ALWAYS,
230 };
231 return map[pipe_func];
232 }
233
234 static unsigned
235 translate_shadow_func(enum pipe_compare_func pipe_func)
236 {
237 /* Gallium specifies the result of shadow comparisons as:
238 *
239 * 1 if ref <op> texel,
240 * 0 otherwise.
241 *
242 * The hardware does:
243 *
244 * 0 if texel <op> ref,
245 * 1 otherwise.
246 *
247 * So we need to flip the operator and also negate.
248 */
249 static const unsigned map[] = {
250 [PIPE_FUNC_NEVER] = PREFILTEROPALWAYS,
251 [PIPE_FUNC_LESS] = PREFILTEROPLEQUAL,
252 [PIPE_FUNC_EQUAL] = PREFILTEROPNOTEQUAL,
253 [PIPE_FUNC_LEQUAL] = PREFILTEROPLESS,
254 [PIPE_FUNC_GREATER] = PREFILTEROPGEQUAL,
255 [PIPE_FUNC_NOTEQUAL] = PREFILTEROPEQUAL,
256 [PIPE_FUNC_GEQUAL] = PREFILTEROPGREATER,
257 [PIPE_FUNC_ALWAYS] = PREFILTEROPNEVER,
258 };
259 return map[pipe_func];
260 }
261
262 static unsigned
263 translate_cull_mode(unsigned pipe_face)
264 {
265 static const unsigned map[4] = {
266 [PIPE_FACE_NONE] = CULLMODE_NONE,
267 [PIPE_FACE_FRONT] = CULLMODE_FRONT,
268 [PIPE_FACE_BACK] = CULLMODE_BACK,
269 [PIPE_FACE_FRONT_AND_BACK] = CULLMODE_BOTH,
270 };
271 return map[pipe_face];
272 }
273
274 static unsigned
275 translate_fill_mode(unsigned pipe_polymode)
276 {
277 static const unsigned map[4] = {
278 [PIPE_POLYGON_MODE_FILL] = FILL_MODE_SOLID,
279 [PIPE_POLYGON_MODE_LINE] = FILL_MODE_WIREFRAME,
280 [PIPE_POLYGON_MODE_POINT] = FILL_MODE_POINT,
281 [PIPE_POLYGON_MODE_FILL_RECTANGLE] = FILL_MODE_SOLID,
282 };
283 return map[pipe_polymode];
284 }
285
286 static struct iris_address
287 ro_bo(struct iris_bo *bo, uint32_t offset)
288 {
289 return (struct iris_address) { .bo = bo, .offset = offset };
290 }
291
292 static void
293 iris_emit_state_base_address(struct iris_batch *batch)
294 {
295 /* XXX: PIPE_CONTROLs */
296
297 iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
298 #if 0
299 // XXX: MOCS is stupid for this.
300 sba.GeneralStateMemoryObjectControlState = MOCS_WB;
301 sba.StatelessDataPortAccessMemoryObjectControlState = MOCS_WB;
302 sba.SurfaceStateMemoryObjectControlState = MOCS_WB;
303 sba.DynamicStateMemoryObjectControlState = MOCS_WB;
304 sba.IndirectObjectMemoryObjectControlState = MOCS_WB;
305 sba.InstructionMemoryObjectControlState = MOCS_WB;
306 sba.BindlessSurfaceStateMemoryObjectControlState = MOCS_WB;
307 #endif
308
309 sba.GeneralStateBaseAddressModifyEnable = true;
310 sba.SurfaceStateBaseAddressModifyEnable = true;
311 sba.DynamicStateBaseAddressModifyEnable = true;
312 sba.IndirectObjectBaseAddressModifyEnable = true;
313 sba.InstructionBaseAddressModifyEnable = true;
314 sba.GeneralStateBufferSizeModifyEnable = true;
315 sba.DynamicStateBufferSizeModifyEnable = true;
316 sba.BindlessSurfaceStateBaseAddressModifyEnable = true;
317 sba.IndirectObjectBufferSizeModifyEnable = true;
318 sba.InstructionBuffersizeModifyEnable = true;
319
320 sba.SurfaceStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
321 sba.DynamicStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
322
323 sba.GeneralStateBufferSize = 0xfffff;
324 sba.IndirectObjectBufferSize = 0xfffff;
325 sba.InstructionBufferSize = 0xfffff;
326 sba.DynamicStateBufferSize = ALIGN(MAX_STATE_SIZE, 4096);
327 }
328 }
329
330 static void
331 iris_init_render_context(struct iris_screen *screen,
332 struct iris_batch *batch,
333 struct pipe_debug_callback *dbg)
334 {
335 batch->emit_state_base_address = iris_emit_state_base_address;
336 iris_init_batch(batch, screen, dbg, I915_EXEC_RENDER);
337
338 iris_emit_cmd(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
339 rect.ClippedDrawingRectangleXMax = UINT16_MAX;
340 rect.ClippedDrawingRectangleYMax = UINT16_MAX;
341 }
342 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_PATTERN), pat) {
343 GEN_SAMPLE_POS_1X(pat._1xSample);
344 GEN_SAMPLE_POS_2X(pat._2xSample);
345 GEN_SAMPLE_POS_4X(pat._4xSample);
346 GEN_SAMPLE_POS_8X(pat._8xSample);
347 GEN_SAMPLE_POS_16X(pat._16xSample);
348 }
349 iris_emit_cmd(batch, GENX(3DSTATE_AA_LINE_PARAMETERS), foo);
350 iris_emit_cmd(batch, GENX(3DSTATE_WM_CHROMAKEY), foo);
351 iris_emit_cmd(batch, GENX(3DSTATE_WM_HZ_OP), foo);
352 /* XXX: may need to set an offset for origin-UL framebuffers */
353 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_OFFSET), foo);
354
355 /* Just assign a static partitioning. */
356 for (int i = 0; i <= MESA_SHADER_FRAGMENT; i++) {
357 iris_emit_cmd(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) {
358 alloc._3DCommandSubOpcode = 18 + i;
359 alloc.ConstantBufferOffset = 6 * i;
360 alloc.ConstantBufferSize = i == MESA_SHADER_FRAGMENT ? 8 : 6;
361 }
362 }
363 }
364
365 static void
366 iris_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *info)
367 {
368 }
369
370 static void
371 iris_set_blend_color(struct pipe_context *ctx,
372 const struct pipe_blend_color *state)
373 {
374 struct iris_context *ice = (struct iris_context *) ctx;
375
376 memcpy(&ice->state.blend_color, state, sizeof(struct pipe_blend_color));
377 ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE;
378 }
379
380 struct iris_blend_state {
381 uint32_t ps_blend[GENX(3DSTATE_PS_BLEND_length)];
382 uint32_t blend_state[GENX(BLEND_STATE_length) +
383 BRW_MAX_DRAW_BUFFERS * GENX(BLEND_STATE_ENTRY_length)];
384
385 bool alpha_to_coverage; /* for shader key */
386 };
387
388 static void *
389 iris_create_blend_state(struct pipe_context *ctx,
390 const struct pipe_blend_state *state)
391 {
392 struct iris_blend_state *cso = malloc(sizeof(struct iris_blend_state));
393 uint32_t *blend_state = cso->blend_state;
394
395 cso->alpha_to_coverage = state->alpha_to_coverage;
396
397 iris_pack_command(GENX(3DSTATE_PS_BLEND), cso->ps_blend, pb) {
398 /* pb.HasWriteableRT is filled in at draw time. */
399 /* pb.AlphaTestEnable is filled in at draw time. */
400 pb.AlphaToCoverageEnable = state->alpha_to_coverage;
401 pb.IndependentAlphaBlendEnable = state->independent_blend_enable;
402
403 pb.ColorBufferBlendEnable = state->rt[0].blend_enable;
404
405 pb.SourceBlendFactor = state->rt[0].rgb_src_factor;
406 pb.SourceAlphaBlendFactor = state->rt[0].alpha_func;
407 pb.DestinationBlendFactor = state->rt[0].rgb_dst_factor;
408 pb.DestinationAlphaBlendFactor = state->rt[0].alpha_dst_factor;
409 }
410
411 iris_pack_state(GENX(BLEND_STATE), blend_state, bs) {
412 bs.AlphaToCoverageEnable = state->alpha_to_coverage;
413 bs.IndependentAlphaBlendEnable = state->independent_blend_enable;
414 bs.AlphaToOneEnable = state->alpha_to_one;
415 bs.AlphaToCoverageDitherEnable = state->alpha_to_coverage;
416 bs.ColorDitherEnable = state->dither;
417 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
418 }
419
420 blend_state += GENX(BLEND_STATE_length);
421
422 for (int i = 0; i < BRW_MAX_DRAW_BUFFERS; i++) {
423 iris_pack_state(GENX(BLEND_STATE_ENTRY), blend_state, be) {
424 be.LogicOpEnable = state->logicop_enable;
425 be.LogicOpFunction = state->logicop_func;
426
427 be.PreBlendSourceOnlyClampEnable = false;
428 be.ColorClampRange = COLORCLAMP_RTFORMAT;
429 be.PreBlendColorClampEnable = true;
430 be.PostBlendColorClampEnable = true;
431
432 be.ColorBufferBlendEnable = state->rt[i].blend_enable;
433
434 be.ColorBlendFunction = state->rt[i].rgb_func;
435 be.AlphaBlendFunction = state->rt[i].alpha_func;
436 be.SourceBlendFactor = state->rt[i].rgb_src_factor;
437 be.SourceAlphaBlendFactor = state->rt[i].alpha_func;
438 be.DestinationBlendFactor = state->rt[i].rgb_dst_factor;
439 be.DestinationAlphaBlendFactor = state->rt[i].alpha_dst_factor;
440
441 be.WriteDisableRed = state->rt[i].colormask & PIPE_MASK_R;
442 be.WriteDisableGreen = state->rt[i].colormask & PIPE_MASK_G;
443 be.WriteDisableBlue = state->rt[i].colormask & PIPE_MASK_B;
444 be.WriteDisableAlpha = state->rt[i].colormask & PIPE_MASK_A;
445 }
446 blend_state += GENX(BLEND_STATE_ENTRY_length);
447 }
448
449 return cso;
450 }
451
452 static void
453 iris_bind_blend_state(struct pipe_context *ctx, void *state)
454 {
455 struct iris_context *ice = (struct iris_context *) ctx;
456 ice->state.cso_blend = state;
457 ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
458 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
459 }
460
461 struct iris_depth_stencil_alpha_state {
462 uint32_t wmds[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
463 uint32_t cc_vp[GENX(CC_VIEWPORT_length)];
464
465 struct pipe_alpha_state alpha; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
466 };
467
468 static void *
469 iris_create_zsa_state(struct pipe_context *ctx,
470 const struct pipe_depth_stencil_alpha_state *state)
471 {
472 struct iris_depth_stencil_alpha_state *cso =
473 malloc(sizeof(struct iris_depth_stencil_alpha_state));
474
475 cso->alpha = state->alpha;
476
477 bool two_sided_stencil = state->stencil[1].enabled;
478
479 /* The state tracker needs to optimize away EQUAL writes for us. */
480 assert(!(state->depth.func == PIPE_FUNC_EQUAL && state->depth.writemask));
481
482 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), cso->wmds, wmds) {
483 wmds.StencilFailOp = state->stencil[0].fail_op;
484 wmds.StencilPassDepthFailOp = state->stencil[0].zfail_op;
485 wmds.StencilPassDepthPassOp = state->stencil[0].zpass_op;
486 wmds.StencilTestFunction =
487 translate_compare_func(state->stencil[0].func);
488 wmds.BackfaceStencilFailOp = state->stencil[1].fail_op;
489 wmds.BackfaceStencilPassDepthFailOp = state->stencil[1].zfail_op;
490 wmds.BackfaceStencilPassDepthPassOp = state->stencil[1].zpass_op;
491 wmds.BackfaceStencilTestFunction =
492 translate_compare_func(state->stencil[1].func);
493 wmds.DepthTestFunction = translate_compare_func(state->depth.func);
494 wmds.DoubleSidedStencilEnable = two_sided_stencil;
495 wmds.StencilTestEnable = state->stencil[0].enabled;
496 wmds.StencilBufferWriteEnable =
497 state->stencil[0].writemask != 0 ||
498 (two_sided_stencil && state->stencil[1].writemask != 0);
499 wmds.DepthTestEnable = state->depth.enabled;
500 wmds.DepthBufferWriteEnable = state->depth.writemask;
501 wmds.StencilTestMask = state->stencil[0].valuemask;
502 wmds.StencilWriteMask = state->stencil[0].writemask;
503 wmds.BackfaceStencilTestMask = state->stencil[1].valuemask;
504 wmds.BackfaceStencilWriteMask = state->stencil[1].writemask;
505 /* wmds.[Backface]StencilReferenceValue are merged later */
506 }
507
508 iris_pack_state(GENX(CC_VIEWPORT), cso->cc_vp, ccvp) {
509 ccvp.MinimumDepth = state->depth.bounds_min;
510 ccvp.MaximumDepth = state->depth.bounds_max;
511 }
512
513 return cso;
514 }
515
516 static void
517 iris_bind_zsa_state(struct pipe_context *ctx, void *state)
518 {
519 struct iris_context *ice = (struct iris_context *) ctx;
520 struct iris_depth_stencil_alpha_state *old_cso = ice->state.cso_zsa;
521 struct iris_depth_stencil_alpha_state *new_cso = state;
522
523 if (new_cso) {
524 if (!old_cso || old_cso->alpha.ref_value != new_cso->alpha.ref_value) {
525 ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE;
526 }
527 }
528
529 ice->state.cso_zsa = new_cso;
530 ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
531 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
532 }
533
534 struct iris_rasterizer_state {
535 uint32_t sf[GENX(3DSTATE_SF_length)];
536 uint32_t clip[GENX(3DSTATE_CLIP_length)];
537 uint32_t raster[GENX(3DSTATE_RASTER_length)];
538 uint32_t wm[GENX(3DSTATE_WM_length)];
539 uint32_t line_stipple[GENX(3DSTATE_LINE_STIPPLE_length)];
540
541 bool flatshade; /* for shader state */
542 bool clamp_fragment_color; /* for shader state */
543 bool light_twoside; /* for shader state */
544 bool rasterizer_discard; /* for 3DSTATE_STREAMOUT */
545 bool half_pixel_center; /* for 3DSTATE_MULTISAMPLE */
546 enum pipe_sprite_coord_mode sprite_coord_mode; /* PIPE_SPRITE_* */
547 };
548
549 static void *
550 iris_create_rasterizer_state(struct pipe_context *ctx,
551 const struct pipe_rasterizer_state *state)
552 {
553 struct iris_rasterizer_state *cso =
554 malloc(sizeof(struct iris_rasterizer_state));
555
556 #if 0
557 sprite_coord_mode -> SBE PointSpriteTextureCoordinateOrigin
558 sprite_coord_enable -> SBE PointSpriteTextureCoordinateEnable
559 point_quad_rasterization -> SBE?
560
561 not necessary?
562 {
563 poly_smooth
564 force_persample_interp - ?
565 bottom_edge_rule
566
567 offset_units_unscaled - cap not exposed
568 }
569 #endif
570
571 cso->flatshade = state->flatshade;
572 cso->clamp_fragment_color = state->clamp_fragment_color;
573 cso->light_twoside = state->light_twoside;
574 cso->rasterizer_discard = state->rasterizer_discard;
575 cso->half_pixel_center = state->half_pixel_center;
576
577 iris_pack_command(GENX(3DSTATE_SF), cso->sf, sf) {
578 sf.StatisticsEnable = true;
579 sf.ViewportTransformEnable = true;
580 sf.AALineDistanceMode = AALINEDISTANCE_TRUE;
581 sf.LineEndCapAntialiasingRegionWidth =
582 state->line_smooth ? _10pixels : _05pixels;
583 sf.LastPixelEnable = state->line_last_pixel;
584 sf.LineWidth = state->line_width;
585 sf.SmoothPointEnable = state->point_smooth;
586 sf.PointWidthSource = state->point_size_per_vertex ? Vertex : State;
587 sf.PointWidth = state->point_size;
588
589 if (state->flatshade_first) {
590 sf.TriangleStripListProvokingVertexSelect = 2;
591 sf.TriangleFanProvokingVertexSelect = 2;
592 sf.LineStripListProvokingVertexSelect = 1;
593 } else {
594 sf.TriangleFanProvokingVertexSelect = 1;
595 }
596 }
597
598 /* COMPLETE! */
599 iris_pack_command(GENX(3DSTATE_RASTER), cso->raster, rr) {
600 rr.FrontWinding = state->front_ccw ? CounterClockwise : Clockwise;
601 rr.CullMode = translate_cull_mode(state->cull_face);
602 rr.FrontFaceFillMode = translate_fill_mode(state->fill_front);
603 rr.BackFaceFillMode = translate_fill_mode(state->fill_back);
604 rr.DXMultisampleRasterizationEnable = state->multisample;
605 rr.GlobalDepthOffsetEnableSolid = state->offset_tri;
606 rr.GlobalDepthOffsetEnableWireframe = state->offset_line;
607 rr.GlobalDepthOffsetEnablePoint = state->offset_point;
608 rr.GlobalDepthOffsetConstant = state->offset_units;
609 rr.GlobalDepthOffsetScale = state->offset_scale;
610 rr.GlobalDepthOffsetClamp = state->offset_clamp;
611 rr.SmoothPointEnable = state->point_smooth;
612 rr.AntialiasingEnable = state->line_smooth;
613 rr.ScissorRectangleEnable = state->scissor;
614 rr.ViewportZNearClipTestEnable = state->depth_clip_near;
615 rr.ViewportZFarClipTestEnable = state->depth_clip_far;
616 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
617 }
618
619 iris_pack_command(GENX(3DSTATE_CLIP), cso->clip, cl) {
620 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
621 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
622 */
623 cl.StatisticsEnable = true;
624 cl.EarlyCullEnable = true;
625 cl.UserClipDistanceClipTestEnableBitmask = state->clip_plane_enable;
626 cl.ForceUserClipDistanceClipTestEnableBitmask = true;
627 cl.APIMode = state->clip_halfz ? APIMODE_D3D : APIMODE_OGL;
628 cl.GuardbandClipTestEnable = true;
629 cl.ClipMode = CLIPMODE_NORMAL;
630 cl.ClipEnable = true;
631 cl.ViewportXYClipTestEnable = state->point_tri_clip;
632 cl.MinimumPointWidth = 0.125;
633 cl.MaximumPointWidth = 255.875;
634
635 if (state->flatshade_first) {
636 cl.TriangleStripListProvokingVertexSelect = 2;
637 cl.TriangleFanProvokingVertexSelect = 2;
638 cl.LineStripListProvokingVertexSelect = 1;
639 } else {
640 cl.TriangleFanProvokingVertexSelect = 1;
641 }
642 }
643
644 iris_pack_command(GENX(3DSTATE_WM), cso->wm, wm) {
645 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
646 * filled in at draw time from the FS program.
647 */
648 wm.LineAntialiasingRegionWidth = _10pixels;
649 wm.LineEndCapAntialiasingRegionWidth = _05pixels;
650 wm.PointRasterizationRule = RASTRULE_UPPER_RIGHT;
651 wm.StatisticsEnable = true;
652 wm.LineStippleEnable = state->line_stipple_enable;
653 wm.PolygonStippleEnable = state->poly_stipple_enable;
654 }
655
656 /* Remap from 0..255 back to 1..256 */
657 const unsigned line_stipple_factor = state->line_stipple_factor + 1;
658
659 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE), cso->line_stipple, line) {
660 line.LineStipplePattern = state->line_stipple_pattern;
661 line.LineStippleInverseRepeatCount = 1.0f / line_stipple_factor;
662 line.LineStippleRepeatCount = line_stipple_factor;
663 }
664
665 return cso;
666 }
667
668 static void
669 iris_bind_rasterizer_state(struct pipe_context *ctx, void *state)
670 {
671 struct iris_context *ice = (struct iris_context *) ctx;
672 struct iris_rasterizer_state *old_cso = ice->state.cso_rast;
673 struct iris_rasterizer_state *new_cso = state;
674
675 if (new_cso) {
676 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
677 if (!old_cso || memcmp(old_cso->line_stipple, new_cso->line_stipple,
678 sizeof(old_cso->line_stipple)) != 0) {
679 ice->state.dirty |= IRIS_DIRTY_LINE_STIPPLE;
680 }
681
682 if (!old_cso ||
683 old_cso->half_pixel_center != new_cso->half_pixel_center) {
684 ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
685 }
686 }
687
688 ice->state.cso_rast = new_cso;
689 ice->state.dirty |= IRIS_DIRTY_RASTER;
690 }
691
692 static uint32_t
693 translate_wrap(unsigned pipe_wrap)
694 {
695 static const unsigned map[] = {
696 [PIPE_TEX_WRAP_REPEAT] = TCM_WRAP,
697 [PIPE_TEX_WRAP_CLAMP] = TCM_HALF_BORDER,
698 [PIPE_TEX_WRAP_CLAMP_TO_EDGE] = TCM_CLAMP,
699 [PIPE_TEX_WRAP_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
700 [PIPE_TEX_WRAP_MIRROR_REPEAT] = TCM_MIRROR,
701 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
702 [PIPE_TEX_WRAP_MIRROR_CLAMP] = -1, // XXX: ???
703 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER] = -1, // XXX: ???
704 };
705 return map[pipe_wrap];
706 }
707
708 /**
709 * Return true if the given wrap mode requires the border color to exist.
710 */
711 static bool
712 wrap_mode_needs_border_color(unsigned wrap_mode)
713 {
714 return wrap_mode == TCM_CLAMP_BORDER || wrap_mode == TCM_HALF_BORDER;
715 }
716
717 static unsigned
718 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip)
719 {
720 static const unsigned map[] = {
721 [PIPE_TEX_MIPFILTER_NEAREST] = MIPFILTER_NEAREST,
722 [PIPE_TEX_MIPFILTER_LINEAR] = MIPFILTER_LINEAR,
723 [PIPE_TEX_MIPFILTER_NONE] = MIPFILTER_NONE,
724 };
725 return map[pipe_mip];
726 }
727
728 struct iris_sampler_state {
729 struct pipe_sampler_state base;
730
731 bool needs_border_color;
732
733 uint32_t sampler_state[GENX(SAMPLER_STATE_length)];
734 };
735
736 static void *
737 iris_create_sampler_state(struct pipe_context *pctx,
738 const struct pipe_sampler_state *state)
739 {
740 struct iris_sampler_state *cso = CALLOC_STRUCT(iris_sampler_state);
741
742 if (!cso)
743 return NULL;
744
745 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST == MAPFILTER_NEAREST);
746 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR == MAPFILTER_LINEAR);
747
748 unsigned wrap_s = translate_wrap(state->wrap_s);
749 unsigned wrap_t = translate_wrap(state->wrap_t);
750 unsigned wrap_r = translate_wrap(state->wrap_r);
751
752 cso->needs_border_color = wrap_mode_needs_border_color(wrap_s) ||
753 wrap_mode_needs_border_color(wrap_t) ||
754 wrap_mode_needs_border_color(wrap_r);
755
756 iris_pack_state(GENX(SAMPLER_STATE), cso->sampler_state, samp) {
757 samp.TCXAddressControlMode = wrap_s;
758 samp.TCYAddressControlMode = wrap_t;
759 samp.TCZAddressControlMode = wrap_r;
760 samp.CubeSurfaceControlMode = state->seamless_cube_map;
761 samp.NonnormalizedCoordinateEnable = !state->normalized_coords;
762 samp.MinModeFilter = state->min_img_filter;
763 samp.MagModeFilter = state->mag_img_filter;
764 samp.MipModeFilter = translate_mip_filter(state->min_mip_filter);
765 samp.MaximumAnisotropy = RATIO21;
766
767 if (state->max_anisotropy >= 2) {
768 if (state->min_img_filter == PIPE_TEX_FILTER_LINEAR) {
769 samp.MinModeFilter = MAPFILTER_ANISOTROPIC;
770 samp.AnisotropicAlgorithm = EWAApproximation;
771 }
772
773 if (state->mag_img_filter == PIPE_TEX_FILTER_LINEAR)
774 samp.MagModeFilter = MAPFILTER_ANISOTROPIC;
775
776 samp.MaximumAnisotropy =
777 MIN2((state->max_anisotropy - 2) / 2, RATIO161);
778 }
779
780 /* Set address rounding bits if not using nearest filtering. */
781 if (state->min_img_filter != PIPE_TEX_FILTER_NEAREST) {
782 samp.UAddressMinFilterRoundingEnable = true;
783 samp.VAddressMinFilterRoundingEnable = true;
784 samp.RAddressMinFilterRoundingEnable = true;
785 }
786
787 if (state->mag_img_filter != PIPE_TEX_FILTER_NEAREST) {
788 samp.UAddressMagFilterRoundingEnable = true;
789 samp.VAddressMagFilterRoundingEnable = true;
790 samp.RAddressMagFilterRoundingEnable = true;
791 }
792
793 if (state->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
794 samp.ShadowFunction = translate_shadow_func(state->compare_func);
795
796 const float hw_max_lod = GEN_GEN >= 7 ? 14 : 13;
797
798 samp.LODPreClampMode = CLAMP_MODE_OGL;
799 samp.MinLOD = CLAMP(state->min_lod, 0, hw_max_lod);
800 samp.MaxLOD = CLAMP(state->max_lod, 0, hw_max_lod);
801 samp.TextureLODBias = CLAMP(state->lod_bias, -16, 15);
802
803 //samp.BorderColorPointer = <<comes from elsewhere>>
804 }
805
806 return cso;
807 }
808
809 static void
810 iris_bind_sampler_states(struct pipe_context *ctx,
811 enum pipe_shader_type p_stage,
812 unsigned start, unsigned count,
813 void **states)
814 {
815 struct iris_context *ice = (struct iris_context *) ctx;
816 gl_shader_stage stage = stage_from_pipe(p_stage);
817
818 assert(start + count <= IRIS_MAX_TEXTURE_SAMPLERS);
819
820 for (int i = 0; i < count; i++) {
821 ice->state.samplers[stage][start + i] = states[i];
822 }
823
824 ice->state.dirty |= IRIS_DIRTY_SAMPLER_STATES_VS << stage;
825 }
826
827 struct iris_sampler_view {
828 struct pipe_sampler_view pipe;
829 struct isl_view view;
830 uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
831 };
832
833 /**
834 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
835 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
836 *
837 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
838 * 0 1 2 3 4 5
839 * 4 5 6 7 0 1
840 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
841 *
842 * which is simply adding 4 then modding by 8 (or anding with 7).
843 *
844 * We then may need to apply workarounds for textureGather hardware bugs.
845 */
846 static enum isl_channel_select
847 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle)
848 {
849 return (swizzle + 4) & 7;
850 }
851
852 static struct pipe_sampler_view *
853 iris_create_sampler_view(struct pipe_context *ctx,
854 struct pipe_resource *tex,
855 const struct pipe_sampler_view *tmpl)
856 {
857 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
858 struct iris_resource *itex = (struct iris_resource *) tex;
859 struct iris_sampler_view *isv = calloc(1, sizeof(struct iris_sampler_view));
860
861 if (!isv)
862 return NULL;
863
864 /* initialize base object */
865 isv->pipe = *tmpl;
866 isv->pipe.context = ctx;
867 isv->pipe.texture = NULL;
868 pipe_reference_init(&isv->pipe.reference, 1);
869 pipe_resource_reference(&isv->pipe.texture, tex);
870
871 /* XXX: do we need brw_get_texture_swizzle hacks here? */
872
873 isv->view = (struct isl_view) {
874 .format = iris_isl_format_for_pipe_format(tmpl->format),
875 .base_level = tmpl->u.tex.first_level,
876 .levels = tmpl->u.tex.last_level - tmpl->u.tex.first_level + 1,
877 .base_array_layer = tmpl->u.tex.first_layer,
878 .array_len = tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1,
879 .swizzle = (struct isl_swizzle) {
880 .r = pipe_swizzle_to_isl_channel(tmpl->swizzle_r),
881 .g = pipe_swizzle_to_isl_channel(tmpl->swizzle_g),
882 .b = pipe_swizzle_to_isl_channel(tmpl->swizzle_b),
883 .a = pipe_swizzle_to_isl_channel(tmpl->swizzle_a),
884 },
885 .usage = ISL_SURF_USAGE_TEXTURE_BIT,
886 };
887
888 isl_surf_fill_state(&screen->isl_dev, isv->surface_state,
889 .surf = &itex->surf, .view = &isv->view,
890 .mocs = MOCS_WB);
891 // .address = ...
892 // .aux_surf =
893 // .clear_color = clear_color,
894
895 return &isv->pipe;
896 }
897
898 struct iris_surface {
899 struct pipe_surface pipe;
900 struct isl_view view;
901 uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
902 };
903
904 static struct pipe_surface *
905 iris_create_surface(struct pipe_context *ctx,
906 struct pipe_resource *tex,
907 const struct pipe_surface *tmpl)
908 {
909 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
910 struct iris_surface *surf = calloc(1, sizeof(struct iris_surface));
911 struct pipe_surface *psurf = &surf->pipe;
912 struct iris_resource *itex = (struct iris_resource *) tex;
913
914 if (!surf)
915 return NULL;
916
917 pipe_reference_init(&psurf->reference, 1);
918 pipe_resource_reference(&psurf->texture, tex);
919 psurf->context = ctx;
920 psurf->format = tmpl->format;
921 psurf->width = tex->width0;
922 psurf->height = tex->height0;
923 psurf->texture = tex;
924 psurf->u.tex.first_layer = tmpl->u.tex.first_layer;
925 psurf->u.tex.last_layer = tmpl->u.tex.last_layer;
926 psurf->u.tex.level = tmpl->u.tex.level;
927
928 surf->view = (struct isl_view) {
929 .format = iris_isl_format_for_pipe_format(tmpl->format),
930 .base_level = tmpl->u.tex.level,
931 .levels = 1,
932 .base_array_layer = tmpl->u.tex.first_layer,
933 .array_len = tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1,
934 .swizzle = ISL_SWIZZLE_IDENTITY,
935 // XXX: DEPTH_BIt, STENCIL_BIT...CUBE_BIT? Other bits?!
936 .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT,
937 };
938
939 isl_surf_fill_state(&screen->isl_dev, surf->surface_state,
940 .surf = &itex->surf, .view = &surf->view,
941 .mocs = MOCS_WB);
942 // .address = ...
943 // .aux_surf =
944 // .clear_color = clear_color,
945
946 return psurf;
947 }
948
949 static void
950 iris_set_sampler_views(struct pipe_context *ctx,
951 enum pipe_shader_type shader,
952 unsigned start, unsigned count,
953 struct pipe_sampler_view **views)
954 {
955 }
956
957 static void
958 iris_set_clip_state(struct pipe_context *ctx,
959 const struct pipe_clip_state *state)
960 {
961 }
962
963 static void
964 iris_set_polygon_stipple(struct pipe_context *ctx,
965 const struct pipe_poly_stipple *state)
966 {
967 struct iris_context *ice = (struct iris_context *) ctx;
968 memcpy(&ice->state.poly_stipple, state, sizeof(*state));
969 ice->state.dirty |= IRIS_DIRTY_POLYGON_STIPPLE;
970 }
971
972 static void
973 iris_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
974 {
975 struct iris_context *ice = (struct iris_context *) ctx;
976
977 ice->state.sample_mask = sample_mask;
978 ice->state.dirty |= IRIS_DIRTY_SAMPLE_MASK;
979 }
980
981 static void
982 iris_set_scissor_states(struct pipe_context *ctx,
983 unsigned start_slot,
984 unsigned num_scissors,
985 const struct pipe_scissor_state *states)
986 {
987 struct iris_context *ice = (struct iris_context *) ctx;
988
989 ice->state.num_scissors = num_scissors;
990
991 for (unsigned i = 0; i < num_scissors; i++) {
992 ice->state.scissors[start_slot + i] = states[i];
993 }
994
995 ice->state.dirty |= IRIS_DIRTY_SCISSOR_RECT;
996 }
997
998 static void
999 iris_set_stencil_ref(struct pipe_context *ctx,
1000 const struct pipe_stencil_ref *state)
1001 {
1002 struct iris_context *ice = (struct iris_context *) ctx;
1003 memcpy(&ice->state.stencil_ref, state, sizeof(*state));
1004 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
1005 }
1006
1007
1008 struct iris_viewport_state {
1009 uint32_t sf_cl_vp[GENX(SF_CLIP_VIEWPORT_length)];
1010 };
1011
1012 static float
1013 extent_from_matrix(const struct pipe_viewport_state *state, int axis)
1014 {
1015 return fabsf(state->scale[axis]) * state->translate[axis];
1016 }
1017
1018 #if 0
1019 static void
1020 calculate_guardband_size(uint32_t fb_width, uint32_t fb_height,
1021 float m00, float m11, float m30, float m31,
1022 float *xmin, float *xmax,
1023 float *ymin, float *ymax)
1024 {
1025 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1026 * Strips and Fans documentation:
1027 *
1028 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1029 * fixed-point "guardband" range supported by the rasterization hardware"
1030 *
1031 * and
1032 *
1033 * "In almost all circumstances, if an object’s vertices are actually
1034 * modified by this clamping (i.e., had X or Y coordinates outside of
1035 * the guardband extent the rendered object will not match the intended
1036 * result. Therefore software should take steps to ensure that this does
1037 * not happen - e.g., by clipping objects such that they do not exceed
1038 * these limits after the Drawing Rectangle is applied."
1039 *
1040 * I believe the fundamental restriction is that the rasterizer (in
1041 * the SF/WM stages) have a limit on the number of pixels that can be
1042 * rasterized. We need to ensure any coordinates beyond the rasterizer
1043 * limit are handled by the clipper. So effectively that limit becomes
1044 * the clipper's guardband size.
1045 *
1046 * It goes on to say:
1047 *
1048 * "In addition, in order to be correctly rendered, objects must have a
1049 * screenspace bounding box not exceeding 8K in the X or Y direction.
1050 * This additional restriction must also be comprehended by software,
1051 * i.e., enforced by use of clipping."
1052 *
1053 * This makes no sense. Gen7+ hardware supports 16K render targets,
1054 * and you definitely need to be able to draw polygons that fill the
1055 * surface. Our assumption is that the rasterizer was limited to 8K
1056 * on Sandybridge, which only supports 8K surfaces, and it was actually
1057 * increased to 16K on Ivybridge and later.
1058 *
1059 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1060 */
1061 const float gb_size = GEN_GEN >= 7 ? 16384.0f : 8192.0f;
1062
1063 if (m00 != 0 && m11 != 0) {
1064 /* First, we compute the screen-space render area */
1065 const float ss_ra_xmin = MIN3( 0, m30 + m00, m30 - m00);
1066 const float ss_ra_xmax = MAX3( fb_width, m30 + m00, m30 - m00);
1067 const float ss_ra_ymin = MIN3( 0, m31 + m11, m31 - m11);
1068 const float ss_ra_ymax = MAX3(fb_height, m31 + m11, m31 - m11);
1069
1070 /* We want the guardband to be centered on that */
1071 const float ss_gb_xmin = (ss_ra_xmin + ss_ra_xmax) / 2 - gb_size;
1072 const float ss_gb_xmax = (ss_ra_xmin + ss_ra_xmax) / 2 + gb_size;
1073 const float ss_gb_ymin = (ss_ra_ymin + ss_ra_ymax) / 2 - gb_size;
1074 const float ss_gb_ymax = (ss_ra_ymin + ss_ra_ymax) / 2 + gb_size;
1075
1076 /* Now we need it in native device coordinates */
1077 const float ndc_gb_xmin = (ss_gb_xmin - m30) / m00;
1078 const float ndc_gb_xmax = (ss_gb_xmax - m30) / m00;
1079 const float ndc_gb_ymin = (ss_gb_ymin - m31) / m11;
1080 const float ndc_gb_ymax = (ss_gb_ymax - m31) / m11;
1081
1082 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1083 * flipped upside-down. X should be fine though.
1084 */
1085 assert(ndc_gb_xmin <= ndc_gb_xmax);
1086 *xmin = ndc_gb_xmin;
1087 *xmax = ndc_gb_xmax;
1088 *ymin = MIN2(ndc_gb_ymin, ndc_gb_ymax);
1089 *ymax = MAX2(ndc_gb_ymin, ndc_gb_ymax);
1090 } else {
1091 /* The viewport scales to 0, so nothing will be rendered. */
1092 *xmin = 0.0f;
1093 *xmax = 0.0f;
1094 *ymin = 0.0f;
1095 *ymax = 0.0f;
1096 }
1097 }
1098 #endif
1099
1100 static void
1101 iris_set_viewport_states(struct pipe_context *ctx,
1102 unsigned start_slot,
1103 unsigned num_viewports,
1104 const struct pipe_viewport_state *state)
1105 {
1106 struct iris_context *ice = (struct iris_context *) ctx;
1107 struct iris_viewport_state *cso =
1108 malloc(sizeof(struct iris_viewport_state));
1109
1110 // XXX: sf_cl_vp is only big enough for one slot, we don't iterate right
1111 for (unsigned i = start_slot; i < start_slot + num_viewports; i++) {
1112 float x_extent = extent_from_matrix(&state[i], 0);
1113 float y_extent = extent_from_matrix(&state[i], 1);
1114
1115 iris_pack_state(GENX(SF_CLIP_VIEWPORT), cso->sf_cl_vp, vp) {
1116 vp.ViewportMatrixElementm00 = state[i].scale[0];
1117 vp.ViewportMatrixElementm11 = state[i].scale[1];
1118 vp.ViewportMatrixElementm22 = state[i].scale[2];
1119 vp.ViewportMatrixElementm30 = state[i].translate[0];
1120 vp.ViewportMatrixElementm31 = state[i].translate[1];
1121 vp.ViewportMatrixElementm32 = state[i].translate[2];
1122 /* XXX: in i965 this is computed based on the drawbuffer size,
1123 * but we don't have that here...
1124 */
1125 vp.XMinClipGuardband = -1.0;
1126 vp.XMaxClipGuardband = 1.0;
1127 vp.YMinClipGuardband = -1.0;
1128 vp.YMaxClipGuardband = 1.0;
1129 vp.XMinViewPort = -x_extent;
1130 vp.XMaxViewPort = x_extent;
1131 vp.YMinViewPort = -y_extent;
1132 vp.YMaxViewPort = y_extent;
1133 }
1134 }
1135
1136 ice->state.cso_vp = cso;
1137 // XXX: start_slot
1138 ice->state.num_viewports = num_viewports;
1139 ice->state.dirty |= IRIS_DIRTY_SF_CL_VIEWPORT;
1140 }
1141
1142 struct iris_depth_state
1143 {
1144 uint32_t depth_buffer[GENX(3DSTATE_DEPTH_BUFFER_length)];
1145 uint32_t hier_depth_buffer[GENX(3DSTATE_HIER_DEPTH_BUFFER_length)];
1146 uint32_t stencil_buffer[GENX(3DSTATE_STENCIL_BUFFER_length)];
1147 };
1148
1149 static void
1150 iris_set_framebuffer_state(struct pipe_context *ctx,
1151 const struct pipe_framebuffer_state *state)
1152 {
1153 struct iris_context *ice = (struct iris_context *) ctx;
1154 struct pipe_framebuffer_state *cso = &ice->state.framebuffer;
1155
1156 if (cso->samples != state->samples) {
1157 ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
1158 }
1159
1160 cso->width = state->width;
1161 cso->height = state->height;
1162 cso->layers = state->layers;
1163 cso->samples = state->samples;
1164
1165 unsigned i;
1166 for (i = 0; i < state->nr_cbufs; i++)
1167 pipe_surface_reference(&cso->cbufs[i], state->cbufs[i]);
1168 for (; i < cso->nr_cbufs; i++)
1169 pipe_surface_reference(&cso->cbufs[i], NULL);
1170
1171 cso->nr_cbufs = state->nr_cbufs;
1172
1173 pipe_surface_reference(&cso->zsbuf, state->zsbuf);
1174
1175 struct isl_depth_stencil_hiz_emit_info info = {
1176 .mocs = MOCS_WB,
1177 };
1178
1179 // XXX: depth buffers
1180 }
1181
1182 static void
1183 iris_set_constant_buffer(struct pipe_context *ctx,
1184 enum pipe_shader_type shader, uint index,
1185 const struct pipe_constant_buffer *cb)
1186 {
1187 }
1188
1189
1190 static void
1191 iris_sampler_view_destroy(struct pipe_context *ctx,
1192 struct pipe_sampler_view *state)
1193 {
1194 pipe_resource_reference(&state->texture, NULL);
1195 free(state);
1196 }
1197
1198
1199 static void
1200 iris_surface_destroy(struct pipe_context *ctx, struct pipe_surface *surface)
1201 {
1202 pipe_resource_reference(&surface->texture, NULL);
1203 free(surface);
1204 }
1205
1206 static void
1207 iris_delete_state(struct pipe_context *ctx, void *state)
1208 {
1209 free(state);
1210 }
1211
1212 struct iris_vertex_buffer_state {
1213 uint32_t vertex_buffers[1 + 33 * GENX(VERTEX_BUFFER_STATE_length)];
1214 struct iris_address bos[33];
1215 unsigned num_buffers;
1216 };
1217
1218 static void
1219 iris_free_vertex_buffers(struct iris_vertex_buffer_state *cso)
1220 {
1221 if (cso) {
1222 for (unsigned i = 0; i < cso->num_buffers; i++)
1223 iris_bo_unreference(cso->bos[i].bo);
1224 free(cso);
1225 }
1226 }
1227
1228 static void
1229 iris_set_vertex_buffers(struct pipe_context *ctx,
1230 unsigned start_slot, unsigned count,
1231 const struct pipe_vertex_buffer *buffers)
1232 {
1233 struct iris_context *ice = (struct iris_context *) ctx;
1234 struct iris_vertex_buffer_state *cso =
1235 malloc(sizeof(struct iris_vertex_buffer_state));
1236
1237 /* If there are no buffers, do nothing. We can leave the stale
1238 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1239 * elements that point to them, it should be fine.
1240 */
1241 if (!buffers)
1242 return;
1243
1244 iris_free_vertex_buffers(ice->state.cso_vertex_buffers);
1245
1246 cso->num_buffers = count;
1247
1248 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS), cso->vertex_buffers, vb) {
1249 vb.DWordLength = 4 * cso->num_buffers - 1;
1250 }
1251
1252 uint32_t *vb_pack_dest = &cso->vertex_buffers[1];
1253
1254 for (unsigned i = 0; i < count; i++) {
1255 assert(!buffers[i].is_user_buffer);
1256
1257 struct iris_resource *res = (void *) buffers[i].buffer.resource;
1258 iris_bo_reference(res->bo);
1259 cso->bos[i] = ro_bo(res->bo, buffers[i].buffer_offset);
1260
1261 iris_pack_state(GENX(VERTEX_BUFFER_STATE), vb_pack_dest, vb) {
1262 vb.VertexBufferIndex = start_slot + i;
1263 vb.MOCS = MOCS_WB;
1264 vb.AddressModifyEnable = true;
1265 vb.BufferPitch = buffers[i].stride;
1266 vb.BufferSize = res->bo->size;
1267 /* vb.BufferStartingAddress is filled in at draw time */
1268 }
1269
1270 vb_pack_dest += GENX(VERTEX_BUFFER_STATE_length);
1271 }
1272
1273 ice->state.cso_vertex_buffers = cso;
1274 ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS;
1275 }
1276
1277 struct iris_vertex_element_state {
1278 uint32_t vertex_elements[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length)];
1279 uint32_t vf_instancing[GENX(3DSTATE_VF_INSTANCING_length)][33];
1280 unsigned count;
1281 };
1282
1283 static void *
1284 iris_create_vertex_elements(struct pipe_context *ctx,
1285 unsigned count,
1286 const struct pipe_vertex_element *state)
1287 {
1288 struct iris_vertex_element_state *cso =
1289 malloc(sizeof(struct iris_vertex_element_state));
1290
1291 cso->count = count;
1292
1293 /* TODO:
1294 * - create edge flag one
1295 * - create SGV ones
1296 * - if those are necessary, use count + 1/2/3... OR in the length
1297 */
1298 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS), cso->vertex_elements, ve);
1299
1300 uint32_t *ve_pack_dest = &cso->vertex_elements[1];
1301
1302 for (int i = 0; i < count; i++) {
1303 iris_pack_state(GENX(VERTEX_ELEMENT_STATE), ve_pack_dest, ve) {
1304 ve.VertexBufferIndex = state[i].vertex_buffer_index;
1305 ve.Valid = true;
1306 ve.SourceElementOffset = state[i].src_offset;
1307 ve.SourceElementFormat =
1308 iris_isl_format_for_pipe_format(state[i].src_format);
1309 }
1310
1311 iris_pack_command(GENX(3DSTATE_VF_INSTANCING), cso->vf_instancing[i], vi) {
1312 vi.VertexElementIndex = i;
1313 vi.InstancingEnable = state[i].instance_divisor > 0;
1314 vi.InstanceDataStepRate = state[i].instance_divisor;
1315 }
1316
1317 ve_pack_dest += GENX(VERTEX_ELEMENT_STATE_length);
1318 }
1319
1320 return cso;
1321 }
1322
1323 static void
1324 iris_bind_vertex_elements_state(struct pipe_context *ctx, void *state)
1325 {
1326 struct iris_context *ice = (struct iris_context *) ctx;
1327
1328 ice->state.cso_vertex_elements = state;
1329 ice->state.dirty |= IRIS_DIRTY_VERTEX_ELEMENTS;
1330 }
1331
1332 static void *
1333 iris_create_compute_state(struct pipe_context *ctx,
1334 const struct pipe_compute_state *state)
1335 {
1336 return malloc(1);
1337 }
1338
1339 static struct pipe_stream_output_target *
1340 iris_create_stream_output_target(struct pipe_context *ctx,
1341 struct pipe_resource *res,
1342 unsigned buffer_offset,
1343 unsigned buffer_size)
1344 {
1345 struct pipe_stream_output_target *t =
1346 CALLOC_STRUCT(pipe_stream_output_target);
1347 if (!t)
1348 return NULL;
1349
1350 pipe_reference_init(&t->reference, 1);
1351 pipe_resource_reference(&t->buffer, res);
1352 t->buffer_offset = buffer_offset;
1353 t->buffer_size = buffer_size;
1354 return t;
1355 }
1356
1357 static void
1358 iris_stream_output_target_destroy(struct pipe_context *ctx,
1359 struct pipe_stream_output_target *t)
1360 {
1361 pipe_resource_reference(&t->buffer, NULL);
1362 free(t);
1363 }
1364
1365 static void
1366 iris_set_stream_output_targets(struct pipe_context *ctx,
1367 unsigned num_targets,
1368 struct pipe_stream_output_target **targets,
1369 const unsigned *offsets)
1370 {
1371 }
1372
1373 static void
1374 iris_bind_compute_state(struct pipe_context *ctx, void *state)
1375 {
1376 }
1377
1378 static void
1379 iris_populate_vs_key(const struct iris_context *ice,
1380 struct brw_vs_prog_key *key)
1381 {
1382 memset(key, 0, sizeof(*key));
1383 }
1384
1385 static void
1386 iris_populate_tcs_key(const struct iris_context *ice,
1387 struct brw_tcs_prog_key *key)
1388 {
1389 memset(key, 0, sizeof(*key));
1390 }
1391
1392 static void
1393 iris_populate_tes_key(const struct iris_context *ice,
1394 struct brw_tes_prog_key *key)
1395 {
1396 memset(key, 0, sizeof(*key));
1397 }
1398
1399 static void
1400 iris_populate_gs_key(const struct iris_context *ice,
1401 struct brw_gs_prog_key *key)
1402 {
1403 memset(key, 0, sizeof(*key));
1404 }
1405
1406 static void
1407 iris_populate_fs_key(const struct iris_context *ice,
1408 struct brw_wm_prog_key *key)
1409 {
1410 memset(key, 0, sizeof(*key));
1411
1412 /* XXX: dirty flags? */
1413 struct pipe_framebuffer_state *fb = &ice->state.framebuffer;
1414 struct iris_depth_stencil_alpha_state *zsa = ice->state.cso_zsa;
1415 struct iris_rasterizer_state *rast = ice->state.cso_rast;
1416 struct iris_blend_state *blend = ice->state.cso_blend;
1417
1418 key->nr_color_regions = fb->nr_cbufs;
1419
1420 key->clamp_fragment_color = rast->clamp_fragment_color;
1421
1422 key->replicate_alpha = fb->nr_cbufs > 1 &&
1423 (zsa->alpha.enabled || blend->alpha_to_coverage);
1424
1425 // key->force_dual_color_blend for unigine
1426 #if 0
1427 if (cso_rast->multisample) {
1428 key->persample_interp =
1429 ctx->Multisample.SampleShading &&
1430 (ctx->Multisample.MinSampleShadingValue *
1431 _mesa_geometric_samples(ctx->DrawBuffer) > 1);
1432
1433 key->multisample_fbo = fb->samples > 1;
1434 }
1435 #endif
1436
1437 key->coherent_fb_fetch = true;
1438 }
1439
1440 //pkt.SamplerCount = \
1441 //DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1442 //pkt.PerThreadScratchSpace = prog_data->total_scratch == 0 ? 0 : \
1443 //ffs(stage_state->per_thread_scratch) - 11; \
1444
1445 static uint64_t
1446 KSP(const struct iris_compiled_shader *shader)
1447 {
1448 struct iris_resource *res = (void *) shader->buffer;
1449 return res->bo->gtt_offset + shader->offset;
1450 }
1451
1452 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1453 pkt.KernelStartPointer = KSP(shader); \
1454 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
1455 pkt.FloatingPointMode = prog_data->use_alt_mode; \
1456 \
1457 pkt.DispatchGRFStartRegisterForURBData = \
1458 prog_data->dispatch_grf_start_reg; \
1459 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1460 pkt.prefix##URBEntryReadOffset = 0; \
1461 \
1462 pkt.StatisticsEnable = true; \
1463 pkt.Enable = true;
1464
1465 static void
1466 iris_set_vs_state(const struct gen_device_info *devinfo,
1467 struct iris_compiled_shader *shader)
1468 {
1469 struct brw_stage_prog_data *prog_data = shader->prog_data;
1470 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1471
1472 iris_pack_command(GENX(3DSTATE_VS), shader->derived_data, vs) {
1473 INIT_THREAD_DISPATCH_FIELDS(vs, Vertex);
1474 vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
1475 vs.SIMD8DispatchEnable = true;
1476 vs.UserClipDistanceCullTestEnableBitmask =
1477 vue_prog_data->cull_distance_mask;
1478 }
1479 }
1480
1481 static void
1482 iris_set_tcs_state(const struct gen_device_info *devinfo,
1483 struct iris_compiled_shader *shader)
1484 {
1485 struct brw_stage_prog_data *prog_data = shader->prog_data;
1486 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1487 struct brw_tcs_prog_data *tcs_prog_data = (void *) prog_data;
1488
1489 iris_pack_command(GENX(3DSTATE_HS), shader->derived_data, hs) {
1490 INIT_THREAD_DISPATCH_FIELDS(hs, Vertex);
1491
1492 hs.InstanceCount = tcs_prog_data->instances - 1;
1493 hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
1494 hs.IncludeVertexHandles = true;
1495 }
1496 }
1497
1498 static void
1499 iris_set_tes_state(const struct gen_device_info *devinfo,
1500 struct iris_compiled_shader *shader)
1501 {
1502 struct brw_stage_prog_data *prog_data = shader->prog_data;
1503 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1504 struct brw_tes_prog_data *tes_prog_data = (void *) prog_data;
1505
1506 uint32_t *te_state = (void *) shader->derived_data;
1507 uint32_t *ds_state = te_state + GENX(3DSTATE_TE_length);
1508
1509 iris_pack_command(GENX(3DSTATE_TE), te_state, te) {
1510 te.Partitioning = tes_prog_data->partitioning;
1511 te.OutputTopology = tes_prog_data->output_topology;
1512 te.TEDomain = tes_prog_data->domain;
1513 te.TEEnable = true;
1514 te.MaximumTessellationFactorOdd = 63.0;
1515 te.MaximumTessellationFactorNotOdd = 64.0;
1516 }
1517
1518 iris_pack_command(GENX(3DSTATE_DS), ds_state, ds) {
1519 INIT_THREAD_DISPATCH_FIELDS(ds, Patch);
1520
1521 ds.DispatchMode = DISPATCH_MODE_SIMD8_SINGLE_PATCH;
1522 ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
1523 ds.ComputeWCoordinateEnable =
1524 tes_prog_data->domain == BRW_TESS_DOMAIN_TRI;
1525
1526 ds.UserClipDistanceCullTestEnableBitmask =
1527 vue_prog_data->cull_distance_mask;
1528 }
1529
1530 }
1531
1532 static void
1533 iris_set_gs_state(const struct gen_device_info *devinfo,
1534 struct iris_compiled_shader *shader)
1535 {
1536 struct brw_stage_prog_data *prog_data = shader->prog_data;
1537 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1538 struct brw_gs_prog_data *gs_prog_data = (void *) prog_data;
1539
1540 iris_pack_command(GENX(3DSTATE_GS), shader->derived_data, gs) {
1541 INIT_THREAD_DISPATCH_FIELDS(gs, Vertex);
1542
1543 gs.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1;
1544 gs.OutputTopology = gs_prog_data->output_topology;
1545 gs.ControlDataHeaderSize =
1546 gs_prog_data->control_data_header_size_hwords;
1547 gs.InstanceControl = gs_prog_data->invocations - 1;
1548 gs.DispatchMode = SIMD8;
1549 gs.IncludePrimitiveID = gs_prog_data->include_primitive_id;
1550 gs.ControlDataFormat = gs_prog_data->control_data_format;
1551 gs.ReorderMode = TRAILING;
1552 gs.ExpectedVertexCount = gs_prog_data->vertices_in;
1553 gs.MaximumNumberofThreads =
1554 GEN_GEN == 8 ? (devinfo->max_gs_threads / 2 - 1)
1555 : (devinfo->max_gs_threads - 1);
1556
1557 if (gs_prog_data->static_vertex_count != -1) {
1558 gs.StaticOutput = true;
1559 gs.StaticOutputVertexCount = gs_prog_data->static_vertex_count;
1560 }
1561 gs.IncludeVertexHandles = vue_prog_data->include_vue_handles;
1562
1563 gs.UserClipDistanceCullTestEnableBitmask =
1564 vue_prog_data->cull_distance_mask;
1565
1566 const int urb_entry_write_offset = 1;
1567 const uint32_t urb_entry_output_length =
1568 DIV_ROUND_UP(vue_prog_data->vue_map.num_slots, 2) -
1569 urb_entry_write_offset;
1570
1571 gs.VertexURBEntryOutputReadOffset = urb_entry_write_offset;
1572 gs.VertexURBEntryOutputLength = MAX2(urb_entry_output_length, 1);
1573 }
1574 }
1575
1576 static void
1577 iris_set_fs_state(const struct gen_device_info *devinfo,
1578 struct iris_compiled_shader *shader)
1579 {
1580 struct brw_stage_prog_data *prog_data = shader->prog_data;
1581 struct brw_wm_prog_data *wm_prog_data = (void *) shader->prog_data;
1582
1583 uint32_t *ps_state = (void *) shader->derived_data;
1584 uint32_t *psx_state = ps_state + GENX(3DSTATE_PS_length);
1585
1586 iris_pack_command(GENX(3DSTATE_PS), ps_state, ps) {
1587 ps.VectorMaskEnable = true;
1588 //ps.SamplerCount = ...
1589 ps.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4;
1590 ps.FloatingPointMode = prog_data->use_alt_mode;
1591 ps.MaximumNumberofThreadsPerPSD = 64 - (GEN_GEN == 8 ? 2 : 1);
1592
1593 ps.PushConstantEnable = prog_data->nr_params > 0 ||
1594 prog_data->ubo_ranges[0].length > 0;
1595
1596 /* From the documentation for this packet:
1597 * "If the PS kernel does not need the Position XY Offsets to
1598 * compute a Position Value, then this field should be programmed
1599 * to POSOFFSET_NONE."
1600 *
1601 * "SW Recommendation: If the PS kernel needs the Position Offsets
1602 * to compute a Position XY value, this field should match Position
1603 * ZW Interpolation Mode to ensure a consistent position.xyzw
1604 * computation."
1605 *
1606 * We only require XY sample offsets. So, this recommendation doesn't
1607 * look useful at the moment. We might need this in future.
1608 */
1609 ps.PositionXYOffsetSelect =
1610 wm_prog_data->uses_pos_offset ? POSOFFSET_SAMPLE : POSOFFSET_NONE;
1611 ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
1612 ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
1613 ps._32PixelDispatchEnable = wm_prog_data->dispatch_32;
1614
1615 // XXX: Disable SIMD32 with 16x MSAA
1616
1617 ps.DispatchGRFStartRegisterForConstantSetupData0 =
1618 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 0);
1619 ps.DispatchGRFStartRegisterForConstantSetupData1 =
1620 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 1);
1621 ps.DispatchGRFStartRegisterForConstantSetupData2 =
1622 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 2);
1623
1624 ps.KernelStartPointer0 =
1625 KSP(shader) + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 0);
1626 ps.KernelStartPointer1 =
1627 KSP(shader) + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 1);
1628 ps.KernelStartPointer2 =
1629 KSP(shader) + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 2);
1630 }
1631
1632 iris_pack_command(GENX(3DSTATE_PS_EXTRA), psx_state, psx) {
1633 psx.PixelShaderValid = true;
1634 psx.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode;
1635 psx.PixelShaderKillsPixel = wm_prog_data->uses_kill;
1636 psx.AttributeEnable = wm_prog_data->num_varying_inputs != 0;
1637 psx.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth;
1638 psx.PixelShaderUsesSourceW = wm_prog_data->uses_src_w;
1639 psx.PixelShaderIsPerSample = wm_prog_data->persample_dispatch;
1640
1641 if (wm_prog_data->uses_sample_mask) {
1642 /* TODO: conservative rasterization */
1643 if (wm_prog_data->post_depth_coverage)
1644 psx.InputCoverageMaskState = ICMS_DEPTH_COVERAGE;
1645 else
1646 psx.InputCoverageMaskState = ICMS_NORMAL;
1647 }
1648
1649 psx.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask;
1650 psx.PixelShaderPullsBary = wm_prog_data->pulls_bary;
1651 psx.PixelShaderComputesStencil = wm_prog_data->computed_stencil;
1652
1653 // XXX: UAV bit
1654 }
1655 }
1656
1657 static unsigned
1658 iris_derived_program_state_size(enum iris_program_cache_id cache_id)
1659 {
1660 assert(cache_id <= IRIS_CACHE_CS);
1661
1662 static const unsigned dwords[] = {
1663 [IRIS_CACHE_VS] = GENX(3DSTATE_VS_length),
1664 [IRIS_CACHE_TCS] = GENX(3DSTATE_HS_length),
1665 [IRIS_CACHE_TES] = GENX(3DSTATE_TE_length) + GENX(3DSTATE_DS_length),
1666 [IRIS_CACHE_GS] = GENX(3DSTATE_GS_length),
1667 [IRIS_CACHE_FS] =
1668 GENX(3DSTATE_PS_length) + GENX(3DSTATE_PS_EXTRA_length),
1669 [IRIS_CACHE_CS] = 0,
1670 [IRIS_CACHE_BLORP_BLIT] = 0,
1671 };
1672
1673 return sizeof(uint32_t) * dwords[cache_id];
1674 }
1675
1676 static void
1677 iris_set_derived_program_state(const struct gen_device_info *devinfo,
1678 enum iris_program_cache_id cache_id,
1679 struct iris_compiled_shader *shader)
1680 {
1681 switch (cache_id) {
1682 case IRIS_CACHE_VS:
1683 iris_set_vs_state(devinfo, shader);
1684 break;
1685 case IRIS_CACHE_TCS:
1686 iris_set_tcs_state(devinfo, shader);
1687 break;
1688 case IRIS_CACHE_TES:
1689 iris_set_tes_state(devinfo, shader);
1690 break;
1691 case IRIS_CACHE_GS:
1692 iris_set_gs_state(devinfo, shader);
1693 break;
1694 case IRIS_CACHE_FS:
1695 iris_set_fs_state(devinfo, shader);
1696 break;
1697 case IRIS_CACHE_CS:
1698 break;
1699 default:
1700 break;
1701 }
1702 }
1703
1704 static void
1705 iris_upload_urb_config(struct iris_context *ice, struct iris_batch *batch)
1706 {
1707 const struct gen_device_info *devinfo = &batch->screen->devinfo;
1708 const unsigned push_size_kB = 32;
1709 unsigned entries[4];
1710 unsigned start[4];
1711 unsigned size[4];
1712
1713 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
1714 if (!ice->shaders.prog[i]) {
1715 size[i] = 1;
1716 } else {
1717 struct brw_vue_prog_data *vue_prog_data =
1718 (void *) ice->shaders.prog[i]->prog_data;
1719 size[i] = vue_prog_data->urb_entry_size;
1720 }
1721 assert(size[i] != 0);
1722 }
1723
1724 gen_get_urb_config(devinfo, 1024 * push_size_kB,
1725 1024 * ice->shaders.urb_size,
1726 ice->shaders.prog[MESA_SHADER_TESS_EVAL] != NULL,
1727 ice->shaders.prog[MESA_SHADER_GEOMETRY] != NULL,
1728 size, entries, start);
1729
1730 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
1731 iris_emit_cmd(batch, GENX(3DSTATE_URB_VS), urb) {
1732 urb._3DCommandSubOpcode += i;
1733 urb.VSURBStartingAddress = start[i];
1734 urb.VSURBEntryAllocationSize = size[i] - 1;
1735 urb.VSNumberofURBEntries = entries[i];
1736 }
1737 }
1738 }
1739
1740 static const uint32_t push_constant_opcodes[] = {
1741 [MESA_SHADER_VERTEX] = 21,
1742 [MESA_SHADER_TESS_CTRL] = 25, /* HS */
1743 [MESA_SHADER_TESS_EVAL] = 26, /* DS */
1744 [MESA_SHADER_GEOMETRY] = 22,
1745 [MESA_SHADER_FRAGMENT] = 23,
1746 [MESA_SHADER_COMPUTE] = 0,
1747 };
1748
1749 static void
1750 iris_upload_render_state(struct iris_context *ice,
1751 struct iris_batch *batch,
1752 const struct pipe_draw_info *draw)
1753 {
1754 const uint64_t dirty = ice->state.dirty;
1755
1756 struct brw_wm_prog_data *wm_prog_data = (void *)
1757 ice->shaders.prog[MESA_SHADER_FRAGMENT]->prog_data;
1758
1759 if (dirty & IRIS_DIRTY_CC_VIEWPORT) {
1760 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1761 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), ptr) {
1762 ptr.CCViewportPointer =
1763 iris_emit_state(batch, cso->cc_vp, sizeof(cso->cc_vp), 32);
1764 }
1765 }
1766
1767 if (dirty & IRIS_DIRTY_SF_CL_VIEWPORT) {
1768 struct iris_viewport_state *cso = ice->state.cso_vp;
1769 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), ptr) {
1770 ptr.SFClipViewportPointer =
1771 iris_emit_state(batch, cso->sf_cl_vp, sizeof(cso->sf_cl_vp), 64);
1772 }
1773 }
1774
1775 /* XXX: L3 State */
1776
1777 if (dirty & IRIS_DIRTY_URB) {
1778 iris_upload_urb_config(ice, batch);
1779 }
1780
1781 if (dirty & IRIS_DIRTY_BLEND_STATE) {
1782 struct iris_blend_state *cso_blend = ice->state.cso_blend;
1783 struct iris_depth_stencil_alpha_state *cso_zsa = ice->state.cso_zsa;
1784 // XXX: 3DSTATE_BLEND_STATE_POINTERS - BLEND_STATE
1785 // -> from iris_blend_state (most) + iris_depth_stencil_alpha_state
1786 // (alpha test function/enable) + has writeable RT from ???????
1787 uint32_t blend_offset;
1788 uint32_t *blend_map =
1789 iris_alloc_state(batch, sizeof(cso_blend->blend_state),
1790 64, &blend_offset);
1791
1792 uint32_t blend_state_header;
1793 iris_pack_state(GENX(BLEND_STATE), &blend_state_header, bs) {
1794 bs.AlphaTestEnable = cso_zsa->alpha.enabled;
1795 bs.AlphaTestFunction = translate_compare_func(cso_zsa->alpha.func);
1796 }
1797
1798 blend_map[0] = blend_state_header | cso_blend->blend_state[0];
1799 memcpy(&blend_map[1], &cso_blend->blend_state[1],
1800 sizeof(cso_blend->blend_state) - sizeof(uint32_t));
1801
1802 iris_emit_cmd(batch, GENX(3DSTATE_BLEND_STATE_POINTERS), ptr) {
1803 ptr.BlendStatePointer = blend_offset;
1804 ptr.BlendStatePointerValid = true;
1805 }
1806 }
1807
1808 if (dirty & IRIS_DIRTY_COLOR_CALC_STATE) {
1809 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1810 uint32_t cc_offset;
1811 void *cc_map =
1812 iris_alloc_state(batch,
1813 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length),
1814 64, &cc_offset);
1815 iris_pack_state(GENX(COLOR_CALC_STATE), cc_map, cc) {
1816 cc.AlphaTestFormat = ALPHATEST_FLOAT32;
1817 cc.AlphaReferenceValueAsFLOAT32 = cso->alpha.ref_value;
1818 cc.BlendConstantColorRed = ice->state.blend_color.color[0];
1819 cc.BlendConstantColorGreen = ice->state.blend_color.color[1];
1820 cc.BlendConstantColorBlue = ice->state.blend_color.color[2];
1821 cc.BlendConstantColorAlpha = ice->state.blend_color.color[3];
1822 }
1823 iris_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
1824 ptr.ColorCalcStatePointer = cc_offset;
1825 ptr.ColorCalcStatePointerValid = true;
1826 }
1827 }
1828
1829 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
1830 if (!(dirty & (IRIS_DIRTY_CONSTANTS_VS << stage)))
1831 continue;
1832
1833 iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_VS), pkt) {
1834 pkt._3DCommandSubOpcode = push_constant_opcodes[stage];
1835 if (ice->shaders.prog[stage]) {
1836 // XXX: 3DSTATE_CONSTANT_XS
1837 }
1838 }
1839 }
1840
1841 // Surfaces:
1842 // - pull constants
1843 // - ubos/ssbos/abos
1844 // - images
1845 // - textures
1846 // - render targets - write and read
1847 // XXX: 3DSTATE_BINDING_TABLE_POINTERS_XS
1848
1849 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
1850 if (!(dirty & (IRIS_DIRTY_SAMPLER_STATES_VS << stage)))
1851 continue;
1852
1853 // XXX: get sampler count from shader; don't emit them all...
1854 const int count = IRIS_MAX_TEXTURE_SAMPLERS;
1855
1856 uint32_t offset;
1857 uint32_t *map = iris_alloc_state(batch,
1858 count * 4 * GENX(SAMPLER_STATE_length),
1859 32, &offset);
1860
1861 for (int i = 0; i < count; i++) {
1862 // XXX: when we have a correct count, these better be bound
1863 if (!ice->state.samplers[stage][i])
1864 continue;
1865 memcpy(map, ice->state.samplers[stage][i]->sampler_state,
1866 4 * GENX(SAMPLER_STATE_length));
1867 map += GENX(SAMPLER_STATE_length);
1868 }
1869
1870 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ptr) {
1871 ptr._3DCommandSubOpcode = 43 + stage;
1872 ptr.PointertoVSSamplerState = offset;
1873 }
1874 }
1875
1876 if (dirty & IRIS_DIRTY_MULTISAMPLE) {
1877 iris_emit_cmd(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
1878 ms.PixelLocation =
1879 ice->state.cso_rast->half_pixel_center ? CENTER : UL_CORNER;
1880 if (ice->state.framebuffer.samples > 0)
1881 ms.NumberofMultisamples = ffs(ice->state.framebuffer.samples) - 1;
1882 }
1883 }
1884
1885 if (dirty & IRIS_DIRTY_SAMPLE_MASK) {
1886 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_MASK), ms) {
1887 ms.SampleMask = ice->state.sample_mask;
1888 }
1889 }
1890
1891 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
1892 if (!(dirty & (IRIS_DIRTY_VS << stage)))
1893 continue;
1894
1895 if (ice->shaders.prog[stage]) {
1896 iris_batch_emit(batch, ice->shaders.prog[stage]->derived_data,
1897 iris_derived_program_state_size(stage));
1898 } else {
1899 if (stage == MESA_SHADER_TESS_EVAL) {
1900 iris_emit_cmd(batch, GENX(3DSTATE_HS), hs);
1901 iris_emit_cmd(batch, GENX(3DSTATE_TE), te);
1902 iris_emit_cmd(batch, GENX(3DSTATE_DS), ds);
1903 } else if (stage == MESA_SHADER_GEOMETRY) {
1904 iris_emit_cmd(batch, GENX(3DSTATE_GS), gs);
1905 }
1906 }
1907 }
1908
1909 // XXX: SOL:
1910 // 3DSTATE_STREAMOUT
1911 // 3DSTATE_SO_BUFFER
1912 // 3DSTATE_SO_DECL_LIST
1913
1914 if (dirty & IRIS_DIRTY_CLIP) {
1915 struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
1916 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
1917
1918 uint32_t dynamic_clip[GENX(3DSTATE_CLIP_length)];
1919 iris_pack_command(GENX(3DSTATE_CLIP), &dynamic_clip, cl) {
1920 if (wm_prog_data->barycentric_interp_modes &
1921 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS)
1922 cl.NonPerspectiveBarycentricEnable = true;
1923
1924 cl.ForceZeroRTAIndexEnable = cso_fb->layers == 0;
1925 }
1926 iris_emit_merge(batch, cso_rast->clip, dynamic_clip,
1927 ARRAY_SIZE(cso_rast->clip));
1928 }
1929
1930 if (dirty & IRIS_DIRTY_RASTER) {
1931 struct iris_rasterizer_state *cso = ice->state.cso_rast;
1932 iris_batch_emit(batch, cso->raster, sizeof(cso->raster));
1933 iris_batch_emit(batch, cso->sf, sizeof(cso->sf));
1934
1935 }
1936
1937 if (dirty & (IRIS_DIRTY_RASTER | IRIS_DIRTY_FS)) {
1938 struct iris_rasterizer_state *cso = ice->state.cso_rast;
1939 uint32_t dynamic_wm[GENX(3DSTATE_WM_length)];
1940
1941 iris_pack_command(GENX(3DSTATE_WM), &dynamic_wm, wm) {
1942 wm.BarycentricInterpolationMode =
1943 wm_prog_data->barycentric_interp_modes;
1944
1945 if (wm_prog_data->early_fragment_tests)
1946 wm.EarlyDepthStencilControl = EDSC_PREPS;
1947 else if (wm_prog_data->has_side_effects)
1948 wm.EarlyDepthStencilControl = EDSC_PSEXEC;
1949 }
1950 iris_emit_merge(batch, cso->wm, dynamic_wm, ARRAY_SIZE(cso->wm));
1951 }
1952
1953 // XXX: 3DSTATE_SBE, 3DSTATE_SBE_SWIZ
1954 // -> iris_raster_state (point sprite texture coordinate origin)
1955 // -> bunch of shader state...
1956
1957 if (dirty & IRIS_DIRTY_PS_BLEND) {
1958 struct iris_blend_state *cso_blend = ice->state.cso_blend;
1959 struct iris_depth_stencil_alpha_state *cso_zsa = ice->state.cso_zsa;
1960 uint32_t dynamic_pb[GENX(3DSTATE_PS_BLEND_length)];
1961 iris_pack_command(GENX(3DSTATE_PS_BLEND), &dynamic_pb, pb) {
1962 pb.HasWriteableRT = true; // XXX: comes from somewhere :(
1963 pb.AlphaTestEnable = cso_zsa->alpha.enabled;
1964 }
1965
1966 iris_emit_merge(batch, cso_blend->ps_blend, dynamic_pb,
1967 ARRAY_SIZE(cso_blend->ps_blend));
1968 }
1969
1970 if (dirty & IRIS_DIRTY_WM_DEPTH_STENCIL) {
1971 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1972 struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref;
1973
1974 uint32_t stencil_refs[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
1975 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), &stencil_refs, wmds) {
1976 wmds.StencilReferenceValue = p_stencil_refs->ref_value[0];
1977 wmds.BackfaceStencilReferenceValue = p_stencil_refs->ref_value[1];
1978 }
1979 iris_emit_merge(batch, cso->wmds, stencil_refs, ARRAY_SIZE(cso->wmds));
1980 }
1981
1982 if (dirty & IRIS_DIRTY_SCISSOR) {
1983 uint32_t scissor_offset =
1984 iris_emit_state(batch, ice->state.scissors,
1985 sizeof(struct pipe_scissor_state) *
1986 ice->state.num_scissors, 32);
1987
1988 iris_emit_cmd(batch, GENX(3DSTATE_SCISSOR_STATE_POINTERS), ptr) {
1989 ptr.ScissorRectPointer = scissor_offset;
1990 }
1991 }
1992
1993 // XXX: 3DSTATE_DEPTH_BUFFER
1994 // XXX: 3DSTATE_HIER_DEPTH_BUFFER
1995 // XXX: 3DSTATE_STENCIL_BUFFER
1996 // XXX: 3DSTATE_CLEAR_PARAMS
1997
1998 if (dirty & IRIS_DIRTY_POLYGON_STIPPLE) {
1999 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
2000 for (int i = 0; i < 32; i++) {
2001 poly.PatternRow[i] = ice->state.poly_stipple.stipple[i];
2002 }
2003 }
2004 }
2005
2006 if (dirty & IRIS_DIRTY_LINE_STIPPLE) {
2007 struct iris_rasterizer_state *cso = ice->state.cso_rast;
2008 iris_batch_emit(batch, cso->line_stipple, sizeof(cso->line_stipple));
2009 }
2010
2011 if (1) {
2012 iris_emit_cmd(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
2013 topo.PrimitiveTopologyType =
2014 translate_prim_type(draw->mode, draw->vertices_per_patch);
2015 }
2016 }
2017
2018 if (draw->index_size > 0) {
2019 struct iris_resource *res = (struct iris_resource *)draw->index.resource;
2020
2021 assert(!draw->has_user_indices);
2022
2023 iris_emit_cmd(batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
2024 ib.IndexFormat = draw->index_size;
2025 ib.MOCS = MOCS_WB;
2026 ib.BufferSize = res->bo->size;
2027 ib.BufferStartingAddress = ro_bo(res->bo, 0);
2028 }
2029 }
2030
2031 if (dirty & IRIS_DIRTY_VERTEX_BUFFERS) {
2032 struct iris_vertex_buffer_state *cso = ice->state.cso_vertex_buffers;
2033
2034 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_length) == 4);
2035 STATIC_ASSERT((GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) % 32) == 0);
2036
2037 uint64_t *addr = batch->cmdbuf.map_next + sizeof(uint32_t) *
2038 (GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) / 32);
2039 uint32_t *delta = cso->vertex_buffers +
2040 (1 + GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) / 32);
2041
2042 iris_batch_emit(batch, cso->vertex_buffers,
2043 sizeof(uint32_t) * (1 + 4 * cso->num_buffers));
2044
2045 for (unsigned i = 0; i < cso->num_buffers; i++) {
2046 *addr = iris_batch_reloc(batch, (void *) addr - batch->cmdbuf.map,
2047 cso->bos[i].bo, cso->bos[i].offset +
2048 *delta, cso->bos[i].reloc_flags);
2049 addr = (void *) addr + 16;
2050 delta = (void *) delta + 16;
2051 }
2052 }
2053
2054 if (dirty & IRIS_DIRTY_VERTEX_ELEMENTS) {
2055 struct iris_vertex_element_state *cso = ice->state.cso_vertex_elements;
2056 iris_batch_emit(batch, cso->vertex_elements, sizeof(uint32_t) *
2057 (1 + cso->count * GENX(VERTEX_ELEMENT_STATE_length)));
2058 for (int i = 0; i < cso->count; i++) {
2059 iris_batch_emit(batch, cso->vf_instancing[i], sizeof(uint32_t) *
2060 (cso->count * GENX(3DSTATE_VF_INSTANCING_length)));
2061 }
2062 for (int i = 0; i < cso->count; i++) {
2063 /* TODO: vertexid, instanceid support */
2064 iris_emit_cmd(batch, GENX(3DSTATE_VF_SGVS), sgvs);
2065 }
2066 }
2067
2068 if (1) {
2069 iris_emit_cmd(batch, GENX(3DSTATE_VF), vf) {
2070 if (draw->primitive_restart) {
2071 vf.IndexedDrawCutIndexEnable = true;
2072 vf.CutIndex = draw->restart_index;
2073 }
2074 }
2075 }
2076
2077 // XXX: Gen8 - PMA fix
2078
2079 assert(!draw->indirect); // XXX: indirect support
2080
2081 iris_emit_cmd(batch, GENX(3DPRIMITIVE), prim) {
2082 prim.StartInstanceLocation = draw->start_instance;
2083 prim.InstanceCount = draw->instance_count;
2084 prim.VertexCountPerInstance = draw->count;
2085 prim.VertexAccessType = draw->index_size > 0 ? RANDOM : SEQUENTIAL;
2086
2087 // XXX: this is probably bonkers.
2088 prim.StartVertexLocation = draw->start;
2089
2090 if (draw->index_size) {
2091 prim.BaseVertexLocation += draw->index_bias;
2092 } else {
2093 prim.StartVertexLocation += draw->index_bias;
2094 }
2095
2096 //prim.BaseVertexLocation = ...;
2097 }
2098 }
2099
2100 static void
2101 iris_destroy_state(struct iris_context *ice)
2102 {
2103 // XXX: unreference resources/surfaces.
2104 for (unsigned i = 0; i < ice->state.framebuffer.nr_cbufs; i++) {
2105 pipe_surface_reference(&ice->state.framebuffer.cbufs[i], NULL);
2106 }
2107 pipe_surface_reference(&ice->state.framebuffer.zsbuf, NULL);
2108 }
2109
2110 void
2111 genX(init_state)(struct iris_context *ice)
2112 {
2113 struct pipe_context *ctx = &ice->ctx;
2114
2115 ctx->create_blend_state = iris_create_blend_state;
2116 ctx->create_depth_stencil_alpha_state = iris_create_zsa_state;
2117 ctx->create_rasterizer_state = iris_create_rasterizer_state;
2118 ctx->create_sampler_state = iris_create_sampler_state;
2119 ctx->create_sampler_view = iris_create_sampler_view;
2120 ctx->create_surface = iris_create_surface;
2121 ctx->create_vertex_elements_state = iris_create_vertex_elements;
2122 ctx->create_compute_state = iris_create_compute_state;
2123 ctx->bind_blend_state = iris_bind_blend_state;
2124 ctx->bind_depth_stencil_alpha_state = iris_bind_zsa_state;
2125 ctx->bind_sampler_states = iris_bind_sampler_states;
2126 ctx->bind_rasterizer_state = iris_bind_rasterizer_state;
2127 ctx->bind_vertex_elements_state = iris_bind_vertex_elements_state;
2128 ctx->bind_compute_state = iris_bind_compute_state;
2129 ctx->delete_blend_state = iris_delete_state;
2130 ctx->delete_depth_stencil_alpha_state = iris_delete_state;
2131 ctx->delete_fs_state = iris_delete_state;
2132 ctx->delete_rasterizer_state = iris_delete_state;
2133 ctx->delete_sampler_state = iris_delete_state;
2134 ctx->delete_vertex_elements_state = iris_delete_state;
2135 ctx->delete_compute_state = iris_delete_state;
2136 ctx->delete_tcs_state = iris_delete_state;
2137 ctx->delete_tes_state = iris_delete_state;
2138 ctx->delete_gs_state = iris_delete_state;
2139 ctx->delete_vs_state = iris_delete_state;
2140 ctx->set_blend_color = iris_set_blend_color;
2141 ctx->set_clip_state = iris_set_clip_state;
2142 ctx->set_constant_buffer = iris_set_constant_buffer;
2143 ctx->set_sampler_views = iris_set_sampler_views;
2144 ctx->set_framebuffer_state = iris_set_framebuffer_state;
2145 ctx->set_polygon_stipple = iris_set_polygon_stipple;
2146 ctx->set_sample_mask = iris_set_sample_mask;
2147 ctx->set_scissor_states = iris_set_scissor_states;
2148 ctx->set_stencil_ref = iris_set_stencil_ref;
2149 ctx->set_vertex_buffers = iris_set_vertex_buffers;
2150 ctx->set_viewport_states = iris_set_viewport_states;
2151 ctx->sampler_view_destroy = iris_sampler_view_destroy;
2152 ctx->surface_destroy = iris_surface_destroy;
2153 ctx->draw_vbo = iris_draw_vbo;
2154 ctx->launch_grid = iris_launch_grid;
2155 ctx->create_stream_output_target = iris_create_stream_output_target;
2156 ctx->stream_output_target_destroy = iris_stream_output_target_destroy;
2157 ctx->set_stream_output_targets = iris_set_stream_output_targets;
2158
2159 ice->state.destroy_state = iris_destroy_state;
2160 ice->state.init_render_context = iris_init_render_context;
2161 ice->state.upload_render_state = iris_upload_render_state;
2162 ice->state.derived_program_state_size = iris_derived_program_state_size;
2163 ice->state.set_derived_program_state = iris_set_derived_program_state;
2164 ice->state.populate_vs_key = iris_populate_vs_key;
2165 ice->state.populate_tcs_key = iris_populate_tcs_key;
2166 ice->state.populate_tes_key = iris_populate_tes_key;
2167 ice->state.populate_gs_key = iris_populate_gs_key;
2168 ice->state.populate_fs_key = iris_populate_fs_key;
2169
2170
2171 ice->state.dirty = ~0ull;
2172 }