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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_inlines.h"
92 #include "util/u_format.h"
93 #include "util/u_framebuffer.h"
94 #include "util/u_transfer.h"
95 #include "util/u_upload_mgr.h"
96 #include "util/u_viewport.h"
99 #include "intel/compiler/brw_compiler.h"
100 #include "intel/common/gen_l3_config.h"
101 #include "intel/common/gen_sample_positions.h"
102 #include "iris_batch.h"
103 #include "iris_context.h"
104 #include "iris_defines.h"
105 #include "iris_pipe.h"
106 #include "iris_resource.h"
108 #define __gen_address_type struct iris_address
109 #define __gen_user_data struct iris_batch
111 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
114 __gen_combine_address(struct iris_batch
*batch
, void *location
,
115 struct iris_address addr
, uint32_t delta
)
117 uint64_t result
= addr
.offset
+ delta
;
120 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
121 /* Assume this is a general address, not relative to a base. */
122 result
+= addr
.bo
->gtt_offset
;
128 #define __genxml_cmd_length(cmd) cmd ## _length
129 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
130 #define __genxml_cmd_header(cmd) cmd ## _header
131 #define __genxml_cmd_pack(cmd) cmd ## _pack
133 #define _iris_pack_command(batch, cmd, dst, name) \
134 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
135 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
136 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
140 #define iris_pack_command(cmd, dst, name) \
141 _iris_pack_command(NULL, cmd, dst, name)
143 #define iris_pack_state(cmd, dst, name) \
144 for (struct cmd name = {}, \
145 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
146 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
149 #define iris_emit_cmd(batch, cmd, name) \
150 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
152 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
154 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
155 for (uint32_t i = 0; i < num_dwords; i++) \
156 dw[i] = (dwords0)[i] | (dwords1)[i]; \
157 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
160 #include "genxml/genX_pack.h"
161 #include "genxml/gen_macros.h"
162 #include "genxml/genX_bits.h"
164 #define MOCS_WB (2 << 1)
167 * Statically assert that PIPE_* enums match the hardware packets.
168 * (As long as they match, we don't need to translate them.)
170 UNUSED
static void pipe_asserts()
172 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
174 /* pipe_logicop happens to match the hardware. */
175 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
176 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
177 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
178 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
179 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
180 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
181 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
182 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
183 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
184 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
185 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
186 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
187 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
188 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
189 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
190 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
192 /* pipe_blend_func happens to match the hardware. */
193 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
194 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
195 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
196 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
197 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
198 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
199 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
200 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
201 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
202 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
203 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
204 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
205 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
206 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
207 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
211 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
213 /* pipe_blend_func happens to match the hardware. */
214 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
215 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
216 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
217 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
218 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
220 /* pipe_stencil_op happens to match the hardware. */
221 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
222 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
223 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
224 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
225 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
226 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
227 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
228 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
230 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
231 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
232 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
237 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
239 static const unsigned map
[] = {
240 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
241 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
242 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
243 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
244 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
245 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
246 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
247 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
248 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
249 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
250 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
251 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
252 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
253 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
254 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
257 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
261 translate_compare_func(enum pipe_compare_func pipe_func
)
263 static const unsigned map
[] = {
264 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
265 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
266 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
267 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
268 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
269 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
270 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
271 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
273 return map
[pipe_func
];
277 translate_shadow_func(enum pipe_compare_func pipe_func
)
279 /* Gallium specifies the result of shadow comparisons as:
281 * 1 if ref <op> texel,
286 * 0 if texel <op> ref,
289 * So we need to flip the operator and also negate.
291 static const unsigned map
[] = {
292 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
293 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
294 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
295 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
296 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
297 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
298 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
299 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
301 return map
[pipe_func
];
305 translate_cull_mode(unsigned pipe_face
)
307 static const unsigned map
[4] = {
308 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
309 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
310 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
311 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
313 return map
[pipe_face
];
317 translate_fill_mode(unsigned pipe_polymode
)
319 static const unsigned map
[4] = {
320 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
321 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
322 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
323 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
325 return map
[pipe_polymode
];
329 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
331 static const unsigned map
[] = {
332 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
333 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
334 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
336 return map
[pipe_mip
];
340 translate_wrap(unsigned pipe_wrap
)
342 static const unsigned map
[] = {
343 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
344 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
345 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
346 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
347 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
348 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
350 /* These are unsupported. */
351 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
352 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
354 return map
[pipe_wrap
];
357 static struct iris_address
358 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
360 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
361 * validation list at CSO creation time, instead of draw time.
363 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
366 static struct iris_address
367 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
369 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
370 * validation list at CSO creation time, instead of draw time.
372 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
376 * Allocate space for some indirect state.
378 * Return a pointer to the map (to fill it out) and a state ref (for
379 * referring to the state in GPU commands).
382 upload_state(struct u_upload_mgr
*uploader
,
383 struct iris_state_ref
*ref
,
388 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
393 * Stream out temporary/short-lived state.
395 * This allocates space, pins the BO, and includes the BO address in the
396 * returned offset (which works because all state lives in 32-bit memory
400 stream_state(struct iris_batch
*batch
,
401 struct u_upload_mgr
*uploader
,
402 struct pipe_resource
**out_res
,
405 uint32_t *out_offset
)
409 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
411 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
412 iris_use_pinned_bo(batch
, bo
, false);
414 *out_offset
+= iris_bo_offset_from_base_address(bo
);
420 * stream_state() + memcpy.
423 emit_state(struct iris_batch
*batch
,
424 struct u_upload_mgr
*uploader
,
425 struct pipe_resource
**out_res
,
432 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
435 memcpy(map
, data
, size
);
441 * Did field 'x' change between 'old_cso' and 'new_cso'?
443 * (If so, we may want to set some dirty flags.)
445 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
446 #define cso_changed_memcmp(x) \
447 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
450 flush_for_state_base_change(struct iris_batch
*batch
)
452 /* Flush before emitting STATE_BASE_ADDRESS.
454 * This isn't documented anywhere in the PRM. However, it seems to be
455 * necessary prior to changing the surface state base adress. We've
456 * seen issues in Vulkan where we get GPU hangs when using multi-level
457 * command buffers which clear depth, reset state base address, and then
460 * Normally, in GL, we would trust the kernel to do sufficient stalls
461 * and flushes prior to executing our batch. However, it doesn't seem
462 * as if the kernel's flushing is always sufficient and we don't want to
465 * We make this an end-of-pipe sync instead of a normal flush because we
466 * do not know the current status of the GPU. On Haswell at least,
467 * having a fast-clear operation in flight at the same time as a normal
468 * rendering operation can cause hangs. Since the kernel's flushing is
469 * insufficient, we need to ensure that any rendering operations from
470 * other processes are definitely complete before we try to do our own
471 * rendering. It's a bit of a big hammer but it appears to work.
473 iris_emit_end_of_pipe_sync(batch
,
474 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
475 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
476 PIPE_CONTROL_DATA_CACHE_FLUSH
);
480 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
482 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
483 lri
.RegisterOffset
= reg
;
487 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
490 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
492 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
493 lrr
.SourceRegisterAddress
= src
;
494 lrr
.DestinationRegisterAddress
= dst
;
499 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
501 #if GEN_GEN >= 8 && GEN_GEN < 10
502 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
504 * Software must clear the COLOR_CALC_STATE Valid field in
505 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
506 * with Pipeline Select set to GPGPU.
508 * The internal hardware docs recommend the same workaround for Gen9
511 if (pipeline
== GPGPU
)
512 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
516 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
517 * PIPELINE_SELECT [DevBWR+]":
521 * Software must ensure all the write caches are flushed through a
522 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
523 * command to invalidate read only caches prior to programming
524 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
526 iris_emit_pipe_control_flush(batch
,
527 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
528 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
529 PIPE_CONTROL_DATA_CACHE_FLUSH
|
530 PIPE_CONTROL_CS_STALL
);
532 iris_emit_pipe_control_flush(batch
,
533 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
534 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
535 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
536 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
538 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
542 sel
.PipelineSelection
= pipeline
;
547 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
552 * "This chicken bit works around a hardware issue with barrier
553 * logic encountered when switching between GPGPU and 3D pipelines.
554 * To workaround the issue, this mode bit should be set after a
555 * pipeline is selected."
558 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
559 reg
.GLKBarrierMode
= value
;
560 reg
.GLKBarrierModeMask
= 1;
562 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
567 init_state_base_address(struct iris_batch
*batch
)
569 flush_for_state_base_change(batch
);
571 /* We program most base addresses once at context initialization time.
572 * Each base address points at a 4GB memory zone, and never needs to
573 * change. See iris_bufmgr.h for a description of the memory zones.
575 * The one exception is Surface State Base Address, which needs to be
576 * updated occasionally. See iris_binder.c for the details there.
578 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
580 // XXX: MOCS is stupid for this.
581 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
582 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
583 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
584 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
585 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
586 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
589 sba
.GeneralStateBaseAddressModifyEnable
= true;
590 sba
.DynamicStateBaseAddressModifyEnable
= true;
591 sba
.IndirectObjectBaseAddressModifyEnable
= true;
592 sba
.InstructionBaseAddressModifyEnable
= true;
593 sba
.GeneralStateBufferSizeModifyEnable
= true;
594 sba
.DynamicStateBufferSizeModifyEnable
= true;
595 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
596 sba
.IndirectObjectBufferSizeModifyEnable
= true;
597 sba
.InstructionBuffersizeModifyEnable
= true;
599 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
600 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
602 sba
.GeneralStateBufferSize
= 0xfffff;
603 sba
.IndirectObjectBufferSize
= 0xfffff;
604 sba
.InstructionBufferSize
= 0xfffff;
605 sba
.DynamicStateBufferSize
= 0xfffff;
610 * Upload the initial GPU state for a render context.
612 * This sets some invariant state that needs to be programmed a particular
613 * way, but we never actually change.
616 iris_init_render_context(struct iris_screen
*screen
,
617 struct iris_batch
*batch
,
618 struct iris_vtable
*vtbl
,
619 struct pipe_debug_callback
*dbg
)
621 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
624 emit_pipeline_select(batch
, _3D
);
626 init_state_base_address(batch
);
628 // XXX: INSTPM on Gen8
629 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
630 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
631 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
633 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
636 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
637 reg
.FloatBlendOptimizationEnable
= true;
638 reg
.FloatBlendOptimizationEnableMask
= true;
639 reg
.PartialResolveDisableInVC
= true;
640 reg
.PartialResolveDisableInVCMask
= true;
642 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
644 if (devinfo
->is_geminilake
)
645 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
649 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
650 reg
.HeaderlessMessageforPreemptableContexts
= 1;
651 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
653 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
658 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
659 * changing it dynamically. We set it to the maximum size here, and
660 * instead include the render target dimensions in the viewport, so
661 * viewport extents clipping takes care of pruning stray geometry.
663 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
664 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
665 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
668 /* Set the initial MSAA sample positions. */
669 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
670 GEN_SAMPLE_POS_1X(pat
._1xSample
);
671 GEN_SAMPLE_POS_2X(pat
._2xSample
);
672 GEN_SAMPLE_POS_4X(pat
._4xSample
);
673 GEN_SAMPLE_POS_8X(pat
._8xSample
);
674 GEN_SAMPLE_POS_16X(pat
._16xSample
);
677 /* Use the legacy AA line coverage computation. */
678 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
680 /* Disable chromakeying (it's for media) */
681 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
683 /* We want regular rendering, not special HiZ operations. */
684 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
686 /* No polygon stippling offsets are necessary. */
687 // XXX: may need to set an offset for origin-UL framebuffers
688 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
690 /* Set a static partitioning of the push constant area. */
691 // XXX: this may be a bad idea...could starve the push ringbuffers...
692 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
693 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
694 alloc
._3DCommandSubOpcode
= 18 + i
;
695 alloc
.ConstantBufferOffset
= 6 * i
;
696 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
702 iris_init_compute_context(struct iris_screen
*screen
,
703 struct iris_batch
*batch
,
704 struct iris_vtable
*vtbl
,
705 struct pipe_debug_callback
*dbg
)
707 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
709 emit_pipeline_select(batch
, GPGPU
);
711 const bool has_slm
= true;
712 const bool wants_dc_cache
= true;
714 const struct gen_l3_weights w
=
715 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
716 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
719 iris_pack_state(GENX(L3CNTLREG
), ®_val
, reg
) {
720 reg
.SLMEnable
= has_slm
;
722 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
723 * in L3CNTLREG register. The default setting of the bit is not the
724 * desirable behavior.
726 reg
.ErrorDetectionBehaviorControl
= true;
728 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
729 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
730 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
731 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
733 iris_emit_lri(batch
, L3CNTLREG
, reg_val
);
735 init_state_base_address(batch
);
738 if (devinfo
->is_geminilake
)
739 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
743 struct iris_vertex_buffer_state
{
744 /** The VERTEX_BUFFER_STATE hardware structure. */
745 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
747 /** The resource to source vertex data from. */
748 struct pipe_resource
*resource
;
751 struct iris_depth_buffer_state
{
752 /* Depth/HiZ/Stencil related hardware packets. */
753 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
754 GENX(3DSTATE_STENCIL_BUFFER_length
) +
755 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
756 GENX(3DSTATE_CLEAR_PARAMS_length
)];
760 * Generation-specific context state (ice->state.genx->...).
762 * Most state can go in iris_context directly, but these encode hardware
763 * packets which vary by generation.
765 struct iris_genx_state
{
766 struct iris_vertex_buffer_state vertex_buffers
[33];
768 /** The number of bound vertex buffers. */
769 uint64_t bound_vertex_buffers
;
771 struct iris_depth_buffer_state depth_buffer
;
773 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
777 * The pipe->set_blend_color() driver hook.
779 * This corresponds to our COLOR_CALC_STATE.
782 iris_set_blend_color(struct pipe_context
*ctx
,
783 const struct pipe_blend_color
*state
)
785 struct iris_context
*ice
= (struct iris_context
*) ctx
;
787 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
788 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
789 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
793 * Gallium CSO for blend state (see pipe_blend_state).
795 struct iris_blend_state
{
796 /** Partial 3DSTATE_PS_BLEND */
797 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
799 /** Partial BLEND_STATE */
800 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
801 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
803 bool alpha_to_coverage
; /* for shader key */
805 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
806 uint8_t blend_enables
;
809 static enum pipe_blendfactor
810 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
813 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
814 return PIPE_BLENDFACTOR_ONE
;
816 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
817 return PIPE_BLENDFACTOR_ZERO
;
824 * The pipe->create_blend_state() driver hook.
826 * Translates a pipe_blend_state into iris_blend_state.
829 iris_create_blend_state(struct pipe_context
*ctx
,
830 const struct pipe_blend_state
*state
)
832 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
833 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
835 cso
->blend_enables
= 0;
836 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
838 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
840 bool indep_alpha_blend
= false;
842 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
843 const struct pipe_rt_blend_state
*rt
=
844 &state
->rt
[state
->independent_blend_enable
? i
: 0];
846 enum pipe_blendfactor src_rgb
=
847 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
848 enum pipe_blendfactor src_alpha
=
849 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
850 enum pipe_blendfactor dst_rgb
=
851 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
852 enum pipe_blendfactor dst_alpha
=
853 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
855 if (rt
->rgb_func
!= rt
->alpha_func
||
856 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
857 indep_alpha_blend
= true;
859 if (rt
->blend_enable
)
860 cso
->blend_enables
|= 1u << i
;
862 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
863 be
.LogicOpEnable
= state
->logicop_enable
;
864 be
.LogicOpFunction
= state
->logicop_func
;
866 be
.PreBlendSourceOnlyClampEnable
= false;
867 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
868 be
.PreBlendColorClampEnable
= true;
869 be
.PostBlendColorClampEnable
= true;
871 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
873 be
.ColorBlendFunction
= rt
->rgb_func
;
874 be
.AlphaBlendFunction
= rt
->alpha_func
;
875 be
.SourceBlendFactor
= src_rgb
;
876 be
.SourceAlphaBlendFactor
= src_alpha
;
877 be
.DestinationBlendFactor
= dst_rgb
;
878 be
.DestinationAlphaBlendFactor
= dst_alpha
;
880 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
881 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
882 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
883 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
885 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
888 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
889 /* pb.HasWriteableRT is filled in at draw time. */
890 /* pb.AlphaTestEnable is filled in at draw time. */
891 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
892 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
894 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
896 pb
.SourceBlendFactor
=
897 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
898 pb
.SourceAlphaBlendFactor
=
899 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
900 pb
.DestinationBlendFactor
=
901 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
902 pb
.DestinationAlphaBlendFactor
=
903 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
906 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
907 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
908 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
909 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
910 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
911 bs
.ColorDitherEnable
= state
->dither
;
912 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
920 * The pipe->bind_blend_state() driver hook.
922 * Bind a blending CSO and flag related dirty bits.
925 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
927 struct iris_context
*ice
= (struct iris_context
*) ctx
;
928 struct iris_blend_state
*cso
= state
;
930 ice
->state
.cso_blend
= cso
;
931 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
933 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
934 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
935 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
939 * Gallium CSO for depth, stencil, and alpha testing state.
941 struct iris_depth_stencil_alpha_state
{
942 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
943 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
945 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
946 struct pipe_alpha_state alpha
;
948 /** Outbound to resolve and cache set tracking. */
949 bool depth_writes_enabled
;
950 bool stencil_writes_enabled
;
954 * The pipe->create_depth_stencil_alpha_state() driver hook.
956 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
957 * testing state since we need pieces of it in a variety of places.
960 iris_create_zsa_state(struct pipe_context
*ctx
,
961 const struct pipe_depth_stencil_alpha_state
*state
)
963 struct iris_depth_stencil_alpha_state
*cso
=
964 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
966 bool two_sided_stencil
= state
->stencil
[1].enabled
;
968 cso
->alpha
= state
->alpha
;
969 cso
->depth_writes_enabled
= state
->depth
.writemask
;
970 cso
->stencil_writes_enabled
=
971 state
->stencil
[0].writemask
!= 0 ||
972 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 1);
974 /* The state tracker needs to optimize away EQUAL writes for us. */
975 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
977 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
978 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
979 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
980 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
981 wmds
.StencilTestFunction
=
982 translate_compare_func(state
->stencil
[0].func
);
983 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
984 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
985 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
986 wmds
.BackfaceStencilTestFunction
=
987 translate_compare_func(state
->stencil
[1].func
);
988 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
989 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
990 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
991 wmds
.StencilBufferWriteEnable
=
992 state
->stencil
[0].writemask
!= 0 ||
993 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
994 wmds
.DepthTestEnable
= state
->depth
.enabled
;
995 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
996 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
997 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
998 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
999 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1000 /* wmds.[Backface]StencilReferenceValue are merged later */
1007 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1009 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1012 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1014 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1015 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1016 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1019 if (cso_changed(alpha
.ref_value
))
1020 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1022 if (cso_changed(alpha
.enabled
))
1023 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1025 if (cso_changed(alpha
.func
))
1026 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1028 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1029 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1032 ice
->state
.cso_zsa
= new_cso
;
1033 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1034 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1035 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1039 * Gallium CSO for rasterizer state.
1041 struct iris_rasterizer_state
{
1042 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1043 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1044 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1045 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1046 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1048 uint8_t num_clip_plane_consts
;
1049 bool clip_halfz
; /* for CC_VIEWPORT */
1050 bool depth_clip_near
; /* for CC_VIEWPORT */
1051 bool depth_clip_far
; /* for CC_VIEWPORT */
1052 bool flatshade
; /* for shader state */
1053 bool flatshade_first
; /* for stream output */
1054 bool clamp_fragment_color
; /* for shader state */
1055 bool light_twoside
; /* for shader state */
1056 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1057 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1058 bool line_stipple_enable
;
1059 bool poly_stipple_enable
;
1061 bool force_persample_interp
;
1062 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1063 uint16_t sprite_coord_enable
;
1067 get_line_width(const struct pipe_rasterizer_state
*state
)
1069 float line_width
= state
->line_width
;
1071 /* From the OpenGL 4.4 spec:
1073 * "The actual width of non-antialiased lines is determined by rounding
1074 * the supplied width to the nearest integer, then clamping it to the
1075 * implementation-dependent maximum non-antialiased line width."
1077 if (!state
->multisample
&& !state
->line_smooth
)
1078 line_width
= roundf(state
->line_width
);
1080 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1081 /* For 1 pixel line thickness or less, the general anti-aliasing
1082 * algorithm gives up, and a garbage line is generated. Setting a
1083 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1084 * (one-pixel-wide), non-antialiased lines.
1086 * Lines rendered with zero Line Width are rasterized using the
1087 * "Grid Intersection Quantization" rules as specified by the
1088 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1097 * The pipe->create_rasterizer_state() driver hook.
1100 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1101 const struct pipe_rasterizer_state
*state
)
1103 struct iris_rasterizer_state
*cso
=
1104 malloc(sizeof(struct iris_rasterizer_state
));
1107 point_quad_rasterization
-> SBE
?
1114 offset_units_unscaled
- cap
not exposed
1118 // XXX: it may make more sense just to store the pipe_rasterizer_state,
1119 // we're copying a lot of booleans here. But we don't need all of them...
1121 cso
->multisample
= state
->multisample
;
1122 cso
->force_persample_interp
= state
->force_persample_interp
;
1123 cso
->clip_halfz
= state
->clip_halfz
;
1124 cso
->depth_clip_near
= state
->depth_clip_near
;
1125 cso
->depth_clip_far
= state
->depth_clip_far
;
1126 cso
->flatshade
= state
->flatshade
;
1127 cso
->flatshade_first
= state
->flatshade_first
;
1128 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1129 cso
->light_twoside
= state
->light_twoside
;
1130 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1131 cso
->half_pixel_center
= state
->half_pixel_center
;
1132 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1133 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1134 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1135 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1137 if (state
->clip_plane_enable
!= 0)
1138 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1140 cso
->num_clip_plane_consts
= 0;
1142 float line_width
= get_line_width(state
);
1144 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1145 sf
.StatisticsEnable
= true;
1146 sf
.ViewportTransformEnable
= true;
1147 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1148 sf
.LineEndCapAntialiasingRegionWidth
=
1149 state
->line_smooth
? _10pixels
: _05pixels
;
1150 sf
.LastPixelEnable
= state
->line_last_pixel
;
1151 sf
.LineWidth
= line_width
;
1152 sf
.SmoothPointEnable
= state
->point_smooth
|| state
->multisample
;
1153 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1154 sf
.PointWidth
= state
->point_size
;
1156 if (state
->flatshade_first
) {
1157 sf
.TriangleFanProvokingVertexSelect
= 1;
1159 sf
.TriangleStripListProvokingVertexSelect
= 2;
1160 sf
.TriangleFanProvokingVertexSelect
= 2;
1161 sf
.LineStripListProvokingVertexSelect
= 1;
1165 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1166 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1167 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1168 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1169 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1170 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1171 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1172 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1173 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1174 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1175 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1176 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1177 rr
.SmoothPointEnable
= state
->point_smooth
|| state
->multisample
;
1178 rr
.AntialiasingEnable
= state
->line_smooth
;
1179 rr
.ScissorRectangleEnable
= state
->scissor
;
1180 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1181 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1182 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
1185 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1186 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1187 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1189 cl
.EarlyCullEnable
= true;
1190 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1191 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1192 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1193 cl
.GuardbandClipTestEnable
= true;
1194 cl
.ClipEnable
= true;
1195 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
1196 cl
.MinimumPointWidth
= 0.125;
1197 cl
.MaximumPointWidth
= 255.875;
1199 if (state
->flatshade_first
) {
1200 cl
.TriangleFanProvokingVertexSelect
= 1;
1202 cl
.TriangleStripListProvokingVertexSelect
= 2;
1203 cl
.TriangleFanProvokingVertexSelect
= 2;
1204 cl
.LineStripListProvokingVertexSelect
= 1;
1208 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1209 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1210 * filled in at draw time from the FS program.
1212 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1213 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1214 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1215 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1216 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1219 /* Remap from 0..255 back to 1..256 */
1220 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1222 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1223 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1224 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1225 line
.LineStippleRepeatCount
= line_stipple_factor
;
1232 * The pipe->bind_rasterizer_state() driver hook.
1234 * Bind a rasterizer CSO and flag related dirty bits.
1237 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1239 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1240 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1241 struct iris_rasterizer_state
*new_cso
= state
;
1244 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1245 if (cso_changed_memcmp(line_stipple
))
1246 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1248 if (cso_changed(half_pixel_center
))
1249 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1251 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1252 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1254 if (cso_changed(rasterizer_discard
))
1255 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1257 if (cso_changed(flatshade_first
))
1258 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1260 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1261 cso_changed(clip_halfz
))
1262 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1264 if (cso_changed(sprite_coord_enable
) ||
1265 cso_changed(sprite_coord_mode
) ||
1266 cso_changed(light_twoside
))
1267 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1270 ice
->state
.cso_rast
= new_cso
;
1271 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1272 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1273 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1277 * Return true if the given wrap mode requires the border color to exist.
1279 * (We can skip uploading it if the sampler isn't going to use it.)
1282 wrap_mode_needs_border_color(unsigned wrap_mode
)
1284 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1288 * Gallium CSO for sampler state.
1290 struct iris_sampler_state
{
1291 union pipe_color_union border_color
;
1292 bool needs_border_color
;
1294 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1298 * The pipe->create_sampler_state() driver hook.
1300 * We fill out SAMPLER_STATE (except for the border color pointer), and
1301 * store that on the CPU. It doesn't make sense to upload it to a GPU
1302 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1303 * all bound sampler states to be in contiguous memor.
1306 iris_create_sampler_state(struct pipe_context
*ctx
,
1307 const struct pipe_sampler_state
*state
)
1309 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1314 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1315 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1317 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1318 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1319 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1321 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1323 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1324 wrap_mode_needs_border_color(wrap_t
) ||
1325 wrap_mode_needs_border_color(wrap_r
);
1327 float min_lod
= state
->min_lod
;
1328 unsigned mag_img_filter
= state
->mag_img_filter
;
1330 // XXX: explain this code ported from ilo...I don't get it at all...
1331 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1332 state
->min_lod
> 0.0f
) {
1334 mag_img_filter
= state
->min_img_filter
;
1337 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1338 samp
.TCXAddressControlMode
= wrap_s
;
1339 samp
.TCYAddressControlMode
= wrap_t
;
1340 samp
.TCZAddressControlMode
= wrap_r
;
1341 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1342 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1343 samp
.MinModeFilter
= state
->min_img_filter
;
1344 samp
.MagModeFilter
= mag_img_filter
;
1345 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1346 samp
.MaximumAnisotropy
= RATIO21
;
1348 if (state
->max_anisotropy
>= 2) {
1349 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1350 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1351 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1354 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1355 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1357 samp
.MaximumAnisotropy
=
1358 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1361 /* Set address rounding bits if not using nearest filtering. */
1362 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1363 samp
.UAddressMinFilterRoundingEnable
= true;
1364 samp
.VAddressMinFilterRoundingEnable
= true;
1365 samp
.RAddressMinFilterRoundingEnable
= true;
1368 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1369 samp
.UAddressMagFilterRoundingEnable
= true;
1370 samp
.VAddressMagFilterRoundingEnable
= true;
1371 samp
.RAddressMagFilterRoundingEnable
= true;
1374 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1375 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1377 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1379 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1380 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1381 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1382 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1384 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1391 * The pipe->bind_sampler_states() driver hook.
1393 * Now that we know all the sampler states, we upload them all into a
1394 * contiguous area of GPU memory, for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1395 * We also fill out the border color state pointers at this point.
1397 * We could defer this work to draw time, but we assume that binding
1398 * will be less frequent than drawing.
1400 // XXX: this may be a bad idea, need to make sure that st/mesa calls us
1401 // XXX: with the complete set of shaders. If it makes multiple calls to
1402 // XXX: things one at a time, we could waste a lot of time assembling things.
1403 // XXX: it doesn't even BUY us anything to do it here, because we only flag
1404 // XXX: IRIS_DIRTY_SAMPLER_STATE when this is called...
1406 iris_bind_sampler_states(struct pipe_context
*ctx
,
1407 enum pipe_shader_type p_stage
,
1408 unsigned start
, unsigned count
,
1411 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1412 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1413 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1415 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1417 for (int i
= 0; i
< count
; i
++) {
1418 shs
->samplers
[start
+ i
] = states
[i
];
1421 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1422 * in the dynamic state memory zone, so we can point to it via the
1423 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1426 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
,
1427 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
1431 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1432 shs
->sampler_table
.offset
+=
1433 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1435 /* Make sure all land in the same BO */
1436 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1438 for (int i
= 0; i
< count
; i
++) {
1439 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1442 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1443 } else if (!state
->needs_border_color
) {
1444 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1446 ice
->state
.need_border_colors
= true;
1448 /* Stream out the border color and merge the pointer. */
1450 iris_upload_border_color(ice
, &state
->border_color
);
1452 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1453 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1454 dyns
.BorderColorPointer
= offset
;
1457 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1458 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1461 map
+= GENX(SAMPLER_STATE_length
);
1464 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1467 static enum isl_channel_select
1468 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1471 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1472 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1473 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1474 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1475 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1476 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1477 default: unreachable("invalid swizzle");
1482 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1485 enum isl_format format
,
1489 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1490 const unsigned cpp
= fmtl
->bpb
/ 8;
1492 /* The ARB_texture_buffer_specification says:
1494 * "The number of texels in the buffer texture's texel array is given by
1496 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1498 * where <buffer_size> is the size of the buffer object, in basic
1499 * machine units and <components> and <base_type> are the element count
1500 * and base data type for elements, as specified in Table X.1. The
1501 * number of texels in the texel array is then clamped to the
1502 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1504 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1505 * so that when ISL divides by stride to obtain the number of texels, that
1506 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1508 unsigned final_size
=
1509 MIN3(size
, bo
->size
- offset
, IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1511 isl_buffer_fill_state(isl_dev
, map
,
1512 .address
= bo
->gtt_offset
+ offset
,
1513 .size_B
= final_size
,
1520 * Allocate a SURFACE_STATE structure.
1523 alloc_surface_states(struct u_upload_mgr
*mgr
,
1524 struct iris_state_ref
*ref
)
1526 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
1528 void *map
= upload_state(mgr
, ref
, surf_size
, 64);
1530 ref
->offset
+= iris_bo_offset_from_base_address(iris_resource_bo(ref
->res
));
1536 fill_surface_state(struct isl_device
*isl_dev
,
1538 struct iris_resource
*res
,
1539 struct isl_view
*view
)
1541 struct isl_surf_fill_state_info f
= {
1545 .address
= res
->bo
->gtt_offset
,
1548 isl_surf_fill_state_s(isl_dev
, map
, &f
);
1552 * The pipe->create_sampler_view() driver hook.
1554 static struct pipe_sampler_view
*
1555 iris_create_sampler_view(struct pipe_context
*ctx
,
1556 struct pipe_resource
*tex
,
1557 const struct pipe_sampler_view
*tmpl
)
1559 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1560 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1561 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1562 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1567 /* initialize base object */
1569 isv
->base
.context
= ctx
;
1570 isv
->base
.texture
= NULL
;
1571 pipe_reference_init(&isv
->base
.reference
, 1);
1572 pipe_resource_reference(&isv
->base
.texture
, tex
);
1574 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1575 &isv
->surface_state
);
1579 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1580 struct iris_resource
*zres
, *sres
;
1581 const struct util_format_description
*desc
=
1582 util_format_description(tmpl
->format
);
1584 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1586 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1589 isv
->res
= (struct iris_resource
*) tex
;
1591 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1593 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1594 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1595 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1597 const struct iris_format_info fmt
=
1598 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1600 isv
->view
= (struct isl_view
) {
1602 .swizzle
= (struct isl_swizzle
) {
1603 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1604 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1605 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1606 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1611 /* Fill out SURFACE_STATE for this view. */
1612 if (tmpl
->target
!= PIPE_BUFFER
) {
1613 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1614 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1615 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1616 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1617 isv
->view
.array_len
=
1618 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1620 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->view
);
1622 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
->bo
, map
,
1623 isv
->view
.format
, tmpl
->u
.buf
.offset
,
1631 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1632 struct pipe_sampler_view
*state
)
1634 struct iris_sampler_view
*isv
= (void *) state
;
1635 pipe_resource_reference(&state
->texture
, NULL
);
1636 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1641 * The pipe->create_surface() driver hook.
1643 * In Gallium nomenclature, "surfaces" are a view of a resource that
1644 * can be bound as a render target or depth/stencil buffer.
1646 static struct pipe_surface
*
1647 iris_create_surface(struct pipe_context
*ctx
,
1648 struct pipe_resource
*tex
,
1649 const struct pipe_surface
*tmpl
)
1651 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1652 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1653 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1654 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1655 struct pipe_surface
*psurf
= &surf
->base
;
1656 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1661 pipe_reference_init(&psurf
->reference
, 1);
1662 pipe_resource_reference(&psurf
->texture
, tex
);
1663 psurf
->context
= ctx
;
1664 psurf
->format
= tmpl
->format
;
1665 psurf
->width
= tex
->width0
;
1666 psurf
->height
= tex
->height0
;
1667 psurf
->texture
= tex
;
1668 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1669 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1670 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1672 isl_surf_usage_flags_t usage
= 0;
1674 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1675 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1676 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1678 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1680 const struct iris_format_info fmt
=
1681 iris_format_for_usage(devinfo
, psurf
->format
, usage
);
1683 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1684 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1685 /* Framebuffer validation will reject this invalid case, but it
1686 * hasn't had the opportunity yet. In the meantime, we need to
1687 * avoid hitting ISL asserts about unsupported formats below.
1693 surf
->view
= (struct isl_view
) {
1695 .base_level
= tmpl
->u
.tex
.level
,
1697 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1698 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1699 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1703 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1704 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1705 ISL_SURF_USAGE_STENCIL_BIT
))
1709 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1710 &surf
->surface_state
);
1714 fill_surface_state(&screen
->isl_dev
, map
, res
, &surf
->view
);
1720 * The pipe->set_shader_images() driver hook.
1723 iris_set_shader_images(struct pipe_context
*ctx
,
1724 enum pipe_shader_type p_stage
,
1725 unsigned start_slot
, unsigned count
,
1726 const struct pipe_image_view
*p_images
)
1728 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1729 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1730 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1731 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1732 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1734 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
1736 for (unsigned i
= 0; i
< count
; i
++) {
1737 if (p_images
&& p_images
[i
].resource
) {
1738 const struct pipe_image_view
*img
= &p_images
[i
];
1739 struct iris_resource
*res
= (void *) img
->resource
;
1740 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, &res
->base
);
1742 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
1744 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
1746 // XXX: these are not retained forever, use a separate uploader?
1748 alloc_surface_states(ice
->state
.surface_uploader
,
1749 &shs
->image
[start_slot
+ i
].surface_state
);
1750 if (!unlikely(map
)) {
1751 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1755 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1756 enum isl_format isl_format
=
1757 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
1759 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
)
1760 isl_format
= isl_lower_storage_image_format(devinfo
, isl_format
);
1762 shs
->image
[start_slot
+ i
].access
= img
->shader_access
;
1764 if (res
->base
.target
!= PIPE_BUFFER
) {
1765 struct isl_view view
= {
1766 .format
= isl_format
,
1767 .base_level
= img
->u
.tex
.level
,
1769 .base_array_layer
= img
->u
.tex
.first_layer
,
1770 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
1771 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1775 fill_surface_state(&screen
->isl_dev
, map
, res
, &view
);
1777 fill_buffer_surface_state(&screen
->isl_dev
, res
->bo
, map
,
1778 isl_format
, img
->u
.buf
.offset
,
1782 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1783 pipe_resource_reference(&shs
->image
[start_slot
+ i
].surface_state
.res
,
1788 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1793 * The pipe->set_sampler_views() driver hook.
1796 iris_set_sampler_views(struct pipe_context
*ctx
,
1797 enum pipe_shader_type p_stage
,
1798 unsigned start
, unsigned count
,
1799 struct pipe_sampler_view
**views
)
1801 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1802 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1803 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1805 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
1807 for (unsigned i
= 0; i
< count
; i
++) {
1808 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1809 &shs
->textures
[start
+ i
], views
[i
]);
1810 struct iris_sampler_view
*view
= (void *) views
[i
];
1812 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
1813 shs
->bound_sampler_views
|= 1 << (start
+ i
);
1817 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
1821 * The pipe->set_tess_state() driver hook.
1824 iris_set_tess_state(struct pipe_context
*ctx
,
1825 const float default_outer_level
[4],
1826 const float default_inner_level
[2])
1828 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1830 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
1831 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
1833 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
1837 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1839 struct iris_surface
*surf
= (void *) p_surf
;
1840 pipe_resource_reference(&p_surf
->texture
, NULL
);
1841 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
1846 iris_set_clip_state(struct pipe_context
*ctx
,
1847 const struct pipe_clip_state
*state
)
1849 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1850 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
1852 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
1854 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
;
1855 shs
->cbuf0_needs_upload
= true;
1859 * The pipe->set_polygon_stipple() driver hook.
1862 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1863 const struct pipe_poly_stipple
*state
)
1865 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1866 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1867 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1871 * The pipe->set_sample_mask() driver hook.
1874 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1876 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1878 /* We only support 16x MSAA, so we have 16 bits of sample maks.
1879 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
1881 ice
->state
.sample_mask
= sample_mask
& 0xffff;
1882 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1886 * The pipe->set_scissor_states() driver hook.
1888 * This corresponds to our SCISSOR_RECT state structures. It's an
1889 * exact match, so we just store them, and memcpy them out later.
1892 iris_set_scissor_states(struct pipe_context
*ctx
,
1893 unsigned start_slot
,
1894 unsigned num_scissors
,
1895 const struct pipe_scissor_state
*rects
)
1897 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1899 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1900 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
1901 /* If the scissor was out of bounds and got clamped to 0 width/height
1902 * at the bounds, the subtraction of 1 from maximums could produce a
1903 * negative number and thus not clip anything. Instead, just provide
1904 * a min > max scissor inside the bounds, which produces the expected
1907 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
1908 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
1911 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
1912 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
1913 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
1918 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1922 * The pipe->set_stencil_ref() driver hook.
1924 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
1927 iris_set_stencil_ref(struct pipe_context
*ctx
,
1928 const struct pipe_stencil_ref
*state
)
1930 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1931 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1932 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1936 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1938 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1942 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1943 float m00
, float m11
, float m30
, float m31
,
1944 float *xmin
, float *xmax
,
1945 float *ymin
, float *ymax
)
1947 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1948 * Strips and Fans documentation:
1950 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1951 * fixed-point "guardband" range supported by the rasterization hardware"
1955 * "In almost all circumstances, if an object’s vertices are actually
1956 * modified by this clamping (i.e., had X or Y coordinates outside of
1957 * the guardband extent the rendered object will not match the intended
1958 * result. Therefore software should take steps to ensure that this does
1959 * not happen - e.g., by clipping objects such that they do not exceed
1960 * these limits after the Drawing Rectangle is applied."
1962 * I believe the fundamental restriction is that the rasterizer (in
1963 * the SF/WM stages) have a limit on the number of pixels that can be
1964 * rasterized. We need to ensure any coordinates beyond the rasterizer
1965 * limit are handled by the clipper. So effectively that limit becomes
1966 * the clipper's guardband size.
1968 * It goes on to say:
1970 * "In addition, in order to be correctly rendered, objects must have a
1971 * screenspace bounding box not exceeding 8K in the X or Y direction.
1972 * This additional restriction must also be comprehended by software,
1973 * i.e., enforced by use of clipping."
1975 * This makes no sense. Gen7+ hardware supports 16K render targets,
1976 * and you definitely need to be able to draw polygons that fill the
1977 * surface. Our assumption is that the rasterizer was limited to 8K
1978 * on Sandybridge, which only supports 8K surfaces, and it was actually
1979 * increased to 16K on Ivybridge and later.
1981 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1983 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1985 if (m00
!= 0 && m11
!= 0) {
1986 /* First, we compute the screen-space render area */
1987 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1988 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1989 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1990 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1992 /* We want the guardband to be centered on that */
1993 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1994 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1995 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1996 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1998 /* Now we need it in native device coordinates */
1999 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2000 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2001 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2002 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2004 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2005 * flipped upside-down. X should be fine though.
2007 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2008 *xmin
= ndc_gb_xmin
;
2009 *xmax
= ndc_gb_xmax
;
2010 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2011 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2013 /* The viewport scales to 0, so nothing will be rendered. */
2022 * The pipe->set_viewport_states() driver hook.
2024 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2025 * the guardband yet, as we need the framebuffer dimensions, but we can
2026 * at least fill out the rest.
2029 iris_set_viewport_states(struct pipe_context
*ctx
,
2030 unsigned start_slot
,
2032 const struct pipe_viewport_state
*states
)
2034 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2036 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2038 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2040 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2041 !ice
->state
.cso_rast
->depth_clip_far
))
2042 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2046 * The pipe->set_framebuffer_state() driver hook.
2048 * Sets the current draw FBO, including color render targets, depth,
2049 * and stencil buffers.
2052 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2053 const struct pipe_framebuffer_state
*state
)
2055 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2056 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2057 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2058 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2059 struct iris_resource
*zres
;
2060 struct iris_resource
*stencil_res
;
2062 unsigned samples
= util_framebuffer_get_num_samples(state
);
2064 if (cso
->samples
!= samples
) {
2065 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2068 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2069 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2072 if ((cso
->layers
== 0) != (state
->layers
== 0)) {
2073 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2076 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2077 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2080 util_copy_framebuffer_state(cso
, state
);
2081 cso
->samples
= samples
;
2083 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2085 struct isl_view view
= {
2088 .base_array_layer
= 0,
2090 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2093 struct isl_depth_stencil_hiz_emit_info info
= {
2099 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2102 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2103 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2105 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2108 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2110 info
.depth_surf
= &zres
->surf
;
2111 info
.depth_address
= zres
->bo
->gtt_offset
;
2112 info
.hiz_usage
= ISL_AUX_USAGE_NONE
;
2114 view
.format
= zres
->surf
.format
;
2118 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2119 info
.stencil_surf
= &stencil_res
->surf
;
2120 info
.stencil_address
= stencil_res
->bo
->gtt_offset
;
2122 view
.format
= stencil_res
->surf
.format
;
2126 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2128 /* Make a null surface for unbound buffers */
2129 void *null_surf_map
=
2130 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2131 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2132 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2133 isl_extent3d(MAX2(cso
->width
, 1),
2134 MAX2(cso
->height
, 1),
2135 cso
->layers
? cso
->layers
: 1));
2136 ice
->state
.null_fb
.offset
+=
2137 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2139 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2141 /* Render target change */
2142 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2144 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2147 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2148 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2150 /* The PIPE_CONTROL command description says:
2152 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2153 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2154 * Target Cache Flush by enabling this bit. When render target flush
2155 * is set due to new association of BTI, PS Scoreboard Stall bit must
2156 * be set in this packet."
2158 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2159 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2160 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2161 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2166 upload_ubo_surf_state(struct iris_context
*ice
,
2167 struct iris_const_buffer
*cbuf
,
2168 unsigned buffer_size
)
2170 struct pipe_context
*ctx
= &ice
->ctx
;
2171 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
2173 // XXX: these are not retained forever, use a separate uploader?
2175 upload_state(ice
->state
.surface_uploader
, &cbuf
->surface_state
,
2176 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2177 if (!unlikely(map
)) {
2178 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2182 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2183 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state
.res
);
2184 cbuf
->surface_state
.offset
+= iris_bo_offset_from_base_address(surf_bo
);
2186 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2187 .address
= res
->bo
->gtt_offset
+ cbuf
->data
.offset
,
2188 .size_B
= MIN2(buffer_size
,
2189 res
->bo
->size
- cbuf
->data
.offset
),
2190 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
2196 * The pipe->set_constant_buffer() driver hook.
2198 * This uploads any constant data in user buffers, and references
2199 * any UBO resources containing constant data.
2202 iris_set_constant_buffer(struct pipe_context
*ctx
,
2203 enum pipe_shader_type p_stage
, unsigned index
,
2204 const struct pipe_constant_buffer
*input
)
2206 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2207 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2208 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2209 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
2211 if (input
&& input
->buffer
) {
2214 pipe_resource_reference(&cbuf
->data
.res
, input
->buffer
);
2215 cbuf
->data
.offset
= input
->buffer_offset
;
2217 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2218 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2220 upload_ubo_surf_state(ice
, cbuf
, input
->buffer_size
);
2222 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2223 pipe_resource_reference(&cbuf
->surface_state
.res
, NULL
);
2228 memcpy(&shs
->cbuf0
, input
, sizeof(shs
->cbuf0
));
2230 memset(&shs
->cbuf0
, 0, sizeof(shs
->cbuf0
));
2232 shs
->cbuf0_needs_upload
= true;
2235 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2236 // XXX: maybe not necessary all the time...?
2237 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2238 // XXX: pull model we may need actual new bindings...
2239 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2243 upload_uniforms(struct iris_context
*ice
,
2244 gl_shader_stage stage
)
2246 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2247 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
2248 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2250 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t) +
2251 shs
->cbuf0
.buffer_size
;
2253 if (upload_size
== 0)
2257 upload_state(ice
->ctx
.const_uploader
, &cbuf
->data
, upload_size
, 64);
2259 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2260 uint32_t sysval
= shader
->system_values
[i
];
2263 if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2264 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2265 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2266 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2267 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
2268 if (stage
== MESA_SHADER_TESS_CTRL
) {
2269 value
= ice
->state
.vertices_per_patch
;
2271 assert(stage
== MESA_SHADER_TESS_EVAL
);
2272 const struct shader_info
*tcs_info
=
2273 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
2276 value
= tcs_info
->tess
.tcs_vertices_out
;
2279 assert(!"unhandled system value");
2285 if (shs
->cbuf0
.user_buffer
) {
2286 memcpy(map
, shs
->cbuf0
.user_buffer
, shs
->cbuf0
.buffer_size
);
2289 upload_ubo_surf_state(ice
, cbuf
, upload_size
);
2293 * The pipe->set_shader_buffers() driver hook.
2295 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2296 * SURFACE_STATE here, as the buffer offset may change each time.
2299 iris_set_shader_buffers(struct pipe_context
*ctx
,
2300 enum pipe_shader_type p_stage
,
2301 unsigned start_slot
, unsigned count
,
2302 const struct pipe_shader_buffer
*buffers
)
2304 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2305 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2306 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2307 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2309 for (unsigned i
= 0; i
< count
; i
++) {
2310 if (buffers
&& buffers
[i
].buffer
) {
2311 const struct pipe_shader_buffer
*buffer
= &buffers
[i
];
2312 struct iris_resource
*res
= (void *) buffer
->buffer
;
2313 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], &res
->base
);
2315 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2317 // XXX: these are not retained forever, use a separate uploader?
2319 upload_state(ice
->state
.surface_uploader
,
2320 &shs
->ssbo_surface_state
[start_slot
+ i
],
2321 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2322 if (!unlikely(map
)) {
2323 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2327 struct iris_bo
*surf_state_bo
=
2328 iris_resource_bo(shs
->ssbo_surface_state
[start_slot
+ i
].res
);
2329 shs
->ssbo_surface_state
[start_slot
+ i
].offset
+=
2330 iris_bo_offset_from_base_address(surf_state_bo
);
2332 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2334 res
->bo
->gtt_offset
+ buffer
->buffer_offset
,
2336 MIN2(buffer
->buffer_size
,
2337 res
->bo
->size
- buffer
->buffer_offset
),
2338 .format
= ISL_FORMAT_RAW
,
2342 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2343 pipe_resource_reference(&shs
->ssbo_surface_state
[start_slot
+ i
].res
,
2348 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2352 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2358 * The pipe->set_vertex_buffers() driver hook.
2360 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2363 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2364 unsigned start_slot
, unsigned count
,
2365 const struct pipe_vertex_buffer
*buffers
)
2367 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2368 struct iris_genx_state
*genx
= ice
->state
.genx
;
2370 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
2372 for (unsigned i
= 0; i
< count
; i
++) {
2373 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
2374 struct iris_vertex_buffer_state
*state
=
2375 &genx
->vertex_buffers
[start_slot
+ i
];
2378 pipe_resource_reference(&state
->resource
, NULL
);
2382 assert(!buffer
->is_user_buffer
);
2384 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
2386 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
2387 struct iris_resource
*res
= (void *) state
->resource
;
2390 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2392 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
2393 vb
.VertexBufferIndex
= start_slot
+ i
;
2395 vb
.AddressModifyEnable
= true;
2396 vb
.BufferPitch
= buffer
->stride
;
2398 vb
.BufferSize
= res
->bo
->size
;
2399 vb
.BufferStartingAddress
=
2400 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
2402 vb
.NullVertexBuffer
= true;
2407 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2411 * Gallium CSO for vertex elements.
2413 struct iris_vertex_element_state
{
2414 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2415 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2420 * The pipe->create_vertex_elements() driver hook.
2422 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2423 * and 3DSTATE_VF_INSTANCING commands. SGVs are handled at draw time.
2426 iris_create_vertex_elements(struct pipe_context
*ctx
,
2428 const struct pipe_vertex_element
*state
)
2430 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2431 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2432 struct iris_vertex_element_state
*cso
=
2433 malloc(sizeof(struct iris_vertex_element_state
));
2438 * - create edge flag one
2440 * - if those are necessary, use count + 1/2/3... OR in the length
2442 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2444 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2447 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2448 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2451 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2453 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2454 ve
.Component0Control
= VFCOMP_STORE_0
;
2455 ve
.Component1Control
= VFCOMP_STORE_0
;
2456 ve
.Component2Control
= VFCOMP_STORE_0
;
2457 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2460 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2464 for (int i
= 0; i
< count
; i
++) {
2465 const struct iris_format_info fmt
=
2466 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2467 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2468 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2470 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2471 case 0: comp
[0] = VFCOMP_STORE_0
;
2472 case 1: comp
[1] = VFCOMP_STORE_0
;
2473 case 2: comp
[2] = VFCOMP_STORE_0
;
2475 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2476 : VFCOMP_STORE_1_FP
;
2479 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2480 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2482 ve
.SourceElementOffset
= state
[i
].src_offset
;
2483 ve
.SourceElementFormat
= fmt
.fmt
;
2484 ve
.Component0Control
= comp
[0];
2485 ve
.Component1Control
= comp
[1];
2486 ve
.Component2Control
= comp
[2];
2487 ve
.Component3Control
= comp
[3];
2490 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2491 vi
.VertexElementIndex
= i
;
2492 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2493 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2496 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2497 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2504 * The pipe->bind_vertex_elements_state() driver hook.
2507 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2509 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2510 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2511 struct iris_vertex_element_state
*new_cso
= state
;
2513 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2514 * we need to re-emit it to ensure we're overriding the right one.
2516 if (new_cso
&& cso_changed(count
))
2517 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2519 ice
->state
.cso_vertex_elements
= state
;
2520 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2524 * The pipe->create_stream_output_target() driver hook.
2526 * "Target" here refers to a destination buffer. We translate this into
2527 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2528 * know which buffer this represents, or whether we ought to zero the
2529 * write-offsets, or append. Those are handled in the set() hook.
2531 static struct pipe_stream_output_target
*
2532 iris_create_stream_output_target(struct pipe_context
*ctx
,
2533 struct pipe_resource
*p_res
,
2534 unsigned buffer_offset
,
2535 unsigned buffer_size
)
2537 struct iris_resource
*res
= (void *) p_res
;
2538 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2542 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
2544 pipe_reference_init(&cso
->base
.reference
, 1);
2545 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
2546 cso
->base
.buffer_offset
= buffer_offset
;
2547 cso
->base
.buffer_size
= buffer_size
;
2548 cso
->base
.context
= ctx
;
2550 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
2556 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2557 struct pipe_stream_output_target
*state
)
2559 struct iris_stream_output_target
*cso
= (void *) state
;
2561 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2562 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2568 * The pipe->set_stream_output_targets() driver hook.
2570 * At this point, we know which targets are bound to a particular index,
2571 * and also whether we want to append or start over. We can finish the
2572 * 3DSTATE_SO_BUFFER packets we started earlier.
2575 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2576 unsigned num_targets
,
2577 struct pipe_stream_output_target
**targets
,
2578 const unsigned *offsets
)
2580 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2581 struct iris_genx_state
*genx
= ice
->state
.genx
;
2582 uint32_t *so_buffers
= genx
->so_buffers
;
2584 const bool active
= num_targets
> 0;
2585 if (ice
->state
.streamout_active
!= active
) {
2586 ice
->state
.streamout_active
= active
;
2587 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2589 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
2590 * it's a non-pipelined command. If we're switching streamout on, we
2591 * may have missed emitting it earlier, so do so now. (We're already
2592 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
2595 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
2598 for (int i
= 0; i
< 4; i
++) {
2599 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2600 i
< num_targets
? targets
[i
] : NULL
);
2603 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2607 for (unsigned i
= 0; i
< 4; i
++,
2608 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2610 if (i
>= num_targets
|| !targets
[i
]) {
2611 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
2612 sob
.SOBufferIndex
= i
;
2616 struct iris_stream_output_target
*tgt
= (void *) targets
[i
];
2617 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
2619 /* Note that offsets[i] will either be 0, causing us to zero
2620 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
2621 * "continue appending at the existing offset."
2623 assert(offsets
[i
] == 0 || offsets
[i
] == 0xFFFFFFFF);
2625 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
2626 sob
.SurfaceBaseAddress
=
2627 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
2628 sob
.SOBufferEnable
= true;
2629 sob
.StreamOffsetWriteEnable
= true;
2630 sob
.StreamOutputBufferOffsetAddressEnable
= true;
2631 sob
.MOCS
= MOCS_WB
; // XXX: MOCS
2633 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
2635 sob
.SOBufferIndex
= i
;
2636 sob
.StreamOffset
= offsets
[i
];
2637 sob
.StreamOutputBufferOffsetAddress
=
2638 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
2639 tgt
->offset
.offset
);
2643 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
2647 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
2648 * 3DSTATE_STREAMOUT packets.
2650 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
2651 * hardware to record. We can create it entirely based on the shader, with
2652 * no dynamic state dependencies.
2654 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
2655 * state-based settings. We capture the shader-related ones here, and merge
2656 * the rest in at draw time.
2659 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
2660 const struct brw_vue_map
*vue_map
)
2662 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2663 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2664 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2665 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2667 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2669 memset(so_decl
, 0, sizeof(so_decl
));
2671 /* Construct the list of SO_DECLs to be emitted. The formatting of the
2672 * command feels strange -- each dword pair contains a SO_DECL per stream.
2674 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
2675 const struct pipe_stream_output
*output
= &info
->output
[i
];
2676 const int buffer
= output
->output_buffer
;
2677 const int varying
= output
->register_index
;
2678 const unsigned stream_id
= output
->stream
;
2679 assert(stream_id
< MAX_VERTEX_STREAMS
);
2681 buffer_mask
[stream_id
] |= 1 << buffer
;
2683 assert(vue_map
->varying_to_slot
[varying
] >= 0);
2685 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
2686 * array. Instead, it simply increments DstOffset for the following
2687 * input by the number of components that should be skipped.
2689 * Our hardware is unusual in that it requires us to program SO_DECLs
2690 * for fake "hole" components, rather than simply taking the offset
2691 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
2692 * program as many size = 4 holes as we can, then a final hole to
2693 * accommodate the final 1, 2, or 3 remaining.
2695 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
2697 while (skip_components
> 0) {
2698 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2700 .OutputBufferSlot
= output
->output_buffer
,
2701 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
2703 skip_components
-= 4;
2706 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
2708 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2709 .OutputBufferSlot
= output
->output_buffer
,
2710 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
2712 ((1 << output
->num_components
) - 1) << output
->start_component
,
2715 if (decls
[stream_id
] > max_decls
)
2716 max_decls
= decls
[stream_id
];
2719 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
2720 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
2721 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
2723 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
2724 int urb_entry_read_offset
= 0;
2725 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
2726 urb_entry_read_offset
;
2728 /* We always read the whole vertex. This could be reduced at some
2729 * point by reading less and offsetting the register index in the
2732 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
2733 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
2734 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
2735 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
2736 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
2737 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
2738 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
2739 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
2741 /* Set buffer pitches; 0 means unbound. */
2742 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
2743 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
2744 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
2745 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
2748 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
2749 list
.DWordLength
= 3 + 2 * max_decls
- 2;
2750 list
.StreamtoBufferSelects0
= buffer_mask
[0];
2751 list
.StreamtoBufferSelects1
= buffer_mask
[1];
2752 list
.StreamtoBufferSelects2
= buffer_mask
[2];
2753 list
.StreamtoBufferSelects3
= buffer_mask
[3];
2754 list
.NumEntries0
= decls
[0];
2755 list
.NumEntries1
= decls
[1];
2756 list
.NumEntries2
= decls
[2];
2757 list
.NumEntries3
= decls
[3];
2760 for (int i
= 0; i
< max_decls
; i
++) {
2761 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
2762 entry
.Stream0Decl
= so_decl
[0][i
];
2763 entry
.Stream1Decl
= so_decl
[1][i
];
2764 entry
.Stream2Decl
= so_decl
[2][i
];
2765 entry
.Stream3Decl
= so_decl
[3][i
];
2773 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
2774 const struct brw_vue_map
*last_vue_map
,
2775 bool two_sided_color
,
2776 unsigned *out_offset
,
2777 unsigned *out_length
)
2779 /* The compiler computes the first URB slot without considering COL/BFC
2780 * swizzling (because it doesn't know whether it's enabled), so we need
2781 * to do that here too. This may result in a smaller offset, which
2784 const unsigned first_slot
=
2785 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
2787 /* This becomes the URB read offset (counted in pairs of slots). */
2788 assert(first_slot
% 2 == 0);
2789 *out_offset
= first_slot
/ 2;
2791 /* We need to adjust the inputs read to account for front/back color
2792 * swizzling, as it can make the URB length longer.
2794 for (int c
= 0; c
<= 1; c
++) {
2795 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
2796 /* If two sided color is enabled, the fragment shader's gl_Color
2797 * (COL0) input comes from either the gl_FrontColor (COL0) or
2798 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
2800 if (two_sided_color
)
2801 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2803 /* If front color isn't written, we opt to give them back color
2804 * instead of an undefined value. Switch from COL to BFC.
2806 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
2807 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
2808 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2813 /* Compute the minimum URB Read Length necessary for the FS inputs.
2815 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
2816 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
2818 * "This field should be set to the minimum length required to read the
2819 * maximum source attribute. The maximum source attribute is indicated
2820 * by the maximum value of the enabled Attribute # Source Attribute if
2821 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
2822 * enable is not set.
2823 * read_length = ceiling((max_source_attr + 1) / 2)
2825 * [errata] Corruption/Hang possible if length programmed larger than
2828 * Similar text exists for Ivy Bridge.
2830 * We find the last URB slot that's actually read by the FS.
2832 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
2833 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
2834 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
2837 /* The URB read length is the difference of the two, counted in pairs. */
2838 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
2842 iris_emit_sbe_swiz(struct iris_batch
*batch
,
2843 const struct iris_context
*ice
,
2844 unsigned urb_read_offset
,
2845 unsigned sprite_coord_enables
)
2847 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
2848 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2849 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2850 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
2851 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2853 /* XXX: this should be generated when putting programs in place */
2855 // XXX: raster->sprite_coord_enable
2857 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
2858 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
2859 if (input_index
< 0 || input_index
>= 16)
2862 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
2863 &attr_overrides
[input_index
];
2864 int slot
= vue_map
->varying_to_slot
[fs_attr
];
2866 /* Viewport and Layer are stored in the VUE header. We need to override
2867 * them to zero if earlier stages didn't write them, as GL requires that
2868 * they read back as zero when not explicitly set.
2871 case VARYING_SLOT_VIEWPORT
:
2872 case VARYING_SLOT_LAYER
:
2873 attr
->ComponentOverrideX
= true;
2874 attr
->ComponentOverrideW
= true;
2875 attr
->ConstantSource
= CONST_0000
;
2877 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
2878 attr
->ComponentOverrideY
= true;
2879 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
2880 attr
->ComponentOverrideZ
= true;
2883 case VARYING_SLOT_PRIMITIVE_ID
:
2884 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
2886 attr
->ComponentOverrideX
= true;
2887 attr
->ComponentOverrideY
= true;
2888 attr
->ComponentOverrideZ
= true;
2889 attr
->ComponentOverrideW
= true;
2890 attr
->ConstantSource
= PRIM_ID
;
2898 if (sprite_coord_enables
& (1 << input_index
))
2901 /* If there was only a back color written but not front, use back
2902 * as the color instead of undefined.
2904 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
2905 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
2906 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
2907 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
2909 /* Not written by the previous stage - undefined. */
2911 attr
->ComponentOverrideX
= true;
2912 attr
->ComponentOverrideY
= true;
2913 attr
->ComponentOverrideZ
= true;
2914 attr
->ComponentOverrideW
= true;
2915 attr
->ConstantSource
= CONST_0001_FLOAT
;
2919 /* Compute the location of the attribute relative to the read offset,
2920 * which is counted in 256-bit increments (two 128-bit VUE slots).
2922 const int source_attr
= slot
- 2 * urb_read_offset
;
2923 assert(source_attr
>= 0 && source_attr
<= 32);
2924 attr
->SourceAttribute
= source_attr
;
2926 /* If we are doing two-sided color, and the VUE slot following this one
2927 * represents a back-facing color, then we need to instruct the SF unit
2928 * to do back-facing swizzling.
2930 if (cso_rast
->light_twoside
&&
2931 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
2932 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
2933 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
2934 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
2935 attr
->SwizzleSelect
= INPUTATTR_FACING
;
2938 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
2939 for (int i
= 0; i
< 16; i
++)
2940 sbes
.Attribute
[i
] = attr_overrides
[i
];
2945 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
2946 const struct iris_rasterizer_state
*cso
)
2948 unsigned overrides
= 0;
2950 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
2951 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
2953 for (int i
= 0; i
< 8; i
++) {
2954 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
2955 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
2956 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
2963 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
2965 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2966 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2967 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2968 const struct shader_info
*fs_info
=
2969 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
2971 unsigned urb_read_offset
, urb_read_length
;
2972 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
2973 ice
->shaders
.last_vue_map
,
2974 cso_rast
->light_twoside
,
2975 &urb_read_offset
, &urb_read_length
);
2977 unsigned sprite_coord_overrides
=
2978 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
2980 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
2981 sbe
.AttributeSwizzleEnable
= true;
2982 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2983 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
2984 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
2985 sbe
.VertexURBEntryReadLength
= urb_read_length
;
2986 sbe
.ForceVertexURBEntryReadOffset
= true;
2987 sbe
.ForceVertexURBEntryReadLength
= true;
2988 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
2989 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
2991 for (int i
= 0; i
< 32; i
++) {
2992 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
2996 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
2999 /* ------------------------------------------------------------------- */
3002 * Populate VS program key fields based on the current state.
3005 iris_populate_vs_key(const struct iris_context
*ice
,
3006 const struct shader_info
*info
,
3007 struct brw_vs_prog_key
*key
)
3009 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3011 if (info
->clip_distance_array_size
== 0 &&
3012 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)))
3013 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3017 * Populate TCS program key fields based on the current state.
3020 iris_populate_tcs_key(const struct iris_context
*ice
,
3021 struct brw_tcs_prog_key
*key
)
3026 * Populate TES program key fields based on the current state.
3029 iris_populate_tes_key(const struct iris_context
*ice
,
3030 struct brw_tes_prog_key
*key
)
3035 * Populate GS program key fields based on the current state.
3038 iris_populate_gs_key(const struct iris_context
*ice
,
3039 struct brw_gs_prog_key
*key
)
3044 * Populate FS program key fields based on the current state.
3047 iris_populate_fs_key(const struct iris_context
*ice
,
3048 struct brw_wm_prog_key
*key
)
3050 /* XXX: dirty flags? */
3051 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3052 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3053 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3054 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3056 key
->nr_color_regions
= fb
->nr_cbufs
;
3058 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3060 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
3061 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
3063 /* XXX: only bother if COL0/1 are read */
3064 key
->flat_shade
= rast
->flatshade
;
3066 key
->persample_interp
= rast
->force_persample_interp
;
3067 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3069 key
->coherent_fb_fetch
= true;
3071 // XXX: uint64_t input_slots_valid; - for >16 inputs
3073 // XXX: key->force_dual_color_blend for unigine
3074 // XXX: respect hint for high_quality_derivatives:1;
3078 iris_populate_cs_key(const struct iris_context
*ice
,
3079 struct brw_cs_prog_key
*key
)
3084 // XXX: these need to go in INIT_THREAD_DISPATCH_FIELDS
3085 pkt
.SamplerCount
= \
3086 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4); \
3091 KSP(const struct iris_compiled_shader
*shader
)
3093 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3094 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3097 // Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3098 // prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3099 // this WA on C0 stepping.
3101 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3102 pkt.KernelStartPointer = KSP(shader); \
3103 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3104 prog_data->binding_table.size_bytes / 4; \
3105 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3107 pkt.DispatchGRFStartRegisterForURBData = \
3108 prog_data->dispatch_grf_start_reg; \
3109 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3110 pkt.prefix##URBEntryReadOffset = 0; \
3112 pkt.StatisticsEnable = true; \
3113 pkt.Enable = true; \
3115 if (prog_data->total_scratch) { \
3116 uint32_t scratch_addr = \
3117 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3118 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3119 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3123 * Encode most of 3DSTATE_VS based on the compiled shader.
3126 iris_store_vs_state(struct iris_context
*ice
,
3127 const struct gen_device_info
*devinfo
,
3128 struct iris_compiled_shader
*shader
)
3130 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3131 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3133 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3134 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3135 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3136 vs
.SIMD8DispatchEnable
= true;
3137 vs
.UserClipDistanceCullTestEnableBitmask
=
3138 vue_prog_data
->cull_distance_mask
;
3143 * Encode most of 3DSTATE_HS based on the compiled shader.
3146 iris_store_tcs_state(struct iris_context
*ice
,
3147 const struct gen_device_info
*devinfo
,
3148 struct iris_compiled_shader
*shader
)
3150 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3151 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3152 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3154 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3155 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3157 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3158 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3159 hs
.IncludeVertexHandles
= true;
3164 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3167 iris_store_tes_state(struct iris_context
*ice
,
3168 const struct gen_device_info
*devinfo
,
3169 struct iris_compiled_shader
*shader
)
3171 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3172 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3173 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3175 uint32_t *te_state
= (void *) shader
->derived_data
;
3176 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3178 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3179 te
.Partitioning
= tes_prog_data
->partitioning
;
3180 te
.OutputTopology
= tes_prog_data
->output_topology
;
3181 te
.TEDomain
= tes_prog_data
->domain
;
3183 te
.MaximumTessellationFactorOdd
= 63.0;
3184 te
.MaximumTessellationFactorNotOdd
= 64.0;
3187 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3188 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3190 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3191 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3192 ds
.ComputeWCoordinateEnable
=
3193 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3195 ds
.UserClipDistanceCullTestEnableBitmask
=
3196 vue_prog_data
->cull_distance_mask
;
3202 * Encode most of 3DSTATE_GS based on the compiled shader.
3205 iris_store_gs_state(struct iris_context
*ice
,
3206 const struct gen_device_info
*devinfo
,
3207 struct iris_compiled_shader
*shader
)
3209 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3210 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3211 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3213 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3214 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3216 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3217 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3218 gs
.ControlDataHeaderSize
=
3219 gs_prog_data
->control_data_header_size_hwords
;
3220 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3221 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3222 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3223 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3224 gs
.ReorderMode
= TRAILING
;
3225 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3226 gs
.MaximumNumberofThreads
=
3227 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3228 : (devinfo
->max_gs_threads
- 1);
3230 if (gs_prog_data
->static_vertex_count
!= -1) {
3231 gs
.StaticOutput
= true;
3232 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3234 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3236 gs
.UserClipDistanceCullTestEnableBitmask
=
3237 vue_prog_data
->cull_distance_mask
;
3239 const int urb_entry_write_offset
= 1;
3240 const uint32_t urb_entry_output_length
=
3241 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3242 urb_entry_write_offset
;
3244 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3245 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3250 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3253 iris_store_fs_state(struct iris_context
*ice
,
3254 const struct gen_device_info
*devinfo
,
3255 struct iris_compiled_shader
*shader
)
3257 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3258 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3260 uint32_t *ps_state
= (void *) shader
->derived_data
;
3261 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3263 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3264 ps
.VectorMaskEnable
= true;
3265 //ps.SamplerCount = ...
3266 // XXX: WABTPPrefetchDisable, see above, drop at C0
3267 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3268 prog_data
->binding_table
.size_bytes
/ 4;
3269 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3270 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3272 ps
.PushConstantEnable
= shader
->num_system_values
> 0 ||
3273 prog_data
->ubo_ranges
[0].length
> 0;
3275 /* From the documentation for this packet:
3276 * "If the PS kernel does not need the Position XY Offsets to
3277 * compute a Position Value, then this field should be programmed
3278 * to POSOFFSET_NONE."
3280 * "SW Recommendation: If the PS kernel needs the Position Offsets
3281 * to compute a Position XY value, this field should match Position
3282 * ZW Interpolation Mode to ensure a consistent position.xyzw
3285 * We only require XY sample offsets. So, this recommendation doesn't
3286 * look useful at the moment. We might need this in future.
3288 ps
.PositionXYOffsetSelect
=
3289 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3290 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
3291 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
3292 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
3294 // XXX: Disable SIMD32 with 16x MSAA
3296 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3297 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
3298 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
3299 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
3300 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3301 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
3303 ps
.KernelStartPointer0
=
3304 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
3305 ps
.KernelStartPointer1
=
3306 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
3307 ps
.KernelStartPointer2
=
3308 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
3310 if (prog_data
->total_scratch
) {
3311 uint32_t scratch_addr
=
3312 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3313 MESA_SHADER_FRAGMENT
);
3314 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3315 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3319 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3320 psx
.PixelShaderValid
= true;
3321 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3322 // XXX: alpha test / alpha to coverage :/
3323 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
||
3324 wm_prog_data
->uses_omask
;
3325 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3326 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3327 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3328 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3330 if (wm_prog_data
->uses_sample_mask
) {
3331 /* TODO: conservative rasterization */
3332 if (wm_prog_data
->post_depth_coverage
)
3333 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
3335 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
3338 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3339 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3340 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3347 * Compute the size of the derived data (shader command packets).
3349 * This must match the data written by the iris_store_xs_state() functions.
3352 iris_store_cs_state(struct iris_context
*ice
,
3353 const struct gen_device_info
*devinfo
,
3354 struct iris_compiled_shader
*shader
)
3356 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3357 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3358 void *map
= shader
->derived_data
;
3360 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3361 desc
.KernelStartPointer
= KSP(shader
);
3362 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3363 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3364 desc
.SharedLocalMemorySize
=
3365 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3366 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3367 desc
.CrossThreadConstantDataReadLength
=
3368 cs_prog_data
->push
.cross_thread
.regs
;
3373 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3375 assert(cache_id
<= IRIS_CACHE_BLORP
);
3377 static const unsigned dwords
[] = {
3378 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3379 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3380 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3381 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3383 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3384 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3385 [IRIS_CACHE_BLORP
] = 0,
3388 return sizeof(uint32_t) * dwords
[cache_id
];
3392 * Create any state packets corresponding to the given shader stage
3393 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3394 * This means that we can look up a program in the in-memory cache and
3395 * get most of the state packet without having to reconstruct it.
3398 iris_store_derived_program_state(struct iris_context
*ice
,
3399 enum iris_program_cache_id cache_id
,
3400 struct iris_compiled_shader
*shader
)
3402 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3403 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3407 iris_store_vs_state(ice
, devinfo
, shader
);
3409 case IRIS_CACHE_TCS
:
3410 iris_store_tcs_state(ice
, devinfo
, shader
);
3412 case IRIS_CACHE_TES
:
3413 iris_store_tes_state(ice
, devinfo
, shader
);
3416 iris_store_gs_state(ice
, devinfo
, shader
);
3419 iris_store_fs_state(ice
, devinfo
, shader
);
3422 iris_store_cs_state(ice
, devinfo
, shader
);
3423 case IRIS_CACHE_BLORP
:
3430 /* ------------------------------------------------------------------- */
3433 * Configure the URB.
3435 * XXX: write a real comment.
3438 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
3440 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
3441 const unsigned push_size_kB
= 32;
3442 unsigned entries
[4];
3446 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3447 if (!ice
->shaders
.prog
[i
]) {
3450 struct brw_vue_prog_data
*vue_prog_data
=
3451 (void *) ice
->shaders
.prog
[i
]->prog_data
;
3452 size
[i
] = vue_prog_data
->urb_entry_size
;
3454 assert(size
[i
] != 0);
3457 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
3458 1024 * ice
->shaders
.urb_size
,
3459 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
3460 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
3461 size
, entries
, start
);
3463 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3464 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
3465 urb
._3DCommandSubOpcode
+= i
;
3466 urb
.VSURBStartingAddress
= start
[i
];
3467 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
3468 urb
.VSNumberofURBEntries
= entries
[i
];
3473 static const uint32_t push_constant_opcodes
[] = {
3474 [MESA_SHADER_VERTEX
] = 21,
3475 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3476 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3477 [MESA_SHADER_GEOMETRY
] = 22,
3478 [MESA_SHADER_FRAGMENT
] = 23,
3479 [MESA_SHADER_COMPUTE
] = 0,
3483 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3485 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3487 iris_use_pinned_bo(batch
, state_bo
, false);
3489 return ice
->state
.unbound_tex
.offset
;
3493 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3495 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3496 if (!ice
->state
.null_fb
.res
)
3497 return use_null_surface(batch
, ice
);
3499 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3501 iris_use_pinned_bo(batch
, state_bo
, false);
3503 return ice
->state
.null_fb
.offset
;
3507 * Add a surface to the validation list, as well as the buffer containing
3508 * the corresponding SURFACE_STATE.
3510 * Returns the binding table entry (offset to SURFACE_STATE).
3513 use_surface(struct iris_batch
*batch
,
3514 struct pipe_surface
*p_surf
,
3517 struct iris_surface
*surf
= (void *) p_surf
;
3519 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
3520 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
3522 return surf
->surface_state
.offset
;
3526 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
3528 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
3529 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
3531 return isv
->surface_state
.offset
;
3535 use_const_buffer(struct iris_batch
*batch
,
3536 struct iris_context
*ice
,
3537 struct iris_const_buffer
*cbuf
)
3539 if (!cbuf
->surface_state
.res
)
3540 return use_null_surface(batch
, ice
);
3542 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->data
.res
), false);
3543 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->surface_state
.res
), false);
3545 return cbuf
->surface_state
.offset
;
3549 use_ssbo(struct iris_batch
*batch
, struct iris_context
*ice
,
3550 struct iris_shader_state
*shs
, int i
)
3553 return use_null_surface(batch
, ice
);
3555 struct iris_state_ref
*surf_state
= &shs
->ssbo_surface_state
[i
];
3557 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->ssbo
[i
]), true);
3558 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3560 return surf_state
->offset
;
3564 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
3565 struct iris_shader_state
*shs
, int i
)
3567 if (!shs
->image
[i
].res
)
3568 return use_null_surface(batch
, ice
);
3570 struct iris_state_ref
*surf_state
= &shs
->image
[i
].surface_state
;
3572 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->image
[i
].res
),
3573 shs
->image
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
);
3574 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3576 return surf_state
->offset
;
3579 #define push_bt_entry(addr) \
3580 assert(addr >= binder_addr); \
3581 assert(s < prog_data->binding_table.size_bytes / sizeof(uint32_t)); \
3582 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
3584 #define bt_assert(section, exists) \
3585 if (!pin_only) assert(prog_data->binding_table.section == \
3586 (exists) ? s : 0xd0d0d0d0)
3589 * Populate the binding table for a given shader stage.
3591 * This fills out the table of pointers to surfaces required by the shader,
3592 * and also adds those buffers to the validation list so the kernel can make
3593 * resident before running our batch.
3596 iris_populate_binding_table(struct iris_context
*ice
,
3597 struct iris_batch
*batch
,
3598 gl_shader_stage stage
,
3601 const struct iris_binder
*binder
= &ice
->state
.binder
;
3602 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3606 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3607 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3608 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
3610 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
3611 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
3614 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
3616 /* TCS passthrough doesn't need a binding table. */
3617 assert(stage
== MESA_SHADER_TESS_CTRL
);
3621 if (stage
== MESA_SHADER_COMPUTE
) {
3622 /* surface for gl_NumWorkGroups */
3623 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
3624 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
3625 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
3626 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
3627 push_bt_entry(grid_state
->offset
);
3630 if (stage
== MESA_SHADER_FRAGMENT
) {
3631 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3632 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
3633 if (cso_fb
->nr_cbufs
) {
3634 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
3636 cso_fb
->cbufs
[i
] ? use_surface(batch
, cso_fb
->cbufs
[i
], true)
3637 : use_null_fb_surface(batch
, ice
);
3638 push_bt_entry(addr
);
3641 uint32_t addr
= use_null_fb_surface(batch
, ice
);
3642 push_bt_entry(addr
);
3646 bt_assert(texture_start
, info
->num_textures
> 0);
3648 for (int i
= 0; i
< info
->num_textures
; i
++) {
3649 struct iris_sampler_view
*view
= shs
->textures
[i
];
3650 uint32_t addr
= view
? use_sampler_view(batch
, view
)
3651 : use_null_surface(batch
, ice
);
3652 push_bt_entry(addr
);
3655 bt_assert(image_start
, info
->num_images
> 0);
3657 for (int i
= 0; i
< info
->num_images
; i
++) {
3658 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
3659 push_bt_entry(addr
);
3662 const int num_ubos
= iris_get_shader_num_ubos(ice
, stage
);
3664 bt_assert(ubo_start
, num_ubos
> 0);
3666 for (int i
= 0; i
< num_ubos
; i
++) {
3667 uint32_t addr
= use_const_buffer(batch
, ice
, &shs
->constbuf
[i
]);
3668 push_bt_entry(addr
);
3671 bt_assert(ssbo_start
, info
->num_abos
+ info
->num_ssbos
> 0);
3673 /* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
3674 * for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
3675 * in st_atom_storagebuf.c so it'll compact them into one range, with
3676 * SSBOs starting at info->num_abos. Ideally it'd reset num_abos to 0 too
3678 if (info
->num_abos
+ info
->num_ssbos
> 0) {
3679 for (int i
= 0; i
< IRIS_MAX_ABOS
+ info
->num_ssbos
; i
++) {
3680 uint32_t addr
= use_ssbo(batch
, ice
, shs
, i
);
3681 push_bt_entry(addr
);
3686 // XXX: not implemented yet
3687 bt_assert(plane_start
[1], ...);
3688 bt_assert(plane_start
[2], ...);
3693 iris_use_optional_res(struct iris_batch
*batch
,
3694 struct pipe_resource
*res
,
3698 struct iris_bo
*bo
= iris_resource_bo(res
);
3699 iris_use_pinned_bo(batch
, bo
, writeable
);
3703 /* ------------------------------------------------------------------- */
3706 * Pin any BOs which were installed by a previous batch, and restored
3707 * via the hardware logical context mechanism.
3709 * We don't need to re-emit all state every batch - the hardware context
3710 * mechanism will save and restore it for us. This includes pointers to
3711 * various BOs...which won't exist unless we ask the kernel to pin them
3712 * by adding them to the validation list.
3714 * We can skip buffers if we've re-emitted those packets, as we're
3715 * overwriting those stale pointers with new ones, and don't actually
3716 * refer to the old BOs.
3719 iris_restore_render_saved_bos(struct iris_context
*ice
,
3720 struct iris_batch
*batch
,
3721 const struct pipe_draw_info
*draw
)
3723 struct iris_genx_state
*genx
= ice
->state
.genx
;
3725 // XXX: whack IRIS_SHADER_DIRTY_BINDING_TABLE on new batch
3727 const uint64_t clean
= ~ice
->state
.dirty
;
3729 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
3730 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
3733 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3734 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
3737 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
3738 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
3741 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3742 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
3745 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
3746 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
3749 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
3750 for (int i
= 0; i
< 4; i
++) {
3751 struct iris_stream_output_target
*tgt
=
3752 (void *) ice
->state
.so_target
[i
];
3754 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
3756 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
3762 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3763 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
3766 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3767 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3772 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3774 for (int i
= 0; i
< 4; i
++) {
3775 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3777 if (range
->length
== 0)
3780 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3781 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3784 iris_use_pinned_bo(batch
, res
->bo
, false);
3786 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3790 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3791 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
3792 /* Re-pin any buffers referred to by the binding table. */
3793 iris_populate_binding_table(ice
, batch
, stage
, true);
3797 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3798 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3799 struct pipe_resource
*res
= shs
->sampler_table
.res
;
3801 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3804 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3805 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
3806 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3808 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3809 iris_use_pinned_bo(batch
, bo
, false);
3812 // XXX: scratch buffer
3816 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
3817 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3819 if (cso_fb
->zsbuf
) {
3820 struct iris_resource
*zres
, *sres
;
3821 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
3823 // XXX: might not be writable...
3825 iris_use_pinned_bo(batch
, zres
->bo
, true);
3827 iris_use_pinned_bo(batch
, sres
->bo
, true);
3831 if (draw
->index_size
== 0 && ice
->state
.last_res
.index_buffer
) {
3832 /* This draw didn't emit a new index buffer, so we are inheriting the
3833 * older index buffer. This draw didn't need it, but future ones may.
3835 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
3836 iris_use_pinned_bo(batch
, bo
, false);
3839 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
3840 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
3842 const int i
= u_bit_scan64(&bound
);
3843 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
3844 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3850 iris_restore_compute_saved_bos(struct iris_context
*ice
,
3851 struct iris_batch
*batch
,
3852 const struct pipe_grid_info
*grid
)
3854 const uint64_t clean
= ~ice
->state
.dirty
;
3856 const int stage
= MESA_SHADER_COMPUTE
;
3857 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3859 if (clean
& IRIS_DIRTY_CONSTANTS_CS
) {
3860 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3863 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3864 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[0];
3866 if (range
->length
> 0) {
3867 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3868 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3871 iris_use_pinned_bo(batch
, res
->bo
, false);
3873 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3878 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
3879 /* Re-pin any buffers referred to by the binding table. */
3880 iris_populate_binding_table(ice
, batch
, stage
, true);
3883 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
3885 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
3887 if (clean
& IRIS_DIRTY_CS
) {
3888 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3890 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3891 iris_use_pinned_bo(batch
, bo
, false);
3894 // XXX: scratch buffer
3899 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
3902 iris_update_surface_base_address(struct iris_batch
*batch
,
3903 struct iris_binder
*binder
)
3905 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
3908 flush_for_state_base_change(batch
);
3910 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
3911 // XXX: sba.SurfaceStateMemoryObjectControlState = MOCS_WB;
3912 sba
.SurfaceStateBaseAddressModifyEnable
= true;
3913 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
3916 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
3920 iris_upload_dirty_render_state(struct iris_context
*ice
,
3921 struct iris_batch
*batch
,
3922 const struct pipe_draw_info
*draw
)
3924 const uint64_t dirty
= ice
->state
.dirty
;
3926 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
3929 struct iris_genx_state
*genx
= ice
->state
.genx
;
3930 struct iris_binder
*binder
= &ice
->state
.binder
;
3931 struct brw_wm_prog_data
*wm_prog_data
= (void *)
3932 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3934 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
3935 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3936 uint32_t cc_vp_address
;
3938 /* XXX: could avoid streaming for depth_clip [0,1] case. */
3939 uint32_t *cc_vp_map
=
3940 stream_state(batch
, ice
->state
.dynamic_uploader
,
3941 &ice
->state
.last_res
.cc_vp
,
3942 4 * ice
->state
.num_viewports
*
3943 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
3944 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
3946 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
3947 cso_rast
->clip_halfz
, &zmin
, &zmax
);
3948 if (cso_rast
->depth_clip_near
)
3950 if (cso_rast
->depth_clip_far
)
3953 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
3954 ccv
.MinimumDepth
= zmin
;
3955 ccv
.MaximumDepth
= zmax
;
3958 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
3961 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
3962 ptr
.CCViewportPointer
= cc_vp_address
;
3966 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3967 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3968 uint32_t sf_cl_vp_address
;
3970 stream_state(batch
, ice
->state
.dynamic_uploader
,
3971 &ice
->state
.last_res
.sf_cl_vp
,
3972 4 * ice
->state
.num_viewports
*
3973 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
3975 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
3976 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
3977 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
3979 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
3980 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
3981 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
3982 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
3984 calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
3985 state
->scale
[0], state
->scale
[1],
3986 state
->translate
[0], state
->translate
[1],
3987 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
3989 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
3990 vp
.ViewportMatrixElementm00
= state
->scale
[0];
3991 vp
.ViewportMatrixElementm11
= state
->scale
[1];
3992 vp
.ViewportMatrixElementm22
= state
->scale
[2];
3993 vp
.ViewportMatrixElementm30
= state
->translate
[0];
3994 vp
.ViewportMatrixElementm31
= state
->translate
[1];
3995 vp
.ViewportMatrixElementm32
= state
->translate
[2];
3996 vp
.XMinClipGuardband
= gb_xmin
;
3997 vp
.XMaxClipGuardband
= gb_xmax
;
3998 vp
.YMinClipGuardband
= gb_ymin
;
3999 vp
.YMaxClipGuardband
= gb_ymax
;
4000 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
4001 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
4002 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
4003 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
4006 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
4009 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
4010 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
4016 // XXX: this is only flagged at setup, we assume a static configuration
4017 if (dirty
& IRIS_DIRTY_URB
) {
4018 iris_upload_urb_config(ice
, batch
);
4021 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
4022 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4023 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4024 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4025 const int header_dwords
= GENX(BLEND_STATE_length
);
4026 const int rt_dwords
= cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
);
4027 uint32_t blend_offset
;
4028 uint32_t *blend_map
=
4029 stream_state(batch
, ice
->state
.dynamic_uploader
,
4030 &ice
->state
.last_res
.blend
,
4031 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4033 uint32_t blend_state_header
;
4034 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4035 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4036 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4039 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4040 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4042 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4043 ptr
.BlendStatePointer
= blend_offset
;
4044 ptr
.BlendStatePointerValid
= true;
4048 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4049 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4052 stream_state(batch
, ice
->state
.dynamic_uploader
,
4053 &ice
->state
.last_res
.color_calc
,
4054 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4056 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4057 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4058 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4059 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4060 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4061 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4062 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4064 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4065 ptr
.ColorCalcStatePointer
= cc_offset
;
4066 ptr
.ColorCalcStatePointerValid
= true;
4070 /* Upload constants for TCS passthrough. */
4071 if ((dirty
& IRIS_DIRTY_CONSTANTS_TCS
) &&
4072 ice
->shaders
.prog
[MESA_SHADER_TESS_CTRL
] &&
4073 !ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
]) {
4074 struct iris_compiled_shader
*tes_shader
= ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
4077 /* Passthrough always copies 2 vec4s, so when uploading data we ensure
4078 * it is in the right layout for TES.
4081 struct brw_tes_prog_data
*tes_prog_data
= (void *) tes_shader
->prog_data
;
4082 switch (tes_prog_data
->domain
) {
4083 case BRW_TESS_DOMAIN_QUAD
:
4084 for (int i
= 0; i
< 4; i
++)
4085 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4086 hdr
[3] = ice
->state
.default_inner_level
[0];
4087 hdr
[2] = ice
->state
.default_inner_level
[1];
4089 case BRW_TESS_DOMAIN_TRI
:
4090 for (int i
= 0; i
< 3; i
++)
4091 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4092 hdr
[4] = ice
->state
.default_inner_level
[0];
4094 case BRW_TESS_DOMAIN_ISOLINE
:
4095 hdr
[7] = ice
->state
.default_outer_level
[1];
4096 hdr
[6] = ice
->state
.default_outer_level
[0];
4100 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
4101 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
4102 u_upload_data(ice
->ctx
.const_uploader
, 0, sizeof(hdr
), 32,
4103 &hdr
[0], &cbuf
->data
.offset
,
4107 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4108 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4111 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4112 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4117 if (shs
->cbuf0_needs_upload
)
4118 upload_uniforms(ice
, stage
);
4120 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4122 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4123 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4125 /* The Skylake PRM contains the following restriction:
4127 * "The driver must ensure The following case does not occur
4128 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4129 * buffer 3 read length equal to zero committed followed by a
4130 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4133 * To avoid this, we program the buffers in the highest slots.
4134 * This way, slot 0 is only used if slot 3 is also used.
4138 for (int i
= 3; i
>= 0; i
--) {
4139 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4141 if (range
->length
== 0)
4144 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4145 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
4147 assert(cbuf
->data
.offset
% 32 == 0);
4149 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4150 pkt
.ConstantBody
.Buffer
[n
] =
4151 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->data
.offset
)
4152 : ro_bo(batch
->screen
->workaround_bo
, 0);
4159 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4160 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4161 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4162 ptr
._3DCommandSubOpcode
= 38 + stage
;
4163 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4168 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4169 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4170 iris_populate_binding_table(ice
, batch
, stage
, false);
4174 if (ice
->state
.need_border_colors
)
4175 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4177 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4178 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4179 !ice
->shaders
.prog
[stage
])
4182 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4183 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4185 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4187 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4188 ptr
._3DCommandSubOpcode
= 43 + stage
;
4189 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4193 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4194 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4196 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4197 if (ice
->state
.framebuffer
.samples
> 0)
4198 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4202 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4203 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4204 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
4208 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4209 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4212 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4215 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4216 iris_use_pinned_bo(batch
, cache
->bo
, false);
4217 iris_batch_emit(batch
, shader
->derived_data
,
4218 iris_derived_program_state_size(stage
));
4220 if (stage
== MESA_SHADER_TESS_EVAL
) {
4221 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4222 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4223 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4224 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4225 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4230 if (ice
->state
.streamout_active
) {
4231 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4232 iris_batch_emit(batch
, genx
->so_buffers
,
4233 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4234 for (int i
= 0; i
< 4; i
++) {
4235 struct iris_stream_output_target
*tgt
=
4236 (void *) ice
->state
.so_target
[i
];
4238 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4240 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4246 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
4247 uint32_t *decl_list
=
4248 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
4249 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
4252 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4253 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4255 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
4256 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
4257 sol
.SOFunctionEnable
= true;
4258 sol
.SOStatisticsEnable
= true;
4260 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
4261 !ice
->state
.prims_generated_query_active
;
4262 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
4265 assert(ice
->state
.streamout
);
4267 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
4268 GENX(3DSTATE_STREAMOUT_length
));
4271 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4272 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
4276 if (dirty
& IRIS_DIRTY_CLIP
) {
4277 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4278 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4280 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
4281 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
4282 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4283 cl
.ClipMode
= cso_rast
->rasterizer_discard
? CLIPMODE_REJECT_ALL
4285 if (wm_prog_data
->barycentric_interp_modes
&
4286 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
4287 cl
.NonPerspectiveBarycentricEnable
= true;
4289 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
4290 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
4292 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
4293 ARRAY_SIZE(cso_rast
->clip
));
4296 if (dirty
& IRIS_DIRTY_RASTER
) {
4297 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4298 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
4299 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
4303 /* XXX: FS program updates needs to flag IRIS_DIRTY_WM */
4304 if (dirty
& IRIS_DIRTY_WM
) {
4305 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4306 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
4308 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
4309 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4311 wm
.BarycentricInterpolationMode
=
4312 wm_prog_data
->barycentric_interp_modes
;
4314 if (wm_prog_data
->early_fragment_tests
)
4315 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
4316 else if (wm_prog_data
->has_side_effects
)
4317 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
4319 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
4322 if (dirty
& IRIS_DIRTY_SBE
) {
4323 iris_emit_sbe(batch
, ice
);
4326 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
4327 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4328 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4329 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
4330 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
4331 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
4332 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4335 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
4336 ARRAY_SIZE(cso_blend
->ps_blend
));
4339 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
4340 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4341 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4343 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
4344 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
4345 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4346 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4348 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
4351 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
4352 uint32_t scissor_offset
=
4353 emit_state(batch
, ice
->state
.dynamic_uploader
,
4354 &ice
->state
.last_res
.scissor
,
4355 ice
->state
.scissors
,
4356 sizeof(struct pipe_scissor_state
) *
4357 ice
->state
.num_viewports
, 32);
4359 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
4360 ptr
.ScissorRectPointer
= scissor_offset
;
4364 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
4365 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4366 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
4368 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
4370 if (cso_fb
->zsbuf
) {
4371 struct iris_resource
*zres
, *sres
;
4372 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
4374 // XXX: might not be writable...
4376 iris_use_pinned_bo(batch
, zres
->bo
, true);
4378 iris_use_pinned_bo(batch
, sres
->bo
, true);
4382 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
4383 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
4384 for (int i
= 0; i
< 32; i
++) {
4385 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
4390 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
4391 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4392 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
4395 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
4396 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
4397 topo
.PrimitiveTopologyType
=
4398 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
4402 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4403 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
4406 /* The VF cache designers cut corners, and made the cache key's
4407 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
4408 * 32 bits of the address. If you have two vertex buffers which get
4409 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
4410 * you can get collisions (even within a single batch).
4412 * So, we need to do a VF cache invalidate if the buffer for a VB
4413 * slot slot changes [48:32] address bits from the previous time.
4415 unsigned flush_flags
= 0;
4417 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4419 const int i
= u_bit_scan64(&bound
);
4420 uint16_t high_bits
= 0;
4422 struct iris_resource
*res
=
4423 (void *) genx
->vertex_buffers
[i
].resource
;
4425 iris_use_pinned_bo(batch
, res
->bo
, false);
4427 high_bits
= res
->bo
->gtt_offset
>> 32ull;
4428 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
4429 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
4430 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
4433 /* If the buffer was written to by streamout, we may need
4434 * to stall so those writes land and become visible to the
4437 * TODO: This may stall more than necessary.
4439 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
4440 flush_flags
|= PIPE_CONTROL_CS_STALL
;
4445 iris_emit_pipe_control_flush(batch
, flush_flags
);
4447 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
4450 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
4451 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
4452 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
4456 bound
= ice
->state
.bound_vertex_buffers
;
4458 const int i
= u_bit_scan64(&bound
);
4459 memcpy(map
, genx
->vertex_buffers
[i
].state
,
4460 sizeof(uint32_t) * vb_dwords
);
4466 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
4467 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4468 const unsigned entries
= MAX2(cso
->count
, 1);
4469 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
4470 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
4471 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
4472 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
4475 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
4476 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
4477 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
4478 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4480 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
4481 if (vs_prog_data
->uses_vertexid
) {
4482 sgv
.VertexIDEnable
= true;
4483 sgv
.VertexIDComponentNumber
= 2;
4484 sgv
.VertexIDElementOffset
= cso
->count
;
4487 if (vs_prog_data
->uses_instanceid
) {
4488 sgv
.InstanceIDEnable
= true;
4489 sgv
.InstanceIDComponentNumber
= 3;
4490 sgv
.InstanceIDElementOffset
= cso
->count
;
4495 if (dirty
& IRIS_DIRTY_VF
) {
4496 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
4497 if (draw
->primitive_restart
) {
4498 vf
.IndexedDrawCutIndexEnable
= true;
4499 vf
.CutIndex
= draw
->restart_index
;
4504 // XXX: Gen8 - PMA fix
4508 iris_upload_render_state(struct iris_context
*ice
,
4509 struct iris_batch
*batch
,
4510 const struct pipe_draw_info
*draw
)
4512 /* Always pin the binder. If we're emitting new binding table pointers,
4513 * we need it. If not, we're probably inheriting old tables via the
4514 * context, and need it anyway. Since true zero-bindings cases are
4515 * practically non-existent, just pin it and avoid last_res tracking.
4517 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
4519 if (!batch
->contains_draw
) {
4520 iris_restore_render_saved_bos(ice
, batch
, draw
);
4521 batch
->contains_draw
= true;
4524 iris_upload_dirty_render_state(ice
, batch
, draw
);
4526 if (draw
->index_size
> 0) {
4529 if (draw
->has_user_indices
) {
4530 u_upload_data(ice
->ctx
.stream_uploader
, 0,
4531 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
4532 &offset
, &ice
->state
.last_res
.index_buffer
);
4534 struct iris_resource
*res
= (void *) draw
->index
.resource
;
4535 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
4537 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
4538 draw
->index
.resource
);
4542 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4544 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
4545 ib
.IndexFormat
= draw
->index_size
>> 1;
4547 ib
.BufferSize
= bo
->size
;
4548 ib
.BufferStartingAddress
= ro_bo(bo
, offset
);
4551 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
4552 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
4553 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
4554 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_VF_CACHE_INVALIDATE
);
4555 ice
->state
.last_index_bo_high_bits
= high_bits
;
4559 #define _3DPRIM_END_OFFSET 0x2420
4560 #define _3DPRIM_START_VERTEX 0x2430
4561 #define _3DPRIM_VERTEX_COUNT 0x2434
4562 #define _3DPRIM_INSTANCE_COUNT 0x2438
4563 #define _3DPRIM_START_INSTANCE 0x243C
4564 #define _3DPRIM_BASE_VERTEX 0x2440
4566 if (draw
->indirect
) {
4567 /* We don't support this MultidrawIndirect. */
4568 assert(!draw
->indirect
->indirect_draw_count
);
4570 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
4573 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4574 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
4575 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
4577 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4578 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
4579 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
4581 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4582 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
4583 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
4585 if (draw
->index_size
) {
4586 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4587 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
4588 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4590 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4591 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4592 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
4595 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4596 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4597 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4599 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
4600 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
4604 } else if (draw
->count_from_stream_output
) {
4605 struct iris_stream_output_target
*so
=
4606 (void *) draw
->count_from_stream_output
;
4608 // XXX: avoid if possible
4609 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
4611 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4612 lrm
.RegisterAddress
= CS_GPR(0);
4614 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
4616 iris_math_div32_gpr0(ice
, batch
, so
->stride
);
4617 _iris_emit_lrr(batch
, _3DPRIM_VERTEX_COUNT
, CS_GPR(0));
4619 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
4620 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
4621 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
4622 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
4625 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
4626 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
4627 prim
.PredicateEnable
=
4628 ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
4630 if (draw
->indirect
|| draw
->count_from_stream_output
) {
4631 prim
.IndirectParameterEnable
= true;
4633 prim
.StartInstanceLocation
= draw
->start_instance
;
4634 prim
.InstanceCount
= draw
->instance_count
;
4635 prim
.VertexCountPerInstance
= draw
->count
;
4637 // XXX: this is probably bonkers.
4638 prim
.StartVertexLocation
= draw
->start
;
4640 if (draw
->index_size
) {
4641 prim
.BaseVertexLocation
+= draw
->index_bias
;
4643 prim
.StartVertexLocation
+= draw
->index_bias
;
4646 //prim.BaseVertexLocation = ...;
4652 iris_upload_compute_state(struct iris_context
*ice
,
4653 struct iris_batch
*batch
,
4654 const struct pipe_grid_info
*grid
)
4656 const uint64_t dirty
= ice
->state
.dirty
;
4657 struct iris_screen
*screen
= batch
->screen
;
4658 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
4659 struct iris_binder
*binder
= &ice
->state
.binder
;
4660 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
4661 struct iris_compiled_shader
*shader
=
4662 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
4663 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4664 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
4666 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->cbuf0_needs_upload
)
4667 upload_uniforms(ice
, MESA_SHADER_COMPUTE
);
4669 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
4670 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
4672 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
4673 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
4675 if (ice
->state
.need_border_colors
)
4676 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4678 if (dirty
& IRIS_DIRTY_CS
) {
4679 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4681 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4682 * the only bits that are changed are scoreboard related: Scoreboard
4683 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
4684 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4687 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
4689 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4690 if (prog_data
->total_scratch
) {
4691 uint32_t scratch_addr
=
4692 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
4693 MESA_SHADER_COMPUTE
);
4694 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
4695 vfe
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
4698 vfe
.MaximumNumberofThreads
=
4699 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
4701 vfe
.ResetGatewayTimer
=
4702 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4705 vfe
.NumberofURBEntries
= 2;
4706 vfe
.URBEntryAllocationSize
= 2;
4708 // XXX: Use Indirect Payload Storage?
4709 vfe
.CURBEAllocationSize
=
4710 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4711 cs_prog_data
->push
.cross_thread
.regs
, 2);
4715 // XXX: hack iris_set_constant_buffers to upload these thread counts
4716 // XXX: along with regular uniforms for compute shaders, somehow.
4718 uint32_t curbe_data_offset
= 0;
4719 // TODO: Move subgroup-id into uniforms ubo so we can push uniforms
4720 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
4721 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
4722 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
4723 struct pipe_resource
*curbe_data_res
= NULL
;
4724 uint32_t *curbe_data_map
=
4725 stream_state(batch
, ice
->state
.dynamic_uploader
, &curbe_data_res
,
4726 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
4727 &curbe_data_offset
);
4728 assert(curbe_data_map
);
4729 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
4730 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
4732 if (dirty
& IRIS_DIRTY_CONSTANTS_CS
) {
4733 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4734 curbe
.CURBETotalDataLength
=
4735 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4736 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
4740 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
4741 IRIS_DIRTY_BINDINGS_CS
|
4742 IRIS_DIRTY_CONSTANTS_CS
|
4744 struct pipe_resource
*desc_res
= NULL
;
4745 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4747 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
4748 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
4749 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
4752 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
4753 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
4755 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4756 load
.InterfaceDescriptorTotalLength
=
4757 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4758 load
.InterfaceDescriptorDataStartAddress
=
4759 emit_state(batch
, ice
->state
.dynamic_uploader
,
4760 &desc_res
, desc
, sizeof(desc
), 32);
4763 pipe_resource_reference(&desc_res
, NULL
);
4766 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
4767 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
4768 uint32_t right_mask
;
4771 right_mask
= ~0u >> (32 - remainder
);
4773 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
4775 #define GPGPU_DISPATCHDIMX 0x2500
4776 #define GPGPU_DISPATCHDIMY 0x2504
4777 #define GPGPU_DISPATCHDIMZ 0x2508
4779 if (grid
->indirect
) {
4780 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
4781 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
4782 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4783 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
4784 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
4786 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4787 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
4788 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
4790 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4791 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
4792 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
4796 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
4797 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
4798 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
4799 ggw
.ThreadDepthCounterMaximum
= 0;
4800 ggw
.ThreadHeightCounterMaximum
= 0;
4801 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
4802 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
4803 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
4804 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
4805 ggw
.RightExecutionMask
= right_mask
;
4806 ggw
.BottomExecutionMask
= 0xffffffff;
4809 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4811 if (!batch
->contains_draw
) {
4812 iris_restore_compute_saved_bos(ice
, batch
, grid
);
4813 batch
->contains_draw
= true;
4818 * State module teardown.
4821 iris_destroy_state(struct iris_context
*ice
)
4823 struct iris_genx_state
*genx
= ice
->state
.genx
;
4825 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
4827 const int i
= u_bit_scan64(&bound_vbs
);
4828 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
4831 // XXX: unreference resources/surfaces.
4832 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
4833 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
4835 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
4837 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
4838 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4839 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
4841 free(ice
->state
.genx
);
4843 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
4845 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
4846 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
4847 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
4848 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
4849 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
4850 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
4853 /* ------------------------------------------------------------------- */
4856 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
4859 _iris_emit_lrr(batch
, dst
, src
);
4863 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
4866 _iris_emit_lrr(batch
, dst
, src
);
4867 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
4871 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
4874 _iris_emit_lri(batch
, reg
, val
);
4878 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
4881 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
4882 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
4886 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
4889 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
4890 struct iris_bo
*bo
, uint32_t offset
)
4892 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4893 lrm
.RegisterAddress
= reg
;
4894 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
4899 * Load a 64-bit value from a buffer into a MMIO register via
4900 * two MI_LOAD_REGISTER_MEM commands.
4903 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
4904 struct iris_bo
*bo
, uint32_t offset
)
4906 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
4907 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
4911 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
4912 struct iris_bo
*bo
, uint32_t offset
,
4915 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
4916 srm
.RegisterAddress
= reg
;
4917 srm
.MemoryAddress
= rw_bo(bo
, offset
);
4918 srm
.PredicateEnable
= predicated
;
4923 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
4924 struct iris_bo
*bo
, uint32_t offset
,
4927 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
4928 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
4932 iris_store_data_imm32(struct iris_batch
*batch
,
4933 struct iris_bo
*bo
, uint32_t offset
,
4936 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
4937 sdi
.Address
= rw_bo(bo
, offset
);
4938 sdi
.ImmediateData
= imm
;
4943 iris_store_data_imm64(struct iris_batch
*batch
,
4944 struct iris_bo
*bo
, uint32_t offset
,
4947 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
4948 * 2 in genxml but it's actually variable length and we need 5 DWords.
4950 void *map
= iris_get_command_space(batch
, 4 * 5);
4951 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
4952 sdi
.DWordLength
= 5 - 2;
4953 sdi
.Address
= rw_bo(bo
, offset
);
4954 sdi
.ImmediateData
= imm
;
4959 iris_copy_mem_mem(struct iris_batch
*batch
,
4960 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
4961 struct iris_bo
*src_bo
, uint32_t src_offset
,
4964 /* MI_COPY_MEM_MEM operates on DWords. */
4965 assert(bytes
% 4 == 0);
4966 assert(dst_offset
% 4 == 0);
4967 assert(src_offset
% 4 == 0);
4969 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
4970 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
4971 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
4972 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
4977 /* ------------------------------------------------------------------- */
4980 flags_to_post_sync_op(uint32_t flags
)
4982 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
4983 return WriteImmediateData
;
4985 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
4986 return WritePSDepthCount
;
4988 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
4989 return WriteTimestamp
;
4995 * Do the given flags have a Post Sync or LRI Post Sync operation?
4997 static enum pipe_control_flags
4998 get_post_sync_flags(enum pipe_control_flags flags
)
5000 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
5001 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5002 PIPE_CONTROL_WRITE_TIMESTAMP
|
5003 PIPE_CONTROL_LRI_POST_SYNC_OP
;
5005 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
5006 * "LRI Post Sync Operation". So more than one bit set would be illegal.
5008 assert(util_bitcount(flags
) <= 1);
5013 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
5016 * Emit a series of PIPE_CONTROL commands, taking into account any
5017 * workarounds necessary to actually accomplish the caller's request.
5019 * Unless otherwise noted, spec quotations in this function come from:
5021 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
5022 * Restrictions for PIPE_CONTROL.
5024 * You should not use this function directly. Use the helpers in
5025 * iris_pipe_control.c instead, which may split the pipe control further.
5028 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
5029 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
5031 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
5032 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
5033 enum pipe_control_flags non_lri_post_sync_flags
=
5034 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
5036 /* Recursive PIPE_CONTROL workarounds --------------------------------
5037 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
5039 * We do these first because we want to look at the original operation,
5040 * rather than any workarounds we set.
5042 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
5043 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
5044 * lists several workarounds:
5046 * "Project: SKL, KBL, BXT
5048 * If the VF Cache Invalidation Enable is set to a 1 in a
5049 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
5050 * sets to 0, with the VF Cache Invalidation Enable set to 0
5051 * needs to be sent prior to the PIPE_CONTROL with VF Cache
5052 * Invalidation Enable set to a 1."
5054 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
5057 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
5058 /* Project: SKL / Argument: LRI Post Sync Operation [23]
5060 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5061 * programmed prior to programming a PIPECONTROL command with "LRI
5062 * Post Sync Operation" in GPGPU mode of operation (i.e when
5063 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
5065 * The same text exists a few rows below for Post Sync Op.
5067 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
5070 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
5072 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
5073 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
5074 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
5076 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
5080 /* "Flush Types" workarounds ---------------------------------------------
5081 * We do these now because they may add post-sync operations or CS stalls.
5084 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
5085 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
5087 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
5088 * 'Write PS Depth Count' or 'Write Timestamp'."
5091 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5092 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5093 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5094 bo
= batch
->screen
->workaround_bo
;
5098 /* #1130 from Gen10 workarounds page:
5100 * "Enable Depth Stall on every Post Sync Op if Render target Cache
5101 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
5102 * board stall if Render target cache flush is enabled."
5104 * Applicable to CNL B0 and C0 steppings only.
5106 * The wording here is unclear, and this workaround doesn't look anything
5107 * like the internal bug report recommendations, but leave it be for now...
5109 if (GEN_GEN
== 10) {
5110 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
5111 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5112 } else if (flags
& non_lri_post_sync_flags
) {
5113 flags
|= PIPE_CONTROL_DEPTH_STALL
;
5117 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
5118 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
5120 * "This bit must be DISABLED for operations other than writing
5123 * This seems like nonsense. An Ivybridge workaround requires us to
5124 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
5125 * operation. Gen8+ requires us to emit depth stalls and depth cache
5126 * flushes together. So, it's hard to imagine this means anything other
5127 * than "we originally intended this to be used for PS_DEPTH_COUNT".
5129 * We ignore the supposed restriction and do nothing.
5133 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5134 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5135 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
5137 * "This bit must be DISABLED for End-of-pipe (Read) fences,
5138 * PS_DEPTH_COUNT or TIMESTAMP queries."
5140 * TODO: Implement end-of-pipe checking.
5142 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5143 PIPE_CONTROL_WRITE_TIMESTAMP
)));
5146 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5147 /* From the PIPE_CONTROL instruction table, bit 1:
5149 * "This bit is ignored if Depth Stall Enable is set.
5150 * Further, the render cache is not flushed even if Write Cache
5151 * Flush Enable bit is set."
5153 * We assert that the caller doesn't do this combination, to try and
5154 * prevent mistakes. It shouldn't hurt the GPU, though.
5156 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
5157 * and "Render Target Flush" combo is explicitly required for BTI
5158 * update workarounds.
5160 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
5161 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
5164 /* PIPE_CONTROL page workarounds ------------------------------------- */
5166 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
5167 /* From the PIPE_CONTROL page itself:
5170 * Restriction: Pipe_control with CS-stall bit set must be issued
5171 * before a pipe-control command that has the State Cache
5172 * Invalidate bit set."
5174 flags
|= PIPE_CONTROL_CS_STALL
;
5177 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
5178 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
5181 * SW must always program Post-Sync Operation to "Write Immediate
5182 * Data" when Flush LLC is set."
5184 * For now, we just require the caller to do it.
5186 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
5189 /* "Post-Sync Operation" workarounds -------------------------------- */
5191 /* Project: All / Argument: Global Snapshot Count Reset [19]
5193 * "This bit must not be exercised on any product.
5194 * Requires stall bit ([20] of DW1) set."
5196 * We don't use this, so we just assert that it isn't used. The
5197 * PIPE_CONTROL instruction page indicates that they intended this
5198 * as a debug feature and don't think it is useful in production,
5199 * but it may actually be usable, should we ever want to.
5201 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
5203 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
5204 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
5205 /* Project: All / Arguments:
5207 * - Generic Media State Clear [16]
5208 * - Indirect State Pointers Disable [16]
5210 * "Requires stall bit ([20] of DW1) set."
5212 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
5213 * State Clear) says:
5215 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5216 * programmed prior to programming a PIPECONTROL command with "Media
5217 * State Clear" set in GPGPU mode of operation"
5219 * This is a subset of the earlier rule, so there's nothing to do.
5221 flags
|= PIPE_CONTROL_CS_STALL
;
5224 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
5225 /* Project: All / Argument: Store Data Index
5227 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5230 * For now, we just assert that the caller does this. We might want to
5231 * automatically add a write to the workaround BO...
5233 assert(non_lri_post_sync_flags
!= 0);
5236 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
5237 /* Project: All / Argument: Sync GFDT
5239 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5240 * than '0' or 0x2520[13] must be set."
5242 * For now, we just assert that the caller does this.
5244 assert(non_lri_post_sync_flags
!= 0);
5247 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
5248 /* Project: IVB+ / Argument: TLB inv
5250 * "Requires stall bit ([20] of DW1) set."
5252 * Also, from the PIPE_CONTROL instruction table:
5255 * Post Sync Operation or CS stall must be set to ensure a TLB
5256 * invalidation occurs. Otherwise no cycle will occur to the TLB
5257 * cache to invalidate."
5259 * This is not a subset of the earlier rule, so there's nothing to do.
5261 flags
|= PIPE_CONTROL_CS_STALL
;
5264 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
5265 /* TODO: The big Skylake GT4 post sync op workaround */
5268 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
5270 if (IS_COMPUTE_PIPELINE(batch
)) {
5271 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
5272 /* Project: SKL+ / Argument: Tex Invalidate
5273 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
5275 flags
|= PIPE_CONTROL_CS_STALL
;
5278 if (GEN_GEN
== 8 && (post_sync_flags
||
5279 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
5280 PIPE_CONTROL_DEPTH_STALL
|
5281 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5282 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5283 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
5284 /* Project: BDW / Arguments:
5286 * - LRI Post Sync Operation [23]
5287 * - Post Sync Op [15:14]
5289 * - Depth Stall [13]
5290 * - Render Target Cache Flush [12]
5291 * - Depth Cache Flush [0]
5292 * - DC Flush Enable [5]
5294 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
5297 flags
|= PIPE_CONTROL_CS_STALL
;
5299 /* Also, from the PIPE_CONTROL instruction table, bit 20:
5302 * This bit must be always set when PIPE_CONTROL command is
5303 * programmed by GPGPU and MEDIA workloads, except for the cases
5304 * when only Read Only Cache Invalidation bits are set (State
5305 * Cache Invalidation Enable, Instruction cache Invalidation
5306 * Enable, Texture Cache Invalidation Enable, Constant Cache
5307 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
5308 * need not implemented when FF_DOP_CG is disable via "Fixed
5309 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
5311 * It sounds like we could avoid CS stalls in some cases, but we
5312 * don't currently bother. This list isn't exactly the list above,
5318 /* "Stall" workarounds ----------------------------------------------
5319 * These have to come after the earlier ones because we may have added
5320 * some additional CS stalls above.
5323 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
5324 /* Project: PRE-SKL, VLV, CHV
5326 * "[All Stepping][All SKUs]:
5328 * One of the following must also be set:
5330 * - Render Target Cache Flush Enable ([12] of DW1)
5331 * - Depth Cache Flush Enable ([0] of DW1)
5332 * - Stall at Pixel Scoreboard ([1] of DW1)
5333 * - Depth Stall ([13] of DW1)
5334 * - Post-Sync Operation ([13] of DW1)
5335 * - DC Flush Enable ([5] of DW1)"
5337 * If we don't already have one of those bits set, we choose to add
5338 * "Stall at Pixel Scoreboard". Some of the other bits require a
5339 * CS stall as a workaround (see above), which would send us into
5340 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
5341 * appears to be safe, so we choose that.
5343 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5344 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5345 PIPE_CONTROL_WRITE_IMMEDIATE
|
5346 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5347 PIPE_CONTROL_WRITE_TIMESTAMP
|
5348 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
5349 PIPE_CONTROL_DEPTH_STALL
|
5350 PIPE_CONTROL_DATA_CACHE_FLUSH
;
5351 if (!(flags
& wa_bits
))
5352 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5355 /* Emit --------------------------------------------------------------- */
5357 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
5358 pc
.LRIPostSyncOperation
= NoLRIOperation
;
5359 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
5360 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
5361 pc
.StoreDataIndex
= 0;
5362 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
5363 pc
.GlobalSnapshotCountReset
=
5364 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
5365 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
5366 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
5367 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5368 pc
.RenderTargetCacheFlushEnable
=
5369 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
5370 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
5371 pc
.StateCacheInvalidationEnable
=
5372 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
5373 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
5374 pc
.ConstantCacheInvalidationEnable
=
5375 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
5376 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
5377 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
5378 pc
.InstructionCacheInvalidateEnable
=
5379 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
5380 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
5381 pc
.IndirectStatePointersDisable
=
5382 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
5383 pc
.TextureCacheInvalidationEnable
=
5384 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
5385 pc
.Address
= rw_bo(bo
, offset
);
5386 pc
.ImmediateData
= imm
;
5391 genX(init_state
)(struct iris_context
*ice
)
5393 struct pipe_context
*ctx
= &ice
->ctx
;
5394 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
5396 ctx
->create_blend_state
= iris_create_blend_state
;
5397 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
5398 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
5399 ctx
->create_sampler_state
= iris_create_sampler_state
;
5400 ctx
->create_sampler_view
= iris_create_sampler_view
;
5401 ctx
->create_surface
= iris_create_surface
;
5402 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
5403 ctx
->bind_blend_state
= iris_bind_blend_state
;
5404 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
5405 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
5406 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
5407 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
5408 ctx
->delete_blend_state
= iris_delete_state
;
5409 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
5410 ctx
->delete_rasterizer_state
= iris_delete_state
;
5411 ctx
->delete_sampler_state
= iris_delete_state
;
5412 ctx
->delete_vertex_elements_state
= iris_delete_state
;
5413 ctx
->set_blend_color
= iris_set_blend_color
;
5414 ctx
->set_clip_state
= iris_set_clip_state
;
5415 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
5416 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
5417 ctx
->set_shader_images
= iris_set_shader_images
;
5418 ctx
->set_sampler_views
= iris_set_sampler_views
;
5419 ctx
->set_tess_state
= iris_set_tess_state
;
5420 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
5421 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
5422 ctx
->set_sample_mask
= iris_set_sample_mask
;
5423 ctx
->set_scissor_states
= iris_set_scissor_states
;
5424 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
5425 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
5426 ctx
->set_viewport_states
= iris_set_viewport_states
;
5427 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
5428 ctx
->surface_destroy
= iris_surface_destroy
;
5429 ctx
->draw_vbo
= iris_draw_vbo
;
5430 ctx
->launch_grid
= iris_launch_grid
;
5431 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
5432 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
5433 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
5435 ice
->vtbl
.destroy_state
= iris_destroy_state
;
5436 ice
->vtbl
.init_render_context
= iris_init_render_context
;
5437 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
5438 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
5439 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
5440 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
5441 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
5442 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
5443 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
5444 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
5445 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
5446 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
5447 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
5448 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
5449 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
5450 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
5451 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
5452 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
5453 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
5454 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
5455 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
5456 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
5457 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
5458 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
5459 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
5460 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
5461 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
5463 ice
->state
.dirty
= ~0ull;
5465 ice
->state
.statistics_counters_enabled
= true;
5467 ice
->state
.sample_mask
= 0xffff;
5468 ice
->state
.num_viewports
= 1;
5469 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
5471 /* Make a 1x1x1 null surface for unbound textures */
5472 void *null_surf_map
=
5473 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
5474 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
5475 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
5476 ice
->state
.unbound_tex
.offset
+=
5477 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
5479 /* Default all scissor rectangles to be empty regions. */
5480 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
5481 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
5482 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,