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15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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20 * DEALINGS IN THE SOFTWARE.
26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_dual_blend.h"
92 #include "util/u_inlines.h"
93 #include "util/format/u_format.h"
94 #include "util/u_framebuffer.h"
95 #include "util/u_transfer.h"
96 #include "util/u_upload_mgr.h"
97 #include "util/u_viewport.h"
98 #include "drm-uapi/i915_drm.h"
100 #include "intel/compiler/brw_compiler.h"
101 #include "intel/common/gen_aux_map.h"
102 #include "intel/common/gen_l3_config.h"
103 #include "intel/common/gen_sample_positions.h"
104 #include "iris_batch.h"
105 #include "iris_context.h"
106 #include "iris_defines.h"
107 #include "iris_pipe.h"
108 #include "iris_resource.h"
110 #include "iris_genx_macros.h"
111 #include "intel/common/gen_guardband.h"
114 * Statically assert that PIPE_* enums match the hardware packets.
115 * (As long as they match, we don't need to translate them.)
117 UNUSED
static void pipe_asserts()
119 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
121 /* pipe_logicop happens to match the hardware. */
122 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
123 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
124 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
125 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
126 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
127 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
128 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
129 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
130 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
131 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
132 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
133 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
134 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
135 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
136 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
137 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
139 /* pipe_blend_func happens to match the hardware. */
140 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
141 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
142 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
143 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
144 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
145 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
146 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
147 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
148 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
149 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
150 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
151 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
152 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
153 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
160 /* pipe_blend_func happens to match the hardware. */
161 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
162 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
163 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
164 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
165 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
167 /* pipe_stencil_op happens to match the hardware. */
168 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
169 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
170 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
171 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
172 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
173 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
174 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
175 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
177 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
178 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
179 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
184 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
186 static const unsigned map
[] = {
187 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
188 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
189 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
190 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
191 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
192 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
193 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
194 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
195 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
196 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
197 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
198 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
199 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
200 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
201 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
204 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
208 translate_compare_func(enum pipe_compare_func pipe_func
)
210 static const unsigned map
[] = {
211 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
212 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
213 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
214 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
215 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
216 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
217 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
218 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
220 return map
[pipe_func
];
224 translate_shadow_func(enum pipe_compare_func pipe_func
)
226 /* Gallium specifies the result of shadow comparisons as:
228 * 1 if ref <op> texel,
233 * 0 if texel <op> ref,
236 * So we need to flip the operator and also negate.
238 static const unsigned map
[] = {
239 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
240 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
241 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
242 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
243 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
244 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
245 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
246 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
248 return map
[pipe_func
];
252 translate_cull_mode(unsigned pipe_face
)
254 static const unsigned map
[4] = {
255 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
256 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
257 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
258 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
260 return map
[pipe_face
];
264 translate_fill_mode(unsigned pipe_polymode
)
266 static const unsigned map
[4] = {
267 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
268 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
269 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
270 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
272 return map
[pipe_polymode
];
276 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
278 static const unsigned map
[] = {
279 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
280 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
281 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
283 return map
[pipe_mip
];
287 translate_wrap(unsigned pipe_wrap
)
289 static const unsigned map
[] = {
290 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
291 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
292 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
293 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
294 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
295 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
297 /* These are unsupported. */
298 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
299 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
301 return map
[pipe_wrap
];
305 * Allocate space for some indirect state.
307 * Return a pointer to the map (to fill it out) and a state ref (for
308 * referring to the state in GPU commands).
311 upload_state(struct u_upload_mgr
*uploader
,
312 struct iris_state_ref
*ref
,
317 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
322 * Stream out temporary/short-lived state.
324 * This allocates space, pins the BO, and includes the BO address in the
325 * returned offset (which works because all state lives in 32-bit memory
329 stream_state(struct iris_batch
*batch
,
330 struct u_upload_mgr
*uploader
,
331 struct pipe_resource
**out_res
,
334 uint32_t *out_offset
)
338 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
340 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
341 iris_use_pinned_bo(batch
, bo
, false);
343 iris_record_state_size(batch
->state_sizes
,
344 bo
->gtt_offset
+ *out_offset
, size
);
346 *out_offset
+= iris_bo_offset_from_base_address(bo
);
352 * stream_state() + memcpy.
355 emit_state(struct iris_batch
*batch
,
356 struct u_upload_mgr
*uploader
,
357 struct pipe_resource
**out_res
,
364 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
367 memcpy(map
, data
, size
);
373 * Did field 'x' change between 'old_cso' and 'new_cso'?
375 * (If so, we may want to set some dirty flags.)
377 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
378 #define cso_changed_memcmp(x) \
379 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
382 flush_before_state_base_change(struct iris_batch
*batch
)
384 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
386 /* Flush before emitting STATE_BASE_ADDRESS.
388 * This isn't documented anywhere in the PRM. However, it seems to be
389 * necessary prior to changing the surface state base adress. We've
390 * seen issues in Vulkan where we get GPU hangs when using multi-level
391 * command buffers which clear depth, reset state base address, and then
394 * Normally, in GL, we would trust the kernel to do sufficient stalls
395 * and flushes prior to executing our batch. However, it doesn't seem
396 * as if the kernel's flushing is always sufficient and we don't want to
399 * We make this an end-of-pipe sync instead of a normal flush because we
400 * do not know the current status of the GPU. On Haswell at least,
401 * having a fast-clear operation in flight at the same time as a normal
402 * rendering operation can cause hangs. Since the kernel's flushing is
403 * insufficient, we need to ensure that any rendering operations from
404 * other processes are definitely complete before we try to do our own
405 * rendering. It's a bit of a big hammer but it appears to work.
407 iris_emit_end_of_pipe_sync(batch
,
408 "change STATE_BASE_ADDRESS (flushes)",
409 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
410 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
411 PIPE_CONTROL_DATA_CACHE_FLUSH
|
412 /* GEN:BUG:1606662791:
414 * Software must program PIPE_CONTROL command
415 * with "HDC Pipeline Flush" prior to
416 * programming of the below two non-pipeline
418 * * STATE_BASE_ADDRESS
419 * * 3DSTATE_BINDING_TABLE_POOL_ALLOC
421 ((GEN_GEN
== 12 && devinfo
->revision
== 0 /* A0 */ ?
422 PIPE_CONTROL_FLUSH_HDC
: 0)));
426 flush_after_state_base_change(struct iris_batch
*batch
)
428 /* After re-setting the surface state base address, we have to do some
429 * cache flusing so that the sampler engine will pick up the new
430 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
431 * Shared Function > 3D Sampler > State > State Caching (page 96):
433 * Coherency with system memory in the state cache, like the texture
434 * cache is handled partially by software. It is expected that the
435 * command stream or shader will issue Cache Flush operation or
436 * Cache_Flush sampler message to ensure that the L1 cache remains
437 * coherent with system memory.
441 * Whenever the value of the Dynamic_State_Base_Addr,
442 * Surface_State_Base_Addr are altered, the L1 state cache must be
443 * invalidated to ensure the new surface or sampler state is fetched
444 * from system memory.
446 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
447 * which, according the PIPE_CONTROL instruction documentation in the
450 * Setting this bit is independent of any other bit in this packet.
451 * This bit controls the invalidation of the L1 and L2 state caches
452 * at the top of the pipe i.e. at the parsing time.
454 * Unfortunately, experimentation seems to indicate that state cache
455 * invalidation through a PIPE_CONTROL does nothing whatsoever in
456 * regards to surface state and binding tables. In stead, it seems that
457 * invalidating the texture cache is what is actually needed.
459 * XXX: As far as we have been able to determine through
460 * experimentation, shows that flush the texture cache appears to be
461 * sufficient. The theory here is that all of the sampling/rendering
462 * units cache the binding table in the texture cache. However, we have
463 * yet to be able to actually confirm this.
465 iris_emit_end_of_pipe_sync(batch
,
466 "change STATE_BASE_ADDRESS (invalidates)",
467 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
468 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
469 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
473 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
475 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
476 lri
.RegisterOffset
= reg
;
480 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
483 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
485 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
486 lrr
.SourceRegisterAddress
= src
;
487 lrr
.DestinationRegisterAddress
= dst
;
492 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
495 _iris_emit_lrr(batch
, dst
, src
);
499 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
502 _iris_emit_lrr(batch
, dst
, src
);
503 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
507 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
510 _iris_emit_lri(batch
, reg
, val
);
514 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
517 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
518 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
522 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
525 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
526 struct iris_bo
*bo
, uint32_t offset
)
528 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
529 lrm
.RegisterAddress
= reg
;
530 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
535 * Load a 64-bit value from a buffer into a MMIO register via
536 * two MI_LOAD_REGISTER_MEM commands.
539 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
540 struct iris_bo
*bo
, uint32_t offset
)
542 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
543 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
547 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
548 struct iris_bo
*bo
, uint32_t offset
,
551 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
552 srm
.RegisterAddress
= reg
;
553 srm
.MemoryAddress
= rw_bo(bo
, offset
);
554 srm
.PredicateEnable
= predicated
;
559 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
560 struct iris_bo
*bo
, uint32_t offset
,
563 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
564 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
568 iris_store_data_imm32(struct iris_batch
*batch
,
569 struct iris_bo
*bo
, uint32_t offset
,
572 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
573 sdi
.Address
= rw_bo(bo
, offset
);
574 sdi
.ImmediateData
= imm
;
579 iris_store_data_imm64(struct iris_batch
*batch
,
580 struct iris_bo
*bo
, uint32_t offset
,
583 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
584 * 2 in genxml but it's actually variable length and we need 5 DWords.
586 void *map
= iris_get_command_space(batch
, 4 * 5);
587 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
588 sdi
.DWordLength
= 5 - 2;
589 sdi
.Address
= rw_bo(bo
, offset
);
590 sdi
.ImmediateData
= imm
;
595 iris_copy_mem_mem(struct iris_batch
*batch
,
596 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
597 struct iris_bo
*src_bo
, uint32_t src_offset
,
600 /* MI_COPY_MEM_MEM operates on DWords. */
601 assert(bytes
% 4 == 0);
602 assert(dst_offset
% 4 == 0);
603 assert(src_offset
% 4 == 0);
605 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
606 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
607 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
608 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
614 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
616 #if GEN_GEN >= 8 && GEN_GEN < 10
617 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
619 * Software must clear the COLOR_CALC_STATE Valid field in
620 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
621 * with Pipeline Select set to GPGPU.
623 * The internal hardware docs recommend the same workaround for Gen9
626 if (pipeline
== GPGPU
)
627 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
631 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
632 * PIPELINE_SELECT [DevBWR+]":
636 * Software must ensure all the write caches are flushed through a
637 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
638 * command to invalidate read only caches prior to programming
639 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
641 iris_emit_pipe_control_flush(batch
,
642 "workaround: PIPELINE_SELECT flushes (1/2)",
643 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
644 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
645 PIPE_CONTROL_DATA_CACHE_FLUSH
|
646 PIPE_CONTROL_CS_STALL
);
648 iris_emit_pipe_control_flush(batch
,
649 "workaround: PIPELINE_SELECT flushes (2/2)",
650 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
651 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
652 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
653 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
655 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
659 sel
.PipelineSelection
= pipeline
;
664 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
669 * "This chicken bit works around a hardware issue with barrier
670 * logic encountered when switching between GPGPU and 3D pipelines.
671 * To workaround the issue, this mode bit should be set after a
672 * pipeline is selected."
675 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
676 reg
.GLKBarrierMode
= value
;
677 reg
.GLKBarrierModeMask
= 1;
679 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
684 init_state_base_address(struct iris_batch
*batch
)
686 uint32_t mocs
= batch
->screen
->isl_dev
.mocs
.internal
;
687 flush_before_state_base_change(batch
);
689 /* We program most base addresses once at context initialization time.
690 * Each base address points at a 4GB memory zone, and never needs to
691 * change. See iris_bufmgr.h for a description of the memory zones.
693 * The one exception is Surface State Base Address, which needs to be
694 * updated occasionally. See iris_binder.c for the details there.
696 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
697 sba
.GeneralStateMOCS
= mocs
;
698 sba
.StatelessDataPortAccessMOCS
= mocs
;
699 sba
.DynamicStateMOCS
= mocs
;
700 sba
.IndirectObjectMOCS
= mocs
;
701 sba
.InstructionMOCS
= mocs
;
702 sba
.SurfaceStateMOCS
= mocs
;
704 sba
.GeneralStateBaseAddressModifyEnable
= true;
705 sba
.DynamicStateBaseAddressModifyEnable
= true;
706 sba
.IndirectObjectBaseAddressModifyEnable
= true;
707 sba
.InstructionBaseAddressModifyEnable
= true;
708 sba
.GeneralStateBufferSizeModifyEnable
= true;
709 sba
.DynamicStateBufferSizeModifyEnable
= true;
711 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
712 sba
.BindlessSurfaceStateMOCS
= mocs
;
714 sba
.IndirectObjectBufferSizeModifyEnable
= true;
715 sba
.InstructionBuffersizeModifyEnable
= true;
717 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
718 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
720 sba
.GeneralStateBufferSize
= 0xfffff;
721 sba
.IndirectObjectBufferSize
= 0xfffff;
722 sba
.InstructionBufferSize
= 0xfffff;
723 sba
.DynamicStateBufferSize
= 0xfffff;
726 flush_after_state_base_change(batch
);
730 iris_emit_l3_config(struct iris_batch
*batch
,
731 const struct gen_l3_config
*cfg
)
736 #define L3_ALLOCATION_REG GENX(L3ALLOC)
737 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
739 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
740 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
743 iris_pack_state(L3_ALLOCATION_REG
, ®_val
, reg
) {
745 reg
.SLMEnable
= cfg
->n
[GEN_L3P_SLM
] > 0;
748 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
749 * in L3CNTLREG register. The default setting of the bit is not the
750 * desirable behavior.
752 reg
.ErrorDetectionBehaviorControl
= true;
753 reg
.UseFullWays
= true;
755 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
756 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
757 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
758 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
760 _iris_emit_lri(batch
, L3_ALLOCATION_REG_num
, reg_val
);
765 iris_enable_obj_preemption(struct iris_batch
*batch
, bool enable
)
769 /* A fixed function pipe flush is required before modifying this field */
770 iris_emit_end_of_pipe_sync(batch
, enable
? "enable preemption"
771 : "disable preemption",
772 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
774 /* enable object level preemption */
775 iris_pack_state(GENX(CS_CHICKEN1
), ®_val
, reg
) {
776 reg
.ReplayMode
= enable
;
777 reg
.ReplayModeMask
= true;
779 iris_emit_lri(batch
, CS_CHICKEN1
, reg_val
);
785 iris_upload_slice_hashing_state(struct iris_batch
*batch
)
787 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
788 int subslices_delta
=
789 devinfo
->ppipe_subslices
[0] - devinfo
->ppipe_subslices
[1];
790 if (subslices_delta
== 0)
793 struct iris_context
*ice
= NULL
;
794 ice
= container_of(batch
, ice
, batches
[IRIS_BATCH_RENDER
]);
795 assert(&ice
->batches
[IRIS_BATCH_RENDER
] == batch
);
797 unsigned size
= GENX(SLICE_HASH_TABLE_length
) * 4;
798 uint32_t hash_address
;
799 struct pipe_resource
*tmp
= NULL
;
801 stream_state(batch
, ice
->state
.dynamic_uploader
, &tmp
,
802 size
, 64, &hash_address
);
803 pipe_resource_reference(&tmp
, NULL
);
805 struct GENX(SLICE_HASH_TABLE
) table0
= {
807 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
808 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
809 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
810 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
811 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
812 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
813 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
814 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
815 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
816 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
817 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
818 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
819 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
820 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
821 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
822 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }
826 struct GENX(SLICE_HASH_TABLE
) table1
= {
828 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
829 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
830 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
831 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
832 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
833 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
834 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
835 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
836 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
837 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
838 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
839 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
840 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
841 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
842 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
843 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }
847 const struct GENX(SLICE_HASH_TABLE
) *table
=
848 subslices_delta
< 0 ? &table0
: &table1
;
849 GENX(SLICE_HASH_TABLE_pack
)(NULL
, map
, table
);
851 iris_emit_cmd(batch
, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS
), ptr
) {
852 ptr
.SliceHashStatePointerValid
= true;
853 ptr
.SliceHashTableStatePointer
= hash_address
;
856 iris_emit_cmd(batch
, GENX(3DSTATE_3D_MODE
), mode
) {
857 mode
.SliceHashingTableEnable
= true;
863 iris_alloc_push_constants(struct iris_batch
*batch
)
865 /* For now, we set a static partitioning of the push constant area,
866 * assuming that all stages could be in use.
868 * TODO: Try lazily allocating the HS/DS/GS sections as needed, and
869 * see if that improves performance by offering more space to
870 * the VS/FS when those aren't in use. Also, try dynamically
871 * enabling/disabling it like i965 does. This would be more
872 * stalls and may not actually help; we don't know yet.
874 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
875 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
876 alloc
._3DCommandSubOpcode
= 18 + i
;
877 alloc
.ConstantBufferOffset
= 6 * i
;
878 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
885 init_aux_map_state(struct iris_batch
*batch
);
889 * Upload the initial GPU state for a render context.
891 * This sets some invariant state that needs to be programmed a particular
892 * way, but we never actually change.
895 iris_init_render_context(struct iris_batch
*batch
)
897 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
900 emit_pipeline_select(batch
, _3D
);
902 iris_emit_l3_config(batch
, batch
->screen
->l3_config_3d
);
904 init_state_base_address(batch
);
907 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
908 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
909 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
911 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
913 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
914 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
915 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
917 iris_emit_lri(batch
, INSTPM
, reg_val
);
921 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
922 reg
.FloatBlendOptimizationEnable
= true;
923 reg
.FloatBlendOptimizationEnableMask
= true;
924 reg
.PartialResolveDisableInVC
= true;
925 reg
.PartialResolveDisableInVCMask
= true;
927 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
929 if (devinfo
->is_geminilake
)
930 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
934 iris_pack_state(GENX(TCCNTLREG
), ®_val
, reg
) {
935 reg
.L3DataPartialWriteMergingEnable
= true;
936 reg
.ColorZPartialWriteMergingEnable
= true;
937 reg
.URBPartialWriteMergingEnable
= true;
938 reg
.TCDisable
= true;
940 iris_emit_lri(batch
, TCCNTLREG
, reg_val
);
942 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
943 reg
.HeaderlessMessageforPreemptableContexts
= 1;
944 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
946 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
948 /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
949 iris_pack_state(GENX(HALF_SLICE_CHICKEN7
), ®_val
, reg
) {
950 reg
.EnabledTexelOffsetPrecisionFix
= 1;
951 reg
.EnabledTexelOffsetPrecisionFixMask
= 1;
953 iris_emit_lri(batch
, HALF_SLICE_CHICKEN7
, reg_val
);
955 /* Hardware specification recommends disabling repacking for the
956 * compatibility with decompression mechanism in display controller.
958 if (devinfo
->disable_ccs_repack
) {
959 iris_pack_state(GENX(CACHE_MODE_0
), ®_val
, reg
) {
960 reg
.DisableRepackingforCompression
= true;
961 reg
.DisableRepackingforCompressionMask
= true;
963 iris_emit_lri(batch
, CACHE_MODE_0
, reg_val
);
966 iris_upload_slice_hashing_state(batch
);
969 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
970 * changing it dynamically. We set it to the maximum size here, and
971 * instead include the render target dimensions in the viewport, so
972 * viewport extents clipping takes care of pruning stray geometry.
974 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
975 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
976 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
979 /* Set the initial MSAA sample positions. */
980 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
981 GEN_SAMPLE_POS_1X(pat
._1xSample
);
982 GEN_SAMPLE_POS_2X(pat
._2xSample
);
983 GEN_SAMPLE_POS_4X(pat
._4xSample
);
984 GEN_SAMPLE_POS_8X(pat
._8xSample
);
986 GEN_SAMPLE_POS_16X(pat
._16xSample
);
990 /* Use the legacy AA line coverage computation. */
991 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
993 /* Disable chromakeying (it's for media) */
994 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
996 /* We want regular rendering, not special HiZ operations. */
997 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
999 /* No polygon stippling offsets are necessary. */
1000 /* TODO: may need to set an offset for origin-UL framebuffers */
1001 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
1003 iris_alloc_push_constants(batch
);
1006 init_aux_map_state(batch
);
1011 iris_init_compute_context(struct iris_batch
*batch
)
1013 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
1015 /* GEN:BUG:1607854226:
1017 * Start with pipeline in 3D mode to set the STATE_BASE_ADDRESS.
1020 emit_pipeline_select(batch
, _3D
);
1022 emit_pipeline_select(batch
, GPGPU
);
1025 iris_emit_l3_config(batch
, batch
->screen
->l3_config_cs
);
1027 init_state_base_address(batch
);
1030 emit_pipeline_select(batch
, GPGPU
);
1034 if (devinfo
->is_geminilake
)
1035 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
1039 init_aux_map_state(batch
);
1044 struct iris_vertex_buffer_state
{
1045 /** The VERTEX_BUFFER_STATE hardware structure. */
1046 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
1048 /** The resource to source vertex data from. */
1049 struct pipe_resource
*resource
;
1054 struct iris_depth_buffer_state
{
1055 /* Depth/HiZ/Stencil related hardware packets. */
1056 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
1057 GENX(3DSTATE_STENCIL_BUFFER_length
) +
1058 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
1059 GENX(3DSTATE_CLEAR_PARAMS_length
) +
1060 GENX(MI_LOAD_REGISTER_IMM_length
) * 2];
1064 * Generation-specific context state (ice->state.genx->...).
1066 * Most state can go in iris_context directly, but these encode hardware
1067 * packets which vary by generation.
1069 struct iris_genx_state
{
1070 struct iris_vertex_buffer_state vertex_buffers
[33];
1071 uint32_t last_index_buffer
[GENX(3DSTATE_INDEX_BUFFER_length
)];
1073 struct iris_depth_buffer_state depth_buffer
;
1075 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
1078 bool pma_fix_enabled
;
1082 /* Is object level preemption enabled? */
1083 bool object_preemption
;
1088 struct brw_image_param image_param
[PIPE_MAX_SHADER_IMAGES
];
1090 } shaders
[MESA_SHADER_STAGES
];
1094 * The pipe->set_blend_color() driver hook.
1096 * This corresponds to our COLOR_CALC_STATE.
1099 iris_set_blend_color(struct pipe_context
*ctx
,
1100 const struct pipe_blend_color
*state
)
1102 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1104 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
1105 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
1106 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1110 * Gallium CSO for blend state (see pipe_blend_state).
1112 struct iris_blend_state
{
1113 /** Partial 3DSTATE_PS_BLEND */
1114 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
1116 /** Partial BLEND_STATE */
1117 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
1118 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
1120 bool alpha_to_coverage
; /* for shader key */
1122 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
1123 uint8_t blend_enables
;
1125 /** Bitfield of whether color writes are enabled for RT[i] */
1126 uint8_t color_write_enables
;
1128 /** Does RT[0] use dual color blending? */
1129 bool dual_color_blending
;
1132 static enum pipe_blendfactor
1133 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
1136 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
1137 return PIPE_BLENDFACTOR_ONE
;
1139 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
1140 return PIPE_BLENDFACTOR_ZERO
;
1147 * The pipe->create_blend_state() driver hook.
1149 * Translates a pipe_blend_state into iris_blend_state.
1152 iris_create_blend_state(struct pipe_context
*ctx
,
1153 const struct pipe_blend_state
*state
)
1155 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
1156 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
1158 cso
->blend_enables
= 0;
1159 cso
->color_write_enables
= 0;
1160 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
1162 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
1164 bool indep_alpha_blend
= false;
1166 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
1167 const struct pipe_rt_blend_state
*rt
=
1168 &state
->rt
[state
->independent_blend_enable
? i
: 0];
1170 enum pipe_blendfactor src_rgb
=
1171 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
1172 enum pipe_blendfactor src_alpha
=
1173 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
1174 enum pipe_blendfactor dst_rgb
=
1175 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
1176 enum pipe_blendfactor dst_alpha
=
1177 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
1179 if (rt
->rgb_func
!= rt
->alpha_func
||
1180 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
1181 indep_alpha_blend
= true;
1183 if (rt
->blend_enable
)
1184 cso
->blend_enables
|= 1u << i
;
1187 cso
->color_write_enables
|= 1u << i
;
1189 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
1190 be
.LogicOpEnable
= state
->logicop_enable
;
1191 be
.LogicOpFunction
= state
->logicop_func
;
1193 be
.PreBlendSourceOnlyClampEnable
= false;
1194 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
1195 be
.PreBlendColorClampEnable
= true;
1196 be
.PostBlendColorClampEnable
= true;
1198 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
1200 be
.ColorBlendFunction
= rt
->rgb_func
;
1201 be
.AlphaBlendFunction
= rt
->alpha_func
;
1202 be
.SourceBlendFactor
= src_rgb
;
1203 be
.SourceAlphaBlendFactor
= src_alpha
;
1204 be
.DestinationBlendFactor
= dst_rgb
;
1205 be
.DestinationAlphaBlendFactor
= dst_alpha
;
1207 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
1208 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
1209 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
1210 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
1212 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
1215 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
1216 /* pb.HasWriteableRT is filled in at draw time.
1217 * pb.AlphaTestEnable is filled in at draw time.
1219 * pb.ColorBufferBlendEnable is filled in at draw time so we can avoid
1220 * setting it when dual color blending without an appropriate shader.
1223 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1224 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1226 pb
.SourceBlendFactor
=
1227 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
1228 pb
.SourceAlphaBlendFactor
=
1229 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
1230 pb
.DestinationBlendFactor
=
1231 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
1232 pb
.DestinationAlphaBlendFactor
=
1233 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
1236 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
1237 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1238 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1239 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
1240 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
1241 bs
.ColorDitherEnable
= state
->dither
;
1242 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
1245 cso
->dual_color_blending
= util_blend_state_is_dual(state
, 0);
1251 * The pipe->bind_blend_state() driver hook.
1253 * Bind a blending CSO and flag related dirty bits.
1256 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
1258 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1259 struct iris_blend_state
*cso
= state
;
1261 ice
->state
.cso_blend
= cso
;
1262 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
1264 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1265 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1266 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1267 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
1270 ice
->state
.dirty
|= IRIS_DIRTY_PMA_FIX
;
1274 * Return true if the FS writes to any color outputs which are not disabled
1275 * via color masking.
1278 has_writeable_rt(const struct iris_blend_state
*cso_blend
,
1279 const struct shader_info
*fs_info
)
1284 unsigned rt_outputs
= fs_info
->outputs_written
>> FRAG_RESULT_DATA0
;
1286 if (fs_info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
))
1287 rt_outputs
= (1 << BRW_MAX_DRAW_BUFFERS
) - 1;
1289 return cso_blend
->color_write_enables
& rt_outputs
;
1293 * Gallium CSO for depth, stencil, and alpha testing state.
1295 struct iris_depth_stencil_alpha_state
{
1296 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
1297 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1300 uint32_t depth_bounds
[GENX(3DSTATE_DEPTH_BOUNDS_length
)];
1303 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
1304 struct pipe_alpha_state alpha
;
1306 /** Outbound to resolve and cache set tracking. */
1307 bool depth_writes_enabled
;
1308 bool stencil_writes_enabled
;
1310 /** Outbound to Gen8-9 PMA stall equations */
1311 bool depth_test_enabled
;
1315 * The pipe->create_depth_stencil_alpha_state() driver hook.
1317 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
1318 * testing state since we need pieces of it in a variety of places.
1321 iris_create_zsa_state(struct pipe_context
*ctx
,
1322 const struct pipe_depth_stencil_alpha_state
*state
)
1324 struct iris_depth_stencil_alpha_state
*cso
=
1325 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
1327 bool two_sided_stencil
= state
->stencil
[1].enabled
;
1329 cso
->alpha
= state
->alpha
;
1330 cso
->depth_writes_enabled
= state
->depth
.writemask
;
1331 cso
->depth_test_enabled
= state
->depth
.enabled
;
1332 cso
->stencil_writes_enabled
=
1333 state
->stencil
[0].writemask
!= 0 ||
1334 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1336 /* The state tracker needs to optimize away EQUAL writes for us. */
1337 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
1339 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
1340 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1341 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1342 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1343 wmds
.StencilTestFunction
=
1344 translate_compare_func(state
->stencil
[0].func
);
1345 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1346 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1347 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1348 wmds
.BackfaceStencilTestFunction
=
1349 translate_compare_func(state
->stencil
[1].func
);
1350 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1351 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1352 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1353 wmds
.StencilBufferWriteEnable
=
1354 state
->stencil
[0].writemask
!= 0 ||
1355 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1356 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1357 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1358 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1359 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1360 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1361 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1362 /* wmds.[Backface]StencilReferenceValue are merged later */
1366 iris_pack_command(GENX(3DSTATE_DEPTH_BOUNDS
), cso
->depth_bounds
, depth_bounds
) {
1367 depth_bounds
.DepthBoundsTestValueModifyDisable
= false;
1368 depth_bounds
.DepthBoundsTestEnableModifyDisable
= false;
1369 depth_bounds
.DepthBoundsTestEnable
= state
->depth
.bounds_test
;
1370 depth_bounds
.DepthBoundsTestMinValue
= state
->depth
.bounds_min
;
1371 depth_bounds
.DepthBoundsTestMaxValue
= state
->depth
.bounds_max
;
1379 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1381 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1384 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1386 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1387 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1388 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1391 if (cso_changed(alpha
.ref_value
))
1392 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1394 if (cso_changed(alpha
.enabled
))
1395 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1397 if (cso_changed(alpha
.func
))
1398 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1400 if (cso_changed(depth_writes_enabled
))
1401 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1403 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1404 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1407 if (cso_changed(depth_bounds
))
1408 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BOUNDS
;
1412 ice
->state
.cso_zsa
= new_cso
;
1413 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1414 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1415 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1418 ice
->state
.dirty
|= IRIS_DIRTY_PMA_FIX
;
1423 want_pma_fix(struct iris_context
*ice
)
1425 UNUSED
struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1426 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1427 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
1428 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
1429 const struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
1430 const struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
1431 const struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
1433 /* In very specific combinations of state, we can instruct Gen8-9 hardware
1434 * to avoid stalling at the pixel mask array. The state equations are
1435 * documented in these places:
1437 * - Gen8 Depth PMA Fix: CACHE_MODE_1::NP_PMA_FIX_ENABLE
1438 * - Gen9 Stencil PMA Fix: CACHE_MODE_0::STC PMA Optimization Enable
1440 * Both equations share some common elements:
1443 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
1444 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
1445 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
1446 * 3DSTATE_WM_HZ_OP::StencilBufferClear) &&
1449 * 3DSTATE_WM::ForceKillPix != ForceOff &&
1450 * (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
1451 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
1452 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
1453 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
1454 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable)
1456 * (Technically the stencil PMA treats ForceKillPix differently,
1457 * but I think this is a documentation oversight, and we don't
1458 * ever use it in this way, so it doesn't matter).
1461 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
1462 * 3DSTATE_RASTER::ForceSampleCount == NUMRASTSAMPLES_0 &&
1463 * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
1464 * 3DSTATE_DEPTH_BUFFER::HIZ Enable &&
1465 * 3DSTATE_WM::EDSC_Mode != EDSC_PREPS &&
1466 * 3DSTATE_PS_EXTRA::PixelShaderValid &&
1469 * These are always true:
1471 * 3DSTATE_RASTER::ForceSampleCount == NUMRASTSAMPLES_0
1472 * 3DSTATE_PS_EXTRA::PixelShaderValid
1474 * Also, we never use the normal drawing path for HiZ ops; these are true:
1476 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
1477 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
1478 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
1479 * 3DSTATE_WM_HZ_OP::StencilBufferClear)
1481 * This happens sometimes:
1483 * 3DSTATE_WM::ForceThreadDispatch != 1
1485 * However, we choose to ignore it as it either agrees with the signal
1486 * (dispatch was already enabled, so nothing out of the ordinary), or
1487 * there are no framebuffer attachments (so no depth or HiZ anyway,
1488 * meaning the PMA signal will already be disabled).
1494 struct iris_resource
*zres
, *sres
;
1495 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
, &zres
, &sres
);
1497 /* 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
1498 * 3DSTATE_DEPTH_BUFFER::HIZ Enable &&
1500 if (!zres
|| !iris_resource_level_has_hiz(zres
, cso_fb
->zsbuf
->u
.tex
.level
))
1503 /* 3DSTATE_WM::EDSC_Mode != EDSC_PREPS */
1504 if (wm_prog_data
->early_fragment_tests
)
1507 /* 3DSTATE_WM::ForceKillPix != ForceOff &&
1508 * (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
1509 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
1510 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
1511 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
1512 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable)
1514 bool killpixels
= wm_prog_data
->uses_kill
|| wm_prog_data
->uses_omask
||
1515 cso_blend
->alpha_to_coverage
|| cso_zsa
->alpha
.enabled
;
1517 /* The Gen8 depth PMA equation becomes:
1520 * 3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
1521 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE
1524 * 3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
1525 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
1526 * 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE
1530 * 3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable &&
1531 * ((killpixels && (depth_writes || stencil_writes)) ||
1532 * 3DSTATE_PS_EXTRA::PixelShaderComputedDepthMode != PSCDEPTH_OFF)
1535 if (!cso_zsa
->depth_test_enabled
)
1538 return wm_prog_data
->computed_depth_mode
!= PSCDEPTH_OFF
||
1539 (killpixels
&& (cso_zsa
->depth_writes_enabled
||
1540 (sres
&& cso_zsa
->stencil_writes_enabled
)));
1545 genX(update_pma_fix
)(struct iris_context
*ice
,
1546 struct iris_batch
*batch
,
1550 struct iris_genx_state
*genx
= ice
->state
.genx
;
1552 if (genx
->pma_fix_enabled
== enable
)
1555 genx
->pma_fix_enabled
= enable
;
1557 /* According to the Broadwell PIPE_CONTROL documentation, software should
1558 * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
1559 * prior to the LRI. If stencil buffer writes are enabled, then a Render * Cache Flush is also necessary.
1561 * The Gen9 docs say to use a depth stall rather than a command streamer
1562 * stall. However, the hardware seems to violently disagree. A full
1563 * command streamer stall seems to be needed in both cases.
1565 iris_emit_pipe_control_flush(batch
, "PMA fix change (1/2)",
1566 PIPE_CONTROL_CS_STALL
|
1567 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1568 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1571 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
1572 reg
.NPPMAFixEnable
= enable
;
1573 reg
.NPEarlyZFailsDisable
= enable
;
1574 reg
.NPPMAFixEnableMask
= true;
1575 reg
.NPEarlyZFailsDisableMask
= true;
1577 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
1579 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
1580 * Flush bits is often necessary. We do it regardless because it's easier.
1581 * The render cache flush is also necessary if stencil writes are enabled.
1583 * Again, the Gen9 docs give a different set of flushes but the Broadwell
1584 * flushes seem to work just as well.
1586 iris_emit_pipe_control_flush(batch
, "PMA fix change (1/2)",
1587 PIPE_CONTROL_DEPTH_STALL
|
1588 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1589 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1594 * Gallium CSO for rasterizer state.
1596 struct iris_rasterizer_state
{
1597 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1598 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1599 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1600 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1601 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1603 uint8_t num_clip_plane_consts
;
1604 bool clip_halfz
; /* for CC_VIEWPORT */
1605 bool depth_clip_near
; /* for CC_VIEWPORT */
1606 bool depth_clip_far
; /* for CC_VIEWPORT */
1607 bool flatshade
; /* for shader state */
1608 bool flatshade_first
; /* for stream output */
1609 bool clamp_fragment_color
; /* for shader state */
1610 bool light_twoside
; /* for shader state */
1611 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1612 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1613 bool line_stipple_enable
;
1614 bool poly_stipple_enable
;
1616 bool force_persample_interp
;
1617 bool conservative_rasterization
;
1618 bool fill_mode_point_or_line
;
1619 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1620 uint16_t sprite_coord_enable
;
1624 get_line_width(const struct pipe_rasterizer_state
*state
)
1626 float line_width
= state
->line_width
;
1628 /* From the OpenGL 4.4 spec:
1630 * "The actual width of non-antialiased lines is determined by rounding
1631 * the supplied width to the nearest integer, then clamping it to the
1632 * implementation-dependent maximum non-antialiased line width."
1634 if (!state
->multisample
&& !state
->line_smooth
)
1635 line_width
= roundf(state
->line_width
);
1637 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1638 /* For 1 pixel line thickness or less, the general anti-aliasing
1639 * algorithm gives up, and a garbage line is generated. Setting a
1640 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1641 * (one-pixel-wide), non-antialiased lines.
1643 * Lines rendered with zero Line Width are rasterized using the
1644 * "Grid Intersection Quantization" rules as specified by the
1645 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1654 * The pipe->create_rasterizer_state() driver hook.
1657 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1658 const struct pipe_rasterizer_state
*state
)
1660 struct iris_rasterizer_state
*cso
=
1661 malloc(sizeof(struct iris_rasterizer_state
));
1663 cso
->multisample
= state
->multisample
;
1664 cso
->force_persample_interp
= state
->force_persample_interp
;
1665 cso
->clip_halfz
= state
->clip_halfz
;
1666 cso
->depth_clip_near
= state
->depth_clip_near
;
1667 cso
->depth_clip_far
= state
->depth_clip_far
;
1668 cso
->flatshade
= state
->flatshade
;
1669 cso
->flatshade_first
= state
->flatshade_first
;
1670 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1671 cso
->light_twoside
= state
->light_twoside
;
1672 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1673 cso
->half_pixel_center
= state
->half_pixel_center
;
1674 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1675 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1676 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1677 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1678 cso
->conservative_rasterization
=
1679 state
->conservative_raster_mode
== PIPE_CONSERVATIVE_RASTER_POST_SNAP
;
1681 cso
->fill_mode_point_or_line
=
1682 state
->fill_front
== PIPE_POLYGON_MODE_LINE
||
1683 state
->fill_front
== PIPE_POLYGON_MODE_POINT
||
1684 state
->fill_back
== PIPE_POLYGON_MODE_LINE
||
1685 state
->fill_back
== PIPE_POLYGON_MODE_POINT
;
1687 if (state
->clip_plane_enable
!= 0)
1688 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1690 cso
->num_clip_plane_consts
= 0;
1692 float line_width
= get_line_width(state
);
1694 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1695 sf
.StatisticsEnable
= true;
1696 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1697 sf
.LineEndCapAntialiasingRegionWidth
=
1698 state
->line_smooth
? _10pixels
: _05pixels
;
1699 sf
.LastPixelEnable
= state
->line_last_pixel
;
1700 sf
.LineWidth
= line_width
;
1701 sf
.SmoothPointEnable
= (state
->point_smooth
|| state
->multisample
) &&
1702 !state
->point_quad_rasterization
;
1703 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1704 sf
.PointWidth
= state
->point_size
;
1706 if (state
->flatshade_first
) {
1707 sf
.TriangleFanProvokingVertexSelect
= 1;
1709 sf
.TriangleStripListProvokingVertexSelect
= 2;
1710 sf
.TriangleFanProvokingVertexSelect
= 2;
1711 sf
.LineStripListProvokingVertexSelect
= 1;
1715 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1716 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1717 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1718 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1719 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1720 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1721 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1722 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1723 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1724 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1725 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1726 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1727 rr
.SmoothPointEnable
= state
->point_smooth
;
1728 rr
.AntialiasingEnable
= state
->line_smooth
;
1729 rr
.ScissorRectangleEnable
= state
->scissor
;
1731 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1732 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1733 rr
.ConservativeRasterizationEnable
=
1734 cso
->conservative_rasterization
;
1736 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1740 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1741 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1742 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1744 cl
.EarlyCullEnable
= true;
1745 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1746 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1747 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1748 cl
.GuardbandClipTestEnable
= true;
1749 cl
.ClipEnable
= true;
1750 cl
.MinimumPointWidth
= 0.125;
1751 cl
.MaximumPointWidth
= 255.875;
1753 if (state
->flatshade_first
) {
1754 cl
.TriangleFanProvokingVertexSelect
= 1;
1756 cl
.TriangleStripListProvokingVertexSelect
= 2;
1757 cl
.TriangleFanProvokingVertexSelect
= 2;
1758 cl
.LineStripListProvokingVertexSelect
= 1;
1762 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1763 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1764 * filled in at draw time from the FS program.
1766 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1767 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1768 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1769 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1770 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1773 /* Remap from 0..255 back to 1..256 */
1774 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1776 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1777 if (state
->line_stipple_enable
) {
1778 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1779 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1780 line
.LineStippleRepeatCount
= line_stipple_factor
;
1788 * The pipe->bind_rasterizer_state() driver hook.
1790 * Bind a rasterizer CSO and flag related dirty bits.
1793 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1795 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1796 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1797 struct iris_rasterizer_state
*new_cso
= state
;
1800 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1801 if (cso_changed_memcmp(line_stipple
))
1802 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1804 if (cso_changed(half_pixel_center
))
1805 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1807 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1808 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1810 if (cso_changed(rasterizer_discard
))
1811 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1813 if (cso_changed(flatshade_first
))
1814 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1816 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1817 cso_changed(clip_halfz
))
1818 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1820 if (cso_changed(sprite_coord_enable
) ||
1821 cso_changed(sprite_coord_mode
) ||
1822 cso_changed(light_twoside
))
1823 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1825 if (cso_changed(conservative_rasterization
))
1826 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
1829 ice
->state
.cso_rast
= new_cso
;
1830 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1831 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1832 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1836 * Return true if the given wrap mode requires the border color to exist.
1838 * (We can skip uploading it if the sampler isn't going to use it.)
1841 wrap_mode_needs_border_color(unsigned wrap_mode
)
1843 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1847 * Gallium CSO for sampler state.
1849 struct iris_sampler_state
{
1850 union pipe_color_union border_color
;
1851 bool needs_border_color
;
1853 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1857 * The pipe->create_sampler_state() driver hook.
1859 * We fill out SAMPLER_STATE (except for the border color pointer), and
1860 * store that on the CPU. It doesn't make sense to upload it to a GPU
1861 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1862 * all bound sampler states to be in contiguous memor.
1865 iris_create_sampler_state(struct pipe_context
*ctx
,
1866 const struct pipe_sampler_state
*state
)
1868 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1873 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1874 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1876 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1877 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1878 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1880 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1882 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1883 wrap_mode_needs_border_color(wrap_t
) ||
1884 wrap_mode_needs_border_color(wrap_r
);
1886 float min_lod
= state
->min_lod
;
1887 unsigned mag_img_filter
= state
->mag_img_filter
;
1889 // XXX: explain this code ported from ilo...I don't get it at all...
1890 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1891 state
->min_lod
> 0.0f
) {
1893 mag_img_filter
= state
->min_img_filter
;
1896 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1897 samp
.TCXAddressControlMode
= wrap_s
;
1898 samp
.TCYAddressControlMode
= wrap_t
;
1899 samp
.TCZAddressControlMode
= wrap_r
;
1900 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1901 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1902 samp
.MinModeFilter
= state
->min_img_filter
;
1903 samp
.MagModeFilter
= mag_img_filter
;
1904 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1905 samp
.MaximumAnisotropy
= RATIO21
;
1907 if (state
->max_anisotropy
>= 2) {
1908 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1909 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1910 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1913 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1914 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1916 samp
.MaximumAnisotropy
=
1917 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1920 /* Set address rounding bits if not using nearest filtering. */
1921 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1922 samp
.UAddressMinFilterRoundingEnable
= true;
1923 samp
.VAddressMinFilterRoundingEnable
= true;
1924 samp
.RAddressMinFilterRoundingEnable
= true;
1927 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1928 samp
.UAddressMagFilterRoundingEnable
= true;
1929 samp
.VAddressMagFilterRoundingEnable
= true;
1930 samp
.RAddressMagFilterRoundingEnable
= true;
1933 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1934 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1936 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1938 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1939 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1940 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1941 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1943 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1950 * The pipe->bind_sampler_states() driver hook.
1953 iris_bind_sampler_states(struct pipe_context
*ctx
,
1954 enum pipe_shader_type p_stage
,
1955 unsigned start
, unsigned count
,
1958 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1959 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1960 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1962 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1966 for (int i
= 0; i
< count
; i
++) {
1967 if (shs
->samplers
[start
+ i
] != states
[i
]) {
1968 shs
->samplers
[start
+ i
] = states
[i
];
1974 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1978 * Upload the sampler states into a contiguous area of GPU memory, for
1979 * for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1981 * Also fill out the border color state pointers.
1984 iris_upload_sampler_states(struct iris_context
*ice
, gl_shader_stage stage
)
1986 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1987 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
1989 /* We assume the state tracker will call pipe->bind_sampler_states()
1990 * if the program's number of textures changes.
1992 unsigned count
= info
? util_last_bit(info
->textures_used
) : 0;
1997 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1998 * in the dynamic state memory zone, so we can point to it via the
1999 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
2001 unsigned size
= count
* 4 * GENX(SAMPLER_STATE_length
);
2003 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
, size
, 32);
2007 struct pipe_resource
*res
= shs
->sampler_table
.res
;
2008 struct iris_bo
*bo
= iris_resource_bo(res
);
2010 iris_record_state_size(ice
->state
.sizes
,
2011 bo
->gtt_offset
+ shs
->sampler_table
.offset
, size
);
2013 shs
->sampler_table
.offset
+= iris_bo_offset_from_base_address(bo
);
2015 /* Make sure all land in the same BO */
2016 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
2018 ice
->state
.need_border_colors
&= ~(1 << stage
);
2020 for (int i
= 0; i
< count
; i
++) {
2021 struct iris_sampler_state
*state
= shs
->samplers
[i
];
2022 struct iris_sampler_view
*tex
= shs
->textures
[i
];
2025 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
2026 } else if (!state
->needs_border_color
) {
2027 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
2029 ice
->state
.need_border_colors
|= 1 << stage
;
2031 /* We may need to swizzle the border color for format faking.
2032 * A/LA formats are faked as R/RG with 000R or R00G swizzles.
2033 * This means we need to move the border color's A channel into
2034 * the R or G channels so that those read swizzles will move it
2037 union pipe_color_union
*color
= &state
->border_color
;
2038 union pipe_color_union tmp
;
2040 enum pipe_format internal_format
= tex
->res
->internal_format
;
2042 if (util_format_is_alpha(internal_format
)) {
2043 unsigned char swz
[4] = {
2044 PIPE_SWIZZLE_W
, PIPE_SWIZZLE_0
,
2045 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
2047 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
2049 } else if (util_format_is_luminance_alpha(internal_format
) &&
2050 internal_format
!= PIPE_FORMAT_L8A8_SRGB
) {
2051 unsigned char swz
[4] = {
2052 PIPE_SWIZZLE_X
, PIPE_SWIZZLE_W
,
2053 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
2055 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
2060 /* Stream out the border color and merge the pointer. */
2061 uint32_t offset
= iris_upload_border_color(ice
, color
);
2063 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
2064 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
2065 dyns
.BorderColorPointer
= offset
;
2068 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
2069 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
2072 map
+= GENX(SAMPLER_STATE_length
);
2076 static enum isl_channel_select
2077 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
2080 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
2081 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
2082 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
2083 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
2084 case PIPE_SWIZZLE_1
: return SCS_ONE
;
2085 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
2086 default: unreachable("invalid swizzle");
2091 fill_buffer_surface_state(struct isl_device
*isl_dev
,
2092 struct iris_resource
*res
,
2094 enum isl_format format
,
2095 struct isl_swizzle swizzle
,
2099 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
2100 const unsigned cpp
= format
== ISL_FORMAT_RAW
? 1 : fmtl
->bpb
/ 8;
2102 /* The ARB_texture_buffer_specification says:
2104 * "The number of texels in the buffer texture's texel array is given by
2106 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
2108 * where <buffer_size> is the size of the buffer object, in basic
2109 * machine units and <components> and <base_type> are the element count
2110 * and base data type for elements, as specified in Table X.1. The
2111 * number of texels in the texel array is then clamped to the
2112 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
2114 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
2115 * so that when ISL divides by stride to obtain the number of texels, that
2116 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
2118 unsigned final_size
=
2119 MIN3(size
, res
->bo
->size
- res
->offset
- offset
,
2120 IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
2122 isl_buffer_fill_state(isl_dev
, map
,
2123 .address
= res
->bo
->gtt_offset
+ res
->offset
+ offset
,
2124 .size_B
= final_size
,
2128 .mocs
= iris_mocs(res
->bo
, isl_dev
));
2131 #define SURFACE_STATE_ALIGNMENT 64
2134 * Allocate several contiguous SURFACE_STATE structures, one for each
2135 * supported auxiliary surface mode. This only allocates the CPU-side
2136 * copy, they will need to be uploaded later after they're filled in.
2139 alloc_surface_states(struct iris_surface_state
*surf_state
,
2140 unsigned aux_usages
)
2142 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
2144 /* If this changes, update this to explicitly align pointers */
2145 STATIC_ASSERT(surf_size
== SURFACE_STATE_ALIGNMENT
);
2147 assert(aux_usages
!= 0);
2149 /* In case we're re-allocating them... */
2150 free(surf_state
->cpu
);
2152 surf_state
->num_states
= util_bitcount(aux_usages
);
2153 surf_state
->cpu
= calloc(surf_state
->num_states
, surf_size
);
2154 surf_state
->ref
.offset
= 0;
2155 pipe_resource_reference(&surf_state
->ref
.res
, NULL
);
2157 assert(surf_state
->cpu
);
2161 * Upload the CPU side SURFACE_STATEs into a GPU buffer.
2164 upload_surface_states(struct u_upload_mgr
*mgr
,
2165 struct iris_surface_state
*surf_state
)
2167 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
2168 const unsigned bytes
= surf_state
->num_states
* surf_size
;
2171 upload_state(mgr
, &surf_state
->ref
, bytes
, SURFACE_STATE_ALIGNMENT
);
2173 surf_state
->ref
.offset
+=
2174 iris_bo_offset_from_base_address(iris_resource_bo(surf_state
->ref
.res
));
2177 memcpy(map
, surf_state
->cpu
, bytes
);
2181 * Update resource addresses in a set of SURFACE_STATE descriptors,
2182 * and re-upload them if necessary.
2185 update_surface_state_addrs(struct u_upload_mgr
*mgr
,
2186 struct iris_surface_state
*surf_state
,
2189 if (surf_state
->bo_address
== bo
->gtt_offset
)
2192 STATIC_ASSERT(GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_start
) % 64 == 0);
2193 STATIC_ASSERT(GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_bits
) == 64);
2195 uint64_t *ss_addr
= (uint64_t *) &surf_state
->cpu
[GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_start
) / 32];
2197 /* First, update the CPU copies. We assume no other fields exist in
2198 * the QWord containing Surface Base Address.
2200 for (unsigned i
= 0; i
< surf_state
->num_states
; i
++) {
2201 *ss_addr
= *ss_addr
- surf_state
->bo_address
+ bo
->gtt_offset
;
2202 ss_addr
= ((void *) ss_addr
) + SURFACE_STATE_ALIGNMENT
;
2205 /* Next, upload the updated copies to a GPU buffer. */
2206 upload_surface_states(mgr
, surf_state
);
2208 surf_state
->bo_address
= bo
->gtt_offset
;
2215 * Return an ISL surface for use with non-coherent render target reads.
2217 * In a few complex cases, we can't use the SURFACE_STATE for normal render
2218 * target writes. We need to make a separate one for sampling which refers
2219 * to the single slice of the texture being read.
2222 get_rt_read_isl_surf(const struct gen_device_info
*devinfo
,
2223 struct iris_resource
*res
,
2224 enum pipe_texture_target target
,
2225 struct isl_view
*view
,
2226 uint32_t *offset_to_tile
,
2227 uint32_t *tile_x_sa
,
2228 uint32_t *tile_y_sa
,
2229 struct isl_surf
*surf
)
2233 const enum isl_dim_layout dim_layout
=
2234 iris_get_isl_dim_layout(devinfo
, res
->surf
.tiling
, target
);
2236 surf
->dim
= target_to_isl_surf_dim(target
);
2238 if (surf
->dim_layout
== dim_layout
)
2241 /* The layout of the specified texture target is not compatible with the
2242 * actual layout of the miptree structure in memory -- You're entering
2243 * dangerous territory, this can only possibly work if you only intended
2244 * to access a single level and slice of the texture, and the hardware
2245 * supports the tile offset feature in order to allow non-tile-aligned
2246 * base offsets, since we'll have to point the hardware to the first
2247 * texel of the level instead of relying on the usual base level/layer
2250 assert(view
->levels
== 1 && view
->array_len
== 1);
2251 assert(*tile_x_sa
== 0 && *tile_y_sa
== 0);
2253 *offset_to_tile
= iris_resource_get_tile_offsets(res
, view
->base_level
,
2254 view
->base_array_layer
,
2255 tile_x_sa
, tile_y_sa
);
2256 const unsigned l
= view
->base_level
;
2258 surf
->logical_level0_px
.width
= minify(surf
->logical_level0_px
.width
, l
);
2259 surf
->logical_level0_px
.height
= surf
->dim
<= ISL_SURF_DIM_1D
? 1 :
2260 minify(surf
->logical_level0_px
.height
, l
);
2261 surf
->logical_level0_px
.depth
= surf
->dim
<= ISL_SURF_DIM_2D
? 1 :
2262 minify(surf
->logical_level0_px
.depth
, l
);
2264 surf
->logical_level0_px
.array_len
= 1;
2266 surf
->dim_layout
= dim_layout
;
2268 view
->base_level
= 0;
2269 view
->base_array_layer
= 0;
2274 fill_surface_state(struct isl_device
*isl_dev
,
2276 struct iris_resource
*res
,
2277 struct isl_surf
*surf
,
2278 struct isl_view
*view
,
2280 uint32_t extra_main_offset
,
2284 struct isl_surf_fill_state_info f
= {
2287 .mocs
= iris_mocs(res
->bo
, isl_dev
),
2288 .address
= res
->bo
->gtt_offset
+ res
->offset
+ extra_main_offset
,
2289 .x_offset_sa
= tile_x_sa
,
2290 .y_offset_sa
= tile_y_sa
,
2293 assert(!iris_resource_unfinished_aux_import(res
));
2295 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
2296 f
.aux_surf
= &res
->aux
.surf
;
2297 f
.aux_usage
= aux_usage
;
2298 f
.aux_address
= res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
;
2300 struct iris_bo
*clear_bo
= NULL
;
2301 uint64_t clear_offset
= 0;
2303 iris_resource_get_clear_color(res
, &clear_bo
, &clear_offset
);
2305 f
.clear_address
= clear_bo
->gtt_offset
+ clear_offset
;
2306 f
.use_clear_address
= isl_dev
->info
->gen
> 9;
2310 isl_surf_fill_state_s(isl_dev
, map
, &f
);
2314 * The pipe->create_sampler_view() driver hook.
2316 static struct pipe_sampler_view
*
2317 iris_create_sampler_view(struct pipe_context
*ctx
,
2318 struct pipe_resource
*tex
,
2319 const struct pipe_sampler_view
*tmpl
)
2321 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2322 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2323 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2324 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
2329 /* initialize base object */
2331 isv
->base
.context
= ctx
;
2332 isv
->base
.texture
= NULL
;
2333 pipe_reference_init(&isv
->base
.reference
, 1);
2334 pipe_resource_reference(&isv
->base
.texture
, tex
);
2336 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
2337 struct iris_resource
*zres
, *sres
;
2338 const struct util_format_description
*desc
=
2339 util_format_description(tmpl
->format
);
2341 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
2343 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
2346 isv
->res
= (struct iris_resource
*) tex
;
2348 alloc_surface_states(&isv
->surface_state
, isv
->res
->aux
.sampler_usages
);
2350 isv
->surface_state
.bo_address
= isv
->res
->bo
->gtt_offset
;
2352 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
2354 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
2355 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
2356 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
2358 const struct iris_format_info fmt
=
2359 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
2361 isv
->clear_color
= isv
->res
->aux
.clear_color
;
2363 isv
->view
= (struct isl_view
) {
2365 .swizzle
= (struct isl_swizzle
) {
2366 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
2367 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
2368 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
2369 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
2374 void *map
= isv
->surface_state
.cpu
;
2376 /* Fill out SURFACE_STATE for this view. */
2377 if (tmpl
->target
!= PIPE_BUFFER
) {
2378 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
2379 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
2380 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
2381 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
2382 isv
->view
.array_len
=
2383 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
2385 if (iris_resource_unfinished_aux_import(isv
->res
))
2386 iris_resource_finish_aux_import(&screen
->base
, isv
->res
);
2388 unsigned aux_modes
= isv
->res
->aux
.sampler_usages
;
2390 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
2392 /* If we have a multisampled depth buffer, do not create a sampler
2393 * surface state with HiZ.
2395 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->res
->surf
,
2396 &isv
->view
, aux_usage
, 0, 0, 0);
2398 map
+= SURFACE_STATE_ALIGNMENT
;
2401 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
2402 isv
->view
.format
, isv
->view
.swizzle
,
2403 tmpl
->u
.buf
.offset
, tmpl
->u
.buf
.size
);
2406 upload_surface_states(ice
->state
.surface_uploader
, &isv
->surface_state
);
2412 iris_sampler_view_destroy(struct pipe_context
*ctx
,
2413 struct pipe_sampler_view
*state
)
2415 struct iris_sampler_view
*isv
= (void *) state
;
2416 pipe_resource_reference(&state
->texture
, NULL
);
2417 pipe_resource_reference(&isv
->surface_state
.ref
.res
, NULL
);
2418 free(isv
->surface_state
.cpu
);
2423 * The pipe->create_surface() driver hook.
2425 * In Gallium nomenclature, "surfaces" are a view of a resource that
2426 * can be bound as a render target or depth/stencil buffer.
2428 static struct pipe_surface
*
2429 iris_create_surface(struct pipe_context
*ctx
,
2430 struct pipe_resource
*tex
,
2431 const struct pipe_surface
*tmpl
)
2433 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2434 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2435 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2437 isl_surf_usage_flags_t usage
= 0;
2439 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
2440 else if (util_format_is_depth_or_stencil(tmpl
->format
))
2441 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
2443 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
2445 const struct iris_format_info fmt
=
2446 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
2448 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
2449 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
2450 /* Framebuffer validation will reject this invalid case, but it
2451 * hasn't had the opportunity yet. In the meantime, we need to
2452 * avoid hitting ISL asserts about unsupported formats below.
2457 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
2458 struct pipe_surface
*psurf
= &surf
->base
;
2459 struct iris_resource
*res
= (struct iris_resource
*) tex
;
2464 pipe_reference_init(&psurf
->reference
, 1);
2465 pipe_resource_reference(&psurf
->texture
, tex
);
2466 psurf
->context
= ctx
;
2467 psurf
->format
= tmpl
->format
;
2468 psurf
->width
= tex
->width0
;
2469 psurf
->height
= tex
->height0
;
2470 psurf
->texture
= tex
;
2471 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
2472 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
2473 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
2475 uint32_t array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
2477 struct isl_view
*view
= &surf
->view
;
2478 *view
= (struct isl_view
) {
2480 .base_level
= tmpl
->u
.tex
.level
,
2482 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2483 .array_len
= array_len
,
2484 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2489 enum pipe_texture_target target
= (tex
->target
== PIPE_TEXTURE_3D
&&
2490 array_len
== 1) ? PIPE_TEXTURE_2D
:
2491 tex
->target
== PIPE_TEXTURE_1D_ARRAY
?
2492 PIPE_TEXTURE_2D_ARRAY
: tex
->target
;
2494 struct isl_view
*read_view
= &surf
->read_view
;
2495 *read_view
= (struct isl_view
) {
2497 .base_level
= tmpl
->u
.tex
.level
,
2499 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2500 .array_len
= array_len
,
2501 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2502 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
2506 surf
->clear_color
= res
->aux
.clear_color
;
2508 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
2509 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
2510 ISL_SURF_USAGE_STENCIL_BIT
))
2514 alloc_surface_states(&surf
->surface_state
, res
->aux
.possible_usages
);
2515 surf
->surface_state
.bo_address
= res
->bo
->gtt_offset
;
2518 alloc_surface_states(&surf
->surface_state_read
, res
->aux
.possible_usages
);
2519 surf
->surface_state_read
.bo_address
= res
->bo
->gtt_offset
;
2522 if (!isl_format_is_compressed(res
->surf
.format
)) {
2523 if (iris_resource_unfinished_aux_import(res
))
2524 iris_resource_finish_aux_import(&screen
->base
, res
);
2526 void *map
= surf
->surface_state
.cpu
;
2527 UNUSED
void *map_read
= surf
->surface_state_read
.cpu
;
2529 /* This is a normal surface. Fill out a SURFACE_STATE for each possible
2530 * auxiliary surface mode and return the pipe_surface.
2532 unsigned aux_modes
= res
->aux
.possible_usages
;
2534 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
2535 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2536 view
, aux_usage
, 0, 0, 0);
2537 map
+= SURFACE_STATE_ALIGNMENT
;
2540 struct isl_surf surf
;
2541 uint32_t offset_to_tile
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
2542 get_rt_read_isl_surf(devinfo
, res
, target
, read_view
,
2543 &offset_to_tile
, &tile_x_sa
, &tile_y_sa
, &surf
);
2544 fill_surface_state(&screen
->isl_dev
, map_read
, res
, &surf
, read_view
,
2545 aux_usage
, offset_to_tile
, tile_x_sa
, tile_y_sa
);
2546 map_read
+= SURFACE_STATE_ALIGNMENT
;
2550 upload_surface_states(ice
->state
.surface_uploader
, &surf
->surface_state
);
2553 upload_surface_states(ice
->state
.surface_uploader
,
2554 &surf
->surface_state_read
);
2560 /* The resource has a compressed format, which is not renderable, but we
2561 * have a renderable view format. We must be attempting to upload blocks
2562 * of compressed data via an uncompressed view.
2564 * In this case, we can assume there are no auxiliary buffers, a single
2565 * miplevel, and that the resource is single-sampled. Gallium may try
2566 * and create an uncompressed view with multiple layers, however.
2568 assert(!isl_format_is_compressed(fmt
.fmt
));
2569 assert(res
->aux
.possible_usages
== 1 << ISL_AUX_USAGE_NONE
);
2570 assert(res
->surf
.samples
== 1);
2571 assert(view
->levels
== 1);
2573 struct isl_surf isl_surf
;
2574 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
2576 if (view
->base_level
> 0) {
2577 /* We can't rely on the hardware's miplevel selection with such
2578 * a substantial lie about the format, so we select a single image
2579 * using the Tile X/Y Offset fields. In this case, we can't handle
2580 * multiple array slices.
2582 * On Broadwell, HALIGN and VALIGN are specified in pixels and are
2583 * hard-coded to align to exactly the block size of the compressed
2584 * texture. This means that, when reinterpreted as a non-compressed
2585 * texture, the tile offsets may be anything and we can't rely on
2588 * Return NULL to force the state tracker to take fallback paths.
2590 if (view
->array_len
> 1 || GEN_GEN
== 8)
2593 const bool is_3d
= res
->surf
.dim
== ISL_SURF_DIM_3D
;
2594 isl_surf_get_image_surf(&screen
->isl_dev
, &res
->surf
,
2596 is_3d
? 0 : view
->base_array_layer
,
2597 is_3d
? view
->base_array_layer
: 0,
2599 &offset_B
, &tile_x_sa
, &tile_y_sa
);
2601 /* We use address and tile offsets to access a single level/layer
2602 * as a subimage, so reset level/layer so it doesn't offset again.
2604 view
->base_array_layer
= 0;
2605 view
->base_level
= 0;
2607 /* Level 0 doesn't require tile offsets, and the hardware can find
2608 * array slices using QPitch even with the format override, so we
2609 * can allow layers in this case. Copy the original ISL surface.
2611 memcpy(&isl_surf
, &res
->surf
, sizeof(isl_surf
));
2614 /* Scale down the image dimensions by the block size. */
2615 const struct isl_format_layout
*fmtl
=
2616 isl_format_get_layout(res
->surf
.format
);
2617 isl_surf
.format
= fmt
.fmt
;
2618 isl_surf
.logical_level0_px
= isl_surf_get_logical_level0_el(&isl_surf
);
2619 isl_surf
.phys_level0_sa
= isl_surf_get_phys_level0_el(&isl_surf
);
2620 tile_x_sa
/= fmtl
->bw
;
2621 tile_y_sa
/= fmtl
->bh
;
2623 psurf
->width
= isl_surf
.logical_level0_px
.width
;
2624 psurf
->height
= isl_surf
.logical_level0_px
.height
;
2626 struct isl_surf_fill_state_info f
= {
2629 .mocs
= iris_mocs(res
->bo
, &screen
->isl_dev
),
2630 .address
= res
->bo
->gtt_offset
+ offset_B
,
2631 .x_offset_sa
= tile_x_sa
,
2632 .y_offset_sa
= tile_y_sa
,
2635 isl_surf_fill_state_s(&screen
->isl_dev
, surf
->surface_state
.cpu
, &f
);
2637 upload_surface_states(ice
->state
.surface_uploader
, &surf
->surface_state
);
2644 fill_default_image_param(struct brw_image_param
*param
)
2646 memset(param
, 0, sizeof(*param
));
2647 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
2648 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
2649 * detailed explanation of these parameters.
2651 param
->swizzling
[0] = 0xff;
2652 param
->swizzling
[1] = 0xff;
2656 fill_buffer_image_param(struct brw_image_param
*param
,
2657 enum pipe_format pfmt
,
2660 const unsigned cpp
= util_format_get_blocksize(pfmt
);
2662 fill_default_image_param(param
);
2663 param
->size
[0] = size
/ cpp
;
2664 param
->stride
[0] = cpp
;
2667 #define isl_surf_fill_image_param(x, ...)
2668 #define fill_default_image_param(x, ...)
2669 #define fill_buffer_image_param(x, ...)
2673 * The pipe->set_shader_images() driver hook.
2676 iris_set_shader_images(struct pipe_context
*ctx
,
2677 enum pipe_shader_type p_stage
,
2678 unsigned start_slot
, unsigned count
,
2679 const struct pipe_image_view
*p_images
)
2681 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2682 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2683 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2684 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2685 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2687 struct iris_genx_state
*genx
= ice
->state
.genx
;
2688 struct brw_image_param
*image_params
= genx
->shaders
[stage
].image_param
;
2691 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
2693 for (unsigned i
= 0; i
< count
; i
++) {
2694 struct iris_image_view
*iv
= &shs
->image
[start_slot
+ i
];
2696 if (p_images
&& p_images
[i
].resource
) {
2697 const struct pipe_image_view
*img
= &p_images
[i
];
2698 struct iris_resource
*res
= (void *) img
->resource
;
2700 util_copy_image_view(&iv
->base
, img
);
2702 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
2704 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
2705 res
->bind_stages
|= 1 << stage
;
2707 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
2708 enum isl_format isl_fmt
=
2709 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
2711 bool untyped_fallback
= false;
2713 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
2714 /* On Gen8, try to use typed surfaces reads (which support a
2715 * limited number of formats), and if not possible, fall back
2718 untyped_fallback
= GEN_GEN
== 8 &&
2719 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
);
2721 if (untyped_fallback
)
2722 isl_fmt
= ISL_FORMAT_RAW
;
2724 isl_fmt
= isl_lower_storage_image_format(devinfo
, isl_fmt
);
2727 alloc_surface_states(&iv
->surface_state
, 1 << ISL_AUX_USAGE_NONE
);
2728 iv
->surface_state
.bo_address
= res
->bo
->gtt_offset
;
2730 void *map
= iv
->surface_state
.cpu
;
2732 if (res
->base
.target
!= PIPE_BUFFER
) {
2733 struct isl_view view
= {
2735 .base_level
= img
->u
.tex
.level
,
2737 .base_array_layer
= img
->u
.tex
.first_layer
,
2738 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
2739 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2743 if (untyped_fallback
) {
2744 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2745 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2748 /* Images don't support compression */
2749 unsigned aux_modes
= 1 << ISL_AUX_USAGE_NONE
;
2751 enum isl_aux_usage usage
= u_bit_scan(&aux_modes
);
2753 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2754 &view
, usage
, 0, 0, 0);
2756 map
+= SURFACE_STATE_ALIGNMENT
;
2760 isl_surf_fill_image_param(&screen
->isl_dev
,
2761 &image_params
[start_slot
+ i
],
2764 util_range_add(&res
->base
, &res
->valid_buffer_range
, img
->u
.buf
.offset
,
2765 img
->u
.buf
.offset
+ img
->u
.buf
.size
);
2767 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2768 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2769 img
->u
.buf
.offset
, img
->u
.buf
.size
);
2770 fill_buffer_image_param(&image_params
[start_slot
+ i
],
2771 img
->format
, img
->u
.buf
.size
);
2774 upload_surface_states(ice
->state
.surface_uploader
, &iv
->surface_state
);
2776 pipe_resource_reference(&iv
->base
.resource
, NULL
);
2777 pipe_resource_reference(&iv
->surface_state
.ref
.res
, NULL
);
2778 fill_default_image_param(&image_params
[start_slot
+ i
]);
2782 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2784 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2785 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2787 /* Broadwell also needs brw_image_params re-uploaded */
2789 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2790 shs
->sysvals_need_upload
= true;
2796 * The pipe->set_sampler_views() driver hook.
2799 iris_set_sampler_views(struct pipe_context
*ctx
,
2800 enum pipe_shader_type p_stage
,
2801 unsigned start
, unsigned count
,
2802 struct pipe_sampler_view
**views
)
2804 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2805 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2806 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2808 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
2810 for (unsigned i
= 0; i
< count
; i
++) {
2811 struct pipe_sampler_view
*pview
= views
? views
[i
] : NULL
;
2812 pipe_sampler_view_reference((struct pipe_sampler_view
**)
2813 &shs
->textures
[start
+ i
], pview
);
2814 struct iris_sampler_view
*view
= (void *) pview
;
2816 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
2817 view
->res
->bind_stages
|= 1 << stage
;
2819 shs
->bound_sampler_views
|= 1 << (start
+ i
);
2821 update_surface_state_addrs(ice
->state
.surface_uploader
,
2822 &view
->surface_state
, view
->res
->bo
);
2826 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
2828 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2829 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2833 * The pipe->set_tess_state() driver hook.
2836 iris_set_tess_state(struct pipe_context
*ctx
,
2837 const float default_outer_level
[4],
2838 const float default_inner_level
[2])
2840 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2841 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
2843 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
2844 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
2846 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
2847 shs
->sysvals_need_upload
= true;
2851 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
2853 struct iris_surface
*surf
= (void *) p_surf
;
2854 pipe_resource_reference(&p_surf
->texture
, NULL
);
2855 pipe_resource_reference(&surf
->surface_state
.ref
.res
, NULL
);
2856 pipe_resource_reference(&surf
->surface_state_read
.ref
.res
, NULL
);
2857 free(surf
->surface_state
.cpu
);
2862 iris_set_clip_state(struct pipe_context
*ctx
,
2863 const struct pipe_clip_state
*state
)
2865 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2866 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
2867 struct iris_shader_state
*gshs
= &ice
->state
.shaders
[MESA_SHADER_GEOMETRY
];
2868 struct iris_shader_state
*tshs
= &ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
];
2870 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
2872 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
| IRIS_DIRTY_CONSTANTS_GS
|
2873 IRIS_DIRTY_CONSTANTS_TES
;
2874 shs
->sysvals_need_upload
= true;
2875 gshs
->sysvals_need_upload
= true;
2876 tshs
->sysvals_need_upload
= true;
2880 * The pipe->set_polygon_stipple() driver hook.
2883 iris_set_polygon_stipple(struct pipe_context
*ctx
,
2884 const struct pipe_poly_stipple
*state
)
2886 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2887 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
2888 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
2892 * The pipe->set_sample_mask() driver hook.
2895 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2897 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2899 /* We only support 16x MSAA, so we have 16 bits of sample maks.
2900 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
2902 ice
->state
.sample_mask
= sample_mask
& 0xffff;
2903 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
2907 * The pipe->set_scissor_states() driver hook.
2909 * This corresponds to our SCISSOR_RECT state structures. It's an
2910 * exact match, so we just store them, and memcpy them out later.
2913 iris_set_scissor_states(struct pipe_context
*ctx
,
2914 unsigned start_slot
,
2915 unsigned num_scissors
,
2916 const struct pipe_scissor_state
*rects
)
2918 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2920 for (unsigned i
= 0; i
< num_scissors
; i
++) {
2921 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
2922 /* If the scissor was out of bounds and got clamped to 0 width/height
2923 * at the bounds, the subtraction of 1 from maximums could produce a
2924 * negative number and thus not clip anything. Instead, just provide
2925 * a min > max scissor inside the bounds, which produces the expected
2928 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2929 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
2932 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2933 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
2934 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
2939 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
2943 * The pipe->set_stencil_ref() driver hook.
2945 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
2948 iris_set_stencil_ref(struct pipe_context
*ctx
,
2949 const struct pipe_stencil_ref
*state
)
2951 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2952 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2954 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2956 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2960 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2962 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2966 * The pipe->set_viewport_states() driver hook.
2968 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2969 * the guardband yet, as we need the framebuffer dimensions, but we can
2970 * at least fill out the rest.
2973 iris_set_viewport_states(struct pipe_context
*ctx
,
2974 unsigned start_slot
,
2976 const struct pipe_viewport_state
*states
)
2978 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2980 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2982 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2984 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2985 !ice
->state
.cso_rast
->depth_clip_far
))
2986 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2990 * The pipe->set_framebuffer_state() driver hook.
2992 * Sets the current draw FBO, including color render targets, depth,
2993 * and stencil buffers.
2996 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2997 const struct pipe_framebuffer_state
*state
)
2999 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3000 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
3001 struct isl_device
*isl_dev
= &screen
->isl_dev
;
3002 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
3003 struct iris_resource
*zres
;
3004 struct iris_resource
*stencil_res
;
3006 unsigned samples
= util_framebuffer_get_num_samples(state
);
3007 unsigned layers
= util_framebuffer_get_num_layers(state
);
3009 if (cso
->samples
!= samples
) {
3010 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
3012 /* We need to toggle 3DSTATE_PS::32 Pixel Dispatch Enable */
3013 if (GEN_GEN
>= 9 && (cso
->samples
== 16 || samples
== 16))
3014 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
3017 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
3018 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
3021 if ((cso
->layers
== 0) != (layers
== 0)) {
3022 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
3025 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
3026 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
3029 if (cso
->zsbuf
|| state
->zsbuf
) {
3030 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
3033 util_copy_framebuffer_state(cso
, state
);
3034 cso
->samples
= samples
;
3035 cso
->layers
= layers
;
3037 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
3039 struct isl_view view
= {
3042 .base_array_layer
= 0,
3044 .swizzle
= ISL_SWIZZLE_IDENTITY
,
3047 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
3050 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
3053 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
3054 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
3056 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
3059 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
3061 info
.depth_surf
= &zres
->surf
;
3062 info
.depth_address
= zres
->bo
->gtt_offset
+ zres
->offset
;
3063 info
.mocs
= iris_mocs(zres
->bo
, isl_dev
);
3065 view
.format
= zres
->surf
.format
;
3067 if (iris_resource_level_has_hiz(zres
, view
.base_level
)) {
3068 info
.hiz_usage
= zres
->aux
.usage
;
3069 info
.hiz_surf
= &zres
->aux
.surf
;
3070 info
.hiz_address
= zres
->aux
.bo
->gtt_offset
+ zres
->aux
.offset
;
3075 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
3076 info
.stencil_aux_usage
= stencil_res
->aux
.usage
;
3077 info
.stencil_surf
= &stencil_res
->surf
;
3078 info
.stencil_address
= stencil_res
->bo
->gtt_offset
+ stencil_res
->offset
;
3080 view
.format
= stencil_res
->surf
.format
;
3081 info
.mocs
= iris_mocs(stencil_res
->bo
, isl_dev
);
3086 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
3088 /* Make a null surface for unbound buffers */
3089 void *null_surf_map
=
3090 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
3091 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
3092 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
3093 isl_extent3d(MAX2(cso
->width
, 1),
3094 MAX2(cso
->height
, 1),
3095 cso
->layers
? cso
->layers
: 1));
3096 ice
->state
.null_fb
.offset
+=
3097 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
3099 /* Render target change */
3100 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
3102 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_BUFFER
;
3104 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
3106 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
3109 ice
->state
.dirty
|= IRIS_DIRTY_PMA_FIX
;
3113 * The pipe->set_constant_buffer() driver hook.
3115 * This uploads any constant data in user buffers, and references
3116 * any UBO resources containing constant data.
3119 iris_set_constant_buffer(struct pipe_context
*ctx
,
3120 enum pipe_shader_type p_stage
, unsigned index
,
3121 const struct pipe_constant_buffer
*input
)
3123 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3124 gl_shader_stage stage
= stage_from_pipe(p_stage
);
3125 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3126 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[index
];
3128 /* TODO: Only do this if the buffer changes? */
3129 pipe_resource_reference(&shs
->constbuf_surf_state
[index
].res
, NULL
);
3131 if (input
&& input
->buffer_size
&& (input
->buffer
|| input
->user_buffer
)) {
3132 shs
->bound_cbufs
|= 1u << index
;
3134 if (input
->user_buffer
) {
3136 pipe_resource_reference(&cbuf
->buffer
, NULL
);
3137 u_upload_alloc(ice
->ctx
.const_uploader
, 0, input
->buffer_size
, 64,
3138 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
3140 if (!cbuf
->buffer
) {
3141 /* Allocation was unsuccessful - just unbind */
3142 iris_set_constant_buffer(ctx
, p_stage
, index
, NULL
);
3147 memcpy(map
, input
->user_buffer
, input
->buffer_size
);
3148 } else if (input
->buffer
) {
3149 pipe_resource_reference(&cbuf
->buffer
, input
->buffer
);
3151 cbuf
->buffer_offset
= input
->buffer_offset
;
3155 MIN2(input
->buffer_size
,
3156 iris_resource_bo(cbuf
->buffer
)->size
- cbuf
->buffer_offset
);
3158 struct iris_resource
*res
= (void *) cbuf
->buffer
;
3159 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
3160 res
->bind_stages
|= 1 << stage
;
3162 shs
->bound_cbufs
&= ~(1u << index
);
3163 pipe_resource_reference(&cbuf
->buffer
, NULL
);
3166 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
3170 upload_sysvals(struct iris_context
*ice
,
3171 gl_shader_stage stage
)
3173 UNUSED
struct iris_genx_state
*genx
= ice
->state
.genx
;
3174 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3176 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3177 if (!shader
|| shader
->num_system_values
== 0)
3180 assert(shader
->num_cbufs
> 0);
3182 unsigned sysval_cbuf_index
= shader
->num_cbufs
- 1;
3183 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[sysval_cbuf_index
];
3184 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t);
3185 uint32_t *map
= NULL
;
3187 assert(sysval_cbuf_index
< PIPE_MAX_CONSTANT_BUFFERS
);
3188 u_upload_alloc(ice
->ctx
.const_uploader
, 0, upload_size
, 64,
3189 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
3191 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
3192 uint32_t sysval
= shader
->system_values
[i
];
3195 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
3197 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
3198 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
3199 struct brw_image_param
*param
=
3200 &genx
->shaders
[stage
].image_param
[img
];
3202 assert(offset
< sizeof(struct brw_image_param
));
3203 value
= ((uint32_t *) param
)[offset
];
3205 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
3207 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
3208 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
3209 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
3210 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
3211 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
3212 if (stage
== MESA_SHADER_TESS_CTRL
) {
3213 value
= ice
->state
.vertices_per_patch
;
3215 assert(stage
== MESA_SHADER_TESS_EVAL
);
3216 const struct shader_info
*tcs_info
=
3217 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
3219 value
= tcs_info
->tess
.tcs_vertices_out
;
3221 value
= ice
->state
.vertices_per_patch
;
3223 } else if (sysval
>= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
&&
3224 sysval
<= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
) {
3225 unsigned i
= sysval
- BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
3226 value
= fui(ice
->state
.default_outer_level
[i
]);
3227 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
) {
3228 value
= fui(ice
->state
.default_inner_level
[0]);
3229 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
) {
3230 value
= fui(ice
->state
.default_inner_level
[1]);
3232 assert(!"unhandled system value");
3238 cbuf
->buffer_size
= upload_size
;
3239 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
3240 &shs
->constbuf_surf_state
[sysval_cbuf_index
], false);
3242 shs
->sysvals_need_upload
= false;
3246 * The pipe->set_shader_buffers() driver hook.
3248 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
3249 * SURFACE_STATE here, as the buffer offset may change each time.
3252 iris_set_shader_buffers(struct pipe_context
*ctx
,
3253 enum pipe_shader_type p_stage
,
3254 unsigned start_slot
, unsigned count
,
3255 const struct pipe_shader_buffer
*buffers
,
3256 unsigned writable_bitmask
)
3258 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3259 gl_shader_stage stage
= stage_from_pipe(p_stage
);
3260 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3262 unsigned modified_bits
= u_bit_consecutive(start_slot
, count
);
3264 shs
->bound_ssbos
&= ~modified_bits
;
3265 shs
->writable_ssbos
&= ~modified_bits
;
3266 shs
->writable_ssbos
|= writable_bitmask
<< start_slot
;
3268 for (unsigned i
= 0; i
< count
; i
++) {
3269 if (buffers
&& buffers
[i
].buffer
) {
3270 struct iris_resource
*res
= (void *) buffers
[i
].buffer
;
3271 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[start_slot
+ i
];
3272 struct iris_state_ref
*surf_state
=
3273 &shs
->ssbo_surf_state
[start_slot
+ i
];
3274 pipe_resource_reference(&ssbo
->buffer
, &res
->base
);
3275 ssbo
->buffer_offset
= buffers
[i
].buffer_offset
;
3277 MIN2(buffers
[i
].buffer_size
, res
->bo
->size
- ssbo
->buffer_offset
);
3279 shs
->bound_ssbos
|= 1 << (start_slot
+ i
);
3281 iris_upload_ubo_ssbo_surf_state(ice
, ssbo
, surf_state
, true);
3283 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
3284 res
->bind_stages
|= 1 << stage
;
3286 util_range_add(&res
->base
, &res
->valid_buffer_range
, ssbo
->buffer_offset
,
3287 ssbo
->buffer_offset
+ ssbo
->buffer_size
);
3289 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
].buffer
, NULL
);
3290 pipe_resource_reference(&shs
->ssbo_surf_state
[start_slot
+ i
].res
,
3295 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
3299 iris_delete_state(struct pipe_context
*ctx
, void *state
)
3305 * The pipe->set_vertex_buffers() driver hook.
3307 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
3310 iris_set_vertex_buffers(struct pipe_context
*ctx
,
3311 unsigned start_slot
, unsigned count
,
3312 const struct pipe_vertex_buffer
*buffers
)
3314 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3315 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
3316 struct iris_genx_state
*genx
= ice
->state
.genx
;
3318 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
3320 for (unsigned i
= 0; i
< count
; i
++) {
3321 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
3322 struct iris_vertex_buffer_state
*state
=
3323 &genx
->vertex_buffers
[start_slot
+ i
];
3326 pipe_resource_reference(&state
->resource
, NULL
);
3330 /* We may see user buffers that are NULL bindings. */
3331 assert(!(buffer
->is_user_buffer
&& buffer
->buffer
.user
!= NULL
));
3333 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
3334 struct iris_resource
*res
= (void *) state
->resource
;
3336 state
->offset
= (int) buffer
->buffer_offset
;
3339 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
3340 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
3343 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
3344 vb
.VertexBufferIndex
= start_slot
+ i
;
3345 vb
.AddressModifyEnable
= true;
3346 vb
.BufferPitch
= buffer
->stride
;
3348 vb
.BufferSize
= res
->base
.width0
- (int) buffer
->buffer_offset
;
3349 vb
.BufferStartingAddress
=
3350 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
3351 vb
.MOCS
= iris_mocs(res
->bo
, &screen
->isl_dev
);
3353 vb
.NullVertexBuffer
= true;
3358 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
3362 * Gallium CSO for vertex elements.
3364 struct iris_vertex_element_state
{
3365 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
3366 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
3367 uint32_t edgeflag_ve
[GENX(VERTEX_ELEMENT_STATE_length
)];
3368 uint32_t edgeflag_vfi
[GENX(3DSTATE_VF_INSTANCING_length
)];
3373 * The pipe->create_vertex_elements() driver hook.
3375 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
3376 * and 3DSTATE_VF_INSTANCING commands. The vertex_elements and vf_instancing
3377 * arrays are ready to be emitted at draw time if no EdgeFlag or SGVs are
3378 * needed. In these cases we will need information available at draw time.
3379 * We setup edgeflag_ve and edgeflag_vfi as alternatives last
3380 * 3DSTATE_VERTEX_ELEMENT and 3DSTATE_VF_INSTANCING that can be used at
3381 * draw time if we detect that EdgeFlag is needed by the Vertex Shader.
3384 iris_create_vertex_elements(struct pipe_context
*ctx
,
3386 const struct pipe_vertex_element
*state
)
3388 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
3389 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3390 struct iris_vertex_element_state
*cso
=
3391 malloc(sizeof(struct iris_vertex_element_state
));
3395 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
3397 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
3400 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
3401 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
3404 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
3406 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
3407 ve
.Component0Control
= VFCOMP_STORE_0
;
3408 ve
.Component1Control
= VFCOMP_STORE_0
;
3409 ve
.Component2Control
= VFCOMP_STORE_0
;
3410 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
3413 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
3417 for (int i
= 0; i
< count
; i
++) {
3418 const struct iris_format_info fmt
=
3419 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
3420 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
3421 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
3423 switch (isl_format_get_num_channels(fmt
.fmt
)) {
3424 case 0: comp
[0] = VFCOMP_STORE_0
; /* fallthrough */
3425 case 1: comp
[1] = VFCOMP_STORE_0
; /* fallthrough */
3426 case 2: comp
[2] = VFCOMP_STORE_0
; /* fallthrough */
3428 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
3429 : VFCOMP_STORE_1_FP
;
3432 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
3433 ve
.EdgeFlagEnable
= false;
3434 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
3436 ve
.SourceElementOffset
= state
[i
].src_offset
;
3437 ve
.SourceElementFormat
= fmt
.fmt
;
3438 ve
.Component0Control
= comp
[0];
3439 ve
.Component1Control
= comp
[1];
3440 ve
.Component2Control
= comp
[2];
3441 ve
.Component3Control
= comp
[3];
3444 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
3445 vi
.VertexElementIndex
= i
;
3446 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
3447 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
3450 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
3451 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
3454 /* An alternative version of the last VE and VFI is stored so it
3455 * can be used at draw time in case Vertex Shader uses EdgeFlag
3458 const unsigned edgeflag_index
= count
- 1;
3459 const struct iris_format_info fmt
=
3460 iris_format_for_usage(devinfo
, state
[edgeflag_index
].src_format
, 0);
3461 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), cso
->edgeflag_ve
, ve
) {
3462 ve
.EdgeFlagEnable
= true ;
3463 ve
.VertexBufferIndex
= state
[edgeflag_index
].vertex_buffer_index
;
3465 ve
.SourceElementOffset
= state
[edgeflag_index
].src_offset
;
3466 ve
.SourceElementFormat
= fmt
.fmt
;
3467 ve
.Component0Control
= VFCOMP_STORE_SRC
;
3468 ve
.Component1Control
= VFCOMP_STORE_0
;
3469 ve
.Component2Control
= VFCOMP_STORE_0
;
3470 ve
.Component3Control
= VFCOMP_STORE_0
;
3472 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->edgeflag_vfi
, vi
) {
3473 /* The vi.VertexElementIndex of the EdgeFlag Vertex Element is filled
3474 * at draw time, as it should change if SGVs are emitted.
3476 vi
.InstancingEnable
= state
[edgeflag_index
].instance_divisor
> 0;
3477 vi
.InstanceDataStepRate
= state
[edgeflag_index
].instance_divisor
;
3485 * The pipe->bind_vertex_elements_state() driver hook.
3488 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
3490 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3491 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
3492 struct iris_vertex_element_state
*new_cso
= state
;
3494 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
3495 * we need to re-emit it to ensure we're overriding the right one.
3497 if (new_cso
&& cso_changed(count
))
3498 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
3500 ice
->state
.cso_vertex_elements
= state
;
3501 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
3505 * The pipe->create_stream_output_target() driver hook.
3507 * "Target" here refers to a destination buffer. We translate this into
3508 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
3509 * know which buffer this represents, or whether we ought to zero the
3510 * write-offsets, or append. Those are handled in the set() hook.
3512 static struct pipe_stream_output_target
*
3513 iris_create_stream_output_target(struct pipe_context
*ctx
,
3514 struct pipe_resource
*p_res
,
3515 unsigned buffer_offset
,
3516 unsigned buffer_size
)
3518 struct iris_resource
*res
= (void *) p_res
;
3519 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
3523 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
3525 pipe_reference_init(&cso
->base
.reference
, 1);
3526 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
3527 cso
->base
.buffer_offset
= buffer_offset
;
3528 cso
->base
.buffer_size
= buffer_size
;
3529 cso
->base
.context
= ctx
;
3531 util_range_add(&res
->base
, &res
->valid_buffer_range
, buffer_offset
,
3532 buffer_offset
+ buffer_size
);
3534 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
3540 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
3541 struct pipe_stream_output_target
*state
)
3543 struct iris_stream_output_target
*cso
= (void *) state
;
3545 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
3546 pipe_resource_reference(&cso
->offset
.res
, NULL
);
3552 * The pipe->set_stream_output_targets() driver hook.
3554 * At this point, we know which targets are bound to a particular index,
3555 * and also whether we want to append or start over. We can finish the
3556 * 3DSTATE_SO_BUFFER packets we started earlier.
3559 iris_set_stream_output_targets(struct pipe_context
*ctx
,
3560 unsigned num_targets
,
3561 struct pipe_stream_output_target
**targets
,
3562 const unsigned *offsets
)
3564 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3565 struct iris_genx_state
*genx
= ice
->state
.genx
;
3566 uint32_t *so_buffers
= genx
->so_buffers
;
3567 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
3569 const bool active
= num_targets
> 0;
3570 if (ice
->state
.streamout_active
!= active
) {
3571 ice
->state
.streamout_active
= active
;
3572 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
3574 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
3575 * it's a non-pipelined command. If we're switching streamout on, we
3576 * may have missed emitting it earlier, so do so now. (We're already
3577 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
3580 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
3583 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3584 struct iris_stream_output_target
*tgt
=
3585 (void *) ice
->state
.so_target
[i
];
3587 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3589 flush
|= iris_flush_bits_for_history(res
);
3590 iris_dirty_for_history(ice
, res
);
3593 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
3594 "make streamout results visible", flush
);
3598 for (int i
= 0; i
< 4; i
++) {
3599 pipe_so_target_reference(&ice
->state
.so_target
[i
],
3600 i
< num_targets
? targets
[i
] : NULL
);
3603 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
3607 for (unsigned i
= 0; i
< 4; i
++,
3608 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
3610 struct iris_stream_output_target
*tgt
= (void *) ice
->state
.so_target
[i
];
3611 unsigned offset
= offsets
[i
];
3614 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
3616 sob
.SOBufferIndex
= i
;
3618 sob
._3DCommandOpcode
= 0;
3619 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ i
;
3625 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3627 /* Note that offsets[i] will either be 0, causing us to zero
3628 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
3629 * "continue appending at the existing offset."
3631 assert(offset
== 0 || offset
== 0xFFFFFFFF);
3633 /* We might be called by Begin (offset = 0), Pause, then Resume
3634 * (offset = 0xFFFFFFFF) before ever drawing (where these commands
3635 * will actually be sent to the GPU). In this case, we don't want
3636 * to append - we still want to do our initial zeroing.
3641 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
3643 sob
.SOBufferIndex
= i
;
3645 sob
._3DCommandOpcode
= 0;
3646 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ i
;
3648 sob
.SurfaceBaseAddress
=
3649 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
3650 sob
.SOBufferEnable
= true;
3651 sob
.StreamOffsetWriteEnable
= true;
3652 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3653 sob
.MOCS
= iris_mocs(res
->bo
, &screen
->isl_dev
);
3655 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
3656 sob
.StreamOffset
= offset
;
3657 sob
.StreamOutputBufferOffsetAddress
=
3658 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
3659 tgt
->offset
.offset
);
3663 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
3667 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
3668 * 3DSTATE_STREAMOUT packets.
3670 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
3671 * hardware to record. We can create it entirely based on the shader, with
3672 * no dynamic state dependencies.
3674 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
3675 * state-based settings. We capture the shader-related ones here, and merge
3676 * the rest in at draw time.
3679 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
3680 const struct brw_vue_map
*vue_map
)
3682 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3683 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3684 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3685 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3687 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3689 memset(so_decl
, 0, sizeof(so_decl
));
3691 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3692 * command feels strange -- each dword pair contains a SO_DECL per stream.
3694 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
3695 const struct pipe_stream_output
*output
= &info
->output
[i
];
3696 const int buffer
= output
->output_buffer
;
3697 const int varying
= output
->register_index
;
3698 const unsigned stream_id
= output
->stream
;
3699 assert(stream_id
< MAX_VERTEX_STREAMS
);
3701 buffer_mask
[stream_id
] |= 1 << buffer
;
3703 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3705 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3706 * array. Instead, it simply increments DstOffset for the following
3707 * input by the number of components that should be skipped.
3709 * Our hardware is unusual in that it requires us to program SO_DECLs
3710 * for fake "hole" components, rather than simply taking the offset
3711 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3712 * program as many size = 4 holes as we can, then a final hole to
3713 * accommodate the final 1, 2, or 3 remaining.
3715 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
3717 while (skip_components
> 0) {
3718 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3720 .OutputBufferSlot
= output
->output_buffer
,
3721 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3723 skip_components
-= 4;
3726 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
3728 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3729 .OutputBufferSlot
= output
->output_buffer
,
3730 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3732 ((1 << output
->num_components
) - 1) << output
->start_component
,
3735 if (decls
[stream_id
] > max_decls
)
3736 max_decls
= decls
[stream_id
];
3739 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
3740 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
3741 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
3743 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
3744 int urb_entry_read_offset
= 0;
3745 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3746 urb_entry_read_offset
;
3748 /* We always read the whole vertex. This could be reduced at some
3749 * point by reading less and offsetting the register index in the
3752 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3753 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3754 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3755 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3756 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3757 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3758 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3759 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3761 /* Set buffer pitches; 0 means unbound. */
3762 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
3763 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
3764 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
3765 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
3768 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
3769 list
.DWordLength
= 3 + 2 * max_decls
- 2;
3770 list
.StreamtoBufferSelects0
= buffer_mask
[0];
3771 list
.StreamtoBufferSelects1
= buffer_mask
[1];
3772 list
.StreamtoBufferSelects2
= buffer_mask
[2];
3773 list
.StreamtoBufferSelects3
= buffer_mask
[3];
3774 list
.NumEntries0
= decls
[0];
3775 list
.NumEntries1
= decls
[1];
3776 list
.NumEntries2
= decls
[2];
3777 list
.NumEntries3
= decls
[3];
3780 for (int i
= 0; i
< max_decls
; i
++) {
3781 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
3782 entry
.Stream0Decl
= so_decl
[0][i
];
3783 entry
.Stream1Decl
= so_decl
[1][i
];
3784 entry
.Stream2Decl
= so_decl
[2][i
];
3785 entry
.Stream3Decl
= so_decl
[3][i
];
3793 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
3794 const struct brw_vue_map
*last_vue_map
,
3795 bool two_sided_color
,
3796 unsigned *out_offset
,
3797 unsigned *out_length
)
3799 /* The compiler computes the first URB slot without considering COL/BFC
3800 * swizzling (because it doesn't know whether it's enabled), so we need
3801 * to do that here too. This may result in a smaller offset, which
3804 const unsigned first_slot
=
3805 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
3807 /* This becomes the URB read offset (counted in pairs of slots). */
3808 assert(first_slot
% 2 == 0);
3809 *out_offset
= first_slot
/ 2;
3811 /* We need to adjust the inputs read to account for front/back color
3812 * swizzling, as it can make the URB length longer.
3814 for (int c
= 0; c
<= 1; c
++) {
3815 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
3816 /* If two sided color is enabled, the fragment shader's gl_Color
3817 * (COL0) input comes from either the gl_FrontColor (COL0) or
3818 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
3820 if (two_sided_color
)
3821 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3823 /* If front color isn't written, we opt to give them back color
3824 * instead of an undefined value. Switch from COL to BFC.
3826 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
3827 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
3828 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3833 /* Compute the minimum URB Read Length necessary for the FS inputs.
3835 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
3836 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
3838 * "This field should be set to the minimum length required to read the
3839 * maximum source attribute. The maximum source attribute is indicated
3840 * by the maximum value of the enabled Attribute # Source Attribute if
3841 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
3842 * enable is not set.
3843 * read_length = ceiling((max_source_attr + 1) / 2)
3845 * [errata] Corruption/Hang possible if length programmed larger than
3848 * Similar text exists for Ivy Bridge.
3850 * We find the last URB slot that's actually read by the FS.
3852 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
3853 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
3854 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
3857 /* The URB read length is the difference of the two, counted in pairs. */
3858 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
3862 iris_emit_sbe_swiz(struct iris_batch
*batch
,
3863 const struct iris_context
*ice
,
3864 unsigned urb_read_offset
,
3865 unsigned sprite_coord_enables
)
3867 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
3868 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3869 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3870 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
3871 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3873 /* XXX: this should be generated when putting programs in place */
3875 for (uint8_t idx
= 0; idx
< wm_prog_data
->urb_setup_attribs_count
; idx
++) {
3876 const uint8_t fs_attr
= wm_prog_data
->urb_setup_attribs
[idx
];
3877 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
3878 if (input_index
< 0 || input_index
>= 16)
3881 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
3882 &attr_overrides
[input_index
];
3883 int slot
= vue_map
->varying_to_slot
[fs_attr
];
3885 /* Viewport and Layer are stored in the VUE header. We need to override
3886 * them to zero if earlier stages didn't write them, as GL requires that
3887 * they read back as zero when not explicitly set.
3890 case VARYING_SLOT_VIEWPORT
:
3891 case VARYING_SLOT_LAYER
:
3892 attr
->ComponentOverrideX
= true;
3893 attr
->ComponentOverrideW
= true;
3894 attr
->ConstantSource
= CONST_0000
;
3896 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
3897 attr
->ComponentOverrideY
= true;
3898 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
3899 attr
->ComponentOverrideZ
= true;
3902 case VARYING_SLOT_PRIMITIVE_ID
:
3903 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
3905 attr
->ComponentOverrideX
= true;
3906 attr
->ComponentOverrideY
= true;
3907 attr
->ComponentOverrideZ
= true;
3908 attr
->ComponentOverrideW
= true;
3909 attr
->ConstantSource
= PRIM_ID
;
3917 if (sprite_coord_enables
& (1 << input_index
))
3920 /* If there was only a back color written but not front, use back
3921 * as the color instead of undefined.
3923 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
3924 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
3925 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
3926 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
3928 /* Not written by the previous stage - undefined. */
3930 attr
->ComponentOverrideX
= true;
3931 attr
->ComponentOverrideY
= true;
3932 attr
->ComponentOverrideZ
= true;
3933 attr
->ComponentOverrideW
= true;
3934 attr
->ConstantSource
= CONST_0001_FLOAT
;
3938 /* Compute the location of the attribute relative to the read offset,
3939 * which is counted in 256-bit increments (two 128-bit VUE slots).
3941 const int source_attr
= slot
- 2 * urb_read_offset
;
3942 assert(source_attr
>= 0 && source_attr
<= 32);
3943 attr
->SourceAttribute
= source_attr
;
3945 /* If we are doing two-sided color, and the VUE slot following this one
3946 * represents a back-facing color, then we need to instruct the SF unit
3947 * to do back-facing swizzling.
3949 if (cso_rast
->light_twoside
&&
3950 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3951 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3952 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3953 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3954 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3957 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3958 for (int i
= 0; i
< 16; i
++)
3959 sbes
.Attribute
[i
] = attr_overrides
[i
];
3964 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3965 const struct iris_rasterizer_state
*cso
)
3967 unsigned overrides
= 0;
3969 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
3970 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
3972 for (int i
= 0; i
< 8; i
++) {
3973 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
3974 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
3975 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
3982 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
3984 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3985 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3986 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3987 const struct shader_info
*fs_info
=
3988 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
3990 unsigned urb_read_offset
, urb_read_length
;
3991 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
3992 ice
->shaders
.last_vue_map
,
3993 cso_rast
->light_twoside
,
3994 &urb_read_offset
, &urb_read_length
);
3996 unsigned sprite_coord_overrides
=
3997 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3999 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
4000 sbe
.AttributeSwizzleEnable
= true;
4001 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
4002 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
4003 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
4004 sbe
.VertexURBEntryReadLength
= urb_read_length
;
4005 sbe
.ForceVertexURBEntryReadOffset
= true;
4006 sbe
.ForceVertexURBEntryReadLength
= true;
4007 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
4008 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
4010 for (int i
= 0; i
< 32; i
++) {
4011 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
4016 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
4019 /* ------------------------------------------------------------------- */
4022 * Populate VS program key fields based on the current state.
4025 iris_populate_vs_key(const struct iris_context
*ice
,
4026 const struct shader_info
*info
,
4027 gl_shader_stage last_stage
,
4028 struct iris_vs_prog_key
*key
)
4030 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4032 if (info
->clip_distance_array_size
== 0 &&
4033 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
4034 last_stage
== MESA_SHADER_VERTEX
)
4035 key
->vue
.nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
4039 * Populate TCS program key fields based on the current state.
4042 iris_populate_tcs_key(const struct iris_context
*ice
,
4043 struct iris_tcs_prog_key
*key
)
4048 * Populate TES program key fields based on the current state.
4051 iris_populate_tes_key(const struct iris_context
*ice
,
4052 const struct shader_info
*info
,
4053 gl_shader_stage last_stage
,
4054 struct iris_tes_prog_key
*key
)
4056 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4058 if (info
->clip_distance_array_size
== 0 &&
4059 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
4060 last_stage
== MESA_SHADER_TESS_EVAL
)
4061 key
->vue
.nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
4065 * Populate GS program key fields based on the current state.
4068 iris_populate_gs_key(const struct iris_context
*ice
,
4069 const struct shader_info
*info
,
4070 gl_shader_stage last_stage
,
4071 struct iris_gs_prog_key
*key
)
4073 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4075 if (info
->clip_distance_array_size
== 0 &&
4076 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
4077 last_stage
== MESA_SHADER_GEOMETRY
)
4078 key
->vue
.nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
4082 * Populate FS program key fields based on the current state.
4085 iris_populate_fs_key(const struct iris_context
*ice
,
4086 const struct shader_info
*info
,
4087 struct iris_fs_prog_key
*key
)
4089 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
4090 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
4091 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
4092 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
4093 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
4095 key
->nr_color_regions
= fb
->nr_cbufs
;
4097 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
4099 key
->alpha_to_coverage
= blend
->alpha_to_coverage
;
4101 key
->alpha_test_replicate_alpha
= fb
->nr_cbufs
> 1 && zsa
->alpha
.enabled
;
4103 key
->flat_shade
= rast
->flatshade
&&
4104 (info
->inputs_read
& (VARYING_BIT_COL0
| VARYING_BIT_COL1
));
4106 key
->persample_interp
= rast
->force_persample_interp
;
4107 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
4109 key
->coherent_fb_fetch
= GEN_GEN
>= 9;
4111 key
->force_dual_color_blend
=
4112 screen
->driconf
.dual_color_blend_by_location
&&
4113 (blend
->blend_enables
& 1) && blend
->dual_color_blending
;
4115 /* TODO: Respect glHint for key->high_quality_derivatives */
4119 iris_populate_cs_key(const struct iris_context
*ice
,
4120 struct iris_cs_prog_key
*key
)
4125 KSP(const struct iris_compiled_shader
*shader
)
4127 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
4128 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
4131 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
4132 pkt.KernelStartPointer = KSP(shader); \
4133 pkt.BindingTableEntryCount = shader->bt.size_bytes / 4; \
4134 pkt.FloatingPointMode = prog_data->use_alt_mode; \
4136 pkt.DispatchGRFStartRegisterForURBData = \
4137 prog_data->dispatch_grf_start_reg; \
4138 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
4139 pkt.prefix##URBEntryReadOffset = 0; \
4141 pkt.StatisticsEnable = true; \
4142 pkt.Enable = true; \
4144 if (prog_data->total_scratch) { \
4145 struct iris_bo *bo = \
4146 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
4147 uint32_t scratch_addr = bo->gtt_offset; \
4148 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
4149 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
4153 * Encode most of 3DSTATE_VS based on the compiled shader.
4156 iris_store_vs_state(struct iris_context
*ice
,
4157 const struct gen_device_info
*devinfo
,
4158 struct iris_compiled_shader
*shader
)
4160 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4161 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4163 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
4164 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
4165 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
4166 vs
.SIMD8DispatchEnable
= true;
4167 vs
.UserClipDistanceCullTestEnableBitmask
=
4168 vue_prog_data
->cull_distance_mask
;
4173 * Encode most of 3DSTATE_HS based on the compiled shader.
4176 iris_store_tcs_state(struct iris_context
*ice
,
4177 const struct gen_device_info
*devinfo
,
4178 struct iris_compiled_shader
*shader
)
4180 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4181 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4182 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
4184 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
4185 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
4188 /* GEN:BUG:1604578095:
4190 * Hang occurs when the number of max threads is less than 2 times
4191 * the number of instance count. The number of max threads must be
4192 * more than 2 times the number of instance count.
4194 assert((devinfo
->max_tcs_threads
/ 2) > tcs_prog_data
->instances
);
4197 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
4198 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
4199 hs
.IncludeVertexHandles
= true;
4202 hs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
4203 hs
.IncludePrimitiveID
= tcs_prog_data
->include_primitive_id
;
4209 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
4212 iris_store_tes_state(struct iris_context
*ice
,
4213 const struct gen_device_info
*devinfo
,
4214 struct iris_compiled_shader
*shader
)
4216 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4217 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4218 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
4220 uint32_t *te_state
= (void *) shader
->derived_data
;
4221 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
4223 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
4224 te
.Partitioning
= tes_prog_data
->partitioning
;
4225 te
.OutputTopology
= tes_prog_data
->output_topology
;
4226 te
.TEDomain
= tes_prog_data
->domain
;
4228 te
.MaximumTessellationFactorOdd
= 63.0;
4229 te
.MaximumTessellationFactorNotOdd
= 64.0;
4232 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
4233 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
4235 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
4236 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
4237 ds
.ComputeWCoordinateEnable
=
4238 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
4240 ds
.UserClipDistanceCullTestEnableBitmask
=
4241 vue_prog_data
->cull_distance_mask
;
4247 * Encode most of 3DSTATE_GS based on the compiled shader.
4250 iris_store_gs_state(struct iris_context
*ice
,
4251 const struct gen_device_info
*devinfo
,
4252 struct iris_compiled_shader
*shader
)
4254 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4255 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4256 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
4258 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
4259 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
4261 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
4262 gs
.OutputTopology
= gs_prog_data
->output_topology
;
4263 gs
.ControlDataHeaderSize
=
4264 gs_prog_data
->control_data_header_size_hwords
;
4265 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
4266 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
4267 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
4268 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
4269 gs
.ReorderMode
= TRAILING
;
4270 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
4271 gs
.MaximumNumberofThreads
=
4272 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
4273 : (devinfo
->max_gs_threads
- 1);
4275 if (gs_prog_data
->static_vertex_count
!= -1) {
4276 gs
.StaticOutput
= true;
4277 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
4279 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
4281 gs
.UserClipDistanceCullTestEnableBitmask
=
4282 vue_prog_data
->cull_distance_mask
;
4284 const int urb_entry_write_offset
= 1;
4285 const uint32_t urb_entry_output_length
=
4286 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
4287 urb_entry_write_offset
;
4289 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
4290 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
4295 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
4298 iris_store_fs_state(struct iris_context
*ice
,
4299 const struct gen_device_info
*devinfo
,
4300 struct iris_compiled_shader
*shader
)
4302 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4303 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
4305 uint32_t *ps_state
= (void *) shader
->derived_data
;
4306 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
4308 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
4309 ps
.VectorMaskEnable
= true;
4310 ps
.BindingTableEntryCount
= shader
->bt
.size_bytes
/ 4;
4311 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
4312 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
4314 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
4316 /* From the documentation for this packet:
4317 * "If the PS kernel does not need the Position XY Offsets to
4318 * compute a Position Value, then this field should be programmed
4319 * to POSOFFSET_NONE."
4321 * "SW Recommendation: If the PS kernel needs the Position Offsets
4322 * to compute a Position XY value, this field should match Position
4323 * ZW Interpolation Mode to ensure a consistent position.xyzw
4326 * We only require XY sample offsets. So, this recommendation doesn't
4327 * look useful at the moment. We might need this in future.
4329 ps
.PositionXYOffsetSelect
=
4330 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
4332 if (prog_data
->total_scratch
) {
4333 struct iris_bo
*bo
=
4334 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
4335 MESA_SHADER_FRAGMENT
);
4336 uint32_t scratch_addr
= bo
->gtt_offset
;
4337 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
4338 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
4342 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
4343 psx
.PixelShaderValid
= true;
4344 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
4345 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
4346 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
4347 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
4348 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
4349 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
4350 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
4353 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
4354 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
4360 * Compute the size of the derived data (shader command packets).
4362 * This must match the data written by the iris_store_xs_state() functions.
4365 iris_store_cs_state(struct iris_context
*ice
,
4366 const struct gen_device_info
*devinfo
,
4367 struct iris_compiled_shader
*shader
)
4369 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4370 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
4371 void *map
= shader
->derived_data
;
4373 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
4374 desc
.KernelStartPointer
= KSP(shader
);
4375 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
4376 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
4377 desc
.SharedLocalMemorySize
=
4378 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
4379 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
4380 desc
.CrossThreadConstantDataReadLength
=
4381 cs_prog_data
->push
.cross_thread
.regs
;
4383 /* TODO: Check if we are missing workarounds and enable mid-thread
4386 * We still have issues with mid-thread preemption (it was already
4387 * disabled by the kernel on gen11, due to missing workarounds). It's
4388 * possible that we are just missing some workarounds, and could enable
4389 * it later, but for now let's disable it to fix a GPU in compute in Car
4390 * Chase (and possibly more).
4392 desc
.ThreadPreemptionDisable
= true;
4398 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
4400 assert(cache_id
<= IRIS_CACHE_BLORP
);
4402 static const unsigned dwords
[] = {
4403 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
4404 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
4405 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
4406 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
4408 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
4409 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
4410 [IRIS_CACHE_BLORP
] = 0,
4413 return sizeof(uint32_t) * dwords
[cache_id
];
4417 * Create any state packets corresponding to the given shader stage
4418 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
4419 * This means that we can look up a program in the in-memory cache and
4420 * get most of the state packet without having to reconstruct it.
4423 iris_store_derived_program_state(struct iris_context
*ice
,
4424 enum iris_program_cache_id cache_id
,
4425 struct iris_compiled_shader
*shader
)
4427 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
4428 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
4432 iris_store_vs_state(ice
, devinfo
, shader
);
4434 case IRIS_CACHE_TCS
:
4435 iris_store_tcs_state(ice
, devinfo
, shader
);
4437 case IRIS_CACHE_TES
:
4438 iris_store_tes_state(ice
, devinfo
, shader
);
4441 iris_store_gs_state(ice
, devinfo
, shader
);
4444 iris_store_fs_state(ice
, devinfo
, shader
);
4447 iris_store_cs_state(ice
, devinfo
, shader
);
4448 case IRIS_CACHE_BLORP
:
4455 /* ------------------------------------------------------------------- */
4457 static const uint32_t push_constant_opcodes
[] = {
4458 [MESA_SHADER_VERTEX
] = 21,
4459 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
4460 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
4461 [MESA_SHADER_GEOMETRY
] = 22,
4462 [MESA_SHADER_FRAGMENT
] = 23,
4463 [MESA_SHADER_COMPUTE
] = 0,
4467 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
4469 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
4471 iris_use_pinned_bo(batch
, state_bo
, false);
4473 return ice
->state
.unbound_tex
.offset
;
4477 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
4479 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
4480 if (!ice
->state
.null_fb
.res
)
4481 return use_null_surface(batch
, ice
);
4483 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
4485 iris_use_pinned_bo(batch
, state_bo
, false);
4487 return ice
->state
.null_fb
.offset
;
4491 surf_state_offset_for_aux(struct iris_resource
*res
,
4493 enum isl_aux_usage aux_usage
)
4495 return SURFACE_STATE_ALIGNMENT
*
4496 util_bitcount(aux_modes
& ((1 << aux_usage
) - 1));
4501 surf_state_update_clear_value(struct iris_batch
*batch
,
4502 struct iris_resource
*res
,
4503 struct iris_state_ref
*state
,
4505 enum isl_aux_usage aux_usage
)
4507 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
4508 struct iris_bo
*state_bo
= iris_resource_bo(state
->res
);
4509 uint64_t real_offset
= state
->offset
+ IRIS_MEMZONE_BINDER_START
;
4510 uint32_t offset_into_bo
= real_offset
- state_bo
->gtt_offset
;
4511 uint32_t clear_offset
= offset_into_bo
+
4512 isl_dev
->ss
.clear_value_offset
+
4513 surf_state_offset_for_aux(res
, aux_modes
, aux_usage
);
4514 uint32_t *color
= res
->aux
.clear_color
.u32
;
4516 assert(isl_dev
->ss
.clear_value_size
== 16);
4518 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
4519 iris_emit_pipe_control_write(batch
, "update fast clear value (Z)",
4520 PIPE_CONTROL_WRITE_IMMEDIATE
,
4521 state_bo
, clear_offset
, color
[0]);
4523 iris_emit_pipe_control_write(batch
, "update fast clear color (RG__)",
4524 PIPE_CONTROL_WRITE_IMMEDIATE
,
4525 state_bo
, clear_offset
,
4526 (uint64_t) color
[0] |
4527 (uint64_t) color
[1] << 32);
4528 iris_emit_pipe_control_write(batch
, "update fast clear color (__BA)",
4529 PIPE_CONTROL_WRITE_IMMEDIATE
,
4530 state_bo
, clear_offset
+ 8,
4531 (uint64_t) color
[2] |
4532 (uint64_t) color
[3] << 32);
4535 iris_emit_pipe_control_flush(batch
,
4536 "update fast clear: state cache invalidate",
4537 PIPE_CONTROL_FLUSH_ENABLE
|
4538 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
4543 update_clear_value(struct iris_context
*ice
,
4544 struct iris_batch
*batch
,
4545 struct iris_resource
*res
,
4546 struct iris_surface_state
*surf_state
,
4547 unsigned all_aux_modes
,
4548 struct isl_view
*view
)
4550 UNUSED
struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
4551 UNUSED
unsigned aux_modes
= all_aux_modes
;
4553 /* We only need to update the clear color in the surface state for gen8 and
4554 * gen9. Newer gens can read it directly from the clear color state buffer.
4557 /* Skip updating the ISL_AUX_USAGE_NONE surface state */
4558 aux_modes
&= ~(1 << ISL_AUX_USAGE_NONE
);
4561 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4563 surf_state_update_clear_value(batch
, res
, &surf_state
->ref
,
4564 all_aux_modes
, aux_usage
);
4567 /* TODO: Could update rather than re-filling */
4568 alloc_surface_states(surf_state
, all_aux_modes
);
4570 void *map
= surf_state
->cpu
;
4573 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4574 fill_surface_state(isl_dev
, map
, res
, &res
->surf
, view
, aux_usage
,
4576 map
+= SURFACE_STATE_ALIGNMENT
;
4579 upload_surface_states(ice
->state
.surface_uploader
, surf_state
);
4584 * Add a surface to the validation list, as well as the buffer containing
4585 * the corresponding SURFACE_STATE.
4587 * Returns the binding table entry (offset to SURFACE_STATE).
4590 use_surface(struct iris_context
*ice
,
4591 struct iris_batch
*batch
,
4592 struct pipe_surface
*p_surf
,
4594 enum isl_aux_usage aux_usage
,
4595 bool is_read_surface
)
4597 struct iris_surface
*surf
= (void *) p_surf
;
4598 struct iris_resource
*res
= (void *) p_surf
->texture
;
4599 uint32_t offset
= 0;
4601 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
4602 if (GEN_GEN
== 8 && is_read_surface
) {
4603 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state_read
.ref
.res
), false);
4605 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.ref
.res
), false);
4609 iris_use_pinned_bo(batch
, res
->aux
.bo
, writeable
);
4610 if (res
->aux
.clear_color_bo
)
4611 iris_use_pinned_bo(batch
, res
->aux
.clear_color_bo
, false);
4613 if (memcmp(&res
->aux
.clear_color
, &surf
->clear_color
,
4614 sizeof(surf
->clear_color
)) != 0) {
4615 update_clear_value(ice
, batch
, res
, &surf
->surface_state
,
4616 res
->aux
.possible_usages
, &surf
->view
);
4618 update_clear_value(ice
, batch
, res
, &surf
->surface_state_read
,
4619 res
->aux
.possible_usages
, &surf
->read_view
);
4621 surf
->clear_color
= res
->aux
.clear_color
;
4625 offset
= (GEN_GEN
== 8 && is_read_surface
)
4626 ? surf
->surface_state_read
.ref
.offset
4627 : surf
->surface_state
.ref
.offset
;
4630 surf_state_offset_for_aux(res
, res
->aux
.possible_usages
, aux_usage
);
4634 use_sampler_view(struct iris_context
*ice
,
4635 struct iris_batch
*batch
,
4636 struct iris_sampler_view
*isv
)
4638 enum isl_aux_usage aux_usage
=
4639 iris_resource_texture_aux_usage(ice
, isv
->res
, isv
->view
.format
);
4641 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
4642 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.ref
.res
), false);
4644 if (isv
->res
->aux
.bo
) {
4645 iris_use_pinned_bo(batch
, isv
->res
->aux
.bo
, false);
4646 if (isv
->res
->aux
.clear_color_bo
)
4647 iris_use_pinned_bo(batch
, isv
->res
->aux
.clear_color_bo
, false);
4648 if (memcmp(&isv
->res
->aux
.clear_color
, &isv
->clear_color
,
4649 sizeof(isv
->clear_color
)) != 0) {
4650 update_clear_value(ice
, batch
, isv
->res
, &isv
->surface_state
,
4651 isv
->res
->aux
.sampler_usages
, &isv
->view
);
4652 isv
->clear_color
= isv
->res
->aux
.clear_color
;
4656 return isv
->surface_state
.ref
.offset
+
4657 surf_state_offset_for_aux(isv
->res
, isv
->res
->aux
.sampler_usages
,
4662 use_ubo_ssbo(struct iris_batch
*batch
,
4663 struct iris_context
*ice
,
4664 struct pipe_shader_buffer
*buf
,
4665 struct iris_state_ref
*surf_state
,
4668 if (!buf
->buffer
|| !surf_state
->res
)
4669 return use_null_surface(batch
, ice
);
4671 iris_use_pinned_bo(batch
, iris_resource_bo(buf
->buffer
), writable
);
4672 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
4674 return surf_state
->offset
;
4678 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
4679 struct iris_shader_state
*shs
, int i
)
4681 struct iris_image_view
*iv
= &shs
->image
[i
];
4682 struct iris_resource
*res
= (void *) iv
->base
.resource
;
4685 return use_null_surface(batch
, ice
);
4687 bool write
= iv
->base
.shader_access
& PIPE_IMAGE_ACCESS_WRITE
;
4689 iris_use_pinned_bo(batch
, res
->bo
, write
);
4690 iris_use_pinned_bo(batch
, iris_resource_bo(iv
->surface_state
.ref
.res
), false);
4693 iris_use_pinned_bo(batch
, res
->aux
.bo
, write
);
4695 return iv
->surface_state
.ref
.offset
;
4698 #define push_bt_entry(addr) \
4699 assert(addr >= binder_addr); \
4700 assert(s < shader->bt.size_bytes / sizeof(uint32_t)); \
4701 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
4703 #define bt_assert(section) \
4704 if (!pin_only && shader->bt.used_mask[section] != 0) \
4705 assert(shader->bt.offsets[section] == s);
4708 * Populate the binding table for a given shader stage.
4710 * This fills out the table of pointers to surfaces required by the shader,
4711 * and also adds those buffers to the validation list so the kernel can make
4712 * resident before running our batch.
4715 iris_populate_binding_table(struct iris_context
*ice
,
4716 struct iris_batch
*batch
,
4717 gl_shader_stage stage
,
4720 const struct iris_binder
*binder
= &ice
->state
.binder
;
4721 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
4722 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4726 struct iris_binding_table
*bt
= &shader
->bt
;
4727 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4728 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4729 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
4731 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
4734 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
4736 /* TCS passthrough doesn't need a binding table. */
4737 assert(stage
== MESA_SHADER_TESS_CTRL
);
4741 if (stage
== MESA_SHADER_COMPUTE
&&
4742 shader
->bt
.used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
]) {
4743 /* surface for gl_NumWorkGroups */
4744 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
4745 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
4746 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
4747 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
4748 push_bt_entry(grid_state
->offset
);
4751 if (stage
== MESA_SHADER_FRAGMENT
) {
4752 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4753 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
4754 if (cso_fb
->nr_cbufs
) {
4755 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
4757 if (cso_fb
->cbufs
[i
]) {
4758 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
], true,
4759 ice
->state
.draw_aux_usage
[i
], false);
4761 addr
= use_null_fb_surface(batch
, ice
);
4763 push_bt_entry(addr
);
4765 } else if (GEN_GEN
< 11) {
4766 uint32_t addr
= use_null_fb_surface(batch
, ice
);
4767 push_bt_entry(addr
);
4771 #define foreach_surface_used(index, group) \
4773 for (int index = 0; index < bt->sizes[group]; index++) \
4774 if (iris_group_index_to_bti(bt, group, index) != \
4775 IRIS_SURFACE_NOT_USED)
4777 foreach_surface_used(i
, IRIS_SURFACE_GROUP_RENDER_TARGET_READ
) {
4778 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4780 if (cso_fb
->cbufs
[i
]) {
4781 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
],
4782 true, ice
->state
.draw_aux_usage
[i
], true);
4783 push_bt_entry(addr
);
4787 foreach_surface_used(i
, IRIS_SURFACE_GROUP_TEXTURE
) {
4788 struct iris_sampler_view
*view
= shs
->textures
[i
];
4789 uint32_t addr
= view
? use_sampler_view(ice
, batch
, view
)
4790 : use_null_surface(batch
, ice
);
4791 push_bt_entry(addr
);
4794 foreach_surface_used(i
, IRIS_SURFACE_GROUP_IMAGE
) {
4795 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
4796 push_bt_entry(addr
);
4799 foreach_surface_used(i
, IRIS_SURFACE_GROUP_UBO
) {
4802 if (i
== bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] - 1) {
4803 if (ish
->const_data
) {
4804 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data
), false);
4805 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data_state
.res
),
4807 addr
= ish
->const_data_state
.offset
;
4809 /* This can only happen with INTEL_DISABLE_COMPACT_BINDING_TABLE=1. */
4810 addr
= use_null_surface(batch
, ice
);
4813 addr
= use_ubo_ssbo(batch
, ice
, &shs
->constbuf
[i
],
4814 &shs
->constbuf_surf_state
[i
], false);
4817 push_bt_entry(addr
);
4820 foreach_surface_used(i
, IRIS_SURFACE_GROUP_SSBO
) {
4822 use_ubo_ssbo(batch
, ice
, &shs
->ssbo
[i
], &shs
->ssbo_surf_state
[i
],
4823 shs
->writable_ssbos
& (1u << i
));
4824 push_bt_entry(addr
);
4828 /* XXX: YUV surfaces not implemented yet */
4829 bt_assert(plane_start
[1], ...);
4830 bt_assert(plane_start
[2], ...);
4835 iris_use_optional_res(struct iris_batch
*batch
,
4836 struct pipe_resource
*res
,
4840 struct iris_bo
*bo
= iris_resource_bo(res
);
4841 iris_use_pinned_bo(batch
, bo
, writeable
);
4846 pin_depth_and_stencil_buffers(struct iris_batch
*batch
,
4847 struct pipe_surface
*zsbuf
,
4848 struct iris_depth_stencil_alpha_state
*cso_zsa
)
4853 struct iris_resource
*zres
, *sres
;
4854 iris_get_depth_stencil_resources(zsbuf
->texture
, &zres
, &sres
);
4857 iris_use_pinned_bo(batch
, zres
->bo
, cso_zsa
->depth_writes_enabled
);
4859 iris_use_pinned_bo(batch
, zres
->aux
.bo
,
4860 cso_zsa
->depth_writes_enabled
);
4865 iris_use_pinned_bo(batch
, sres
->bo
, cso_zsa
->stencil_writes_enabled
);
4869 /* ------------------------------------------------------------------- */
4872 * Pin any BOs which were installed by a previous batch, and restored
4873 * via the hardware logical context mechanism.
4875 * We don't need to re-emit all state every batch - the hardware context
4876 * mechanism will save and restore it for us. This includes pointers to
4877 * various BOs...which won't exist unless we ask the kernel to pin them
4878 * by adding them to the validation list.
4880 * We can skip buffers if we've re-emitted those packets, as we're
4881 * overwriting those stale pointers with new ones, and don't actually
4882 * refer to the old BOs.
4885 iris_restore_render_saved_bos(struct iris_context
*ice
,
4886 struct iris_batch
*batch
,
4887 const struct pipe_draw_info
*draw
)
4889 struct iris_genx_state
*genx
= ice
->state
.genx
;
4891 const uint64_t clean
= ~ice
->state
.dirty
;
4893 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
4894 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
4897 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4898 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
4901 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
4902 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
4905 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4906 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
4909 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
4910 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
4913 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
4914 for (int i
= 0; i
< 4; i
++) {
4915 struct iris_stream_output_target
*tgt
=
4916 (void *) ice
->state
.so_target
[i
];
4918 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4920 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4926 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4927 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4930 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4931 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4936 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4938 for (int i
= 0; i
< 4; i
++) {
4939 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4941 if (range
->length
== 0)
4944 /* Range block is a binding table index, map back to UBO index. */
4945 unsigned block_index
= iris_bti_to_group_index(
4946 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
4947 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
4949 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4950 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4953 iris_use_pinned_bo(batch
, res
->bo
, false);
4955 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4959 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4960 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4961 /* Re-pin any buffers referred to by the binding table. */
4962 iris_populate_binding_table(ice
, batch
, stage
, true);
4966 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4967 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4968 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4970 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4973 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4974 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
4975 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4978 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4979 iris_use_pinned_bo(batch
, bo
, false);
4981 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4983 if (prog_data
->total_scratch
> 0) {
4984 struct iris_bo
*bo
=
4985 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4986 iris_use_pinned_bo(batch
, bo
, true);
4992 if ((clean
& IRIS_DIRTY_DEPTH_BUFFER
) &&
4993 (clean
& IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
4994 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4995 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
4998 iris_use_optional_res(batch
, ice
->state
.last_res
.index_buffer
, false);
5000 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
5001 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
5003 const int i
= u_bit_scan64(&bound
);
5004 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
5005 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
5011 iris_restore_compute_saved_bos(struct iris_context
*ice
,
5012 struct iris_batch
*batch
,
5013 const struct pipe_grid_info
*grid
)
5015 const uint64_t clean
= ~ice
->state
.dirty
;
5017 const int stage
= MESA_SHADER_COMPUTE
;
5018 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5020 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
5021 /* Re-pin any buffers referred to by the binding table. */
5022 iris_populate_binding_table(ice
, batch
, stage
, true);
5025 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
5027 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
5029 if ((clean
& IRIS_DIRTY_SAMPLER_STATES_CS
) &&
5030 (clean
& IRIS_DIRTY_BINDINGS_CS
) &&
5031 (clean
& IRIS_DIRTY_CONSTANTS_CS
) &&
5032 (clean
& IRIS_DIRTY_CS
)) {
5033 iris_use_optional_res(batch
, ice
->state
.last_res
.cs_desc
, false);
5036 if (clean
& IRIS_DIRTY_CS
) {
5037 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5040 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
5041 iris_use_pinned_bo(batch
, bo
, false);
5043 struct iris_bo
*curbe_bo
=
5044 iris_resource_bo(ice
->state
.last_res
.cs_thread_ids
);
5045 iris_use_pinned_bo(batch
, curbe_bo
, false);
5047 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5049 if (prog_data
->total_scratch
> 0) {
5050 struct iris_bo
*bo
=
5051 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
5052 iris_use_pinned_bo(batch
, bo
, true);
5059 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
5062 iris_update_surface_base_address(struct iris_batch
*batch
,
5063 struct iris_binder
*binder
)
5065 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
5068 uint32_t mocs
= batch
->screen
->isl_dev
.mocs
.internal
;
5070 flush_before_state_base_change(batch
);
5073 /* GEN:BUG:1607854226:
5075 * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
5076 * mode by putting the pipeline temporarily in 3D mode..
5078 if (batch
->name
== IRIS_BATCH_COMPUTE
)
5079 emit_pipeline_select(batch
, _3D
);
5082 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
5083 sba
.SurfaceStateBaseAddressModifyEnable
= true;
5084 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
5086 /* The hardware appears to pay attention to the MOCS fields even
5087 * if you don't set the "Address Modify Enable" bit for the base.
5089 sba
.GeneralStateMOCS
= mocs
;
5090 sba
.StatelessDataPortAccessMOCS
= mocs
;
5091 sba
.DynamicStateMOCS
= mocs
;
5092 sba
.IndirectObjectMOCS
= mocs
;
5093 sba
.InstructionMOCS
= mocs
;
5094 sba
.SurfaceStateMOCS
= mocs
;
5096 sba
.BindlessSurfaceStateMOCS
= mocs
;
5101 /* GEN:BUG:1607854226:
5103 * Put the pipeline back into compute mode.
5105 if (batch
->name
== IRIS_BATCH_COMPUTE
)
5106 emit_pipeline_select(batch
, GPGPU
);
5109 flush_after_state_base_change(batch
);
5111 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
5115 iris_viewport_zmin_zmax(const struct pipe_viewport_state
*vp
, bool halfz
,
5116 bool window_space_position
, float *zmin
, float *zmax
)
5118 if (window_space_position
) {
5123 util_viewport_zmin_zmax(vp
, halfz
, zmin
, zmax
);
5128 genX(invalidate_aux_map_state
)(struct iris_batch
*batch
)
5130 struct iris_screen
*screen
= batch
->screen
;
5131 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
5134 uint32_t aux_map_state_num
= gen_aux_map_get_state_num(aux_map_ctx
);
5135 if (batch
->last_aux_map_state
!= aux_map_state_num
) {
5136 /* HSD 1209978178: docs say that before programming the aux table:
5138 * "Driver must ensure that the engine is IDLE but ensure it doesn't
5139 * add extra flushes in the case it knows that the engine is already
5142 * An end of pipe sync is needed here, otherwise we see GPU hangs in
5143 * dEQP-GLES31.functional.copy_image.* tests.
5145 iris_emit_end_of_pipe_sync(batch
, "Invalidate aux map table",
5146 PIPE_CONTROL_CS_STALL
);
5148 /* If the aux-map state number increased, then we need to rewrite the
5149 * register. Rewriting the register is used to both set the aux-map
5150 * translation table address, and also to invalidate any previously
5151 * cached translations.
5153 iris_load_register_imm32(batch
, GENX(GFX_CCS_AUX_INV_num
), 1);
5154 batch
->last_aux_map_state
= aux_map_state_num
;
5159 init_aux_map_state(struct iris_batch
*batch
)
5161 struct iris_screen
*screen
= batch
->screen
;
5162 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
5166 uint64_t base_addr
= gen_aux_map_get_base(aux_map_ctx
);
5167 assert(base_addr
!= 0 && align64(base_addr
, 32 * 1024) == base_addr
);
5168 iris_load_register_imm64(batch
, GENX(GFX_AUX_TABLE_BASE_ADDR_num
),
5175 struct iris_address addr
;
5179 uint32_t max_length
;
5183 setup_constant_buffers(struct iris_context
*ice
,
5184 struct iris_batch
*batch
,
5186 struct push_bos
*push_bos
)
5188 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5189 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5190 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
5192 uint32_t push_range_sum
= 0;
5195 for (int i
= 0; i
< 4; i
++) {
5196 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
5198 if (range
->length
== 0)
5201 push_range_sum
+= range
->length
;
5203 if (range
->length
> push_bos
->max_length
)
5204 push_bos
->max_length
= range
->length
;
5206 /* Range block is a binding table index, map back to UBO index. */
5207 unsigned block_index
= iris_bti_to_group_index(
5208 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
5209 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
5211 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
5212 struct iris_resource
*res
= (void *) cbuf
->buffer
;
5214 assert(cbuf
->buffer_offset
% 32 == 0);
5216 push_bos
->buffers
[n
].length
= range
->length
;
5217 push_bos
->buffers
[n
].addr
=
5218 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->buffer_offset
)
5219 : ro_bo(batch
->screen
->workaround_bo
, 0);
5223 /* From the 3DSTATE_CONSTANT_XS and 3DSTATE_CONSTANT_ALL programming notes:
5225 * "The sum of all four read length fields must be less than or
5226 * equal to the size of 64."
5228 assert(push_range_sum
<= 64);
5230 push_bos
->buffer_count
= n
;
5234 emit_push_constant_packets(struct iris_context
*ice
,
5235 struct iris_batch
*batch
,
5237 const struct push_bos
*push_bos
)
5239 UNUSED
struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
5240 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5241 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
5243 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
5244 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
5246 pkt
.MOCS
= isl_dev
->mocs
.internal
;
5249 /* The Skylake PRM contains the following restriction:
5251 * "The driver must ensure The following case does not occur
5252 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
5253 * buffer 3 read length equal to zero committed followed by a
5254 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
5257 * To avoid this, we program the buffers in the highest slots.
5258 * This way, slot 0 is only used if slot 3 is also used.
5260 int n
= push_bos
->buffer_count
;
5262 const unsigned shift
= 4 - n
;
5263 for (int i
= 0; i
< n
; i
++) {
5264 pkt
.ConstantBody
.ReadLength
[i
+ shift
] =
5265 push_bos
->buffers
[i
].length
;
5266 pkt
.ConstantBody
.Buffer
[i
+ shift
] = push_bos
->buffers
[i
].addr
;
5274 emit_push_constant_packet_all(struct iris_context
*ice
,
5275 struct iris_batch
*batch
,
5276 uint32_t shader_mask
,
5277 const struct push_bos
*push_bos
)
5279 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
5282 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_ALL
), pc
) {
5283 pc
.ShaderUpdateEnable
= shader_mask
;
5288 const uint32_t n
= push_bos
->buffer_count
;
5289 const uint32_t max_pointers
= 4;
5290 const uint32_t num_dwords
= 2 + 2 * n
;
5291 uint32_t const_all
[2 + 2 * max_pointers
];
5292 uint32_t *dw
= &const_all
[0];
5294 assert(n
<= max_pointers
);
5295 iris_pack_command(GENX(3DSTATE_CONSTANT_ALL
), dw
, all
) {
5296 all
.DWordLength
= num_dwords
- 2;
5297 all
.MOCS
= isl_dev
->mocs
.internal
;
5298 all
.ShaderUpdateEnable
= shader_mask
;
5299 all
.PointerBufferMask
= (1 << n
) - 1;
5303 for (int i
= 0; i
< n
; i
++) {
5304 _iris_pack_state(batch
, GENX(3DSTATE_CONSTANT_ALL_DATA
),
5306 data
.PointerToConstantBuffer
= push_bos
->buffers
[i
].addr
;
5307 data
.ConstantBufferReadLength
= push_bos
->buffers
[i
].length
;
5310 iris_batch_emit(batch
, const_all
, sizeof(uint32_t) * num_dwords
);
5315 iris_upload_dirty_render_state(struct iris_context
*ice
,
5316 struct iris_batch
*batch
,
5317 const struct pipe_draw_info
*draw
)
5319 const uint64_t dirty
= ice
->state
.dirty
;
5321 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
5324 struct iris_genx_state
*genx
= ice
->state
.genx
;
5325 struct iris_binder
*binder
= &ice
->state
.binder
;
5326 struct brw_wm_prog_data
*wm_prog_data
= (void *)
5327 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
5329 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
5330 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5331 uint32_t cc_vp_address
;
5333 /* XXX: could avoid streaming for depth_clip [0,1] case. */
5334 uint32_t *cc_vp_map
=
5335 stream_state(batch
, ice
->state
.dynamic_uploader
,
5336 &ice
->state
.last_res
.cc_vp
,
5337 4 * ice
->state
.num_viewports
*
5338 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
5339 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
5341 iris_viewport_zmin_zmax(&ice
->state
.viewports
[i
], cso_rast
->clip_halfz
,
5342 ice
->state
.window_space_position
,
5344 if (cso_rast
->depth_clip_near
)
5346 if (cso_rast
->depth_clip_far
)
5349 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
5350 ccv
.MinimumDepth
= zmin
;
5351 ccv
.MaximumDepth
= zmax
;
5354 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
5357 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
5358 ptr
.CCViewportPointer
= cc_vp_address
;
5362 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
5363 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5364 uint32_t sf_cl_vp_address
;
5366 stream_state(batch
, ice
->state
.dynamic_uploader
,
5367 &ice
->state
.last_res
.sf_cl_vp
,
5368 4 * ice
->state
.num_viewports
*
5369 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
5371 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
5372 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
5373 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
5375 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
5376 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
5377 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
5378 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
5380 gen_calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
5381 state
->scale
[0], state
->scale
[1],
5382 state
->translate
[0], state
->translate
[1],
5383 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
5385 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
5386 vp
.ViewportMatrixElementm00
= state
->scale
[0];
5387 vp
.ViewportMatrixElementm11
= state
->scale
[1];
5388 vp
.ViewportMatrixElementm22
= state
->scale
[2];
5389 vp
.ViewportMatrixElementm30
= state
->translate
[0];
5390 vp
.ViewportMatrixElementm31
= state
->translate
[1];
5391 vp
.ViewportMatrixElementm32
= state
->translate
[2];
5392 vp
.XMinClipGuardband
= gb_xmin
;
5393 vp
.XMaxClipGuardband
= gb_xmax
;
5394 vp
.YMinClipGuardband
= gb_ymin
;
5395 vp
.YMaxClipGuardband
= gb_ymax
;
5396 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
5397 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
5398 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
5399 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
5402 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
5405 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
5406 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
5410 if (dirty
& IRIS_DIRTY_URB
) {
5413 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
5414 if (!ice
->shaders
.prog
[i
]) {
5417 struct brw_vue_prog_data
*vue_prog_data
=
5418 (void *) ice
->shaders
.prog
[i
]->prog_data
;
5419 size
[i
] = vue_prog_data
->urb_entry_size
;
5421 assert(size
[i
] != 0);
5424 unsigned entries
[4], start
[4];
5425 gen_get_urb_config(&batch
->screen
->devinfo
,
5426 batch
->screen
->l3_config_3d
,
5427 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
5428 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
5429 size
, entries
, start
,
5430 &ice
->state
.urb_deref_block_size
);
5432 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
5433 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
5434 urb
._3DCommandSubOpcode
+= i
;
5435 urb
.VSURBStartingAddress
= start
[i
];
5436 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
5437 urb
.VSNumberofURBEntries
= entries
[i
];
5442 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
5443 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
5444 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5445 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
5446 const int header_dwords
= GENX(BLEND_STATE_length
);
5448 /* Always write at least one BLEND_STATE - the final RT message will
5449 * reference BLEND_STATE[0] even if there aren't color writes. There
5450 * may still be alpha testing, computed depth, and so on.
5452 const int rt_dwords
=
5453 MAX2(cso_fb
->nr_cbufs
, 1) * GENX(BLEND_STATE_ENTRY_length
);
5455 uint32_t blend_offset
;
5456 uint32_t *blend_map
=
5457 stream_state(batch
, ice
->state
.dynamic_uploader
,
5458 &ice
->state
.last_res
.blend
,
5459 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
5461 uint32_t blend_state_header
;
5462 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
5463 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
5464 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
5467 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
5468 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
5470 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
5471 ptr
.BlendStatePointer
= blend_offset
;
5472 ptr
.BlendStatePointerValid
= true;
5476 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
5477 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
5479 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
5483 stream_state(batch
, ice
->state
.dynamic_uploader
,
5484 &ice
->state
.last_res
.color_calc
,
5485 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
5487 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
5488 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
5489 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
5490 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
5491 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
5492 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
5493 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
5495 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
5496 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
5499 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
5500 ptr
.ColorCalcStatePointer
= cc_offset
;
5501 ptr
.ColorCalcStatePointerValid
= true;
5505 /* GEN:BUG:1604061319
5507 * 3DSTATE_CONSTANT_* needs to be programmed before BTP_*
5509 * Testing shows that all the 3DSTATE_CONSTANT_XS need to be emitted if
5510 * any stage has a dirty binding table.
5512 const bool emit_const_wa
= GEN_GEN
>= 11 &&
5513 (dirty
& IRIS_ALL_DIRTY_BINDINGS
) != 0;
5516 uint32_t nobuffer_stages
= 0;
5519 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5520 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)) &&
5524 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5525 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5530 if (shs
->sysvals_need_upload
)
5531 upload_sysvals(ice
, stage
);
5533 struct push_bos push_bos
= {};
5534 setup_constant_buffers(ice
, batch
, stage
, &push_bos
);
5537 /* If this stage doesn't have any push constants, emit it later in a
5538 * single CONSTANT_ALL packet with all the other stages.
5540 if (push_bos
.buffer_count
== 0) {
5541 nobuffer_stages
|= 1 << stage
;
5545 /* The Constant Buffer Read Length field from 3DSTATE_CONSTANT_ALL
5546 * contains only 5 bits, so we can only use it for buffers smaller than
5549 if (push_bos
.max_length
< 32) {
5550 emit_push_constant_packet_all(ice
, batch
, 1 << stage
, &push_bos
);
5554 emit_push_constant_packets(ice
, batch
, stage
, &push_bos
);
5558 if (nobuffer_stages
)
5559 emit_push_constant_packet_all(ice
, batch
, nobuffer_stages
, NULL
);
5562 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5563 /* Gen9 requires 3DSTATE_BINDING_TABLE_POINTERS_XS to be re-emitted
5564 * in order to commit constants. TODO: Investigate "Disable Gather
5565 * at Set Shader" to go back to legacy mode...
5567 if (dirty
& ((IRIS_DIRTY_BINDINGS_VS
|
5568 (GEN_GEN
== 9 ? IRIS_DIRTY_CONSTANTS_VS
: 0)) << stage
)) {
5569 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
5570 ptr
._3DCommandSubOpcode
= 38 + stage
;
5571 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
5576 if (GEN_GEN
>= 11 && (dirty
& IRIS_DIRTY_RENDER_BUFFER
)) {
5577 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
5578 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
5580 /* The PIPE_CONTROL command description says:
5582 * "Whenever a Binding Table Index (BTI) used by a Render Target
5583 * Message points to a different RENDER_SURFACE_STATE, SW must issue a
5584 * Render Target Cache Flush by enabling this bit. When render target
5585 * flush is set due to new association of BTI, PS Scoreboard Stall bit
5586 * must be set in this packet."
5588 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
5589 iris_emit_pipe_control_flush(batch
, "workaround: RT BTI change [draw]",
5590 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5591 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
5594 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5595 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
5596 iris_populate_binding_table(ice
, batch
, stage
, false);
5600 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5601 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
5602 !ice
->shaders
.prog
[stage
])
5605 iris_upload_sampler_states(ice
, stage
);
5607 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5608 struct pipe_resource
*res
= shs
->sampler_table
.res
;
5610 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
5612 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
5613 ptr
._3DCommandSubOpcode
= 43 + stage
;
5614 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
5618 if (ice
->state
.need_border_colors
)
5619 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
5621 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
5622 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
5624 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
5625 if (ice
->state
.framebuffer
.samples
> 0)
5626 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
5630 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
5631 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
5632 ms
.SampleMask
= ice
->state
.sample_mask
;
5636 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5637 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
5640 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5643 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5644 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
5645 iris_use_pinned_bo(batch
, cache
->bo
, false);
5647 if (prog_data
->total_scratch
> 0) {
5648 struct iris_bo
*bo
=
5649 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
5650 iris_use_pinned_bo(batch
, bo
, true);
5653 if (stage
== MESA_SHADER_FRAGMENT
) {
5654 UNUSED
struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5655 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5657 uint32_t ps_state
[GENX(3DSTATE_PS_length
)] = {0};
5658 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
5659 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
5660 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
5661 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
5663 /* The docs for 3DSTATE_PS::32 Pixel Dispatch Enable say:
5665 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16,
5666 * SIMD32 Dispatch must not be enabled for PER_PIXEL dispatch
5669 * 16x MSAA only exists on Gen9+, so we can skip this on Gen8.
5671 if (GEN_GEN
>= 9 && cso_fb
->samples
== 16 &&
5672 !wm_prog_data
->persample_dispatch
) {
5673 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
5674 ps
._32PixelDispatchEnable
= false;
5677 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
5678 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
5679 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
5680 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
5681 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
5682 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
5684 ps
.KernelStartPointer0
= KSP(shader
) +
5685 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
5686 ps
.KernelStartPointer1
= KSP(shader
) +
5687 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
5688 ps
.KernelStartPointer2
= KSP(shader
) +
5689 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
5692 uint32_t psx_state
[GENX(3DSTATE_PS_EXTRA_length
)] = {0};
5693 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
5695 if (!wm_prog_data
->uses_sample_mask
)
5696 psx
.InputCoverageMaskState
= ICMS_NONE
;
5697 else if (wm_prog_data
->post_depth_coverage
)
5698 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
5699 else if (wm_prog_data
->inner_coverage
&&
5700 cso
->conservative_rasterization
)
5701 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
5703 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
5705 psx
.PixelShaderUsesInputCoverageMask
=
5706 wm_prog_data
->uses_sample_mask
;
5710 uint32_t *shader_ps
= (uint32_t *) shader
->derived_data
;
5711 uint32_t *shader_psx
= shader_ps
+ GENX(3DSTATE_PS_length
);
5712 iris_emit_merge(batch
, shader_ps
, ps_state
,
5713 GENX(3DSTATE_PS_length
));
5714 iris_emit_merge(batch
, shader_psx
, psx_state
,
5715 GENX(3DSTATE_PS_EXTRA_length
));
5717 iris_batch_emit(batch
, shader
->derived_data
,
5718 iris_derived_program_state_size(stage
));
5721 if (stage
== MESA_SHADER_TESS_EVAL
) {
5722 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
5723 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
5724 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
5725 } else if (stage
== MESA_SHADER_GEOMETRY
) {
5726 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
5731 if (ice
->state
.streamout_active
) {
5732 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
5733 iris_batch_emit(batch
, genx
->so_buffers
,
5734 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
5735 for (int i
= 0; i
< 4; i
++) {
5736 struct iris_stream_output_target
*tgt
=
5737 (void *) ice
->state
.so_target
[i
];
5740 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
5742 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
5748 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
5749 uint32_t *decl_list
=
5750 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
5751 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
5754 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
5755 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5757 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
5758 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
5759 sol
.SOFunctionEnable
= true;
5760 sol
.SOStatisticsEnable
= true;
5762 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
5763 !ice
->state
.prims_generated_query_active
;
5764 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
5767 assert(ice
->state
.streamout
);
5769 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
5770 GENX(3DSTATE_STREAMOUT_length
));
5773 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
5774 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
5778 if (dirty
& IRIS_DIRTY_CLIP
) {
5779 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5780 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5782 bool gs_or_tes
= ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] ||
5783 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
5784 bool points_or_lines
= cso_rast
->fill_mode_point_or_line
||
5785 (gs_or_tes
? ice
->shaders
.output_topology_is_points_or_lines
5786 : ice
->state
.prim_is_points_or_lines
);
5788 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
5789 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
5790 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5791 if (cso_rast
->rasterizer_discard
)
5792 cl
.ClipMode
= CLIPMODE_REJECT_ALL
;
5793 else if (ice
->state
.window_space_position
)
5794 cl
.ClipMode
= CLIPMODE_ACCEPT_ALL
;
5796 cl
.ClipMode
= CLIPMODE_NORMAL
;
5798 cl
.PerspectiveDivideDisable
= ice
->state
.window_space_position
;
5799 cl
.ViewportXYClipTestEnable
= !points_or_lines
;
5801 if (wm_prog_data
->barycentric_interp_modes
&
5802 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
5803 cl
.NonPerspectiveBarycentricEnable
= true;
5805 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
<= 1;
5806 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
5808 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
5809 ARRAY_SIZE(cso_rast
->clip
));
5812 if (dirty
& (IRIS_DIRTY_RASTER
| IRIS_DIRTY_URB
)) {
5813 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5814 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
5816 uint32_t dynamic_sf
[GENX(3DSTATE_SF_length
)];
5817 iris_pack_command(GENX(3DSTATE_SF
), &dynamic_sf
, sf
) {
5818 sf
.ViewportTransformEnable
= !ice
->state
.window_space_position
;
5821 sf
.DerefBlockSize
= ice
->state
.urb_deref_block_size
;
5824 iris_emit_merge(batch
, cso
->sf
, dynamic_sf
,
5825 ARRAY_SIZE(dynamic_sf
));
5828 if (dirty
& IRIS_DIRTY_WM
) {
5829 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5830 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
5832 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
5833 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5835 wm
.BarycentricInterpolationMode
=
5836 wm_prog_data
->barycentric_interp_modes
;
5838 if (wm_prog_data
->early_fragment_tests
)
5839 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
5840 else if (wm_prog_data
->has_side_effects
)
5841 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
5843 /* We could skip this bit if color writes are enabled. */
5844 if (wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
)
5845 wm
.ForceThreadDispatchEnable
= ForceON
;
5847 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
5850 if (dirty
& IRIS_DIRTY_SBE
) {
5851 iris_emit_sbe(batch
, ice
);
5854 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
5855 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
5856 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
5857 const struct shader_info
*fs_info
=
5858 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
5860 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
5861 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
5862 pb
.HasWriteableRT
= has_writeable_rt(cso_blend
, fs_info
);
5863 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
5865 /* The dual source blending docs caution against using SRC1 factors
5866 * when the shader doesn't use a dual source render target write.
5867 * Empirically, this can lead to GPU hangs, and the results are
5868 * undefined anyway, so simply disable blending to avoid the hang.
5870 pb
.ColorBufferBlendEnable
= (cso_blend
->blend_enables
& 1) &&
5871 (!cso_blend
->dual_color_blending
|| wm_prog_data
->dual_src_blend
);
5874 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
5875 ARRAY_SIZE(cso_blend
->ps_blend
));
5878 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
5879 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
5881 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
5882 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
5883 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
5884 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
5885 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
5887 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
5889 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
5893 iris_batch_emit(batch
, cso
->depth_bounds
, sizeof(cso
->depth_bounds
));
5897 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
5898 uint32_t scissor_offset
=
5899 emit_state(batch
, ice
->state
.dynamic_uploader
,
5900 &ice
->state
.last_res
.scissor
,
5901 ice
->state
.scissors
,
5902 sizeof(struct pipe_scissor_state
) *
5903 ice
->state
.num_viewports
, 32);
5905 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
5906 ptr
.ScissorRectPointer
= scissor_offset
;
5910 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
5911 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
5913 /* Do not emit the clear params yets. We need to update the clear value
5916 uint32_t clear_length
= GENX(3DSTATE_CLEAR_PARAMS_length
) * 4;
5917 uint32_t cso_z_size
= batch
->screen
->isl_dev
.ds
.size
- clear_length
;;
5920 /* GEN:BUG:14010455700
5922 * ISL will change some CHICKEN registers depending on the depth surface
5923 * format, along with emitting the depth and stencil packets. In that
5924 * case, we want to do a depth flush and stall, so the pipeline is not
5925 * using these settings while we change the registers.
5927 iris_emit_end_of_pipe_sync(batch
,
5928 "Workaround: Stop pipeline for 14010455700",
5929 PIPE_CONTROL_DEPTH_STALL
|
5930 PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
5933 iris_batch_emit(batch
, cso_z
->packets
, cso_z_size
);
5934 if (GEN_GEN
>= 12) {
5935 /* GEN:BUG:1408224581
5937 * Workaround: Gen12LP Astep only An additional pipe control with
5938 * post-sync = store dword operation would be required.( w/a is to
5939 * have an additional pipe control after the stencil state whenever
5940 * the surface state bits of this state is changing).
5942 iris_emit_pipe_control_write(batch
, "WA for stencil state",
5943 PIPE_CONTROL_WRITE_IMMEDIATE
,
5944 batch
->screen
->workaround_bo
, 0, 0);
5947 union isl_color_value clear_value
= { .f32
= { 0, } };
5949 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5950 if (cso_fb
->zsbuf
) {
5951 struct iris_resource
*zres
, *sres
;
5952 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
5954 if (zres
&& zres
->aux
.bo
)
5955 clear_value
= iris_resource_get_clear_color(zres
, NULL
, NULL
);
5958 uint32_t clear_params
[GENX(3DSTATE_CLEAR_PARAMS_length
)];
5959 iris_pack_command(GENX(3DSTATE_CLEAR_PARAMS
), clear_params
, clear
) {
5960 clear
.DepthClearValueValid
= true;
5961 clear
.DepthClearValue
= clear_value
.f32
[0];
5963 iris_batch_emit(batch
, clear_params
, clear_length
);
5966 if (dirty
& (IRIS_DIRTY_DEPTH_BUFFER
| IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
5967 /* Listen for buffer changes, and also write enable changes. */
5968 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5969 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
5972 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
5973 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
5974 for (int i
= 0; i
< 32; i
++) {
5975 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
5980 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
5981 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5982 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
5985 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
5986 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
5987 topo
.PrimitiveTopologyType
=
5988 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
5992 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
5993 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
5994 int dynamic_bound
= ice
->state
.bound_vertex_buffers
;
5996 if (ice
->state
.vs_uses_draw_params
) {
5997 assert(ice
->draw
.draw_params
.res
);
5999 struct iris_vertex_buffer_state
*state
=
6000 &(ice
->state
.genx
->vertex_buffers
[count
]);
6001 pipe_resource_reference(&state
->resource
, ice
->draw
.draw_params
.res
);
6002 struct iris_resource
*res
= (void *) state
->resource
;
6004 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
6005 vb
.VertexBufferIndex
= count
;
6006 vb
.AddressModifyEnable
= true;
6008 vb
.BufferSize
= res
->bo
->size
- ice
->draw
.draw_params
.offset
;
6009 vb
.BufferStartingAddress
=
6010 ro_bo(NULL
, res
->bo
->gtt_offset
+
6011 (int) ice
->draw
.draw_params
.offset
);
6012 vb
.MOCS
= iris_mocs(res
->bo
, &batch
->screen
->isl_dev
);
6014 dynamic_bound
|= 1ull << count
;
6018 if (ice
->state
.vs_uses_derived_draw_params
) {
6019 struct iris_vertex_buffer_state
*state
=
6020 &(ice
->state
.genx
->vertex_buffers
[count
]);
6021 pipe_resource_reference(&state
->resource
,
6022 ice
->draw
.derived_draw_params
.res
);
6023 struct iris_resource
*res
= (void *) ice
->draw
.derived_draw_params
.res
;
6025 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
6026 vb
.VertexBufferIndex
= count
;
6027 vb
.AddressModifyEnable
= true;
6030 res
->bo
->size
- ice
->draw
.derived_draw_params
.offset
;
6031 vb
.BufferStartingAddress
=
6032 ro_bo(NULL
, res
->bo
->gtt_offset
+
6033 (int) ice
->draw
.derived_draw_params
.offset
);
6034 vb
.MOCS
= iris_mocs(res
->bo
, &batch
->screen
->isl_dev
);
6036 dynamic_bound
|= 1ull << count
;
6042 /* Gen11+ doesn't need the cache workaround below */
6043 uint64_t bound
= dynamic_bound
;
6045 const int i
= u_bit_scan64(&bound
);
6046 iris_use_optional_res(batch
, genx
->vertex_buffers
[i
].resource
,
6050 /* The VF cache designers cut corners, and made the cache key's
6051 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
6052 * 32 bits of the address. If you have two vertex buffers which get
6053 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
6054 * you can get collisions (even within a single batch).
6056 * So, we need to do a VF cache invalidate if the buffer for a VB
6057 * slot slot changes [48:32] address bits from the previous time.
6059 unsigned flush_flags
= 0;
6061 uint64_t bound
= dynamic_bound
;
6063 const int i
= u_bit_scan64(&bound
);
6064 uint16_t high_bits
= 0;
6066 struct iris_resource
*res
=
6067 (void *) genx
->vertex_buffers
[i
].resource
;
6069 iris_use_pinned_bo(batch
, res
->bo
, false);
6071 high_bits
= res
->bo
->gtt_offset
>> 32ull;
6072 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
6073 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
|
6074 PIPE_CONTROL_CS_STALL
;
6075 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
6081 iris_emit_pipe_control_flush(batch
,
6082 "workaround: VF cache 32-bit key [VB]",
6087 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
6090 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
6091 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
6092 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
6096 bound
= dynamic_bound
;
6098 const int i
= u_bit_scan64(&bound
);
6099 memcpy(map
, genx
->vertex_buffers
[i
].state
,
6100 sizeof(uint32_t) * vb_dwords
);
6106 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
6107 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
6108 const unsigned entries
= MAX2(cso
->count
, 1);
6109 if (!(ice
->state
.vs_needs_sgvs_element
||
6110 ice
->state
.vs_uses_derived_draw_params
||
6111 ice
->state
.vs_needs_edge_flag
)) {
6112 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
6113 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
6115 uint32_t dynamic_ves
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
6116 const unsigned dyn_count
= cso
->count
+
6117 ice
->state
.vs_needs_sgvs_element
+
6118 ice
->state
.vs_uses_derived_draw_params
;
6120 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
),
6123 1 + GENX(VERTEX_ELEMENT_STATE_length
) * dyn_count
- 2;
6125 memcpy(&dynamic_ves
[1], &cso
->vertex_elements
[1],
6126 (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
6127 GENX(VERTEX_ELEMENT_STATE_length
) * sizeof(uint32_t));
6128 uint32_t *ve_pack_dest
=
6129 &dynamic_ves
[1 + (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
6130 GENX(VERTEX_ELEMENT_STATE_length
)];
6132 if (ice
->state
.vs_needs_sgvs_element
) {
6133 uint32_t base_ctrl
= ice
->state
.vs_uses_draw_params
?
6134 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
6135 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
6137 ve
.VertexBufferIndex
=
6138 util_bitcount64(ice
->state
.bound_vertex_buffers
);
6139 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
6140 ve
.Component0Control
= base_ctrl
;
6141 ve
.Component1Control
= base_ctrl
;
6142 ve
.Component2Control
= VFCOMP_STORE_0
;
6143 ve
.Component3Control
= VFCOMP_STORE_0
;
6145 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
6147 if (ice
->state
.vs_uses_derived_draw_params
) {
6148 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
6150 ve
.VertexBufferIndex
=
6151 util_bitcount64(ice
->state
.bound_vertex_buffers
) +
6152 ice
->state
.vs_uses_draw_params
;
6153 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
6154 ve
.Component0Control
= VFCOMP_STORE_SRC
;
6155 ve
.Component1Control
= VFCOMP_STORE_SRC
;
6156 ve
.Component2Control
= VFCOMP_STORE_0
;
6157 ve
.Component3Control
= VFCOMP_STORE_0
;
6159 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
6161 if (ice
->state
.vs_needs_edge_flag
) {
6162 for (int i
= 0; i
< GENX(VERTEX_ELEMENT_STATE_length
); i
++)
6163 ve_pack_dest
[i
] = cso
->edgeflag_ve
[i
];
6166 iris_batch_emit(batch
, &dynamic_ves
, sizeof(uint32_t) *
6167 (1 + dyn_count
* GENX(VERTEX_ELEMENT_STATE_length
)));
6170 if (!ice
->state
.vs_needs_edge_flag
) {
6171 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
6172 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
6174 assert(cso
->count
> 0);
6175 const unsigned edgeflag_index
= cso
->count
- 1;
6176 uint32_t dynamic_vfi
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
6177 memcpy(&dynamic_vfi
[0], cso
->vf_instancing
, edgeflag_index
*
6178 GENX(3DSTATE_VF_INSTANCING_length
) * sizeof(uint32_t));
6180 uint32_t *vfi_pack_dest
= &dynamic_vfi
[0] +
6181 edgeflag_index
* GENX(3DSTATE_VF_INSTANCING_length
);
6182 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
6183 vi
.VertexElementIndex
= edgeflag_index
+
6184 ice
->state
.vs_needs_sgvs_element
+
6185 ice
->state
.vs_uses_derived_draw_params
;
6187 for (int i
= 0; i
< GENX(3DSTATE_VF_INSTANCING_length
); i
++)
6188 vfi_pack_dest
[i
] |= cso
->edgeflag_vfi
[i
];
6190 iris_batch_emit(batch
, &dynamic_vfi
[0], sizeof(uint32_t) *
6191 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
6195 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
6196 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
6197 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
6198 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
6200 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
6201 if (vs_prog_data
->uses_vertexid
) {
6202 sgv
.VertexIDEnable
= true;
6203 sgv
.VertexIDComponentNumber
= 2;
6204 sgv
.VertexIDElementOffset
=
6205 cso
->count
- ice
->state
.vs_needs_edge_flag
;
6208 if (vs_prog_data
->uses_instanceid
) {
6209 sgv
.InstanceIDEnable
= true;
6210 sgv
.InstanceIDComponentNumber
= 3;
6211 sgv
.InstanceIDElementOffset
=
6212 cso
->count
- ice
->state
.vs_needs_edge_flag
;
6217 if (dirty
& IRIS_DIRTY_VF
) {
6218 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
6219 if (draw
->primitive_restart
) {
6220 vf
.IndexedDrawCutIndexEnable
= true;
6221 vf
.CutIndex
= draw
->restart_index
;
6226 if (dirty
& IRIS_DIRTY_VF_STATISTICS
) {
6227 iris_emit_cmd(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
6228 vf
.StatisticsEnable
= true;
6233 if (dirty
& IRIS_DIRTY_PMA_FIX
) {
6234 bool enable
= want_pma_fix(ice
);
6235 genX(update_pma_fix
)(ice
, batch
, enable
);
6239 if (ice
->state
.current_hash_scale
!= 1)
6240 genX(emit_hashing_mode
)(ice
, batch
, UINT_MAX
, UINT_MAX
, 1);
6243 genX(invalidate_aux_map_state
)(batch
);
6248 iris_upload_render_state(struct iris_context
*ice
,
6249 struct iris_batch
*batch
,
6250 const struct pipe_draw_info
*draw
)
6252 bool use_predicate
= ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
6254 /* Always pin the binder. If we're emitting new binding table pointers,
6255 * we need it. If not, we're probably inheriting old tables via the
6256 * context, and need it anyway. Since true zero-bindings cases are
6257 * practically non-existent, just pin it and avoid last_res tracking.
6259 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
6261 if (!batch
->contains_draw
) {
6262 iris_restore_render_saved_bos(ice
, batch
, draw
);
6263 batch
->contains_draw
= true;
6266 iris_upload_dirty_render_state(ice
, batch
, draw
);
6268 if (draw
->index_size
> 0) {
6271 if (draw
->has_user_indices
) {
6272 u_upload_data(ice
->ctx
.stream_uploader
, 0,
6273 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
6274 &offset
, &ice
->state
.last_res
.index_buffer
);
6276 struct iris_resource
*res
= (void *) draw
->index
.resource
;
6277 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
6279 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
6280 draw
->index
.resource
);
6284 struct iris_genx_state
*genx
= ice
->state
.genx
;
6285 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
6287 uint32_t ib_packet
[GENX(3DSTATE_INDEX_BUFFER_length
)];
6288 iris_pack_command(GENX(3DSTATE_INDEX_BUFFER
), ib_packet
, ib
) {
6289 ib
.IndexFormat
= draw
->index_size
>> 1;
6290 ib
.MOCS
= iris_mocs(bo
, &batch
->screen
->isl_dev
);
6291 ib
.BufferSize
= bo
->size
- offset
;
6292 ib
.BufferStartingAddress
= ro_bo(NULL
, bo
->gtt_offset
+ offset
);
6295 if (memcmp(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
)) != 0) {
6296 memcpy(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
));
6297 iris_batch_emit(batch
, ib_packet
, sizeof(ib_packet
));
6298 iris_use_pinned_bo(batch
, bo
, false);
6302 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
6303 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
6304 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
6305 iris_emit_pipe_control_flush(batch
,
6306 "workaround: VF cache 32-bit key [IB]",
6307 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
6308 PIPE_CONTROL_CS_STALL
);
6309 ice
->state
.last_index_bo_high_bits
= high_bits
;
6314 #define _3DPRIM_END_OFFSET 0x2420
6315 #define _3DPRIM_START_VERTEX 0x2430
6316 #define _3DPRIM_VERTEX_COUNT 0x2434
6317 #define _3DPRIM_INSTANCE_COUNT 0x2438
6318 #define _3DPRIM_START_INSTANCE 0x243C
6319 #define _3DPRIM_BASE_VERTEX 0x2440
6321 if (draw
->indirect
) {
6322 if (draw
->indirect
->indirect_draw_count
) {
6323 use_predicate
= true;
6325 struct iris_bo
*draw_count_bo
=
6326 iris_resource_bo(draw
->indirect
->indirect_draw_count
);
6327 unsigned draw_count_offset
=
6328 draw
->indirect
->indirect_draw_count_offset
;
6330 iris_emit_pipe_control_flush(batch
,
6331 "ensure indirect draw buffer is flushed",
6332 PIPE_CONTROL_FLUSH_ENABLE
);
6334 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
) {
6335 struct gen_mi_builder b
;
6336 gen_mi_builder_init(&b
, batch
);
6338 /* comparison = draw id < draw count */
6339 struct gen_mi_value comparison
=
6340 gen_mi_ult(&b
, gen_mi_imm(draw
->drawid
),
6341 gen_mi_mem32(ro_bo(draw_count_bo
,
6342 draw_count_offset
)));
6344 /* predicate = comparison & conditional rendering predicate */
6345 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_RESULT
),
6346 gen_mi_iand(&b
, comparison
,
6347 gen_mi_reg32(CS_GPR(15))));
6349 uint32_t mi_predicate
;
6351 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
6352 iris_load_register_imm64(batch
, MI_PREDICATE_SRC1
, draw
->drawid
);
6353 /* Upload the current draw count from the draw parameters buffer
6354 * to MI_PREDICATE_SRC0.
6356 iris_load_register_mem32(batch
, MI_PREDICATE_SRC0
,
6357 draw_count_bo
, draw_count_offset
);
6358 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
6359 iris_load_register_imm32(batch
, MI_PREDICATE_SRC0
+ 4, 0);
6361 if (draw
->drawid
== 0) {
6362 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
6363 MI_PREDICATE_COMBINEOP_SET
|
6364 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
6366 /* While draw_index < draw_count the predicate's result will be
6367 * (draw_index == draw_count) ^ TRUE = TRUE
6368 * When draw_index == draw_count the result is
6369 * (TRUE) ^ TRUE = FALSE
6370 * After this all results will be:
6371 * (FALSE) ^ FALSE = FALSE
6373 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOAD
|
6374 MI_PREDICATE_COMBINEOP_XOR
|
6375 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
6377 iris_batch_emit(batch
, &mi_predicate
, sizeof(uint32_t));
6380 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
6383 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6384 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
6385 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
6387 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6388 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
6389 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
6391 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6392 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
6393 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
6395 if (draw
->index_size
) {
6396 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6397 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
6398 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
6400 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6401 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
6402 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
6405 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6406 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
6407 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
6409 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
6410 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
6414 } else if (draw
->count_from_stream_output
) {
6415 struct iris_stream_output_target
*so
=
6416 (void *) draw
->count_from_stream_output
;
6418 /* XXX: Replace with actual cache tracking */
6419 iris_emit_pipe_control_flush(batch
,
6420 "draw count from stream output stall",
6421 PIPE_CONTROL_CS_STALL
);
6423 struct gen_mi_builder b
;
6424 gen_mi_builder_init(&b
, batch
);
6426 struct iris_address addr
=
6427 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
6428 struct gen_mi_value offset
=
6429 gen_mi_iadd_imm(&b
, gen_mi_mem32(addr
), -so
->base
.buffer_offset
);
6431 gen_mi_store(&b
, gen_mi_reg32(_3DPRIM_VERTEX_COUNT
),
6432 gen_mi_udiv32_imm(&b
, offset
, so
->stride
));
6434 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
6435 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
6436 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
6437 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
6440 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
6441 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
6442 prim
.PredicateEnable
= use_predicate
;
6444 if (draw
->indirect
|| draw
->count_from_stream_output
) {
6445 prim
.IndirectParameterEnable
= true;
6447 prim
.StartInstanceLocation
= draw
->start_instance
;
6448 prim
.InstanceCount
= draw
->instance_count
;
6449 prim
.VertexCountPerInstance
= draw
->count
;
6451 prim
.StartVertexLocation
= draw
->start
;
6453 if (draw
->index_size
) {
6454 prim
.BaseVertexLocation
+= draw
->index_bias
;
6456 prim
.StartVertexLocation
+= draw
->index_bias
;
6463 iris_upload_compute_state(struct iris_context
*ice
,
6464 struct iris_batch
*batch
,
6465 const struct pipe_grid_info
*grid
)
6467 const uint64_t dirty
= ice
->state
.dirty
;
6468 struct iris_screen
*screen
= batch
->screen
;
6469 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
6470 struct iris_binder
*binder
= &ice
->state
.binder
;
6471 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
6472 struct iris_compiled_shader
*shader
=
6473 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
6474 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
6475 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
6477 /* Always pin the binder. If we're emitting new binding table pointers,
6478 * we need it. If not, we're probably inheriting old tables via the
6479 * context, and need it anyway. Since true zero-bindings cases are
6480 * practically non-existent, just pin it and avoid last_res tracking.
6482 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
6484 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->sysvals_need_upload
)
6485 upload_sysvals(ice
, MESA_SHADER_COMPUTE
);
6487 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
6488 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
6490 if (dirty
& IRIS_DIRTY_SAMPLER_STATES_CS
)
6491 iris_upload_sampler_states(ice
, MESA_SHADER_COMPUTE
);
6493 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
6494 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
6496 if (ice
->state
.need_border_colors
)
6497 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
6500 genX(invalidate_aux_map_state
)(batch
);
6503 if (dirty
& IRIS_DIRTY_CS
) {
6504 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
6506 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
6507 * the only bits that are changed are scoreboard related: Scoreboard
6508 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
6509 * these scoreboard related states, a MEDIA_STATE_FLUSH is
6512 iris_emit_pipe_control_flush(batch
,
6513 "workaround: stall before MEDIA_VFE_STATE",
6514 PIPE_CONTROL_CS_STALL
);
6516 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
6517 if (prog_data
->total_scratch
) {
6518 struct iris_bo
*bo
=
6519 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
6520 MESA_SHADER_COMPUTE
);
6521 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
6522 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
6525 vfe
.MaximumNumberofThreads
=
6526 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
6528 vfe
.ResetGatewayTimer
=
6529 Resettingrelativetimerandlatchingtheglobaltimestamp
;
6532 vfe
.BypassGatewayControl
= true;
6534 vfe
.NumberofURBEntries
= 2;
6535 vfe
.URBEntryAllocationSize
= 2;
6537 vfe
.CURBEAllocationSize
=
6538 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
6539 cs_prog_data
->push
.cross_thread
.regs
, 2);
6543 /* TODO: Combine subgroup-id with cbuf0 so we can push regular uniforms */
6544 if (dirty
& IRIS_DIRTY_CS
) {
6545 uint32_t curbe_data_offset
= 0;
6546 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
6547 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
6548 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
6549 uint32_t *curbe_data_map
=
6550 stream_state(batch
, ice
->state
.dynamic_uploader
,
6551 &ice
->state
.last_res
.cs_thread_ids
,
6552 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
6553 &curbe_data_offset
);
6554 assert(curbe_data_map
);
6555 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
6556 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
6558 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
6559 curbe
.CURBETotalDataLength
=
6560 ALIGN(cs_prog_data
->push
.total
.size
, 64);
6561 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
6565 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
6566 IRIS_DIRTY_BINDINGS_CS
|
6567 IRIS_DIRTY_CONSTANTS_CS
|
6569 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
6571 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
6572 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
6573 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
6576 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
6577 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
6579 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
6580 load
.InterfaceDescriptorTotalLength
=
6581 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
6582 load
.InterfaceDescriptorDataStartAddress
=
6583 emit_state(batch
, ice
->state
.dynamic_uploader
,
6584 &ice
->state
.last_res
.cs_desc
, desc
, sizeof(desc
), 64);
6588 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
6589 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
6590 uint32_t right_mask
;
6593 right_mask
= ~0u >> (32 - remainder
);
6595 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
6597 #define GPGPU_DISPATCHDIMX 0x2500
6598 #define GPGPU_DISPATCHDIMY 0x2504
6599 #define GPGPU_DISPATCHDIMZ 0x2508
6601 if (grid
->indirect
) {
6602 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
6603 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
6604 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6605 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
6606 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
6608 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6609 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
6610 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
6612 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6613 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
6614 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
6618 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
6619 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
6620 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
6621 ggw
.ThreadDepthCounterMaximum
= 0;
6622 ggw
.ThreadHeightCounterMaximum
= 0;
6623 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
6624 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
6625 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
6626 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
6627 ggw
.RightExecutionMask
= right_mask
;
6628 ggw
.BottomExecutionMask
= 0xffffffff;
6631 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
6633 if (!batch
->contains_draw
) {
6634 iris_restore_compute_saved_bos(ice
, batch
, grid
);
6635 batch
->contains_draw
= true;
6640 * State module teardown.
6643 iris_destroy_state(struct iris_context
*ice
)
6645 struct iris_genx_state
*genx
= ice
->state
.genx
;
6647 pipe_resource_reference(&ice
->draw
.draw_params
.res
, NULL
);
6648 pipe_resource_reference(&ice
->draw
.derived_draw_params
.res
, NULL
);
6650 /* Loop over all VBOs, including ones for draw parameters */
6651 for (unsigned i
= 0; i
< ARRAY_SIZE(genx
->vertex_buffers
); i
++) {
6652 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
6655 free(ice
->state
.genx
);
6657 for (int i
= 0; i
< 4; i
++) {
6658 pipe_so_target_reference(&ice
->state
.so_target
[i
], NULL
);
6661 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
6662 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
6664 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
6666 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
6667 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
6668 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
6669 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
6670 pipe_resource_reference(&shs
->constbuf
[i
].buffer
, NULL
);
6671 pipe_resource_reference(&shs
->constbuf_surf_state
[i
].res
, NULL
);
6673 for (int i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
6674 pipe_resource_reference(&shs
->image
[i
].base
.resource
, NULL
);
6675 pipe_resource_reference(&shs
->image
[i
].surface_state
.ref
.res
, NULL
);
6676 free(shs
->image
[i
].surface_state
.cpu
);
6678 for (int i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
6679 pipe_resource_reference(&shs
->ssbo
[i
].buffer
, NULL
);
6680 pipe_resource_reference(&shs
->ssbo_surf_state
[i
].res
, NULL
);
6682 for (int i
= 0; i
< IRIS_MAX_TEXTURE_SAMPLERS
; i
++) {
6683 pipe_sampler_view_reference((struct pipe_sampler_view
**)
6684 &shs
->textures
[i
], NULL
);
6688 pipe_resource_reference(&ice
->state
.grid_size
.res
, NULL
);
6689 pipe_resource_reference(&ice
->state
.grid_surf_state
.res
, NULL
);
6691 pipe_resource_reference(&ice
->state
.null_fb
.res
, NULL
);
6692 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
6694 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
6695 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
6696 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
6697 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
6698 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
6699 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
6700 pipe_resource_reference(&ice
->state
.last_res
.cs_thread_ids
, NULL
);
6701 pipe_resource_reference(&ice
->state
.last_res
.cs_desc
, NULL
);
6704 /* ------------------------------------------------------------------- */
6707 iris_rebind_buffer(struct iris_context
*ice
,
6708 struct iris_resource
*res
)
6710 struct pipe_context
*ctx
= &ice
->ctx
;
6711 struct iris_genx_state
*genx
= ice
->state
.genx
;
6713 assert(res
->base
.target
== PIPE_BUFFER
);
6715 /* Buffers can't be framebuffer attachments, nor display related,
6716 * and we don't have upstream Clover support.
6718 assert(!(res
->bind_history
& (PIPE_BIND_DEPTH_STENCIL
|
6719 PIPE_BIND_RENDER_TARGET
|
6720 PIPE_BIND_BLENDABLE
|
6721 PIPE_BIND_DISPLAY_TARGET
|
6723 PIPE_BIND_COMPUTE_RESOURCE
|
6724 PIPE_BIND_GLOBAL
)));
6726 if (res
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
6727 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
6729 const int i
= u_bit_scan64(&bound_vbs
);
6730 struct iris_vertex_buffer_state
*state
= &genx
->vertex_buffers
[i
];
6732 /* Update the CPU struct */
6733 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_start
) == 32);
6734 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) == 64);
6735 uint64_t *addr
= (uint64_t *) &state
->state
[1];
6736 struct iris_bo
*bo
= iris_resource_bo(state
->resource
);
6738 if (*addr
!= bo
->gtt_offset
+ state
->offset
) {
6739 *addr
= bo
->gtt_offset
+ state
->offset
;
6740 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
6745 /* We don't need to handle PIPE_BIND_INDEX_BUFFER here: we re-emit
6746 * the 3DSTATE_INDEX_BUFFER packet whenever the address changes.
6748 * There is also no need to handle these:
6749 * - PIPE_BIND_COMMAND_ARGS_BUFFER (emitted for every indirect draw)
6750 * - PIPE_BIND_QUERY_BUFFER (no persistent state references)
6753 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
6754 /* XXX: be careful about resetting vs appending... */
6758 for (int s
= MESA_SHADER_VERTEX
; s
< MESA_SHADER_STAGES
; s
++) {
6759 struct iris_shader_state
*shs
= &ice
->state
.shaders
[s
];
6760 enum pipe_shader_type p_stage
= stage_to_pipe(s
);
6762 if (!(res
->bind_stages
& (1 << s
)))
6765 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
6766 /* Skip constant buffer 0, it's for regular uniforms, not UBOs */
6767 uint32_t bound_cbufs
= shs
->bound_cbufs
& ~1u;
6768 while (bound_cbufs
) {
6769 const int i
= u_bit_scan(&bound_cbufs
);
6770 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[i
];
6771 struct iris_state_ref
*surf_state
= &shs
->constbuf_surf_state
[i
];
6773 if (res
->bo
== iris_resource_bo(cbuf
->buffer
)) {
6774 pipe_resource_reference(&surf_state
->res
, NULL
);
6775 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< s
;
6780 if (res
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
6781 uint32_t bound_ssbos
= shs
->bound_ssbos
;
6782 while (bound_ssbos
) {
6783 const int i
= u_bit_scan(&bound_ssbos
);
6784 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[i
];
6786 if (res
->bo
== iris_resource_bo(ssbo
->buffer
)) {
6787 struct pipe_shader_buffer buf
= {
6788 .buffer
= &res
->base
,
6789 .buffer_offset
= ssbo
->buffer_offset
,
6790 .buffer_size
= ssbo
->buffer_size
,
6792 iris_set_shader_buffers(ctx
, p_stage
, i
, 1, &buf
,
6793 (shs
->writable_ssbos
>> i
) & 1);
6798 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
6799 uint32_t bound_sampler_views
= shs
->bound_sampler_views
;
6800 while (bound_sampler_views
) {
6801 const int i
= u_bit_scan(&bound_sampler_views
);
6802 struct iris_sampler_view
*isv
= shs
->textures
[i
];
6803 struct iris_bo
*bo
= isv
->res
->bo
;
6805 if (update_surface_state_addrs(ice
->state
.surface_uploader
,
6806 &isv
->surface_state
, bo
)) {
6807 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< s
;
6812 if (res
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
6813 uint32_t bound_image_views
= shs
->bound_image_views
;
6814 while (bound_image_views
) {
6815 const int i
= u_bit_scan(&bound_image_views
);
6816 struct iris_image_view
*iv
= &shs
->image
[i
];
6817 struct iris_bo
*bo
= iris_resource_bo(iv
->base
.resource
);
6819 if (update_surface_state_addrs(ice
->state
.surface_uploader
,
6820 &iv
->surface_state
, bo
)) {
6821 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< s
;
6828 /* ------------------------------------------------------------------- */
6831 flags_to_post_sync_op(uint32_t flags
)
6833 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
6834 return WriteImmediateData
;
6836 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
6837 return WritePSDepthCount
;
6839 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
6840 return WriteTimestamp
;
6846 * Do the given flags have a Post Sync or LRI Post Sync operation?
6848 static enum pipe_control_flags
6849 get_post_sync_flags(enum pipe_control_flags flags
)
6851 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
6852 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6853 PIPE_CONTROL_WRITE_TIMESTAMP
|
6854 PIPE_CONTROL_LRI_POST_SYNC_OP
;
6856 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
6857 * "LRI Post Sync Operation". So more than one bit set would be illegal.
6859 assert(util_bitcount(flags
) <= 1);
6864 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
6867 * Emit a series of PIPE_CONTROL commands, taking into account any
6868 * workarounds necessary to actually accomplish the caller's request.
6870 * Unless otherwise noted, spec quotations in this function come from:
6872 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
6873 * Restrictions for PIPE_CONTROL.
6875 * You should not use this function directly. Use the helpers in
6876 * iris_pipe_control.c instead, which may split the pipe control further.
6879 iris_emit_raw_pipe_control(struct iris_batch
*batch
,
6886 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6887 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
6888 enum pipe_control_flags non_lri_post_sync_flags
=
6889 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
6891 /* Recursive PIPE_CONTROL workarounds --------------------------------
6892 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
6894 * We do these first because we want to look at the original operation,
6895 * rather than any workarounds we set.
6897 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
6898 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
6899 * lists several workarounds:
6901 * "Project: SKL, KBL, BXT
6903 * If the VF Cache Invalidation Enable is set to a 1 in a
6904 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
6905 * sets to 0, with the VF Cache Invalidation Enable set to 0
6906 * needs to be sent prior to the PIPE_CONTROL with VF Cache
6907 * Invalidation Enable set to a 1."
6909 iris_emit_raw_pipe_control(batch
,
6910 "workaround: recursive VF cache invalidate",
6914 /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
6915 * invalidates the instruction cache
6917 if (GEN_GEN
== 12 && (flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
)) {
6918 iris_emit_raw_pipe_control(batch
,
6919 "workaround: CS stall before instruction "
6921 PIPE_CONTROL_CS_STALL
|
6922 PIPE_CONTROL_STALL_AT_SCOREBOARD
, bo
, offset
,
6926 if ((GEN_GEN
== 9 || (GEN_GEN
== 12 && devinfo
->revision
== 0 /* A0*/)) &&
6927 IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
6928 /* Project: SKL / Argument: LRI Post Sync Operation [23]
6930 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6931 * programmed prior to programming a PIPECONTROL command with "LRI
6932 * Post Sync Operation" in GPGPU mode of operation (i.e when
6933 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
6935 * The same text exists a few rows below for Post Sync Op.
6937 * On Gen12 this is GEN:BUG:1607156449.
6939 iris_emit_raw_pipe_control(batch
,
6940 "workaround: CS stall before gpgpu post-sync",
6941 PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
6944 /* "Flush Types" workarounds ---------------------------------------------
6945 * We do these now because they may add post-sync operations or CS stalls.
6948 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
6949 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
6951 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
6952 * 'Write PS Depth Count' or 'Write Timestamp'."
6955 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6956 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6957 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6958 bo
= batch
->screen
->workaround_bo
;
6962 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
6963 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
6965 * "This bit must be DISABLED for operations other than writing
6968 * This seems like nonsense. An Ivybridge workaround requires us to
6969 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
6970 * operation. Gen8+ requires us to emit depth stalls and depth cache
6971 * flushes together. So, it's hard to imagine this means anything other
6972 * than "we originally intended this to be used for PS_DEPTH_COUNT".
6974 * We ignore the supposed restriction and do nothing.
6978 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6979 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6980 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
6982 * "This bit must be DISABLED for End-of-pipe (Read) fences,
6983 * PS_DEPTH_COUNT or TIMESTAMP queries."
6985 * TODO: Implement end-of-pipe checking.
6987 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6988 PIPE_CONTROL_WRITE_TIMESTAMP
)));
6991 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6992 /* From the PIPE_CONTROL instruction table, bit 1:
6994 * "This bit is ignored if Depth Stall Enable is set.
6995 * Further, the render cache is not flushed even if Write Cache
6996 * Flush Enable bit is set."
6998 * We assert that the caller doesn't do this combination, to try and
6999 * prevent mistakes. It shouldn't hurt the GPU, though.
7001 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
7002 * and "Render Target Flush" combo is explicitly required for BTI
7003 * update workarounds.
7005 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
7006 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
7009 /* PIPE_CONTROL page workarounds ------------------------------------- */
7011 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
7012 /* From the PIPE_CONTROL page itself:
7015 * Restriction: Pipe_control with CS-stall bit set must be issued
7016 * before a pipe-control command that has the State Cache
7017 * Invalidate bit set."
7019 flags
|= PIPE_CONTROL_CS_STALL
;
7022 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
7023 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
7026 * SW must always program Post-Sync Operation to "Write Immediate
7027 * Data" when Flush LLC is set."
7029 * For now, we just require the caller to do it.
7031 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
7034 /* "Post-Sync Operation" workarounds -------------------------------- */
7036 /* Project: All / Argument: Global Snapshot Count Reset [19]
7038 * "This bit must not be exercised on any product.
7039 * Requires stall bit ([20] of DW1) set."
7041 * We don't use this, so we just assert that it isn't used. The
7042 * PIPE_CONTROL instruction page indicates that they intended this
7043 * as a debug feature and don't think it is useful in production,
7044 * but it may actually be usable, should we ever want to.
7046 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
7048 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
7049 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
7050 /* Project: All / Arguments:
7052 * - Generic Media State Clear [16]
7053 * - Indirect State Pointers Disable [16]
7055 * "Requires stall bit ([20] of DW1) set."
7057 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
7058 * State Clear) says:
7060 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
7061 * programmed prior to programming a PIPECONTROL command with "Media
7062 * State Clear" set in GPGPU mode of operation"
7064 * This is a subset of the earlier rule, so there's nothing to do.
7066 flags
|= PIPE_CONTROL_CS_STALL
;
7069 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
7070 /* Project: All / Argument: Store Data Index
7072 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
7075 * For now, we just assert that the caller does this. We might want to
7076 * automatically add a write to the workaround BO...
7078 assert(non_lri_post_sync_flags
!= 0);
7081 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
7082 /* Project: All / Argument: Sync GFDT
7084 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
7085 * than '0' or 0x2520[13] must be set."
7087 * For now, we just assert that the caller does this.
7089 assert(non_lri_post_sync_flags
!= 0);
7092 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
7093 /* Project: IVB+ / Argument: TLB inv
7095 * "Requires stall bit ([20] of DW1) set."
7097 * Also, from the PIPE_CONTROL instruction table:
7100 * Post Sync Operation or CS stall must be set to ensure a TLB
7101 * invalidation occurs. Otherwise no cycle will occur to the TLB
7102 * cache to invalidate."
7104 * This is not a subset of the earlier rule, so there's nothing to do.
7106 flags
|= PIPE_CONTROL_CS_STALL
;
7109 if (GEN_GEN
>= 12 && ((flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) ||
7110 (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
))) {
7111 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
7114 * Unified Cache (Tile Cache Disabled):
7116 * When the Color and Depth (Z) streams are enabled to be cached in
7117 * the DC space of L2, Software must use "Render Target Cache Flush
7118 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
7119 * Flush" for getting the color and depth (Z) write data to be
7120 * globally observable. In this mode of operation it is not required
7121 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
7123 flags
|= PIPE_CONTROL_TILE_CACHE_FLUSH
;
7126 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
7127 /* TODO: The big Skylake GT4 post sync op workaround */
7130 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
7132 if (IS_COMPUTE_PIPELINE(batch
)) {
7133 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
7134 /* Project: SKL+ / Argument: Tex Invalidate
7135 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
7137 flags
|= PIPE_CONTROL_CS_STALL
;
7140 if (GEN_GEN
== 8 && (post_sync_flags
||
7141 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
7142 PIPE_CONTROL_DEPTH_STALL
|
7143 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
7144 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
7145 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
7146 /* Project: BDW / Arguments:
7148 * - LRI Post Sync Operation [23]
7149 * - Post Sync Op [15:14]
7151 * - Depth Stall [13]
7152 * - Render Target Cache Flush [12]
7153 * - Depth Cache Flush [0]
7154 * - DC Flush Enable [5]
7156 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
7159 flags
|= PIPE_CONTROL_CS_STALL
;
7161 /* Also, from the PIPE_CONTROL instruction table, bit 20:
7164 * This bit must be always set when PIPE_CONTROL command is
7165 * programmed by GPGPU and MEDIA workloads, except for the cases
7166 * when only Read Only Cache Invalidation bits are set (State
7167 * Cache Invalidation Enable, Instruction cache Invalidation
7168 * Enable, Texture Cache Invalidation Enable, Constant Cache
7169 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
7170 * need not implemented when FF_DOP_CG is disable via "Fixed
7171 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
7173 * It sounds like we could avoid CS stalls in some cases, but we
7174 * don't currently bother. This list isn't exactly the list above,
7180 /* "Stall" workarounds ----------------------------------------------
7181 * These have to come after the earlier ones because we may have added
7182 * some additional CS stalls above.
7185 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
7186 /* Project: PRE-SKL, VLV, CHV
7188 * "[All Stepping][All SKUs]:
7190 * One of the following must also be set:
7192 * - Render Target Cache Flush Enable ([12] of DW1)
7193 * - Depth Cache Flush Enable ([0] of DW1)
7194 * - Stall at Pixel Scoreboard ([1] of DW1)
7195 * - Depth Stall ([13] of DW1)
7196 * - Post-Sync Operation ([13] of DW1)
7197 * - DC Flush Enable ([5] of DW1)"
7199 * If we don't already have one of those bits set, we choose to add
7200 * "Stall at Pixel Scoreboard". Some of the other bits require a
7201 * CS stall as a workaround (see above), which would send us into
7202 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
7203 * appears to be safe, so we choose that.
7205 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
7206 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
7207 PIPE_CONTROL_WRITE_IMMEDIATE
|
7208 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
7209 PIPE_CONTROL_WRITE_TIMESTAMP
|
7210 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
7211 PIPE_CONTROL_DEPTH_STALL
|
7212 PIPE_CONTROL_DATA_CACHE_FLUSH
;
7213 if (!(flags
& wa_bits
))
7214 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
7217 if (GEN_GEN
>= 12 && (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
)) {
7218 /* GEN:BUG:1409600907:
7220 * "PIPE_CONTROL with Depth Stall Enable bit must be set
7221 * with any PIPE_CONTROL with Depth Flush Enable bit set.
7223 flags
|= PIPE_CONTROL_DEPTH_STALL
;
7226 /* Emit --------------------------------------------------------------- */
7228 if (INTEL_DEBUG
& DEBUG_PIPE_CONTROL
) {
7230 " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64
"]: %s\n",
7231 (flags
& PIPE_CONTROL_FLUSH_ENABLE
) ? "PipeCon " : "",
7232 (flags
& PIPE_CONTROL_CS_STALL
) ? "CS " : "",
7233 (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) ? "Scoreboard " : "",
7234 (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) ? "VF " : "",
7235 (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) ? "RT " : "",
7236 (flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
) ? "Const " : "",
7237 (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
) ? "TC " : "",
7238 (flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
) ? "DC " : "",
7239 (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
) ? "ZFlush " : "",
7240 (flags
& PIPE_CONTROL_DEPTH_STALL
) ? "ZStall " : "",
7241 (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
) ? "State " : "",
7242 (flags
& PIPE_CONTROL_TLB_INVALIDATE
) ? "TLB " : "",
7243 (flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
) ? "Inst " : "",
7244 (flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
) ? "MediaClear " : "",
7245 (flags
& PIPE_CONTROL_NOTIFY_ENABLE
) ? "Notify " : "",
7246 (flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) ?
7248 (flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
) ?
7250 (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
) ? "WriteImm " : "",
7251 (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
) ? "WriteZCount " : "",
7252 (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
) ? "WriteTimestamp " : "",
7253 (flags
& PIPE_CONTROL_FLUSH_HDC
) ? "HDC " : "",
7257 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
7259 pc
.TileCacheFlushEnable
= flags
& PIPE_CONTROL_TILE_CACHE_FLUSH
;
7262 pc
.HDCPipelineFlushEnable
= flags
& PIPE_CONTROL_FLUSH_HDC
;
7264 pc
.LRIPostSyncOperation
= NoLRIOperation
;
7265 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
7266 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
7267 pc
.StoreDataIndex
= 0;
7268 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
7269 pc
.GlobalSnapshotCountReset
=
7270 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
7271 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
7272 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
7273 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
7274 pc
.RenderTargetCacheFlushEnable
=
7275 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
7276 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
7277 pc
.StateCacheInvalidationEnable
=
7278 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
7279 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
7280 pc
.ConstantCacheInvalidationEnable
=
7281 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
7282 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
7283 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
7284 pc
.InstructionCacheInvalidateEnable
=
7285 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
7286 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
7287 pc
.IndirectStatePointersDisable
=
7288 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
7289 pc
.TextureCacheInvalidationEnable
=
7290 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
7291 pc
.Address
= rw_bo(bo
, offset
);
7292 pc
.ImmediateData
= imm
;
7298 * Preemption on Gen9 has to be enabled or disabled in various cases.
7300 * See these workarounds for preemption:
7301 * - WaDisableMidObjectPreemptionForGSLineStripAdj
7302 * - WaDisableMidObjectPreemptionForTrifanOrPolygon
7303 * - WaDisableMidObjectPreemptionForLineLoop
7306 * We don't put this in the vtable because it's only used on Gen9.
7309 gen9_toggle_preemption(struct iris_context
*ice
,
7310 struct iris_batch
*batch
,
7311 const struct pipe_draw_info
*draw
)
7313 struct iris_genx_state
*genx
= ice
->state
.genx
;
7314 bool object_preemption
= true;
7316 /* WaDisableMidObjectPreemptionForGSLineStripAdj
7318 * "WA: Disable mid-draw preemption when draw-call is a linestrip_adj
7319 * and GS is enabled."
7321 if (draw
->mode
== PIPE_PRIM_LINE_STRIP_ADJACENCY
&&
7322 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
7323 object_preemption
= false;
7325 /* WaDisableMidObjectPreemptionForTrifanOrPolygon
7327 * "TriFan miscompare in Execlist Preemption test. Cut index that is
7328 * on a previous context. End the previous, the resume another context
7329 * with a tri-fan or polygon, and the vertex count is corrupted. If we
7330 * prempt again we will cause corruption.
7332 * WA: Disable mid-draw preemption when draw-call has a tri-fan."
7334 if (draw
->mode
== PIPE_PRIM_TRIANGLE_FAN
)
7335 object_preemption
= false;
7337 /* WaDisableMidObjectPreemptionForLineLoop
7339 * "VF Stats Counters Missing a vertex when preemption enabled.
7341 * WA: Disable mid-draw preemption when the draw uses a lineloop
7344 if (draw
->mode
== PIPE_PRIM_LINE_LOOP
)
7345 object_preemption
= false;
7349 * "VF is corrupting GAFS data when preempted on an instance boundary
7350 * and replayed with instancing enabled.
7352 * WA: Disable preemption when using instanceing."
7354 if (draw
->instance_count
> 1)
7355 object_preemption
= false;
7357 if (genx
->object_preemption
!= object_preemption
) {
7358 iris_enable_obj_preemption(batch
, object_preemption
);
7359 genx
->object_preemption
= object_preemption
;
7365 iris_lost_genx_state(struct iris_context
*ice
, struct iris_batch
*batch
)
7367 struct iris_genx_state
*genx
= ice
->state
.genx
;
7369 memset(genx
->last_index_buffer
, 0, sizeof(genx
->last_index_buffer
));
7373 iris_emit_mi_report_perf_count(struct iris_batch
*batch
,
7375 uint32_t offset_in_bytes
,
7378 iris_emit_cmd(batch
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
7379 mi_rpc
.MemoryAddress
= rw_bo(bo
, offset_in_bytes
);
7380 mi_rpc
.ReportID
= report_id
;
7385 * Update the pixel hashing modes that determine the balancing of PS threads
7386 * across subslices and slices.
7388 * \param width Width bound of the rendering area (already scaled down if \p
7389 * scale is greater than 1).
7390 * \param height Height bound of the rendering area (already scaled down if \p
7391 * scale is greater than 1).
7392 * \param scale The number of framebuffer samples that could potentially be
7393 * affected by an individual channel of the PS thread. This is
7394 * typically one for single-sampled rendering, but for operations
7395 * like CCS resolves and fast clears a single PS invocation may
7396 * update a huge number of pixels, in which case a finer
7397 * balancing is desirable in order to maximally utilize the
7398 * bandwidth available. UINT_MAX can be used as shorthand for
7399 * "finest hashing mode available".
7402 genX(emit_hashing_mode
)(struct iris_context
*ice
, struct iris_batch
*batch
,
7403 unsigned width
, unsigned height
, unsigned scale
)
7406 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
7407 const unsigned slice_hashing
[] = {
7408 /* Because all Gen9 platforms with more than one slice require
7409 * three-way subslice hashing, a single "normal" 16x16 slice hashing
7410 * block is guaranteed to suffer from substantial imbalance, with one
7411 * subslice receiving twice as much work as the other two in the
7414 * The performance impact of that would be particularly severe when
7415 * three-way hashing is also in use for slice balancing (which is the
7416 * case for all Gen9 GT4 platforms), because one of the slices
7417 * receives one every three 16x16 blocks in either direction, which
7418 * is roughly the periodicity of the underlying subslice imbalance
7419 * pattern ("roughly" because in reality the hardware's
7420 * implementation of three-way hashing doesn't do exact modulo 3
7421 * arithmetic, which somewhat decreases the magnitude of this effect
7422 * in practice). This leads to a systematic subslice imbalance
7423 * within that slice regardless of the size of the primitive. The
7424 * 32x32 hashing mode guarantees that the subslice imbalance within a
7425 * single slice hashing block is minimal, largely eliminating this
7429 /* Finest slice hashing mode available. */
7432 const unsigned subslice_hashing
[] = {
7433 /* 16x16 would provide a slight cache locality benefit especially
7434 * visible in the sampler L1 cache efficiency of low-bandwidth
7435 * non-LLC platforms, but it comes at the cost of greater subslice
7436 * imbalance for primitives of dimensions approximately intermediate
7437 * between 16x4 and 16x16.
7440 /* Finest subslice hashing mode available. */
7443 /* Dimensions of the smallest hashing block of a given hashing mode. If
7444 * the rendering area is smaller than this there can't possibly be any
7445 * benefit from switching to this mode, so we optimize out the
7448 const unsigned min_size
[][2] = {
7452 const unsigned idx
= scale
> 1;
7454 if (width
> min_size
[idx
][0] || height
> min_size
[idx
][1]) {
7457 iris_pack_state(GENX(GT_MODE
), >_mode
, reg
) {
7458 reg
.SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0);
7459 reg
.SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0);
7460 reg
.SubsliceHashing
= subslice_hashing
[idx
];
7461 reg
.SubsliceHashingMask
= -1;
7464 iris_emit_raw_pipe_control(batch
,
7465 "workaround: CS stall before GT_MODE LRI",
7466 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
7467 PIPE_CONTROL_CS_STALL
,
7470 iris_emit_lri(batch
, GT_MODE
, gt_mode
);
7472 ice
->state
.current_hash_scale
= scale
;
7478 iris_set_frontend_noop(struct pipe_context
*ctx
, bool enable
)
7480 struct iris_context
*ice
= (struct iris_context
*) ctx
;
7482 ice
->state
.dirty
|= iris_batch_prepare_noop(&ice
->batches
[IRIS_BATCH_RENDER
],
7484 IRIS_ALL_DIRTY_FOR_RENDER
);
7485 ice
->state
.dirty
|= iris_batch_prepare_noop(&ice
->batches
[IRIS_BATCH_COMPUTE
],
7487 IRIS_ALL_DIRTY_FOR_COMPUTE
);
7491 genX(init_state
)(struct iris_context
*ice
)
7493 struct pipe_context
*ctx
= &ice
->ctx
;
7494 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
7496 ctx
->create_blend_state
= iris_create_blend_state
;
7497 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
7498 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
7499 ctx
->create_sampler_state
= iris_create_sampler_state
;
7500 ctx
->create_sampler_view
= iris_create_sampler_view
;
7501 ctx
->create_surface
= iris_create_surface
;
7502 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
7503 ctx
->bind_blend_state
= iris_bind_blend_state
;
7504 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
7505 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
7506 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
7507 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
7508 ctx
->delete_blend_state
= iris_delete_state
;
7509 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
7510 ctx
->delete_rasterizer_state
= iris_delete_state
;
7511 ctx
->delete_sampler_state
= iris_delete_state
;
7512 ctx
->delete_vertex_elements_state
= iris_delete_state
;
7513 ctx
->set_blend_color
= iris_set_blend_color
;
7514 ctx
->set_clip_state
= iris_set_clip_state
;
7515 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
7516 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
7517 ctx
->set_shader_images
= iris_set_shader_images
;
7518 ctx
->set_sampler_views
= iris_set_sampler_views
;
7519 ctx
->set_tess_state
= iris_set_tess_state
;
7520 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
7521 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
7522 ctx
->set_sample_mask
= iris_set_sample_mask
;
7523 ctx
->set_scissor_states
= iris_set_scissor_states
;
7524 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
7525 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
7526 ctx
->set_viewport_states
= iris_set_viewport_states
;
7527 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
7528 ctx
->surface_destroy
= iris_surface_destroy
;
7529 ctx
->draw_vbo
= iris_draw_vbo
;
7530 ctx
->launch_grid
= iris_launch_grid
;
7531 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
7532 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
7533 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
7534 ctx
->set_frontend_noop
= iris_set_frontend_noop
;
7536 ice
->vtbl
.destroy_state
= iris_destroy_state
;
7537 ice
->vtbl
.init_render_context
= iris_init_render_context
;
7538 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
7539 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
7540 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
7541 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
7542 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
7543 ice
->vtbl
.emit_mi_report_perf_count
= iris_emit_mi_report_perf_count
;
7544 ice
->vtbl
.rebind_buffer
= iris_rebind_buffer
;
7545 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
7546 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
7547 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
7548 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
7549 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
7550 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
7551 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
7552 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
7553 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
7554 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
7555 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
7556 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
7557 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
7558 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
7559 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
7560 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
7561 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
7562 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
7563 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
7564 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
7565 ice
->vtbl
.lost_genx_state
= iris_lost_genx_state
;
7567 ice
->state
.dirty
= ~0ull;
7569 ice
->state
.statistics_counters_enabled
= true;
7571 ice
->state
.sample_mask
= 0xffff;
7572 ice
->state
.num_viewports
= 1;
7573 ice
->state
.prim_mode
= PIPE_PRIM_MAX
;
7574 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
7575 ice
->draw
.derived_params
.drawid
= -1;
7577 /* Make a 1x1x1 null surface for unbound textures */
7578 void *null_surf_map
=
7579 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
7580 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
7581 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
7582 ice
->state
.unbound_tex
.offset
+=
7583 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
7585 /* Default all scissor rectangles to be empty regions. */
7586 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
7587 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
7588 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,