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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_dual_blend.h"
92 #include "util/u_inlines.h"
93 #include "util/u_format.h"
94 #include "util/u_framebuffer.h"
95 #include "util/u_transfer.h"
96 #include "util/u_upload_mgr.h"
97 #include "util/u_viewport.h"
98 #include "drm-uapi/i915_drm.h"
100 #include "intel/compiler/brw_compiler.h"
101 #include "intel/common/gen_l3_config.h"
102 #include "intel/common/gen_sample_positions.h"
103 #include "iris_batch.h"
104 #include "iris_context.h"
105 #include "iris_defines.h"
106 #include "iris_pipe.h"
107 #include "iris_resource.h"
109 #include "iris_genx_macros.h"
110 #include "intel/common/gen_guardband.h"
113 #define MOCS_PTE 0x18
116 #define MOCS_PTE (1 << 1)
117 #define MOCS_WB (2 << 1)
121 mocs(const struct iris_bo
*bo
)
123 return bo
&& bo
->external
? MOCS_PTE
: MOCS_WB
;
127 * Statically assert that PIPE_* enums match the hardware packets.
128 * (As long as they match, we don't need to translate them.)
130 UNUSED
static void pipe_asserts()
132 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
134 /* pipe_logicop happens to match the hardware. */
135 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
136 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
137 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
138 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
139 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
140 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
141 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
142 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
143 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
144 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
145 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
146 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
147 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
148 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
149 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
150 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
152 /* pipe_blend_func happens to match the hardware. */
153 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
160 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
161 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
162 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
163 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
164 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
165 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
166 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
167 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
168 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
169 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
170 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
171 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
173 /* pipe_blend_func happens to match the hardware. */
174 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
175 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
176 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
177 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
178 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
180 /* pipe_stencil_op happens to match the hardware. */
181 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
182 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
183 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
184 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
185 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
186 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
187 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
188 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
190 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
191 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
192 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
197 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
199 static const unsigned map
[] = {
200 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
201 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
202 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
203 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
204 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
205 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
206 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
207 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
208 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
209 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
210 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
211 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
212 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
213 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
214 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
217 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
221 translate_compare_func(enum pipe_compare_func pipe_func
)
223 static const unsigned map
[] = {
224 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
225 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
226 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
227 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
228 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
229 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
230 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
231 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
233 return map
[pipe_func
];
237 translate_shadow_func(enum pipe_compare_func pipe_func
)
239 /* Gallium specifies the result of shadow comparisons as:
241 * 1 if ref <op> texel,
246 * 0 if texel <op> ref,
249 * So we need to flip the operator and also negate.
251 static const unsigned map
[] = {
252 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
253 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
254 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
255 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
256 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
257 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
258 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
259 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
261 return map
[pipe_func
];
265 translate_cull_mode(unsigned pipe_face
)
267 static const unsigned map
[4] = {
268 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
269 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
270 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
271 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
273 return map
[pipe_face
];
277 translate_fill_mode(unsigned pipe_polymode
)
279 static const unsigned map
[4] = {
280 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
281 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
282 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
283 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
285 return map
[pipe_polymode
];
289 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
291 static const unsigned map
[] = {
292 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
293 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
294 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
296 return map
[pipe_mip
];
300 translate_wrap(unsigned pipe_wrap
)
302 static const unsigned map
[] = {
303 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
304 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
305 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
306 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
307 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
308 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
310 /* These are unsupported. */
311 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
312 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
314 return map
[pipe_wrap
];
318 * Allocate space for some indirect state.
320 * Return a pointer to the map (to fill it out) and a state ref (for
321 * referring to the state in GPU commands).
324 upload_state(struct u_upload_mgr
*uploader
,
325 struct iris_state_ref
*ref
,
330 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
335 * Stream out temporary/short-lived state.
337 * This allocates space, pins the BO, and includes the BO address in the
338 * returned offset (which works because all state lives in 32-bit memory
342 stream_state(struct iris_batch
*batch
,
343 struct u_upload_mgr
*uploader
,
344 struct pipe_resource
**out_res
,
347 uint32_t *out_offset
)
351 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
353 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
354 iris_use_pinned_bo(batch
, bo
, false);
356 *out_offset
+= iris_bo_offset_from_base_address(bo
);
358 iris_record_state_size(batch
->state_sizes
, *out_offset
, size
);
364 * stream_state() + memcpy.
367 emit_state(struct iris_batch
*batch
,
368 struct u_upload_mgr
*uploader
,
369 struct pipe_resource
**out_res
,
376 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
379 memcpy(map
, data
, size
);
385 * Did field 'x' change between 'old_cso' and 'new_cso'?
387 * (If so, we may want to set some dirty flags.)
389 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
390 #define cso_changed_memcmp(x) \
391 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
394 flush_for_state_base_change(struct iris_batch
*batch
)
396 /* Flush before emitting STATE_BASE_ADDRESS.
398 * This isn't documented anywhere in the PRM. However, it seems to be
399 * necessary prior to changing the surface state base adress. We've
400 * seen issues in Vulkan where we get GPU hangs when using multi-level
401 * command buffers which clear depth, reset state base address, and then
404 * Normally, in GL, we would trust the kernel to do sufficient stalls
405 * and flushes prior to executing our batch. However, it doesn't seem
406 * as if the kernel's flushing is always sufficient and we don't want to
409 * We make this an end-of-pipe sync instead of a normal flush because we
410 * do not know the current status of the GPU. On Haswell at least,
411 * having a fast-clear operation in flight at the same time as a normal
412 * rendering operation can cause hangs. Since the kernel's flushing is
413 * insufficient, we need to ensure that any rendering operations from
414 * other processes are definitely complete before we try to do our own
415 * rendering. It's a bit of a big hammer but it appears to work.
417 iris_emit_end_of_pipe_sync(batch
,
418 "change STATE_BASE_ADDRESS",
419 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
420 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
421 PIPE_CONTROL_DATA_CACHE_FLUSH
);
425 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
427 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
428 lri
.RegisterOffset
= reg
;
432 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
435 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
437 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
438 lrr
.SourceRegisterAddress
= src
;
439 lrr
.DestinationRegisterAddress
= dst
;
444 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
446 #if GEN_GEN >= 8 && GEN_GEN < 10
447 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
449 * Software must clear the COLOR_CALC_STATE Valid field in
450 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
451 * with Pipeline Select set to GPGPU.
453 * The internal hardware docs recommend the same workaround for Gen9
456 if (pipeline
== GPGPU
)
457 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
461 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
462 * PIPELINE_SELECT [DevBWR+]":
466 * Software must ensure all the write caches are flushed through a
467 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
468 * command to invalidate read only caches prior to programming
469 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
471 iris_emit_pipe_control_flush(batch
,
472 "workaround: PIPELINE_SELECT flushes (1/2)",
473 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
474 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
475 PIPE_CONTROL_DATA_CACHE_FLUSH
|
476 PIPE_CONTROL_CS_STALL
);
478 iris_emit_pipe_control_flush(batch
,
479 "workaround: PIPELINE_SELECT flushes (2/2)",
480 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
481 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
482 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
483 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
485 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
489 sel
.PipelineSelection
= pipeline
;
494 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
499 * "This chicken bit works around a hardware issue with barrier
500 * logic encountered when switching between GPGPU and 3D pipelines.
501 * To workaround the issue, this mode bit should be set after a
502 * pipeline is selected."
505 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
506 reg
.GLKBarrierMode
= value
;
507 reg
.GLKBarrierModeMask
= 1;
509 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
514 init_state_base_address(struct iris_batch
*batch
)
516 flush_for_state_base_change(batch
);
518 /* We program most base addresses once at context initialization time.
519 * Each base address points at a 4GB memory zone, and never needs to
520 * change. See iris_bufmgr.h for a description of the memory zones.
522 * The one exception is Surface State Base Address, which needs to be
523 * updated occasionally. See iris_binder.c for the details there.
525 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
526 sba
.GeneralStateMOCS
= MOCS_WB
;
527 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
528 sba
.DynamicStateMOCS
= MOCS_WB
;
529 sba
.IndirectObjectMOCS
= MOCS_WB
;
530 sba
.InstructionMOCS
= MOCS_WB
;
532 sba
.GeneralStateBaseAddressModifyEnable
= true;
533 sba
.DynamicStateBaseAddressModifyEnable
= true;
534 sba
.IndirectObjectBaseAddressModifyEnable
= true;
535 sba
.InstructionBaseAddressModifyEnable
= true;
536 sba
.GeneralStateBufferSizeModifyEnable
= true;
537 sba
.DynamicStateBufferSizeModifyEnable
= true;
539 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
540 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
542 sba
.IndirectObjectBufferSizeModifyEnable
= true;
543 sba
.InstructionBuffersizeModifyEnable
= true;
545 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
546 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
548 sba
.GeneralStateBufferSize
= 0xfffff;
549 sba
.IndirectObjectBufferSize
= 0xfffff;
550 sba
.InstructionBufferSize
= 0xfffff;
551 sba
.DynamicStateBufferSize
= 0xfffff;
556 iris_emit_l3_config(struct iris_batch
*batch
, const struct gen_l3_config
*cfg
,
557 bool has_slm
, bool wants_dc_cache
)
560 iris_pack_state(GENX(L3CNTLREG
), ®_val
, reg
) {
561 reg
.SLMEnable
= has_slm
;
563 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
564 * in L3CNTLREG register. The default setting of the bit is not the
565 * desirable behavior.
567 reg
.ErrorDetectionBehaviorControl
= true;
568 reg
.UseFullWays
= true;
570 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
571 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
572 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
573 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
575 iris_emit_lri(batch
, L3CNTLREG
, reg_val
);
579 iris_emit_default_l3_config(struct iris_batch
*batch
,
580 const struct gen_device_info
*devinfo
,
583 bool wants_dc_cache
= true;
584 bool has_slm
= compute
;
585 const struct gen_l3_weights w
=
586 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
587 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
588 iris_emit_l3_config(batch
, cfg
, has_slm
, wants_dc_cache
);
591 #if GEN_GEN == 9 || GEN_GEN == 10
593 iris_enable_obj_preemption(struct iris_batch
*batch
, bool enable
)
597 /* A fixed function pipe flush is required before modifying this field */
598 iris_emit_end_of_pipe_sync(batch
, enable
? "enable preemption"
599 : "disable preemption",
600 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
602 /* enable object level preemption */
603 iris_pack_state(GENX(CS_CHICKEN1
), ®_val
, reg
) {
604 reg
.ReplayMode
= enable
;
605 reg
.ReplayModeMask
= true;
607 iris_emit_lri(batch
, CS_CHICKEN1
, reg_val
);
612 * Upload the initial GPU state for a render context.
614 * This sets some invariant state that needs to be programmed a particular
615 * way, but we never actually change.
618 iris_init_render_context(struct iris_screen
*screen
,
619 struct iris_batch
*batch
,
620 struct iris_vtable
*vtbl
,
621 struct pipe_debug_callback
*dbg
)
623 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
626 emit_pipeline_select(batch
, _3D
);
628 iris_emit_default_l3_config(batch
, devinfo
, false);
630 init_state_base_address(batch
);
633 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
634 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
635 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
637 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
639 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
640 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
641 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
643 iris_emit_lri(batch
, INSTPM
, reg_val
);
647 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
648 reg
.FloatBlendOptimizationEnable
= true;
649 reg
.FloatBlendOptimizationEnableMask
= true;
650 reg
.PartialResolveDisableInVC
= true;
651 reg
.PartialResolveDisableInVCMask
= true;
653 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
655 if (devinfo
->is_geminilake
)
656 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
660 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
661 reg
.HeaderlessMessageforPreemptableContexts
= 1;
662 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
664 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
666 /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
667 iris_pack_state(GENX(HALF_SLICE_CHICKEN7
), ®_val
, reg
) {
668 reg
.EnabledTexelOffsetPrecisionFix
= 1;
669 reg
.EnabledTexelOffsetPrecisionFixMask
= 1;
671 iris_emit_lri(batch
, HALF_SLICE_CHICKEN7
, reg_val
);
673 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
674 reg
.StateCacheRedirectToCSSectionEnable
= true;
675 reg
.StateCacheRedirectToCSSectionEnableMask
= true;
677 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
679 /* Hardware specification recommends disabling repacking for the
680 * compatibility with decompression mechanism in display controller.
682 if (devinfo
->disable_ccs_repack
) {
683 iris_pack_state(GENX(CACHE_MODE_0
), ®_val
, reg
) {
684 reg
.DisableRepackingforCompression
= true;
685 reg
.DisableRepackingforCompressionMask
= true;
687 iris_emit_lri(batch
, CACHE_MODE_0
, reg_val
);
693 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
694 * changing it dynamically. We set it to the maximum size here, and
695 * instead include the render target dimensions in the viewport, so
696 * viewport extents clipping takes care of pruning stray geometry.
698 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
699 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
700 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
703 /* Set the initial MSAA sample positions. */
704 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
705 GEN_SAMPLE_POS_1X(pat
._1xSample
);
706 GEN_SAMPLE_POS_2X(pat
._2xSample
);
707 GEN_SAMPLE_POS_4X(pat
._4xSample
);
708 GEN_SAMPLE_POS_8X(pat
._8xSample
);
710 GEN_SAMPLE_POS_16X(pat
._16xSample
);
714 /* Use the legacy AA line coverage computation. */
715 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
717 /* Disable chromakeying (it's for media) */
718 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
720 /* We want regular rendering, not special HiZ operations. */
721 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
723 /* No polygon stippling offsets are necessary. */
724 /* TODO: may need to set an offset for origin-UL framebuffers */
725 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
727 /* Set a static partitioning of the push constant area. */
728 /* TODO: this may be a bad idea...could starve the push ringbuffers... */
729 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
730 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
731 alloc
._3DCommandSubOpcode
= 18 + i
;
732 alloc
.ConstantBufferOffset
= 6 * i
;
733 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
738 /* Gen11+ is enabled for us by the kernel. */
739 iris_enable_obj_preemption(batch
, true);
744 iris_init_compute_context(struct iris_screen
*screen
,
745 struct iris_batch
*batch
,
746 struct iris_vtable
*vtbl
,
747 struct pipe_debug_callback
*dbg
)
749 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
751 emit_pipeline_select(batch
, GPGPU
);
753 iris_emit_default_l3_config(batch
, devinfo
, true);
755 init_state_base_address(batch
);
758 if (devinfo
->is_geminilake
)
759 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
763 struct iris_vertex_buffer_state
{
764 /** The VERTEX_BUFFER_STATE hardware structure. */
765 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
767 /** The resource to source vertex data from. */
768 struct pipe_resource
*resource
;
771 struct iris_depth_buffer_state
{
772 /* Depth/HiZ/Stencil related hardware packets. */
773 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
774 GENX(3DSTATE_STENCIL_BUFFER_length
) +
775 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
776 GENX(3DSTATE_CLEAR_PARAMS_length
)];
780 * Generation-specific context state (ice->state.genx->...).
782 * Most state can go in iris_context directly, but these encode hardware
783 * packets which vary by generation.
785 struct iris_genx_state
{
786 struct iris_vertex_buffer_state vertex_buffers
[33];
788 struct iris_depth_buffer_state depth_buffer
;
790 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
793 /* Is object level preemption enabled? */
794 bool object_preemption
;
799 struct brw_image_param image_param
[PIPE_MAX_SHADER_IMAGES
];
801 } shaders
[MESA_SHADER_STAGES
];
805 * The pipe->set_blend_color() driver hook.
807 * This corresponds to our COLOR_CALC_STATE.
810 iris_set_blend_color(struct pipe_context
*ctx
,
811 const struct pipe_blend_color
*state
)
813 struct iris_context
*ice
= (struct iris_context
*) ctx
;
815 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
816 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
817 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
821 * Gallium CSO for blend state (see pipe_blend_state).
823 struct iris_blend_state
{
824 /** Partial 3DSTATE_PS_BLEND */
825 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
827 /** Partial BLEND_STATE */
828 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
829 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
831 bool alpha_to_coverage
; /* for shader key */
833 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
834 uint8_t blend_enables
;
836 /** Bitfield of whether color writes are enabled for RT[i] */
837 uint8_t color_write_enables
;
839 /** Does RT[0] use dual color blending? */
840 bool dual_color_blending
;
843 static enum pipe_blendfactor
844 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
847 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
848 return PIPE_BLENDFACTOR_ONE
;
850 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
851 return PIPE_BLENDFACTOR_ZERO
;
858 * The pipe->create_blend_state() driver hook.
860 * Translates a pipe_blend_state into iris_blend_state.
863 iris_create_blend_state(struct pipe_context
*ctx
,
864 const struct pipe_blend_state
*state
)
866 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
867 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
869 cso
->blend_enables
= 0;
870 cso
->color_write_enables
= 0;
871 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
873 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
875 bool indep_alpha_blend
= false;
877 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
878 const struct pipe_rt_blend_state
*rt
=
879 &state
->rt
[state
->independent_blend_enable
? i
: 0];
881 enum pipe_blendfactor src_rgb
=
882 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
883 enum pipe_blendfactor src_alpha
=
884 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
885 enum pipe_blendfactor dst_rgb
=
886 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
887 enum pipe_blendfactor dst_alpha
=
888 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
890 if (rt
->rgb_func
!= rt
->alpha_func
||
891 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
892 indep_alpha_blend
= true;
894 if (rt
->blend_enable
)
895 cso
->blend_enables
|= 1u << i
;
898 cso
->color_write_enables
|= 1u << i
;
900 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
901 be
.LogicOpEnable
= state
->logicop_enable
;
902 be
.LogicOpFunction
= state
->logicop_func
;
904 be
.PreBlendSourceOnlyClampEnable
= false;
905 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
906 be
.PreBlendColorClampEnable
= true;
907 be
.PostBlendColorClampEnable
= true;
909 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
911 be
.ColorBlendFunction
= rt
->rgb_func
;
912 be
.AlphaBlendFunction
= rt
->alpha_func
;
913 be
.SourceBlendFactor
= src_rgb
;
914 be
.SourceAlphaBlendFactor
= src_alpha
;
915 be
.DestinationBlendFactor
= dst_rgb
;
916 be
.DestinationAlphaBlendFactor
= dst_alpha
;
918 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
919 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
920 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
921 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
923 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
926 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
927 /* pb.HasWriteableRT is filled in at draw time.
928 * pb.AlphaTestEnable is filled in at draw time.
930 * pb.ColorBufferBlendEnable is filled in at draw time so we can avoid
931 * setting it when dual color blending without an appropriate shader.
934 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
935 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
937 pb
.SourceBlendFactor
=
938 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
939 pb
.SourceAlphaBlendFactor
=
940 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
941 pb
.DestinationBlendFactor
=
942 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
943 pb
.DestinationAlphaBlendFactor
=
944 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
947 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
948 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
949 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
950 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
951 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
952 bs
.ColorDitherEnable
= state
->dither
;
953 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
956 cso
->dual_color_blending
= util_blend_state_is_dual(state
, 0);
962 * The pipe->bind_blend_state() driver hook.
964 * Bind a blending CSO and flag related dirty bits.
967 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
969 struct iris_context
*ice
= (struct iris_context
*) ctx
;
970 struct iris_blend_state
*cso
= state
;
972 ice
->state
.cso_blend
= cso
;
973 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
975 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
976 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
977 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
978 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
982 * Return true if the FS writes to any color outputs which are not disabled
986 has_writeable_rt(const struct iris_blend_state
*cso_blend
,
987 const struct shader_info
*fs_info
)
992 unsigned rt_outputs
= fs_info
->outputs_written
>> FRAG_RESULT_DATA0
;
994 if (fs_info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
))
995 rt_outputs
= (1 << BRW_MAX_DRAW_BUFFERS
) - 1;
997 return cso_blend
->color_write_enables
& rt_outputs
;
1001 * Gallium CSO for depth, stencil, and alpha testing state.
1003 struct iris_depth_stencil_alpha_state
{
1004 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
1005 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1007 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
1008 struct pipe_alpha_state alpha
;
1010 /** Outbound to resolve and cache set tracking. */
1011 bool depth_writes_enabled
;
1012 bool stencil_writes_enabled
;
1016 * The pipe->create_depth_stencil_alpha_state() driver hook.
1018 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
1019 * testing state since we need pieces of it in a variety of places.
1022 iris_create_zsa_state(struct pipe_context
*ctx
,
1023 const struct pipe_depth_stencil_alpha_state
*state
)
1025 struct iris_depth_stencil_alpha_state
*cso
=
1026 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
1028 bool two_sided_stencil
= state
->stencil
[1].enabled
;
1030 cso
->alpha
= state
->alpha
;
1031 cso
->depth_writes_enabled
= state
->depth
.writemask
;
1032 cso
->stencil_writes_enabled
=
1033 state
->stencil
[0].writemask
!= 0 ||
1034 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1036 /* The state tracker needs to optimize away EQUAL writes for us. */
1037 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
1039 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
1040 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1041 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1042 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1043 wmds
.StencilTestFunction
=
1044 translate_compare_func(state
->stencil
[0].func
);
1045 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1046 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1047 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1048 wmds
.BackfaceStencilTestFunction
=
1049 translate_compare_func(state
->stencil
[1].func
);
1050 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1051 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1052 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1053 wmds
.StencilBufferWriteEnable
=
1054 state
->stencil
[0].writemask
!= 0 ||
1055 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1056 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1057 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1058 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1059 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1060 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1061 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1062 /* wmds.[Backface]StencilReferenceValue are merged later */
1069 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1071 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1074 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1076 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1077 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1078 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1081 if (cso_changed(alpha
.ref_value
))
1082 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1084 if (cso_changed(alpha
.enabled
))
1085 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1087 if (cso_changed(alpha
.func
))
1088 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1090 if (cso_changed(depth_writes_enabled
))
1091 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1093 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1094 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1097 ice
->state
.cso_zsa
= new_cso
;
1098 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1099 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1100 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1104 * Gallium CSO for rasterizer state.
1106 struct iris_rasterizer_state
{
1107 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1108 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1109 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1110 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1111 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1113 uint8_t num_clip_plane_consts
;
1114 bool clip_halfz
; /* for CC_VIEWPORT */
1115 bool depth_clip_near
; /* for CC_VIEWPORT */
1116 bool depth_clip_far
; /* for CC_VIEWPORT */
1117 bool flatshade
; /* for shader state */
1118 bool flatshade_first
; /* for stream output */
1119 bool clamp_fragment_color
; /* for shader state */
1120 bool light_twoside
; /* for shader state */
1121 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1122 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1123 bool line_stipple_enable
;
1124 bool poly_stipple_enable
;
1126 bool force_persample_interp
;
1127 bool conservative_rasterization
;
1128 bool fill_mode_point_or_line
;
1129 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1130 uint16_t sprite_coord_enable
;
1134 get_line_width(const struct pipe_rasterizer_state
*state
)
1136 float line_width
= state
->line_width
;
1138 /* From the OpenGL 4.4 spec:
1140 * "The actual width of non-antialiased lines is determined by rounding
1141 * the supplied width to the nearest integer, then clamping it to the
1142 * implementation-dependent maximum non-antialiased line width."
1144 if (!state
->multisample
&& !state
->line_smooth
)
1145 line_width
= roundf(state
->line_width
);
1147 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1148 /* For 1 pixel line thickness or less, the general anti-aliasing
1149 * algorithm gives up, and a garbage line is generated. Setting a
1150 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1151 * (one-pixel-wide), non-antialiased lines.
1153 * Lines rendered with zero Line Width are rasterized using the
1154 * "Grid Intersection Quantization" rules as specified by the
1155 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1164 * The pipe->create_rasterizer_state() driver hook.
1167 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1168 const struct pipe_rasterizer_state
*state
)
1170 struct iris_rasterizer_state
*cso
=
1171 malloc(sizeof(struct iris_rasterizer_state
));
1173 cso
->multisample
= state
->multisample
;
1174 cso
->force_persample_interp
= state
->force_persample_interp
;
1175 cso
->clip_halfz
= state
->clip_halfz
;
1176 cso
->depth_clip_near
= state
->depth_clip_near
;
1177 cso
->depth_clip_far
= state
->depth_clip_far
;
1178 cso
->flatshade
= state
->flatshade
;
1179 cso
->flatshade_first
= state
->flatshade_first
;
1180 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1181 cso
->light_twoside
= state
->light_twoside
;
1182 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1183 cso
->half_pixel_center
= state
->half_pixel_center
;
1184 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1185 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1186 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1187 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1188 cso
->conservative_rasterization
=
1189 state
->conservative_raster_mode
== PIPE_CONSERVATIVE_RASTER_POST_SNAP
;
1191 cso
->fill_mode_point_or_line
=
1192 state
->fill_front
== PIPE_POLYGON_MODE_LINE
||
1193 state
->fill_front
== PIPE_POLYGON_MODE_POINT
||
1194 state
->fill_back
== PIPE_POLYGON_MODE_LINE
||
1195 state
->fill_back
== PIPE_POLYGON_MODE_POINT
;
1197 if (state
->clip_plane_enable
!= 0)
1198 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1200 cso
->num_clip_plane_consts
= 0;
1202 float line_width
= get_line_width(state
);
1204 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1205 sf
.StatisticsEnable
= true;
1206 sf
.ViewportTransformEnable
= true;
1207 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1208 sf
.LineEndCapAntialiasingRegionWidth
=
1209 state
->line_smooth
? _10pixels
: _05pixels
;
1210 sf
.LastPixelEnable
= state
->line_last_pixel
;
1211 sf
.LineWidth
= line_width
;
1212 sf
.SmoothPointEnable
= (state
->point_smooth
|| state
->multisample
) &&
1213 !state
->point_quad_rasterization
;
1214 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1215 sf
.PointWidth
= state
->point_size
;
1217 if (state
->flatshade_first
) {
1218 sf
.TriangleFanProvokingVertexSelect
= 1;
1220 sf
.TriangleStripListProvokingVertexSelect
= 2;
1221 sf
.TriangleFanProvokingVertexSelect
= 2;
1222 sf
.LineStripListProvokingVertexSelect
= 1;
1226 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1227 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1228 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1229 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1230 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1231 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1232 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1233 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1234 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1235 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1236 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1237 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1238 rr
.SmoothPointEnable
= state
->point_smooth
;
1239 rr
.AntialiasingEnable
= state
->line_smooth
;
1240 rr
.ScissorRectangleEnable
= state
->scissor
;
1242 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1243 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1244 rr
.ConservativeRasterizationEnable
=
1245 cso
->conservative_rasterization
;
1247 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1251 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1252 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1253 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1255 cl
.EarlyCullEnable
= true;
1256 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1257 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1258 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1259 cl
.GuardbandClipTestEnable
= true;
1260 cl
.ClipEnable
= true;
1261 cl
.MinimumPointWidth
= 0.125;
1262 cl
.MaximumPointWidth
= 255.875;
1264 if (state
->flatshade_first
) {
1265 cl
.TriangleFanProvokingVertexSelect
= 1;
1267 cl
.TriangleStripListProvokingVertexSelect
= 2;
1268 cl
.TriangleFanProvokingVertexSelect
= 2;
1269 cl
.LineStripListProvokingVertexSelect
= 1;
1273 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1274 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1275 * filled in at draw time from the FS program.
1277 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1278 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1279 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1280 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1281 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1284 /* Remap from 0..255 back to 1..256 */
1285 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1287 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1288 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1289 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1290 line
.LineStippleRepeatCount
= line_stipple_factor
;
1297 * The pipe->bind_rasterizer_state() driver hook.
1299 * Bind a rasterizer CSO and flag related dirty bits.
1302 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1304 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1305 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1306 struct iris_rasterizer_state
*new_cso
= state
;
1309 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1310 if (cso_changed_memcmp(line_stipple
))
1311 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1313 if (cso_changed(half_pixel_center
))
1314 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1316 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1317 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1319 if (cso_changed(rasterizer_discard
))
1320 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1322 if (cso_changed(flatshade_first
))
1323 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1325 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1326 cso_changed(clip_halfz
))
1327 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1329 if (cso_changed(sprite_coord_enable
) ||
1330 cso_changed(sprite_coord_mode
) ||
1331 cso_changed(light_twoside
))
1332 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1334 if (cso_changed(conservative_rasterization
))
1335 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
1338 ice
->state
.cso_rast
= new_cso
;
1339 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1340 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1341 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1345 * Return true if the given wrap mode requires the border color to exist.
1347 * (We can skip uploading it if the sampler isn't going to use it.)
1350 wrap_mode_needs_border_color(unsigned wrap_mode
)
1352 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1356 * Gallium CSO for sampler state.
1358 struct iris_sampler_state
{
1359 union pipe_color_union border_color
;
1360 bool needs_border_color
;
1362 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1366 * The pipe->create_sampler_state() driver hook.
1368 * We fill out SAMPLER_STATE (except for the border color pointer), and
1369 * store that on the CPU. It doesn't make sense to upload it to a GPU
1370 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1371 * all bound sampler states to be in contiguous memor.
1374 iris_create_sampler_state(struct pipe_context
*ctx
,
1375 const struct pipe_sampler_state
*state
)
1377 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1382 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1383 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1385 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1386 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1387 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1389 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1391 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1392 wrap_mode_needs_border_color(wrap_t
) ||
1393 wrap_mode_needs_border_color(wrap_r
);
1395 float min_lod
= state
->min_lod
;
1396 unsigned mag_img_filter
= state
->mag_img_filter
;
1398 // XXX: explain this code ported from ilo...I don't get it at all...
1399 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1400 state
->min_lod
> 0.0f
) {
1402 mag_img_filter
= state
->min_img_filter
;
1405 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1406 samp
.TCXAddressControlMode
= wrap_s
;
1407 samp
.TCYAddressControlMode
= wrap_t
;
1408 samp
.TCZAddressControlMode
= wrap_r
;
1409 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1410 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1411 samp
.MinModeFilter
= state
->min_img_filter
;
1412 samp
.MagModeFilter
= mag_img_filter
;
1413 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1414 samp
.MaximumAnisotropy
= RATIO21
;
1416 if (state
->max_anisotropy
>= 2) {
1417 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1418 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1419 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1422 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1423 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1425 samp
.MaximumAnisotropy
=
1426 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1429 /* Set address rounding bits if not using nearest filtering. */
1430 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1431 samp
.UAddressMinFilterRoundingEnable
= true;
1432 samp
.VAddressMinFilterRoundingEnable
= true;
1433 samp
.RAddressMinFilterRoundingEnable
= true;
1436 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1437 samp
.UAddressMagFilterRoundingEnable
= true;
1438 samp
.VAddressMagFilterRoundingEnable
= true;
1439 samp
.RAddressMagFilterRoundingEnable
= true;
1442 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1443 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1445 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1447 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1448 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1449 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1450 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1452 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1459 * The pipe->bind_sampler_states() driver hook.
1462 iris_bind_sampler_states(struct pipe_context
*ctx
,
1463 enum pipe_shader_type p_stage
,
1464 unsigned start
, unsigned count
,
1467 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1468 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1469 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1471 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1473 for (int i
= 0; i
< count
; i
++) {
1474 shs
->samplers
[start
+ i
] = states
[i
];
1477 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1481 * Upload the sampler states into a contiguous area of GPU memory, for
1482 * for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1484 * Also fill out the border color state pointers.
1487 iris_upload_sampler_states(struct iris_context
*ice
, gl_shader_stage stage
)
1489 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1490 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
1492 /* We assume the state tracker will call pipe->bind_sampler_states()
1493 * if the program's number of textures changes.
1495 unsigned count
= info
? util_last_bit(info
->textures_used
) : 0;
1500 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1501 * in the dynamic state memory zone, so we can point to it via the
1502 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1504 unsigned size
= count
* 4 * GENX(SAMPLER_STATE_length
);
1506 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
, size
, 32);
1510 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1511 shs
->sampler_table
.offset
+=
1512 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1514 iris_record_state_size(ice
->state
.sizes
, shs
->sampler_table
.offset
, size
);
1516 /* Make sure all land in the same BO */
1517 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1519 ice
->state
.need_border_colors
&= ~(1 << stage
);
1521 for (int i
= 0; i
< count
; i
++) {
1522 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1523 struct iris_sampler_view
*tex
= shs
->textures
[i
];
1526 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1527 } else if (!state
->needs_border_color
) {
1528 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1530 ice
->state
.need_border_colors
|= 1 << stage
;
1532 /* We may need to swizzle the border color for format faking.
1533 * A/LA formats are faked as R/RG with 000R or R00G swizzles.
1534 * This means we need to move the border color's A channel into
1535 * the R or G channels so that those read swizzles will move it
1538 union pipe_color_union
*color
= &state
->border_color
;
1539 union pipe_color_union tmp
;
1541 enum pipe_format internal_format
= tex
->res
->internal_format
;
1543 if (util_format_is_alpha(internal_format
)) {
1544 unsigned char swz
[4] = {
1545 PIPE_SWIZZLE_W
, PIPE_SWIZZLE_0
,
1546 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1548 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1550 } else if (util_format_is_luminance_alpha(internal_format
) &&
1551 internal_format
!= PIPE_FORMAT_L8A8_SRGB
) {
1552 unsigned char swz
[4] = {
1553 PIPE_SWIZZLE_X
, PIPE_SWIZZLE_W
,
1554 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1556 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1561 /* Stream out the border color and merge the pointer. */
1562 uint32_t offset
= iris_upload_border_color(ice
, color
);
1564 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1565 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1566 dyns
.BorderColorPointer
= offset
;
1569 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1570 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1573 map
+= GENX(SAMPLER_STATE_length
);
1577 static enum isl_channel_select
1578 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1581 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1582 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1583 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1584 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1585 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1586 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1587 default: unreachable("invalid swizzle");
1592 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1593 struct iris_resource
*res
,
1595 enum isl_format format
,
1596 struct isl_swizzle swizzle
,
1600 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1601 const unsigned cpp
= format
== ISL_FORMAT_RAW
? 1 : fmtl
->bpb
/ 8;
1603 /* The ARB_texture_buffer_specification says:
1605 * "The number of texels in the buffer texture's texel array is given by
1607 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1609 * where <buffer_size> is the size of the buffer object, in basic
1610 * machine units and <components> and <base_type> are the element count
1611 * and base data type for elements, as specified in Table X.1. The
1612 * number of texels in the texel array is then clamped to the
1613 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1615 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1616 * so that when ISL divides by stride to obtain the number of texels, that
1617 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1619 unsigned final_size
=
1620 MIN3(size
, res
->bo
->size
- res
->offset
- offset
,
1621 IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1623 isl_buffer_fill_state(isl_dev
, map
,
1624 .address
= res
->bo
->gtt_offset
+ res
->offset
+ offset
,
1625 .size_B
= final_size
,
1629 .mocs
= mocs(res
->bo
));
1632 #define SURFACE_STATE_ALIGNMENT 64
1635 * Allocate several contiguous SURFACE_STATE structures, one for each
1636 * supported auxiliary surface mode.
1639 alloc_surface_states(struct u_upload_mgr
*mgr
,
1640 struct iris_state_ref
*ref
,
1641 unsigned aux_usages
)
1643 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
1645 /* If this changes, update this to explicitly align pointers */
1646 STATIC_ASSERT(surf_size
== SURFACE_STATE_ALIGNMENT
);
1648 assert(aux_usages
!= 0);
1651 upload_state(mgr
, ref
, util_bitcount(aux_usages
) * surf_size
,
1652 SURFACE_STATE_ALIGNMENT
);
1654 ref
->offset
+= iris_bo_offset_from_base_address(iris_resource_bo(ref
->res
));
1660 fill_surface_state(struct isl_device
*isl_dev
,
1662 struct iris_resource
*res
,
1663 struct isl_view
*view
,
1666 struct isl_surf_fill_state_info f
= {
1669 .mocs
= mocs(res
->bo
),
1670 .address
= res
->bo
->gtt_offset
+ res
->offset
,
1673 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1674 f
.aux_surf
= &res
->aux
.surf
;
1675 f
.aux_usage
= aux_usage
;
1676 f
.aux_address
= res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
;
1678 struct iris_bo
*clear_bo
= NULL
;
1679 uint64_t clear_offset
= 0;
1681 iris_resource_get_clear_color(res
, &clear_bo
, &clear_offset
);
1683 f
.clear_address
= clear_bo
->gtt_offset
+ clear_offset
;
1684 f
.use_clear_address
= isl_dev
->info
->gen
> 9;
1688 isl_surf_fill_state_s(isl_dev
, map
, &f
);
1692 * The pipe->create_sampler_view() driver hook.
1694 static struct pipe_sampler_view
*
1695 iris_create_sampler_view(struct pipe_context
*ctx
,
1696 struct pipe_resource
*tex
,
1697 const struct pipe_sampler_view
*tmpl
)
1699 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1700 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1701 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1702 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1707 /* initialize base object */
1709 isv
->base
.context
= ctx
;
1710 isv
->base
.texture
= NULL
;
1711 pipe_reference_init(&isv
->base
.reference
, 1);
1712 pipe_resource_reference(&isv
->base
.texture
, tex
);
1714 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1715 struct iris_resource
*zres
, *sres
;
1716 const struct util_format_description
*desc
=
1717 util_format_description(tmpl
->format
);
1719 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1721 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1724 isv
->res
= (struct iris_resource
*) tex
;
1726 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1727 &isv
->surface_state
,
1728 isv
->res
->aux
.sampler_usages
);
1732 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1734 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1735 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1736 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1738 const struct iris_format_info fmt
=
1739 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1741 isv
->clear_color
= isv
->res
->aux
.clear_color
;
1743 isv
->view
= (struct isl_view
) {
1745 .swizzle
= (struct isl_swizzle
) {
1746 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1747 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1748 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1749 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1754 /* Fill out SURFACE_STATE for this view. */
1755 if (tmpl
->target
!= PIPE_BUFFER
) {
1756 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1757 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1758 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1759 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1760 isv
->view
.array_len
=
1761 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1763 unsigned aux_modes
= isv
->res
->aux
.sampler_usages
;
1765 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1767 /* If we have a multisampled depth buffer, do not create a sampler
1768 * surface state with HiZ.
1770 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->view
,
1773 map
+= SURFACE_STATE_ALIGNMENT
;
1776 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
1777 isv
->view
.format
, isv
->view
.swizzle
,
1778 tmpl
->u
.buf
.offset
, tmpl
->u
.buf
.size
);
1785 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1786 struct pipe_sampler_view
*state
)
1788 struct iris_sampler_view
*isv
= (void *) state
;
1789 pipe_resource_reference(&state
->texture
, NULL
);
1790 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1795 * The pipe->create_surface() driver hook.
1797 * In Gallium nomenclature, "surfaces" are a view of a resource that
1798 * can be bound as a render target or depth/stencil buffer.
1800 static struct pipe_surface
*
1801 iris_create_surface(struct pipe_context
*ctx
,
1802 struct pipe_resource
*tex
,
1803 const struct pipe_surface
*tmpl
)
1805 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1806 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1807 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1809 isl_surf_usage_flags_t usage
= 0;
1811 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1812 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1813 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1815 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1817 const struct iris_format_info fmt
=
1818 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1820 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1821 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1822 /* Framebuffer validation will reject this invalid case, but it
1823 * hasn't had the opportunity yet. In the meantime, we need to
1824 * avoid hitting ISL asserts about unsupported formats below.
1829 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1830 struct pipe_surface
*psurf
= &surf
->base
;
1831 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1836 pipe_reference_init(&psurf
->reference
, 1);
1837 pipe_resource_reference(&psurf
->texture
, tex
);
1838 psurf
->context
= ctx
;
1839 psurf
->format
= tmpl
->format
;
1840 psurf
->width
= tex
->width0
;
1841 psurf
->height
= tex
->height0
;
1842 psurf
->texture
= tex
;
1843 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1844 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1845 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1847 struct isl_view
*view
= &surf
->view
;
1848 *view
= (struct isl_view
) {
1850 .base_level
= tmpl
->u
.tex
.level
,
1852 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1853 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1854 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1858 surf
->clear_color
= res
->aux
.clear_color
;
1860 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1861 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1862 ISL_SURF_USAGE_STENCIL_BIT
))
1866 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1867 &surf
->surface_state
,
1868 res
->aux
.possible_usages
);
1872 if (!isl_format_is_compressed(res
->surf
.format
)) {
1873 /* This is a normal surface. Fill out a SURFACE_STATE for each possible
1874 * auxiliary surface mode and return the pipe_surface.
1876 unsigned aux_modes
= res
->aux
.possible_usages
;
1878 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1880 fill_surface_state(&screen
->isl_dev
, map
, res
, view
, aux_usage
);
1882 map
+= SURFACE_STATE_ALIGNMENT
;
1888 /* The resource has a compressed format, which is not renderable, but we
1889 * have a renderable view format. We must be attempting to upload blocks
1890 * of compressed data via an uncompressed view.
1892 * In this case, we can assume there are no auxiliary buffers, a single
1893 * miplevel, and that the resource is single-sampled. Gallium may try
1894 * and create an uncompressed view with multiple layers, however.
1896 assert(!isl_format_is_compressed(fmt
.fmt
));
1897 assert(res
->aux
.possible_usages
== 1 << ISL_AUX_USAGE_NONE
);
1898 assert(res
->surf
.samples
== 1);
1899 assert(view
->levels
== 1);
1901 struct isl_surf isl_surf
;
1902 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
1904 if (view
->base_level
> 0) {
1905 /* We can't rely on the hardware's miplevel selection with such
1906 * a substantial lie about the format, so we select a single image
1907 * using the Tile X/Y Offset fields. In this case, we can't handle
1908 * multiple array slices.
1910 * On Broadwell, HALIGN and VALIGN are specified in pixels and are
1911 * hard-coded to align to exactly the block size of the compressed
1912 * texture. This means that, when reinterpreted as a non-compressed
1913 * texture, the tile offsets may be anything and we can't rely on
1916 * Return NULL to force the state tracker to take fallback paths.
1918 if (view
->array_len
> 1 || GEN_GEN
== 8)
1921 const bool is_3d
= res
->surf
.dim
== ISL_SURF_DIM_3D
;
1922 isl_surf_get_image_surf(&screen
->isl_dev
, &res
->surf
,
1924 is_3d
? 0 : view
->base_array_layer
,
1925 is_3d
? view
->base_array_layer
: 0,
1927 &offset_B
, &tile_x_sa
, &tile_y_sa
);
1929 /* We use address and tile offsets to access a single level/layer
1930 * as a subimage, so reset level/layer so it doesn't offset again.
1932 view
->base_array_layer
= 0;
1933 view
->base_level
= 0;
1935 /* Level 0 doesn't require tile offsets, and the hardware can find
1936 * array slices using QPitch even with the format override, so we
1937 * can allow layers in this case. Copy the original ISL surface.
1939 memcpy(&isl_surf
, &res
->surf
, sizeof(isl_surf
));
1942 /* Scale down the image dimensions by the block size. */
1943 const struct isl_format_layout
*fmtl
=
1944 isl_format_get_layout(res
->surf
.format
);
1945 isl_surf
.format
= fmt
.fmt
;
1946 isl_surf
.logical_level0_px
= isl_surf_get_logical_level0_el(&isl_surf
);
1947 isl_surf
.phys_level0_sa
= isl_surf_get_phys_level0_el(&isl_surf
);
1948 tile_x_sa
/= fmtl
->bw
;
1949 tile_y_sa
/= fmtl
->bh
;
1951 psurf
->width
= isl_surf
.logical_level0_px
.width
;
1952 psurf
->height
= isl_surf
.logical_level0_px
.height
;
1954 struct isl_surf_fill_state_info f
= {
1957 .mocs
= mocs(res
->bo
),
1958 .address
= res
->bo
->gtt_offset
+ offset_B
,
1959 .x_offset_sa
= tile_x_sa
,
1960 .y_offset_sa
= tile_y_sa
,
1963 isl_surf_fill_state_s(&screen
->isl_dev
, map
, &f
);
1969 fill_default_image_param(struct brw_image_param
*param
)
1971 memset(param
, 0, sizeof(*param
));
1972 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
1973 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
1974 * detailed explanation of these parameters.
1976 param
->swizzling
[0] = 0xff;
1977 param
->swizzling
[1] = 0xff;
1981 fill_buffer_image_param(struct brw_image_param
*param
,
1982 enum pipe_format pfmt
,
1985 const unsigned cpp
= util_format_get_blocksize(pfmt
);
1987 fill_default_image_param(param
);
1988 param
->size
[0] = size
/ cpp
;
1989 param
->stride
[0] = cpp
;
1992 #define isl_surf_fill_image_param(x, ...)
1993 #define fill_default_image_param(x, ...)
1994 #define fill_buffer_image_param(x, ...)
1998 * The pipe->set_shader_images() driver hook.
2001 iris_set_shader_images(struct pipe_context
*ctx
,
2002 enum pipe_shader_type p_stage
,
2003 unsigned start_slot
, unsigned count
,
2004 const struct pipe_image_view
*p_images
)
2006 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2007 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2008 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2009 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2010 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2012 struct iris_genx_state
*genx
= ice
->state
.genx
;
2013 struct brw_image_param
*image_params
= genx
->shaders
[stage
].image_param
;
2016 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
2018 for (unsigned i
= 0; i
< count
; i
++) {
2019 struct iris_image_view
*iv
= &shs
->image
[start_slot
+ i
];
2021 if (p_images
&& p_images
[i
].resource
) {
2022 const struct pipe_image_view
*img
= &p_images
[i
];
2023 struct iris_resource
*res
= (void *) img
->resource
;
2026 alloc_surface_states(ice
->state
.surface_uploader
,
2027 &iv
->surface_state
, 1 << ISL_AUX_USAGE_NONE
);
2031 util_copy_image_view(&iv
->base
, img
);
2033 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
2035 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
2037 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
2038 enum isl_format isl_fmt
=
2039 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
2041 bool untyped_fallback
= false;
2043 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
2044 /* On Gen8, try to use typed surfaces reads (which support a
2045 * limited number of formats), and if not possible, fall back
2048 untyped_fallback
= GEN_GEN
== 8 &&
2049 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
);
2051 if (untyped_fallback
)
2052 isl_fmt
= ISL_FORMAT_RAW
;
2054 isl_fmt
= isl_lower_storage_image_format(devinfo
, isl_fmt
);
2057 if (res
->base
.target
!= PIPE_BUFFER
) {
2058 struct isl_view view
= {
2060 .base_level
= img
->u
.tex
.level
,
2062 .base_array_layer
= img
->u
.tex
.first_layer
,
2063 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
2064 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2068 if (untyped_fallback
) {
2069 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2070 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2073 /* Images don't support compression */
2074 unsigned aux_modes
= 1 << ISL_AUX_USAGE_NONE
;
2076 enum isl_aux_usage usage
= u_bit_scan(&aux_modes
);
2078 fill_surface_state(&screen
->isl_dev
, map
, res
, &view
, usage
);
2080 map
+= SURFACE_STATE_ALIGNMENT
;
2084 isl_surf_fill_image_param(&screen
->isl_dev
,
2085 &image_params
[start_slot
+ i
],
2088 util_range_add(&res
->valid_buffer_range
, img
->u
.buf
.offset
,
2089 img
->u
.buf
.offset
+ img
->u
.buf
.size
);
2091 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2092 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2093 img
->u
.buf
.offset
, img
->u
.buf
.size
);
2094 fill_buffer_image_param(&image_params
[start_slot
+ i
],
2095 img
->format
, img
->u
.buf
.size
);
2098 pipe_resource_reference(&iv
->base
.resource
, NULL
);
2099 pipe_resource_reference(&iv
->surface_state
.res
, NULL
);
2100 fill_default_image_param(&image_params
[start_slot
+ i
]);
2104 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2106 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2107 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2109 /* Broadwell also needs brw_image_params re-uploaded */
2111 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2112 shs
->sysvals_need_upload
= true;
2118 * The pipe->set_sampler_views() driver hook.
2121 iris_set_sampler_views(struct pipe_context
*ctx
,
2122 enum pipe_shader_type p_stage
,
2123 unsigned start
, unsigned count
,
2124 struct pipe_sampler_view
**views
)
2126 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2127 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2128 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2130 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
2132 for (unsigned i
= 0; i
< count
; i
++) {
2133 struct pipe_sampler_view
*pview
= views
? views
[i
] : NULL
;
2134 pipe_sampler_view_reference((struct pipe_sampler_view
**)
2135 &shs
->textures
[start
+ i
], pview
);
2136 struct iris_sampler_view
*view
= (void *) pview
;
2138 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
2139 shs
->bound_sampler_views
|= 1 << (start
+ i
);
2143 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
2145 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2146 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2150 * The pipe->set_tess_state() driver hook.
2153 iris_set_tess_state(struct pipe_context
*ctx
,
2154 const float default_outer_level
[4],
2155 const float default_inner_level
[2])
2157 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2158 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
2160 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
2161 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
2163 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
2164 shs
->sysvals_need_upload
= true;
2168 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
2170 struct iris_surface
*surf
= (void *) p_surf
;
2171 pipe_resource_reference(&p_surf
->texture
, NULL
);
2172 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2177 iris_set_clip_state(struct pipe_context
*ctx
,
2178 const struct pipe_clip_state
*state
)
2180 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2181 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
2183 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
2185 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
;
2186 shs
->sysvals_need_upload
= true;
2190 * The pipe->set_polygon_stipple() driver hook.
2193 iris_set_polygon_stipple(struct pipe_context
*ctx
,
2194 const struct pipe_poly_stipple
*state
)
2196 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2197 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
2198 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
2202 * The pipe->set_sample_mask() driver hook.
2205 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2207 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2209 /* We only support 16x MSAA, so we have 16 bits of sample maks.
2210 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
2212 ice
->state
.sample_mask
= sample_mask
& 0xffff;
2213 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
2217 * The pipe->set_scissor_states() driver hook.
2219 * This corresponds to our SCISSOR_RECT state structures. It's an
2220 * exact match, so we just store them, and memcpy them out later.
2223 iris_set_scissor_states(struct pipe_context
*ctx
,
2224 unsigned start_slot
,
2225 unsigned num_scissors
,
2226 const struct pipe_scissor_state
*rects
)
2228 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2230 for (unsigned i
= 0; i
< num_scissors
; i
++) {
2231 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
2232 /* If the scissor was out of bounds and got clamped to 0 width/height
2233 * at the bounds, the subtraction of 1 from maximums could produce a
2234 * negative number and thus not clip anything. Instead, just provide
2235 * a min > max scissor inside the bounds, which produces the expected
2238 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2239 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
2242 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2243 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
2244 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
2249 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
2253 * The pipe->set_stencil_ref() driver hook.
2255 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
2258 iris_set_stencil_ref(struct pipe_context
*ctx
,
2259 const struct pipe_stencil_ref
*state
)
2261 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2262 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2264 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2266 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2270 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2272 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2276 * The pipe->set_viewport_states() driver hook.
2278 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2279 * the guardband yet, as we need the framebuffer dimensions, but we can
2280 * at least fill out the rest.
2283 iris_set_viewport_states(struct pipe_context
*ctx
,
2284 unsigned start_slot
,
2286 const struct pipe_viewport_state
*states
)
2288 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2290 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2292 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2294 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2295 !ice
->state
.cso_rast
->depth_clip_far
))
2296 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2300 * The pipe->set_framebuffer_state() driver hook.
2302 * Sets the current draw FBO, including color render targets, depth,
2303 * and stencil buffers.
2306 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2307 const struct pipe_framebuffer_state
*state
)
2309 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2310 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2311 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2312 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2313 struct iris_resource
*zres
;
2314 struct iris_resource
*stencil_res
;
2316 unsigned samples
= util_framebuffer_get_num_samples(state
);
2317 unsigned layers
= util_framebuffer_get_num_layers(state
);
2319 if (cso
->samples
!= samples
) {
2320 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2322 /* We need to toggle 3DSTATE_PS::32 Pixel Dispatch Enable */
2323 if (GEN_GEN
>= 9 && (cso
->samples
== 16 || samples
== 16))
2324 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
2327 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2328 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2331 if ((cso
->layers
== 0) != (layers
== 0)) {
2332 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2335 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2336 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2339 util_copy_framebuffer_state(cso
, state
);
2340 cso
->samples
= samples
;
2341 cso
->layers
= layers
;
2343 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2345 struct isl_view view
= {
2348 .base_array_layer
= 0,
2350 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2353 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
2356 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2359 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2360 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2362 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2365 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2367 info
.depth_surf
= &zres
->surf
;
2368 info
.depth_address
= zres
->bo
->gtt_offset
+ zres
->offset
;
2369 info
.mocs
= mocs(zres
->bo
);
2371 view
.format
= zres
->surf
.format
;
2373 if (iris_resource_level_has_hiz(zres
, view
.base_level
)) {
2374 info
.hiz_usage
= ISL_AUX_USAGE_HIZ
;
2375 info
.hiz_surf
= &zres
->aux
.surf
;
2376 info
.hiz_address
= zres
->aux
.bo
->gtt_offset
;
2381 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2382 info
.stencil_surf
= &stencil_res
->surf
;
2383 info
.stencil_address
= stencil_res
->bo
->gtt_offset
+ stencil_res
->offset
;
2385 view
.format
= stencil_res
->surf
.format
;
2386 info
.mocs
= mocs(stencil_res
->bo
);
2391 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2393 /* Make a null surface for unbound buffers */
2394 void *null_surf_map
=
2395 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2396 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2397 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2398 isl_extent3d(MAX2(cso
->width
, 1),
2399 MAX2(cso
->height
, 1),
2400 cso
->layers
? cso
->layers
: 1));
2401 ice
->state
.null_fb
.offset
+=
2402 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2404 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2406 /* Render target change */
2407 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2409 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2411 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2414 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2415 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2417 /* The PIPE_CONTROL command description says:
2419 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2420 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2421 * Target Cache Flush by enabling this bit. When render target flush
2422 * is set due to new association of BTI, PS Scoreboard Stall bit must
2423 * be set in this packet."
2425 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2426 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2427 "workaround: RT BTI change [draw]",
2428 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2429 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2434 * The pipe->set_constant_buffer() driver hook.
2436 * This uploads any constant data in user buffers, and references
2437 * any UBO resources containing constant data.
2440 iris_set_constant_buffer(struct pipe_context
*ctx
,
2441 enum pipe_shader_type p_stage
, unsigned index
,
2442 const struct pipe_constant_buffer
*input
)
2444 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2445 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2446 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2447 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[index
];
2449 if (input
&& input
->buffer_size
&& (input
->buffer
|| input
->user_buffer
)) {
2450 shs
->bound_cbufs
|= 1u << index
;
2452 if (input
->user_buffer
) {
2454 pipe_resource_reference(&cbuf
->buffer
, NULL
);
2455 u_upload_alloc(ice
->ctx
.const_uploader
, 0, input
->buffer_size
, 64,
2456 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
2458 if (!cbuf
->buffer
) {
2459 /* Allocation was unsuccessful - just unbind */
2460 iris_set_constant_buffer(ctx
, p_stage
, index
, NULL
);
2465 memcpy(map
, input
->user_buffer
, input
->buffer_size
);
2466 } else if (input
->buffer
) {
2467 pipe_resource_reference(&cbuf
->buffer
, input
->buffer
);
2469 cbuf
->buffer_offset
= input
->buffer_offset
;
2471 MIN2(input
->buffer_size
,
2472 iris_resource_bo(cbuf
->buffer
)->size
- cbuf
->buffer_offset
);
2475 struct iris_resource
*res
= (void *) cbuf
->buffer
;
2476 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2478 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
2479 &shs
->constbuf_surf_state
[index
],
2482 shs
->bound_cbufs
&= ~(1u << index
);
2483 pipe_resource_reference(&cbuf
->buffer
, NULL
);
2484 pipe_resource_reference(&shs
->constbuf_surf_state
[index
].res
, NULL
);
2487 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2488 // XXX: maybe not necessary all the time...?
2489 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2490 // XXX: pull model we may need actual new bindings...
2491 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2495 upload_sysvals(struct iris_context
*ice
,
2496 gl_shader_stage stage
)
2498 UNUSED
struct iris_genx_state
*genx
= ice
->state
.genx
;
2499 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2501 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2502 if (!shader
|| shader
->num_system_values
== 0)
2505 assert(shader
->num_cbufs
> 0);
2507 unsigned sysval_cbuf_index
= shader
->num_cbufs
- 1;
2508 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[sysval_cbuf_index
];
2509 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t);
2510 uint32_t *map
= NULL
;
2512 assert(sysval_cbuf_index
< PIPE_MAX_CONSTANT_BUFFERS
);
2513 u_upload_alloc(ice
->ctx
.const_uploader
, 0, upload_size
, 64,
2514 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
2516 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2517 uint32_t sysval
= shader
->system_values
[i
];
2520 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
2522 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
2523 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
2524 struct brw_image_param
*param
=
2525 &genx
->shaders
[stage
].image_param
[img
];
2527 assert(offset
< sizeof(struct brw_image_param
));
2528 value
= ((uint32_t *) param
)[offset
];
2530 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
2532 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2533 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2534 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2535 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2536 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
2537 if (stage
== MESA_SHADER_TESS_CTRL
) {
2538 value
= ice
->state
.vertices_per_patch
;
2540 assert(stage
== MESA_SHADER_TESS_EVAL
);
2541 const struct shader_info
*tcs_info
=
2542 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
2544 value
= tcs_info
->tess
.tcs_vertices_out
;
2546 value
= ice
->state
.vertices_per_patch
;
2548 } else if (sysval
>= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
&&
2549 sysval
<= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
) {
2550 unsigned i
= sysval
- BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
2551 value
= fui(ice
->state
.default_outer_level
[i
]);
2552 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
) {
2553 value
= fui(ice
->state
.default_inner_level
[0]);
2554 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
) {
2555 value
= fui(ice
->state
.default_inner_level
[1]);
2557 assert(!"unhandled system value");
2563 cbuf
->buffer_size
= upload_size
;
2564 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
2565 &shs
->constbuf_surf_state
[sysval_cbuf_index
], false);
2567 shs
->sysvals_need_upload
= false;
2571 * The pipe->set_shader_buffers() driver hook.
2573 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2574 * SURFACE_STATE here, as the buffer offset may change each time.
2577 iris_set_shader_buffers(struct pipe_context
*ctx
,
2578 enum pipe_shader_type p_stage
,
2579 unsigned start_slot
, unsigned count
,
2580 const struct pipe_shader_buffer
*buffers
,
2581 unsigned writable_bitmask
)
2583 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2584 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2585 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2587 unsigned modified_bits
= u_bit_consecutive(start_slot
, count
);
2589 shs
->bound_ssbos
&= ~modified_bits
;
2590 shs
->writable_ssbos
&= ~modified_bits
;
2591 shs
->writable_ssbos
|= writable_bitmask
<< start_slot
;
2593 for (unsigned i
= 0; i
< count
; i
++) {
2594 if (buffers
&& buffers
[i
].buffer
) {
2595 struct iris_resource
*res
= (void *) buffers
[i
].buffer
;
2596 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[start_slot
+ i
];
2597 struct iris_state_ref
*surf_state
=
2598 &shs
->ssbo_surf_state
[start_slot
+ i
];
2599 pipe_resource_reference(&ssbo
->buffer
, &res
->base
);
2600 ssbo
->buffer_offset
= buffers
[i
].buffer_offset
;
2602 MIN2(buffers
[i
].buffer_size
, res
->bo
->size
- ssbo
->buffer_offset
);
2604 shs
->bound_ssbos
|= 1 << (start_slot
+ i
);
2606 iris_upload_ubo_ssbo_surf_state(ice
, ssbo
, surf_state
, true);
2608 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2610 util_range_add(&res
->valid_buffer_range
, ssbo
->buffer_offset
,
2611 ssbo
->buffer_offset
+ ssbo
->buffer_size
);
2613 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
].buffer
, NULL
);
2614 pipe_resource_reference(&shs
->ssbo_surf_state
[start_slot
+ i
].res
,
2619 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2623 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2629 * The pipe->set_vertex_buffers() driver hook.
2631 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2634 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2635 unsigned start_slot
, unsigned count
,
2636 const struct pipe_vertex_buffer
*buffers
)
2638 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2639 struct iris_genx_state
*genx
= ice
->state
.genx
;
2641 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
2643 for (unsigned i
= 0; i
< count
; i
++) {
2644 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
2645 struct iris_vertex_buffer_state
*state
=
2646 &genx
->vertex_buffers
[start_slot
+ i
];
2649 pipe_resource_reference(&state
->resource
, NULL
);
2653 /* We may see user buffers that are NULL bindings. */
2654 assert(!(buffer
->is_user_buffer
&& buffer
->buffer
.user
!= NULL
));
2656 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
2657 struct iris_resource
*res
= (void *) state
->resource
;
2660 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
2661 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2664 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
2665 vb
.VertexBufferIndex
= start_slot
+ i
;
2666 vb
.AddressModifyEnable
= true;
2667 vb
.BufferPitch
= buffer
->stride
;
2669 vb
.BufferSize
= res
->bo
->size
- (int) buffer
->buffer_offset
;
2670 vb
.BufferStartingAddress
=
2671 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
2672 vb
.MOCS
= mocs(res
->bo
);
2674 vb
.NullVertexBuffer
= true;
2679 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2683 * Gallium CSO for vertex elements.
2685 struct iris_vertex_element_state
{
2686 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2687 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2688 uint32_t edgeflag_ve
[GENX(VERTEX_ELEMENT_STATE_length
)];
2689 uint32_t edgeflag_vfi
[GENX(3DSTATE_VF_INSTANCING_length
)];
2694 * The pipe->create_vertex_elements() driver hook.
2696 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2697 * and 3DSTATE_VF_INSTANCING commands. The vertex_elements and vf_instancing
2698 * arrays are ready to be emitted at draw time if no EdgeFlag or SGVs are
2699 * needed. In these cases we will need information available at draw time.
2700 * We setup edgeflag_ve and edgeflag_vfi as alternatives last
2701 * 3DSTATE_VERTEX_ELEMENT and 3DSTATE_VF_INSTANCING that can be used at
2702 * draw time if we detect that EdgeFlag is needed by the Vertex Shader.
2705 iris_create_vertex_elements(struct pipe_context
*ctx
,
2707 const struct pipe_vertex_element
*state
)
2709 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2710 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2711 struct iris_vertex_element_state
*cso
=
2712 malloc(sizeof(struct iris_vertex_element_state
));
2716 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2718 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2721 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2722 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2725 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2727 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2728 ve
.Component0Control
= VFCOMP_STORE_0
;
2729 ve
.Component1Control
= VFCOMP_STORE_0
;
2730 ve
.Component2Control
= VFCOMP_STORE_0
;
2731 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2734 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2738 for (int i
= 0; i
< count
; i
++) {
2739 const struct iris_format_info fmt
=
2740 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2741 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2742 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2744 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2745 case 0: comp
[0] = VFCOMP_STORE_0
; /* fallthrough */
2746 case 1: comp
[1] = VFCOMP_STORE_0
; /* fallthrough */
2747 case 2: comp
[2] = VFCOMP_STORE_0
; /* fallthrough */
2749 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2750 : VFCOMP_STORE_1_FP
;
2753 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2754 ve
.EdgeFlagEnable
= false;
2755 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2757 ve
.SourceElementOffset
= state
[i
].src_offset
;
2758 ve
.SourceElementFormat
= fmt
.fmt
;
2759 ve
.Component0Control
= comp
[0];
2760 ve
.Component1Control
= comp
[1];
2761 ve
.Component2Control
= comp
[2];
2762 ve
.Component3Control
= comp
[3];
2765 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2766 vi
.VertexElementIndex
= i
;
2767 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2768 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2771 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2772 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2775 /* An alternative version of the last VE and VFI is stored so it
2776 * can be used at draw time in case Vertex Shader uses EdgeFlag
2779 const unsigned edgeflag_index
= count
- 1;
2780 const struct iris_format_info fmt
=
2781 iris_format_for_usage(devinfo
, state
[edgeflag_index
].src_format
, 0);
2782 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), cso
->edgeflag_ve
, ve
) {
2783 ve
.EdgeFlagEnable
= true ;
2784 ve
.VertexBufferIndex
= state
[edgeflag_index
].vertex_buffer_index
;
2786 ve
.SourceElementOffset
= state
[edgeflag_index
].src_offset
;
2787 ve
.SourceElementFormat
= fmt
.fmt
;
2788 ve
.Component0Control
= VFCOMP_STORE_SRC
;
2789 ve
.Component1Control
= VFCOMP_STORE_0
;
2790 ve
.Component2Control
= VFCOMP_STORE_0
;
2791 ve
.Component3Control
= VFCOMP_STORE_0
;
2793 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->edgeflag_vfi
, vi
) {
2794 /* The vi.VertexElementIndex of the EdgeFlag Vertex Element is filled
2795 * at draw time, as it should change if SGVs are emitted.
2797 vi
.InstancingEnable
= state
[edgeflag_index
].instance_divisor
> 0;
2798 vi
.InstanceDataStepRate
= state
[edgeflag_index
].instance_divisor
;
2806 * The pipe->bind_vertex_elements_state() driver hook.
2809 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2811 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2812 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2813 struct iris_vertex_element_state
*new_cso
= state
;
2815 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2816 * we need to re-emit it to ensure we're overriding the right one.
2818 if (new_cso
&& cso_changed(count
))
2819 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2821 ice
->state
.cso_vertex_elements
= state
;
2822 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2826 * The pipe->create_stream_output_target() driver hook.
2828 * "Target" here refers to a destination buffer. We translate this into
2829 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2830 * know which buffer this represents, or whether we ought to zero the
2831 * write-offsets, or append. Those are handled in the set() hook.
2833 static struct pipe_stream_output_target
*
2834 iris_create_stream_output_target(struct pipe_context
*ctx
,
2835 struct pipe_resource
*p_res
,
2836 unsigned buffer_offset
,
2837 unsigned buffer_size
)
2839 struct iris_resource
*res
= (void *) p_res
;
2840 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2844 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
2846 pipe_reference_init(&cso
->base
.reference
, 1);
2847 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
2848 cso
->base
.buffer_offset
= buffer_offset
;
2849 cso
->base
.buffer_size
= buffer_size
;
2850 cso
->base
.context
= ctx
;
2852 util_range_add(&res
->valid_buffer_range
, buffer_offset
,
2853 buffer_offset
+ buffer_size
);
2855 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
2861 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2862 struct pipe_stream_output_target
*state
)
2864 struct iris_stream_output_target
*cso
= (void *) state
;
2866 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2867 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2873 * The pipe->set_stream_output_targets() driver hook.
2875 * At this point, we know which targets are bound to a particular index,
2876 * and also whether we want to append or start over. We can finish the
2877 * 3DSTATE_SO_BUFFER packets we started earlier.
2880 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2881 unsigned num_targets
,
2882 struct pipe_stream_output_target
**targets
,
2883 const unsigned *offsets
)
2885 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2886 struct iris_genx_state
*genx
= ice
->state
.genx
;
2887 uint32_t *so_buffers
= genx
->so_buffers
;
2889 const bool active
= num_targets
> 0;
2890 if (ice
->state
.streamout_active
!= active
) {
2891 ice
->state
.streamout_active
= active
;
2892 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2894 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
2895 * it's a non-pipelined command. If we're switching streamout on, we
2896 * may have missed emitting it earlier, so do so now. (We're already
2897 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
2900 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
2903 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2904 struct iris_stream_output_target
*tgt
=
2905 (void *) ice
->state
.so_target
[i
];
2907 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
2909 flush
|= iris_flush_bits_for_history(res
);
2910 iris_dirty_for_history(ice
, res
);
2913 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2914 "make streamout results visible", flush
);
2918 for (int i
= 0; i
< 4; i
++) {
2919 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2920 i
< num_targets
? targets
[i
] : NULL
);
2923 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2927 for (unsigned i
= 0; i
< 4; i
++,
2928 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2930 struct iris_stream_output_target
*tgt
= (void *) ice
->state
.so_target
[i
];
2931 unsigned offset
= offsets
[i
];
2934 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
2935 sob
.SOBufferIndex
= i
;
2939 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
2941 /* Note that offsets[i] will either be 0, causing us to zero
2942 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
2943 * "continue appending at the existing offset."
2945 assert(offset
== 0 || offset
== 0xFFFFFFFF);
2947 /* We might be called by Begin (offset = 0), Pause, then Resume
2948 * (offset = 0xFFFFFFFF) before ever drawing (where these commands
2949 * will actually be sent to the GPU). In this case, we don't want
2950 * to append - we still want to do our initial zeroing.
2955 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
2956 sob
.SurfaceBaseAddress
=
2957 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
2958 sob
.SOBufferEnable
= true;
2959 sob
.StreamOffsetWriteEnable
= true;
2960 sob
.StreamOutputBufferOffsetAddressEnable
= true;
2961 sob
.MOCS
= mocs(res
->bo
);
2963 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
2965 sob
.SOBufferIndex
= i
;
2966 sob
.StreamOffset
= offset
;
2967 sob
.StreamOutputBufferOffsetAddress
=
2968 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
2969 tgt
->offset
.offset
);
2973 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
2977 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
2978 * 3DSTATE_STREAMOUT packets.
2980 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
2981 * hardware to record. We can create it entirely based on the shader, with
2982 * no dynamic state dependencies.
2984 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
2985 * state-based settings. We capture the shader-related ones here, and merge
2986 * the rest in at draw time.
2989 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
2990 const struct brw_vue_map
*vue_map
)
2992 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2993 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2994 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2995 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2997 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2999 memset(so_decl
, 0, sizeof(so_decl
));
3001 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3002 * command feels strange -- each dword pair contains a SO_DECL per stream.
3004 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
3005 const struct pipe_stream_output
*output
= &info
->output
[i
];
3006 const int buffer
= output
->output_buffer
;
3007 const int varying
= output
->register_index
;
3008 const unsigned stream_id
= output
->stream
;
3009 assert(stream_id
< MAX_VERTEX_STREAMS
);
3011 buffer_mask
[stream_id
] |= 1 << buffer
;
3013 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3015 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3016 * array. Instead, it simply increments DstOffset for the following
3017 * input by the number of components that should be skipped.
3019 * Our hardware is unusual in that it requires us to program SO_DECLs
3020 * for fake "hole" components, rather than simply taking the offset
3021 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3022 * program as many size = 4 holes as we can, then a final hole to
3023 * accommodate the final 1, 2, or 3 remaining.
3025 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
3027 while (skip_components
> 0) {
3028 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3030 .OutputBufferSlot
= output
->output_buffer
,
3031 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3033 skip_components
-= 4;
3036 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
3038 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3039 .OutputBufferSlot
= output
->output_buffer
,
3040 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3042 ((1 << output
->num_components
) - 1) << output
->start_component
,
3045 if (decls
[stream_id
] > max_decls
)
3046 max_decls
= decls
[stream_id
];
3049 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
3050 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
3051 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
3053 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
3054 int urb_entry_read_offset
= 0;
3055 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3056 urb_entry_read_offset
;
3058 /* We always read the whole vertex. This could be reduced at some
3059 * point by reading less and offsetting the register index in the
3062 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3063 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3064 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3065 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3066 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3067 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3068 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3069 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3071 /* Set buffer pitches; 0 means unbound. */
3072 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
3073 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
3074 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
3075 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
3078 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
3079 list
.DWordLength
= 3 + 2 * max_decls
- 2;
3080 list
.StreamtoBufferSelects0
= buffer_mask
[0];
3081 list
.StreamtoBufferSelects1
= buffer_mask
[1];
3082 list
.StreamtoBufferSelects2
= buffer_mask
[2];
3083 list
.StreamtoBufferSelects3
= buffer_mask
[3];
3084 list
.NumEntries0
= decls
[0];
3085 list
.NumEntries1
= decls
[1];
3086 list
.NumEntries2
= decls
[2];
3087 list
.NumEntries3
= decls
[3];
3090 for (int i
= 0; i
< max_decls
; i
++) {
3091 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
3092 entry
.Stream0Decl
= so_decl
[0][i
];
3093 entry
.Stream1Decl
= so_decl
[1][i
];
3094 entry
.Stream2Decl
= so_decl
[2][i
];
3095 entry
.Stream3Decl
= so_decl
[3][i
];
3103 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
3104 const struct brw_vue_map
*last_vue_map
,
3105 bool two_sided_color
,
3106 unsigned *out_offset
,
3107 unsigned *out_length
)
3109 /* The compiler computes the first URB slot without considering COL/BFC
3110 * swizzling (because it doesn't know whether it's enabled), so we need
3111 * to do that here too. This may result in a smaller offset, which
3114 const unsigned first_slot
=
3115 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
3117 /* This becomes the URB read offset (counted in pairs of slots). */
3118 assert(first_slot
% 2 == 0);
3119 *out_offset
= first_slot
/ 2;
3121 /* We need to adjust the inputs read to account for front/back color
3122 * swizzling, as it can make the URB length longer.
3124 for (int c
= 0; c
<= 1; c
++) {
3125 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
3126 /* If two sided color is enabled, the fragment shader's gl_Color
3127 * (COL0) input comes from either the gl_FrontColor (COL0) or
3128 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
3130 if (two_sided_color
)
3131 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3133 /* If front color isn't written, we opt to give them back color
3134 * instead of an undefined value. Switch from COL to BFC.
3136 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
3137 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
3138 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3143 /* Compute the minimum URB Read Length necessary for the FS inputs.
3145 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
3146 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
3148 * "This field should be set to the minimum length required to read the
3149 * maximum source attribute. The maximum source attribute is indicated
3150 * by the maximum value of the enabled Attribute # Source Attribute if
3151 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
3152 * enable is not set.
3153 * read_length = ceiling((max_source_attr + 1) / 2)
3155 * [errata] Corruption/Hang possible if length programmed larger than
3158 * Similar text exists for Ivy Bridge.
3160 * We find the last URB slot that's actually read by the FS.
3162 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
3163 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
3164 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
3167 /* The URB read length is the difference of the two, counted in pairs. */
3168 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
3172 iris_emit_sbe_swiz(struct iris_batch
*batch
,
3173 const struct iris_context
*ice
,
3174 unsigned urb_read_offset
,
3175 unsigned sprite_coord_enables
)
3177 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
3178 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3179 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3180 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
3181 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3183 /* XXX: this should be generated when putting programs in place */
3185 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
3186 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
3187 if (input_index
< 0 || input_index
>= 16)
3190 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
3191 &attr_overrides
[input_index
];
3192 int slot
= vue_map
->varying_to_slot
[fs_attr
];
3194 /* Viewport and Layer are stored in the VUE header. We need to override
3195 * them to zero if earlier stages didn't write them, as GL requires that
3196 * they read back as zero when not explicitly set.
3199 case VARYING_SLOT_VIEWPORT
:
3200 case VARYING_SLOT_LAYER
:
3201 attr
->ComponentOverrideX
= true;
3202 attr
->ComponentOverrideW
= true;
3203 attr
->ConstantSource
= CONST_0000
;
3205 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
3206 attr
->ComponentOverrideY
= true;
3207 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
3208 attr
->ComponentOverrideZ
= true;
3211 case VARYING_SLOT_PRIMITIVE_ID
:
3212 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
3214 attr
->ComponentOverrideX
= true;
3215 attr
->ComponentOverrideY
= true;
3216 attr
->ComponentOverrideZ
= true;
3217 attr
->ComponentOverrideW
= true;
3218 attr
->ConstantSource
= PRIM_ID
;
3226 if (sprite_coord_enables
& (1 << input_index
))
3229 /* If there was only a back color written but not front, use back
3230 * as the color instead of undefined.
3232 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
3233 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
3234 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
3235 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
3237 /* Not written by the previous stage - undefined. */
3239 attr
->ComponentOverrideX
= true;
3240 attr
->ComponentOverrideY
= true;
3241 attr
->ComponentOverrideZ
= true;
3242 attr
->ComponentOverrideW
= true;
3243 attr
->ConstantSource
= CONST_0001_FLOAT
;
3247 /* Compute the location of the attribute relative to the read offset,
3248 * which is counted in 256-bit increments (two 128-bit VUE slots).
3250 const int source_attr
= slot
- 2 * urb_read_offset
;
3251 assert(source_attr
>= 0 && source_attr
<= 32);
3252 attr
->SourceAttribute
= source_attr
;
3254 /* If we are doing two-sided color, and the VUE slot following this one
3255 * represents a back-facing color, then we need to instruct the SF unit
3256 * to do back-facing swizzling.
3258 if (cso_rast
->light_twoside
&&
3259 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3260 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3261 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3262 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3263 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3266 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3267 for (int i
= 0; i
< 16; i
++)
3268 sbes
.Attribute
[i
] = attr_overrides
[i
];
3273 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3274 const struct iris_rasterizer_state
*cso
)
3276 unsigned overrides
= 0;
3278 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
3279 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
3281 for (int i
= 0; i
< 8; i
++) {
3282 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
3283 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
3284 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
3291 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
3293 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3294 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3295 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3296 const struct shader_info
*fs_info
=
3297 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
3299 unsigned urb_read_offset
, urb_read_length
;
3300 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
3301 ice
->shaders
.last_vue_map
,
3302 cso_rast
->light_twoside
,
3303 &urb_read_offset
, &urb_read_length
);
3305 unsigned sprite_coord_overrides
=
3306 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3308 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
3309 sbe
.AttributeSwizzleEnable
= true;
3310 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3311 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3312 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3313 sbe
.VertexURBEntryReadLength
= urb_read_length
;
3314 sbe
.ForceVertexURBEntryReadOffset
= true;
3315 sbe
.ForceVertexURBEntryReadLength
= true;
3316 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3317 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
3319 for (int i
= 0; i
< 32; i
++) {
3320 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3325 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
3328 /* ------------------------------------------------------------------- */
3331 * Populate VS program key fields based on the current state.
3334 iris_populate_vs_key(const struct iris_context
*ice
,
3335 const struct shader_info
*info
,
3336 struct brw_vs_prog_key
*key
)
3338 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3340 if (info
->clip_distance_array_size
== 0 &&
3341 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)))
3342 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3346 * Populate TCS program key fields based on the current state.
3349 iris_populate_tcs_key(const struct iris_context
*ice
,
3350 struct brw_tcs_prog_key
*key
)
3355 * Populate TES program key fields based on the current state.
3358 iris_populate_tes_key(const struct iris_context
*ice
,
3359 struct brw_tes_prog_key
*key
)
3364 * Populate GS program key fields based on the current state.
3367 iris_populate_gs_key(const struct iris_context
*ice
,
3368 struct brw_gs_prog_key
*key
)
3373 * Populate FS program key fields based on the current state.
3376 iris_populate_fs_key(const struct iris_context
*ice
,
3377 const struct shader_info
*info
,
3378 struct brw_wm_prog_key
*key
)
3380 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3381 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3382 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3383 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3384 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3386 key
->nr_color_regions
= fb
->nr_cbufs
;
3388 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3390 key
->alpha_to_coverage
= blend
->alpha_to_coverage
;
3392 key
->alpha_test_replicate_alpha
= fb
->nr_cbufs
> 1 && zsa
->alpha
.enabled
;
3394 key
->flat_shade
= rast
->flatshade
&&
3395 (info
->inputs_read
& (VARYING_BIT_COL0
| VARYING_BIT_COL1
));
3397 key
->persample_interp
= rast
->force_persample_interp
;
3398 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3400 key
->coherent_fb_fetch
= true;
3402 key
->force_dual_color_blend
=
3403 screen
->driconf
.dual_color_blend_by_location
&&
3404 (blend
->blend_enables
& 1) && blend
->dual_color_blending
;
3406 /* TODO: Respect glHint for key->high_quality_derivatives */
3410 iris_populate_cs_key(const struct iris_context
*ice
,
3411 struct brw_cs_prog_key
*key
)
3416 KSP(const struct iris_compiled_shader
*shader
)
3418 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3419 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3422 /* Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3423 * prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3424 * this WA on C0 stepping.
3426 * TODO: Fill out SamplerCount for prefetching?
3429 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3430 pkt.KernelStartPointer = KSP(shader); \
3431 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3432 shader->bt.size_bytes / 4; \
3433 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3435 pkt.DispatchGRFStartRegisterForURBData = \
3436 prog_data->dispatch_grf_start_reg; \
3437 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3438 pkt.prefix##URBEntryReadOffset = 0; \
3440 pkt.StatisticsEnable = true; \
3441 pkt.Enable = true; \
3443 if (prog_data->total_scratch) { \
3444 struct iris_bo *bo = \
3445 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3446 uint32_t scratch_addr = bo->gtt_offset; \
3447 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3448 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3452 * Encode most of 3DSTATE_VS based on the compiled shader.
3455 iris_store_vs_state(struct iris_context
*ice
,
3456 const struct gen_device_info
*devinfo
,
3457 struct iris_compiled_shader
*shader
)
3459 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3460 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3462 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3463 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3464 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3465 vs
.SIMD8DispatchEnable
= true;
3466 vs
.UserClipDistanceCullTestEnableBitmask
=
3467 vue_prog_data
->cull_distance_mask
;
3472 * Encode most of 3DSTATE_HS based on the compiled shader.
3475 iris_store_tcs_state(struct iris_context
*ice
,
3476 const struct gen_device_info
*devinfo
,
3477 struct iris_compiled_shader
*shader
)
3479 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3480 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3481 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3483 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3484 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3486 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3487 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3488 hs
.IncludeVertexHandles
= true;
3491 hs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
3492 hs
.IncludePrimitiveID
= tcs_prog_data
->include_primitive_id
;
3498 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3501 iris_store_tes_state(struct iris_context
*ice
,
3502 const struct gen_device_info
*devinfo
,
3503 struct iris_compiled_shader
*shader
)
3505 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3506 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3507 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3509 uint32_t *te_state
= (void *) shader
->derived_data
;
3510 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3512 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3513 te
.Partitioning
= tes_prog_data
->partitioning
;
3514 te
.OutputTopology
= tes_prog_data
->output_topology
;
3515 te
.TEDomain
= tes_prog_data
->domain
;
3517 te
.MaximumTessellationFactorOdd
= 63.0;
3518 te
.MaximumTessellationFactorNotOdd
= 64.0;
3521 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3522 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3524 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3525 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3526 ds
.ComputeWCoordinateEnable
=
3527 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3529 ds
.UserClipDistanceCullTestEnableBitmask
=
3530 vue_prog_data
->cull_distance_mask
;
3536 * Encode most of 3DSTATE_GS based on the compiled shader.
3539 iris_store_gs_state(struct iris_context
*ice
,
3540 const struct gen_device_info
*devinfo
,
3541 struct iris_compiled_shader
*shader
)
3543 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3544 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3545 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3547 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3548 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3550 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3551 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3552 gs
.ControlDataHeaderSize
=
3553 gs_prog_data
->control_data_header_size_hwords
;
3554 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3555 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3556 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3557 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3558 gs
.ReorderMode
= TRAILING
;
3559 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3560 gs
.MaximumNumberofThreads
=
3561 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3562 : (devinfo
->max_gs_threads
- 1);
3564 if (gs_prog_data
->static_vertex_count
!= -1) {
3565 gs
.StaticOutput
= true;
3566 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3568 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3570 gs
.UserClipDistanceCullTestEnableBitmask
=
3571 vue_prog_data
->cull_distance_mask
;
3573 const int urb_entry_write_offset
= 1;
3574 const uint32_t urb_entry_output_length
=
3575 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3576 urb_entry_write_offset
;
3578 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3579 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3584 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3587 iris_store_fs_state(struct iris_context
*ice
,
3588 const struct gen_device_info
*devinfo
,
3589 struct iris_compiled_shader
*shader
)
3591 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3592 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3594 uint32_t *ps_state
= (void *) shader
->derived_data
;
3595 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3597 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3598 ps
.VectorMaskEnable
= true;
3599 // XXX: WABTPPrefetchDisable, see above, drop at C0
3600 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3601 shader
->bt
.size_bytes
/ 4;
3602 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3603 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3605 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
3607 /* From the documentation for this packet:
3608 * "If the PS kernel does not need the Position XY Offsets to
3609 * compute a Position Value, then this field should be programmed
3610 * to POSOFFSET_NONE."
3612 * "SW Recommendation: If the PS kernel needs the Position Offsets
3613 * to compute a Position XY value, this field should match Position
3614 * ZW Interpolation Mode to ensure a consistent position.xyzw
3617 * We only require XY sample offsets. So, this recommendation doesn't
3618 * look useful at the moment. We might need this in future.
3620 ps
.PositionXYOffsetSelect
=
3621 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3622 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
3623 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
3624 /* ps._32PixelDispatchEnable is filled in at draw time. */
3626 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3627 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
3628 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
3629 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
3630 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3631 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
3633 ps
.KernelStartPointer0
=
3634 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
3635 ps
.KernelStartPointer1
=
3636 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
3637 ps
.KernelStartPointer2
=
3638 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
3640 if (prog_data
->total_scratch
) {
3641 struct iris_bo
*bo
=
3642 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3643 MESA_SHADER_FRAGMENT
);
3644 uint32_t scratch_addr
= bo
->gtt_offset
;
3645 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3646 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3650 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3651 psx
.PixelShaderValid
= true;
3652 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3653 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
3654 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3655 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3656 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3657 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3658 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3661 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3662 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3664 psx
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
3670 * Compute the size of the derived data (shader command packets).
3672 * This must match the data written by the iris_store_xs_state() functions.
3675 iris_store_cs_state(struct iris_context
*ice
,
3676 const struct gen_device_info
*devinfo
,
3677 struct iris_compiled_shader
*shader
)
3679 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3680 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3681 void *map
= shader
->derived_data
;
3683 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3684 desc
.KernelStartPointer
= KSP(shader
);
3685 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3686 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3687 desc
.SharedLocalMemorySize
=
3688 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3689 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3690 desc
.CrossThreadConstantDataReadLength
=
3691 cs_prog_data
->push
.cross_thread
.regs
;
3696 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3698 assert(cache_id
<= IRIS_CACHE_BLORP
);
3700 static const unsigned dwords
[] = {
3701 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3702 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3703 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3704 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3706 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3707 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3708 [IRIS_CACHE_BLORP
] = 0,
3711 return sizeof(uint32_t) * dwords
[cache_id
];
3715 * Create any state packets corresponding to the given shader stage
3716 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3717 * This means that we can look up a program in the in-memory cache and
3718 * get most of the state packet without having to reconstruct it.
3721 iris_store_derived_program_state(struct iris_context
*ice
,
3722 enum iris_program_cache_id cache_id
,
3723 struct iris_compiled_shader
*shader
)
3725 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3726 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3730 iris_store_vs_state(ice
, devinfo
, shader
);
3732 case IRIS_CACHE_TCS
:
3733 iris_store_tcs_state(ice
, devinfo
, shader
);
3735 case IRIS_CACHE_TES
:
3736 iris_store_tes_state(ice
, devinfo
, shader
);
3739 iris_store_gs_state(ice
, devinfo
, shader
);
3742 iris_store_fs_state(ice
, devinfo
, shader
);
3745 iris_store_cs_state(ice
, devinfo
, shader
);
3746 case IRIS_CACHE_BLORP
:
3753 /* ------------------------------------------------------------------- */
3755 static const uint32_t push_constant_opcodes
[] = {
3756 [MESA_SHADER_VERTEX
] = 21,
3757 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3758 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3759 [MESA_SHADER_GEOMETRY
] = 22,
3760 [MESA_SHADER_FRAGMENT
] = 23,
3761 [MESA_SHADER_COMPUTE
] = 0,
3765 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3767 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3769 iris_use_pinned_bo(batch
, state_bo
, false);
3771 return ice
->state
.unbound_tex
.offset
;
3775 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3777 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3778 if (!ice
->state
.null_fb
.res
)
3779 return use_null_surface(batch
, ice
);
3781 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3783 iris_use_pinned_bo(batch
, state_bo
, false);
3785 return ice
->state
.null_fb
.offset
;
3789 surf_state_offset_for_aux(struct iris_resource
*res
,
3791 enum isl_aux_usage aux_usage
)
3793 return SURFACE_STATE_ALIGNMENT
*
3794 util_bitcount(res
->aux
.possible_usages
& ((1 << aux_usage
) - 1));
3798 surf_state_update_clear_value(struct iris_batch
*batch
,
3799 struct iris_resource
*res
,
3800 struct iris_state_ref
*state
,
3802 enum isl_aux_usage aux_usage
)
3804 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
3805 struct iris_bo
*state_bo
= iris_resource_bo(state
->res
);
3806 uint64_t real_offset
= state
->offset
+
3807 IRIS_MEMZONE_BINDER_START
;
3808 uint32_t offset_into_bo
= real_offset
- state_bo
->gtt_offset
;
3809 uint32_t clear_offset
= offset_into_bo
+
3810 isl_dev
->ss
.clear_value_offset
+
3811 surf_state_offset_for_aux(res
, aux_modes
, aux_usage
);
3813 batch
->vtbl
->copy_mem_mem(batch
, state_bo
, clear_offset
,
3814 res
->aux
.clear_color_bo
,
3815 res
->aux
.clear_color_offset
,
3816 isl_dev
->ss
.clear_value_size
);
3820 update_clear_value(struct iris_context
*ice
,
3821 struct iris_batch
*batch
,
3822 struct iris_resource
*res
,
3823 struct iris_state_ref
*state
,
3825 struct isl_view
*view
)
3827 struct iris_screen
*screen
= batch
->screen
;
3828 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3830 /* We only need to update the clear color in the surface state for gen8 and
3831 * gen9. Newer gens can read it directly from the clear color state buffer.
3833 if (devinfo
->gen
> 9)
3836 if (devinfo
->gen
== 9) {
3837 /* Skip updating the ISL_AUX_USAGE_NONE surface state */
3838 aux_modes
&= ~(1 << ISL_AUX_USAGE_NONE
);
3841 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
3843 surf_state_update_clear_value(batch
, res
, state
, aux_modes
,
3846 } else if (devinfo
->gen
== 8) {
3847 pipe_resource_reference(&state
->res
, NULL
);
3848 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
3849 state
, res
->aux
.possible_usages
);
3851 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
3852 fill_surface_state(&screen
->isl_dev
, map
, res
, view
, aux_usage
);
3853 map
+= SURFACE_STATE_ALIGNMENT
;
3859 * Add a surface to the validation list, as well as the buffer containing
3860 * the corresponding SURFACE_STATE.
3862 * Returns the binding table entry (offset to SURFACE_STATE).
3865 use_surface(struct iris_context
*ice
,
3866 struct iris_batch
*batch
,
3867 struct pipe_surface
*p_surf
,
3869 enum isl_aux_usage aux_usage
)
3871 struct iris_surface
*surf
= (void *) p_surf
;
3872 struct iris_resource
*res
= (void *) p_surf
->texture
;
3874 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
3875 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
3878 iris_use_pinned_bo(batch
, res
->aux
.bo
, writeable
);
3879 if (res
->aux
.clear_color_bo
)
3880 iris_use_pinned_bo(batch
, res
->aux
.clear_color_bo
, false);
3882 if (memcmp(&res
->aux
.clear_color
, &surf
->clear_color
,
3883 sizeof(surf
->clear_color
)) != 0) {
3884 update_clear_value(ice
, batch
, res
, &surf
->surface_state
,
3885 res
->aux
.possible_usages
, &surf
->view
);
3886 surf
->clear_color
= res
->aux
.clear_color
;
3890 return surf
->surface_state
.offset
+
3891 surf_state_offset_for_aux(res
, res
->aux
.possible_usages
, aux_usage
);
3895 use_sampler_view(struct iris_context
*ice
,
3896 struct iris_batch
*batch
,
3897 struct iris_sampler_view
*isv
)
3900 enum isl_aux_usage aux_usage
=
3901 iris_resource_texture_aux_usage(ice
, isv
->res
, isv
->view
.format
, 0);
3903 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
3904 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
3906 if (isv
->res
->aux
.bo
) {
3907 iris_use_pinned_bo(batch
, isv
->res
->aux
.bo
, false);
3908 if (isv
->res
->aux
.clear_color_bo
)
3909 iris_use_pinned_bo(batch
, isv
->res
->aux
.clear_color_bo
, false);
3910 if (memcmp(&isv
->res
->aux
.clear_color
, &isv
->clear_color
,
3911 sizeof(isv
->clear_color
)) != 0) {
3912 update_clear_value(ice
, batch
, isv
->res
, &isv
->surface_state
,
3913 isv
->res
->aux
.sampler_usages
, &isv
->view
);
3914 isv
->clear_color
= isv
->res
->aux
.clear_color
;
3918 return isv
->surface_state
.offset
+
3919 surf_state_offset_for_aux(isv
->res
, isv
->res
->aux
.sampler_usages
,
3924 use_ubo_ssbo(struct iris_batch
*batch
,
3925 struct iris_context
*ice
,
3926 struct pipe_shader_buffer
*buf
,
3927 struct iris_state_ref
*surf_state
,
3931 return use_null_surface(batch
, ice
);
3933 iris_use_pinned_bo(batch
, iris_resource_bo(buf
->buffer
), writable
);
3934 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3936 return surf_state
->offset
;
3940 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
3941 struct iris_shader_state
*shs
, int i
)
3943 struct iris_image_view
*iv
= &shs
->image
[i
];
3944 struct iris_resource
*res
= (void *) iv
->base
.resource
;
3947 return use_null_surface(batch
, ice
);
3949 bool write
= iv
->base
.shader_access
& PIPE_IMAGE_ACCESS_WRITE
;
3951 iris_use_pinned_bo(batch
, res
->bo
, write
);
3952 iris_use_pinned_bo(batch
, iris_resource_bo(iv
->surface_state
.res
), false);
3955 iris_use_pinned_bo(batch
, res
->aux
.bo
, write
);
3957 return iv
->surface_state
.offset
;
3960 #define push_bt_entry(addr) \
3961 assert(addr >= binder_addr); \
3962 assert(s < shader->bt.size_bytes / sizeof(uint32_t)); \
3963 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
3965 #define bt_assert(section) \
3966 if (!pin_only && shader->bt.used_mask[section] != 0) \
3967 assert(shader->bt.offsets[section] == s);
3970 * Populate the binding table for a given shader stage.
3972 * This fills out the table of pointers to surfaces required by the shader,
3973 * and also adds those buffers to the validation list so the kernel can make
3974 * resident before running our batch.
3977 iris_populate_binding_table(struct iris_context
*ice
,
3978 struct iris_batch
*batch
,
3979 gl_shader_stage stage
,
3982 const struct iris_binder
*binder
= &ice
->state
.binder
;
3983 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
3984 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3988 struct iris_binding_table
*bt
= &shader
->bt
;
3989 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3990 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3991 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
3993 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
3996 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
3998 /* TCS passthrough doesn't need a binding table. */
3999 assert(stage
== MESA_SHADER_TESS_CTRL
);
4003 if (stage
== MESA_SHADER_COMPUTE
&&
4004 shader
->bt
.used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
]) {
4005 /* surface for gl_NumWorkGroups */
4006 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
4007 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
4008 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
4009 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
4010 push_bt_entry(grid_state
->offset
);
4013 if (stage
== MESA_SHADER_FRAGMENT
) {
4014 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4015 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
4016 if (cso_fb
->nr_cbufs
) {
4017 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
4019 if (cso_fb
->cbufs
[i
]) {
4020 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
], true,
4021 ice
->state
.draw_aux_usage
[i
]);
4023 addr
= use_null_fb_surface(batch
, ice
);
4025 push_bt_entry(addr
);
4028 uint32_t addr
= use_null_fb_surface(batch
, ice
);
4029 push_bt_entry(addr
);
4033 #define foreach_surface_used(index, group) \
4035 for (int index = 0; index < bt->sizes[group]; index++) \
4036 if (iris_group_index_to_bti(bt, group, index) != \
4037 IRIS_SURFACE_NOT_USED)
4039 foreach_surface_used(i
, IRIS_SURFACE_GROUP_TEXTURE
) {
4040 struct iris_sampler_view
*view
= shs
->textures
[i
];
4041 uint32_t addr
= view
? use_sampler_view(ice
, batch
, view
)
4042 : use_null_surface(batch
, ice
);
4043 push_bt_entry(addr
);
4046 foreach_surface_used(i
, IRIS_SURFACE_GROUP_IMAGE
) {
4047 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
4048 push_bt_entry(addr
);
4051 foreach_surface_used(i
, IRIS_SURFACE_GROUP_UBO
) {
4054 if (i
== bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] - 1) {
4055 if (ish
->const_data
) {
4056 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data
), false);
4057 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data_state
.res
),
4059 addr
= ish
->const_data_state
.offset
;
4061 /* This can only happen with INTEL_DISABLE_COMPACT_BINDING_TABLE=1. */
4062 addr
= use_null_surface(batch
, ice
);
4065 addr
= use_ubo_ssbo(batch
, ice
, &shs
->constbuf
[i
],
4066 &shs
->constbuf_surf_state
[i
], false);
4069 push_bt_entry(addr
);
4072 foreach_surface_used(i
, IRIS_SURFACE_GROUP_SSBO
) {
4074 use_ubo_ssbo(batch
, ice
, &shs
->ssbo
[i
], &shs
->ssbo_surf_state
[i
],
4075 shs
->writable_ssbos
& (1u << i
));
4076 push_bt_entry(addr
);
4080 /* XXX: YUV surfaces not implemented yet */
4081 bt_assert(plane_start
[1], ...);
4082 bt_assert(plane_start
[2], ...);
4087 iris_use_optional_res(struct iris_batch
*batch
,
4088 struct pipe_resource
*res
,
4092 struct iris_bo
*bo
= iris_resource_bo(res
);
4093 iris_use_pinned_bo(batch
, bo
, writeable
);
4098 pin_depth_and_stencil_buffers(struct iris_batch
*batch
,
4099 struct pipe_surface
*zsbuf
,
4100 struct iris_depth_stencil_alpha_state
*cso_zsa
)
4105 struct iris_resource
*zres
, *sres
;
4106 iris_get_depth_stencil_resources(zsbuf
->texture
, &zres
, &sres
);
4109 iris_use_pinned_bo(batch
, zres
->bo
, cso_zsa
->depth_writes_enabled
);
4111 iris_use_pinned_bo(batch
, zres
->aux
.bo
,
4112 cso_zsa
->depth_writes_enabled
);
4117 iris_use_pinned_bo(batch
, sres
->bo
, cso_zsa
->stencil_writes_enabled
);
4121 /* ------------------------------------------------------------------- */
4124 * Pin any BOs which were installed by a previous batch, and restored
4125 * via the hardware logical context mechanism.
4127 * We don't need to re-emit all state every batch - the hardware context
4128 * mechanism will save and restore it for us. This includes pointers to
4129 * various BOs...which won't exist unless we ask the kernel to pin them
4130 * by adding them to the validation list.
4132 * We can skip buffers if we've re-emitted those packets, as we're
4133 * overwriting those stale pointers with new ones, and don't actually
4134 * refer to the old BOs.
4137 iris_restore_render_saved_bos(struct iris_context
*ice
,
4138 struct iris_batch
*batch
,
4139 const struct pipe_draw_info
*draw
)
4141 struct iris_genx_state
*genx
= ice
->state
.genx
;
4143 const uint64_t clean
= ~ice
->state
.dirty
;
4145 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
4146 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
4149 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4150 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
4153 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
4154 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
4157 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4158 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
4161 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
4162 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
4165 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
4166 for (int i
= 0; i
< 4; i
++) {
4167 struct iris_stream_output_target
*tgt
=
4168 (void *) ice
->state
.so_target
[i
];
4170 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4172 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4178 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4179 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4182 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4183 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4188 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4190 for (int i
= 0; i
< 4; i
++) {
4191 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4193 if (range
->length
== 0)
4196 /* Range block is a binding table index, map back to UBO index. */
4197 unsigned block_index
= iris_bti_to_group_index(
4198 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
4199 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
4201 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4202 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4205 iris_use_pinned_bo(batch
, res
->bo
, false);
4207 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4211 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4212 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4213 /* Re-pin any buffers referred to by the binding table. */
4214 iris_populate_binding_table(ice
, batch
, stage
, true);
4218 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4219 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4220 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4222 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4225 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4226 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
4227 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4230 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4231 iris_use_pinned_bo(batch
, bo
, false);
4233 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4235 if (prog_data
->total_scratch
> 0) {
4236 struct iris_bo
*bo
=
4237 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4238 iris_use_pinned_bo(batch
, bo
, true);
4244 if ((clean
& IRIS_DIRTY_DEPTH_BUFFER
) &&
4245 (clean
& IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
4246 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4247 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
4250 if (draw
->index_size
== 0 && ice
->state
.last_res
.index_buffer
) {
4251 /* This draw didn't emit a new index buffer, so we are inheriting the
4252 * older index buffer. This draw didn't need it, but future ones may.
4254 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4255 iris_use_pinned_bo(batch
, bo
, false);
4258 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4259 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4261 const int i
= u_bit_scan64(&bound
);
4262 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
4263 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4269 iris_restore_compute_saved_bos(struct iris_context
*ice
,
4270 struct iris_batch
*batch
,
4271 const struct pipe_grid_info
*grid
)
4273 const uint64_t clean
= ~ice
->state
.dirty
;
4275 const int stage
= MESA_SHADER_COMPUTE
;
4276 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4278 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
4279 /* Re-pin any buffers referred to by the binding table. */
4280 iris_populate_binding_table(ice
, batch
, stage
, true);
4283 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
4285 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
4287 if ((clean
& IRIS_DIRTY_SAMPLER_STATES_CS
) &&
4288 (clean
& IRIS_DIRTY_BINDINGS_CS
) &&
4289 (clean
& IRIS_DIRTY_CONSTANTS_CS
) &&
4290 (clean
& IRIS_DIRTY_CS
)) {
4291 iris_use_optional_res(batch
, ice
->state
.last_res
.cs_desc
, false);
4294 if (clean
& IRIS_DIRTY_CS
) {
4295 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4298 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4299 iris_use_pinned_bo(batch
, bo
, false);
4301 struct iris_bo
*curbe_bo
=
4302 iris_resource_bo(ice
->state
.last_res
.cs_thread_ids
);
4303 iris_use_pinned_bo(batch
, curbe_bo
, false);
4305 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4307 if (prog_data
->total_scratch
> 0) {
4308 struct iris_bo
*bo
=
4309 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4310 iris_use_pinned_bo(batch
, bo
, true);
4317 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
4320 iris_update_surface_base_address(struct iris_batch
*batch
,
4321 struct iris_binder
*binder
)
4323 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
4326 flush_for_state_base_change(batch
);
4328 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
4329 sba
.SurfaceStateMOCS
= MOCS_WB
;
4330 sba
.SurfaceStateBaseAddressModifyEnable
= true;
4331 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
4334 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
4338 iris_upload_dirty_render_state(struct iris_context
*ice
,
4339 struct iris_batch
*batch
,
4340 const struct pipe_draw_info
*draw
)
4342 const uint64_t dirty
= ice
->state
.dirty
;
4344 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
4347 struct iris_genx_state
*genx
= ice
->state
.genx
;
4348 struct iris_binder
*binder
= &ice
->state
.binder
;
4349 struct brw_wm_prog_data
*wm_prog_data
= (void *)
4350 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
4352 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
4353 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4354 uint32_t cc_vp_address
;
4356 /* XXX: could avoid streaming for depth_clip [0,1] case. */
4357 uint32_t *cc_vp_map
=
4358 stream_state(batch
, ice
->state
.dynamic_uploader
,
4359 &ice
->state
.last_res
.cc_vp
,
4360 4 * ice
->state
.num_viewports
*
4361 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
4362 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4364 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
4365 cso_rast
->clip_halfz
, &zmin
, &zmax
);
4366 if (cso_rast
->depth_clip_near
)
4368 if (cso_rast
->depth_clip_far
)
4371 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
4372 ccv
.MinimumDepth
= zmin
;
4373 ccv
.MaximumDepth
= zmax
;
4376 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
4379 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
4380 ptr
.CCViewportPointer
= cc_vp_address
;
4384 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4385 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4386 uint32_t sf_cl_vp_address
;
4388 stream_state(batch
, ice
->state
.dynamic_uploader
,
4389 &ice
->state
.last_res
.sf_cl_vp
,
4390 4 * ice
->state
.num_viewports
*
4391 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
4393 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4394 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
4395 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
4397 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
4398 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
4399 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
4400 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
4402 gen_calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
4403 state
->scale
[0], state
->scale
[1],
4404 state
->translate
[0], state
->translate
[1],
4405 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
4407 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
4408 vp
.ViewportMatrixElementm00
= state
->scale
[0];
4409 vp
.ViewportMatrixElementm11
= state
->scale
[1];
4410 vp
.ViewportMatrixElementm22
= state
->scale
[2];
4411 vp
.ViewportMatrixElementm30
= state
->translate
[0];
4412 vp
.ViewportMatrixElementm31
= state
->translate
[1];
4413 vp
.ViewportMatrixElementm32
= state
->translate
[2];
4414 vp
.XMinClipGuardband
= gb_xmin
;
4415 vp
.XMaxClipGuardband
= gb_xmax
;
4416 vp
.YMinClipGuardband
= gb_ymin
;
4417 vp
.YMaxClipGuardband
= gb_ymax
;
4418 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
4419 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
4420 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
4421 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
4424 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
4427 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
4428 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
4432 if (dirty
& IRIS_DIRTY_URB
) {
4435 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
4436 if (!ice
->shaders
.prog
[i
]) {
4439 struct brw_vue_prog_data
*vue_prog_data
=
4440 (void *) ice
->shaders
.prog
[i
]->prog_data
;
4441 size
[i
] = vue_prog_data
->urb_entry_size
;
4443 assert(size
[i
] != 0);
4446 genX(emit_urb_setup
)(ice
, batch
, size
,
4447 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
4448 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
);
4451 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
4452 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4453 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4454 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4455 const int header_dwords
= GENX(BLEND_STATE_length
);
4457 /* Always write at least one BLEND_STATE - the final RT message will
4458 * reference BLEND_STATE[0] even if there aren't color writes. There
4459 * may still be alpha testing, computed depth, and so on.
4461 const int rt_dwords
=
4462 MAX2(cso_fb
->nr_cbufs
, 1) * GENX(BLEND_STATE_ENTRY_length
);
4464 uint32_t blend_offset
;
4465 uint32_t *blend_map
=
4466 stream_state(batch
, ice
->state
.dynamic_uploader
,
4467 &ice
->state
.last_res
.blend
,
4468 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4470 uint32_t blend_state_header
;
4471 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4472 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4473 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4476 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4477 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4479 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4480 ptr
.BlendStatePointer
= blend_offset
;
4481 ptr
.BlendStatePointerValid
= true;
4485 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4486 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4488 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4492 stream_state(batch
, ice
->state
.dynamic_uploader
,
4493 &ice
->state
.last_res
.color_calc
,
4494 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4496 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4497 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4498 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4499 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4500 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4501 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4502 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4504 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4505 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4508 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4509 ptr
.ColorCalcStatePointer
= cc_offset
;
4510 ptr
.ColorCalcStatePointerValid
= true;
4514 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4515 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4518 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4519 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4524 if (shs
->sysvals_need_upload
)
4525 upload_sysvals(ice
, stage
);
4527 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4529 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4530 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4532 /* The Skylake PRM contains the following restriction:
4534 * "The driver must ensure The following case does not occur
4535 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4536 * buffer 3 read length equal to zero committed followed by a
4537 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4540 * To avoid this, we program the buffers in the highest slots.
4541 * This way, slot 0 is only used if slot 3 is also used.
4545 for (int i
= 3; i
>= 0; i
--) {
4546 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4548 if (range
->length
== 0)
4551 /* Range block is a binding table index, map back to UBO index. */
4552 unsigned block_index
= iris_bti_to_group_index(
4553 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
4554 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
4556 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4557 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4559 assert(cbuf
->buffer_offset
% 32 == 0);
4561 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4562 pkt
.ConstantBody
.Buffer
[n
] =
4563 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->buffer_offset
)
4564 : ro_bo(batch
->screen
->workaround_bo
, 0);
4571 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4572 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4573 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4574 ptr
._3DCommandSubOpcode
= 38 + stage
;
4575 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4580 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4581 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4582 iris_populate_binding_table(ice
, batch
, stage
, false);
4586 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4587 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4588 !ice
->shaders
.prog
[stage
])
4591 iris_upload_sampler_states(ice
, stage
);
4593 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4594 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4596 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4598 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4599 ptr
._3DCommandSubOpcode
= 43 + stage
;
4600 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4604 if (ice
->state
.need_border_colors
)
4605 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4607 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4608 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4610 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4611 if (ice
->state
.framebuffer
.samples
> 0)
4612 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4616 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4617 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4618 ms
.SampleMask
= ice
->state
.sample_mask
;
4622 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4623 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4626 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4629 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4630 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4631 iris_use_pinned_bo(batch
, cache
->bo
, false);
4633 if (prog_data
->total_scratch
> 0) {
4634 struct iris_bo
*bo
=
4635 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4636 iris_use_pinned_bo(batch
, bo
, true);
4639 if (stage
== MESA_SHADER_FRAGMENT
&& wm_prog_data
->uses_sample_mask
) {
4640 uint32_t *shader_ps
= (uint32_t *) shader
->derived_data
;
4641 uint32_t *shader_psx
= shader_ps
+ GENX(3DSTATE_PS_length
);
4642 uint32_t ps_state
[GENX(3DSTATE_PS_length
)] = {0};
4643 uint32_t psx_state
[GENX(3DSTATE_PS_EXTRA_length
)] = {0};
4644 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4645 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4647 /* The docs for 3DSTATE_PS::32 Pixel Dispatch Enable say:
4649 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16,
4650 * SIMD32 Dispatch must not be enabled for PER_PIXEL dispatch
4653 * 16x MSAA only exists on Gen9+, so we can skip this on Gen8.
4655 iris_pack_command(GENX(3DSTATE_PS
), &ps_state
, ps
) {
4656 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
&&
4657 (cso_fb
->samples
!= 16 || wm_prog_data
->persample_dispatch
);
4660 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), &psx_state
, psx
) {
4661 if (wm_prog_data
->post_depth_coverage
)
4662 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4663 else if (wm_prog_data
->inner_coverage
&& cso
->conservative_rasterization
)
4664 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4666 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4669 iris_emit_merge(batch
, shader_ps
, ps_state
,
4670 GENX(3DSTATE_PS_length
));
4671 iris_emit_merge(batch
,
4674 GENX(3DSTATE_PS_EXTRA_length
));
4677 iris_batch_emit(batch
, shader
->derived_data
,
4678 iris_derived_program_state_size(stage
));
4680 if (stage
== MESA_SHADER_TESS_EVAL
) {
4681 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4682 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4683 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4684 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4685 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4690 if (ice
->state
.streamout_active
) {
4691 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4692 iris_batch_emit(batch
, genx
->so_buffers
,
4693 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4694 for (int i
= 0; i
< 4; i
++) {
4695 struct iris_stream_output_target
*tgt
=
4696 (void *) ice
->state
.so_target
[i
];
4699 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4701 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4707 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
4708 uint32_t *decl_list
=
4709 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
4710 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
4713 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4714 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4716 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
4717 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
4718 sol
.SOFunctionEnable
= true;
4719 sol
.SOStatisticsEnable
= true;
4721 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
4722 !ice
->state
.prims_generated_query_active
;
4723 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
4726 assert(ice
->state
.streamout
);
4728 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
4729 GENX(3DSTATE_STREAMOUT_length
));
4732 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4733 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
4737 if (dirty
& IRIS_DIRTY_CLIP
) {
4738 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4739 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4741 bool gs_or_tes
= ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] ||
4742 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
4743 bool points_or_lines
= cso_rast
->fill_mode_point_or_line
||
4744 (gs_or_tes
? ice
->shaders
.output_topology_is_points_or_lines
4745 : ice
->state
.prim_is_points_or_lines
);
4747 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
4748 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
4749 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4750 cl
.ClipMode
= cso_rast
->rasterizer_discard
? CLIPMODE_REJECT_ALL
4752 cl
.ViewportXYClipTestEnable
= !points_or_lines
;
4754 if (wm_prog_data
->barycentric_interp_modes
&
4755 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
4756 cl
.NonPerspectiveBarycentricEnable
= true;
4758 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
4759 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
4761 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
4762 ARRAY_SIZE(cso_rast
->clip
));
4765 if (dirty
& IRIS_DIRTY_RASTER
) {
4766 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4767 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
4768 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
4772 if (dirty
& IRIS_DIRTY_WM
) {
4773 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4774 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
4776 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
4777 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4779 wm
.BarycentricInterpolationMode
=
4780 wm_prog_data
->barycentric_interp_modes
;
4782 if (wm_prog_data
->early_fragment_tests
)
4783 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
4784 else if (wm_prog_data
->has_side_effects
)
4785 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
4787 /* We could skip this bit if color writes are enabled. */
4788 if (wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
)
4789 wm
.ForceThreadDispatchEnable
= ForceON
;
4791 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
4794 if (dirty
& IRIS_DIRTY_SBE
) {
4795 iris_emit_sbe(batch
, ice
);
4798 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
4799 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4800 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4801 const struct shader_info
*fs_info
=
4802 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
4804 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
4805 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
4806 pb
.HasWriteableRT
= has_writeable_rt(cso_blend
, fs_info
);
4807 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4809 /* The dual source blending docs caution against using SRC1 factors
4810 * when the shader doesn't use a dual source render target write.
4811 * Empirically, this can lead to GPU hangs, and the results are
4812 * undefined anyway, so simply disable blending to avoid the hang.
4814 pb
.ColorBufferBlendEnable
= (cso_blend
->blend_enables
& 1) &&
4815 (!cso_blend
->dual_color_blending
|| wm_prog_data
->dual_src_blend
);
4818 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
4819 ARRAY_SIZE(cso_blend
->ps_blend
));
4822 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
4823 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4825 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4826 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
4827 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
4828 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4829 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4831 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
4833 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
4837 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
4838 uint32_t scissor_offset
=
4839 emit_state(batch
, ice
->state
.dynamic_uploader
,
4840 &ice
->state
.last_res
.scissor
,
4841 ice
->state
.scissors
,
4842 sizeof(struct pipe_scissor_state
) *
4843 ice
->state
.num_viewports
, 32);
4845 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
4846 ptr
.ScissorRectPointer
= scissor_offset
;
4850 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
4851 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
4853 /* Do not emit the clear params yets. We need to update the clear value
4856 uint32_t clear_length
= GENX(3DSTATE_CLEAR_PARAMS_length
) * 4;
4857 uint32_t cso_z_size
= sizeof(cso_z
->packets
) - clear_length
;
4858 iris_batch_emit(batch
, cso_z
->packets
, cso_z_size
);
4860 union isl_color_value clear_value
= { .f32
= { 0, } };
4862 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4863 if (cso_fb
->zsbuf
) {
4864 struct iris_resource
*zres
, *sres
;
4865 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
4867 if (zres
&& zres
->aux
.bo
)
4868 clear_value
= iris_resource_get_clear_color(zres
, NULL
, NULL
);
4871 uint32_t clear_params
[GENX(3DSTATE_CLEAR_PARAMS_length
)];
4872 iris_pack_command(GENX(3DSTATE_CLEAR_PARAMS
), clear_params
, clear
) {
4873 clear
.DepthClearValueValid
= true;
4874 clear
.DepthClearValue
= clear_value
.f32
[0];
4876 iris_batch_emit(batch
, clear_params
, clear_length
);
4879 if (dirty
& (IRIS_DIRTY_DEPTH_BUFFER
| IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
4880 /* Listen for buffer changes, and also write enable changes. */
4881 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4882 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
4885 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
4886 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
4887 for (int i
= 0; i
< 32; i
++) {
4888 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
4893 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
4894 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4895 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
4898 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
4899 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
4900 topo
.PrimitiveTopologyType
=
4901 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
4905 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4906 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
4907 int dynamic_bound
= ice
->state
.bound_vertex_buffers
;
4909 if (ice
->state
.vs_uses_draw_params
) {
4910 if (ice
->draw
.draw_params_offset
== 0) {
4911 u_upload_data(ice
->ctx
.stream_uploader
, 0, sizeof(ice
->draw
.params
),
4912 4, &ice
->draw
.params
, &ice
->draw
.draw_params_offset
,
4913 &ice
->draw
.draw_params_res
);
4915 assert(ice
->draw
.draw_params_res
);
4917 struct iris_vertex_buffer_state
*state
=
4918 &(ice
->state
.genx
->vertex_buffers
[count
]);
4919 pipe_resource_reference(&state
->resource
, ice
->draw
.draw_params_res
);
4920 struct iris_resource
*res
= (void *) state
->resource
;
4922 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
4923 vb
.VertexBufferIndex
= count
;
4924 vb
.AddressModifyEnable
= true;
4926 vb
.BufferSize
= res
->bo
->size
- ice
->draw
.draw_params_offset
;
4927 vb
.BufferStartingAddress
=
4928 ro_bo(NULL
, res
->bo
->gtt_offset
+
4929 (int) ice
->draw
.draw_params_offset
);
4930 vb
.MOCS
= mocs(res
->bo
);
4932 dynamic_bound
|= 1ull << count
;
4936 if (ice
->state
.vs_uses_derived_draw_params
) {
4937 u_upload_data(ice
->ctx
.stream_uploader
, 0,
4938 sizeof(ice
->draw
.derived_params
), 4,
4939 &ice
->draw
.derived_params
,
4940 &ice
->draw
.derived_draw_params_offset
,
4941 &ice
->draw
.derived_draw_params_res
);
4943 struct iris_vertex_buffer_state
*state
=
4944 &(ice
->state
.genx
->vertex_buffers
[count
]);
4945 pipe_resource_reference(&state
->resource
,
4946 ice
->draw
.derived_draw_params_res
);
4947 struct iris_resource
*res
= (void *) ice
->draw
.derived_draw_params_res
;
4949 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
4950 vb
.VertexBufferIndex
= count
;
4951 vb
.AddressModifyEnable
= true;
4954 res
->bo
->size
- ice
->draw
.derived_draw_params_offset
;
4955 vb
.BufferStartingAddress
=
4956 ro_bo(NULL
, res
->bo
->gtt_offset
+
4957 (int) ice
->draw
.derived_draw_params_offset
);
4958 vb
.MOCS
= mocs(res
->bo
);
4960 dynamic_bound
|= 1ull << count
;
4965 /* The VF cache designers cut corners, and made the cache key's
4966 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
4967 * 32 bits of the address. If you have two vertex buffers which get
4968 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
4969 * you can get collisions (even within a single batch).
4971 * So, we need to do a VF cache invalidate if the buffer for a VB
4972 * slot slot changes [48:32] address bits from the previous time.
4974 unsigned flush_flags
= 0;
4976 uint64_t bound
= dynamic_bound
;
4978 const int i
= u_bit_scan64(&bound
);
4979 uint16_t high_bits
= 0;
4981 struct iris_resource
*res
=
4982 (void *) genx
->vertex_buffers
[i
].resource
;
4984 iris_use_pinned_bo(batch
, res
->bo
, false);
4986 high_bits
= res
->bo
->gtt_offset
>> 32ull;
4987 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
4988 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
|
4989 PIPE_CONTROL_CS_STALL
;
4990 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
4996 iris_emit_pipe_control_flush(batch
,
4997 "workaround: VF cache 32-bit key [VB]",
5001 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
5004 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
5005 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
5006 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
5010 bound
= dynamic_bound
;
5012 const int i
= u_bit_scan64(&bound
);
5013 memcpy(map
, genx
->vertex_buffers
[i
].state
,
5014 sizeof(uint32_t) * vb_dwords
);
5020 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
5021 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5022 const unsigned entries
= MAX2(cso
->count
, 1);
5023 if (!(ice
->state
.vs_needs_sgvs_element
||
5024 ice
->state
.vs_uses_derived_draw_params
||
5025 ice
->state
.vs_needs_edge_flag
)) {
5026 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
5027 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
5029 uint32_t dynamic_ves
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
5030 const unsigned dyn_count
= cso
->count
+
5031 ice
->state
.vs_needs_sgvs_element
+
5032 ice
->state
.vs_uses_derived_draw_params
;
5034 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
),
5037 1 + GENX(VERTEX_ELEMENT_STATE_length
) * dyn_count
- 2;
5039 memcpy(&dynamic_ves
[1], &cso
->vertex_elements
[1],
5040 (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5041 GENX(VERTEX_ELEMENT_STATE_length
) * sizeof(uint32_t));
5042 uint32_t *ve_pack_dest
=
5043 &dynamic_ves
[1 + (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5044 GENX(VERTEX_ELEMENT_STATE_length
)];
5046 if (ice
->state
.vs_needs_sgvs_element
) {
5047 uint32_t base_ctrl
= ice
->state
.vs_uses_draw_params
?
5048 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
5049 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5051 ve
.VertexBufferIndex
=
5052 util_bitcount64(ice
->state
.bound_vertex_buffers
);
5053 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5054 ve
.Component0Control
= base_ctrl
;
5055 ve
.Component1Control
= base_ctrl
;
5056 ve
.Component2Control
= VFCOMP_STORE_0
;
5057 ve
.Component3Control
= VFCOMP_STORE_0
;
5059 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5061 if (ice
->state
.vs_uses_derived_draw_params
) {
5062 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5064 ve
.VertexBufferIndex
=
5065 util_bitcount64(ice
->state
.bound_vertex_buffers
) +
5066 ice
->state
.vs_uses_draw_params
;
5067 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5068 ve
.Component0Control
= VFCOMP_STORE_SRC
;
5069 ve
.Component1Control
= VFCOMP_STORE_SRC
;
5070 ve
.Component2Control
= VFCOMP_STORE_0
;
5071 ve
.Component3Control
= VFCOMP_STORE_0
;
5073 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5075 if (ice
->state
.vs_needs_edge_flag
) {
5076 for (int i
= 0; i
< GENX(VERTEX_ELEMENT_STATE_length
); i
++)
5077 ve_pack_dest
[i
] = cso
->edgeflag_ve
[i
];
5080 iris_batch_emit(batch
, &dynamic_ves
, sizeof(uint32_t) *
5081 (1 + dyn_count
* GENX(VERTEX_ELEMENT_STATE_length
)));
5084 if (!ice
->state
.vs_needs_edge_flag
) {
5085 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
5086 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5088 assert(cso
->count
> 0);
5089 const unsigned edgeflag_index
= cso
->count
- 1;
5090 uint32_t dynamic_vfi
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
5091 memcpy(&dynamic_vfi
[0], cso
->vf_instancing
, edgeflag_index
*
5092 GENX(3DSTATE_VF_INSTANCING_length
) * sizeof(uint32_t));
5094 uint32_t *vfi_pack_dest
= &dynamic_vfi
[0] +
5095 edgeflag_index
* GENX(3DSTATE_VF_INSTANCING_length
);
5096 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
5097 vi
.VertexElementIndex
= edgeflag_index
+
5098 ice
->state
.vs_needs_sgvs_element
+
5099 ice
->state
.vs_uses_derived_draw_params
;
5101 for (int i
= 0; i
< GENX(3DSTATE_VF_INSTANCING_length
); i
++)
5102 vfi_pack_dest
[i
] |= cso
->edgeflag_vfi
[i
];
5104 iris_batch_emit(batch
, &dynamic_vfi
[0], sizeof(uint32_t) *
5105 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5109 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
5110 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
5111 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
5112 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5114 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
5115 if (vs_prog_data
->uses_vertexid
) {
5116 sgv
.VertexIDEnable
= true;
5117 sgv
.VertexIDComponentNumber
= 2;
5118 sgv
.VertexIDElementOffset
=
5119 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5122 if (vs_prog_data
->uses_instanceid
) {
5123 sgv
.InstanceIDEnable
= true;
5124 sgv
.InstanceIDComponentNumber
= 3;
5125 sgv
.InstanceIDElementOffset
=
5126 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5131 if (dirty
& IRIS_DIRTY_VF
) {
5132 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
5133 if (draw
->primitive_restart
) {
5134 vf
.IndexedDrawCutIndexEnable
= true;
5135 vf
.CutIndex
= draw
->restart_index
;
5140 if (dirty
& IRIS_DIRTY_VF_STATISTICS
) {
5141 iris_emit_cmd(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
5142 vf
.StatisticsEnable
= true;
5146 /* TODO: Gen8 PMA fix */
5150 iris_upload_render_state(struct iris_context
*ice
,
5151 struct iris_batch
*batch
,
5152 const struct pipe_draw_info
*draw
)
5154 bool use_predicate
= ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
5156 /* Always pin the binder. If we're emitting new binding table pointers,
5157 * we need it. If not, we're probably inheriting old tables via the
5158 * context, and need it anyway. Since true zero-bindings cases are
5159 * practically non-existent, just pin it and avoid last_res tracking.
5161 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5163 if (!batch
->contains_draw
) {
5164 iris_restore_render_saved_bos(ice
, batch
, draw
);
5165 batch
->contains_draw
= true;
5168 iris_upload_dirty_render_state(ice
, batch
, draw
);
5170 if (draw
->index_size
> 0) {
5173 if (draw
->has_user_indices
) {
5174 u_upload_data(ice
->ctx
.stream_uploader
, 0,
5175 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
5176 &offset
, &ice
->state
.last_res
.index_buffer
);
5178 struct iris_resource
*res
= (void *) draw
->index
.resource
;
5179 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
5181 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
5182 draw
->index
.resource
);
5186 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
5188 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
5189 ib
.IndexFormat
= draw
->index_size
>> 1;
5191 ib
.BufferSize
= bo
->size
- offset
;
5192 ib
.BufferStartingAddress
= ro_bo(bo
, offset
);
5195 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
5196 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
5197 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
5198 iris_emit_pipe_control_flush(batch
,
5199 "workaround: VF cache 32-bit key [IB]",
5200 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5201 PIPE_CONTROL_CS_STALL
);
5202 ice
->state
.last_index_bo_high_bits
= high_bits
;
5206 #define _3DPRIM_END_OFFSET 0x2420
5207 #define _3DPRIM_START_VERTEX 0x2430
5208 #define _3DPRIM_VERTEX_COUNT 0x2434
5209 #define _3DPRIM_INSTANCE_COUNT 0x2438
5210 #define _3DPRIM_START_INSTANCE 0x243C
5211 #define _3DPRIM_BASE_VERTEX 0x2440
5213 if (draw
->indirect
) {
5214 if (draw
->indirect
->indirect_draw_count
) {
5215 use_predicate
= true;
5217 struct iris_bo
*draw_count_bo
=
5218 iris_resource_bo(draw
->indirect
->indirect_draw_count
);
5219 unsigned draw_count_offset
=
5220 draw
->indirect
->indirect_draw_count_offset
;
5222 iris_emit_pipe_control_flush(batch
,
5223 "ensure indirect draw buffer is flushed",
5224 PIPE_CONTROL_FLUSH_ENABLE
);
5226 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
) {
5227 struct gen_mi_builder b
;
5228 gen_mi_builder_init(&b
, batch
);
5230 /* comparison = draw id < draw count */
5231 struct gen_mi_value comparison
=
5232 gen_mi_ult(&b
, gen_mi_imm(draw
->drawid
),
5233 gen_mi_mem32(ro_bo(draw_count_bo
,
5234 draw_count_offset
)));
5236 /* predicate = comparison & conditional rendering predicate */
5237 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_RESULT
),
5238 gen_mi_iand(&b
, comparison
,
5239 gen_mi_reg32(CS_GPR(15))));
5241 uint32_t mi_predicate
;
5243 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
5244 ice
->vtbl
.load_register_imm64(batch
, MI_PREDICATE_SRC1
,
5246 /* Upload the current draw count from the draw parameters buffer
5247 * to MI_PREDICATE_SRC0.
5249 ice
->vtbl
.load_register_mem32(batch
, MI_PREDICATE_SRC0
,
5250 draw_count_bo
, draw_count_offset
);
5251 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
5252 ice
->vtbl
.load_register_imm32(batch
, MI_PREDICATE_SRC0
+ 4, 0);
5254 if (draw
->drawid
== 0) {
5255 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
5256 MI_PREDICATE_COMBINEOP_SET
|
5257 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
5259 /* While draw_index < draw_count the predicate's result will be
5260 * (draw_index == draw_count) ^ TRUE = TRUE
5261 * When draw_index == draw_count the result is
5262 * (TRUE) ^ TRUE = FALSE
5263 * After this all results will be:
5264 * (FALSE) ^ FALSE = FALSE
5266 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOAD
|
5267 MI_PREDICATE_COMBINEOP_XOR
|
5268 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
5270 iris_batch_emit(batch
, &mi_predicate
, sizeof(uint32_t));
5273 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
5276 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5277 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
5278 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
5280 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5281 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
5282 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
5284 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5285 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
5286 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
5288 if (draw
->index_size
) {
5289 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5290 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
5291 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5293 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5294 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5295 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
5298 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5299 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5300 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5302 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
5303 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
5307 } else if (draw
->count_from_stream_output
) {
5308 struct iris_stream_output_target
*so
=
5309 (void *) draw
->count_from_stream_output
;
5311 /* XXX: Replace with actual cache tracking */
5312 iris_emit_pipe_control_flush(batch
,
5313 "draw count from stream output stall",
5314 PIPE_CONTROL_CS_STALL
);
5316 struct gen_mi_builder b
;
5317 gen_mi_builder_init(&b
, batch
);
5319 struct iris_address addr
=
5320 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
5321 struct gen_mi_value offset
=
5322 gen_mi_iadd_imm(&b
, gen_mi_mem64(addr
), -so
->base
.buffer_offset
);
5324 gen_mi_store(&b
, gen_mi_reg32(_3DPRIM_VERTEX_COUNT
),
5325 gen_mi_udiv32_imm(&b
, offset
, so
->stride
));
5327 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
5328 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
5329 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
5330 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
5333 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
5334 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
5335 prim
.PredicateEnable
= use_predicate
;
5337 if (draw
->indirect
|| draw
->count_from_stream_output
) {
5338 prim
.IndirectParameterEnable
= true;
5340 prim
.StartInstanceLocation
= draw
->start_instance
;
5341 prim
.InstanceCount
= draw
->instance_count
;
5342 prim
.VertexCountPerInstance
= draw
->count
;
5344 prim
.StartVertexLocation
= draw
->start
;
5346 if (draw
->index_size
) {
5347 prim
.BaseVertexLocation
+= draw
->index_bias
;
5349 prim
.StartVertexLocation
+= draw
->index_bias
;
5356 iris_upload_compute_state(struct iris_context
*ice
,
5357 struct iris_batch
*batch
,
5358 const struct pipe_grid_info
*grid
)
5360 const uint64_t dirty
= ice
->state
.dirty
;
5361 struct iris_screen
*screen
= batch
->screen
;
5362 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
5363 struct iris_binder
*binder
= &ice
->state
.binder
;
5364 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
5365 struct iris_compiled_shader
*shader
=
5366 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
5367 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5368 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
5370 /* Always pin the binder. If we're emitting new binding table pointers,
5371 * we need it. If not, we're probably inheriting old tables via the
5372 * context, and need it anyway. Since true zero-bindings cases are
5373 * practically non-existent, just pin it and avoid last_res tracking.
5375 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5377 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->sysvals_need_upload
)
5378 upload_sysvals(ice
, MESA_SHADER_COMPUTE
);
5380 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
5381 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
5383 if (dirty
& IRIS_DIRTY_SAMPLER_STATES_CS
)
5384 iris_upload_sampler_states(ice
, MESA_SHADER_COMPUTE
);
5386 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
5387 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
5389 if (ice
->state
.need_border_colors
)
5390 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
5392 if (dirty
& IRIS_DIRTY_CS
) {
5393 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
5395 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
5396 * the only bits that are changed are scoreboard related: Scoreboard
5397 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
5398 * these scoreboard related states, a MEDIA_STATE_FLUSH is
5401 iris_emit_pipe_control_flush(batch
,
5402 "workaround: stall before MEDIA_VFE_STATE",
5403 PIPE_CONTROL_CS_STALL
);
5405 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
5406 if (prog_data
->total_scratch
) {
5407 struct iris_bo
*bo
=
5408 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
5409 MESA_SHADER_COMPUTE
);
5410 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
5411 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
5414 vfe
.MaximumNumberofThreads
=
5415 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
5417 vfe
.ResetGatewayTimer
=
5418 Resettingrelativetimerandlatchingtheglobaltimestamp
;
5421 vfe
.BypassGatewayControl
= true;
5423 vfe
.NumberofURBEntries
= 2;
5424 vfe
.URBEntryAllocationSize
= 2;
5426 vfe
.CURBEAllocationSize
=
5427 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
5428 cs_prog_data
->push
.cross_thread
.regs
, 2);
5432 /* TODO: Combine subgroup-id with cbuf0 so we can push regular uniforms */
5433 if (dirty
& IRIS_DIRTY_CS
) {
5434 uint32_t curbe_data_offset
= 0;
5435 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
5436 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
5437 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
5438 uint32_t *curbe_data_map
=
5439 stream_state(batch
, ice
->state
.dynamic_uploader
,
5440 &ice
->state
.last_res
.cs_thread_ids
,
5441 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
5442 &curbe_data_offset
);
5443 assert(curbe_data_map
);
5444 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
5445 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
5447 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
5448 curbe
.CURBETotalDataLength
=
5449 ALIGN(cs_prog_data
->push
.total
.size
, 64);
5450 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
5454 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
5455 IRIS_DIRTY_BINDINGS_CS
|
5456 IRIS_DIRTY_CONSTANTS_CS
|
5458 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
5460 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
5461 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
5462 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
5465 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
5466 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
5468 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
5469 load
.InterfaceDescriptorTotalLength
=
5470 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
5471 load
.InterfaceDescriptorDataStartAddress
=
5472 emit_state(batch
, ice
->state
.dynamic_uploader
,
5473 &ice
->state
.last_res
.cs_desc
, desc
, sizeof(desc
), 64);
5477 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
5478 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
5479 uint32_t right_mask
;
5482 right_mask
= ~0u >> (32 - remainder
);
5484 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
5486 #define GPGPU_DISPATCHDIMX 0x2500
5487 #define GPGPU_DISPATCHDIMY 0x2504
5488 #define GPGPU_DISPATCHDIMZ 0x2508
5490 if (grid
->indirect
) {
5491 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
5492 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
5493 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5494 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
5495 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
5497 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5498 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
5499 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
5501 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5502 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
5503 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
5507 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
5508 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
5509 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
5510 ggw
.ThreadDepthCounterMaximum
= 0;
5511 ggw
.ThreadHeightCounterMaximum
= 0;
5512 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
5513 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
5514 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
5515 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
5516 ggw
.RightExecutionMask
= right_mask
;
5517 ggw
.BottomExecutionMask
= 0xffffffff;
5520 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
5522 if (!batch
->contains_draw
) {
5523 iris_restore_compute_saved_bos(ice
, batch
, grid
);
5524 batch
->contains_draw
= true;
5529 * State module teardown.
5532 iris_destroy_state(struct iris_context
*ice
)
5534 struct iris_genx_state
*genx
= ice
->state
.genx
;
5536 pipe_resource_reference(&ice
->draw
.draw_params_res
, NULL
);
5537 pipe_resource_reference(&ice
->draw
.derived_draw_params_res
, NULL
);
5539 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5541 const int i
= u_bit_scan64(&bound_vbs
);
5542 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
5544 free(ice
->state
.genx
);
5546 for (int i
= 0; i
< 4; i
++) {
5547 pipe_so_target_reference(&ice
->state
.so_target
[i
], NULL
);
5550 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
5551 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
5553 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
5555 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
5556 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5557 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
5558 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
5559 pipe_resource_reference(&shs
->constbuf
[i
].buffer
, NULL
);
5560 pipe_resource_reference(&shs
->constbuf_surf_state
[i
].res
, NULL
);
5562 for (int i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
5563 pipe_resource_reference(&shs
->image
[i
].base
.resource
, NULL
);
5564 pipe_resource_reference(&shs
->image
[i
].surface_state
.res
, NULL
);
5566 for (int i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
5567 pipe_resource_reference(&shs
->ssbo
[i
].buffer
, NULL
);
5568 pipe_resource_reference(&shs
->ssbo_surf_state
[i
].res
, NULL
);
5570 for (int i
= 0; i
< IRIS_MAX_TEXTURE_SAMPLERS
; i
++) {
5571 pipe_sampler_view_reference((struct pipe_sampler_view
**)
5572 &shs
->textures
[i
], NULL
);
5576 pipe_resource_reference(&ice
->state
.grid_size
.res
, NULL
);
5577 pipe_resource_reference(&ice
->state
.grid_surf_state
.res
, NULL
);
5579 pipe_resource_reference(&ice
->state
.null_fb
.res
, NULL
);
5580 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
5582 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
5583 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
5584 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
5585 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
5586 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
5587 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
5588 pipe_resource_reference(&ice
->state
.last_res
.cs_thread_ids
, NULL
);
5589 pipe_resource_reference(&ice
->state
.last_res
.cs_desc
, NULL
);
5592 /* ------------------------------------------------------------------- */
5595 iris_rebind_buffer(struct iris_context
*ice
,
5596 struct iris_resource
*res
,
5597 uint64_t old_address
)
5599 struct pipe_context
*ctx
= &ice
->ctx
;
5600 struct iris_screen
*screen
= (void *) ctx
->screen
;
5601 struct iris_genx_state
*genx
= ice
->state
.genx
;
5603 assert(res
->base
.target
== PIPE_BUFFER
);
5605 /* Buffers can't be framebuffer attachments, nor display related,
5606 * and we don't have upstream Clover support.
5608 assert(!(res
->bind_history
& (PIPE_BIND_DEPTH_STENCIL
|
5609 PIPE_BIND_RENDER_TARGET
|
5610 PIPE_BIND_BLENDABLE
|
5611 PIPE_BIND_DISPLAY_TARGET
|
5613 PIPE_BIND_COMPUTE_RESOURCE
|
5614 PIPE_BIND_GLOBAL
)));
5616 if (res
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
5617 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5619 const int i
= u_bit_scan64(&bound_vbs
);
5620 struct iris_vertex_buffer_state
*state
= &genx
->vertex_buffers
[i
];
5622 /* Update the CPU struct */
5623 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_start
) == 32);
5624 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) == 64);
5625 uint64_t *addr
= (uint64_t *) &state
->state
[1];
5627 if (*addr
== old_address
) {
5628 *addr
= res
->bo
->gtt_offset
;
5629 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
5634 /* No need to handle these:
5635 * - PIPE_BIND_INDEX_BUFFER (emitted for every indexed draw)
5636 * - PIPE_BIND_COMMAND_ARGS_BUFFER (emitted for every indirect draw)
5637 * - PIPE_BIND_QUERY_BUFFER (no persistent state references)
5640 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
5641 /* XXX: be careful about resetting vs appending... */
5645 for (int s
= MESA_SHADER_VERTEX
; s
< MESA_SHADER_STAGES
; s
++) {
5646 struct iris_shader_state
*shs
= &ice
->state
.shaders
[s
];
5647 enum pipe_shader_type p_stage
= stage_to_pipe(s
);
5649 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
5650 /* Skip constant buffer 0, it's for regular uniforms, not UBOs */
5651 uint32_t bound_cbufs
= shs
->bound_cbufs
& ~1u;
5652 while (bound_cbufs
) {
5653 const int i
= u_bit_scan(&bound_cbufs
);
5654 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[i
];
5655 struct iris_state_ref
*surf_state
= &shs
->constbuf_surf_state
[i
];
5657 if (res
->bo
== iris_resource_bo(cbuf
->buffer
)) {
5658 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
, surf_state
, false);
5659 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< s
;
5664 if (res
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
5665 uint32_t bound_ssbos
= shs
->bound_ssbos
;
5666 while (bound_ssbos
) {
5667 const int i
= u_bit_scan(&bound_ssbos
);
5668 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[i
];
5670 if (res
->bo
== iris_resource_bo(ssbo
->buffer
)) {
5671 struct pipe_shader_buffer buf
= {
5672 .buffer
= &res
->base
,
5673 .buffer_offset
= ssbo
->buffer_offset
,
5674 .buffer_size
= ssbo
->buffer_size
,
5676 iris_set_shader_buffers(ctx
, p_stage
, i
, 1, &buf
,
5677 (shs
->writable_ssbos
>> i
) & 1);
5682 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
5683 uint32_t bound_sampler_views
= shs
->bound_sampler_views
;
5684 while (bound_sampler_views
) {
5685 const int i
= u_bit_scan(&bound_sampler_views
);
5686 struct iris_sampler_view
*isv
= shs
->textures
[i
];
5688 if (res
->bo
== iris_resource_bo(isv
->base
.texture
)) {
5689 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
5690 &isv
->surface_state
,
5691 isv
->res
->aux
.sampler_usages
);
5693 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
5694 isv
->view
.format
, isv
->view
.swizzle
,
5695 isv
->base
.u
.buf
.offset
,
5696 isv
->base
.u
.buf
.size
);
5697 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< s
;
5702 if (res
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
5703 uint32_t bound_image_views
= shs
->bound_image_views
;
5704 while (bound_image_views
) {
5705 const int i
= u_bit_scan(&bound_image_views
);
5706 struct iris_image_view
*iv
= &shs
->image
[i
];
5708 if (res
->bo
== iris_resource_bo(iv
->base
.resource
)) {
5709 iris_set_shader_images(ctx
, p_stage
, i
, 1, &iv
->base
);
5716 /* ------------------------------------------------------------------- */
5719 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
5722 _iris_emit_lrr(batch
, dst
, src
);
5726 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
5729 _iris_emit_lrr(batch
, dst
, src
);
5730 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
5734 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
5737 _iris_emit_lri(batch
, reg
, val
);
5741 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
5744 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
5745 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
5749 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
5752 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5753 struct iris_bo
*bo
, uint32_t offset
)
5755 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5756 lrm
.RegisterAddress
= reg
;
5757 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
5762 * Load a 64-bit value from a buffer into a MMIO register via
5763 * two MI_LOAD_REGISTER_MEM commands.
5766 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5767 struct iris_bo
*bo
, uint32_t offset
)
5769 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
5770 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
5774 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5775 struct iris_bo
*bo
, uint32_t offset
,
5778 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
5779 srm
.RegisterAddress
= reg
;
5780 srm
.MemoryAddress
= rw_bo(bo
, offset
);
5781 srm
.PredicateEnable
= predicated
;
5786 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5787 struct iris_bo
*bo
, uint32_t offset
,
5790 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
5791 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
5795 iris_store_data_imm32(struct iris_batch
*batch
,
5796 struct iris_bo
*bo
, uint32_t offset
,
5799 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
5800 sdi
.Address
= rw_bo(bo
, offset
);
5801 sdi
.ImmediateData
= imm
;
5806 iris_store_data_imm64(struct iris_batch
*batch
,
5807 struct iris_bo
*bo
, uint32_t offset
,
5810 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
5811 * 2 in genxml but it's actually variable length and we need 5 DWords.
5813 void *map
= iris_get_command_space(batch
, 4 * 5);
5814 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
5815 sdi
.DWordLength
= 5 - 2;
5816 sdi
.Address
= rw_bo(bo
, offset
);
5817 sdi
.ImmediateData
= imm
;
5822 iris_copy_mem_mem(struct iris_batch
*batch
,
5823 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
5824 struct iris_bo
*src_bo
, uint32_t src_offset
,
5827 /* MI_COPY_MEM_MEM operates on DWords. */
5828 assert(bytes
% 4 == 0);
5829 assert(dst_offset
% 4 == 0);
5830 assert(src_offset
% 4 == 0);
5832 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
5833 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
5834 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
5835 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
5840 /* ------------------------------------------------------------------- */
5843 flags_to_post_sync_op(uint32_t flags
)
5845 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
5846 return WriteImmediateData
;
5848 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
5849 return WritePSDepthCount
;
5851 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
5852 return WriteTimestamp
;
5858 * Do the given flags have a Post Sync or LRI Post Sync operation?
5860 static enum pipe_control_flags
5861 get_post_sync_flags(enum pipe_control_flags flags
)
5863 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
5864 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5865 PIPE_CONTROL_WRITE_TIMESTAMP
|
5866 PIPE_CONTROL_LRI_POST_SYNC_OP
;
5868 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
5869 * "LRI Post Sync Operation". So more than one bit set would be illegal.
5871 assert(util_bitcount(flags
) <= 1);
5876 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
5879 * Emit a series of PIPE_CONTROL commands, taking into account any
5880 * workarounds necessary to actually accomplish the caller's request.
5882 * Unless otherwise noted, spec quotations in this function come from:
5884 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
5885 * Restrictions for PIPE_CONTROL.
5887 * You should not use this function directly. Use the helpers in
5888 * iris_pipe_control.c instead, which may split the pipe control further.
5891 iris_emit_raw_pipe_control(struct iris_batch
*batch
,
5898 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
5899 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
5900 enum pipe_control_flags non_lri_post_sync_flags
=
5901 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
5903 /* Recursive PIPE_CONTROL workarounds --------------------------------
5904 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
5906 * We do these first because we want to look at the original operation,
5907 * rather than any workarounds we set.
5909 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
5910 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
5911 * lists several workarounds:
5913 * "Project: SKL, KBL, BXT
5915 * If the VF Cache Invalidation Enable is set to a 1 in a
5916 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
5917 * sets to 0, with the VF Cache Invalidation Enable set to 0
5918 * needs to be sent prior to the PIPE_CONTROL with VF Cache
5919 * Invalidation Enable set to a 1."
5921 iris_emit_raw_pipe_control(batch
,
5922 "workaround: recursive VF cache invalidate",
5926 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
5927 /* Project: SKL / Argument: LRI Post Sync Operation [23]
5929 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5930 * programmed prior to programming a PIPECONTROL command with "LRI
5931 * Post Sync Operation" in GPGPU mode of operation (i.e when
5932 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
5934 * The same text exists a few rows below for Post Sync Op.
5936 iris_emit_raw_pipe_control(batch
,
5937 "workaround: CS stall before gpgpu post-sync",
5938 PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
5941 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
5943 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
5944 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
5945 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
5947 iris_emit_raw_pipe_control(batch
,
5948 "workaround: PC flush before RT flush",
5949 PIPE_CONTROL_FLUSH_ENABLE
, bo
, offset
, imm
);
5952 /* "Flush Types" workarounds ---------------------------------------------
5953 * We do these now because they may add post-sync operations or CS stalls.
5956 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
5957 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
5959 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
5960 * 'Write PS Depth Count' or 'Write Timestamp'."
5963 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5964 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5965 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5966 bo
= batch
->screen
->workaround_bo
;
5970 /* #1130 from Gen10 workarounds page:
5972 * "Enable Depth Stall on every Post Sync Op if Render target Cache
5973 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
5974 * board stall if Render target cache flush is enabled."
5976 * Applicable to CNL B0 and C0 steppings only.
5978 * The wording here is unclear, and this workaround doesn't look anything
5979 * like the internal bug report recommendations, but leave it be for now...
5981 if (GEN_GEN
== 10) {
5982 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
5983 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5984 } else if (flags
& non_lri_post_sync_flags
) {
5985 flags
|= PIPE_CONTROL_DEPTH_STALL
;
5989 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
5990 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
5992 * "This bit must be DISABLED for operations other than writing
5995 * This seems like nonsense. An Ivybridge workaround requires us to
5996 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
5997 * operation. Gen8+ requires us to emit depth stalls and depth cache
5998 * flushes together. So, it's hard to imagine this means anything other
5999 * than "we originally intended this to be used for PS_DEPTH_COUNT".
6001 * We ignore the supposed restriction and do nothing.
6005 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6006 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6007 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
6009 * "This bit must be DISABLED for End-of-pipe (Read) fences,
6010 * PS_DEPTH_COUNT or TIMESTAMP queries."
6012 * TODO: Implement end-of-pipe checking.
6014 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6015 PIPE_CONTROL_WRITE_TIMESTAMP
)));
6018 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6019 /* From the PIPE_CONTROL instruction table, bit 1:
6021 * "This bit is ignored if Depth Stall Enable is set.
6022 * Further, the render cache is not flushed even if Write Cache
6023 * Flush Enable bit is set."
6025 * We assert that the caller doesn't do this combination, to try and
6026 * prevent mistakes. It shouldn't hurt the GPU, though.
6028 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
6029 * and "Render Target Flush" combo is explicitly required for BTI
6030 * update workarounds.
6032 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
6033 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
6036 /* PIPE_CONTROL page workarounds ------------------------------------- */
6038 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
6039 /* From the PIPE_CONTROL page itself:
6042 * Restriction: Pipe_control with CS-stall bit set must be issued
6043 * before a pipe-control command that has the State Cache
6044 * Invalidate bit set."
6046 flags
|= PIPE_CONTROL_CS_STALL
;
6049 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
6050 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
6053 * SW must always program Post-Sync Operation to "Write Immediate
6054 * Data" when Flush LLC is set."
6056 * For now, we just require the caller to do it.
6058 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
6061 /* "Post-Sync Operation" workarounds -------------------------------- */
6063 /* Project: All / Argument: Global Snapshot Count Reset [19]
6065 * "This bit must not be exercised on any product.
6066 * Requires stall bit ([20] of DW1) set."
6068 * We don't use this, so we just assert that it isn't used. The
6069 * PIPE_CONTROL instruction page indicates that they intended this
6070 * as a debug feature and don't think it is useful in production,
6071 * but it may actually be usable, should we ever want to.
6073 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
6075 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
6076 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
6077 /* Project: All / Arguments:
6079 * - Generic Media State Clear [16]
6080 * - Indirect State Pointers Disable [16]
6082 * "Requires stall bit ([20] of DW1) set."
6084 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
6085 * State Clear) says:
6087 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6088 * programmed prior to programming a PIPECONTROL command with "Media
6089 * State Clear" set in GPGPU mode of operation"
6091 * This is a subset of the earlier rule, so there's nothing to do.
6093 flags
|= PIPE_CONTROL_CS_STALL
;
6096 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
6097 /* Project: All / Argument: Store Data Index
6099 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6102 * For now, we just assert that the caller does this. We might want to
6103 * automatically add a write to the workaround BO...
6105 assert(non_lri_post_sync_flags
!= 0);
6108 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
6109 /* Project: All / Argument: Sync GFDT
6111 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6112 * than '0' or 0x2520[13] must be set."
6114 * For now, we just assert that the caller does this.
6116 assert(non_lri_post_sync_flags
!= 0);
6119 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
6120 /* Project: IVB+ / Argument: TLB inv
6122 * "Requires stall bit ([20] of DW1) set."
6124 * Also, from the PIPE_CONTROL instruction table:
6127 * Post Sync Operation or CS stall must be set to ensure a TLB
6128 * invalidation occurs. Otherwise no cycle will occur to the TLB
6129 * cache to invalidate."
6131 * This is not a subset of the earlier rule, so there's nothing to do.
6133 flags
|= PIPE_CONTROL_CS_STALL
;
6136 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
6137 /* TODO: The big Skylake GT4 post sync op workaround */
6140 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
6142 if (IS_COMPUTE_PIPELINE(batch
)) {
6143 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
6144 /* Project: SKL+ / Argument: Tex Invalidate
6145 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
6147 flags
|= PIPE_CONTROL_CS_STALL
;
6150 if (GEN_GEN
== 8 && (post_sync_flags
||
6151 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
6152 PIPE_CONTROL_DEPTH_STALL
|
6153 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6154 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6155 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
6156 /* Project: BDW / Arguments:
6158 * - LRI Post Sync Operation [23]
6159 * - Post Sync Op [15:14]
6161 * - Depth Stall [13]
6162 * - Render Target Cache Flush [12]
6163 * - Depth Cache Flush [0]
6164 * - DC Flush Enable [5]
6166 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
6169 flags
|= PIPE_CONTROL_CS_STALL
;
6171 /* Also, from the PIPE_CONTROL instruction table, bit 20:
6174 * This bit must be always set when PIPE_CONTROL command is
6175 * programmed by GPGPU and MEDIA workloads, except for the cases
6176 * when only Read Only Cache Invalidation bits are set (State
6177 * Cache Invalidation Enable, Instruction cache Invalidation
6178 * Enable, Texture Cache Invalidation Enable, Constant Cache
6179 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
6180 * need not implemented when FF_DOP_CG is disable via "Fixed
6181 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
6183 * It sounds like we could avoid CS stalls in some cases, but we
6184 * don't currently bother. This list isn't exactly the list above,
6190 /* "Stall" workarounds ----------------------------------------------
6191 * These have to come after the earlier ones because we may have added
6192 * some additional CS stalls above.
6195 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
6196 /* Project: PRE-SKL, VLV, CHV
6198 * "[All Stepping][All SKUs]:
6200 * One of the following must also be set:
6202 * - Render Target Cache Flush Enable ([12] of DW1)
6203 * - Depth Cache Flush Enable ([0] of DW1)
6204 * - Stall at Pixel Scoreboard ([1] of DW1)
6205 * - Depth Stall ([13] of DW1)
6206 * - Post-Sync Operation ([13] of DW1)
6207 * - DC Flush Enable ([5] of DW1)"
6209 * If we don't already have one of those bits set, we choose to add
6210 * "Stall at Pixel Scoreboard". Some of the other bits require a
6211 * CS stall as a workaround (see above), which would send us into
6212 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
6213 * appears to be safe, so we choose that.
6215 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6216 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6217 PIPE_CONTROL_WRITE_IMMEDIATE
|
6218 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6219 PIPE_CONTROL_WRITE_TIMESTAMP
|
6220 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
6221 PIPE_CONTROL_DEPTH_STALL
|
6222 PIPE_CONTROL_DATA_CACHE_FLUSH
;
6223 if (!(flags
& wa_bits
))
6224 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6227 /* Emit --------------------------------------------------------------- */
6229 if (INTEL_DEBUG
& DEBUG_PIPE_CONTROL
) {
6231 " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64
"]: %s\n",
6232 (flags
& PIPE_CONTROL_FLUSH_ENABLE
) ? "PipeCon " : "",
6233 (flags
& PIPE_CONTROL_CS_STALL
) ? "CS " : "",
6234 (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) ? "Scoreboard " : "",
6235 (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) ? "VF " : "",
6236 (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) ? "RT " : "",
6237 (flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
) ? "Const " : "",
6238 (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
) ? "TC " : "",
6239 (flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
) ? "DC " : "",
6240 (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
) ? "ZFlush " : "",
6241 (flags
& PIPE_CONTROL_DEPTH_STALL
) ? "ZStall " : "",
6242 (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
) ? "State " : "",
6243 (flags
& PIPE_CONTROL_TLB_INVALIDATE
) ? "TLB " : "",
6244 (flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
) ? "Inst " : "",
6245 (flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
) ? "MediaClear " : "",
6246 (flags
& PIPE_CONTROL_NOTIFY_ENABLE
) ? "Notify " : "",
6247 (flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) ?
6249 (flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
) ?
6251 (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
) ? "WriteImm " : "",
6252 (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
) ? "WriteZCount " : "",
6253 (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
) ? "WriteTimestamp " : "",
6257 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
6258 pc
.LRIPostSyncOperation
= NoLRIOperation
;
6259 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
6260 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
6261 pc
.StoreDataIndex
= 0;
6262 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
6263 pc
.GlobalSnapshotCountReset
=
6264 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
6265 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
6266 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
6267 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6268 pc
.RenderTargetCacheFlushEnable
=
6269 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
6270 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
6271 pc
.StateCacheInvalidationEnable
=
6272 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
6273 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
6274 pc
.ConstantCacheInvalidationEnable
=
6275 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
6276 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
6277 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
6278 pc
.InstructionCacheInvalidateEnable
=
6279 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
6280 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
6281 pc
.IndirectStatePointersDisable
=
6282 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
6283 pc
.TextureCacheInvalidationEnable
=
6284 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
6285 pc
.Address
= rw_bo(bo
, offset
);
6286 pc
.ImmediateData
= imm
;
6291 genX(emit_urb_setup
)(struct iris_context
*ice
,
6292 struct iris_batch
*batch
,
6293 const unsigned size
[4],
6294 bool tess_present
, bool gs_present
)
6296 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6297 const unsigned push_size_kB
= 32;
6298 unsigned entries
[4];
6301 ice
->shaders
.last_vs_entry_size
= size
[MESA_SHADER_VERTEX
];
6303 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
6304 1024 * ice
->shaders
.urb_size
,
6305 tess_present
, gs_present
,
6306 size
, entries
, start
);
6308 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
6309 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
6310 urb
._3DCommandSubOpcode
+= i
;
6311 urb
.VSURBStartingAddress
= start
[i
];
6312 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
6313 urb
.VSNumberofURBEntries
= entries
[i
];
6320 * Preemption on Gen9 has to be enabled or disabled in various cases.
6322 * See these workarounds for preemption:
6323 * - WaDisableMidObjectPreemptionForGSLineStripAdj
6324 * - WaDisableMidObjectPreemptionForTrifanOrPolygon
6325 * - WaDisableMidObjectPreemptionForLineLoop
6328 * We don't put this in the vtable because it's only used on Gen9.
6331 gen9_toggle_preemption(struct iris_context
*ice
,
6332 struct iris_batch
*batch
,
6333 const struct pipe_draw_info
*draw
)
6335 struct iris_genx_state
*genx
= ice
->state
.genx
;
6336 bool object_preemption
= true;
6338 /* WaDisableMidObjectPreemptionForGSLineStripAdj
6340 * "WA: Disable mid-draw preemption when draw-call is a linestrip_adj
6341 * and GS is enabled."
6343 if (draw
->mode
== PIPE_PRIM_LINE_STRIP_ADJACENCY
&&
6344 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
6345 object_preemption
= false;
6347 /* WaDisableMidObjectPreemptionForTrifanOrPolygon
6349 * "TriFan miscompare in Execlist Preemption test. Cut index that is
6350 * on a previous context. End the previous, the resume another context
6351 * with a tri-fan or polygon, and the vertex count is corrupted. If we
6352 * prempt again we will cause corruption.
6354 * WA: Disable mid-draw preemption when draw-call has a tri-fan."
6356 if (draw
->mode
== PIPE_PRIM_TRIANGLE_FAN
)
6357 object_preemption
= false;
6359 /* WaDisableMidObjectPreemptionForLineLoop
6361 * "VF Stats Counters Missing a vertex when preemption enabled.
6363 * WA: Disable mid-draw preemption when the draw uses a lineloop
6366 if (draw
->mode
== PIPE_PRIM_LINE_LOOP
)
6367 object_preemption
= false;
6371 * "VF is corrupting GAFS data when preempted on an instance boundary
6372 * and replayed with instancing enabled.
6374 * WA: Disable preemption when using instanceing."
6376 if (draw
->instance_count
> 1)
6377 object_preemption
= false;
6379 if (genx
->object_preemption
!= object_preemption
) {
6380 iris_enable_obj_preemption(batch
, object_preemption
);
6381 genx
->object_preemption
= object_preemption
;
6387 genX(init_state
)(struct iris_context
*ice
)
6389 struct pipe_context
*ctx
= &ice
->ctx
;
6390 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
6392 ctx
->create_blend_state
= iris_create_blend_state
;
6393 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
6394 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
6395 ctx
->create_sampler_state
= iris_create_sampler_state
;
6396 ctx
->create_sampler_view
= iris_create_sampler_view
;
6397 ctx
->create_surface
= iris_create_surface
;
6398 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
6399 ctx
->bind_blend_state
= iris_bind_blend_state
;
6400 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
6401 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
6402 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
6403 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
6404 ctx
->delete_blend_state
= iris_delete_state
;
6405 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
6406 ctx
->delete_rasterizer_state
= iris_delete_state
;
6407 ctx
->delete_sampler_state
= iris_delete_state
;
6408 ctx
->delete_vertex_elements_state
= iris_delete_state
;
6409 ctx
->set_blend_color
= iris_set_blend_color
;
6410 ctx
->set_clip_state
= iris_set_clip_state
;
6411 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
6412 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
6413 ctx
->set_shader_images
= iris_set_shader_images
;
6414 ctx
->set_sampler_views
= iris_set_sampler_views
;
6415 ctx
->set_tess_state
= iris_set_tess_state
;
6416 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
6417 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
6418 ctx
->set_sample_mask
= iris_set_sample_mask
;
6419 ctx
->set_scissor_states
= iris_set_scissor_states
;
6420 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
6421 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
6422 ctx
->set_viewport_states
= iris_set_viewport_states
;
6423 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
6424 ctx
->surface_destroy
= iris_surface_destroy
;
6425 ctx
->draw_vbo
= iris_draw_vbo
;
6426 ctx
->launch_grid
= iris_launch_grid
;
6427 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
6428 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
6429 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
6431 ice
->vtbl
.destroy_state
= iris_destroy_state
;
6432 ice
->vtbl
.init_render_context
= iris_init_render_context
;
6433 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
6434 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
6435 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
6436 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
6437 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
6438 ice
->vtbl
.rebind_buffer
= iris_rebind_buffer
;
6439 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
6440 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
6441 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
6442 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
6443 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
6444 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
6445 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
6446 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
6447 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
6448 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
6449 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
6450 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
6451 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
6452 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
6453 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
6454 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
6455 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
6456 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
6457 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
6458 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
6459 ice
->vtbl
.mocs
= mocs
;
6461 ice
->state
.dirty
= ~0ull;
6463 ice
->state
.statistics_counters_enabled
= true;
6465 ice
->state
.sample_mask
= 0xffff;
6466 ice
->state
.num_viewports
= 1;
6467 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
6469 /* Make a 1x1x1 null surface for unbound textures */
6470 void *null_surf_map
=
6471 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
6472 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
6473 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
6474 ice
->state
.unbound_tex
.offset
+=
6475 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
6477 /* Default all scissor rectangles to be empty regions. */
6478 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
6479 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
6480 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,