2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
31 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
37 #include "pipe/p_defines.h"
38 #include "pipe/p_state.h"
39 #include "pipe/p_context.h"
40 #include "pipe/p_screen.h"
41 #include "util/u_inlines.h"
42 #include "util/u_format.h"
43 #include "util/u_framebuffer.h"
44 #include "util/u_transfer.h"
45 #include "util/u_upload_mgr.h"
48 #include "intel/compiler/brw_compiler.h"
49 #include "intel/common/gen_l3_config.h"
50 #include "intel/common/gen_sample_positions.h"
51 #include "iris_batch.h"
52 #include "iris_context.h"
53 #include "iris_pipe.h"
54 #include "iris_resource.h"
56 #define __gen_address_type struct iris_address
57 #define __gen_user_data struct iris_batch
59 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
62 __gen_combine_address(struct iris_batch
*batch
, void *location
,
63 struct iris_address addr
, uint32_t delta
)
65 uint64_t result
= addr
.offset
+ delta
;
68 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
69 /* Assume this is a general address, not relative to a base. */
70 result
+= addr
.bo
->gtt_offset
;
76 #define __genxml_cmd_length(cmd) cmd ## _length
77 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
78 #define __genxml_cmd_header(cmd) cmd ## _header
79 #define __genxml_cmd_pack(cmd) cmd ## _pack
81 #define _iris_pack_command(batch, cmd, dst, name) \
82 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
83 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
84 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
88 #define iris_pack_command(cmd, dst, name) \
89 _iris_pack_command(NULL, cmd, dst, name)
91 #define iris_pack_state(cmd, dst, name) \
92 for (struct cmd name = {}, \
93 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
94 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
97 #define iris_emit_cmd(batch, cmd, name) \
98 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
100 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
102 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
103 for (uint32_t i = 0; i < num_dwords; i++) \
104 dw[i] = (dwords0)[i] | (dwords1)[i]; \
105 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
108 #include "genxml/genX_pack.h"
109 #include "genxml/gen_macros.h"
110 #include "genxml/genX_bits.h"
112 #define MOCS_WB (2 << 1)
114 UNUSED
static void pipe_asserts()
116 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
118 /* pipe_logicop happens to match the hardware. */
119 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
120 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
121 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
122 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
123 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
124 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
125 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
126 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
127 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
128 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
129 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
130 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
131 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
132 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
133 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
134 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
136 /* pipe_blend_func happens to match the hardware. */
137 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
138 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
139 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
140 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
141 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
142 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
143 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
144 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
145 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
146 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
147 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
148 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
149 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
150 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
151 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
152 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
153 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
157 /* pipe_blend_func happens to match the hardware. */
158 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
159 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
160 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
161 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
162 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
164 /* pipe_stencil_op happens to match the hardware. */
165 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
166 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
167 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
168 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
169 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
170 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
171 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
172 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
174 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
175 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
176 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
181 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
183 static const unsigned map
[] = {
184 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
185 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
186 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
187 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
188 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
189 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
190 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
191 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
192 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
193 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
194 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
195 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
196 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
197 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
198 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
201 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
205 translate_compare_func(enum pipe_compare_func pipe_func
)
207 static const unsigned map
[] = {
208 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
209 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
210 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
211 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
212 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
213 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
214 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
215 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
217 return map
[pipe_func
];
221 translate_shadow_func(enum pipe_compare_func pipe_func
)
223 /* Gallium specifies the result of shadow comparisons as:
225 * 1 if ref <op> texel,
230 * 0 if texel <op> ref,
233 * So we need to flip the operator and also negate.
235 static const unsigned map
[] = {
236 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
237 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
238 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
239 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
240 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
241 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
242 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
243 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
245 return map
[pipe_func
];
249 translate_cull_mode(unsigned pipe_face
)
251 static const unsigned map
[4] = {
252 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
253 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
254 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
255 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
257 return map
[pipe_face
];
261 translate_fill_mode(unsigned pipe_polymode
)
263 static const unsigned map
[4] = {
264 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
265 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
266 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
267 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
269 return map
[pipe_polymode
];
272 static struct iris_address
273 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
276 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
280 upload_state(struct u_upload_mgr
*uploader
,
281 struct iris_state_ref
*ref
,
286 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
291 stream_state(struct iris_batch
*batch
,
292 struct u_upload_mgr
*uploader
,
293 struct pipe_resource
**out_res
,
296 uint32_t *out_offset
)
300 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
302 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
303 iris_use_pinned_bo(batch
, bo
, false);
305 *out_offset
+= iris_bo_offset_from_base_address(bo
);
311 emit_state(struct iris_batch
*batch
,
312 struct u_upload_mgr
*uploader
,
313 struct pipe_resource
**out_res
,
320 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
323 memcpy(map
, data
, size
);
328 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
329 #define cso_changed_memcmp(x) \
330 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
333 iris_init_render_context(struct iris_screen
*screen
,
334 struct iris_batch
*batch
,
335 struct iris_vtable
*vtbl
,
336 struct pipe_debug_callback
*dbg
)
338 iris_init_batch(batch
, screen
, vtbl
, dbg
, I915_EXEC_RENDER
);
340 /* XXX: PIPE_CONTROLs */
342 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
344 // XXX: MOCS is stupid for this.
345 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
346 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
347 sba
.SurfaceStateMemoryObjectControlState
= MOCS_WB
;
348 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
349 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
350 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
351 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
354 sba
.GeneralStateBaseAddressModifyEnable
= true;
355 sba
.SurfaceStateBaseAddressModifyEnable
= true;
356 sba
.DynamicStateBaseAddressModifyEnable
= true;
357 sba
.IndirectObjectBaseAddressModifyEnable
= true;
358 sba
.InstructionBaseAddressModifyEnable
= true;
359 sba
.GeneralStateBufferSizeModifyEnable
= true;
360 sba
.DynamicStateBufferSizeModifyEnable
= true;
361 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
362 sba
.IndirectObjectBufferSizeModifyEnable
= true;
363 sba
.InstructionBuffersizeModifyEnable
= true;
365 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
366 sba
.SurfaceStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SURFACE_START
);
367 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
369 sba
.GeneralStateBufferSize
= 0xfffff;
370 sba
.IndirectObjectBufferSize
= 0xfffff;
371 sba
.InstructionBufferSize
= 0xfffff;
372 sba
.DynamicStateBufferSize
= 0xfffff;
375 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
376 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
377 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
379 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
380 GEN_SAMPLE_POS_1X(pat
._1xSample
);
381 GEN_SAMPLE_POS_2X(pat
._2xSample
);
382 GEN_SAMPLE_POS_4X(pat
._4xSample
);
383 GEN_SAMPLE_POS_8X(pat
._8xSample
);
384 GEN_SAMPLE_POS_16X(pat
._16xSample
);
386 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
387 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
388 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
389 /* XXX: may need to set an offset for origin-UL framebuffers */
390 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
392 /* Just assign a static partitioning. */
393 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
394 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
395 alloc
._3DCommandSubOpcode
= 18 + i
;
396 alloc
.ConstantBufferOffset
= 6 * i
;
397 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
402 struct iris_viewport_state
{
403 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
) * IRIS_MAX_VIEWPORTS
];
406 struct iris_vertex_buffer_state
{
407 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
408 struct pipe_resource
*resources
[33];
409 unsigned num_buffers
;
412 struct iris_depth_buffer_state
{
413 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
414 GENX(3DSTATE_STENCIL_BUFFER_length
) +
415 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
416 GENX(3DSTATE_CLEAR_PARAMS_length
)];
420 * State that can't be stored directly in iris_context because the data
421 * layout varies per generation.
423 struct iris_genx_state
{
424 struct iris_viewport_state viewport
;
425 struct iris_vertex_buffer_state vertex_buffers
;
426 struct iris_depth_buffer_state depth_buffer
;
430 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
435 iris_set_blend_color(struct pipe_context
*ctx
,
436 const struct pipe_blend_color
*state
)
438 struct iris_context
*ice
= (struct iris_context
*) ctx
;
440 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
441 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
444 struct iris_blend_state
{
445 /** Partial 3DSTATE_PS_BLEND */
446 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
448 /** Partial BLEND_STATE */
449 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
450 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
452 bool alpha_to_coverage
; /* for shader key */
456 iris_create_blend_state(struct pipe_context
*ctx
,
457 const struct pipe_blend_state
*state
)
459 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
460 uint32_t *blend_state
= cso
->blend_state
;
462 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
464 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
465 /* pb.HasWriteableRT is filled in at draw time. */
466 /* pb.AlphaTestEnable is filled in at draw time. */
467 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
468 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
470 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
472 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
473 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
474 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
475 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
478 iris_pack_state(GENX(BLEND_STATE
), blend_state
, bs
) {
479 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
480 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
481 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
482 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
483 bs
.ColorDitherEnable
= state
->dither
;
484 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
487 blend_state
+= GENX(BLEND_STATE_length
);
489 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
490 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_state
, be
) {
491 be
.LogicOpEnable
= state
->logicop_enable
;
492 be
.LogicOpFunction
= state
->logicop_func
;
494 be
.PreBlendSourceOnlyClampEnable
= false;
495 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
496 be
.PreBlendColorClampEnable
= true;
497 be
.PostBlendColorClampEnable
= true;
499 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
501 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
502 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
503 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
504 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
505 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
506 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
508 be
.WriteDisableRed
= !(state
->rt
[i
].colormask
& PIPE_MASK_R
);
509 be
.WriteDisableGreen
= !(state
->rt
[i
].colormask
& PIPE_MASK_G
);
510 be
.WriteDisableBlue
= !(state
->rt
[i
].colormask
& PIPE_MASK_B
);
511 be
.WriteDisableAlpha
= !(state
->rt
[i
].colormask
& PIPE_MASK_A
);
513 blend_state
+= GENX(BLEND_STATE_ENTRY_length
);
520 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
522 struct iris_context
*ice
= (struct iris_context
*) ctx
;
523 ice
->state
.cso_blend
= state
;
524 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
525 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
528 struct iris_depth_stencil_alpha_state
{
529 /** Partial 3DSTATE_WM_DEPTH_STENCIL */
530 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
532 /** Complete CC_VIEWPORT */
533 uint32_t cc_vp
[GENX(CC_VIEWPORT_length
)];
535 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE */
536 struct pipe_alpha_state alpha
;
540 iris_create_zsa_state(struct pipe_context
*ctx
,
541 const struct pipe_depth_stencil_alpha_state
*state
)
543 struct iris_depth_stencil_alpha_state
*cso
=
544 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
546 cso
->alpha
= state
->alpha
;
548 bool two_sided_stencil
= state
->stencil
[1].enabled
;
550 /* The state tracker needs to optimize away EQUAL writes for us. */
551 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
553 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
554 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
555 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
556 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
557 wmds
.StencilTestFunction
=
558 translate_compare_func(state
->stencil
[0].func
);
559 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
560 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
561 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
562 wmds
.BackfaceStencilTestFunction
=
563 translate_compare_func(state
->stencil
[1].func
);
564 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
565 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
566 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
567 wmds
.StencilBufferWriteEnable
=
568 state
->stencil
[0].writemask
!= 0 ||
569 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
570 wmds
.DepthTestEnable
= state
->depth
.enabled
;
571 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
572 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
573 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
574 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
575 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
576 /* wmds.[Backface]StencilReferenceValue are merged later */
579 iris_pack_state(GENX(CC_VIEWPORT
), cso
->cc_vp
, ccvp
) {
580 ccvp
.MinimumDepth
= state
->depth
.bounds_min
;
581 ccvp
.MaximumDepth
= state
->depth
.bounds_max
;
588 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
590 struct iris_context
*ice
= (struct iris_context
*) ctx
;
591 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
592 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
595 if (cso_changed(alpha
.ref_value
))
596 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
598 if (cso_changed(alpha
.enabled
))
599 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
602 ice
->state
.cso_zsa
= new_cso
;
603 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
604 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
607 struct iris_rasterizer_state
{
608 uint32_t sf
[GENX(3DSTATE_SF_length
)];
609 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
610 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
611 uint32_t wm
[GENX(3DSTATE_WM_length
)];
612 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
614 bool flatshade
; /* for shader state */
615 bool clamp_fragment_color
; /* for shader state */
616 bool light_twoside
; /* for shader state */
617 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
618 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
619 bool line_stipple_enable
;
620 bool poly_stipple_enable
;
621 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
622 uint16_t sprite_coord_enable
;
626 iris_create_rasterizer_state(struct pipe_context
*ctx
,
627 const struct pipe_rasterizer_state
*state
)
629 struct iris_rasterizer_state
*cso
=
630 malloc(sizeof(struct iris_rasterizer_state
));
633 point_quad_rasterization
-> SBE
?
638 force_persample_interp
- ?
641 offset_units_unscaled
- cap
not exposed
645 cso
->flatshade
= state
->flatshade
;
646 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
647 cso
->light_twoside
= state
->light_twoside
;
648 cso
->rasterizer_discard
= state
->rasterizer_discard
;
649 cso
->half_pixel_center
= state
->half_pixel_center
;
650 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
651 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
652 cso
->line_stipple_enable
= state
->line_stipple_enable
;
653 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
655 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
656 sf
.StatisticsEnable
= true;
657 sf
.ViewportTransformEnable
= true;
658 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
659 sf
.LineEndCapAntialiasingRegionWidth
=
660 state
->line_smooth
? _10pixels
: _05pixels
;
661 sf
.LastPixelEnable
= state
->line_last_pixel
;
662 sf
.LineWidth
= state
->line_width
;
663 sf
.SmoothPointEnable
= state
->point_smooth
;
664 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
665 sf
.PointWidth
= state
->point_size
;
667 if (state
->flatshade_first
) {
668 sf
.TriangleFanProvokingVertexSelect
= 1;
670 sf
.TriangleStripListProvokingVertexSelect
= 2;
671 sf
.TriangleFanProvokingVertexSelect
= 2;
672 sf
.LineStripListProvokingVertexSelect
= 1;
676 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
677 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
678 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
679 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
680 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
681 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
682 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
683 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
684 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
685 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
686 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
687 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
688 rr
.SmoothPointEnable
= state
->point_smooth
;
689 rr
.AntialiasingEnable
= state
->line_smooth
;
690 rr
.ScissorRectangleEnable
= state
->scissor
;
691 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
692 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
693 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
696 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
697 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
698 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
700 cl
.StatisticsEnable
= true;
701 cl
.EarlyCullEnable
= true;
702 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
703 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
704 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
705 cl
.GuardbandClipTestEnable
= true;
706 cl
.ClipMode
= CLIPMODE_NORMAL
;
707 cl
.ClipEnable
= true;
708 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
709 cl
.MinimumPointWidth
= 0.125;
710 cl
.MaximumPointWidth
= 255.875;
712 if (state
->flatshade_first
) {
713 cl
.TriangleFanProvokingVertexSelect
= 1;
715 cl
.TriangleStripListProvokingVertexSelect
= 2;
716 cl
.TriangleFanProvokingVertexSelect
= 2;
717 cl
.LineStripListProvokingVertexSelect
= 1;
721 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
722 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
723 * filled in at draw time from the FS program.
725 wm
.LineAntialiasingRegionWidth
= _10pixels
;
726 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
727 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
728 wm
.StatisticsEnable
= true;
729 wm
.LineStippleEnable
= state
->line_stipple_enable
;
730 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
733 /* Remap from 0..255 back to 1..256 */
734 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
736 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
737 line
.LineStipplePattern
= state
->line_stipple_pattern
;
738 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
739 line
.LineStippleRepeatCount
= line_stipple_factor
;
746 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
748 struct iris_context
*ice
= (struct iris_context
*) ctx
;
749 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
750 struct iris_rasterizer_state
*new_cso
= state
;
753 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
754 if (cso_changed_memcmp(line_stipple
))
755 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
757 if (cso_changed(half_pixel_center
))
758 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
760 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
761 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
764 ice
->state
.cso_rast
= new_cso
;
765 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
766 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
770 translate_wrap(unsigned pipe_wrap
)
772 static const unsigned map
[] = {
773 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
774 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
775 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
776 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
777 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
778 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
780 /* These are unsupported. */
781 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
782 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
784 return map
[pipe_wrap
];
788 * Return true if the given wrap mode requires the border color to exist.
791 wrap_mode_needs_border_color(unsigned wrap_mode
)
793 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
797 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
799 static const unsigned map
[] = {
800 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
801 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
802 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
804 return map
[pipe_mip
];
807 struct iris_sampler_state
{
808 struct pipe_sampler_state base
;
810 bool needs_border_color
;
812 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
816 iris_create_sampler_state(struct pipe_context
*ctx
,
817 const struct pipe_sampler_state
*state
)
819 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
824 memcpy(&cso
->base
, state
, sizeof(*state
));
826 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
827 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
829 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
830 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
831 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
833 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
834 wrap_mode_needs_border_color(wrap_t
) ||
835 wrap_mode_needs_border_color(wrap_r
);
837 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
838 samp
.TCXAddressControlMode
= wrap_s
;
839 samp
.TCYAddressControlMode
= wrap_t
;
840 samp
.TCZAddressControlMode
= wrap_r
;
841 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
842 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
843 samp
.MinModeFilter
= state
->min_img_filter
;
844 samp
.MagModeFilter
= state
->mag_img_filter
;
845 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
846 samp
.MaximumAnisotropy
= RATIO21
;
848 if (state
->max_anisotropy
>= 2) {
849 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
850 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
851 samp
.AnisotropicAlgorithm
= EWAApproximation
;
854 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
855 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
857 samp
.MaximumAnisotropy
=
858 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
861 /* Set address rounding bits if not using nearest filtering. */
862 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
863 samp
.UAddressMinFilterRoundingEnable
= true;
864 samp
.VAddressMinFilterRoundingEnable
= true;
865 samp
.RAddressMinFilterRoundingEnable
= true;
868 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
869 samp
.UAddressMagFilterRoundingEnable
= true;
870 samp
.VAddressMagFilterRoundingEnable
= true;
871 samp
.RAddressMagFilterRoundingEnable
= true;
874 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
875 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
877 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
879 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
880 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
881 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
882 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
884 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
891 iris_bind_sampler_states(struct pipe_context
*ctx
,
892 enum pipe_shader_type p_stage
,
893 unsigned start
, unsigned count
,
896 struct iris_context
*ice
= (struct iris_context
*) ctx
;
897 gl_shader_stage stage
= stage_from_pipe(p_stage
);
899 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
900 ice
->state
.num_samplers
[stage
] =
901 MAX2(ice
->state
.num_samplers
[stage
], start
+ count
);
903 for (int i
= 0; i
< count
; i
++) {
904 ice
->state
.samplers
[stage
][start
+ i
] = states
[i
];
907 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
908 * in the dynamic state memory zone, so we can point to it via the
909 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
911 void *map
= upload_state(ice
->state
.dynamic_uploader
,
912 &ice
->state
.sampler_table
[stage
],
913 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
917 struct pipe_resource
*res
= ice
->state
.sampler_table
[stage
].res
;
918 ice
->state
.sampler_table
[stage
].offset
+=
919 iris_bo_offset_from_base_address(iris_resource_bo(res
));
921 /* Make sure all land in the same BO */
922 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
924 for (int i
= 0; i
< count
; i
++) {
925 struct iris_sampler_state
*state
= ice
->state
.samplers
[stage
][i
];
927 /* Save a pointer to the iris_sampler_state, a few fields need
928 * to inform draw-time decisions.
930 ice
->state
.samplers
[stage
][start
+ i
] = state
;
933 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
934 } else if (!state
->needs_border_color
) {
935 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
937 ice
->state
.need_border_colors
= true;
939 /* Stream out the border color and merge the pointer. */
941 iris_upload_border_color(ice
, &state
->base
.border_color
);
943 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
944 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
945 dyns
.BorderColorPointer
= offset
;
948 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
949 ((uint32_t *) map
)[j
] = state
->sampler_state
[j
] | dynamic
[j
];
952 map
+= GENX(SAMPLER_STATE_length
);
955 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
958 struct iris_sampler_view
{
959 struct pipe_sampler_view pipe
;
960 struct isl_view view
;
962 /** The resource (BO) holding our SURFACE_STATE. */
963 struct iris_state_ref surface_state
;
967 * Convert an swizzle enumeration (i.e. PIPE_SWIZZLE_X) to one of the Gen7.5+
968 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
970 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
973 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
975 * which is simply adding 4 then modding by 8 (or anding with 7).
977 * We then may need to apply workarounds for textureGather hardware bugs.
979 static enum isl_channel_select
980 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
982 return (swizzle
+ 4) & 7;
985 static struct pipe_sampler_view
*
986 iris_create_sampler_view(struct pipe_context
*ctx
,
987 struct pipe_resource
*tex
,
988 const struct pipe_sampler_view
*tmpl
)
990 struct iris_context
*ice
= (struct iris_context
*) ctx
;
991 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
992 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
993 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
998 /* initialize base object */
1000 isv
->pipe
.context
= ctx
;
1001 isv
->pipe
.texture
= NULL
;
1002 pipe_reference_init(&isv
->pipe
.reference
, 1);
1003 pipe_resource_reference(&isv
->pipe
.texture
, tex
);
1005 /* XXX: do we need brw_get_texture_swizzle hacks here? */
1007 isv
->view
= (struct isl_view
) {
1008 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
1009 .base_level
= tmpl
->u
.tex
.first_level
,
1010 .levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1,
1011 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1012 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1013 .swizzle
= (struct isl_swizzle
) {
1014 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
1015 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
1016 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
1017 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
1019 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
1020 (itex
->surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
),
1023 void *map
= upload_state(ice
->state
.surface_uploader
, &isv
->surface_state
,
1024 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1028 struct iris_bo
*state_bo
= iris_resource_bo(isv
->surface_state
.res
);
1029 isv
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1031 isl_surf_fill_state(&screen
->isl_dev
, map
,
1032 .surf
= &itex
->surf
, .view
= &isv
->view
,
1034 .address
= itex
->bo
->gtt_offset
);
1036 // .clear_color = clear_color,
1041 static struct pipe_surface
*
1042 iris_create_surface(struct pipe_context
*ctx
,
1043 struct pipe_resource
*tex
,
1044 const struct pipe_surface
*tmpl
)
1046 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1047 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1048 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1049 struct pipe_surface
*psurf
= &surf
->pipe
;
1050 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1055 pipe_reference_init(&psurf
->reference
, 1);
1056 pipe_resource_reference(&psurf
->texture
, tex
);
1057 psurf
->context
= ctx
;
1058 psurf
->format
= tmpl
->format
;
1059 psurf
->width
= tex
->width0
;
1060 psurf
->height
= tex
->height0
;
1061 psurf
->texture
= tex
;
1062 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1063 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1064 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1068 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1069 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1070 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1072 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1074 surf
->view
= (struct isl_view
) {
1075 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
1076 .base_level
= tmpl
->u
.tex
.level
,
1078 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1079 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1080 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1084 /* Bail early for depth/stencil */
1085 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1086 ISL_SURF_USAGE_STENCIL_BIT
))
1090 void *map
= upload_state(ice
->state
.surface_uploader
, &surf
->surface_state
,
1091 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1095 struct iris_bo
*state_bo
= iris_resource_bo(surf
->surface_state
.res
);
1096 surf
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1098 isl_surf_fill_state(&screen
->isl_dev
, map
,
1099 .surf
= &res
->surf
, .view
= &surf
->view
,
1101 .address
= res
->bo
->gtt_offset
);
1103 // .clear_color = clear_color,
1109 iris_set_sampler_views(struct pipe_context
*ctx
,
1110 enum pipe_shader_type p_stage
,
1111 unsigned start
, unsigned count
,
1112 struct pipe_sampler_view
**views
)
1114 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1115 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1118 for (i
= 0; i
< count
; i
++) {
1119 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1120 &ice
->state
.textures
[stage
][i
], views
[i
]);
1122 for (; i
< ice
->state
.num_textures
[stage
]; i
++) {
1123 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1124 &ice
->state
.textures
[stage
][i
], NULL
);
1127 ice
->state
.num_textures
[stage
] = count
;
1129 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
1133 iris_set_clip_state(struct pipe_context
*ctx
,
1134 const struct pipe_clip_state
*state
)
1139 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1140 const struct pipe_poly_stipple
*state
)
1142 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1143 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1144 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1148 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1150 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1152 ice
->state
.sample_mask
= sample_mask
;
1153 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1157 iris_set_scissor_states(struct pipe_context
*ctx
,
1158 unsigned start_slot
,
1159 unsigned num_scissors
,
1160 const struct pipe_scissor_state
*states
)
1162 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1164 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1165 ice
->state
.scissors
[start_slot
+ i
] = states
[i
];
1168 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1172 iris_set_stencil_ref(struct pipe_context
*ctx
,
1173 const struct pipe_stencil_ref
*state
)
1175 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1176 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1177 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1181 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1183 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1188 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1189 float m00
, float m11
, float m30
, float m31
,
1190 float *xmin
, float *xmax
,
1191 float *ymin
, float *ymax
)
1193 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1194 * Strips and Fans documentation:
1196 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1197 * fixed-point "guardband" range supported by the rasterization hardware"
1201 * "In almost all circumstances, if an object’s vertices are actually
1202 * modified by this clamping (i.e., had X or Y coordinates outside of
1203 * the guardband extent the rendered object will not match the intended
1204 * result. Therefore software should take steps to ensure that this does
1205 * not happen - e.g., by clipping objects such that they do not exceed
1206 * these limits after the Drawing Rectangle is applied."
1208 * I believe the fundamental restriction is that the rasterizer (in
1209 * the SF/WM stages) have a limit on the number of pixels that can be
1210 * rasterized. We need to ensure any coordinates beyond the rasterizer
1211 * limit are handled by the clipper. So effectively that limit becomes
1212 * the clipper's guardband size.
1214 * It goes on to say:
1216 * "In addition, in order to be correctly rendered, objects must have a
1217 * screenspace bounding box not exceeding 8K in the X or Y direction.
1218 * This additional restriction must also be comprehended by software,
1219 * i.e., enforced by use of clipping."
1221 * This makes no sense. Gen7+ hardware supports 16K render targets,
1222 * and you definitely need to be able to draw polygons that fill the
1223 * surface. Our assumption is that the rasterizer was limited to 8K
1224 * on Sandybridge, which only supports 8K surfaces, and it was actually
1225 * increased to 16K on Ivybridge and later.
1227 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1229 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1231 if (m00
!= 0 && m11
!= 0) {
1232 /* First, we compute the screen-space render area */
1233 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1234 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1235 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1236 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1238 /* We want the guardband to be centered on that */
1239 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1240 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1241 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1242 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1244 /* Now we need it in native device coordinates */
1245 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1246 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1247 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1248 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1250 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1251 * flipped upside-down. X should be fine though.
1253 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1254 *xmin
= ndc_gb_xmin
;
1255 *xmax
= ndc_gb_xmax
;
1256 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1257 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1259 /* The viewport scales to 0, so nothing will be rendered. */
1269 iris_set_viewport_states(struct pipe_context
*ctx
,
1270 unsigned start_slot
,
1272 const struct pipe_viewport_state
*states
)
1274 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1275 struct iris_viewport_state
*cso
= &ice
->state
.genx
->viewport
;
1276 uint32_t *vp_map
= &cso
->sf_cl_vp
[start_slot
];
1278 // XXX: sf_cl_vp is only big enough for one slot, we don't iterate right
1279 for (unsigned i
= 0; i
< count
; i
++) {
1280 const struct pipe_viewport_state
*state
= &states
[start_slot
+ i
];
1281 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
1282 vp
.ViewportMatrixElementm00
= state
->scale
[0];
1283 vp
.ViewportMatrixElementm11
= state
->scale
[1];
1284 vp
.ViewportMatrixElementm22
= state
->scale
[2];
1285 vp
.ViewportMatrixElementm30
= state
->translate
[0];
1286 vp
.ViewportMatrixElementm31
= state
->translate
[1];
1287 vp
.ViewportMatrixElementm32
= state
->translate
[2];
1288 /* XXX: in i965 this is computed based on the drawbuffer size,
1289 * but we don't have that here...
1291 vp
.XMinClipGuardband
= -1.0;
1292 vp
.XMaxClipGuardband
= 1.0;
1293 vp
.YMinClipGuardband
= -1.0;
1294 vp
.YMaxClipGuardband
= 1.0;
1295 vp
.XMinViewPort
= viewport_extent(state
, 0, -1.0f
);
1296 vp
.XMaxViewPort
= viewport_extent(state
, 0, 1.0f
) - 1;
1297 vp
.YMinViewPort
= viewport_extent(state
, 1, -1.0f
);
1298 vp
.YMaxViewPort
= viewport_extent(state
, 1, 1.0f
) - 1;
1301 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
1304 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1308 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1309 const struct pipe_framebuffer_state
*state
)
1311 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1312 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1313 struct isl_device
*isl_dev
= &screen
->isl_dev
;
1314 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1316 if (cso
->samples
!= state
->samples
) {
1317 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1320 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
1321 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1324 if ((cso
->layers
== 0) == (state
->layers
== 0)) {
1325 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1328 util_copy_framebuffer_state(cso
, state
);
1330 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
1332 struct isl_view view
= {
1335 .base_array_layer
= 0,
1337 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1340 struct isl_depth_stencil_hiz_emit_info info
= {
1345 struct iris_resource
*zres
=
1346 (void *) (cso
->zsbuf
? cso
->zsbuf
->texture
: NULL
);
1349 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
1351 info
.depth_surf
= &zres
->surf
;
1352 info
.depth_address
= zres
->bo
->gtt_offset
;
1354 view
.format
= zres
->surf
.format
;
1356 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
1357 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
1359 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
1361 info
.hiz_usage
= ISL_AUX_USAGE_NONE
;
1366 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
1367 info
.stencil_surf
= &stencil_mt
->surf
;
1370 view
.base_level
= stencil_irb
->mt_level
- stencil_irb
->mt
->first_level
;
1371 view
.base_array_layer
= stencil_irb
->mt_layer
;
1372 view
.array_len
= MAX2(stencil_irb
->layer_count
, 1);
1373 view
.format
= stencil_mt
->surf
.format
;
1376 uint32_t stencil_offset
= 0;
1377 info
.stencil_address
= stencil_mt
->bo
->gtt_offset
+ stencil_mt
->offset
;
1381 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
1383 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
1385 /* Render target change */
1386 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
1390 iris_set_constant_buffer(struct pipe_context
*ctx
,
1391 enum pipe_shader_type p_stage
, unsigned index
,
1392 const struct pipe_constant_buffer
*input
)
1394 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1395 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1396 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1397 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
1398 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
1400 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1401 if (input
->user_buffer
) {
1402 u_upload_data(ctx
->const_uploader
, 0, input
->buffer_size
, 32,
1403 input
->user_buffer
, &cbuf
->data
.offset
,
1406 pipe_resource_reference(&cbuf
->data
.res
, input
->buffer
);
1409 // XXX: these are not retained forever, use a separate uploader?
1411 upload_state(ice
->state
.surface_uploader
, &cbuf
->surface_state
,
1412 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1413 if (!unlikely(map
)) {
1414 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
1418 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
1419 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state
.res
);
1420 cbuf
->surface_state
.offset
+= iris_bo_offset_from_base_address(surf_bo
);
1422 isl_buffer_fill_state(&screen
->isl_dev
, map
,
1423 .address
= res
->bo
->gtt_offset
+ cbuf
->data
.offset
,
1424 .size_B
= input
->buffer_size
,
1425 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
1429 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
1430 pipe_resource_reference(&cbuf
->surface_state
.res
, NULL
);
1433 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
1434 // XXX: maybe not necessary all the time...?
1435 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1439 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1440 struct pipe_sampler_view
*state
)
1442 struct iris_sampler_view
*isv
= (void *) state
;
1443 pipe_resource_reference(&state
->texture
, NULL
);
1444 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1450 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1452 struct iris_surface
*surf
= (void *) p_surf
;
1453 pipe_resource_reference(&p_surf
->texture
, NULL
);
1454 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
1459 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1465 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
1467 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
1468 pipe_resource_reference(&cso
->resources
[i
], NULL
);
1472 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1473 unsigned start_slot
, unsigned count
,
1474 const struct pipe_vertex_buffer
*buffers
)
1476 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1477 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
1479 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
1484 cso
->num_buffers
= count
;
1486 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1487 vb
.DWordLength
= 4 * MAX2(cso
->num_buffers
, 1) - 1;
1490 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1493 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1494 vb
.VertexBufferIndex
= start_slot
;
1495 vb
.NullVertexBuffer
= true;
1496 vb
.AddressModifyEnable
= true;
1500 for (unsigned i
= 0; i
< count
; i
++) {
1501 assert(!buffers
[i
].is_user_buffer
);
1503 pipe_resource_reference(&cso
->resources
[i
], buffers
[i
].buffer
.resource
);
1504 struct iris_resource
*res
= (void *) cso
->resources
[i
];
1506 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1507 vb
.VertexBufferIndex
= start_slot
+ i
;
1509 vb
.AddressModifyEnable
= true;
1510 vb
.BufferPitch
= buffers
[i
].stride
;
1511 vb
.BufferSize
= res
->bo
->size
;
1512 vb
.BufferStartingAddress
=
1513 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffers
[i
].buffer_offset
);
1516 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1519 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1522 struct iris_vertex_element_state
{
1523 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1524 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
1529 iris_create_vertex_elements(struct pipe_context
*ctx
,
1531 const struct pipe_vertex_element
*state
)
1533 struct iris_vertex_element_state
*cso
=
1534 malloc(sizeof(struct iris_vertex_element_state
));
1536 cso
->count
= MAX2(count
, 1);
1539 * - create edge flag one
1541 * - if those are necessary, use count + 1/2/3... OR in the length
1543 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
1544 ve
.DWordLength
= 1 + GENX(VERTEX_ELEMENT_STATE_length
) * cso
->count
- 2;
1547 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1548 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
1551 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1553 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
1554 ve
.Component0Control
= VFCOMP_STORE_0
;
1555 ve
.Component1Control
= VFCOMP_STORE_0
;
1556 ve
.Component2Control
= VFCOMP_STORE_0
;
1557 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
1560 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
1564 for (int i
= 0; i
< count
; i
++) {
1565 enum isl_format isl_format
=
1566 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1567 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
1568 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
1570 switch (isl_format_get_num_channels(isl_format
)) {
1571 case 0: comp
[0] = VFCOMP_STORE_0
;
1572 case 1: comp
[1] = VFCOMP_STORE_0
;
1573 case 2: comp
[2] = VFCOMP_STORE_0
;
1575 comp
[3] = isl_format_has_int_channel(isl_format
) ? VFCOMP_STORE_1_INT
1576 : VFCOMP_STORE_1_FP
;
1579 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1580 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1582 ve
.SourceElementOffset
= state
[i
].src_offset
;
1583 ve
.SourceElementFormat
= isl_format
;
1584 ve
.Component0Control
= comp
[0];
1585 ve
.Component1Control
= comp
[1];
1586 ve
.Component2Control
= comp
[2];
1587 ve
.Component3Control
= comp
[3];
1590 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
1591 vi
.VertexElementIndex
= i
;
1592 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1593 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1596 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1597 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
1604 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
1606 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1608 ice
->state
.cso_vertex_elements
= state
;
1609 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
1613 iris_create_compute_state(struct pipe_context
*ctx
,
1614 const struct pipe_compute_state
*state
)
1619 static struct pipe_stream_output_target
*
1620 iris_create_stream_output_target(struct pipe_context
*ctx
,
1621 struct pipe_resource
*res
,
1622 unsigned buffer_offset
,
1623 unsigned buffer_size
)
1625 struct pipe_stream_output_target
*t
=
1626 CALLOC_STRUCT(pipe_stream_output_target
);
1630 pipe_reference_init(&t
->reference
, 1);
1631 pipe_resource_reference(&t
->buffer
, res
);
1632 t
->buffer_offset
= buffer_offset
;
1633 t
->buffer_size
= buffer_size
;
1638 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
1639 struct pipe_stream_output_target
*t
)
1641 pipe_resource_reference(&t
->buffer
, NULL
);
1646 iris_set_stream_output_targets(struct pipe_context
*ctx
,
1647 unsigned num_targets
,
1648 struct pipe_stream_output_target
**targets
,
1649 const unsigned *offsets
)
1654 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
1655 const struct brw_vue_map
*last_vue_map
,
1656 bool two_sided_color
,
1657 unsigned *out_offset
,
1658 unsigned *out_length
)
1660 /* The compiler computes the first URB slot without considering COL/BFC
1661 * swizzling (because it doesn't know whether it's enabled), so we need
1662 * to do that here too. This may result in a smaller offset, which
1665 const unsigned first_slot
=
1666 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
1668 /* This becomes the URB read offset (counted in pairs of slots). */
1669 assert(first_slot
% 2 == 0);
1670 *out_offset
= first_slot
/ 2;
1672 /* We need to adjust the inputs read to account for front/back color
1673 * swizzling, as it can make the URB length longer.
1675 for (int c
= 0; c
<= 1; c
++) {
1676 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
1677 /* If two sided color is enabled, the fragment shader's gl_Color
1678 * (COL0) input comes from either the gl_FrontColor (COL0) or
1679 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
1681 if (two_sided_color
)
1682 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1684 /* If front color isn't written, we opt to give them back color
1685 * instead of an undefined value. Switch from COL to BFC.
1687 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
1688 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
1689 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1694 /* Compute the minimum URB Read Length necessary for the FS inputs.
1696 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1697 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1699 * "This field should be set to the minimum length required to read the
1700 * maximum source attribute. The maximum source attribute is indicated
1701 * by the maximum value of the enabled Attribute # Source Attribute if
1702 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1703 * enable is not set.
1704 * read_length = ceiling((max_source_attr + 1) / 2)
1706 * [errata] Corruption/Hang possible if length programmed larger than
1709 * Similar text exists for Ivy Bridge.
1711 * We find the last URB slot that's actually read by the FS.
1713 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
1714 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
1715 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
1718 /* The URB read length is the difference of the two, counted in pairs. */
1719 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
1723 iris_emit_sbe_swiz(struct iris_batch
*batch
,
1724 const struct iris_context
*ice
,
1725 unsigned urb_read_offset
)
1727 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
1728 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
1729 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
1730 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
1731 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
1733 /* XXX: this should be generated when putting programs in place */
1735 // XXX: raster->sprite_coord_enable
1737 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
1738 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
1739 if (input_index
< 0 || input_index
>= 16)
1742 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
1743 &attr_overrides
[input_index
];
1745 /* Viewport and Layer are stored in the VUE header. We need to override
1746 * them to zero if earlier stages didn't write them, as GL requires that
1747 * they read back as zero when not explicitly set.
1750 case VARYING_SLOT_VIEWPORT
:
1751 case VARYING_SLOT_LAYER
:
1752 attr
->ComponentOverrideX
= true;
1753 attr
->ComponentOverrideW
= true;
1754 attr
->ConstantSource
= CONST_0000
;
1756 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
1757 attr
->ComponentOverrideY
= true;
1758 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
1759 attr
->ComponentOverrideZ
= true;
1762 case VARYING_SLOT_PRIMITIVE_ID
:
1763 attr
->ComponentOverrideX
= true;
1764 attr
->ComponentOverrideY
= true;
1765 attr
->ComponentOverrideZ
= true;
1766 attr
->ComponentOverrideW
= true;
1767 attr
->ConstantSource
= PRIM_ID
;
1774 int slot
= vue_map
->varying_to_slot
[fs_attr
];
1776 /* If there was only a back color written but not front, use back
1777 * as the color instead of undefined.
1779 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
1780 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
1781 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
1782 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
1784 /* Not written by the previous stage - undefined. */
1786 attr
->ComponentOverrideX
= true;
1787 attr
->ComponentOverrideY
= true;
1788 attr
->ComponentOverrideZ
= true;
1789 attr
->ComponentOverrideW
= true;
1790 attr
->ConstantSource
= CONST_0001_FLOAT
;
1794 /* Compute the location of the attribute relative to the read offset,
1795 * which is counted in 256-bit increments (two 128-bit VUE slots).
1797 const int source_attr
= slot
- 2 * urb_read_offset
;
1798 assert(source_attr
>= 0 && source_attr
<= 32);
1799 attr
->SourceAttribute
= source_attr
;
1801 /* If we are doing two-sided color, and the VUE slot following this one
1802 * represents a back-facing color, then we need to instruct the SF unit
1803 * to do back-facing swizzling.
1805 if (cso_rast
->light_twoside
&&
1806 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1807 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1808 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1809 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
1810 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1813 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
1814 for (int i
= 0; i
< 16; i
++)
1815 sbes
.Attribute
[i
] = attr_overrides
[i
];
1820 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
1822 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
1823 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
1824 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
1825 struct pipe_shader_state
*p_fs
=
1826 (void *) ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1827 assert(p_fs
->type
== PIPE_SHADER_IR_NIR
);
1828 nir_shader
*fs_nir
= p_fs
->ir
.nir
;
1830 unsigned urb_read_offset
, urb_read_length
;
1831 iris_compute_sbe_urb_read_interval(fs_nir
->info
.inputs_read
,
1832 ice
->shaders
.last_vue_map
,
1833 cso_rast
->light_twoside
,
1834 &urb_read_offset
, &urb_read_length
);
1836 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
1837 sbe
.AttributeSwizzleEnable
= true;
1838 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1839 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
1840 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
1841 sbe
.VertexURBEntryReadLength
= urb_read_length
;
1842 sbe
.ForceVertexURBEntryReadOffset
= true;
1843 sbe
.ForceVertexURBEntryReadLength
= true;
1844 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1846 for (int i
= 0; i
< 32; i
++) {
1847 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
1851 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
);
1855 iris_bind_compute_state(struct pipe_context
*ctx
, void *state
)
1860 iris_populate_sampler_key(const struct iris_context
*ice
,
1861 struct brw_sampler_prog_key_data
*key
)
1863 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
1864 key
->swizzles
[i
] = 0x688; /* XYZW */
1869 iris_populate_vs_key(const struct iris_context
*ice
,
1870 struct brw_vs_prog_key
*key
)
1872 memset(key
, 0, sizeof(*key
));
1873 iris_populate_sampler_key(ice
, &key
->tex
);
1877 iris_populate_tcs_key(const struct iris_context
*ice
,
1878 struct brw_tcs_prog_key
*key
)
1880 memset(key
, 0, sizeof(*key
));
1881 iris_populate_sampler_key(ice
, &key
->tex
);
1885 iris_populate_tes_key(const struct iris_context
*ice
,
1886 struct brw_tes_prog_key
*key
)
1888 memset(key
, 0, sizeof(*key
));
1889 iris_populate_sampler_key(ice
, &key
->tex
);
1893 iris_populate_gs_key(const struct iris_context
*ice
,
1894 struct brw_gs_prog_key
*key
)
1896 memset(key
, 0, sizeof(*key
));
1897 iris_populate_sampler_key(ice
, &key
->tex
);
1901 iris_populate_fs_key(const struct iris_context
*ice
,
1902 struct brw_wm_prog_key
*key
)
1904 memset(key
, 0, sizeof(*key
));
1905 iris_populate_sampler_key(ice
, &key
->tex
);
1907 /* XXX: dirty flags? */
1908 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
1909 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
1910 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
1911 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
1913 key
->nr_color_regions
= fb
->nr_cbufs
;
1915 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
1917 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
1918 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
1920 /* XXX: only bother if COL0/1 are read */
1921 key
->flat_shade
= rast
->flatshade
;
1923 // key->force_dual_color_blend for unigine
1925 if (cso_rast
->multisample
) {
1926 key
->persample_interp
=
1927 ctx
->Multisample
.SampleShading
&&
1928 (ctx
->Multisample
.MinSampleShadingValue
*
1929 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1);
1931 key
->multisample_fbo
= fb
->samples
> 1;
1935 key
->coherent_fb_fetch
= true;
1939 // XXX: these need to go in INIT_THREAD_DISPATCH_FIELDS
1940 pkt
.SamplerCount
= \
1941 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4); \
1942 pkt
.PerThreadScratchSpace
= prog_data
->total_scratch
== 0 ? 0 : \
1943 ffs(stage_state
->per_thread_scratch
) - 11; \
1948 KSP(const struct iris_compiled_shader
*shader
)
1950 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
1951 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
1954 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1955 pkt.KernelStartPointer = KSP(shader); \
1956 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
1957 pkt.FloatingPointMode = prog_data->use_alt_mode; \
1959 pkt.DispatchGRFStartRegisterForURBData = \
1960 prog_data->dispatch_grf_start_reg; \
1961 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1962 pkt.prefix##URBEntryReadOffset = 0; \
1964 pkt.StatisticsEnable = true; \
1968 iris_store_vs_state(const struct gen_device_info
*devinfo
,
1969 struct iris_compiled_shader
*shader
)
1971 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1972 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1974 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
1975 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1976 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1977 vs
.SIMD8DispatchEnable
= true;
1978 vs
.UserClipDistanceCullTestEnableBitmask
=
1979 vue_prog_data
->cull_distance_mask
;
1984 iris_store_tcs_state(const struct gen_device_info
*devinfo
,
1985 struct iris_compiled_shader
*shader
)
1987 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1988 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1989 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
1991 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
1992 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
1994 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
1995 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
1996 hs
.IncludeVertexHandles
= true;
2001 iris_store_tes_state(const struct gen_device_info
*devinfo
,
2002 struct iris_compiled_shader
*shader
)
2004 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2005 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2006 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
2008 uint32_t *te_state
= (void *) shader
->derived_data
;
2009 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
2011 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
2012 te
.Partitioning
= tes_prog_data
->partitioning
;
2013 te
.OutputTopology
= tes_prog_data
->output_topology
;
2014 te
.TEDomain
= tes_prog_data
->domain
;
2016 te
.MaximumTessellationFactorOdd
= 63.0;
2017 te
.MaximumTessellationFactorNotOdd
= 64.0;
2020 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
2021 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
2023 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
2024 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
2025 ds
.ComputeWCoordinateEnable
=
2026 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
2028 ds
.UserClipDistanceCullTestEnableBitmask
=
2029 vue_prog_data
->cull_distance_mask
;
2035 iris_store_gs_state(const struct gen_device_info
*devinfo
,
2036 struct iris_compiled_shader
*shader
)
2038 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2039 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2040 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
2042 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
2043 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2045 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2046 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2047 gs
.ControlDataHeaderSize
=
2048 gs_prog_data
->control_data_header_size_hwords
;
2049 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2050 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
2051 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2052 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2053 gs
.ReorderMode
= TRAILING
;
2054 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2055 gs
.MaximumNumberofThreads
=
2056 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2057 : (devinfo
->max_gs_threads
- 1);
2059 if (gs_prog_data
->static_vertex_count
!= -1) {
2060 gs
.StaticOutput
= true;
2061 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2063 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2065 gs
.UserClipDistanceCullTestEnableBitmask
=
2066 vue_prog_data
->cull_distance_mask
;
2068 const int urb_entry_write_offset
= 1;
2069 const uint32_t urb_entry_output_length
=
2070 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2071 urb_entry_write_offset
;
2073 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2074 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2079 iris_store_fs_state(const struct gen_device_info
*devinfo
,
2080 struct iris_compiled_shader
*shader
)
2082 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2083 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
2085 uint32_t *ps_state
= (void *) shader
->derived_data
;
2086 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
2088 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
2089 ps
.VectorMaskEnable
= true;
2090 //ps.SamplerCount = ...
2091 ps
.BindingTableEntryCount
= prog_data
->binding_table
.size_bytes
/ 4;
2092 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
2093 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
2095 ps
.PushConstantEnable
= prog_data
->nr_params
> 0 ||
2096 prog_data
->ubo_ranges
[0].length
> 0;
2098 /* From the documentation for this packet:
2099 * "If the PS kernel does not need the Position XY Offsets to
2100 * compute a Position Value, then this field should be programmed
2101 * to POSOFFSET_NONE."
2103 * "SW Recommendation: If the PS kernel needs the Position Offsets
2104 * to compute a Position XY value, this field should match Position
2105 * ZW Interpolation Mode to ensure a consistent position.xyzw
2108 * We only require XY sample offsets. So, this recommendation doesn't
2109 * look useful at the moment. We might need this in future.
2111 ps
.PositionXYOffsetSelect
=
2112 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
2113 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
2114 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
2115 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
2117 // XXX: Disable SIMD32 with 16x MSAA
2119 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
2120 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
2121 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
2122 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
2123 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
2124 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
2126 ps
.KernelStartPointer0
=
2127 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
2128 ps
.KernelStartPointer1
=
2129 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
2130 ps
.KernelStartPointer2
=
2131 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
2134 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
2135 psx
.PixelShaderValid
= true;
2136 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
2137 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
2138 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
2139 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
2140 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
2141 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
2143 if (wm_prog_data
->uses_sample_mask
) {
2144 /* TODO: conservative rasterization */
2145 if (wm_prog_data
->post_depth_coverage
)
2146 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
2148 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
2151 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
2152 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
2153 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
2160 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
2162 assert(cache_id
<= IRIS_CACHE_BLORP
);
2164 static const unsigned dwords
[] = {
2165 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
2166 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
2167 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
2168 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
2170 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
2171 [IRIS_CACHE_CS
] = 0,
2172 [IRIS_CACHE_BLORP
] = 0,
2175 return sizeof(uint32_t) * dwords
[cache_id
];
2179 iris_store_derived_program_state(const struct gen_device_info
*devinfo
,
2180 enum iris_program_cache_id cache_id
,
2181 struct iris_compiled_shader
*shader
)
2185 iris_store_vs_state(devinfo
, shader
);
2187 case IRIS_CACHE_TCS
:
2188 iris_store_tcs_state(devinfo
, shader
);
2190 case IRIS_CACHE_TES
:
2191 iris_store_tes_state(devinfo
, shader
);
2194 iris_store_gs_state(devinfo
, shader
);
2197 iris_store_fs_state(devinfo
, shader
);
2200 case IRIS_CACHE_BLORP
:
2208 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
2210 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
2211 const unsigned push_size_kB
= 32;
2212 unsigned entries
[4];
2216 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2217 if (!ice
->shaders
.prog
[i
]) {
2220 struct brw_vue_prog_data
*vue_prog_data
=
2221 (void *) ice
->shaders
.prog
[i
]->prog_data
;
2222 size
[i
] = vue_prog_data
->urb_entry_size
;
2224 assert(size
[i
] != 0);
2227 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
2228 1024 * ice
->shaders
.urb_size
,
2229 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
2230 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
2231 size
, entries
, start
);
2233 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2234 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
2235 urb
._3DCommandSubOpcode
+= i
;
2236 urb
.VSURBStartingAddress
= start
[i
];
2237 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
2238 urb
.VSNumberofURBEntries
= entries
[i
];
2243 static const uint32_t push_constant_opcodes
[] = {
2244 [MESA_SHADER_VERTEX
] = 21,
2245 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2246 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2247 [MESA_SHADER_GEOMETRY
] = 22,
2248 [MESA_SHADER_FRAGMENT
] = 23,
2249 [MESA_SHADER_COMPUTE
] = 0,
2253 * Add a surface to the validation list, as well as the buffer containing
2254 * the corresponding SURFACE_STATE.
2256 * Returns the binding table entry (offset to SURFACE_STATE).
2259 use_surface(struct iris_batch
*batch
,
2260 struct pipe_surface
*p_surf
,
2263 struct iris_surface
*surf
= (void *) p_surf
;
2265 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
2266 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
2268 return surf
->surface_state
.offset
;
2272 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
2274 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->pipe
.texture
), false);
2275 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
2277 return isv
->surface_state
.offset
;
2281 use_const_buffer(struct iris_batch
*batch
, struct iris_const_buffer
*cbuf
)
2283 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->data
.res
), false);
2284 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->surface_state
.res
), false);
2286 return cbuf
->surface_state
.offset
;
2290 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
2292 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
2294 iris_use_pinned_bo(batch
, state_bo
, false);
2296 return ice
->state
.unbound_tex
.offset
;
2300 iris_populate_binding_table(struct iris_context
*ice
,
2301 struct iris_batch
*batch
,
2302 gl_shader_stage stage
)
2304 const struct iris_binder
*binder
= &batch
->binder
;
2305 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2311 // - ubos/ssbos/abos
2314 // - render targets - write and read
2316 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
2317 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
2320 if (stage
== MESA_SHADER_FRAGMENT
) {
2321 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2322 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
2323 bt_map
[s
++] = use_surface(batch
, cso_fb
->cbufs
[i
], true);
2327 //assert(prog_data->binding_table.texture_start ==
2328 //(ice->state.num_textures[stage] ? s : 0xd0d0d0d0));
2330 for (int i
= 0; i
< ice
->state
.num_textures
[stage
]; i
++) {
2331 struct iris_sampler_view
*view
= ice
->state
.textures
[stage
][i
];
2332 bt_map
[s
++] = view
? use_sampler_view(batch
, view
)
2333 : use_null_surface(batch
, ice
);
2336 // XXX: want the number of BTE's to shorten this loop
2337 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2338 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
2339 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[i
];
2340 if (!cbuf
->surface_state
.res
)
2343 bt_map
[s
++] = use_const_buffer(batch
, cbuf
);
2346 // XXX: not implemented yet
2347 assert(prog_data
->binding_table
.pull_constants_start
== 0xd0d0d0d0);
2348 assert(prog_data
->binding_table
.ubo_start
== 0xd0d0d0d0);
2349 assert(prog_data
->binding_table
.ssbo_start
== 0xd0d0d0d0);
2350 assert(prog_data
->binding_table
.image_start
== 0xd0d0d0d0);
2351 assert(prog_data
->binding_table
.shader_time_start
== 0xd0d0d0d0);
2352 //assert(prog_data->binding_table.plane_start[1] == 0xd0d0d0d0);
2353 //assert(prog_data->binding_table.plane_start[2] == 0xd0d0d0d0);
2358 iris_use_optional_res(struct iris_batch
*batch
,
2359 struct pipe_resource
*res
,
2363 struct iris_bo
*bo
= iris_resource_bo(res
);
2364 iris_use_pinned_bo(batch
, bo
, writeable
);
2370 * Pin any BOs which were installed by a previous batch, and restored
2371 * via the hardware logical context mechanism.
2373 * We don't need to re-emit all state every batch - the hardware context
2374 * mechanism will save and restore it for us. This includes pointers to
2375 * various BOs...which won't exist unless we ask the kernel to pin them
2376 * by adding them to the validation list.
2378 * We can skip buffers if we've re-emitted those packets, as we're
2379 * overwriting those stale pointers with new ones, and don't actually
2380 * refer to the old BOs.
2383 iris_restore_context_saved_bos(struct iris_context
*ice
,
2384 struct iris_batch
*batch
,
2385 const struct pipe_draw_info
*draw
)
2387 // XXX: whack IRIS_SHADER_DIRTY_BINDING_TABLE on new batch
2389 const uint64_t clean
= ~ice
->state
.dirty
;
2391 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
2392 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
2395 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
2396 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
2399 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
2400 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
2403 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
2404 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
2407 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
2408 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
2411 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2412 if (clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
))
2415 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2416 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2421 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
2423 for (int i
= 0; i
< 4; i
++) {
2424 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2426 if (range
->length
== 0)
2429 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
2430 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2433 iris_use_pinned_bo(batch
, res
->bo
, false);
2435 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
2439 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2440 struct pipe_resource
*res
= ice
->state
.sampler_table
[stage
].res
;
2442 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
2445 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2446 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
2447 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2449 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
2450 iris_use_pinned_bo(batch
, bo
, false);
2453 // XXX: scratch buffer
2457 // XXX: 3DSTATE_SO_BUFFER
2459 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
2460 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2462 if (cso_fb
->zsbuf
) {
2463 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
2464 // XXX: depth might not be writable...
2465 iris_use_pinned_bo(batch
, zres
->bo
, true);
2469 if (draw
->index_size
> 0) {
2470 // XXX: index buffer
2473 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
2474 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
2475 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
2476 struct iris_resource
*res
= (void *) cso
->resources
[i
];
2477 iris_use_pinned_bo(batch
, res
->bo
, false);
2483 iris_upload_render_state(struct iris_context
*ice
,
2484 struct iris_batch
*batch
,
2485 const struct pipe_draw_info
*draw
)
2487 const uint64_t dirty
= ice
->state
.dirty
;
2489 struct brw_wm_prog_data
*wm_prog_data
= (void *)
2490 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2492 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
2493 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2494 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2495 ptr
.CCViewportPointer
=
2496 emit_state(batch
, ice
->state
.dynamic_uploader
,
2497 &ice
->state
.last_res
.cc_vp
,
2498 cso
->cc_vp
, sizeof(cso
->cc_vp
), 32);
2502 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
2503 struct iris_viewport_state
*cso
= &ice
->state
.genx
->viewport
;
2504 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2505 ptr
.SFClipViewportPointer
=
2506 emit_state(batch
, ice
->state
.dynamic_uploader
,
2507 &ice
->state
.last_res
.sf_cl_vp
,
2508 cso
->sf_cl_vp
, 4 * GENX(SF_CLIP_VIEWPORT_length
) *
2509 ice
->state
.num_viewports
, 64);
2515 // XXX: this is only flagged at setup, we assume a static configuration
2516 if (dirty
& IRIS_DIRTY_URB
) {
2517 iris_upload_urb_config(ice
, batch
);
2520 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
2521 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2522 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2523 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2524 const int num_dwords
= 4 * (GENX(BLEND_STATE_length
) +
2525 cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
));
2526 uint32_t blend_offset
;
2527 uint32_t *blend_map
=
2528 stream_state(batch
, ice
->state
.dynamic_uploader
,
2529 &ice
->state
.last_res
.blend
,
2530 4 * num_dwords
, 64, &blend_offset
);
2532 uint32_t blend_state_header
;
2533 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
2534 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2535 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
2538 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
2539 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1],
2540 sizeof(cso_blend
->blend_state
) - sizeof(uint32_t));
2542 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2543 ptr
.BlendStatePointer
= blend_offset
;
2544 ptr
.BlendStatePointerValid
= true;
2548 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
2549 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2552 stream_state(batch
, ice
->state
.dynamic_uploader
,
2553 &ice
->state
.last_res
.color_calc
,
2554 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
2556 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
2557 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
2558 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
2559 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
2560 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
2561 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
2562 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
2564 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2565 ptr
.ColorCalcStatePointer
= cc_offset
;
2566 ptr
.ColorCalcStatePointerValid
= true;
2570 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2571 // XXX: wrong dirty tracking...
2572 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
2575 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2576 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2581 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
2583 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2584 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2586 /* The Skylake PRM contains the following restriction:
2588 * "The driver must ensure The following case does not occur
2589 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2590 * buffer 3 read length equal to zero committed followed by a
2591 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2594 * To avoid this, we program the buffers in the highest slots.
2595 * This way, slot 0 is only used if slot 3 is also used.
2599 for (int i
= 3; i
>= 0; i
--) {
2600 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2602 if (range
->length
== 0)
2605 // XXX: is range->block a constbuf index? it would be nice
2606 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
2607 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2609 assert(cbuf
->data
.offset
% 32 == 0);
2611 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
2612 pkt
.ConstantBody
.Buffer
[n
] =
2613 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->data
.offset
)
2614 : ro_bo(batch
->screen
->workaround_bo
, 0);
2621 struct iris_binder
*binder
= &batch
->binder
;
2623 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2624 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
2625 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
2626 ptr
._3DCommandSubOpcode
= 38 + stage
;
2627 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
2632 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2633 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
2634 iris_populate_binding_table(ice
, batch
, stage
);
2638 if (ice
->state
.need_border_colors
)
2639 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
2641 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2642 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
2643 !ice
->shaders
.prog
[stage
])
2646 struct pipe_resource
*res
= ice
->state
.sampler_table
[stage
].res
;
2648 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
2650 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
2651 ptr
._3DCommandSubOpcode
= 43 + stage
;
2652 ptr
.PointertoVSSamplerState
= ice
->state
.sampler_table
[stage
].offset
;
2656 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
2657 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
2659 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
2660 if (ice
->state
.framebuffer
.samples
> 0)
2661 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
2665 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
2666 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
2667 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
2671 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2672 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
2675 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2678 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
2679 iris_use_pinned_bo(batch
, cache
->bo
, false);
2680 iris_batch_emit(batch
, shader
->derived_data
,
2681 iris_derived_program_state_size(stage
));
2683 if (stage
== MESA_SHADER_TESS_EVAL
) {
2684 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
2685 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
2686 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
2687 } else if (stage
== MESA_SHADER_GEOMETRY
) {
2688 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
2694 // 3DSTATE_STREAMOUT
2695 // 3DSTATE_SO_BUFFER
2696 // 3DSTATE_SO_DECL_LIST
2698 if (dirty
& IRIS_DIRTY_CLIP
) {
2699 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2700 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2702 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
2703 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
2704 if (wm_prog_data
->barycentric_interp_modes
&
2705 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
2706 cl
.NonPerspectiveBarycentricEnable
= true;
2708 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
2709 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
2711 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
2712 ARRAY_SIZE(cso_rast
->clip
));
2715 if (dirty
& IRIS_DIRTY_RASTER
) {
2716 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2717 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
2718 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
2722 /* XXX: FS program updates needs to flag IRIS_DIRTY_WM */
2723 if (dirty
& IRIS_DIRTY_WM
) {
2724 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2725 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
2727 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
2728 wm
.BarycentricInterpolationMode
=
2729 wm_prog_data
->barycentric_interp_modes
;
2731 if (wm_prog_data
->early_fragment_tests
)
2732 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
2733 else if (wm_prog_data
->has_side_effects
)
2734 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
2736 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
2740 // XXX: 3DSTATE_SBE, 3DSTATE_SBE_SWIZ
2741 // -> iris_raster_state (point sprite texture coordinate origin)
2742 // -> bunch of shader state...
2743 iris_emit_sbe(batch
, ice
);
2746 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
2747 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2748 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2749 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
2750 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
2751 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
2752 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2755 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
2756 ARRAY_SIZE(cso_blend
->ps_blend
));
2759 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
2760 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2761 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
2763 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
2764 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
2765 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
2766 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
2768 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
2771 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
2772 uint32_t scissor_offset
=
2773 emit_state(batch
, ice
->state
.dynamic_uploader
,
2774 &ice
->state
.last_res
.scissor
,
2775 ice
->state
.scissors
,
2776 sizeof(struct pipe_scissor_state
) *
2777 ice
->state
.num_viewports
, 32);
2779 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2780 ptr
.ScissorRectPointer
= scissor_offset
;
2784 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
2785 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2786 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2788 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
2790 if (cso_fb
->zsbuf
) {
2791 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
2792 // XXX: depth might not be writable...
2793 iris_use_pinned_bo(batch
, zres
->bo
, true);
2797 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
2798 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
2799 for (int i
= 0; i
< 32; i
++) {
2800 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
2805 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
2806 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2807 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
2811 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
2812 topo
.PrimitiveTopologyType
=
2813 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
2817 if (draw
->index_size
> 0) {
2818 struct iris_resource
*res
= NULL
;
2821 if (draw
->has_user_indices
) {
2822 u_upload_data(ice
->ctx
.stream_uploader
, 0,
2823 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
2824 &offset
, (struct pipe_resource
**) &res
);
2826 res
= (struct iris_resource
*) draw
->index
.resource
;
2830 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
2831 ib
.IndexFormat
= draw
->index_size
>> 1;
2833 ib
.BufferSize
= res
->bo
->size
;
2834 ib
.BufferStartingAddress
= ro_bo(res
->bo
, offset
);
2838 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
2839 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
2840 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
2842 if (cso
->num_buffers
> 0) {
2843 iris_batch_emit(batch
, cso
->vertex_buffers
, sizeof(uint32_t) *
2844 (1 + vb_dwords
* cso
->num_buffers
));
2846 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
2847 struct iris_resource
*res
= (void *) cso
->resources
[i
];
2848 iris_use_pinned_bo(batch
, res
->bo
, false);
2853 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
2854 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
2855 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
2856 (1 + cso
->count
* GENX(VERTEX_ELEMENT_STATE_length
)));
2857 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
2858 cso
->count
* GENX(3DSTATE_VF_INSTANCING_length
));
2859 for (int i
= 0; i
< cso
->count
; i
++) {
2860 /* TODO: vertexid, instanceid support */
2861 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
);
2866 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
2867 if (draw
->primitive_restart
) {
2868 vf
.IndexedDrawCutIndexEnable
= true;
2869 vf
.CutIndex
= draw
->restart_index
;
2874 // XXX: Gen8 - PMA fix
2876 assert(!draw
->indirect
); // XXX: indirect support
2878 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
2879 prim
.StartInstanceLocation
= draw
->start_instance
;
2880 prim
.InstanceCount
= draw
->instance_count
;
2881 prim
.VertexCountPerInstance
= draw
->count
;
2882 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
2884 // XXX: this is probably bonkers.
2885 prim
.StartVertexLocation
= draw
->start
;
2887 if (draw
->index_size
) {
2888 prim
.BaseVertexLocation
+= draw
->index_bias
;
2890 prim
.StartVertexLocation
+= draw
->index_bias
;
2893 //prim.BaseVertexLocation = ...;
2896 if (!batch
->contains_draw
) {
2897 iris_restore_context_saved_bos(ice
, batch
, draw
);
2898 batch
->contains_draw
= true;
2903 * State module teardown.
2906 iris_destroy_state(struct iris_context
*ice
)
2908 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
2910 // XXX: unreference resources/surfaces.
2911 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
2912 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
2914 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
2916 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
2917 pipe_resource_reference(&ice
->state
.sampler_table
[stage
].res
, NULL
);
2919 free(ice
->state
.genx
);
2921 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
2922 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
2923 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
2924 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
2925 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
2929 flags_to_post_sync_op(uint32_t flags
)
2931 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
2932 return WriteImmediateData
;
2934 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
2935 return WritePSDepthCount
;
2937 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
2938 return WriteTimestamp
;
2944 * Do the given flags have a Post Sync or LRI Post Sync operation?
2946 static enum pipe_control_flags
2947 get_post_sync_flags(enum pipe_control_flags flags
)
2949 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
2950 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2951 PIPE_CONTROL_WRITE_TIMESTAMP
|
2952 PIPE_CONTROL_LRI_POST_SYNC_OP
;
2954 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
2955 * "LRI Post Sync Operation". So more than one bit set would be illegal.
2957 assert(util_bitcount(flags
) <= 1);
2962 // XXX: compute support
2963 #define IS_COMPUTE_PIPELINE(batch) (batch->ring != I915_EXEC_RENDER)
2966 * Emit a series of PIPE_CONTROL commands, taking into account any
2967 * workarounds necessary to actually accomplish the caller's request.
2969 * Unless otherwise noted, spec quotations in this function come from:
2971 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
2972 * Restrictions for PIPE_CONTROL.
2975 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
2976 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
2978 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
2979 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
2980 enum pipe_control_flags non_lri_post_sync_flags
=
2981 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
2983 /* Recursive PIPE_CONTROL workarounds --------------------------------
2984 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
2986 * We do these first because we want to look at the original operation,
2987 * rather than any workarounds we set.
2989 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
2990 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
2991 * lists several workarounds:
2993 * "Project: SKL, KBL, BXT
2995 * If the VF Cache Invalidation Enable is set to a 1 in a
2996 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
2997 * sets to 0, with the VF Cache Invalidation Enable set to 0
2998 * needs to be sent prior to the PIPE_CONTROL with VF Cache
2999 * Invalidation Enable set to a 1."
3001 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
3004 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
3005 /* Project: SKL / Argument: LRI Post Sync Operation [23]
3007 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
3008 * programmed prior to programming a PIPECONTROL command with "LRI
3009 * Post Sync Operation" in GPGPU mode of operation (i.e when
3010 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
3012 * The same text exists a few rows below for Post Sync Op.
3014 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
3017 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
3019 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
3020 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
3021 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
3023 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
3027 /* "Flush Types" workarounds ---------------------------------------------
3028 * We do these now because they may add post-sync operations or CS stalls.
3031 if (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
3032 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
3034 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
3035 * 'Write PS Depth Count' or 'Write Timestamp'."
3038 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3039 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3040 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3041 bo
= batch
->screen
->workaround_bo
;
3045 /* #1130 from Gen10 workarounds page:
3047 * "Enable Depth Stall on every Post Sync Op if Render target Cache
3048 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
3049 * board stall if Render target cache flush is enabled."
3051 * Applicable to CNL B0 and C0 steppings only.
3053 * The wording here is unclear, and this workaround doesn't look anything
3054 * like the internal bug report recommendations, but leave it be for now...
3056 if (GEN_GEN
== 10) {
3057 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
3058 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
3059 } else if (flags
& non_lri_post_sync_flags
) {
3060 flags
|= PIPE_CONTROL_DEPTH_STALL
;
3064 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
3065 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
3067 * "This bit must be DISABLED for operations other than writing
3070 * This seems like nonsense. An Ivybridge workaround requires us to
3071 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
3072 * operation. Gen8+ requires us to emit depth stalls and depth cache
3073 * flushes together. So, it's hard to imagine this means anything other
3074 * than "we originally intended this to be used for PS_DEPTH_COUNT".
3076 * We ignore the supposed restriction and do nothing.
3080 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
3081 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
3082 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
3084 * "This bit must be DISABLED for End-of-pipe (Read) fences,
3085 * PS_DEPTH_COUNT or TIMESTAMP queries."
3087 * TODO: Implement end-of-pipe checking.
3089 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
3090 PIPE_CONTROL_WRITE_TIMESTAMP
)));
3093 if (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) {
3094 /* From the PIPE_CONTROL instruction table, bit 1:
3096 * "This bit is ignored if Depth Stall Enable is set.
3097 * Further, the render cache is not flushed even if Write Cache
3098 * Flush Enable bit is set."
3100 * We assert that the caller doesn't do this combination, to try and
3101 * prevent mistakes. It shouldn't hurt the GPU, though.
3103 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
3104 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
3107 /* PIPE_CONTROL page workarounds ------------------------------------- */
3109 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
3110 /* From the PIPE_CONTROL page itself:
3113 * Restriction: Pipe_control with CS-stall bit set must be issued
3114 * before a pipe-control command that has the State Cache
3115 * Invalidate bit set."
3117 flags
|= PIPE_CONTROL_CS_STALL
;
3120 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
3121 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
3124 * SW must always program Post-Sync Operation to "Write Immediate
3125 * Data" when Flush LLC is set."
3127 * For now, we just require the caller to do it.
3129 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
3132 /* "Post-Sync Operation" workarounds -------------------------------- */
3134 /* Project: All / Argument: Global Snapshot Count Reset [19]
3136 * "This bit must not be exercised on any product.
3137 * Requires stall bit ([20] of DW1) set."
3139 * We don't use this, so we just assert that it isn't used. The
3140 * PIPE_CONTROL instruction page indicates that they intended this
3141 * as a debug feature and don't think it is useful in production,
3142 * but it may actually be usable, should we ever want to.
3144 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
3146 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
3147 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
3148 /* Project: All / Arguments:
3150 * - Generic Media State Clear [16]
3151 * - Indirect State Pointers Disable [16]
3153 * "Requires stall bit ([20] of DW1) set."
3155 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
3156 * State Clear) says:
3158 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
3159 * programmed prior to programming a PIPECONTROL command with "Media
3160 * State Clear" set in GPGPU mode of operation"
3162 * This is a subset of the earlier rule, so there's nothing to do.
3164 flags
|= PIPE_CONTROL_CS_STALL
;
3167 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
3168 /* Project: All / Argument: Store Data Index
3170 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
3173 * For now, we just assert that the caller does this. We might want to
3174 * automatically add a write to the workaround BO...
3176 assert(non_lri_post_sync_flags
!= 0);
3179 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
3180 /* Project: All / Argument: Sync GFDT
3182 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
3183 * than '0' or 0x2520[13] must be set."
3185 * For now, we just assert that the caller does this.
3187 assert(non_lri_post_sync_flags
!= 0);
3190 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
3191 /* Project: IVB+ / Argument: TLB inv
3193 * "Requires stall bit ([20] of DW1) set."
3195 * Also, from the PIPE_CONTROL instruction table:
3198 * Post Sync Operation or CS stall must be set to ensure a TLB
3199 * invalidation occurs. Otherwise no cycle will occur to the TLB
3200 * cache to invalidate."
3202 * This is not a subset of the earlier rule, so there's nothing to do.
3204 flags
|= PIPE_CONTROL_CS_STALL
;
3207 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
3208 /* TODO: The big Skylake GT4 post sync op workaround */
3211 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
3213 if (IS_COMPUTE_PIPELINE(batch
)) {
3214 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
3215 /* Project: SKL+ / Argument: Tex Invalidate
3216 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
3218 flags
|= PIPE_CONTROL_CS_STALL
;
3221 if (GEN_GEN
== 8 && (post_sync_flags
||
3222 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
3223 PIPE_CONTROL_DEPTH_STALL
|
3224 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
3225 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
3226 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
3227 /* Project: BDW / Arguments:
3229 * - LRI Post Sync Operation [23]
3230 * - Post Sync Op [15:14]
3232 * - Depth Stall [13]
3233 * - Render Target Cache Flush [12]
3234 * - Depth Cache Flush [0]
3235 * - DC Flush Enable [5]
3237 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
3240 flags
|= PIPE_CONTROL_CS_STALL
;
3242 /* Also, from the PIPE_CONTROL instruction table, bit 20:
3245 * This bit must be always set when PIPE_CONTROL command is
3246 * programmed by GPGPU and MEDIA workloads, except for the cases
3247 * when only Read Only Cache Invalidation bits are set (State
3248 * Cache Invalidation Enable, Instruction cache Invalidation
3249 * Enable, Texture Cache Invalidation Enable, Constant Cache
3250 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
3251 * need not implemented when FF_DOP_CG is disable via "Fixed
3252 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
3254 * It sounds like we could avoid CS stalls in some cases, but we
3255 * don't currently bother. This list isn't exactly the list above,
3261 /* "Stall" workarounds ----------------------------------------------
3262 * These have to come after the earlier ones because we may have added
3263 * some additional CS stalls above.
3266 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
3267 /* Project: PRE-SKL, VLV, CHV
3269 * "[All Stepping][All SKUs]:
3271 * One of the following must also be set:
3273 * - Render Target Cache Flush Enable ([12] of DW1)
3274 * - Depth Cache Flush Enable ([0] of DW1)
3275 * - Stall at Pixel Scoreboard ([1] of DW1)
3276 * - Depth Stall ([13] of DW1)
3277 * - Post-Sync Operation ([13] of DW1)
3278 * - DC Flush Enable ([5] of DW1)"
3280 * If we don't already have one of those bits set, we choose to add
3281 * "Stall at Pixel Scoreboard". Some of the other bits require a
3282 * CS stall as a workaround (see above), which would send us into
3283 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
3284 * appears to be safe, so we choose that.
3286 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
3287 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
3288 PIPE_CONTROL_WRITE_IMMEDIATE
|
3289 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
3290 PIPE_CONTROL_WRITE_TIMESTAMP
|
3291 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
3292 PIPE_CONTROL_DEPTH_STALL
|
3293 PIPE_CONTROL_DATA_CACHE_FLUSH
;
3294 if (!(flags
& wa_bits
))
3295 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
3298 /* Emit --------------------------------------------------------------- */
3300 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
3301 pc
.LRIPostSyncOperation
= NoLRIOperation
;
3302 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
3303 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
3304 pc
.StoreDataIndex
= 0;
3305 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
3306 pc
.GlobalSnapshotCountReset
=
3307 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
3308 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
3309 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
3310 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
3311 pc
.RenderTargetCacheFlushEnable
=
3312 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
3313 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
3314 pc
.StateCacheInvalidationEnable
=
3315 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
3316 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
3317 pc
.ConstantCacheInvalidationEnable
=
3318 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
3319 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
3320 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
3321 pc
.InstructionCacheInvalidateEnable
=
3322 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
3323 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
3324 pc
.IndirectStatePointersDisable
=
3325 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
3326 pc
.TextureCacheInvalidationEnable
=
3327 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
3328 pc
.Address
= ro_bo(bo
, offset
);
3329 pc
.ImmediateData
= imm
;
3334 genX(init_state
)(struct iris_context
*ice
)
3336 struct pipe_context
*ctx
= &ice
->ctx
;
3337 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
3339 ctx
->create_blend_state
= iris_create_blend_state
;
3340 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
3341 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
3342 ctx
->create_sampler_state
= iris_create_sampler_state
;
3343 ctx
->create_sampler_view
= iris_create_sampler_view
;
3344 ctx
->create_surface
= iris_create_surface
;
3345 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
3346 ctx
->create_compute_state
= iris_create_compute_state
;
3347 ctx
->bind_blend_state
= iris_bind_blend_state
;
3348 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
3349 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
3350 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
3351 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
3352 ctx
->bind_compute_state
= iris_bind_compute_state
;
3353 ctx
->delete_blend_state
= iris_delete_state
;
3354 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
3355 ctx
->delete_fs_state
= iris_delete_state
;
3356 ctx
->delete_rasterizer_state
= iris_delete_state
;
3357 ctx
->delete_sampler_state
= iris_delete_state
;
3358 ctx
->delete_vertex_elements_state
= iris_delete_state
;
3359 ctx
->delete_compute_state
= iris_delete_state
;
3360 ctx
->delete_tcs_state
= iris_delete_state
;
3361 ctx
->delete_tes_state
= iris_delete_state
;
3362 ctx
->delete_gs_state
= iris_delete_state
;
3363 ctx
->delete_vs_state
= iris_delete_state
;
3364 ctx
->set_blend_color
= iris_set_blend_color
;
3365 ctx
->set_clip_state
= iris_set_clip_state
;
3366 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
3367 ctx
->set_sampler_views
= iris_set_sampler_views
;
3368 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
3369 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
3370 ctx
->set_sample_mask
= iris_set_sample_mask
;
3371 ctx
->set_scissor_states
= iris_set_scissor_states
;
3372 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
3373 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
3374 ctx
->set_viewport_states
= iris_set_viewport_states
;
3375 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
3376 ctx
->surface_destroy
= iris_surface_destroy
;
3377 ctx
->draw_vbo
= iris_draw_vbo
;
3378 ctx
->launch_grid
= iris_launch_grid
;
3379 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
3380 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
3381 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
3383 ice
->vtbl
.destroy_state
= iris_destroy_state
;
3384 ice
->vtbl
.init_render_context
= iris_init_render_context
;
3385 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
3386 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
3387 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
3388 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
3389 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
3390 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
3391 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
3392 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
3393 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
3395 ice
->state
.dirty
= ~0ull;
3397 ice
->state
.num_viewports
= 1;
3398 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
3400 /* Make a 1x1x1 null surface for unbound textures */
3401 void *null_surf_map
=
3402 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
3403 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
3404 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));