2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "util/u_upload_mgr.h"
43 #include "intel/compiler/brw_compiler.h"
44 #include "intel/common/gen_l3_config.h"
45 #include "intel/common/gen_sample_positions.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_pipe.h"
49 #include "iris_resource.h"
51 #define __gen_address_type struct iris_address
52 #define __gen_user_data struct iris_batch
54 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
57 __gen_combine_address(struct iris_batch
*batch
, void *location
,
58 struct iris_address addr
, uint32_t delta
)
60 uint64_t result
= addr
.offset
+ delta
;
63 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
64 /* Assume this is a general address, not relative to a base. */
65 result
+= addr
.bo
->gtt_offset
;
71 #define __genxml_cmd_length(cmd) cmd ## _length
72 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
73 #define __genxml_cmd_header(cmd) cmd ## _header
74 #define __genxml_cmd_pack(cmd) cmd ## _pack
77 get_command_space(struct iris_batch
*batch
, unsigned bytes
)
79 iris_require_command_space(batch
, bytes
);
80 void *map
= batch
->cmdbuf
.map_next
;
81 batch
->cmdbuf
.map_next
+= bytes
;
85 #define _iris_pack_command(batch, cmd, dst, name) \
86 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
87 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
88 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
92 #define iris_pack_command(cmd, dst, name) \
93 _iris_pack_command(NULL, cmd, dst, name)
95 #define iris_pack_state(cmd, dst, name) \
96 for (struct cmd name = {}, \
97 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
98 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
101 #define iris_emit_cmd(batch, cmd, name) \
102 _iris_pack_command(batch, cmd, get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
104 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
106 uint32_t *dw = get_command_space(batch, 4 * num_dwords); \
107 for (uint32_t i = 0; i < num_dwords; i++) \
108 dw[i] = (dwords0)[i] | (dwords1)[i]; \
109 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
112 #include "genxml/genX_pack.h"
113 #include "genxml/gen_macros.h"
114 #include "genxml/genX_bits.h"
116 #define MOCS_WB (2 << 1)
118 UNUSED
static void pipe_asserts()
120 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
122 /* pipe_logicop happens to match the hardware. */
123 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
124 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
125 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
126 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
127 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
128 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
129 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
130 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
131 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
132 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
133 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
134 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
135 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
136 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
137 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
138 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
140 /* pipe_blend_func happens to match the hardware. */
141 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
142 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
143 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
144 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
145 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
146 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
147 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
148 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
149 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
150 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
151 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
152 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
153 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
161 /* pipe_blend_func happens to match the hardware. */
162 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
163 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
164 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
165 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
166 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
168 /* pipe_stencil_op happens to match the hardware. */
169 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
170 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
171 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
172 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
173 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
174 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
175 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
176 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
178 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
179 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
180 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
185 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
187 static const unsigned map
[] = {
188 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
189 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
190 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
191 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
192 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
193 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
194 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
195 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
196 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
197 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
198 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
199 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
200 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
201 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
202 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
205 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
209 translate_compare_func(enum pipe_compare_func pipe_func
)
211 static const unsigned map
[] = {
212 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
213 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
214 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
215 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
216 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
217 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
218 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
219 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
221 return map
[pipe_func
];
225 translate_shadow_func(enum pipe_compare_func pipe_func
)
227 /* Gallium specifies the result of shadow comparisons as:
229 * 1 if ref <op> texel,
234 * 0 if texel <op> ref,
237 * So we need to flip the operator and also negate.
239 static const unsigned map
[] = {
240 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
241 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
242 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
243 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
244 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
245 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
246 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
247 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
249 return map
[pipe_func
];
253 translate_cull_mode(unsigned pipe_face
)
255 static const unsigned map
[4] = {
256 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
257 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
258 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
259 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
261 return map
[pipe_face
];
265 translate_fill_mode(unsigned pipe_polymode
)
267 static const unsigned map
[4] = {
268 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
269 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
270 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
271 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
273 return map
[pipe_polymode
];
276 static struct iris_address
277 bo_addr(struct iris_bo
*bo
)
279 return (struct iris_address
) { .offset
= bo
->gtt_offset
};
283 static struct iris_address
284 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
286 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
290 * Returns the BO's address relative to the appropriate base address.
292 * All of our base addresses are programmed to the start of a 4GB region,
293 * so simply returning the bottom 32 bits of the BO address will give us
294 * the offset from whatever base address corresponds to that memory region.
297 bo_offset_from_base_address(struct pipe_resource
*res
)
299 struct iris_bo
*bo
= ((struct iris_resource
*) res
)->bo
;
301 /* This only works for buffers in the memory zones corresponding to a
302 * base address - the top, unbounded memory zone doesn't have a base.
304 assert(bo
->gtt_offset
< 3 * (1ull << 32));
305 return bo
->gtt_offset
;
309 stream_state(struct iris_batch
*batch
,
310 struct u_upload_mgr
*uploader
,
313 uint32_t *out_offset
)
315 struct pipe_resource
*res
= NULL
;
318 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, &res
, &ptr
);
320 struct iris_bo
*bo
= ((struct iris_resource
*) res
)->bo
;
321 iris_use_pinned_bo(batch
, bo
, false);
323 *out_offset
+= bo_offset_from_base_address(res
);
325 pipe_resource_reference(&res
, NULL
);
331 emit_state(struct iris_batch
*batch
,
332 struct u_upload_mgr
*uploader
,
338 uint32_t *map
= stream_state(batch
, uploader
, size
, alignment
, &offset
);
341 memcpy(map
, data
, size
);
347 iris_emit_state_base_address(struct iris_batch
*batch
)
349 /* XXX: PIPE_CONTROLs */
351 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
353 // XXX: MOCS is stupid for this.
354 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
355 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
356 sba
.SurfaceStateMemoryObjectControlState
= MOCS_WB
;
357 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
358 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
359 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
360 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
363 sba
.GeneralStateBaseAddressModifyEnable
= true;
364 sba
.SurfaceStateBaseAddressModifyEnable
= true;
365 sba
.DynamicStateBaseAddressModifyEnable
= true;
366 sba
.IndirectObjectBaseAddressModifyEnable
= true;
367 sba
.InstructionBaseAddressModifyEnable
= true;
368 sba
.GeneralStateBufferSizeModifyEnable
= true;
369 sba
.DynamicStateBufferSizeModifyEnable
= true;
370 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
371 sba
.IndirectObjectBufferSizeModifyEnable
= true;
372 sba
.InstructionBuffersizeModifyEnable
= true;
374 sba
.SurfaceStateBaseAddress
= ro_bo(NULL
, 1ull << 32);
375 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, 2 * (1ull << 32));
377 sba
.GeneralStateBufferSize
= 0xfffff;
378 sba
.IndirectObjectBufferSize
= 0xfffff;
379 sba
.InstructionBufferSize
= 0xfffff;
380 sba
.DynamicStateBufferSize
= 0xfffff;
385 iris_init_render_context(struct iris_screen
*screen
,
386 struct iris_batch
*batch
,
387 struct pipe_debug_callback
*dbg
)
389 batch
->emit_state_base_address
= iris_emit_state_base_address
;
390 iris_init_batch(batch
, screen
, dbg
, I915_EXEC_RENDER
);
392 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
393 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
394 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
396 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
397 GEN_SAMPLE_POS_1X(pat
._1xSample
);
398 GEN_SAMPLE_POS_2X(pat
._2xSample
);
399 GEN_SAMPLE_POS_4X(pat
._4xSample
);
400 GEN_SAMPLE_POS_8X(pat
._8xSample
);
401 GEN_SAMPLE_POS_16X(pat
._16xSample
);
403 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
404 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
405 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
406 /* XXX: may need to set an offset for origin-UL framebuffers */
407 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
409 /* Just assign a static partitioning. */
410 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
411 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
412 alloc
._3DCommandSubOpcode
= 18 + i
;
413 alloc
.ConstantBufferOffset
= 6 * i
;
414 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
420 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
425 iris_set_blend_color(struct pipe_context
*ctx
,
426 const struct pipe_blend_color
*state
)
428 struct iris_context
*ice
= (struct iris_context
*) ctx
;
430 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
431 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
434 struct iris_blend_state
{
435 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
436 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
437 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
439 bool alpha_to_coverage
; /* for shader key */
443 iris_create_blend_state(struct pipe_context
*ctx
,
444 const struct pipe_blend_state
*state
)
446 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
447 uint32_t *blend_state
= cso
->blend_state
;
449 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
451 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
452 /* pb.HasWriteableRT is filled in at draw time. */
453 /* pb.AlphaTestEnable is filled in at draw time. */
454 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
455 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
457 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
459 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
460 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
461 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
462 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
465 iris_pack_state(GENX(BLEND_STATE
), blend_state
, bs
) {
466 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
467 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
468 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
469 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
470 bs
.ColorDitherEnable
= state
->dither
;
471 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
474 blend_state
+= GENX(BLEND_STATE_length
);
476 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
477 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_state
, be
) {
478 be
.LogicOpEnable
= state
->logicop_enable
;
479 be
.LogicOpFunction
= state
->logicop_func
;
481 be
.PreBlendSourceOnlyClampEnable
= false;
482 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
483 be
.PreBlendColorClampEnable
= true;
484 be
.PostBlendColorClampEnable
= true;
486 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
488 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
489 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
490 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
491 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
492 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
493 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
495 be
.WriteDisableRed
= !(state
->rt
[i
].colormask
& PIPE_MASK_R
);
496 be
.WriteDisableGreen
= !(state
->rt
[i
].colormask
& PIPE_MASK_G
);
497 be
.WriteDisableBlue
= !(state
->rt
[i
].colormask
& PIPE_MASK_B
);
498 be
.WriteDisableAlpha
= !(state
->rt
[i
].colormask
& PIPE_MASK_A
);
500 blend_state
+= GENX(BLEND_STATE_ENTRY_length
);
507 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
509 struct iris_context
*ice
= (struct iris_context
*) ctx
;
510 ice
->state
.cso_blend
= state
;
511 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
512 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
515 struct iris_depth_stencil_alpha_state
{
516 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
517 uint32_t cc_vp
[GENX(CC_VIEWPORT_length
)];
519 struct pipe_alpha_state alpha
; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
523 iris_create_zsa_state(struct pipe_context
*ctx
,
524 const struct pipe_depth_stencil_alpha_state
*state
)
526 struct iris_depth_stencil_alpha_state
*cso
=
527 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
529 cso
->alpha
= state
->alpha
;
531 bool two_sided_stencil
= state
->stencil
[1].enabled
;
533 /* The state tracker needs to optimize away EQUAL writes for us. */
534 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
536 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
537 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
538 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
539 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
540 wmds
.StencilTestFunction
=
541 translate_compare_func(state
->stencil
[0].func
);
542 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
543 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
544 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
545 wmds
.BackfaceStencilTestFunction
=
546 translate_compare_func(state
->stencil
[1].func
);
547 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
548 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
549 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
550 wmds
.StencilBufferWriteEnable
=
551 state
->stencil
[0].writemask
!= 0 ||
552 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
553 wmds
.DepthTestEnable
= state
->depth
.enabled
;
554 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
555 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
556 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
557 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
558 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
559 /* wmds.[Backface]StencilReferenceValue are merged later */
562 iris_pack_state(GENX(CC_VIEWPORT
), cso
->cc_vp
, ccvp
) {
563 ccvp
.MinimumDepth
= state
->depth
.bounds_min
;
564 ccvp
.MaximumDepth
= state
->depth
.bounds_max
;
571 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
573 struct iris_context
*ice
= (struct iris_context
*) ctx
;
574 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
575 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
578 if (!old_cso
|| old_cso
->alpha
.ref_value
!= new_cso
->alpha
.ref_value
) {
579 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
583 ice
->state
.cso_zsa
= new_cso
;
584 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
585 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
588 struct iris_rasterizer_state
{
589 uint32_t sf
[GENX(3DSTATE_SF_length
)];
590 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
591 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
592 uint32_t wm
[GENX(3DSTATE_WM_length
)];
593 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
595 bool flatshade
; /* for shader state */
596 bool clamp_fragment_color
; /* for shader state */
597 bool light_twoside
; /* for shader state */
598 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
599 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
600 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
601 uint16_t sprite_coord_enable
;
605 iris_create_rasterizer_state(struct pipe_context
*ctx
,
606 const struct pipe_rasterizer_state
*state
)
608 struct iris_rasterizer_state
*cso
=
609 malloc(sizeof(struct iris_rasterizer_state
));
612 point_quad_rasterization
-> SBE
?
617 force_persample_interp
- ?
620 offset_units_unscaled
- cap
not exposed
624 cso
->flatshade
= state
->flatshade
;
625 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
626 cso
->light_twoside
= state
->light_twoside
;
627 cso
->rasterizer_discard
= state
->rasterizer_discard
;
628 cso
->half_pixel_center
= state
->half_pixel_center
;
629 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
630 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
632 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
633 sf
.StatisticsEnable
= true;
634 sf
.ViewportTransformEnable
= true;
635 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
636 sf
.LineEndCapAntialiasingRegionWidth
=
637 state
->line_smooth
? _10pixels
: _05pixels
;
638 sf
.LastPixelEnable
= state
->line_last_pixel
;
639 sf
.LineWidth
= state
->line_width
;
640 sf
.SmoothPointEnable
= state
->point_smooth
;
641 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
642 sf
.PointWidth
= state
->point_size
;
644 if (state
->flatshade_first
) {
645 sf
.TriangleStripListProvokingVertexSelect
= 2;
646 sf
.TriangleFanProvokingVertexSelect
= 2;
647 sf
.LineStripListProvokingVertexSelect
= 1;
649 sf
.TriangleFanProvokingVertexSelect
= 1;
654 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
655 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
656 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
657 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
658 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
659 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
660 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
661 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
662 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
663 rr
.GlobalDepthOffsetConstant
= state
->offset_units
;
664 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
665 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
666 rr
.SmoothPointEnable
= state
->point_smooth
;
667 rr
.AntialiasingEnable
= state
->line_smooth
;
668 rr
.ScissorRectangleEnable
= state
->scissor
;
669 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
670 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
671 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
674 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
675 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
676 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
678 cl
.StatisticsEnable
= true;
679 cl
.EarlyCullEnable
= true;
680 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
681 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
682 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
683 cl
.GuardbandClipTestEnable
= true;
684 cl
.ClipMode
= CLIPMODE_NORMAL
;
685 cl
.ClipEnable
= true;
686 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
687 cl
.MinimumPointWidth
= 0.125;
688 cl
.MaximumPointWidth
= 255.875;
690 if (state
->flatshade_first
) {
691 cl
.TriangleStripListProvokingVertexSelect
= 2;
692 cl
.TriangleFanProvokingVertexSelect
= 2;
693 cl
.LineStripListProvokingVertexSelect
= 1;
695 cl
.TriangleFanProvokingVertexSelect
= 1;
699 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
700 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
701 * filled in at draw time from the FS program.
703 wm
.LineAntialiasingRegionWidth
= _10pixels
;
704 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
705 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
706 wm
.StatisticsEnable
= true;
707 wm
.LineStippleEnable
= state
->line_stipple_enable
;
708 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
711 /* Remap from 0..255 back to 1..256 */
712 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
714 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
715 line
.LineStipplePattern
= state
->line_stipple_pattern
;
716 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
717 line
.LineStippleRepeatCount
= line_stipple_factor
;
724 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
726 struct iris_context
*ice
= (struct iris_context
*) ctx
;
727 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
728 struct iris_rasterizer_state
*new_cso
= state
;
731 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
732 if (!old_cso
|| memcmp(old_cso
->line_stipple
, new_cso
->line_stipple
,
733 sizeof(old_cso
->line_stipple
)) != 0) {
734 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
738 old_cso
->half_pixel_center
!= new_cso
->half_pixel_center
) {
739 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
743 ice
->state
.cso_rast
= new_cso
;
744 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
748 translate_wrap(unsigned pipe_wrap
)
750 static const unsigned map
[] = {
751 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
752 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
753 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
754 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
755 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
756 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
757 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1, // XXX: ???
758 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1, // XXX: ???
760 return map
[pipe_wrap
];
764 * Return true if the given wrap mode requires the border color to exist.
767 wrap_mode_needs_border_color(unsigned wrap_mode
)
769 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
773 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
775 static const unsigned map
[] = {
776 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
777 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
778 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
780 return map
[pipe_mip
];
783 struct iris_sampler_state
{
784 struct pipe_sampler_state base
;
786 bool needs_border_color
;
788 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
792 iris_create_sampler_state(struct pipe_context
*pctx
,
793 const struct pipe_sampler_state
*state
)
795 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
800 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
801 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
803 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
804 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
805 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
807 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
808 wrap_mode_needs_border_color(wrap_t
) ||
809 wrap_mode_needs_border_color(wrap_r
);
811 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
812 samp
.TCXAddressControlMode
= wrap_s
;
813 samp
.TCYAddressControlMode
= wrap_t
;
814 samp
.TCZAddressControlMode
= wrap_r
;
815 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
816 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
817 samp
.MinModeFilter
= state
->min_img_filter
;
818 samp
.MagModeFilter
= state
->mag_img_filter
;
819 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
820 samp
.MaximumAnisotropy
= RATIO21
;
822 if (state
->max_anisotropy
>= 2) {
823 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
824 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
825 samp
.AnisotropicAlgorithm
= EWAApproximation
;
828 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
829 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
831 samp
.MaximumAnisotropy
=
832 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
835 /* Set address rounding bits if not using nearest filtering. */
836 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
837 samp
.UAddressMinFilterRoundingEnable
= true;
838 samp
.VAddressMinFilterRoundingEnable
= true;
839 samp
.RAddressMinFilterRoundingEnable
= true;
842 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
843 samp
.UAddressMagFilterRoundingEnable
= true;
844 samp
.VAddressMagFilterRoundingEnable
= true;
845 samp
.RAddressMagFilterRoundingEnable
= true;
848 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
849 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
851 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
853 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
854 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
855 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
856 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
858 //samp.BorderColorPointer = <<comes from elsewhere>>
865 iris_bind_sampler_states(struct pipe_context
*ctx
,
866 enum pipe_shader_type p_stage
,
867 unsigned start
, unsigned count
,
870 struct iris_context
*ice
= (struct iris_context
*) ctx
;
871 gl_shader_stage stage
= stage_from_pipe(p_stage
);
873 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
875 /* Assemble the SAMPLER_STATEs into a contiguous chunk of memory
876 * relative to Dynamic State Base Address.
879 u_upload_alloc(ice
->state
.dynamic_uploader
, 0,
880 count
* 4 * GENX(SAMPLER_STATE_length
), 32,
881 &ice
->state
.sampler_table_offset
[stage
],
882 &ice
->state
.sampler_table_resource
[stage
],
887 ice
->state
.sampler_table_offset
[stage
] +=
888 bo_offset_from_base_address(ice
->state
.sampler_table_resource
[stage
]);
890 for (int i
= 0; i
< count
; i
++) {
891 struct iris_sampler_state
*state
= states
[i
];
893 /* Save a pointer to the iris_sampler_state, a few fields need
894 * to inform draw-time decisions.
896 ice
->state
.samplers
[stage
][start
+ i
] = state
;
899 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
901 map
+= GENX(SAMPLER_STATE_length
);
904 ice
->state
.num_samplers
= count
;
906 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
909 struct iris_sampler_view
{
910 struct pipe_sampler_view pipe
;
911 struct isl_view view
;
913 /** The resource (BO) holding our SURFACE_STATE. */
914 struct pipe_resource
*surface_state_resource
;
915 unsigned surface_state_offset
;
917 //uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
921 * Convert an swizzle enumeration (i.e. PIPE_SWIZZLE_X) to one of the Gen7.5+
922 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
924 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
927 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
929 * which is simply adding 4 then modding by 8 (or anding with 7).
931 * We then may need to apply workarounds for textureGather hardware bugs.
933 static enum isl_channel_select
934 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
936 return (swizzle
+ 4) & 7;
939 static struct pipe_sampler_view
*
940 iris_create_sampler_view(struct pipe_context
*ctx
,
941 struct pipe_resource
*tex
,
942 const struct pipe_sampler_view
*tmpl
)
944 struct iris_context
*ice
= (struct iris_context
*) ctx
;
945 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
946 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
947 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
952 /* initialize base object */
954 isv
->pipe
.context
= ctx
;
955 isv
->pipe
.texture
= NULL
;
956 pipe_reference_init(&isv
->pipe
.reference
, 1);
957 pipe_resource_reference(&isv
->pipe
.texture
, tex
);
959 /* XXX: do we need brw_get_texture_swizzle hacks here? */
961 isv
->view
= (struct isl_view
) {
962 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
963 .base_level
= tmpl
->u
.tex
.first_level
,
964 .levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1,
965 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
966 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
967 .swizzle
= (struct isl_swizzle
) {
968 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
969 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
970 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
971 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
973 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
977 u_upload_alloc(ice
->state
.surface_uploader
, 0,
978 4 * GENX(RENDER_SURFACE_STATE_length
), 64,
979 &isv
->surface_state_offset
,
980 &isv
->surface_state_resource
,
985 isv
->surface_state_offset
+=
986 bo_offset_from_base_address(isv
->surface_state_resource
);
988 isl_surf_fill_state(&screen
->isl_dev
, map
,
989 .surf
= &itex
->surf
, .view
= &isv
->view
,
991 .address
= itex
->bo
->gtt_offset
);
993 // .clear_color = clear_color,
998 struct iris_surface
{
999 struct pipe_surface pipe
;
1000 struct isl_view view
;
1002 /** The resource (BO) holding our SURFACE_STATE. */
1003 struct pipe_resource
*surface_state_resource
;
1004 unsigned surface_state_offset
;
1006 // uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
1009 static struct pipe_surface
*
1010 iris_create_surface(struct pipe_context
*ctx
,
1011 struct pipe_resource
*tex
,
1012 const struct pipe_surface
*tmpl
)
1014 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1015 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1016 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1017 struct pipe_surface
*psurf
= &surf
->pipe
;
1018 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
1023 pipe_reference_init(&psurf
->reference
, 1);
1024 pipe_resource_reference(&psurf
->texture
, tex
);
1025 psurf
->context
= ctx
;
1026 psurf
->format
= tmpl
->format
;
1027 psurf
->width
= tex
->width0
;
1028 psurf
->height
= tex
->height0
;
1029 psurf
->texture
= tex
;
1030 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1031 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1032 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1034 surf
->view
= (struct isl_view
) {
1035 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
1036 .base_level
= tmpl
->u
.tex
.level
,
1038 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1039 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1040 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1041 // XXX: DEPTH_BIt, STENCIL_BIT...CUBE_BIT? Other bits?!
1042 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1046 u_upload_alloc(ice
->state
.surface_uploader
, 0,
1047 4 * GENX(RENDER_SURFACE_STATE_length
), 64,
1048 &surf
->surface_state_offset
,
1049 &surf
->surface_state_resource
,
1054 surf
->surface_state_offset
+=
1055 bo_offset_from_base_address(surf
->surface_state_resource
);
1057 isl_surf_fill_state(&screen
->isl_dev
, map
,
1058 .surf
= &itex
->surf
, .view
= &surf
->view
,
1060 .address
= itex
->bo
->gtt_offset
);
1062 // .clear_color = clear_color,
1068 iris_set_sampler_views(struct pipe_context
*ctx
,
1069 enum pipe_shader_type shader
,
1070 unsigned start
, unsigned count
,
1071 struct pipe_sampler_view
**views
)
1076 iris_set_clip_state(struct pipe_context
*ctx
,
1077 const struct pipe_clip_state
*state
)
1082 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1083 const struct pipe_poly_stipple
*state
)
1085 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1086 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1087 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1091 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1093 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1095 ice
->state
.sample_mask
= sample_mask
;
1096 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1100 iris_set_scissor_states(struct pipe_context
*ctx
,
1101 unsigned start_slot
,
1102 unsigned num_scissors
,
1103 const struct pipe_scissor_state
*states
)
1105 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1107 ice
->state
.num_scissors
= num_scissors
;
1109 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1110 ice
->state
.scissors
[start_slot
+ i
] = states
[i
];
1113 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1117 iris_set_stencil_ref(struct pipe_context
*ctx
,
1118 const struct pipe_stencil_ref
*state
)
1120 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1121 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1122 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1126 struct iris_viewport_state
{
1127 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
) * IRIS_MAX_VIEWPORTS
];
1131 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1133 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1138 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1139 float m00
, float m11
, float m30
, float m31
,
1140 float *xmin
, float *xmax
,
1141 float *ymin
, float *ymax
)
1143 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1144 * Strips and Fans documentation:
1146 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1147 * fixed-point "guardband" range supported by the rasterization hardware"
1151 * "In almost all circumstances, if an object’s vertices are actually
1152 * modified by this clamping (i.e., had X or Y coordinates outside of
1153 * the guardband extent the rendered object will not match the intended
1154 * result. Therefore software should take steps to ensure that this does
1155 * not happen - e.g., by clipping objects such that they do not exceed
1156 * these limits after the Drawing Rectangle is applied."
1158 * I believe the fundamental restriction is that the rasterizer (in
1159 * the SF/WM stages) have a limit on the number of pixels that can be
1160 * rasterized. We need to ensure any coordinates beyond the rasterizer
1161 * limit are handled by the clipper. So effectively that limit becomes
1162 * the clipper's guardband size.
1164 * It goes on to say:
1166 * "In addition, in order to be correctly rendered, objects must have a
1167 * screenspace bounding box not exceeding 8K in the X or Y direction.
1168 * This additional restriction must also be comprehended by software,
1169 * i.e., enforced by use of clipping."
1171 * This makes no sense. Gen7+ hardware supports 16K render targets,
1172 * and you definitely need to be able to draw polygons that fill the
1173 * surface. Our assumption is that the rasterizer was limited to 8K
1174 * on Sandybridge, which only supports 8K surfaces, and it was actually
1175 * increased to 16K on Ivybridge and later.
1177 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1179 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1181 if (m00
!= 0 && m11
!= 0) {
1182 /* First, we compute the screen-space render area */
1183 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1184 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1185 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1186 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1188 /* We want the guardband to be centered on that */
1189 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1190 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1191 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1192 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1194 /* Now we need it in native device coordinates */
1195 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1196 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1197 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1198 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1200 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1201 * flipped upside-down. X should be fine though.
1203 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1204 *xmin
= ndc_gb_xmin
;
1205 *xmax
= ndc_gb_xmax
;
1206 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1207 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1209 /* The viewport scales to 0, so nothing will be rendered. */
1219 iris_set_viewport_states(struct pipe_context
*ctx
,
1220 unsigned start_slot
,
1221 unsigned num_viewports
,
1222 const struct pipe_viewport_state
*state
)
1224 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1225 struct iris_viewport_state
*cso
=
1226 malloc(sizeof(struct iris_viewport_state
));
1227 uint32_t *vp_map
= &cso
->sf_cl_vp
[start_slot
];
1229 // XXX: sf_cl_vp is only big enough for one slot, we don't iterate right
1230 for (unsigned i
= 0; i
< num_viewports
; i
++) {
1231 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
1232 vp
.ViewportMatrixElementm00
= state
[i
].scale
[0];
1233 vp
.ViewportMatrixElementm11
= state
[i
].scale
[1];
1234 vp
.ViewportMatrixElementm22
= state
[i
].scale
[2];
1235 vp
.ViewportMatrixElementm30
= state
[i
].translate
[0];
1236 vp
.ViewportMatrixElementm31
= state
[i
].translate
[1];
1237 vp
.ViewportMatrixElementm32
= state
[i
].translate
[2];
1238 /* XXX: in i965 this is computed based on the drawbuffer size,
1239 * but we don't have that here...
1241 vp
.XMinClipGuardband
= -1.0;
1242 vp
.XMaxClipGuardband
= 1.0;
1243 vp
.YMinClipGuardband
= -1.0;
1244 vp
.YMaxClipGuardband
= 1.0;
1245 vp
.XMinViewPort
= viewport_extent(&state
[i
], 0, -1.0f
);
1246 vp
.XMaxViewPort
= viewport_extent(&state
[i
], 0, 1.0f
) - 1;
1247 vp
.YMinViewPort
= viewport_extent(&state
[i
], 1, -1.0f
);
1248 vp
.YMaxViewPort
= viewport_extent(&state
[i
], 1, 1.0f
) - 1;
1251 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
1254 ice
->state
.cso_vp
= cso
;
1255 ice
->state
.num_viewports
= num_viewports
;
1256 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1259 struct iris_depth_state
1261 uint32_t depth_buffer
[GENX(3DSTATE_DEPTH_BUFFER_length
)];
1262 uint32_t hier_depth_buffer
[GENX(3DSTATE_HIER_DEPTH_BUFFER_length
)];
1263 uint32_t stencil_buffer
[GENX(3DSTATE_STENCIL_BUFFER_length
)];
1267 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1268 const struct pipe_framebuffer_state
*state
)
1270 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1271 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1273 if (cso
->samples
!= state
->samples
) {
1274 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1277 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
1278 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1281 cso
->width
= state
->width
;
1282 cso
->height
= state
->height
;
1283 cso
->layers
= state
->layers
;
1284 cso
->samples
= state
->samples
;
1287 for (i
= 0; i
< state
->nr_cbufs
; i
++)
1288 pipe_surface_reference(&cso
->cbufs
[i
], state
->cbufs
[i
]);
1289 for (; i
< cso
->nr_cbufs
; i
++)
1290 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
1292 cso
->nr_cbufs
= state
->nr_cbufs
;
1294 pipe_surface_reference(&cso
->zsbuf
, state
->zsbuf
);
1296 struct isl_depth_stencil_hiz_emit_info info
= {
1300 // XXX: depth buffers
1304 iris_set_constant_buffer(struct pipe_context
*ctx
,
1305 enum pipe_shader_type p_stage
, unsigned index
,
1306 const struct pipe_constant_buffer
*cb
)
1308 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1309 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1311 util_copy_constant_buffer(&ice
->shaders
.state
[stage
].constbuf
[index
], cb
);
1315 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1316 struct pipe_sampler_view
*state
)
1318 pipe_resource_reference(&state
->texture
, NULL
);
1324 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1326 struct iris_surface
*surf
= (void *) p_surf
;
1327 pipe_resource_reference(&p_surf
->texture
, NULL
);
1328 pipe_resource_reference(&surf
->surface_state_resource
, NULL
);
1333 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1338 struct iris_vertex_buffer_state
{
1339 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
1340 struct iris_bo
*bos
[33];
1341 unsigned num_buffers
;
1345 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
1348 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
1349 iris_bo_unreference(cso
->bos
[i
]);
1355 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1356 unsigned start_slot
, unsigned count
,
1357 const struct pipe_vertex_buffer
*buffers
)
1359 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1360 struct iris_vertex_buffer_state
*cso
=
1361 malloc(sizeof(struct iris_vertex_buffer_state
));
1363 /* If there are no buffers, do nothing. We can leave the stale
1364 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1365 * elements that point to them, it should be fine.
1370 iris_free_vertex_buffers(ice
->state
.cso_vertex_buffers
);
1372 cso
->num_buffers
= count
;
1374 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1375 vb
.DWordLength
= 4 * cso
->num_buffers
- 1;
1378 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1380 for (unsigned i
= 0; i
< count
; i
++) {
1381 assert(!buffers
[i
].is_user_buffer
);
1383 struct iris_resource
*res
= (void *) buffers
[i
].buffer
.resource
;
1384 iris_bo_reference(res
->bo
);
1385 cso
->bos
[i
] = res
->bo
;
1387 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1388 vb
.VertexBufferIndex
= start_slot
+ i
;
1390 vb
.AddressModifyEnable
= true;
1391 vb
.BufferPitch
= buffers
[i
].stride
;
1392 vb
.BufferSize
= res
->bo
->size
;
1393 vb
.BufferStartingAddress
=
1394 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffers
[i
].buffer_offset
);
1397 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1400 ice
->state
.cso_vertex_buffers
= cso
;
1401 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1404 struct iris_vertex_element_state
{
1405 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1406 uint32_t vf_instancing
[GENX(3DSTATE_VF_INSTANCING_length
)][33];
1411 iris_create_vertex_elements(struct pipe_context
*ctx
,
1413 const struct pipe_vertex_element
*state
)
1415 struct iris_vertex_element_state
*cso
=
1416 malloc(sizeof(struct iris_vertex_element_state
));
1421 * - create edge flag one
1423 * - if those are necessary, use count + 1/2/3... OR in the length
1425 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
);
1427 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1429 for (int i
= 0; i
< count
; i
++) {
1430 enum isl_format isl_format
=
1431 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1432 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
1433 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
1435 switch (isl_format_get_num_channels(isl_format
)) {
1436 case 0: comp
[0] = VFCOMP_STORE_0
;
1437 case 1: comp
[1] = VFCOMP_STORE_0
;
1438 case 2: comp
[2] = VFCOMP_STORE_0
;
1440 comp
[3] = isl_format_has_int_channel(isl_format
) ? VFCOMP_STORE_1_INT
1441 : VFCOMP_STORE_1_FP
;
1444 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1445 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1447 ve
.SourceElementOffset
= state
[i
].src_offset
;
1448 ve
.SourceElementFormat
= isl_format
;
1449 ve
.Component0Control
= comp
[0];
1450 ve
.Component1Control
= comp
[1];
1451 ve
.Component2Control
= comp
[2];
1452 ve
.Component3Control
= comp
[3];
1455 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->vf_instancing
[i
], vi
) {
1456 vi
.VertexElementIndex
= i
;
1457 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1458 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1461 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1468 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
1470 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1472 ice
->state
.cso_vertex_elements
= state
;
1473 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
1477 iris_create_compute_state(struct pipe_context
*ctx
,
1478 const struct pipe_compute_state
*state
)
1483 static struct pipe_stream_output_target
*
1484 iris_create_stream_output_target(struct pipe_context
*ctx
,
1485 struct pipe_resource
*res
,
1486 unsigned buffer_offset
,
1487 unsigned buffer_size
)
1489 struct pipe_stream_output_target
*t
=
1490 CALLOC_STRUCT(pipe_stream_output_target
);
1494 pipe_reference_init(&t
->reference
, 1);
1495 pipe_resource_reference(&t
->buffer
, res
);
1496 t
->buffer_offset
= buffer_offset
;
1497 t
->buffer_size
= buffer_size
;
1502 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
1503 struct pipe_stream_output_target
*t
)
1505 pipe_resource_reference(&t
->buffer
, NULL
);
1510 iris_set_stream_output_targets(struct pipe_context
*ctx
,
1511 unsigned num_targets
,
1512 struct pipe_stream_output_target
**targets
,
1513 const unsigned *offsets
)
1519 iris_compute_sbe(const struct iris_context
*ice
,
1520 const struct brw_wm_prog_data
*wm_prog_data
)
1522 uint32_t sbe_map
[GENX(3DSTATE_SBE_length
)];
1523 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
1525 unsigned urb_read_offset
, urb_read_length
;
1526 brw_compute_sbe_urb_slot_interval(fp
->info
.inputs_read
,
1527 ice
->shaders
.last_vue_map
,
1528 &urb_read_offset
, &urb_read_length
);
1530 iris_pack_command(GENX(3DSTATE_SBE
), sbe_map
, sbe
) {
1531 sbe
.AttributeSwizzleEnable
= true;
1532 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1533 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
1534 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
1535 sbe
.VertexURBEntryReadLength
= urb_read_length
;
1536 sbe
.ForceVertexURBEntryReadOffset
= true;
1537 sbe
.ForceVertexURBEntryReadLength
= true;
1538 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1540 for (int i
= 0; i
< urb_read_length
* 2; i
++) {
1541 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
1548 iris_bind_compute_state(struct pipe_context
*ctx
, void *state
)
1553 iris_populate_vs_key(const struct iris_context
*ice
,
1554 struct brw_vs_prog_key
*key
)
1556 memset(key
, 0, sizeof(*key
));
1560 iris_populate_tcs_key(const struct iris_context
*ice
,
1561 struct brw_tcs_prog_key
*key
)
1563 memset(key
, 0, sizeof(*key
));
1567 iris_populate_tes_key(const struct iris_context
*ice
,
1568 struct brw_tes_prog_key
*key
)
1570 memset(key
, 0, sizeof(*key
));
1574 iris_populate_gs_key(const struct iris_context
*ice
,
1575 struct brw_gs_prog_key
*key
)
1577 memset(key
, 0, sizeof(*key
));
1581 iris_populate_fs_key(const struct iris_context
*ice
,
1582 struct brw_wm_prog_key
*key
)
1584 memset(key
, 0, sizeof(*key
));
1586 /* XXX: dirty flags? */
1587 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
1588 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
1589 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
1590 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
1592 key
->nr_color_regions
= fb
->nr_cbufs
;
1594 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
1596 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
1597 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
1599 // key->force_dual_color_blend for unigine
1601 if (cso_rast
->multisample
) {
1602 key
->persample_interp
=
1603 ctx
->Multisample
.SampleShading
&&
1604 (ctx
->Multisample
.MinSampleShadingValue
*
1605 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1);
1607 key
->multisample_fbo
= fb
->samples
> 1;
1611 key
->coherent_fb_fetch
= true;
1614 //pkt.SamplerCount = \
1615 //DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1616 //pkt.PerThreadScratchSpace = prog_data->total_scratch == 0 ? 0 : \
1617 //ffs(stage_state->per_thread_scratch) - 11; \
1620 KSP(const struct iris_compiled_shader
*shader
)
1622 struct iris_resource
*res
= (void *) shader
->buffer
;
1623 return res
->bo
->gtt_offset
+ shader
->offset
;
1626 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1627 pkt.KernelStartPointer = KSP(shader); \
1628 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
1629 pkt.FloatingPointMode = prog_data->use_alt_mode; \
1631 pkt.DispatchGRFStartRegisterForURBData = \
1632 prog_data->dispatch_grf_start_reg; \
1633 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1634 pkt.prefix##URBEntryReadOffset = 0; \
1636 pkt.StatisticsEnable = true; \
1640 iris_set_vs_state(const struct gen_device_info
*devinfo
,
1641 struct iris_compiled_shader
*shader
)
1643 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1644 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1646 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
1647 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1648 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1649 vs
.SIMD8DispatchEnable
= true;
1650 vs
.UserClipDistanceCullTestEnableBitmask
=
1651 vue_prog_data
->cull_distance_mask
;
1656 iris_set_tcs_state(const struct gen_device_info
*devinfo
,
1657 struct iris_compiled_shader
*shader
)
1659 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1660 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1661 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
1663 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
1664 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
1666 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
1667 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
1668 hs
.IncludeVertexHandles
= true;
1673 iris_set_tes_state(const struct gen_device_info
*devinfo
,
1674 struct iris_compiled_shader
*shader
)
1676 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1677 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1678 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
1680 uint32_t *te_state
= (void *) shader
->derived_data
;
1681 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
1683 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
1684 te
.Partitioning
= tes_prog_data
->partitioning
;
1685 te
.OutputTopology
= tes_prog_data
->output_topology
;
1686 te
.TEDomain
= tes_prog_data
->domain
;
1688 te
.MaximumTessellationFactorOdd
= 63.0;
1689 te
.MaximumTessellationFactorNotOdd
= 64.0;
1692 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
1693 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
1695 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
1696 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
1697 ds
.ComputeWCoordinateEnable
=
1698 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
1700 ds
.UserClipDistanceCullTestEnableBitmask
=
1701 vue_prog_data
->cull_distance_mask
;
1707 iris_set_gs_state(const struct gen_device_info
*devinfo
,
1708 struct iris_compiled_shader
*shader
)
1710 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1711 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1712 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
1714 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
1715 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
1717 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
1718 gs
.OutputTopology
= gs_prog_data
->output_topology
;
1719 gs
.ControlDataHeaderSize
=
1720 gs_prog_data
->control_data_header_size_hwords
;
1721 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
1722 gs
.DispatchMode
= SIMD8
;
1723 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
1724 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
1725 gs
.ReorderMode
= TRAILING
;
1726 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
1727 gs
.MaximumNumberofThreads
=
1728 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
1729 : (devinfo
->max_gs_threads
- 1);
1731 if (gs_prog_data
->static_vertex_count
!= -1) {
1732 gs
.StaticOutput
= true;
1733 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
1735 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
1737 gs
.UserClipDistanceCullTestEnableBitmask
=
1738 vue_prog_data
->cull_distance_mask
;
1740 const int urb_entry_write_offset
= 1;
1741 const uint32_t urb_entry_output_length
=
1742 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
1743 urb_entry_write_offset
;
1745 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
1746 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
1751 iris_set_fs_state(const struct gen_device_info
*devinfo
,
1752 struct iris_compiled_shader
*shader
)
1754 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1755 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
1757 uint32_t *ps_state
= (void *) shader
->derived_data
;
1758 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
1760 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
1761 ps
.VectorMaskEnable
= true;
1762 //ps.SamplerCount = ...
1763 ps
.BindingTableEntryCount
= prog_data
->binding_table
.size_bytes
/ 4;
1764 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
1765 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
1767 ps
.PushConstantEnable
= prog_data
->nr_params
> 0 ||
1768 prog_data
->ubo_ranges
[0].length
> 0;
1770 /* From the documentation for this packet:
1771 * "If the PS kernel does not need the Position XY Offsets to
1772 * compute a Position Value, then this field should be programmed
1773 * to POSOFFSET_NONE."
1775 * "SW Recommendation: If the PS kernel needs the Position Offsets
1776 * to compute a Position XY value, this field should match Position
1777 * ZW Interpolation Mode to ensure a consistent position.xyzw
1780 * We only require XY sample offsets. So, this recommendation doesn't
1781 * look useful at the moment. We might need this in future.
1783 ps
.PositionXYOffsetSelect
=
1784 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
1785 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1786 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1787 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
1789 // XXX: Disable SIMD32 with 16x MSAA
1791 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
1792 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
1793 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
1794 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
1795 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
1796 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
1798 ps
.KernelStartPointer0
=
1799 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
1800 ps
.KernelStartPointer1
=
1801 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
1802 ps
.KernelStartPointer2
=
1803 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
1806 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
1807 psx
.PixelShaderValid
= true;
1808 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1809 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
1810 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
1811 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1812 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1813 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
1815 if (wm_prog_data
->uses_sample_mask
) {
1816 /* TODO: conservative rasterization */
1817 if (wm_prog_data
->post_depth_coverage
)
1818 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
1820 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
1823 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1824 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
1825 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
1832 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
1834 assert(cache_id
<= IRIS_CACHE_CS
);
1836 static const unsigned dwords
[] = {
1837 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
1838 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
1839 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
1840 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
1842 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
1843 [IRIS_CACHE_CS
] = 0,
1844 [IRIS_CACHE_BLORP_BLIT
] = 0,
1847 return sizeof(uint32_t) * dwords
[cache_id
];
1851 iris_set_derived_program_state(const struct gen_device_info
*devinfo
,
1852 enum iris_program_cache_id cache_id
,
1853 struct iris_compiled_shader
*shader
)
1857 iris_set_vs_state(devinfo
, shader
);
1859 case IRIS_CACHE_TCS
:
1860 iris_set_tcs_state(devinfo
, shader
);
1862 case IRIS_CACHE_TES
:
1863 iris_set_tes_state(devinfo
, shader
);
1866 iris_set_gs_state(devinfo
, shader
);
1869 iris_set_fs_state(devinfo
, shader
);
1879 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
1881 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
1882 const unsigned push_size_kB
= 32;
1883 unsigned entries
[4];
1887 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1888 if (!ice
->shaders
.prog
[i
]) {
1891 struct brw_vue_prog_data
*vue_prog_data
=
1892 (void *) ice
->shaders
.prog
[i
]->prog_data
;
1893 size
[i
] = vue_prog_data
->urb_entry_size
;
1895 assert(size
[i
] != 0);
1898 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
1899 1024 * ice
->shaders
.urb_size
,
1900 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
1901 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
1902 size
, entries
, start
);
1904 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1905 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
1906 urb
._3DCommandSubOpcode
+= i
;
1907 urb
.VSURBStartingAddress
= start
[i
];
1908 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
1909 urb
.VSNumberofURBEntries
= entries
[i
];
1914 static const uint32_t push_constant_opcodes
[] = {
1915 [MESA_SHADER_VERTEX
] = 21,
1916 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1917 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1918 [MESA_SHADER_GEOMETRY
] = 22,
1919 [MESA_SHADER_FRAGMENT
] = 23,
1920 [MESA_SHADER_COMPUTE
] = 0,
1924 * Add a surface to the validation list, as well as the buffer containing
1925 * the corresponding SURFACE_STATE.
1927 * Returns the binding table entry (offset to SURFACE_STATE).
1930 use_surface(struct iris_batch
*batch
,
1931 struct pipe_surface
*p_surf
,
1934 struct iris_surface
*surf
= (void *) p_surf
;
1935 struct iris_resource
*res
= (void *) surf
->pipe
.texture
;
1936 struct iris_resource
*state_res
= (void *) surf
->surface_state_resource
;
1937 iris_use_pinned_bo(batch
, res
->bo
, writeable
);
1938 iris_use_pinned_bo(batch
, state_res
->bo
, false);
1940 return surf
->surface_state_offset
;
1944 iris_upload_render_state(struct iris_context
*ice
,
1945 struct iris_batch
*batch
,
1946 const struct pipe_draw_info
*draw
)
1948 const uint64_t dirty
= ice
->state
.dirty
;
1950 struct brw_wm_prog_data
*wm_prog_data
= (void *)
1951 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
1953 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
1954 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1955 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
1956 ptr
.CCViewportPointer
=
1957 emit_state(batch
, ice
->state
.dynamic_uploader
,
1958 cso
->cc_vp
, sizeof(cso
->cc_vp
), 32);
1962 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
1963 struct iris_viewport_state
*cso
= ice
->state
.cso_vp
;
1964 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
1965 ptr
.SFClipViewportPointer
=
1966 emit_state(batch
, ice
->state
.dynamic_uploader
, cso
->sf_cl_vp
,
1967 4 * GENX(SF_CLIP_VIEWPORT_length
) *
1968 ice
->state
.num_viewports
, 64);
1974 if (dirty
& IRIS_DIRTY_URB
) {
1975 iris_upload_urb_config(ice
, batch
);
1978 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
1979 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
1980 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
1981 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
1982 const int num_dwords
= 4 * (GENX(BLEND_STATE_length
) +
1983 cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
));
1984 uint32_t blend_offset
;
1985 uint32_t *blend_map
=
1986 stream_state(batch
, ice
->state
.dynamic_uploader
, 4 * num_dwords
, 64,
1989 uint32_t blend_state_header
;
1990 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
1991 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
1992 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
1995 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
1996 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1],
1997 sizeof(cso_blend
->blend_state
) - sizeof(uint32_t));
1999 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2000 ptr
.BlendStatePointer
= blend_offset
;
2001 ptr
.BlendStatePointerValid
= true;
2005 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
2006 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2009 stream_state(batch
, ice
->state
.dynamic_uploader
,
2010 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
2012 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
2013 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
2014 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
2015 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
2016 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
2017 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
2018 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
2020 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2021 ptr
.ColorCalcStatePointer
= cc_offset
;
2022 ptr
.ColorCalcStatePointerValid
= true;
2026 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2027 // XXX: wrong dirty tracking...
2028 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
2031 struct pipe_constant_buffer
*cbuf0
=
2032 &ice
->shaders
.state
[stage
].constbuf
[0];
2034 if (!ice
->shaders
.prog
[stage
] || cbuf0
->buffer
|| !cbuf0
->buffer_size
)
2037 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2038 shs
->const_size
= cbuf0
->buffer_size
;
2039 u_upload_data(ice
->ctx
.const_uploader
, 0, shs
->const_size
, 32,
2040 cbuf0
->user_buffer
, &shs
->const_offset
,
2041 &shs
->push_resource
);
2044 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2045 // XXX: wrong dirty tracking...
2046 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
2049 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2050 struct iris_resource
*res
= (void *) shs
->push_resource
;
2052 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2053 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2055 pkt
.ConstantBody
.ReadLength
[3] = shs
->const_size
;
2056 pkt
.ConstantBody
.Buffer
[3] = ro_bo(res
->bo
, shs
->const_offset
);
2063 // - ubos/ssbos/abos
2066 // - render targets - write and read
2067 // XXX: 3DSTATE_BINDING_TABLE_POINTERS_XS
2069 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2070 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2071 if (!shader
) // XXX: dirty bits...also, emit a disable maybe?
2074 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
2075 uint32_t bt_offset
= 0;
2076 uint32_t *bt_map
= NULL
;
2078 if (prog_data
->binding_table
.size_bytes
!= 0) {
2079 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
2080 bt_map
= iris_binder_reserve(&ice
->state
.binder
,
2081 prog_data
->binding_table
.size_bytes
,
2085 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
2086 ptr
._3DCommandSubOpcode
= 38 + stage
;
2087 ptr
.PointertoVSBindingTable
= bt_offset
;
2090 if (stage
== MESA_SHADER_FRAGMENT
) {
2091 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2092 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
2093 *bt_map
++ = use_surface(batch
, cso_fb
->cbufs
[i
], true);
2098 for (int i
= 0; i
< ice
->state
.num_samplers
; i
++) {
2099 struct iris_sampler_view
*view
= SOMEWHERE
;
2100 struct iris_resource
*res
= (void *) view
->pipe
.texture
;
2101 *bt_map
++ = use_surface(batch
, isv
, true);
2104 // XXX: not implemented yet
2105 assert(prog_data
->binding_table
.pull_constants_start
== 0xd0d0d0d0);
2106 assert(prog_data
->binding_table
.ubo_start
== 0xd0d0d0d0);
2107 assert(prog_data
->binding_table
.ssbo_start
== 0xd0d0d0d0);
2108 assert(prog_data
->binding_table
.image_start
== 0xd0d0d0d0);
2109 assert(prog_data
->binding_table
.shader_time_start
== 0xd0d0d0d0);
2110 //assert(prog_data->binding_table.plane_start[1] == 0xd0d0d0d0);
2111 //assert(prog_data->binding_table.plane_start[2] == 0xd0d0d0d0);
2115 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2116 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
2117 !ice
->shaders
.prog
[stage
])
2120 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
2121 ptr
._3DCommandSubOpcode
= 43 + stage
;
2122 ptr
.PointertoVSSamplerState
= ice
->state
.sampler_table_offset
[stage
];
2126 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
2127 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
2129 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
2130 if (ice
->state
.framebuffer
.samples
> 0)
2131 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
2135 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
2136 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
2137 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
2141 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2142 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
2145 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2148 struct iris_resource
*cache
= (void *) shader
->buffer
;
2149 iris_use_pinned_bo(batch
, cache
->bo
, false);
2150 iris_batch_emit(batch
, shader
->derived_data
,
2151 iris_derived_program_state_size(stage
));
2153 if (stage
== MESA_SHADER_TESS_EVAL
) {
2154 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
2155 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
2156 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
2157 } else if (stage
== MESA_SHADER_GEOMETRY
) {
2158 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
2164 // 3DSTATE_STREAMOUT
2165 // 3DSTATE_SO_BUFFER
2166 // 3DSTATE_SO_DECL_LIST
2168 if (dirty
& IRIS_DIRTY_CLIP
) {
2169 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2170 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2172 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
2173 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
2174 if (wm_prog_data
->barycentric_interp_modes
&
2175 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
2176 cl
.NonPerspectiveBarycentricEnable
= true;
2178 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
2180 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
2181 ARRAY_SIZE(cso_rast
->clip
));
2184 if (dirty
& IRIS_DIRTY_RASTER
) {
2185 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2186 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
2187 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
2191 if (dirty
& (IRIS_DIRTY_RASTER
| IRIS_DIRTY_FS
)) {
2192 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2193 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
2195 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
2196 wm
.BarycentricInterpolationMode
=
2197 wm_prog_data
->barycentric_interp_modes
;
2199 if (wm_prog_data
->early_fragment_tests
)
2200 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
2201 else if (wm_prog_data
->has_side_effects
)
2202 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
2204 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
2208 // XXX: 3DSTATE_SBE, 3DSTATE_SBE_SWIZ
2209 // -> iris_raster_state (point sprite texture coordinate origin)
2210 // -> bunch of shader state...
2212 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
2213 sbe
.AttributeSwizzleEnable
= true;
2214 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2215 sbe
.VertexURBEntryReadOffset
= 1;
2216 sbe
.VertexURBEntryReadLength
= 1;
2217 sbe
.ForceVertexURBEntryReadOffset
= true;
2218 sbe
.ForceVertexURBEntryReadLength
= true;
2219 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
2221 for (int i
= 0; i
< 2; i
++) {
2222 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
2226 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbe
) {
2230 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
2231 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2232 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2233 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
2234 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
2235 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
2236 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2239 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
2240 ARRAY_SIZE(cso_blend
->ps_blend
));
2243 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
2244 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2245 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
2247 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
2248 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
2249 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
2250 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
2252 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
2255 if (dirty
& IRIS_DIRTY_SCISSOR
) {
2256 uint32_t scissor_offset
=
2257 emit_state(batch
, ice
->state
.dynamic_uploader
, ice
->state
.scissors
,
2258 sizeof(struct pipe_scissor_state
) *
2259 ice
->state
.num_scissors
, 32);
2261 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2262 ptr
.ScissorRectPointer
= scissor_offset
;
2266 // XXX: 3DSTATE_DEPTH_BUFFER
2267 // XXX: 3DSTATE_HIER_DEPTH_BUFFER
2268 // XXX: 3DSTATE_STENCIL_BUFFER
2269 // XXX: 3DSTATE_CLEAR_PARAMS
2271 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
2272 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
2273 for (int i
= 0; i
< 32; i
++) {
2274 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
2279 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
2280 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2281 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
2285 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
2286 topo
.PrimitiveTopologyType
=
2287 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
2291 if (draw
->index_size
> 0) {
2292 struct iris_resource
*res
= (struct iris_resource
*)draw
->index
.resource
;
2294 assert(!draw
->has_user_indices
);
2296 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
2297 ib
.IndexFormat
= draw
->index_size
;
2299 ib
.BufferSize
= res
->bo
->size
;
2300 ib
.BufferStartingAddress
= ro_bo(res
->bo
, 0);
2304 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
2305 struct iris_vertex_buffer_state
*cso
= ice
->state
.cso_vertex_buffers
;
2307 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_length
) == 4);
2308 STATIC_ASSERT((GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) % 32) == 0);
2310 iris_batch_emit(batch
, cso
->vertex_buffers
,
2311 sizeof(uint32_t) * (1 + 4 * cso
->num_buffers
));
2313 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
2314 iris_use_pinned_bo(batch
, cso
->bos
[i
], false);
2318 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
2319 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
2320 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
2321 (1 + cso
->count
* GENX(VERTEX_ELEMENT_STATE_length
)));
2322 for (int i
= 0; i
< cso
->count
; i
++) {
2323 iris_batch_emit(batch
, cso
->vf_instancing
[i
], sizeof(uint32_t) *
2324 (cso
->count
* GENX(3DSTATE_VF_INSTANCING_length
)));
2326 for (int i
= 0; i
< cso
->count
; i
++) {
2327 /* TODO: vertexid, instanceid support */
2328 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
);
2333 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
2334 if (draw
->primitive_restart
) {
2335 vf
.IndexedDrawCutIndexEnable
= true;
2336 vf
.CutIndex
= draw
->restart_index
;
2341 // XXX: Gen8 - PMA fix
2343 assert(!draw
->indirect
); // XXX: indirect support
2345 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
2346 prim
.StartInstanceLocation
= draw
->start_instance
;
2347 prim
.InstanceCount
= draw
->instance_count
;
2348 prim
.VertexCountPerInstance
= draw
->count
;
2349 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
2351 // XXX: this is probably bonkers.
2352 prim
.StartVertexLocation
= draw
->start
;
2354 if (draw
->index_size
) {
2355 prim
.BaseVertexLocation
+= draw
->index_bias
;
2357 prim
.StartVertexLocation
+= draw
->index_bias
;
2360 //prim.BaseVertexLocation = ...;
2365 iris_destroy_state(struct iris_context
*ice
)
2367 // XXX: unreference resources/surfaces.
2368 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
2369 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
2371 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
2375 genX(init_state
)(struct iris_context
*ice
)
2377 struct pipe_context
*ctx
= &ice
->ctx
;
2379 ctx
->create_blend_state
= iris_create_blend_state
;
2380 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
2381 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
2382 ctx
->create_sampler_state
= iris_create_sampler_state
;
2383 ctx
->create_sampler_view
= iris_create_sampler_view
;
2384 ctx
->create_surface
= iris_create_surface
;
2385 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
2386 ctx
->create_compute_state
= iris_create_compute_state
;
2387 ctx
->bind_blend_state
= iris_bind_blend_state
;
2388 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
2389 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
2390 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
2391 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
2392 ctx
->bind_compute_state
= iris_bind_compute_state
;
2393 ctx
->delete_blend_state
= iris_delete_state
;
2394 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
2395 ctx
->delete_fs_state
= iris_delete_state
;
2396 ctx
->delete_rasterizer_state
= iris_delete_state
;
2397 ctx
->delete_sampler_state
= iris_delete_state
;
2398 ctx
->delete_vertex_elements_state
= iris_delete_state
;
2399 ctx
->delete_compute_state
= iris_delete_state
;
2400 ctx
->delete_tcs_state
= iris_delete_state
;
2401 ctx
->delete_tes_state
= iris_delete_state
;
2402 ctx
->delete_gs_state
= iris_delete_state
;
2403 ctx
->delete_vs_state
= iris_delete_state
;
2404 ctx
->set_blend_color
= iris_set_blend_color
;
2405 ctx
->set_clip_state
= iris_set_clip_state
;
2406 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
2407 ctx
->set_sampler_views
= iris_set_sampler_views
;
2408 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
2409 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
2410 ctx
->set_sample_mask
= iris_set_sample_mask
;
2411 ctx
->set_scissor_states
= iris_set_scissor_states
;
2412 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
2413 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
2414 ctx
->set_viewport_states
= iris_set_viewport_states
;
2415 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
2416 ctx
->surface_destroy
= iris_surface_destroy
;
2417 ctx
->draw_vbo
= iris_draw_vbo
;
2418 ctx
->launch_grid
= iris_launch_grid
;
2419 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
2420 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
2421 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
2423 ice
->state
.destroy_state
= iris_destroy_state
;
2424 ice
->state
.init_render_context
= iris_init_render_context
;
2425 ice
->state
.upload_render_state
= iris_upload_render_state
;
2426 ice
->state
.derived_program_state_size
= iris_derived_program_state_size
;
2427 ice
->state
.set_derived_program_state
= iris_set_derived_program_state
;
2428 ice
->state
.populate_vs_key
= iris_populate_vs_key
;
2429 ice
->state
.populate_tcs_key
= iris_populate_tcs_key
;
2430 ice
->state
.populate_tes_key
= iris_populate_tes_key
;
2431 ice
->state
.populate_gs_key
= iris_populate_gs_key
;
2432 ice
->state
.populate_fs_key
= iris_populate_fs_key
;
2435 ice
->state
.dirty
= ~0ull;