2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
31 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
37 #include "pipe/p_defines.h"
38 #include "pipe/p_state.h"
39 #include "pipe/p_context.h"
40 #include "pipe/p_screen.h"
41 #include "util/u_inlines.h"
42 #include "util/u_format.h"
43 #include "util/u_framebuffer.h"
44 #include "util/u_transfer.h"
45 #include "util/u_upload_mgr.h"
48 #include "intel/compiler/brw_compiler.h"
49 #include "intel/common/gen_l3_config.h"
50 #include "intel/common/gen_sample_positions.h"
51 #include "iris_batch.h"
52 #include "iris_context.h"
53 #include "iris_pipe.h"
54 #include "iris_resource.h"
56 #define __gen_address_type struct iris_address
57 #define __gen_user_data struct iris_batch
59 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
62 __gen_combine_address(struct iris_batch
*batch
, void *location
,
63 struct iris_address addr
, uint32_t delta
)
65 uint64_t result
= addr
.offset
+ delta
;
68 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
69 /* Assume this is a general address, not relative to a base. */
70 result
+= addr
.bo
->gtt_offset
;
76 #define __genxml_cmd_length(cmd) cmd ## _length
77 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
78 #define __genxml_cmd_header(cmd) cmd ## _header
79 #define __genxml_cmd_pack(cmd) cmd ## _pack
81 #define _iris_pack_command(batch, cmd, dst, name) \
82 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
83 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
84 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
88 #define iris_pack_command(cmd, dst, name) \
89 _iris_pack_command(NULL, cmd, dst, name)
91 #define iris_pack_state(cmd, dst, name) \
92 for (struct cmd name = {}, \
93 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
94 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
97 #define iris_emit_cmd(batch, cmd, name) \
98 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
100 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
102 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
103 for (uint32_t i = 0; i < num_dwords; i++) \
104 dw[i] = (dwords0)[i] | (dwords1)[i]; \
105 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
108 #include "genxml/genX_pack.h"
109 #include "genxml/gen_macros.h"
110 #include "genxml/genX_bits.h"
112 #define MOCS_WB (2 << 1)
114 UNUSED
static void pipe_asserts()
116 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
118 /* pipe_logicop happens to match the hardware. */
119 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
120 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
121 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
122 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
123 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
124 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
125 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
126 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
127 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
128 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
129 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
130 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
131 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
132 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
133 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
134 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
136 /* pipe_blend_func happens to match the hardware. */
137 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
138 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
139 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
140 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
141 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
142 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
143 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
144 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
145 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
146 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
147 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
148 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
149 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
150 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
151 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
152 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
153 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
157 /* pipe_blend_func happens to match the hardware. */
158 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
159 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
160 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
161 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
162 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
164 /* pipe_stencil_op happens to match the hardware. */
165 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
166 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
167 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
168 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
169 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
170 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
171 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
172 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
174 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
175 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
176 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
181 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
183 static const unsigned map
[] = {
184 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
185 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
186 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
187 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
188 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
189 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
190 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
191 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
192 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
193 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
194 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
195 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
196 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
197 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
198 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
201 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
205 translate_compare_func(enum pipe_compare_func pipe_func
)
207 static const unsigned map
[] = {
208 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
209 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
210 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
211 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
212 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
213 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
214 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
215 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
217 return map
[pipe_func
];
221 translate_shadow_func(enum pipe_compare_func pipe_func
)
223 /* Gallium specifies the result of shadow comparisons as:
225 * 1 if ref <op> texel,
230 * 0 if texel <op> ref,
233 * So we need to flip the operator and also negate.
235 static const unsigned map
[] = {
236 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
237 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
238 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
239 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
240 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
241 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
242 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
243 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
245 return map
[pipe_func
];
249 translate_cull_mode(unsigned pipe_face
)
251 static const unsigned map
[4] = {
252 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
253 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
254 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
255 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
257 return map
[pipe_face
];
261 translate_fill_mode(unsigned pipe_polymode
)
263 static const unsigned map
[4] = {
264 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
265 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
266 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
267 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
269 return map
[pipe_polymode
];
272 static struct iris_address
273 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
276 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
280 upload_state(struct u_upload_mgr
*uploader
,
281 struct iris_state_ref
*ref
,
286 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
291 stream_state(struct iris_batch
*batch
,
292 struct u_upload_mgr
*uploader
,
293 struct pipe_resource
**out_res
,
296 uint32_t *out_offset
)
300 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
302 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
303 iris_use_pinned_bo(batch
, bo
, false);
305 *out_offset
+= iris_bo_offset_from_base_address(bo
);
311 emit_state(struct iris_batch
*batch
,
312 struct u_upload_mgr
*uploader
,
313 struct pipe_resource
**out_res
,
320 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
323 memcpy(map
, data
, size
);
328 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
329 #define cso_changed_memcmp(x) \
330 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
333 iris_init_render_context(struct iris_screen
*screen
,
334 struct iris_batch
*batch
,
335 struct iris_vtable
*vtbl
,
336 struct pipe_debug_callback
*dbg
)
338 iris_init_batch(batch
, screen
, vtbl
, dbg
, I915_EXEC_RENDER
);
340 /* XXX: PIPE_CONTROLs */
342 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
344 // XXX: MOCS is stupid for this.
345 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
346 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
347 sba
.SurfaceStateMemoryObjectControlState
= MOCS_WB
;
348 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
349 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
350 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
351 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
354 sba
.GeneralStateBaseAddressModifyEnable
= true;
355 sba
.SurfaceStateBaseAddressModifyEnable
= true;
356 sba
.DynamicStateBaseAddressModifyEnable
= true;
357 sba
.IndirectObjectBaseAddressModifyEnable
= true;
358 sba
.InstructionBaseAddressModifyEnable
= true;
359 sba
.GeneralStateBufferSizeModifyEnable
= true;
360 sba
.DynamicStateBufferSizeModifyEnable
= true;
361 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
362 sba
.IndirectObjectBufferSizeModifyEnable
= true;
363 sba
.InstructionBuffersizeModifyEnable
= true;
365 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
366 sba
.SurfaceStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SURFACE_START
);
367 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
369 sba
.GeneralStateBufferSize
= 0xfffff;
370 sba
.IndirectObjectBufferSize
= 0xfffff;
371 sba
.InstructionBufferSize
= 0xfffff;
372 sba
.DynamicStateBufferSize
= 0xfffff;
375 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
376 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
377 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
379 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
380 GEN_SAMPLE_POS_1X(pat
._1xSample
);
381 GEN_SAMPLE_POS_2X(pat
._2xSample
);
382 GEN_SAMPLE_POS_4X(pat
._4xSample
);
383 GEN_SAMPLE_POS_8X(pat
._8xSample
);
384 GEN_SAMPLE_POS_16X(pat
._16xSample
);
386 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
387 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
388 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
389 /* XXX: may need to set an offset for origin-UL framebuffers */
390 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
392 /* Just assign a static partitioning. */
393 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
394 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
395 alloc
._3DCommandSubOpcode
= 18 + i
;
396 alloc
.ConstantBufferOffset
= 6 * i
;
397 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
403 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
408 iris_set_blend_color(struct pipe_context
*ctx
,
409 const struct pipe_blend_color
*state
)
411 struct iris_context
*ice
= (struct iris_context
*) ctx
;
413 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
414 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
417 struct iris_blend_state
{
418 /** Partial 3DSTATE_PS_BLEND */
419 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
421 /** Partial BLEND_STATE */
422 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
423 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
425 bool alpha_to_coverage
; /* for shader key */
429 iris_create_blend_state(struct pipe_context
*ctx
,
430 const struct pipe_blend_state
*state
)
432 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
433 uint32_t *blend_state
= cso
->blend_state
;
435 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
437 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
438 /* pb.HasWriteableRT is filled in at draw time. */
439 /* pb.AlphaTestEnable is filled in at draw time. */
440 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
441 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
443 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
445 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
446 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
447 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
448 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
451 iris_pack_state(GENX(BLEND_STATE
), blend_state
, bs
) {
452 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
453 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
454 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
455 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
456 bs
.ColorDitherEnable
= state
->dither
;
457 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
460 blend_state
+= GENX(BLEND_STATE_length
);
462 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
463 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_state
, be
) {
464 be
.LogicOpEnable
= state
->logicop_enable
;
465 be
.LogicOpFunction
= state
->logicop_func
;
467 be
.PreBlendSourceOnlyClampEnable
= false;
468 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
469 be
.PreBlendColorClampEnable
= true;
470 be
.PostBlendColorClampEnable
= true;
472 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
474 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
475 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
476 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
477 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
478 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
479 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
481 be
.WriteDisableRed
= !(state
->rt
[i
].colormask
& PIPE_MASK_R
);
482 be
.WriteDisableGreen
= !(state
->rt
[i
].colormask
& PIPE_MASK_G
);
483 be
.WriteDisableBlue
= !(state
->rt
[i
].colormask
& PIPE_MASK_B
);
484 be
.WriteDisableAlpha
= !(state
->rt
[i
].colormask
& PIPE_MASK_A
);
486 blend_state
+= GENX(BLEND_STATE_ENTRY_length
);
493 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
495 struct iris_context
*ice
= (struct iris_context
*) ctx
;
496 ice
->state
.cso_blend
= state
;
497 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
498 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
501 struct iris_depth_stencil_alpha_state
{
502 /** Partial 3DSTATE_WM_DEPTH_STENCIL */
503 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
505 /** Complete CC_VIEWPORT */
506 uint32_t cc_vp
[GENX(CC_VIEWPORT_length
)];
508 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE */
509 struct pipe_alpha_state alpha
;
513 iris_create_zsa_state(struct pipe_context
*ctx
,
514 const struct pipe_depth_stencil_alpha_state
*state
)
516 struct iris_depth_stencil_alpha_state
*cso
=
517 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
519 cso
->alpha
= state
->alpha
;
521 bool two_sided_stencil
= state
->stencil
[1].enabled
;
523 /* The state tracker needs to optimize away EQUAL writes for us. */
524 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
526 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
527 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
528 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
529 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
530 wmds
.StencilTestFunction
=
531 translate_compare_func(state
->stencil
[0].func
);
532 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
533 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
534 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
535 wmds
.BackfaceStencilTestFunction
=
536 translate_compare_func(state
->stencil
[1].func
);
537 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
538 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
539 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
540 wmds
.StencilBufferWriteEnable
=
541 state
->stencil
[0].writemask
!= 0 ||
542 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
543 wmds
.DepthTestEnable
= state
->depth
.enabled
;
544 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
545 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
546 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
547 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
548 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
549 /* wmds.[Backface]StencilReferenceValue are merged later */
552 iris_pack_state(GENX(CC_VIEWPORT
), cso
->cc_vp
, ccvp
) {
553 ccvp
.MinimumDepth
= state
->depth
.bounds_min
;
554 ccvp
.MaximumDepth
= state
->depth
.bounds_max
;
561 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
563 struct iris_context
*ice
= (struct iris_context
*) ctx
;
564 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
565 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
568 if (cso_changed(alpha
.ref_value
))
569 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
571 if (cso_changed(alpha
.enabled
))
572 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
575 ice
->state
.cso_zsa
= new_cso
;
576 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
577 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
580 struct iris_rasterizer_state
{
581 uint32_t sf
[GENX(3DSTATE_SF_length
)];
582 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
583 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
584 uint32_t wm
[GENX(3DSTATE_WM_length
)];
585 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
587 bool flatshade
; /* for shader state */
588 bool clamp_fragment_color
; /* for shader state */
589 bool light_twoside
; /* for shader state */
590 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
591 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
592 bool line_stipple_enable
;
593 bool poly_stipple_enable
;
594 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
595 uint16_t sprite_coord_enable
;
599 iris_create_rasterizer_state(struct pipe_context
*ctx
,
600 const struct pipe_rasterizer_state
*state
)
602 struct iris_rasterizer_state
*cso
=
603 malloc(sizeof(struct iris_rasterizer_state
));
606 point_quad_rasterization
-> SBE
?
611 force_persample_interp
- ?
614 offset_units_unscaled
- cap
not exposed
618 cso
->flatshade
= state
->flatshade
;
619 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
620 cso
->light_twoside
= state
->light_twoside
;
621 cso
->rasterizer_discard
= state
->rasterizer_discard
;
622 cso
->half_pixel_center
= state
->half_pixel_center
;
623 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
624 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
625 cso
->line_stipple_enable
= state
->line_stipple_enable
;
626 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
628 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
629 sf
.StatisticsEnable
= true;
630 sf
.ViewportTransformEnable
= true;
631 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
632 sf
.LineEndCapAntialiasingRegionWidth
=
633 state
->line_smooth
? _10pixels
: _05pixels
;
634 sf
.LastPixelEnable
= state
->line_last_pixel
;
635 sf
.LineWidth
= state
->line_width
;
636 sf
.SmoothPointEnable
= state
->point_smooth
;
637 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
638 sf
.PointWidth
= state
->point_size
;
640 if (state
->flatshade_first
) {
641 sf
.TriangleFanProvokingVertexSelect
= 1;
643 sf
.TriangleStripListProvokingVertexSelect
= 2;
644 sf
.TriangleFanProvokingVertexSelect
= 2;
645 sf
.LineStripListProvokingVertexSelect
= 1;
649 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
650 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
651 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
652 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
653 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
654 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
655 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
656 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
657 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
658 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
659 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
660 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
661 rr
.SmoothPointEnable
= state
->point_smooth
;
662 rr
.AntialiasingEnable
= state
->line_smooth
;
663 rr
.ScissorRectangleEnable
= state
->scissor
;
664 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
665 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
666 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
669 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
670 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
671 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
673 cl
.StatisticsEnable
= true;
674 cl
.EarlyCullEnable
= true;
675 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
676 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
677 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
678 cl
.GuardbandClipTestEnable
= true;
679 cl
.ClipMode
= CLIPMODE_NORMAL
;
680 cl
.ClipEnable
= true;
681 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
682 cl
.MinimumPointWidth
= 0.125;
683 cl
.MaximumPointWidth
= 255.875;
685 if (state
->flatshade_first
) {
686 cl
.TriangleFanProvokingVertexSelect
= 1;
688 cl
.TriangleStripListProvokingVertexSelect
= 2;
689 cl
.TriangleFanProvokingVertexSelect
= 2;
690 cl
.LineStripListProvokingVertexSelect
= 1;
694 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
695 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
696 * filled in at draw time from the FS program.
698 wm
.LineAntialiasingRegionWidth
= _10pixels
;
699 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
700 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
701 wm
.StatisticsEnable
= true;
702 wm
.LineStippleEnable
= state
->line_stipple_enable
;
703 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
706 /* Remap from 0..255 back to 1..256 */
707 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
709 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
710 line
.LineStipplePattern
= state
->line_stipple_pattern
;
711 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
712 line
.LineStippleRepeatCount
= line_stipple_factor
;
719 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
721 struct iris_context
*ice
= (struct iris_context
*) ctx
;
722 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
723 struct iris_rasterizer_state
*new_cso
= state
;
726 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
727 if (cso_changed_memcmp(line_stipple
))
728 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
730 if (cso_changed(half_pixel_center
))
731 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
733 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
734 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
737 ice
->state
.cso_rast
= new_cso
;
738 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
739 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
743 translate_wrap(unsigned pipe_wrap
)
745 static const unsigned map
[] = {
746 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
747 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
748 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
749 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
750 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
751 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
753 /* These are unsupported. */
754 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
755 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
757 return map
[pipe_wrap
];
761 * Return true if the given wrap mode requires the border color to exist.
764 wrap_mode_needs_border_color(unsigned wrap_mode
)
766 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
770 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
772 static const unsigned map
[] = {
773 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
774 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
775 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
777 return map
[pipe_mip
];
780 struct iris_sampler_state
{
781 struct pipe_sampler_state base
;
783 bool needs_border_color
;
785 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
789 iris_create_sampler_state(struct pipe_context
*pctx
,
790 const struct pipe_sampler_state
*state
)
792 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
797 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
798 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
800 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
801 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
802 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
804 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
805 wrap_mode_needs_border_color(wrap_t
) ||
806 wrap_mode_needs_border_color(wrap_r
);
808 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
809 samp
.TCXAddressControlMode
= wrap_s
;
810 samp
.TCYAddressControlMode
= wrap_t
;
811 samp
.TCZAddressControlMode
= wrap_r
;
812 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
813 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
814 samp
.MinModeFilter
= state
->min_img_filter
;
815 samp
.MagModeFilter
= state
->mag_img_filter
;
816 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
817 samp
.MaximumAnisotropy
= RATIO21
;
819 if (state
->max_anisotropy
>= 2) {
820 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
821 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
822 samp
.AnisotropicAlgorithm
= EWAApproximation
;
825 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
826 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
828 samp
.MaximumAnisotropy
=
829 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
832 /* Set address rounding bits if not using nearest filtering. */
833 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
834 samp
.UAddressMinFilterRoundingEnable
= true;
835 samp
.VAddressMinFilterRoundingEnable
= true;
836 samp
.RAddressMinFilterRoundingEnable
= true;
839 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
840 samp
.UAddressMagFilterRoundingEnable
= true;
841 samp
.VAddressMagFilterRoundingEnable
= true;
842 samp
.RAddressMagFilterRoundingEnable
= true;
845 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
846 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
848 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
850 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
851 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
852 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
853 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
855 //samp.BorderColorPointer = <<comes from elsewhere>>
862 iris_bind_sampler_states(struct pipe_context
*ctx
,
863 enum pipe_shader_type p_stage
,
864 unsigned start
, unsigned count
,
867 struct iris_context
*ice
= (struct iris_context
*) ctx
;
868 gl_shader_stage stage
= stage_from_pipe(p_stage
);
870 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
872 /* Assemble the SAMPLER_STATEs into a contiguous chunk of memory
873 * relative to Dynamic State Base Address.
875 void *map
= upload_state(ice
->state
.dynamic_uploader
,
876 &ice
->state
.sampler_table
[stage
],
877 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
881 struct pipe_resource
*res
= ice
->state
.sampler_table
[stage
].res
;
882 ice
->state
.sampler_table
[stage
].offset
+=
883 iris_bo_offset_from_base_address(iris_resource_bo(res
));
885 for (int i
= 0; i
< count
; i
++) {
886 struct iris_sampler_state
*state
= states
[i
];
888 /* Save a pointer to the iris_sampler_state, a few fields need
889 * to inform draw-time decisions.
891 ice
->state
.samplers
[stage
][start
+ i
] = state
;
894 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
896 map
+= GENX(SAMPLER_STATE_length
);
899 ice
->state
.num_samplers
[stage
] = count
;
901 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
904 struct iris_sampler_view
{
905 struct pipe_sampler_view pipe
;
906 struct isl_view view
;
908 /** The resource (BO) holding our SURFACE_STATE. */
909 struct iris_state_ref surface_state
;
913 * Convert an swizzle enumeration (i.e. PIPE_SWIZZLE_X) to one of the Gen7.5+
914 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
916 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
919 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
921 * which is simply adding 4 then modding by 8 (or anding with 7).
923 * We then may need to apply workarounds for textureGather hardware bugs.
925 static enum isl_channel_select
926 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
928 return (swizzle
+ 4) & 7;
931 static struct pipe_sampler_view
*
932 iris_create_sampler_view(struct pipe_context
*ctx
,
933 struct pipe_resource
*tex
,
934 const struct pipe_sampler_view
*tmpl
)
936 struct iris_context
*ice
= (struct iris_context
*) ctx
;
937 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
938 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
939 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
944 /* initialize base object */
946 isv
->pipe
.context
= ctx
;
947 isv
->pipe
.texture
= NULL
;
948 pipe_reference_init(&isv
->pipe
.reference
, 1);
949 pipe_resource_reference(&isv
->pipe
.texture
, tex
);
951 /* XXX: do we need brw_get_texture_swizzle hacks here? */
953 isv
->view
= (struct isl_view
) {
954 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
955 .base_level
= tmpl
->u
.tex
.first_level
,
956 .levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1,
957 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
958 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
959 .swizzle
= (struct isl_swizzle
) {
960 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
961 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
962 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
963 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
965 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
968 void *map
= upload_state(ice
->state
.surface_uploader
, &isv
->surface_state
,
969 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
973 struct iris_bo
*state_bo
= iris_resource_bo(isv
->surface_state
.res
);
974 isv
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
976 isl_surf_fill_state(&screen
->isl_dev
, map
,
977 .surf
= &itex
->surf
, .view
= &isv
->view
,
979 .address
= itex
->bo
->gtt_offset
);
981 // .clear_color = clear_color,
986 static struct pipe_surface
*
987 iris_create_surface(struct pipe_context
*ctx
,
988 struct pipe_resource
*tex
,
989 const struct pipe_surface
*tmpl
)
991 struct iris_context
*ice
= (struct iris_context
*) ctx
;
992 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
993 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
994 struct pipe_surface
*psurf
= &surf
->pipe
;
995 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1000 pipe_reference_init(&psurf
->reference
, 1);
1001 pipe_resource_reference(&psurf
->texture
, tex
);
1002 psurf
->context
= ctx
;
1003 psurf
->format
= tmpl
->format
;
1004 psurf
->width
= tex
->width0
;
1005 psurf
->height
= tex
->height0
;
1006 psurf
->texture
= tex
;
1007 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1008 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1009 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1013 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1014 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1015 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1017 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1019 surf
->view
= (struct isl_view
) {
1020 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
1021 .base_level
= tmpl
->u
.tex
.level
,
1023 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1024 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1025 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1029 /* Bail early for depth/stencil */
1030 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1031 ISL_SURF_USAGE_STENCIL_BIT
))
1035 void *map
= upload_state(ice
->state
.surface_uploader
, &surf
->surface_state
,
1036 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1040 struct iris_bo
*state_bo
= iris_resource_bo(surf
->surface_state
.res
);
1041 surf
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1043 isl_surf_fill_state(&screen
->isl_dev
, map
,
1044 .surf
= &res
->surf
, .view
= &surf
->view
,
1046 .address
= res
->bo
->gtt_offset
);
1048 // .clear_color = clear_color,
1054 iris_set_sampler_views(struct pipe_context
*ctx
,
1055 enum pipe_shader_type p_stage
,
1056 unsigned start
, unsigned count
,
1057 struct pipe_sampler_view
**views
)
1059 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1060 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1063 for (i
= 0; i
< count
; i
++) {
1064 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1065 &ice
->state
.textures
[stage
][i
], views
[i
]);
1067 for (; i
< ice
->state
.num_textures
[stage
]; i
++) {
1068 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1069 &ice
->state
.textures
[stage
][i
], NULL
);
1072 ice
->state
.num_textures
[stage
] = count
;
1074 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
1078 iris_set_clip_state(struct pipe_context
*ctx
,
1079 const struct pipe_clip_state
*state
)
1084 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1085 const struct pipe_poly_stipple
*state
)
1087 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1088 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1089 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1093 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1095 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1097 ice
->state
.sample_mask
= sample_mask
;
1098 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1102 iris_set_scissor_states(struct pipe_context
*ctx
,
1103 unsigned start_slot
,
1104 unsigned num_scissors
,
1105 const struct pipe_scissor_state
*states
)
1107 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1109 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1110 ice
->state
.scissors
[start_slot
+ i
] = states
[i
];
1113 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1117 iris_set_stencil_ref(struct pipe_context
*ctx
,
1118 const struct pipe_stencil_ref
*state
)
1120 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1121 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1122 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1126 struct iris_viewport_state
{
1127 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
) * IRIS_MAX_VIEWPORTS
];
1131 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1133 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1138 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1139 float m00
, float m11
, float m30
, float m31
,
1140 float *xmin
, float *xmax
,
1141 float *ymin
, float *ymax
)
1143 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1144 * Strips and Fans documentation:
1146 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1147 * fixed-point "guardband" range supported by the rasterization hardware"
1151 * "In almost all circumstances, if an object’s vertices are actually
1152 * modified by this clamping (i.e., had X or Y coordinates outside of
1153 * the guardband extent the rendered object will not match the intended
1154 * result. Therefore software should take steps to ensure that this does
1155 * not happen - e.g., by clipping objects such that they do not exceed
1156 * these limits after the Drawing Rectangle is applied."
1158 * I believe the fundamental restriction is that the rasterizer (in
1159 * the SF/WM stages) have a limit on the number of pixels that can be
1160 * rasterized. We need to ensure any coordinates beyond the rasterizer
1161 * limit are handled by the clipper. So effectively that limit becomes
1162 * the clipper's guardband size.
1164 * It goes on to say:
1166 * "In addition, in order to be correctly rendered, objects must have a
1167 * screenspace bounding box not exceeding 8K in the X or Y direction.
1168 * This additional restriction must also be comprehended by software,
1169 * i.e., enforced by use of clipping."
1171 * This makes no sense. Gen7+ hardware supports 16K render targets,
1172 * and you definitely need to be able to draw polygons that fill the
1173 * surface. Our assumption is that the rasterizer was limited to 8K
1174 * on Sandybridge, which only supports 8K surfaces, and it was actually
1175 * increased to 16K on Ivybridge and later.
1177 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1179 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1181 if (m00
!= 0 && m11
!= 0) {
1182 /* First, we compute the screen-space render area */
1183 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1184 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1185 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1186 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1188 /* We want the guardband to be centered on that */
1189 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1190 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1191 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1192 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1194 /* Now we need it in native device coordinates */
1195 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1196 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1197 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1198 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1200 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1201 * flipped upside-down. X should be fine though.
1203 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1204 *xmin
= ndc_gb_xmin
;
1205 *xmax
= ndc_gb_xmax
;
1206 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1207 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1209 /* The viewport scales to 0, so nothing will be rendered. */
1219 iris_set_viewport_states(struct pipe_context
*ctx
,
1220 unsigned start_slot
,
1222 const struct pipe_viewport_state
*states
)
1224 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1225 struct iris_viewport_state
*cso
= ice
->state
.cso_vp
;
1226 uint32_t *vp_map
= &cso
->sf_cl_vp
[start_slot
];
1228 // XXX: sf_cl_vp is only big enough for one slot, we don't iterate right
1229 for (unsigned i
= 0; i
< count
; i
++) {
1230 const struct pipe_viewport_state
*state
= &states
[start_slot
+ i
];
1231 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
1232 vp
.ViewportMatrixElementm00
= state
->scale
[0];
1233 vp
.ViewportMatrixElementm11
= state
->scale
[1];
1234 vp
.ViewportMatrixElementm22
= state
->scale
[2];
1235 vp
.ViewportMatrixElementm30
= state
->translate
[0];
1236 vp
.ViewportMatrixElementm31
= state
->translate
[1];
1237 vp
.ViewportMatrixElementm32
= state
->translate
[2];
1238 /* XXX: in i965 this is computed based on the drawbuffer size,
1239 * but we don't have that here...
1241 vp
.XMinClipGuardband
= -1.0;
1242 vp
.XMaxClipGuardband
= 1.0;
1243 vp
.YMinClipGuardband
= -1.0;
1244 vp
.YMaxClipGuardband
= 1.0;
1245 vp
.XMinViewPort
= viewport_extent(state
, 0, -1.0f
);
1246 vp
.XMaxViewPort
= viewport_extent(state
, 0, 1.0f
) - 1;
1247 vp
.YMinViewPort
= viewport_extent(state
, 1, -1.0f
);
1248 vp
.YMaxViewPort
= viewport_extent(state
, 1, 1.0f
) - 1;
1251 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
1254 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1257 struct iris_depth_buffer_state
1259 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
1260 GENX(3DSTATE_STENCIL_BUFFER_length
) +
1261 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
1262 GENX(3DSTATE_CLEAR_PARAMS_length
)];
1266 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1267 const struct pipe_framebuffer_state
*state
)
1269 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1270 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1271 struct isl_device
*isl_dev
= &screen
->isl_dev
;
1272 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1274 if (cso
->samples
!= state
->samples
) {
1275 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1278 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
1279 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1282 if ((cso
->layers
== 0) == (state
->layers
== 0)) {
1283 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1286 util_copy_framebuffer_state(cso
, state
);
1288 struct iris_depth_buffer_state
*cso_z
=
1289 malloc(sizeof(struct iris_depth_buffer_state
));
1291 struct isl_view view
= {
1294 .base_array_layer
= 0,
1296 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1299 struct isl_depth_stencil_hiz_emit_info info
= {
1304 struct iris_resource
*zres
=
1305 (void *) (cso
->zsbuf
? cso
->zsbuf
->texture
: NULL
);
1308 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
1310 info
.depth_surf
= &zres
->surf
;
1311 info
.depth_address
= zres
->bo
->gtt_offset
;
1313 view
.format
= zres
->surf
.format
;
1315 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
1316 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
1318 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
1320 info
.hiz_usage
= ISL_AUX_USAGE_NONE
;
1325 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
1326 info
.stencil_surf
= &stencil_mt
->surf
;
1329 view
.base_level
= stencil_irb
->mt_level
- stencil_irb
->mt
->first_level
;
1330 view
.base_array_layer
= stencil_irb
->mt_layer
;
1331 view
.array_len
= MAX2(stencil_irb
->layer_count
, 1);
1332 view
.format
= stencil_mt
->surf
.format
;
1335 uint32_t stencil_offset
= 0;
1336 info
.stencil_address
= stencil_mt
->bo
->gtt_offset
+ stencil_mt
->offset
;
1340 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
1342 free(ice
->state
.cso_depthbuffer
);
1343 ice
->state
.cso_depthbuffer
= cso_z
;
1344 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
1346 /* Render target change */
1347 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
1351 iris_set_constant_buffer(struct pipe_context
*ctx
,
1352 enum pipe_shader_type p_stage
, unsigned index
,
1353 const struct pipe_constant_buffer
*input
)
1355 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1356 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1357 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1358 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
1359 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
1361 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1362 if (input
->user_buffer
) {
1363 u_upload_data(ctx
->const_uploader
, 0, input
->buffer_size
, 32,
1364 input
->user_buffer
, &cbuf
->data
.offset
,
1367 pipe_resource_reference(&cbuf
->data
.res
, input
->buffer
);
1370 // XXX: these are not retained forever, use a separate uploader?
1372 upload_state(ice
->state
.surface_uploader
, &cbuf
->surface_state
,
1373 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1374 if (!unlikely(map
)) {
1375 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
1379 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
1380 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state
.res
);
1381 cbuf
->surface_state
.offset
+= iris_bo_offset_from_base_address(surf_bo
);
1383 isl_buffer_fill_state(&screen
->isl_dev
, map
,
1384 .address
= res
->bo
->gtt_offset
+ cbuf
->data
.offset
,
1385 .size_B
= input
->buffer_size
,
1386 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
1390 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
1391 pipe_resource_reference(&cbuf
->surface_state
.res
, NULL
);
1394 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
1395 // XXX: maybe not necessary all the time...?
1396 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1400 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1401 struct pipe_sampler_view
*state
)
1403 struct iris_sampler_view
*isv
= (void *) state
;
1404 pipe_resource_reference(&state
->texture
, NULL
);
1405 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1411 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1413 struct iris_surface
*surf
= (void *) p_surf
;
1414 pipe_resource_reference(&p_surf
->texture
, NULL
);
1415 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
1420 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1425 struct iris_vertex_buffer_state
{
1426 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
1427 struct pipe_resource
*resources
[33];
1428 unsigned num_buffers
;
1432 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
1434 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
1435 pipe_resource_reference(&cso
->resources
[i
], NULL
);
1439 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1440 unsigned start_slot
, unsigned count
,
1441 const struct pipe_vertex_buffer
*buffers
)
1443 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1444 struct iris_vertex_buffer_state
*cso
= ice
->state
.cso_vertex_buffers
;
1446 iris_free_vertex_buffers(ice
->state
.cso_vertex_buffers
);
1451 cso
->num_buffers
= count
;
1453 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1454 vb
.DWordLength
= 4 * MAX2(cso
->num_buffers
, 1) - 1;
1457 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1460 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1461 vb
.VertexBufferIndex
= start_slot
;
1462 vb
.NullVertexBuffer
= true;
1463 vb
.AddressModifyEnable
= true;
1467 for (unsigned i
= 0; i
< count
; i
++) {
1468 assert(!buffers
[i
].is_user_buffer
);
1470 pipe_resource_reference(&cso
->resources
[i
], buffers
[i
].buffer
.resource
);
1471 struct iris_resource
*res
= (void *) cso
->resources
[i
];
1473 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1474 vb
.VertexBufferIndex
= start_slot
+ i
;
1476 vb
.AddressModifyEnable
= true;
1477 vb
.BufferPitch
= buffers
[i
].stride
;
1478 vb
.BufferSize
= res
->bo
->size
;
1479 vb
.BufferStartingAddress
=
1480 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffers
[i
].buffer_offset
);
1483 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1486 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1489 struct iris_vertex_element_state
{
1490 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1491 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
1496 iris_create_vertex_elements(struct pipe_context
*ctx
,
1498 const struct pipe_vertex_element
*state
)
1500 struct iris_vertex_element_state
*cso
=
1501 malloc(sizeof(struct iris_vertex_element_state
));
1503 cso
->count
= MAX2(count
, 1);
1506 * - create edge flag one
1508 * - if those are necessary, use count + 1/2/3... OR in the length
1510 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
1511 ve
.DWordLength
= 1 + GENX(VERTEX_ELEMENT_STATE_length
) * cso
->count
- 2;
1514 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1515 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
1518 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1520 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
1521 ve
.Component0Control
= VFCOMP_STORE_0
;
1522 ve
.Component1Control
= VFCOMP_STORE_0
;
1523 ve
.Component2Control
= VFCOMP_STORE_0
;
1524 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
1527 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
1531 for (int i
= 0; i
< count
; i
++) {
1532 enum isl_format isl_format
=
1533 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1534 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
1535 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
1537 switch (isl_format_get_num_channels(isl_format
)) {
1538 case 0: comp
[0] = VFCOMP_STORE_0
;
1539 case 1: comp
[1] = VFCOMP_STORE_0
;
1540 case 2: comp
[2] = VFCOMP_STORE_0
;
1542 comp
[3] = isl_format_has_int_channel(isl_format
) ? VFCOMP_STORE_1_INT
1543 : VFCOMP_STORE_1_FP
;
1546 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1547 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1549 ve
.SourceElementOffset
= state
[i
].src_offset
;
1550 ve
.SourceElementFormat
= isl_format
;
1551 ve
.Component0Control
= comp
[0];
1552 ve
.Component1Control
= comp
[1];
1553 ve
.Component2Control
= comp
[2];
1554 ve
.Component3Control
= comp
[3];
1557 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
1558 vi
.VertexElementIndex
= i
;
1559 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1560 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1563 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1564 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
1571 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
1573 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1575 ice
->state
.cso_vertex_elements
= state
;
1576 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
1580 iris_create_compute_state(struct pipe_context
*ctx
,
1581 const struct pipe_compute_state
*state
)
1586 static struct pipe_stream_output_target
*
1587 iris_create_stream_output_target(struct pipe_context
*ctx
,
1588 struct pipe_resource
*res
,
1589 unsigned buffer_offset
,
1590 unsigned buffer_size
)
1592 struct pipe_stream_output_target
*t
=
1593 CALLOC_STRUCT(pipe_stream_output_target
);
1597 pipe_reference_init(&t
->reference
, 1);
1598 pipe_resource_reference(&t
->buffer
, res
);
1599 t
->buffer_offset
= buffer_offset
;
1600 t
->buffer_size
= buffer_size
;
1605 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
1606 struct pipe_stream_output_target
*t
)
1608 pipe_resource_reference(&t
->buffer
, NULL
);
1613 iris_set_stream_output_targets(struct pipe_context
*ctx
,
1614 unsigned num_targets
,
1615 struct pipe_stream_output_target
**targets
,
1616 const unsigned *offsets
)
1621 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
1622 const struct brw_vue_map
*last_vue_map
,
1623 bool two_sided_color
,
1624 unsigned *out_offset
,
1625 unsigned *out_length
)
1627 /* The compiler computes the first URB slot without considering COL/BFC
1628 * swizzling (because it doesn't know whether it's enabled), so we need
1629 * to do that here too. This may result in a smaller offset, which
1632 const unsigned first_slot
=
1633 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
1635 /* This becomes the URB read offset (counted in pairs of slots). */
1636 assert(first_slot
% 2 == 0);
1637 *out_offset
= first_slot
/ 2;
1639 /* We need to adjust the inputs read to account for front/back color
1640 * swizzling, as it can make the URB length longer.
1642 for (int c
= 0; c
<= 1; c
++) {
1643 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
1644 /* If two sided color is enabled, the fragment shader's gl_Color
1645 * (COL0) input comes from either the gl_FrontColor (COL0) or
1646 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
1648 if (two_sided_color
)
1649 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1651 /* If front color isn't written, we opt to give them back color
1652 * instead of an undefined value. Switch from COL to BFC.
1654 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
1655 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
1656 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1661 /* Compute the minimum URB Read Length necessary for the FS inputs.
1663 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1664 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1666 * "This field should be set to the minimum length required to read the
1667 * maximum source attribute. The maximum source attribute is indicated
1668 * by the maximum value of the enabled Attribute # Source Attribute if
1669 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1670 * enable is not set.
1671 * read_length = ceiling((max_source_attr + 1) / 2)
1673 * [errata] Corruption/Hang possible if length programmed larger than
1676 * Similar text exists for Ivy Bridge.
1678 * We find the last URB slot that's actually read by the FS.
1680 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
1681 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
1682 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
1685 /* The URB read length is the difference of the two, counted in pairs. */
1686 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
1690 iris_emit_sbe_swiz(struct iris_batch
*batch
,
1691 const struct iris_context
*ice
,
1692 unsigned urb_read_offset
)
1694 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
1695 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
1696 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
1697 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
1698 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
1700 /* XXX: this should be generated when putting programs in place */
1702 // XXX: raster->sprite_coord_enable
1704 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
1705 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
1706 if (input_index
< 0 || input_index
>= 16)
1709 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
1710 &attr_overrides
[input_index
];
1712 /* Viewport and Layer are stored in the VUE header. We need to override
1713 * them to zero if earlier stages didn't write them, as GL requires that
1714 * they read back as zero when not explicitly set.
1717 case VARYING_SLOT_VIEWPORT
:
1718 case VARYING_SLOT_LAYER
:
1719 attr
->ComponentOverrideX
= true;
1720 attr
->ComponentOverrideW
= true;
1721 attr
->ConstantSource
= CONST_0000
;
1723 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
1724 attr
->ComponentOverrideY
= true;
1725 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
1726 attr
->ComponentOverrideZ
= true;
1729 case VARYING_SLOT_PRIMITIVE_ID
:
1730 attr
->ComponentOverrideX
= true;
1731 attr
->ComponentOverrideY
= true;
1732 attr
->ComponentOverrideZ
= true;
1733 attr
->ComponentOverrideW
= true;
1734 attr
->ConstantSource
= PRIM_ID
;
1741 int slot
= vue_map
->varying_to_slot
[fs_attr
];
1743 /* If there was only a back color written but not front, use back
1744 * as the color instead of undefined.
1746 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
1747 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
1748 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
1749 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
1751 /* Not written by the previous stage - undefined. */
1753 attr
->ComponentOverrideX
= true;
1754 attr
->ComponentOverrideY
= true;
1755 attr
->ComponentOverrideZ
= true;
1756 attr
->ComponentOverrideW
= true;
1757 attr
->ConstantSource
= CONST_0001_FLOAT
;
1761 /* Compute the location of the attribute relative to the read offset,
1762 * which is counted in 256-bit increments (two 128-bit VUE slots).
1764 const int source_attr
= slot
- 2 * urb_read_offset
;
1765 assert(source_attr
>= 0 && source_attr
<= 32);
1766 attr
->SourceAttribute
= source_attr
;
1768 /* If we are doing two-sided color, and the VUE slot following this one
1769 * represents a back-facing color, then we need to instruct the SF unit
1770 * to do back-facing swizzling.
1772 if (cso_rast
->light_twoside
&&
1773 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
1774 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
1775 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
1776 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
1777 attr
->SwizzleSelect
= INPUTATTR_FACING
;
1780 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
1781 for (int i
= 0; i
< 16; i
++)
1782 sbes
.Attribute
[i
] = attr_overrides
[i
];
1787 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
1789 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
1790 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
1791 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
1792 struct pipe_shader_state
*p_fs
=
1793 (void *) ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1794 assert(p_fs
->type
== PIPE_SHADER_IR_NIR
);
1795 nir_shader
*fs_nir
= p_fs
->ir
.nir
;
1797 unsigned urb_read_offset
, urb_read_length
;
1798 iris_compute_sbe_urb_read_interval(fs_nir
->info
.inputs_read
,
1799 ice
->shaders
.last_vue_map
,
1800 cso_rast
->light_twoside
,
1801 &urb_read_offset
, &urb_read_length
);
1803 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
1804 sbe
.AttributeSwizzleEnable
= true;
1805 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1806 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
1807 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
1808 sbe
.VertexURBEntryReadLength
= urb_read_length
;
1809 sbe
.ForceVertexURBEntryReadOffset
= true;
1810 sbe
.ForceVertexURBEntryReadLength
= true;
1811 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1813 for (int i
= 0; i
< 32; i
++) {
1814 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
1818 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
);
1822 iris_bind_compute_state(struct pipe_context
*ctx
, void *state
)
1827 iris_populate_sampler_key(const struct iris_context
*ice
,
1828 struct brw_sampler_prog_key_data
*key
)
1830 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
1831 key
->swizzles
[i
] = 0x688; /* XYZW */
1836 iris_populate_vs_key(const struct iris_context
*ice
,
1837 struct brw_vs_prog_key
*key
)
1839 memset(key
, 0, sizeof(*key
));
1840 iris_populate_sampler_key(ice
, &key
->tex
);
1844 iris_populate_tcs_key(const struct iris_context
*ice
,
1845 struct brw_tcs_prog_key
*key
)
1847 memset(key
, 0, sizeof(*key
));
1848 iris_populate_sampler_key(ice
, &key
->tex
);
1852 iris_populate_tes_key(const struct iris_context
*ice
,
1853 struct brw_tes_prog_key
*key
)
1855 memset(key
, 0, sizeof(*key
));
1856 iris_populate_sampler_key(ice
, &key
->tex
);
1860 iris_populate_gs_key(const struct iris_context
*ice
,
1861 struct brw_gs_prog_key
*key
)
1863 memset(key
, 0, sizeof(*key
));
1864 iris_populate_sampler_key(ice
, &key
->tex
);
1868 iris_populate_fs_key(const struct iris_context
*ice
,
1869 struct brw_wm_prog_key
*key
)
1871 memset(key
, 0, sizeof(*key
));
1872 iris_populate_sampler_key(ice
, &key
->tex
);
1874 /* XXX: dirty flags? */
1875 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
1876 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
1877 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
1878 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
1880 key
->nr_color_regions
= fb
->nr_cbufs
;
1882 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
1884 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
1885 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
1887 /* XXX: only bother if COL0/1 are read */
1888 key
->flat_shade
= rast
->flatshade
;
1890 // key->force_dual_color_blend for unigine
1892 if (cso_rast
->multisample
) {
1893 key
->persample_interp
=
1894 ctx
->Multisample
.SampleShading
&&
1895 (ctx
->Multisample
.MinSampleShadingValue
*
1896 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1);
1898 key
->multisample_fbo
= fb
->samples
> 1;
1902 key
->coherent_fb_fetch
= true;
1906 // XXX: these need to go in INIT_THREAD_DISPATCH_FIELDS
1907 pkt
.SamplerCount
= \
1908 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4); \
1909 pkt
.PerThreadScratchSpace
= prog_data
->total_scratch
== 0 ? 0 : \
1910 ffs(stage_state
->per_thread_scratch
) - 11; \
1915 KSP(const struct iris_compiled_shader
*shader
)
1917 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
1918 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
1921 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1922 pkt.KernelStartPointer = KSP(shader); \
1923 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
1924 pkt.FloatingPointMode = prog_data->use_alt_mode; \
1926 pkt.DispatchGRFStartRegisterForURBData = \
1927 prog_data->dispatch_grf_start_reg; \
1928 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1929 pkt.prefix##URBEntryReadOffset = 0; \
1931 pkt.StatisticsEnable = true; \
1935 iris_store_vs_state(const struct gen_device_info
*devinfo
,
1936 struct iris_compiled_shader
*shader
)
1938 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1939 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1941 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
1942 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1943 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1944 vs
.SIMD8DispatchEnable
= true;
1945 vs
.UserClipDistanceCullTestEnableBitmask
=
1946 vue_prog_data
->cull_distance_mask
;
1951 iris_store_tcs_state(const struct gen_device_info
*devinfo
,
1952 struct iris_compiled_shader
*shader
)
1954 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1955 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1956 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
1958 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
1959 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
1961 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
1962 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
1963 hs
.IncludeVertexHandles
= true;
1968 iris_store_tes_state(const struct gen_device_info
*devinfo
,
1969 struct iris_compiled_shader
*shader
)
1971 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1972 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1973 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
1975 uint32_t *te_state
= (void *) shader
->derived_data
;
1976 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
1978 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
1979 te
.Partitioning
= tes_prog_data
->partitioning
;
1980 te
.OutputTopology
= tes_prog_data
->output_topology
;
1981 te
.TEDomain
= tes_prog_data
->domain
;
1983 te
.MaximumTessellationFactorOdd
= 63.0;
1984 te
.MaximumTessellationFactorNotOdd
= 64.0;
1987 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
1988 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
1990 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
1991 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
1992 ds
.ComputeWCoordinateEnable
=
1993 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
1995 ds
.UserClipDistanceCullTestEnableBitmask
=
1996 vue_prog_data
->cull_distance_mask
;
2002 iris_store_gs_state(const struct gen_device_info
*devinfo
,
2003 struct iris_compiled_shader
*shader
)
2005 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2006 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2007 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
2009 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
2010 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2012 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2013 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2014 gs
.ControlDataHeaderSize
=
2015 gs_prog_data
->control_data_header_size_hwords
;
2016 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2017 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
2018 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2019 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2020 gs
.ReorderMode
= TRAILING
;
2021 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2022 gs
.MaximumNumberofThreads
=
2023 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2024 : (devinfo
->max_gs_threads
- 1);
2026 if (gs_prog_data
->static_vertex_count
!= -1) {
2027 gs
.StaticOutput
= true;
2028 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2030 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2032 gs
.UserClipDistanceCullTestEnableBitmask
=
2033 vue_prog_data
->cull_distance_mask
;
2035 const int urb_entry_write_offset
= 1;
2036 const uint32_t urb_entry_output_length
=
2037 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2038 urb_entry_write_offset
;
2040 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2041 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2046 iris_store_fs_state(const struct gen_device_info
*devinfo
,
2047 struct iris_compiled_shader
*shader
)
2049 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2050 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
2052 uint32_t *ps_state
= (void *) shader
->derived_data
;
2053 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
2055 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
2056 ps
.VectorMaskEnable
= true;
2057 //ps.SamplerCount = ...
2058 ps
.BindingTableEntryCount
= prog_data
->binding_table
.size_bytes
/ 4;
2059 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
2060 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
2062 ps
.PushConstantEnable
= prog_data
->nr_params
> 0 ||
2063 prog_data
->ubo_ranges
[0].length
> 0;
2065 /* From the documentation for this packet:
2066 * "If the PS kernel does not need the Position XY Offsets to
2067 * compute a Position Value, then this field should be programmed
2068 * to POSOFFSET_NONE."
2070 * "SW Recommendation: If the PS kernel needs the Position Offsets
2071 * to compute a Position XY value, this field should match Position
2072 * ZW Interpolation Mode to ensure a consistent position.xyzw
2075 * We only require XY sample offsets. So, this recommendation doesn't
2076 * look useful at the moment. We might need this in future.
2078 ps
.PositionXYOffsetSelect
=
2079 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
2080 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
2081 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
2082 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
2084 // XXX: Disable SIMD32 with 16x MSAA
2086 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
2087 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
2088 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
2089 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
2090 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
2091 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
2093 ps
.KernelStartPointer0
=
2094 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
2095 ps
.KernelStartPointer1
=
2096 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
2097 ps
.KernelStartPointer2
=
2098 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
2101 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
2102 psx
.PixelShaderValid
= true;
2103 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
2104 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
2105 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
2106 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
2107 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
2108 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
2110 if (wm_prog_data
->uses_sample_mask
) {
2111 /* TODO: conservative rasterization */
2112 if (wm_prog_data
->post_depth_coverage
)
2113 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
2115 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
2118 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
2119 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
2120 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
2127 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
2129 assert(cache_id
<= IRIS_CACHE_BLORP
);
2131 static const unsigned dwords
[] = {
2132 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
2133 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
2134 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
2135 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
2137 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
2138 [IRIS_CACHE_CS
] = 0,
2139 [IRIS_CACHE_BLORP
] = 0,
2142 return sizeof(uint32_t) * dwords
[cache_id
];
2146 iris_store_derived_program_state(const struct gen_device_info
*devinfo
,
2147 enum iris_program_cache_id cache_id
,
2148 struct iris_compiled_shader
*shader
)
2152 iris_store_vs_state(devinfo
, shader
);
2154 case IRIS_CACHE_TCS
:
2155 iris_store_tcs_state(devinfo
, shader
);
2157 case IRIS_CACHE_TES
:
2158 iris_store_tes_state(devinfo
, shader
);
2161 iris_store_gs_state(devinfo
, shader
);
2164 iris_store_fs_state(devinfo
, shader
);
2167 case IRIS_CACHE_BLORP
:
2175 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
2177 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
2178 const unsigned push_size_kB
= 32;
2179 unsigned entries
[4];
2183 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2184 if (!ice
->shaders
.prog
[i
]) {
2187 struct brw_vue_prog_data
*vue_prog_data
=
2188 (void *) ice
->shaders
.prog
[i
]->prog_data
;
2189 size
[i
] = vue_prog_data
->urb_entry_size
;
2191 assert(size
[i
] != 0);
2194 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
2195 1024 * ice
->shaders
.urb_size
,
2196 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
2197 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
2198 size
, entries
, start
);
2200 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2201 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
2202 urb
._3DCommandSubOpcode
+= i
;
2203 urb
.VSURBStartingAddress
= start
[i
];
2204 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
2205 urb
.VSNumberofURBEntries
= entries
[i
];
2210 static const uint32_t push_constant_opcodes
[] = {
2211 [MESA_SHADER_VERTEX
] = 21,
2212 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2213 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2214 [MESA_SHADER_GEOMETRY
] = 22,
2215 [MESA_SHADER_FRAGMENT
] = 23,
2216 [MESA_SHADER_COMPUTE
] = 0,
2220 * Add a surface to the validation list, as well as the buffer containing
2221 * the corresponding SURFACE_STATE.
2223 * Returns the binding table entry (offset to SURFACE_STATE).
2226 use_surface(struct iris_batch
*batch
,
2227 struct pipe_surface
*p_surf
,
2230 struct iris_surface
*surf
= (void *) p_surf
;
2232 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
2233 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
2235 return surf
->surface_state
.offset
;
2239 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
2241 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->pipe
.texture
), false);
2242 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
2244 return isv
->surface_state
.offset
;
2248 use_const_buffer(struct iris_batch
*batch
, struct iris_const_buffer
*cbuf
)
2250 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->data
.res
), false);
2251 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->surface_state
.res
), false);
2253 return cbuf
->surface_state
.offset
;
2257 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
2259 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
2261 iris_use_pinned_bo(batch
, state_bo
, false);
2263 return ice
->state
.unbound_tex
.offset
;
2267 iris_populate_binding_table(struct iris_context
*ice
,
2268 struct iris_batch
*batch
,
2269 gl_shader_stage stage
)
2271 const struct iris_binder
*binder
= &batch
->binder
;
2272 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2278 // - ubos/ssbos/abos
2281 // - render targets - write and read
2283 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
2284 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
2287 if (stage
== MESA_SHADER_FRAGMENT
) {
2288 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2289 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
2290 bt_map
[s
++] = use_surface(batch
, cso_fb
->cbufs
[i
], true);
2294 //assert(prog_data->binding_table.texture_start ==
2295 //(ice->state.num_textures[stage] ? s : 0xd0d0d0d0));
2297 for (int i
= 0; i
< ice
->state
.num_textures
[stage
]; i
++) {
2298 struct iris_sampler_view
*view
= ice
->state
.textures
[stage
][i
];
2299 bt_map
[s
++] = view
? use_sampler_view(batch
, view
)
2300 : use_null_surface(batch
, ice
);
2303 // XXX: want the number of BTE's to shorten this loop
2304 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2305 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
2306 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[i
];
2307 if (!cbuf
->surface_state
.res
)
2310 bt_map
[s
++] = use_const_buffer(batch
, cbuf
);
2313 // XXX: not implemented yet
2314 assert(prog_data
->binding_table
.pull_constants_start
== 0xd0d0d0d0);
2315 assert(prog_data
->binding_table
.ubo_start
== 0xd0d0d0d0);
2316 assert(prog_data
->binding_table
.ssbo_start
== 0xd0d0d0d0);
2317 assert(prog_data
->binding_table
.image_start
== 0xd0d0d0d0);
2318 assert(prog_data
->binding_table
.shader_time_start
== 0xd0d0d0d0);
2319 //assert(prog_data->binding_table.plane_start[1] == 0xd0d0d0d0);
2320 //assert(prog_data->binding_table.plane_start[2] == 0xd0d0d0d0);
2325 iris_use_optional_res(struct iris_batch
*batch
,
2326 struct pipe_resource
*res
,
2330 struct iris_bo
*bo
= iris_resource_bo(res
);
2331 iris_use_pinned_bo(batch
, bo
, writeable
);
2337 * Pin any BOs which were installed by a previous batch, and restored
2338 * via the hardware logical context mechanism.
2340 * We don't need to re-emit all state every batch - the hardware context
2341 * mechanism will save and restore it for us. This includes pointers to
2342 * various BOs...which won't exist unless we ask the kernel to pin them
2343 * by adding them to the validation list.
2345 * We can skip buffers if we've re-emitted those packets, as we're
2346 * overwriting those stale pointers with new ones, and don't actually
2347 * refer to the old BOs.
2350 iris_restore_context_saved_bos(struct iris_context
*ice
,
2351 struct iris_batch
*batch
,
2352 const struct pipe_draw_info
*draw
)
2354 // XXX: whack IRIS_SHADER_DIRTY_BINDING_TABLE on new batch
2356 const uint64_t clean
= ~ice
->state
.dirty
;
2358 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
2359 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
2362 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
2363 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
2366 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
2367 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
2370 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
2371 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
2374 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
2375 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
2378 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2379 if (clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
))
2382 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2383 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2388 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
2390 for (int i
= 0; i
< 4; i
++) {
2391 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2393 if (range
->length
== 0)
2396 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
2397 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2400 iris_use_pinned_bo(batch
, res
->bo
, false);
2402 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
2406 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2407 struct pipe_resource
*res
= ice
->state
.sampler_table
[stage
].res
;
2409 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
2412 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2413 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
2414 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2416 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
2417 iris_use_pinned_bo(batch
, bo
, false);
2420 // XXX: scratch buffer
2424 // XXX: 3DSTATE_SO_BUFFER
2426 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
2427 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2429 if (cso_fb
->zsbuf
) {
2430 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
2431 // XXX: depth might not be writable...
2432 iris_use_pinned_bo(batch
, zres
->bo
, true);
2436 if (draw
->index_size
> 0) {
2437 // XXX: index buffer
2440 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
2441 struct iris_vertex_buffer_state
*cso
= ice
->state
.cso_vertex_buffers
;
2442 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
2443 struct iris_resource
*res
= (void *) cso
->resources
[i
];
2444 iris_use_pinned_bo(batch
, res
->bo
, false);
2450 iris_upload_render_state(struct iris_context
*ice
,
2451 struct iris_batch
*batch
,
2452 const struct pipe_draw_info
*draw
)
2454 const uint64_t dirty
= ice
->state
.dirty
;
2456 struct brw_wm_prog_data
*wm_prog_data
= (void *)
2457 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2459 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
2460 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2461 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2462 ptr
.CCViewportPointer
=
2463 emit_state(batch
, ice
->state
.dynamic_uploader
,
2464 &ice
->state
.last_res
.cc_vp
,
2465 cso
->cc_vp
, sizeof(cso
->cc_vp
), 32);
2469 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
2470 struct iris_viewport_state
*cso
= ice
->state
.cso_vp
;
2471 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2472 ptr
.SFClipViewportPointer
=
2473 emit_state(batch
, ice
->state
.dynamic_uploader
,
2474 &ice
->state
.last_res
.sf_cl_vp
,
2475 cso
->sf_cl_vp
, 4 * GENX(SF_CLIP_VIEWPORT_length
) *
2476 ice
->state
.num_viewports
, 64);
2482 // XXX: this is only flagged at setup, we assume a static configuration
2483 if (dirty
& IRIS_DIRTY_URB
) {
2484 iris_upload_urb_config(ice
, batch
);
2487 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
2488 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2489 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2490 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2491 const int num_dwords
= 4 * (GENX(BLEND_STATE_length
) +
2492 cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
));
2493 uint32_t blend_offset
;
2494 uint32_t *blend_map
=
2495 stream_state(batch
, ice
->state
.dynamic_uploader
,
2496 &ice
->state
.last_res
.blend
,
2497 4 * num_dwords
, 64, &blend_offset
);
2499 uint32_t blend_state_header
;
2500 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
2501 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2502 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
2505 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
2506 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1],
2507 sizeof(cso_blend
->blend_state
) - sizeof(uint32_t));
2509 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2510 ptr
.BlendStatePointer
= blend_offset
;
2511 ptr
.BlendStatePointerValid
= true;
2515 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
2516 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2519 stream_state(batch
, ice
->state
.dynamic_uploader
,
2520 &ice
->state
.last_res
.color_calc
,
2521 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
2523 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
2524 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
2525 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
2526 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
2527 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
2528 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
2529 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
2531 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2532 ptr
.ColorCalcStatePointer
= cc_offset
;
2533 ptr
.ColorCalcStatePointerValid
= true;
2537 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2538 // XXX: wrong dirty tracking...
2539 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
2542 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2543 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2548 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
2550 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2551 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2553 /* The Skylake PRM contains the following restriction:
2555 * "The driver must ensure The following case does not occur
2556 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2557 * buffer 3 read length equal to zero committed followed by a
2558 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2561 * To avoid this, we program the buffers in the highest slots.
2562 * This way, slot 0 is only used if slot 3 is also used.
2566 for (int i
= 3; i
>= 0; i
--) {
2567 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2569 if (range
->length
== 0)
2572 // XXX: is range->block a constbuf index? it would be nice
2573 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
2574 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2576 assert(cbuf
->data
.offset
% 32 == 0);
2578 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
2579 pkt
.ConstantBody
.Buffer
[n
] =
2580 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->data
.offset
)
2581 : ro_bo(batch
->screen
->workaround_bo
, 0);
2588 struct iris_binder
*binder
= &batch
->binder
;
2590 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2591 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
2592 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
2593 ptr
._3DCommandSubOpcode
= 38 + stage
;
2594 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
2599 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2600 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
2601 iris_populate_binding_table(ice
, batch
, stage
);
2605 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2606 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
2607 !ice
->shaders
.prog
[stage
])
2610 struct pipe_resource
*res
= ice
->state
.sampler_table
[stage
].res
;
2612 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
2614 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
2615 ptr
._3DCommandSubOpcode
= 43 + stage
;
2616 ptr
.PointertoVSSamplerState
= ice
->state
.sampler_table
[stage
].offset
;
2620 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
2621 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
2623 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
2624 if (ice
->state
.framebuffer
.samples
> 0)
2625 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
2629 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
2630 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
2631 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
2635 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2636 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
2639 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2642 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
2643 iris_use_pinned_bo(batch
, cache
->bo
, false);
2644 iris_batch_emit(batch
, shader
->derived_data
,
2645 iris_derived_program_state_size(stage
));
2647 if (stage
== MESA_SHADER_TESS_EVAL
) {
2648 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
2649 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
2650 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
2651 } else if (stage
== MESA_SHADER_GEOMETRY
) {
2652 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
2658 // 3DSTATE_STREAMOUT
2659 // 3DSTATE_SO_BUFFER
2660 // 3DSTATE_SO_DECL_LIST
2662 if (dirty
& IRIS_DIRTY_CLIP
) {
2663 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2664 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2666 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
2667 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
2668 if (wm_prog_data
->barycentric_interp_modes
&
2669 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
2670 cl
.NonPerspectiveBarycentricEnable
= true;
2672 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
2673 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
2675 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
2676 ARRAY_SIZE(cso_rast
->clip
));
2679 if (dirty
& IRIS_DIRTY_RASTER
) {
2680 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2681 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
2682 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
2686 /* XXX: FS program updates needs to flag IRIS_DIRTY_WM */
2687 if (dirty
& IRIS_DIRTY_WM
) {
2688 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2689 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
2691 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
2692 wm
.BarycentricInterpolationMode
=
2693 wm_prog_data
->barycentric_interp_modes
;
2695 if (wm_prog_data
->early_fragment_tests
)
2696 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
2697 else if (wm_prog_data
->has_side_effects
)
2698 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
2700 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
2704 // XXX: 3DSTATE_SBE, 3DSTATE_SBE_SWIZ
2705 // -> iris_raster_state (point sprite texture coordinate origin)
2706 // -> bunch of shader state...
2707 iris_emit_sbe(batch
, ice
);
2710 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
2711 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2712 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2713 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
2714 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
2715 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
2716 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2719 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
2720 ARRAY_SIZE(cso_blend
->ps_blend
));
2723 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
2724 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2725 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
2727 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
2728 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
2729 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
2730 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
2732 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
2735 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
2736 uint32_t scissor_offset
=
2737 emit_state(batch
, ice
->state
.dynamic_uploader
,
2738 &ice
->state
.last_res
.scissor
,
2739 ice
->state
.scissors
,
2740 sizeof(struct pipe_scissor_state
) *
2741 ice
->state
.num_viewports
, 32);
2743 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2744 ptr
.ScissorRectPointer
= scissor_offset
;
2748 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
2749 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2750 struct iris_depth_buffer_state
*cso_z
= ice
->state
.cso_depthbuffer
;
2752 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
2754 if (cso_fb
->zsbuf
) {
2755 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
2756 // XXX: depth might not be writable...
2757 iris_use_pinned_bo(batch
, zres
->bo
, true);
2761 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
2762 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
2763 for (int i
= 0; i
< 32; i
++) {
2764 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
2769 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
2770 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2771 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
2775 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
2776 topo
.PrimitiveTopologyType
=
2777 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
2781 if (draw
->index_size
> 0) {
2782 struct iris_resource
*res
= NULL
;
2785 if (draw
->has_user_indices
) {
2786 u_upload_data(ice
->ctx
.stream_uploader
, 0,
2787 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
2788 &offset
, (struct pipe_resource
**) &res
);
2790 res
= (struct iris_resource
*) draw
->index
.resource
;
2794 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
2795 ib
.IndexFormat
= draw
->index_size
>> 1;
2797 ib
.BufferSize
= res
->bo
->size
;
2798 ib
.BufferStartingAddress
= ro_bo(res
->bo
, offset
);
2802 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
2803 struct iris_vertex_buffer_state
*cso
= ice
->state
.cso_vertex_buffers
;
2804 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
2806 if (cso
->num_buffers
> 0) {
2807 iris_batch_emit(batch
, cso
->vertex_buffers
, sizeof(uint32_t) *
2808 (1 + vb_dwords
* cso
->num_buffers
));
2810 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
2811 struct iris_resource
*res
= (void *) cso
->resources
[i
];
2812 iris_use_pinned_bo(batch
, res
->bo
, false);
2817 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
2818 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
2819 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
2820 (1 + cso
->count
* GENX(VERTEX_ELEMENT_STATE_length
)));
2821 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
2822 cso
->count
* GENX(3DSTATE_VF_INSTANCING_length
));
2823 for (int i
= 0; i
< cso
->count
; i
++) {
2824 /* TODO: vertexid, instanceid support */
2825 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
);
2830 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
2831 if (draw
->primitive_restart
) {
2832 vf
.IndexedDrawCutIndexEnable
= true;
2833 vf
.CutIndex
= draw
->restart_index
;
2838 // XXX: Gen8 - PMA fix
2840 assert(!draw
->indirect
); // XXX: indirect support
2842 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
2843 prim
.StartInstanceLocation
= draw
->start_instance
;
2844 prim
.InstanceCount
= draw
->instance_count
;
2845 prim
.VertexCountPerInstance
= draw
->count
;
2846 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
2848 // XXX: this is probably bonkers.
2849 prim
.StartVertexLocation
= draw
->start
;
2851 if (draw
->index_size
) {
2852 prim
.BaseVertexLocation
+= draw
->index_bias
;
2854 prim
.StartVertexLocation
+= draw
->index_bias
;
2857 //prim.BaseVertexLocation = ...;
2860 if (!batch
->contains_draw
) {
2861 iris_restore_context_saved_bos(ice
, batch
, draw
);
2862 batch
->contains_draw
= true;
2867 * State module teardown.
2870 iris_destroy_state(struct iris_context
*ice
)
2872 iris_free_vertex_buffers(ice
->state
.cso_vertex_buffers
);
2874 // XXX: unreference resources/surfaces.
2875 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
2876 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
2878 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
2880 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
2881 pipe_resource_reference(&ice
->state
.sampler_table
[stage
].res
, NULL
);
2883 free(ice
->state
.cso_vp
);
2884 free(ice
->state
.cso_depthbuffer
);
2886 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
2887 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
2888 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
2889 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
2890 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
2894 flags_to_post_sync_op(uint32_t flags
)
2896 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
2897 return WriteImmediateData
;
2899 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
2900 return WritePSDepthCount
;
2902 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
2903 return WriteTimestamp
;
2909 * Do the given flags have a Post Sync or LRI Post Sync operation?
2911 static enum pipe_control_flags
2912 get_post_sync_flags(enum pipe_control_flags flags
)
2914 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
2915 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2916 PIPE_CONTROL_WRITE_TIMESTAMP
|
2917 PIPE_CONTROL_LRI_POST_SYNC_OP
;
2919 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
2920 * "LRI Post Sync Operation". So more than one bit set would be illegal.
2922 assert(util_bitcount(flags
) <= 1);
2927 // XXX: compute support
2928 #define IS_COMPUTE_PIPELINE(batch) (batch->ring != I915_EXEC_RENDER)
2931 * Emit a series of PIPE_CONTROL commands, taking into account any
2932 * workarounds necessary to actually accomplish the caller's request.
2934 * Unless otherwise noted, spec quotations in this function come from:
2936 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
2937 * Restrictions for PIPE_CONTROL.
2940 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
2941 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
2943 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
2944 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
2945 enum pipe_control_flags non_lri_post_sync_flags
=
2946 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
2948 /* Recursive PIPE_CONTROL workarounds --------------------------------
2949 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
2951 * We do these first because we want to look at the original operation,
2952 * rather than any workarounds we set.
2954 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
2955 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
2956 * lists several workarounds:
2958 * "Project: SKL, KBL, BXT
2960 * If the VF Cache Invalidation Enable is set to a 1 in a
2961 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
2962 * sets to 0, with the VF Cache Invalidation Enable set to 0
2963 * needs to be sent prior to the PIPE_CONTROL with VF Cache
2964 * Invalidation Enable set to a 1."
2966 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
2969 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
2970 /* Project: SKL / Argument: LRI Post Sync Operation [23]
2972 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2973 * programmed prior to programming a PIPECONTROL command with "LRI
2974 * Post Sync Operation" in GPGPU mode of operation (i.e when
2975 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2977 * The same text exists a few rows below for Post Sync Op.
2979 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
2982 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
2984 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
2985 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
2986 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
2988 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
2992 /* "Flush Types" workarounds ---------------------------------------------
2993 * We do these now because they may add post-sync operations or CS stalls.
2996 if (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
2997 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
2999 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
3000 * 'Write PS Depth Count' or 'Write Timestamp'."
3003 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3004 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3005 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3006 bo
= batch
->screen
->workaround_bo
;
3010 /* #1130 from Gen10 workarounds page:
3012 * "Enable Depth Stall on every Post Sync Op if Render target Cache
3013 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
3014 * board stall if Render target cache flush is enabled."
3016 * Applicable to CNL B0 and C0 steppings only.
3018 * The wording here is unclear, and this workaround doesn't look anything
3019 * like the internal bug report recommendations, but leave it be for now...
3021 if (GEN_GEN
== 10) {
3022 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
3023 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
3024 } else if (flags
& non_lri_post_sync_flags
) {
3025 flags
|= PIPE_CONTROL_DEPTH_STALL
;
3029 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
3030 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
3032 * "This bit must be DISABLED for operations other than writing
3035 * This seems like nonsense. An Ivybridge workaround requires us to
3036 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
3037 * operation. Gen8+ requires us to emit depth stalls and depth cache
3038 * flushes together. So, it's hard to imagine this means anything other
3039 * than "we originally intended this to be used for PS_DEPTH_COUNT".
3041 * We ignore the supposed restriction and do nothing.
3045 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
3046 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
3047 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
3049 * "This bit must be DISABLED for End-of-pipe (Read) fences,
3050 * PS_DEPTH_COUNT or TIMESTAMP queries."
3052 * TODO: Implement end-of-pipe checking.
3054 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
3055 PIPE_CONTROL_WRITE_TIMESTAMP
)));
3058 if (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) {
3059 /* From the PIPE_CONTROL instruction table, bit 1:
3061 * "This bit is ignored if Depth Stall Enable is set.
3062 * Further, the render cache is not flushed even if Write Cache
3063 * Flush Enable bit is set."
3065 * We assert that the caller doesn't do this combination, to try and
3066 * prevent mistakes. It shouldn't hurt the GPU, though.
3068 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
3069 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
3072 /* PIPE_CONTROL page workarounds ------------------------------------- */
3074 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
3075 /* From the PIPE_CONTROL page itself:
3078 * Restriction: Pipe_control with CS-stall bit set must be issued
3079 * before a pipe-control command that has the State Cache
3080 * Invalidate bit set."
3082 flags
|= PIPE_CONTROL_CS_STALL
;
3085 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
3086 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
3089 * SW must always program Post-Sync Operation to "Write Immediate
3090 * Data" when Flush LLC is set."
3092 * For now, we just require the caller to do it.
3094 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
3097 /* "Post-Sync Operation" workarounds -------------------------------- */
3099 /* Project: All / Argument: Global Snapshot Count Reset [19]
3101 * "This bit must not be exercised on any product.
3102 * Requires stall bit ([20] of DW1) set."
3104 * We don't use this, so we just assert that it isn't used. The
3105 * PIPE_CONTROL instruction page indicates that they intended this
3106 * as a debug feature and don't think it is useful in production,
3107 * but it may actually be usable, should we ever want to.
3109 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
3111 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
3112 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
3113 /* Project: All / Arguments:
3115 * - Generic Media State Clear [16]
3116 * - Indirect State Pointers Disable [16]
3118 * "Requires stall bit ([20] of DW1) set."
3120 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
3121 * State Clear) says:
3123 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
3124 * programmed prior to programming a PIPECONTROL command with "Media
3125 * State Clear" set in GPGPU mode of operation"
3127 * This is a subset of the earlier rule, so there's nothing to do.
3129 flags
|= PIPE_CONTROL_CS_STALL
;
3132 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
3133 /* Project: All / Argument: Store Data Index
3135 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
3138 * For now, we just assert that the caller does this. We might want to
3139 * automatically add a write to the workaround BO...
3141 assert(non_lri_post_sync_flags
!= 0);
3144 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
3145 /* Project: All / Argument: Sync GFDT
3147 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
3148 * than '0' or 0x2520[13] must be set."
3150 * For now, we just assert that the caller does this.
3152 assert(non_lri_post_sync_flags
!= 0);
3155 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
3156 /* Project: IVB+ / Argument: TLB inv
3158 * "Requires stall bit ([20] of DW1) set."
3160 * Also, from the PIPE_CONTROL instruction table:
3163 * Post Sync Operation or CS stall must be set to ensure a TLB
3164 * invalidation occurs. Otherwise no cycle will occur to the TLB
3165 * cache to invalidate."
3167 * This is not a subset of the earlier rule, so there's nothing to do.
3169 flags
|= PIPE_CONTROL_CS_STALL
;
3172 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
3173 /* TODO: The big Skylake GT4 post sync op workaround */
3176 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
3178 if (IS_COMPUTE_PIPELINE(batch
)) {
3179 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
3180 /* Project: SKL+ / Argument: Tex Invalidate
3181 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
3183 flags
|= PIPE_CONTROL_CS_STALL
;
3186 if (GEN_GEN
== 8 && (post_sync_flags
||
3187 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
3188 PIPE_CONTROL_DEPTH_STALL
|
3189 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
3190 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
3191 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
3192 /* Project: BDW / Arguments:
3194 * - LRI Post Sync Operation [23]
3195 * - Post Sync Op [15:14]
3197 * - Depth Stall [13]
3198 * - Render Target Cache Flush [12]
3199 * - Depth Cache Flush [0]
3200 * - DC Flush Enable [5]
3202 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
3205 flags
|= PIPE_CONTROL_CS_STALL
;
3207 /* Also, from the PIPE_CONTROL instruction table, bit 20:
3210 * This bit must be always set when PIPE_CONTROL command is
3211 * programmed by GPGPU and MEDIA workloads, except for the cases
3212 * when only Read Only Cache Invalidation bits are set (State
3213 * Cache Invalidation Enable, Instruction cache Invalidation
3214 * Enable, Texture Cache Invalidation Enable, Constant Cache
3215 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
3216 * need not implemented when FF_DOP_CG is disable via "Fixed
3217 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
3219 * It sounds like we could avoid CS stalls in some cases, but we
3220 * don't currently bother. This list isn't exactly the list above,
3226 /* "Stall" workarounds ----------------------------------------------
3227 * These have to come after the earlier ones because we may have added
3228 * some additional CS stalls above.
3231 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
3232 /* Project: PRE-SKL, VLV, CHV
3234 * "[All Stepping][All SKUs]:
3236 * One of the following must also be set:
3238 * - Render Target Cache Flush Enable ([12] of DW1)
3239 * - Depth Cache Flush Enable ([0] of DW1)
3240 * - Stall at Pixel Scoreboard ([1] of DW1)
3241 * - Depth Stall ([13] of DW1)
3242 * - Post-Sync Operation ([13] of DW1)
3243 * - DC Flush Enable ([5] of DW1)"
3245 * If we don't already have one of those bits set, we choose to add
3246 * "Stall at Pixel Scoreboard". Some of the other bits require a
3247 * CS stall as a workaround (see above), which would send us into
3248 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
3249 * appears to be safe, so we choose that.
3251 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
3252 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
3253 PIPE_CONTROL_WRITE_IMMEDIATE
|
3254 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
3255 PIPE_CONTROL_WRITE_TIMESTAMP
|
3256 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
3257 PIPE_CONTROL_DEPTH_STALL
|
3258 PIPE_CONTROL_DATA_CACHE_FLUSH
;
3259 if (!(flags
& wa_bits
))
3260 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
3263 /* Emit --------------------------------------------------------------- */
3265 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
3266 pc
.LRIPostSyncOperation
= NoLRIOperation
;
3267 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
3268 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
3269 pc
.StoreDataIndex
= 0;
3270 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
3271 pc
.GlobalSnapshotCountReset
=
3272 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
3273 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
3274 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
3275 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
3276 pc
.RenderTargetCacheFlushEnable
=
3277 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
3278 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
3279 pc
.StateCacheInvalidationEnable
=
3280 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
3281 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
3282 pc
.ConstantCacheInvalidationEnable
=
3283 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
3284 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
3285 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
3286 pc
.InstructionCacheInvalidateEnable
=
3287 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
3288 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
3289 pc
.IndirectStatePointersDisable
=
3290 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
3291 pc
.TextureCacheInvalidationEnable
=
3292 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
3293 pc
.Address
= ro_bo(bo
, offset
);
3294 pc
.ImmediateData
= imm
;
3299 genX(init_state
)(struct iris_context
*ice
)
3301 struct pipe_context
*ctx
= &ice
->ctx
;
3302 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
3304 ctx
->create_blend_state
= iris_create_blend_state
;
3305 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
3306 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
3307 ctx
->create_sampler_state
= iris_create_sampler_state
;
3308 ctx
->create_sampler_view
= iris_create_sampler_view
;
3309 ctx
->create_surface
= iris_create_surface
;
3310 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
3311 ctx
->create_compute_state
= iris_create_compute_state
;
3312 ctx
->bind_blend_state
= iris_bind_blend_state
;
3313 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
3314 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
3315 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
3316 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
3317 ctx
->bind_compute_state
= iris_bind_compute_state
;
3318 ctx
->delete_blend_state
= iris_delete_state
;
3319 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
3320 ctx
->delete_fs_state
= iris_delete_state
;
3321 ctx
->delete_rasterizer_state
= iris_delete_state
;
3322 ctx
->delete_sampler_state
= iris_delete_state
;
3323 ctx
->delete_vertex_elements_state
= iris_delete_state
;
3324 ctx
->delete_compute_state
= iris_delete_state
;
3325 ctx
->delete_tcs_state
= iris_delete_state
;
3326 ctx
->delete_tes_state
= iris_delete_state
;
3327 ctx
->delete_gs_state
= iris_delete_state
;
3328 ctx
->delete_vs_state
= iris_delete_state
;
3329 ctx
->set_blend_color
= iris_set_blend_color
;
3330 ctx
->set_clip_state
= iris_set_clip_state
;
3331 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
3332 ctx
->set_sampler_views
= iris_set_sampler_views
;
3333 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
3334 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
3335 ctx
->set_sample_mask
= iris_set_sample_mask
;
3336 ctx
->set_scissor_states
= iris_set_scissor_states
;
3337 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
3338 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
3339 ctx
->set_viewport_states
= iris_set_viewport_states
;
3340 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
3341 ctx
->surface_destroy
= iris_surface_destroy
;
3342 ctx
->draw_vbo
= iris_draw_vbo
;
3343 ctx
->launch_grid
= iris_launch_grid
;
3344 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
3345 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
3346 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
3348 ice
->vtbl
.destroy_state
= iris_destroy_state
;
3349 ice
->vtbl
.init_render_context
= iris_init_render_context
;
3350 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
3351 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
3352 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
3353 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
3354 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
3355 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
3356 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
3357 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
3358 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
3360 ice
->state
.dirty
= ~0ull;
3362 ice
->state
.num_viewports
= 1;
3363 ice
->state
.cso_vp
= calloc(1, sizeof(struct iris_viewport_state
));
3364 ice
->state
.cso_vertex_buffers
=
3365 calloc(1, sizeof(struct iris_vertex_buffer_state
));
3367 /* Make a 1x1x1 null surface for unbound textures */
3368 void *null_surf_map
=
3369 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
3370 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
3371 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));