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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_inlines.h"
92 #include "util/u_format.h"
93 #include "util/u_framebuffer.h"
94 #include "util/u_transfer.h"
95 #include "util/u_upload_mgr.h"
96 #include "util/u_viewport.h"
99 #include "intel/compiler/brw_compiler.h"
100 #include "intel/common/gen_l3_config.h"
101 #include "intel/common/gen_sample_positions.h"
102 #include "iris_batch.h"
103 #include "iris_context.h"
104 #include "iris_pipe.h"
105 #include "iris_resource.h"
107 #define __gen_address_type struct iris_address
108 #define __gen_user_data struct iris_batch
110 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
113 __gen_combine_address(struct iris_batch
*batch
, void *location
,
114 struct iris_address addr
, uint32_t delta
)
116 uint64_t result
= addr
.offset
+ delta
;
119 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
120 /* Assume this is a general address, not relative to a base. */
121 result
+= addr
.bo
->gtt_offset
;
127 #define __genxml_cmd_length(cmd) cmd ## _length
128 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
129 #define __genxml_cmd_header(cmd) cmd ## _header
130 #define __genxml_cmd_pack(cmd) cmd ## _pack
132 #define _iris_pack_command(batch, cmd, dst, name) \
133 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
134 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
135 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
139 #define iris_pack_command(cmd, dst, name) \
140 _iris_pack_command(NULL, cmd, dst, name)
142 #define iris_pack_state(cmd, dst, name) \
143 for (struct cmd name = {}, \
144 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
145 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
148 #define iris_emit_cmd(batch, cmd, name) \
149 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
151 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
153 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
154 for (uint32_t i = 0; i < num_dwords; i++) \
155 dw[i] = (dwords0)[i] | (dwords1)[i]; \
156 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
159 #include "genxml/genX_pack.h"
160 #include "genxml/gen_macros.h"
161 #include "genxml/genX_bits.h"
163 #define MOCS_WB (2 << 1)
166 * Statically assert that PIPE_* enums match the hardware packets.
167 * (As long as they match, we don't need to translate them.)
169 UNUSED
static void pipe_asserts()
171 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
173 /* pipe_logicop happens to match the hardware. */
174 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
175 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
176 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
177 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
178 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
179 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
180 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
181 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
182 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
183 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
184 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
185 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
186 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
187 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
188 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
189 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
191 /* pipe_blend_func happens to match the hardware. */
192 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
193 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
194 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
195 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
196 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
197 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
198 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
199 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
200 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
201 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
202 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
203 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
204 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
205 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
206 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
207 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
212 /* pipe_blend_func happens to match the hardware. */
213 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
214 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
215 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
216 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
217 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
219 /* pipe_stencil_op happens to match the hardware. */
220 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
221 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
222 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
223 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
224 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
225 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
226 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
227 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
229 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
230 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
231 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
236 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
238 static const unsigned map
[] = {
239 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
240 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
241 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
242 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
243 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
244 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
245 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
246 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
247 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
248 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
249 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
250 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
251 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
252 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
253 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
256 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
260 translate_compare_func(enum pipe_compare_func pipe_func
)
262 static const unsigned map
[] = {
263 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
264 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
265 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
266 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
267 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
268 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
269 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
270 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
272 return map
[pipe_func
];
276 translate_shadow_func(enum pipe_compare_func pipe_func
)
278 /* Gallium specifies the result of shadow comparisons as:
280 * 1 if ref <op> texel,
285 * 0 if texel <op> ref,
288 * So we need to flip the operator and also negate.
290 static const unsigned map
[] = {
291 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
292 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
293 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
294 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
295 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
296 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
297 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
298 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
300 return map
[pipe_func
];
304 translate_cull_mode(unsigned pipe_face
)
306 static const unsigned map
[4] = {
307 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
308 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
309 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
310 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
312 return map
[pipe_face
];
316 translate_fill_mode(unsigned pipe_polymode
)
318 static const unsigned map
[4] = {
319 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
320 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
321 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
322 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
324 return map
[pipe_polymode
];
328 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
330 static const unsigned map
[] = {
331 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
332 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
333 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
335 return map
[pipe_mip
];
339 translate_wrap(unsigned pipe_wrap
)
341 static const unsigned map
[] = {
342 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
343 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
344 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
345 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
346 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
347 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
349 /* These are unsupported. */
350 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
351 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
353 return map
[pipe_wrap
];
356 static struct iris_address
357 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
359 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
360 * validation list at CSO creation time, instead of draw time.
362 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
365 static struct iris_address
366 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
368 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
369 * validation list at CSO creation time, instead of draw time.
371 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
375 * Allocate space for some indirect state.
377 * Return a pointer to the map (to fill it out) and a state ref (for
378 * referring to the state in GPU commands).
381 upload_state(struct u_upload_mgr
*uploader
,
382 struct iris_state_ref
*ref
,
387 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
392 * Stream out temporary/short-lived state.
394 * This allocates space, pins the BO, and includes the BO address in the
395 * returned offset (which works because all state lives in 32-bit memory
399 stream_state(struct iris_batch
*batch
,
400 struct u_upload_mgr
*uploader
,
401 struct pipe_resource
**out_res
,
404 uint32_t *out_offset
)
408 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
410 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
411 iris_use_pinned_bo(batch
, bo
, false);
413 *out_offset
+= iris_bo_offset_from_base_address(bo
);
419 * stream_state() + memcpy.
422 emit_state(struct iris_batch
*batch
,
423 struct u_upload_mgr
*uploader
,
424 struct pipe_resource
**out_res
,
431 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
434 memcpy(map
, data
, size
);
440 * Did field 'x' change between 'old_cso' and 'new_cso'?
442 * (If so, we may want to set some dirty flags.)
444 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
445 #define cso_changed_memcmp(x) \
446 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
449 flush_for_state_base_change(struct iris_batch
*batch
)
451 /* Flush before emitting STATE_BASE_ADDRESS.
453 * This isn't documented anywhere in the PRM. However, it seems to be
454 * necessary prior to changing the surface state base adress. We've
455 * seen issues in Vulkan where we get GPU hangs when using multi-level
456 * command buffers which clear depth, reset state base address, and then
459 * Normally, in GL, we would trust the kernel to do sufficient stalls
460 * and flushes prior to executing our batch. However, it doesn't seem
461 * as if the kernel's flushing is always sufficient and we don't want to
464 * We make this an end-of-pipe sync instead of a normal flush because we
465 * do not know the current status of the GPU. On Haswell at least,
466 * having a fast-clear operation in flight at the same time as a normal
467 * rendering operation can cause hangs. Since the kernel's flushing is
468 * insufficient, we need to ensure that any rendering operations from
469 * other processes are definitely complete before we try to do our own
470 * rendering. It's a bit of a big hammer but it appears to work.
472 iris_emit_end_of_pipe_sync(batch
,
473 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
474 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
475 PIPE_CONTROL_DATA_CACHE_FLUSH
);
479 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
481 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
482 lri
.RegisterOffset
= reg
;
486 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
489 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
491 #if GEN_GEN >= 8 && GEN_GEN < 10
492 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
494 * Software must clear the COLOR_CALC_STATE Valid field in
495 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
496 * with Pipeline Select set to GPGPU.
498 * The internal hardware docs recommend the same workaround for Gen9
501 if (pipeline
== GPGPU
)
502 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
506 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
507 * PIPELINE_SELECT [DevBWR+]":
511 * Software must ensure all the write caches are flushed through a
512 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
513 * command to invalidate read only caches prior to programming
514 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
516 iris_emit_pipe_control_flush(batch
,
517 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
518 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
519 PIPE_CONTROL_DATA_CACHE_FLUSH
|
520 PIPE_CONTROL_CS_STALL
);
522 iris_emit_pipe_control_flush(batch
,
523 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
524 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
525 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
526 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
528 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
532 sel
.PipelineSelection
= pipeline
;
537 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
542 * "This chicken bit works around a hardware issue with barrier
543 * logic encountered when switching between GPGPU and 3D pipelines.
544 * To workaround the issue, this mode bit should be set after a
545 * pipeline is selected."
548 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
549 reg
.GLKBarrierMode
= value
;
550 reg
.GLKBarrierModeMask
= 1;
552 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
557 init_state_base_address(struct iris_batch
*batch
)
559 flush_for_state_base_change(batch
);
561 /* We program most base addresses once at context initialization time.
562 * Each base address points at a 4GB memory zone, and never needs to
563 * change. See iris_bufmgr.h for a description of the memory zones.
565 * The one exception is Surface State Base Address, which needs to be
566 * updated occasionally. See iris_binder.c for the details there.
568 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
570 // XXX: MOCS is stupid for this.
571 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
572 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
573 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
574 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
575 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
576 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
579 sba
.GeneralStateBaseAddressModifyEnable
= true;
580 sba
.DynamicStateBaseAddressModifyEnable
= true;
581 sba
.IndirectObjectBaseAddressModifyEnable
= true;
582 sba
.InstructionBaseAddressModifyEnable
= true;
583 sba
.GeneralStateBufferSizeModifyEnable
= true;
584 sba
.DynamicStateBufferSizeModifyEnable
= true;
585 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
586 sba
.IndirectObjectBufferSizeModifyEnable
= true;
587 sba
.InstructionBuffersizeModifyEnable
= true;
589 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
590 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
592 sba
.GeneralStateBufferSize
= 0xfffff;
593 sba
.IndirectObjectBufferSize
= 0xfffff;
594 sba
.InstructionBufferSize
= 0xfffff;
595 sba
.DynamicStateBufferSize
= 0xfffff;
600 * Upload the initial GPU state for a render context.
602 * This sets some invariant state that needs to be programmed a particular
603 * way, but we never actually change.
606 iris_init_render_context(struct iris_screen
*screen
,
607 struct iris_batch
*batch
,
608 struct iris_vtable
*vtbl
,
609 struct pipe_debug_callback
*dbg
)
611 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
614 emit_pipeline_select(batch
, _3D
);
616 init_state_base_address(batch
);
618 // XXX: INSTPM on Gen8
619 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
620 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
621 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
623 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
626 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
627 reg
.FloatBlendOptimizationEnable
= true;
628 reg
.FloatBlendOptimizationEnableMask
= true;
629 reg
.PartialResolveDisableInVC
= true;
630 reg
.PartialResolveDisableInVCMask
= true;
632 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
634 if (devinfo
->is_geminilake
)
635 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
639 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
640 reg
.HeaderlessMessageforPreemptableContexts
= 1;
641 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
643 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
648 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
649 * changing it dynamically. We set it to the maximum size here, and
650 * instead include the render target dimensions in the viewport, so
651 * viewport extents clipping takes care of pruning stray geometry.
653 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
654 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
655 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
658 /* Set the initial MSAA sample positions. */
659 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
660 GEN_SAMPLE_POS_1X(pat
._1xSample
);
661 GEN_SAMPLE_POS_2X(pat
._2xSample
);
662 GEN_SAMPLE_POS_4X(pat
._4xSample
);
663 GEN_SAMPLE_POS_8X(pat
._8xSample
);
664 GEN_SAMPLE_POS_16X(pat
._16xSample
);
667 /* Use the legacy AA line coverage computation. */
668 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
670 /* Disable chromakeying (it's for media) */
671 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
673 /* We want regular rendering, not special HiZ operations. */
674 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
676 /* No polygon stippling offsets are necessary. */
677 // XXX: may need to set an offset for origin-UL framebuffers
678 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
680 /* Set a static partitioning of the push constant area. */
681 // XXX: this may be a bad idea...could starve the push ringbuffers...
682 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
683 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
684 alloc
._3DCommandSubOpcode
= 18 + i
;
685 alloc
.ConstantBufferOffset
= 6 * i
;
686 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
692 iris_init_compute_context(struct iris_screen
*screen
,
693 struct iris_batch
*batch
,
694 struct iris_vtable
*vtbl
,
695 struct pipe_debug_callback
*dbg
)
697 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
699 emit_pipeline_select(batch
, GPGPU
);
701 init_state_base_address(batch
);
704 if (devinfo
->is_geminilake
)
705 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
709 struct iris_vertex_buffer_state
{
710 /** The 3DSTATE_VERTEX_BUFFERS hardware packet. */
711 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
713 /** The resource to source vertex data from. */
714 struct pipe_resource
*resources
[33];
716 /** The number of bound vertex buffers. */
717 unsigned num_buffers
;
720 struct iris_depth_buffer_state
{
721 /* Depth/HiZ/Stencil related hardware packets. */
722 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
723 GENX(3DSTATE_STENCIL_BUFFER_length
) +
724 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
725 GENX(3DSTATE_CLEAR_PARAMS_length
)];
729 * Generation-specific context state (ice->state.genx->...).
731 * Most state can go in iris_context directly, but these encode hardware
732 * packets which vary by generation.
734 struct iris_genx_state
{
735 /** SF_CLIP_VIEWPORT */
736 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
) * IRIS_MAX_VIEWPORTS
];
738 struct iris_vertex_buffer_state vertex_buffers
;
739 struct iris_depth_buffer_state depth_buffer
;
741 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
742 uint32_t streamout
[4 * GENX(3DSTATE_STREAMOUT_length
)];
746 * The pipe->set_blend_color() driver hook.
748 * This corresponds to our COLOR_CALC_STATE.
751 iris_set_blend_color(struct pipe_context
*ctx
,
752 const struct pipe_blend_color
*state
)
754 struct iris_context
*ice
= (struct iris_context
*) ctx
;
756 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
757 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
758 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
762 * Gallium CSO for blend state (see pipe_blend_state).
764 struct iris_blend_state
{
765 /** Partial 3DSTATE_PS_BLEND */
766 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
768 /** Partial BLEND_STATE */
769 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
770 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
772 bool alpha_to_coverage
; /* for shader key */
776 * The pipe->create_blend_state() driver hook.
778 * Translates a pipe_blend_state into iris_blend_state.
781 iris_create_blend_state(struct pipe_context
*ctx
,
782 const struct pipe_blend_state
*state
)
784 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
785 uint32_t *blend_state
= cso
->blend_state
;
787 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
789 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
790 /* pb.HasWriteableRT is filled in at draw time. */
791 /* pb.AlphaTestEnable is filled in at draw time. */
792 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
793 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
795 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
797 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
798 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
799 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
800 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
803 iris_pack_state(GENX(BLEND_STATE
), blend_state
, bs
) {
804 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
805 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
806 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
807 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
808 bs
.ColorDitherEnable
= state
->dither
;
809 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
812 blend_state
+= GENX(BLEND_STATE_length
);
814 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
815 const struct pipe_rt_blend_state
*rt
=
816 &state
->rt
[state
->independent_blend_enable
? i
: 0];
817 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_state
, be
) {
818 be
.LogicOpEnable
= state
->logicop_enable
;
819 be
.LogicOpFunction
= state
->logicop_func
;
821 be
.PreBlendSourceOnlyClampEnable
= false;
822 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
823 be
.PreBlendColorClampEnable
= true;
824 be
.PostBlendColorClampEnable
= true;
826 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
828 be
.ColorBlendFunction
= rt
->rgb_func
;
829 be
.AlphaBlendFunction
= rt
->alpha_func
;
830 be
.SourceBlendFactor
= rt
->rgb_src_factor
;
831 be
.SourceAlphaBlendFactor
= rt
->alpha_func
;
832 be
.DestinationBlendFactor
= rt
->rgb_dst_factor
;
833 be
.DestinationAlphaBlendFactor
= rt
->alpha_dst_factor
;
835 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
836 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
837 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
838 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
840 blend_state
+= GENX(BLEND_STATE_ENTRY_length
);
847 * The pipe->bind_blend_state() driver hook.
849 * Bind a blending CSO and flag related dirty bits.
852 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
854 struct iris_context
*ice
= (struct iris_context
*) ctx
;
855 ice
->state
.cso_blend
= state
;
856 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
857 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
858 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
862 * Gallium CSO for depth, stencil, and alpha testing state.
864 struct iris_depth_stencil_alpha_state
{
865 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
866 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
868 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
869 struct pipe_alpha_state alpha
;
871 /** Outbound to resolve and cache set tracking. */
872 bool depth_writes_enabled
;
873 bool stencil_writes_enabled
;
877 * The pipe->create_depth_stencil_alpha_state() driver hook.
879 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
880 * testing state since we need pieces of it in a variety of places.
883 iris_create_zsa_state(struct pipe_context
*ctx
,
884 const struct pipe_depth_stencil_alpha_state
*state
)
886 struct iris_depth_stencil_alpha_state
*cso
=
887 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
889 bool two_sided_stencil
= state
->stencil
[1].enabled
;
891 cso
->alpha
= state
->alpha
;
892 cso
->depth_writes_enabled
= state
->depth
.writemask
;
893 cso
->stencil_writes_enabled
=
894 state
->stencil
[0].writemask
!= 0 ||
895 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 1);
897 /* The state tracker needs to optimize away EQUAL writes for us. */
898 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
900 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
901 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
902 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
903 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
904 wmds
.StencilTestFunction
=
905 translate_compare_func(state
->stencil
[0].func
);
906 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
907 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
908 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
909 wmds
.BackfaceStencilTestFunction
=
910 translate_compare_func(state
->stencil
[1].func
);
911 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
912 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
913 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
914 wmds
.StencilBufferWriteEnable
=
915 state
->stencil
[0].writemask
!= 0 ||
916 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
917 wmds
.DepthTestEnable
= state
->depth
.enabled
;
918 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
919 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
920 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
921 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
922 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
923 /* wmds.[Backface]StencilReferenceValue are merged later */
930 * The pipe->bind_depth_stencil_alpha_state() driver hook.
932 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
935 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
937 struct iris_context
*ice
= (struct iris_context
*) ctx
;
938 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
939 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
942 if (cso_changed(alpha
.ref_value
))
943 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
945 if (cso_changed(alpha
.enabled
))
946 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
948 if (cso_changed(alpha
.func
))
949 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
951 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
952 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
955 ice
->state
.cso_zsa
= new_cso
;
956 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
957 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
958 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
962 * Gallium CSO for rasterizer state.
964 struct iris_rasterizer_state
{
965 uint32_t sf
[GENX(3DSTATE_SF_length
)];
966 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
967 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
968 uint32_t wm
[GENX(3DSTATE_WM_length
)];
969 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
971 uint8_t num_clip_plane_consts
;
972 bool clip_halfz
; /* for CC_VIEWPORT */
973 bool depth_clip_near
; /* for CC_VIEWPORT */
974 bool depth_clip_far
; /* for CC_VIEWPORT */
975 bool flatshade
; /* for shader state */
976 bool flatshade_first
; /* for stream output */
977 bool clamp_fragment_color
; /* for shader state */
978 bool light_twoside
; /* for shader state */
979 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
980 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
981 bool line_stipple_enable
;
982 bool poly_stipple_enable
;
984 bool force_persample_interp
;
985 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
986 uint16_t sprite_coord_enable
;
990 get_line_width(const struct pipe_rasterizer_state
*state
)
992 float line_width
= state
->line_width
;
994 /* From the OpenGL 4.4 spec:
996 * "The actual width of non-antialiased lines is determined by rounding
997 * the supplied width to the nearest integer, then clamping it to the
998 * implementation-dependent maximum non-antialiased line width."
1000 if (!state
->multisample
&& !state
->line_smooth
)
1001 line_width
= roundf(state
->line_width
);
1003 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1004 /* For 1 pixel line thickness or less, the general anti-aliasing
1005 * algorithm gives up, and a garbage line is generated. Setting a
1006 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1007 * (one-pixel-wide), non-antialiased lines.
1009 * Lines rendered with zero Line Width are rasterized using the
1010 * "Grid Intersection Quantization" rules as specified by the
1011 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1020 * The pipe->create_rasterizer_state() driver hook.
1023 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1024 const struct pipe_rasterizer_state
*state
)
1026 struct iris_rasterizer_state
*cso
=
1027 malloc(sizeof(struct iris_rasterizer_state
));
1030 point_quad_rasterization
-> SBE
?
1035 force_persample_interp
- ?
1038 offset_units_unscaled
- cap
not exposed
1042 // XXX: it may make more sense just to store the pipe_rasterizer_state,
1043 // we're copying a lot of booleans here. But we don't need all of them...
1045 cso
->multisample
= state
->multisample
;
1046 cso
->force_persample_interp
= state
->force_persample_interp
;
1047 cso
->clip_halfz
= state
->clip_halfz
;
1048 cso
->depth_clip_near
= state
->depth_clip_near
;
1049 cso
->depth_clip_far
= state
->depth_clip_far
;
1050 cso
->flatshade
= state
->flatshade
;
1051 cso
->flatshade_first
= state
->flatshade_first
;
1052 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1053 cso
->light_twoside
= state
->light_twoside
;
1054 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1055 cso
->half_pixel_center
= state
->half_pixel_center
;
1056 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1057 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1058 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1059 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1061 float line_width
= get_line_width(state
);
1063 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1064 sf
.StatisticsEnable
= true;
1065 sf
.ViewportTransformEnable
= true;
1066 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1067 sf
.LineEndCapAntialiasingRegionWidth
=
1068 state
->line_smooth
? _10pixels
: _05pixels
;
1069 sf
.LastPixelEnable
= state
->line_last_pixel
;
1070 sf
.LineWidth
= line_width
;
1071 sf
.SmoothPointEnable
= state
->point_smooth
|| state
->multisample
;
1072 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1073 sf
.PointWidth
= state
->point_size
;
1075 if (state
->flatshade_first
) {
1076 sf
.TriangleFanProvokingVertexSelect
= 1;
1078 sf
.TriangleStripListProvokingVertexSelect
= 2;
1079 sf
.TriangleFanProvokingVertexSelect
= 2;
1080 sf
.LineStripListProvokingVertexSelect
= 1;
1084 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1085 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1086 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1087 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1088 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1089 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1090 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1091 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1092 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1093 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1094 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1095 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1096 rr
.SmoothPointEnable
= state
->point_smooth
|| state
->multisample
;
1097 rr
.AntialiasingEnable
= state
->line_smooth
;
1098 rr
.ScissorRectangleEnable
= state
->scissor
;
1099 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1100 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1101 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
1104 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1105 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1106 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1108 cl
.StatisticsEnable
= true;
1109 cl
.EarlyCullEnable
= true;
1110 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1111 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1112 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1113 cl
.GuardbandClipTestEnable
= true;
1114 cl
.ClipMode
= CLIPMODE_NORMAL
;
1115 cl
.ClipEnable
= true;
1116 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
1117 cl
.MinimumPointWidth
= 0.125;
1118 cl
.MaximumPointWidth
= 255.875;
1120 if (state
->flatshade_first
) {
1121 cl
.TriangleFanProvokingVertexSelect
= 1;
1123 cl
.TriangleStripListProvokingVertexSelect
= 2;
1124 cl
.TriangleFanProvokingVertexSelect
= 2;
1125 cl
.LineStripListProvokingVertexSelect
= 1;
1129 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1130 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1131 * filled in at draw time from the FS program.
1133 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1134 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1135 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1136 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1137 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1140 /* Remap from 0..255 back to 1..256 */
1141 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1143 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1144 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1145 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1146 line
.LineStippleRepeatCount
= line_stipple_factor
;
1149 if (state
->clip_plane_enable
!= 0)
1150 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1156 * The pipe->bind_rasterizer_state() driver hook.
1158 * Bind a rasterizer CSO and flag related dirty bits.
1161 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1163 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1164 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1165 struct iris_rasterizer_state
*new_cso
= state
;
1168 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1169 if (cso_changed_memcmp(line_stipple
))
1170 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1172 if (cso_changed(half_pixel_center
))
1173 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1175 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1176 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1178 if (cso_changed(rasterizer_discard
) || cso_changed(flatshade_first
))
1179 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1181 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1182 cso_changed(clip_halfz
))
1183 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1185 if (cso_changed(sprite_coord_enable
) || cso_changed(light_twoside
))
1186 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1189 ice
->state
.cso_rast
= new_cso
;
1190 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1191 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1192 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1196 * Return true if the given wrap mode requires the border color to exist.
1198 * (We can skip uploading it if the sampler isn't going to use it.)
1201 wrap_mode_needs_border_color(unsigned wrap_mode
)
1203 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1207 * Gallium CSO for sampler state.
1209 struct iris_sampler_state
{
1210 union pipe_color_union border_color
;
1211 bool needs_border_color
;
1213 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1217 * The pipe->create_sampler_state() driver hook.
1219 * We fill out SAMPLER_STATE (except for the border color pointer), and
1220 * store that on the CPU. It doesn't make sense to upload it to a GPU
1221 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1222 * all bound sampler states to be in contiguous memor.
1225 iris_create_sampler_state(struct pipe_context
*ctx
,
1226 const struct pipe_sampler_state
*state
)
1228 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1233 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1234 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1236 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1237 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1238 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1240 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1242 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1243 wrap_mode_needs_border_color(wrap_t
) ||
1244 wrap_mode_needs_border_color(wrap_r
);
1246 float min_lod
= state
->min_lod
;
1247 unsigned mag_img_filter
= state
->mag_img_filter
;
1249 // XXX: explain this code ported from ilo...I don't get it at all...
1250 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1251 state
->min_lod
> 0.0f
) {
1253 mag_img_filter
= state
->min_img_filter
;
1256 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1257 samp
.TCXAddressControlMode
= wrap_s
;
1258 samp
.TCYAddressControlMode
= wrap_t
;
1259 samp
.TCZAddressControlMode
= wrap_r
;
1260 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1261 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1262 samp
.MinModeFilter
= state
->min_img_filter
;
1263 samp
.MagModeFilter
= mag_img_filter
;
1264 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1265 samp
.MaximumAnisotropy
= RATIO21
;
1267 if (state
->max_anisotropy
>= 2) {
1268 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1269 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1270 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1273 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1274 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1276 samp
.MaximumAnisotropy
=
1277 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1280 /* Set address rounding bits if not using nearest filtering. */
1281 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1282 samp
.UAddressMinFilterRoundingEnable
= true;
1283 samp
.VAddressMinFilterRoundingEnable
= true;
1284 samp
.RAddressMinFilterRoundingEnable
= true;
1287 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1288 samp
.UAddressMagFilterRoundingEnable
= true;
1289 samp
.VAddressMagFilterRoundingEnable
= true;
1290 samp
.RAddressMagFilterRoundingEnable
= true;
1293 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1294 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1296 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1298 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1299 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1300 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1301 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1303 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1310 * The pipe->bind_sampler_states() driver hook.
1312 * Now that we know all the sampler states, we upload them all into a
1313 * contiguous area of GPU memory, for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1314 * We also fill out the border color state pointers at this point.
1316 * We could defer this work to draw time, but we assume that binding
1317 * will be less frequent than drawing.
1319 // XXX: this may be a bad idea, need to make sure that st/mesa calls us
1320 // XXX: with the complete set of shaders. If it makes multiple calls to
1321 // XXX: things one at a time, we could waste a lot of time assembling things.
1322 // XXX: it doesn't even BUY us anything to do it here, because we only flag
1323 // XXX: IRIS_DIRTY_SAMPLER_STATE when this is called...
1325 iris_bind_sampler_states(struct pipe_context
*ctx
,
1326 enum pipe_shader_type p_stage
,
1327 unsigned start
, unsigned count
,
1330 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1331 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1332 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1334 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1335 shs
->num_samplers
= MAX2(shs
->num_samplers
, start
+ count
);
1337 for (int i
= 0; i
< count
; i
++) {
1338 shs
->samplers
[start
+ i
] = states
[i
];
1341 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1342 * in the dynamic state memory zone, so we can point to it via the
1343 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1346 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
,
1347 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
1351 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1352 shs
->sampler_table
.offset
+=
1353 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1355 /* Make sure all land in the same BO */
1356 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1358 for (int i
= 0; i
< count
; i
++) {
1359 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1362 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1363 } else if (!state
->needs_border_color
) {
1364 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1366 ice
->state
.need_border_colors
= true;
1368 /* Stream out the border color and merge the pointer. */
1370 iris_upload_border_color(ice
, &state
->border_color
);
1372 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1373 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1374 dyns
.BorderColorPointer
= offset
;
1377 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1378 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1381 map
+= GENX(SAMPLER_STATE_length
);
1384 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1387 static enum isl_channel_select
1388 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1391 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1392 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1393 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1394 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1395 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1396 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1397 default: unreachable("invalid swizzle");
1402 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1405 enum isl_format format
,
1409 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1410 const unsigned cpp
= fmtl
->bpb
/ 8;
1412 /* The ARB_texture_buffer_specification says:
1414 * "The number of texels in the buffer texture's texel array is given by
1416 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1418 * where <buffer_size> is the size of the buffer object, in basic
1419 * machine units and <components> and <base_type> are the element count
1420 * and base data type for elements, as specified in Table X.1. The
1421 * number of texels in the texel array is then clamped to the
1422 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1424 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1425 * so that when ISL divides by stride to obtain the number of texels, that
1426 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1428 unsigned final_size
=
1429 MIN3(size
, bo
->size
- offset
, IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1431 isl_buffer_fill_state(isl_dev
, map
,
1432 .address
= bo
->gtt_offset
+ offset
,
1433 .size_B
= final_size
,
1440 * The pipe->create_sampler_view() driver hook.
1442 static struct pipe_sampler_view
*
1443 iris_create_sampler_view(struct pipe_context
*ctx
,
1444 struct pipe_resource
*tex
,
1445 const struct pipe_sampler_view
*tmpl
)
1447 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1448 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1449 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1450 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1455 /* initialize base object */
1457 isv
->base
.context
= ctx
;
1458 isv
->base
.texture
= NULL
;
1459 pipe_reference_init(&isv
->base
.reference
, 1);
1460 pipe_resource_reference(&isv
->base
.texture
, tex
);
1462 void *map
= upload_state(ice
->state
.surface_uploader
, &isv
->surface_state
,
1463 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1467 struct iris_bo
*state_bo
= iris_resource_bo(isv
->surface_state
.res
);
1468 isv
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1470 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1471 struct iris_resource
*zres
, *sres
;
1472 const struct util_format_description
*desc
=
1473 util_format_description(tmpl
->format
);
1475 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1477 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1480 isv
->res
= (struct iris_resource
*) tex
;
1482 isl_surf_usage_flags_t usage
=
1483 ISL_SURF_USAGE_TEXTURE_BIT
|
1484 (isv
->res
->surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
);
1486 const struct iris_format_info fmt
=
1487 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1489 isv
->view
= (struct isl_view
) {
1491 .swizzle
= (struct isl_swizzle
) {
1492 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1493 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1494 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1495 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1500 /* Fill out SURFACE_STATE for this view. */
1501 if (tmpl
->target
!= PIPE_BUFFER
) {
1502 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1503 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1504 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1505 isv
->view
.array_len
=
1506 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1508 isl_surf_fill_state(&screen
->isl_dev
, map
,
1509 .surf
= &isv
->res
->surf
, .view
= &isv
->view
,
1511 .address
= isv
->res
->bo
->gtt_offset
);
1513 // .clear_color = clear_color,
1515 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
->bo
, map
,
1516 isv
->view
.format
, tmpl
->u
.buf
.offset
,
1524 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1525 struct pipe_sampler_view
*state
)
1527 struct iris_sampler_view
*isv
= (void *) state
;
1528 pipe_resource_reference(&state
->texture
, NULL
);
1529 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1534 * The pipe->create_surface() driver hook.
1536 * In Gallium nomenclature, "surfaces" are a view of a resource that
1537 * can be bound as a render target or depth/stencil buffer.
1539 static struct pipe_surface
*
1540 iris_create_surface(struct pipe_context
*ctx
,
1541 struct pipe_resource
*tex
,
1542 const struct pipe_surface
*tmpl
)
1544 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1545 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1546 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1547 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1548 struct pipe_surface
*psurf
= &surf
->base
;
1549 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1554 pipe_reference_init(&psurf
->reference
, 1);
1555 pipe_resource_reference(&psurf
->texture
, tex
);
1556 psurf
->context
= ctx
;
1557 psurf
->format
= tmpl
->format
;
1558 psurf
->width
= tex
->width0
;
1559 psurf
->height
= tex
->height0
;
1560 psurf
->texture
= tex
;
1561 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1562 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1563 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1565 isl_surf_usage_flags_t usage
= 0;
1567 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1568 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1569 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1571 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1573 const struct iris_format_info fmt
=
1574 iris_format_for_usage(devinfo
, psurf
->format
, usage
);
1576 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1577 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1578 /* Framebuffer validation will reject this invalid case, but it
1579 * hasn't had the opportunity yet. In the meantime, we need to
1580 * avoid hitting ISL asserts about unsupported formats below.
1586 surf
->view
= (struct isl_view
) {
1588 .base_level
= tmpl
->u
.tex
.level
,
1590 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1591 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1592 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1596 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1597 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1598 ISL_SURF_USAGE_STENCIL_BIT
))
1602 void *map
= upload_state(ice
->state
.surface_uploader
, &surf
->surface_state
,
1603 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1607 struct iris_bo
*state_bo
= iris_resource_bo(surf
->surface_state
.res
);
1608 surf
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1610 isl_surf_fill_state(&screen
->isl_dev
, map
,
1611 .surf
= &res
->surf
, .view
= &surf
->view
,
1613 .address
= res
->bo
->gtt_offset
);
1615 // .clear_color = clear_color,
1621 * The pipe->set_shader_images() driver hook.
1624 iris_set_shader_images(struct pipe_context
*ctx
,
1625 enum pipe_shader_type p_stage
,
1626 unsigned start_slot
, unsigned count
,
1627 const struct pipe_image_view
*p_images
)
1629 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1630 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1631 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1632 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1633 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1635 for (unsigned i
= 0; i
< count
; i
++) {
1636 if (p_images
&& p_images
[i
].resource
) {
1637 const struct pipe_image_view
*img
= &p_images
[i
];
1638 struct iris_resource
*res
= (void *) img
->resource
;
1639 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, &res
->base
);
1641 // XXX: these are not retained forever, use a separate uploader?
1643 upload_state(ice
->state
.surface_uploader
,
1644 &shs
->image
[start_slot
+ i
].surface_state
,
1645 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1646 if (!unlikely(map
)) {
1647 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1651 struct iris_bo
*surf_state_bo
=
1652 iris_resource_bo(shs
->image
[start_slot
+ i
].surface_state
.res
);
1653 shs
->image
[start_slot
+ i
].surface_state
.offset
+=
1654 iris_bo_offset_from_base_address(surf_state_bo
);
1656 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1657 enum isl_format isl_format
=
1658 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
1660 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
)
1661 isl_format
= isl_lower_storage_image_format(devinfo
, isl_format
);
1663 shs
->image
[start_slot
+ i
].access
= img
->shader_access
;
1665 if (res
->base
.target
!= PIPE_BUFFER
) {
1666 struct isl_view view
= {
1667 .format
= isl_format
,
1668 .base_level
= img
->u
.tex
.level
,
1670 .base_array_layer
= img
->u
.tex
.first_layer
,
1671 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
1672 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1676 isl_surf_fill_state(&screen
->isl_dev
, map
,
1677 .surf
= &res
->surf
, .view
= &view
,
1679 .address
= res
->bo
->gtt_offset
);
1681 // .clear_color = clear_color,
1683 fill_buffer_surface_state(&screen
->isl_dev
, res
->bo
, map
,
1684 isl_format
, img
->u
.buf
.offset
,
1688 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1689 pipe_resource_reference(&shs
->image
[start_slot
+ i
].surface_state
.res
,
1694 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1699 * The pipe->set_sampler_views() driver hook.
1702 iris_set_sampler_views(struct pipe_context
*ctx
,
1703 enum pipe_shader_type p_stage
,
1704 unsigned start
, unsigned count
,
1705 struct pipe_sampler_view
**views
)
1707 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1708 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1709 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1712 for (i
= 0; i
< count
; i
++) {
1713 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1714 &shs
->textures
[i
], views
[i
]);
1716 for (; i
< shs
->num_textures
; i
++) {
1717 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1718 &shs
->textures
[i
], NULL
);
1721 shs
->num_textures
= count
;
1723 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
1727 * The pipe->set_tess_state() driver hook.
1730 iris_set_tess_state(struct pipe_context
*ctx
,
1731 const float default_outer_level
[4],
1732 const float default_inner_level
[2])
1734 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1736 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
1737 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
1739 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
1743 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1745 struct iris_surface
*surf
= (void *) p_surf
;
1746 pipe_resource_reference(&p_surf
->texture
, NULL
);
1747 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
1751 // XXX: actually implement user clip planes
1753 iris_set_clip_state(struct pipe_context
*ctx
,
1754 const struct pipe_clip_state
*state
)
1759 * The pipe->set_polygon_stipple() driver hook.
1762 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1763 const struct pipe_poly_stipple
*state
)
1765 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1766 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1767 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1771 * The pipe->set_sample_mask() driver hook.
1774 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1776 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1778 /* We only support 16x MSAA, so we have 16 bits of sample maks.
1779 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
1781 ice
->state
.sample_mask
= sample_mask
& 0xffff;
1782 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1786 * The pipe->set_scissor_states() driver hook.
1788 * This corresponds to our SCISSOR_RECT state structures. It's an
1789 * exact match, so we just store them, and memcpy them out later.
1792 iris_set_scissor_states(struct pipe_context
*ctx
,
1793 unsigned start_slot
,
1794 unsigned num_scissors
,
1795 const struct pipe_scissor_state
*rects
)
1797 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1799 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1800 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
1801 /* If the scissor was out of bounds and got clamped to 0 width/height
1802 * at the bounds, the subtraction of 1 from maximums could produce a
1803 * negative number and thus not clip anything. Instead, just provide
1804 * a min > max scissor inside the bounds, which produces the expected
1807 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
1808 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
1811 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
1812 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
1813 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
1818 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1822 * The pipe->set_stencil_ref() driver hook.
1824 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
1827 iris_set_stencil_ref(struct pipe_context
*ctx
,
1828 const struct pipe_stencil_ref
*state
)
1830 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1831 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1832 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1836 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1838 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1843 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1844 float m00
, float m11
, float m30
, float m31
,
1845 float *xmin
, float *xmax
,
1846 float *ymin
, float *ymax
)
1848 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1849 * Strips and Fans documentation:
1851 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1852 * fixed-point "guardband" range supported by the rasterization hardware"
1856 * "In almost all circumstances, if an object’s vertices are actually
1857 * modified by this clamping (i.e., had X or Y coordinates outside of
1858 * the guardband extent the rendered object will not match the intended
1859 * result. Therefore software should take steps to ensure that this does
1860 * not happen - e.g., by clipping objects such that they do not exceed
1861 * these limits after the Drawing Rectangle is applied."
1863 * I believe the fundamental restriction is that the rasterizer (in
1864 * the SF/WM stages) have a limit on the number of pixels that can be
1865 * rasterized. We need to ensure any coordinates beyond the rasterizer
1866 * limit are handled by the clipper. So effectively that limit becomes
1867 * the clipper's guardband size.
1869 * It goes on to say:
1871 * "In addition, in order to be correctly rendered, objects must have a
1872 * screenspace bounding box not exceeding 8K in the X or Y direction.
1873 * This additional restriction must also be comprehended by software,
1874 * i.e., enforced by use of clipping."
1876 * This makes no sense. Gen7+ hardware supports 16K render targets,
1877 * and you definitely need to be able to draw polygons that fill the
1878 * surface. Our assumption is that the rasterizer was limited to 8K
1879 * on Sandybridge, which only supports 8K surfaces, and it was actually
1880 * increased to 16K on Ivybridge and later.
1882 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1884 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1886 if (m00
!= 0 && m11
!= 0) {
1887 /* First, we compute the screen-space render area */
1888 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1889 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1890 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1891 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1893 /* We want the guardband to be centered on that */
1894 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1895 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1896 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1897 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1899 /* Now we need it in native device coordinates */
1900 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1901 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1902 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1903 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1905 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1906 * flipped upside-down. X should be fine though.
1908 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1909 *xmin
= ndc_gb_xmin
;
1910 *xmax
= ndc_gb_xmax
;
1911 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1912 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1914 /* The viewport scales to 0, so nothing will be rendered. */
1924 * The pipe->set_viewport_states() driver hook.
1926 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
1927 * the guardband yet, as we need the framebuffer dimensions, but we can
1928 * at least fill out the rest.
1931 iris_set_viewport_states(struct pipe_context
*ctx
,
1932 unsigned start_slot
,
1934 const struct pipe_viewport_state
*states
)
1936 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1937 struct iris_genx_state
*genx
= ice
->state
.genx
;
1939 &genx
->sf_cl_vp
[start_slot
* GENX(SF_CLIP_VIEWPORT_length
)];
1941 for (unsigned i
= 0; i
< count
; i
++) {
1942 const struct pipe_viewport_state
*state
= &states
[i
];
1944 memcpy(&ice
->state
.viewports
[start_slot
+ i
], state
, sizeof(*state
));
1946 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
1947 vp
.ViewportMatrixElementm00
= state
->scale
[0];
1948 vp
.ViewportMatrixElementm11
= state
->scale
[1];
1949 vp
.ViewportMatrixElementm22
= state
->scale
[2];
1950 vp
.ViewportMatrixElementm30
= state
->translate
[0];
1951 vp
.ViewportMatrixElementm31
= state
->translate
[1];
1952 vp
.ViewportMatrixElementm32
= state
->translate
[2];
1953 /* XXX: in i965 this is computed based on the drawbuffer size,
1954 * but we don't have that here...
1956 vp
.XMinClipGuardband
= -1.0;
1957 vp
.XMaxClipGuardband
= 1.0;
1958 vp
.YMinClipGuardband
= -1.0;
1959 vp
.YMaxClipGuardband
= 1.0;
1960 vp
.XMinViewPort
= viewport_extent(state
, 0, -1.0f
);
1961 vp
.XMaxViewPort
= viewport_extent(state
, 0, 1.0f
) - 1;
1962 vp
.YMinViewPort
= viewport_extent(state
, 1, -1.0f
);
1963 vp
.YMaxViewPort
= viewport_extent(state
, 1, 1.0f
) - 1;
1966 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
1969 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1971 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
1972 !ice
->state
.cso_rast
->depth_clip_far
))
1973 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1977 * The pipe->set_framebuffer_state() driver hook.
1979 * Sets the current draw FBO, including color render targets, depth,
1980 * and stencil buffers.
1983 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1984 const struct pipe_framebuffer_state
*state
)
1986 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1987 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1988 struct isl_device
*isl_dev
= &screen
->isl_dev
;
1989 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1990 struct iris_resource
*zres
;
1991 struct iris_resource
*stencil_res
;
1993 unsigned samples
= util_framebuffer_get_num_samples(state
);
1995 if (cso
->samples
!= samples
) {
1996 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1999 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2000 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2003 if ((cso
->layers
== 0) != (state
->layers
== 0)) {
2004 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2007 util_copy_framebuffer_state(cso
, state
);
2008 cso
->samples
= samples
;
2010 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2012 struct isl_view view
= {
2015 .base_array_layer
= 0,
2017 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2020 struct isl_depth_stencil_hiz_emit_info info
= {
2026 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2029 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2030 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2032 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2035 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2037 info
.depth_surf
= &zres
->surf
;
2038 info
.depth_address
= zres
->bo
->gtt_offset
;
2039 info
.hiz_usage
= ISL_AUX_USAGE_NONE
;
2041 view
.format
= zres
->surf
.format
;
2045 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2046 info
.stencil_surf
= &stencil_res
->surf
;
2047 info
.stencil_address
= stencil_res
->bo
->gtt_offset
;
2049 view
.format
= stencil_res
->surf
.format
;
2053 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2055 /* Make a null surface for unbound buffers */
2056 void *null_surf_map
=
2057 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2058 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2059 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2060 isl_extent3d(MAX2(cso
->width
, 1),
2061 MAX2(cso
->height
, 1),
2062 cso
->layers
? cso
->layers
: 1));
2063 ice
->state
.null_fb
.offset
+=
2064 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2066 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2068 /* Render target change */
2069 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2071 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2074 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2075 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2077 /* The PIPE_CONTROL command description says:
2079 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2080 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2081 * Target Cache Flush by enabling this bit. When render target flush
2082 * is set due to new association of BTI, PS Scoreboard Stall bit must
2083 * be set in this packet."
2085 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2086 iris_emit_pipe_control_flush(&ice
->render_batch
,
2087 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2088 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2093 upload_ubo_surf_state(struct iris_context
*ice
,
2094 struct iris_const_buffer
*cbuf
,
2095 unsigned buffer_size
)
2097 struct pipe_context
*ctx
= &ice
->ctx
;
2098 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
2100 // XXX: these are not retained forever, use a separate uploader?
2102 upload_state(ice
->state
.surface_uploader
, &cbuf
->surface_state
,
2103 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2104 if (!unlikely(map
)) {
2105 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2109 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2110 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state
.res
);
2111 cbuf
->surface_state
.offset
+= iris_bo_offset_from_base_address(surf_bo
);
2113 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2114 .address
= res
->bo
->gtt_offset
+ cbuf
->data
.offset
,
2115 .size_B
= MIN2(buffer_size
,
2116 res
->bo
->size
- cbuf
->data
.offset
),
2117 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
2123 * The pipe->set_constant_buffer() driver hook.
2125 * This uploads any constant data in user buffers, and references
2126 * any UBO resources containing constant data.
2129 iris_set_constant_buffer(struct pipe_context
*ctx
,
2130 enum pipe_shader_type p_stage
, unsigned index
,
2131 const struct pipe_constant_buffer
*input
)
2133 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2134 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2135 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2136 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
2138 if (input
&& input
->buffer
) {
2141 pipe_resource_reference(&cbuf
->data
.res
, input
->buffer
);
2142 cbuf
->data
.offset
= input
->buffer_offset
;
2144 upload_ubo_surf_state(ice
, cbuf
, input
->buffer_size
);
2146 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2147 pipe_resource_reference(&cbuf
->surface_state
.res
, NULL
);
2152 memcpy(&shs
->cbuf0
, input
, sizeof(shs
->cbuf0
));
2154 memset(&shs
->cbuf0
, 0, sizeof(shs
->cbuf0
));
2156 shs
->cbuf0_needs_upload
= true;
2159 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2160 // XXX: maybe not necessary all the time...?
2161 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2162 // XXX: pull model we may need actual new bindings...
2163 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2167 upload_uniforms(struct iris_context
*ice
,
2168 gl_shader_stage stage
)
2170 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2171 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
2172 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2173 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
2175 unsigned upload_size
= prog_data
->nr_params
* sizeof(uint32_t) +
2176 shs
->cbuf0
.buffer_size
;
2178 if (upload_size
== 0)
2182 upload_state(ice
->ctx
.const_uploader
, &cbuf
->data
, upload_size
, 64);
2184 for (int i
= 0; i
< prog_data
->nr_params
; i
++) {
2185 uint32_t param
= prog_data
->param
[i
];
2188 printf("got a param to upload - %u\n", param
);
2193 if (shs
->cbuf0
.user_buffer
) {
2194 memcpy(map
, shs
->cbuf0
.user_buffer
, shs
->cbuf0
.buffer_size
);
2197 upload_ubo_surf_state(ice
, cbuf
, upload_size
);
2201 * The pipe->set_shader_buffers() driver hook.
2203 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2204 * SURFACE_STATE here, as the buffer offset may change each time.
2207 iris_set_shader_buffers(struct pipe_context
*ctx
,
2208 enum pipe_shader_type p_stage
,
2209 unsigned start_slot
, unsigned count
,
2210 const struct pipe_shader_buffer
*buffers
)
2212 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2213 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2214 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2215 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2217 for (unsigned i
= 0; i
< count
; i
++) {
2218 if (buffers
&& buffers
[i
].buffer
) {
2219 const struct pipe_shader_buffer
*buffer
= &buffers
[i
];
2220 struct iris_resource
*res
= (void *) buffer
->buffer
;
2221 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], &res
->base
);
2223 // XXX: these are not retained forever, use a separate uploader?
2225 upload_state(ice
->state
.surface_uploader
,
2226 &shs
->ssbo_surface_state
[start_slot
+ i
],
2227 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2228 if (!unlikely(map
)) {
2229 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2233 struct iris_bo
*surf_state_bo
=
2234 iris_resource_bo(shs
->ssbo_surface_state
[start_slot
+ i
].res
);
2235 shs
->ssbo_surface_state
[start_slot
+ i
].offset
+=
2236 iris_bo_offset_from_base_address(surf_state_bo
);
2238 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2240 res
->bo
->gtt_offset
+ buffer
->buffer_offset
,
2242 MIN2(buffer
->buffer_size
,
2243 res
->bo
->size
- buffer
->buffer_offset
),
2244 .format
= ISL_FORMAT_RAW
,
2248 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2249 pipe_resource_reference(&shs
->ssbo_surface_state
[start_slot
+ i
].res
,
2254 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2258 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2264 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
2266 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
2267 pipe_resource_reference(&cso
->resources
[i
], NULL
);
2271 * The pipe->set_vertex_buffers() driver hook.
2273 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2276 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2277 unsigned start_slot
, unsigned count
,
2278 const struct pipe_vertex_buffer
*buffers
)
2280 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2281 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
2283 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
2288 cso
->num_buffers
= count
;
2290 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
2291 vb
.DWordLength
= 4 * MAX2(cso
->num_buffers
, 1) - 1;
2294 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
2297 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
2298 vb
.VertexBufferIndex
= start_slot
;
2299 vb
.NullVertexBuffer
= true;
2300 vb
.AddressModifyEnable
= true;
2304 for (unsigned i
= 0; i
< count
; i
++) {
2305 assert(!buffers
[i
].is_user_buffer
);
2307 pipe_resource_reference(&cso
->resources
[i
], buffers
[i
].buffer
.resource
);
2308 struct iris_resource
*res
= (void *) cso
->resources
[i
];
2310 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
2311 vb
.VertexBufferIndex
= start_slot
+ i
;
2313 vb
.AddressModifyEnable
= true;
2314 vb
.BufferPitch
= buffers
[i
].stride
;
2316 vb
.BufferSize
= res
->bo
->size
;
2317 vb
.BufferStartingAddress
=
2318 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffers
[i
].buffer_offset
);
2320 vb
.NullVertexBuffer
= true;
2324 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
2327 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2331 * Gallium CSO for vertex elements.
2333 struct iris_vertex_element_state
{
2334 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2335 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2340 * The pipe->create_vertex_elements() driver hook.
2342 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2343 * and 3DSTATE_VF_INSTANCING commands. SGVs are handled at draw time.
2346 iris_create_vertex_elements(struct pipe_context
*ctx
,
2348 const struct pipe_vertex_element
*state
)
2350 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2351 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2352 struct iris_vertex_element_state
*cso
=
2353 malloc(sizeof(struct iris_vertex_element_state
));
2358 * - create edge flag one
2360 * - if those are necessary, use count + 1/2/3... OR in the length
2362 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2364 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2367 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2368 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2371 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2373 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2374 ve
.Component0Control
= VFCOMP_STORE_0
;
2375 ve
.Component1Control
= VFCOMP_STORE_0
;
2376 ve
.Component2Control
= VFCOMP_STORE_0
;
2377 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2380 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2384 for (int i
= 0; i
< count
; i
++) {
2385 const struct iris_format_info fmt
=
2386 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2387 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2388 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2390 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2391 case 0: comp
[0] = VFCOMP_STORE_0
;
2392 case 1: comp
[1] = VFCOMP_STORE_0
;
2393 case 2: comp
[2] = VFCOMP_STORE_0
;
2395 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2396 : VFCOMP_STORE_1_FP
;
2399 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2400 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2402 ve
.SourceElementOffset
= state
[i
].src_offset
;
2403 ve
.SourceElementFormat
= fmt
.fmt
;
2404 ve
.Component0Control
= comp
[0];
2405 ve
.Component1Control
= comp
[1];
2406 ve
.Component2Control
= comp
[2];
2407 ve
.Component3Control
= comp
[3];
2410 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2411 vi
.VertexElementIndex
= i
;
2412 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2413 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2416 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2417 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2424 * The pipe->bind_vertex_elements_state() driver hook.
2427 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2429 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2430 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2431 struct iris_vertex_element_state
*new_cso
= state
;
2433 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2434 * we need to re-emit it to ensure we're overriding the right one.
2436 if (new_cso
&& cso_changed(count
))
2437 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2439 ice
->state
.cso_vertex_elements
= state
;
2440 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2444 * Gallium CSO for stream output (transform feedback) targets.
2446 struct iris_stream_output_target
{
2447 struct pipe_stream_output_target base
;
2449 uint32_t so_buffer
[GENX(3DSTATE_SO_BUFFER_length
)];
2451 /** Storage holding the offset where we're writing in the buffer */
2452 struct iris_state_ref offset
;
2456 * The pipe->create_stream_output_target() driver hook.
2458 * "Target" here refers to a destination buffer. We translate this into
2459 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2460 * know which buffer this represents, or whether we ought to zero the
2461 * write-offsets, or append. Those are handled in the set() hook.
2463 static struct pipe_stream_output_target
*
2464 iris_create_stream_output_target(struct pipe_context
*ctx
,
2465 struct pipe_resource
*res
,
2466 unsigned buffer_offset
,
2467 unsigned buffer_size
)
2469 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2473 pipe_reference_init(&cso
->base
.reference
, 1);
2474 pipe_resource_reference(&cso
->base
.buffer
, res
);
2475 cso
->base
.buffer_offset
= buffer_offset
;
2476 cso
->base
.buffer_size
= buffer_size
;
2477 cso
->base
.context
= ctx
;
2479 upload_state(ctx
->stream_uploader
, &cso
->offset
, 4 * sizeof(uint32_t), 4);
2481 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), cso
->so_buffer
, sob
) {
2482 sob
.SurfaceBaseAddress
=
2483 rw_bo(NULL
, iris_resource_bo(res
)->gtt_offset
+ buffer_offset
);
2484 sob
.SOBufferEnable
= true;
2485 sob
.StreamOffsetWriteEnable
= true;
2486 sob
.StreamOutputBufferOffsetAddressEnable
= true;
2487 sob
.MOCS
= MOCS_WB
; // XXX: MOCS
2489 sob
.SurfaceSize
= MAX2(buffer_size
/ 4, 1) - 1;
2491 /* .SOBufferIndex, .StreamOffset, and .StreamOutputBufferOffsetAddress
2492 * are filled in later when we have stream IDs.
2500 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2501 struct pipe_stream_output_target
*state
)
2503 struct iris_stream_output_target
*cso
= (void *) state
;
2505 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2506 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2512 * The pipe->set_stream_output_targets() driver hook.
2514 * At this point, we know which targets are bound to a particular index,
2515 * and also whether we want to append or start over. We can finish the
2516 * 3DSTATE_SO_BUFFER packets we started earlier.
2519 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2520 unsigned num_targets
,
2521 struct pipe_stream_output_target
**targets
,
2522 const unsigned *offsets
)
2524 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2525 struct iris_genx_state
*genx
= ice
->state
.genx
;
2526 uint32_t *so_buffers
= genx
->so_buffers
;
2528 const bool active
= num_targets
> 0;
2529 if (ice
->state
.streamout_active
!= active
) {
2530 ice
->state
.streamout_active
= active
;
2531 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2533 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
2534 * it's a non-pipelined command. If we're switching streamout on, we
2535 * may have missed emitting it earlier, so do so now. (We're already
2536 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
2539 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
2542 for (int i
= 0; i
< 4; i
++) {
2543 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2544 i
< num_targets
? targets
[i
] : NULL
);
2547 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2551 for (unsigned i
= 0; i
< 4; i
++,
2552 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2554 if (i
>= num_targets
|| !targets
[i
]) {
2555 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
2556 sob
.SOBufferIndex
= i
;
2560 struct iris_stream_output_target
*tgt
= (void *) targets
[i
];
2562 /* Note that offsets[i] will either be 0, causing us to zero
2563 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
2564 * "continue appending at the existing offset."
2566 assert(offsets
[i
] == 0 || offsets
[i
] == 0xFFFFFFFF);
2568 uint32_t dynamic
[GENX(3DSTATE_SO_BUFFER_length
)];
2569 iris_pack_state(GENX(3DSTATE_SO_BUFFER
), dynamic
, dyns
) {
2570 dyns
.SOBufferIndex
= i
;
2571 dyns
.StreamOffset
= offsets
[i
];
2572 dyns
.StreamOutputBufferOffsetAddress
=
2573 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+ tgt
->offset
.offset
+ i
* sizeof(uint32_t));
2576 for (uint32_t j
= 0; j
< GENX(3DSTATE_SO_BUFFER_length
); j
++) {
2577 so_buffers
[j
] = tgt
->so_buffer
[j
] | dynamic
[j
];
2581 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
2585 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
2586 * 3DSTATE_STREAMOUT packets.
2588 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
2589 * hardware to record. We can create it entirely based on the shader, with
2590 * no dynamic state dependencies.
2592 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
2593 * state-based settings. We capture the shader-related ones here, and merge
2594 * the rest in at draw time.
2597 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
2598 const struct brw_vue_map
*vue_map
)
2600 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2601 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2602 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2603 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2605 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2607 memset(so_decl
, 0, sizeof(so_decl
));
2609 /* Construct the list of SO_DECLs to be emitted. The formatting of the
2610 * command feels strange -- each dword pair contains a SO_DECL per stream.
2612 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
2613 const struct pipe_stream_output
*output
= &info
->output
[i
];
2614 const int buffer
= output
->output_buffer
;
2615 const int varying
= output
->register_index
;
2616 const unsigned stream_id
= output
->stream
;
2617 assert(stream_id
< MAX_VERTEX_STREAMS
);
2619 buffer_mask
[stream_id
] |= 1 << buffer
;
2621 assert(vue_map
->varying_to_slot
[varying
] >= 0);
2623 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
2624 * array. Instead, it simply increments DstOffset for the following
2625 * input by the number of components that should be skipped.
2627 * Our hardware is unusual in that it requires us to program SO_DECLs
2628 * for fake "hole" components, rather than simply taking the offset
2629 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
2630 * program as many size = 4 holes as we can, then a final hole to
2631 * accommodate the final 1, 2, or 3 remaining.
2633 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
2635 while (skip_components
> 0) {
2636 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2638 .OutputBufferSlot
= output
->output_buffer
,
2639 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
2641 skip_components
-= 4;
2644 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
2646 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2647 .OutputBufferSlot
= output
->output_buffer
,
2648 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
2650 ((1 << output
->num_components
) - 1) << output
->start_component
,
2653 if (decls
[stream_id
] > max_decls
)
2654 max_decls
= decls
[stream_id
];
2657 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
2658 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
2659 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
2661 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
2662 int urb_entry_read_offset
= 0;
2663 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
2664 urb_entry_read_offset
;
2666 /* We always read the whole vertex. This could be reduced at some
2667 * point by reading less and offsetting the register index in the
2670 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
2671 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
2672 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
2673 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
2674 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
2675 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
2676 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
2677 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
2679 /* Set buffer pitches; 0 means unbound. */
2680 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
2681 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
2682 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
2683 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
2686 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
2687 list
.DWordLength
= 3 + 2 * max_decls
- 2;
2688 list
.StreamtoBufferSelects0
= buffer_mask
[0];
2689 list
.StreamtoBufferSelects1
= buffer_mask
[1];
2690 list
.StreamtoBufferSelects2
= buffer_mask
[2];
2691 list
.StreamtoBufferSelects3
= buffer_mask
[3];
2692 list
.NumEntries0
= decls
[0];
2693 list
.NumEntries1
= decls
[1];
2694 list
.NumEntries2
= decls
[2];
2695 list
.NumEntries3
= decls
[3];
2698 for (int i
= 0; i
< max_decls
; i
++) {
2699 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
2700 entry
.Stream0Decl
= so_decl
[0][i
];
2701 entry
.Stream1Decl
= so_decl
[1][i
];
2702 entry
.Stream2Decl
= so_decl
[2][i
];
2703 entry
.Stream3Decl
= so_decl
[3][i
];
2711 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
2712 const struct brw_vue_map
*last_vue_map
,
2713 bool two_sided_color
,
2714 unsigned *out_offset
,
2715 unsigned *out_length
)
2717 /* The compiler computes the first URB slot without considering COL/BFC
2718 * swizzling (because it doesn't know whether it's enabled), so we need
2719 * to do that here too. This may result in a smaller offset, which
2722 const unsigned first_slot
=
2723 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
2725 /* This becomes the URB read offset (counted in pairs of slots). */
2726 assert(first_slot
% 2 == 0);
2727 *out_offset
= first_slot
/ 2;
2729 /* We need to adjust the inputs read to account for front/back color
2730 * swizzling, as it can make the URB length longer.
2732 for (int c
= 0; c
<= 1; c
++) {
2733 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
2734 /* If two sided color is enabled, the fragment shader's gl_Color
2735 * (COL0) input comes from either the gl_FrontColor (COL0) or
2736 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
2738 if (two_sided_color
)
2739 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2741 /* If front color isn't written, we opt to give them back color
2742 * instead of an undefined value. Switch from COL to BFC.
2744 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
2745 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
2746 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2751 /* Compute the minimum URB Read Length necessary for the FS inputs.
2753 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
2754 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
2756 * "This field should be set to the minimum length required to read the
2757 * maximum source attribute. The maximum source attribute is indicated
2758 * by the maximum value of the enabled Attribute # Source Attribute if
2759 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
2760 * enable is not set.
2761 * read_length = ceiling((max_source_attr + 1) / 2)
2763 * [errata] Corruption/Hang possible if length programmed larger than
2766 * Similar text exists for Ivy Bridge.
2768 * We find the last URB slot that's actually read by the FS.
2770 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
2771 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
2772 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
2775 /* The URB read length is the difference of the two, counted in pairs. */
2776 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
2780 iris_emit_sbe_swiz(struct iris_batch
*batch
,
2781 const struct iris_context
*ice
,
2782 unsigned urb_read_offset
,
2783 unsigned sprite_coord_enables
)
2785 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
2786 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2787 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2788 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
2789 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2791 /* XXX: this should be generated when putting programs in place */
2793 // XXX: raster->sprite_coord_enable
2795 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
2796 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
2797 if (input_index
< 0 || input_index
>= 16)
2800 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
2801 &attr_overrides
[input_index
];
2802 int slot
= vue_map
->varying_to_slot
[fs_attr
];
2804 /* Viewport and Layer are stored in the VUE header. We need to override
2805 * them to zero if earlier stages didn't write them, as GL requires that
2806 * they read back as zero when not explicitly set.
2809 case VARYING_SLOT_VIEWPORT
:
2810 case VARYING_SLOT_LAYER
:
2811 attr
->ComponentOverrideX
= true;
2812 attr
->ComponentOverrideW
= true;
2813 attr
->ConstantSource
= CONST_0000
;
2815 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
2816 attr
->ComponentOverrideY
= true;
2817 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
2818 attr
->ComponentOverrideZ
= true;
2821 case VARYING_SLOT_PRIMITIVE_ID
:
2822 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
2824 attr
->ComponentOverrideX
= true;
2825 attr
->ComponentOverrideY
= true;
2826 attr
->ComponentOverrideZ
= true;
2827 attr
->ComponentOverrideW
= true;
2828 attr
->ConstantSource
= PRIM_ID
;
2836 if (sprite_coord_enables
& (1 << input_index
))
2839 /* If there was only a back color written but not front, use back
2840 * as the color instead of undefined.
2842 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
2843 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
2844 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
2845 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
2847 /* Not written by the previous stage - undefined. */
2849 attr
->ComponentOverrideX
= true;
2850 attr
->ComponentOverrideY
= true;
2851 attr
->ComponentOverrideZ
= true;
2852 attr
->ComponentOverrideW
= true;
2853 attr
->ConstantSource
= CONST_0001_FLOAT
;
2857 /* Compute the location of the attribute relative to the read offset,
2858 * which is counted in 256-bit increments (two 128-bit VUE slots).
2860 const int source_attr
= slot
- 2 * urb_read_offset
;
2861 assert(source_attr
>= 0 && source_attr
<= 32);
2862 attr
->SourceAttribute
= source_attr
;
2864 /* If we are doing two-sided color, and the VUE slot following this one
2865 * represents a back-facing color, then we need to instruct the SF unit
2866 * to do back-facing swizzling.
2868 if (cso_rast
->light_twoside
&&
2869 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
2870 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
2871 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
2872 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
2873 attr
->SwizzleSelect
= INPUTATTR_FACING
;
2876 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
2877 for (int i
= 0; i
< 16; i
++)
2878 sbes
.Attribute
[i
] = attr_overrides
[i
];
2883 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
2884 const struct iris_rasterizer_state
*cso
)
2886 unsigned overrides
= 0;
2888 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
2889 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
2891 for (int i
= 0; i
< 8; i
++) {
2892 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
2893 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
2894 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
2901 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
2903 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2904 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2905 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2906 const struct shader_info
*fs_info
=
2907 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
2909 unsigned urb_read_offset
, urb_read_length
;
2910 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
2911 ice
->shaders
.last_vue_map
,
2912 cso_rast
->light_twoside
,
2913 &urb_read_offset
, &urb_read_length
);
2915 unsigned sprite_coord_overrides
=
2916 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
2918 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
2919 sbe
.AttributeSwizzleEnable
= true;
2920 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2921 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
2922 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
2923 sbe
.VertexURBEntryReadLength
= urb_read_length
;
2924 sbe
.ForceVertexURBEntryReadOffset
= true;
2925 sbe
.ForceVertexURBEntryReadLength
= true;
2926 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
2927 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
2929 for (int i
= 0; i
< 32; i
++) {
2930 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
2934 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
2937 /* ------------------------------------------------------------------- */
2940 * Set sampler-related program key fields based on the current state.
2943 iris_populate_sampler_key(const struct iris_context
*ice
,
2944 struct brw_sampler_prog_key_data
*key
)
2946 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
2947 key
->swizzles
[i
] = 0x688; /* XYZW */
2952 * Populate VS program key fields based on the current state.
2955 iris_populate_vs_key(const struct iris_context
*ice
,
2956 const struct shader_info
*info
,
2957 struct brw_vs_prog_key
*key
)
2959 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2961 iris_populate_sampler_key(ice
, &key
->tex
);
2963 if (info
->clip_distance_array_size
== 0)
2964 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
2968 * Populate TCS program key fields based on the current state.
2971 iris_populate_tcs_key(const struct iris_context
*ice
,
2972 struct brw_tcs_prog_key
*key
)
2974 iris_populate_sampler_key(ice
, &key
->tex
);
2978 * Populate TES program key fields based on the current state.
2981 iris_populate_tes_key(const struct iris_context
*ice
,
2982 struct brw_tes_prog_key
*key
)
2984 iris_populate_sampler_key(ice
, &key
->tex
);
2988 * Populate GS program key fields based on the current state.
2991 iris_populate_gs_key(const struct iris_context
*ice
,
2992 struct brw_gs_prog_key
*key
)
2994 iris_populate_sampler_key(ice
, &key
->tex
);
2998 * Populate FS program key fields based on the current state.
3001 iris_populate_fs_key(const struct iris_context
*ice
,
3002 struct brw_wm_prog_key
*key
)
3004 iris_populate_sampler_key(ice
, &key
->tex
);
3006 /* XXX: dirty flags? */
3007 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3008 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3009 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3010 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3012 key
->nr_color_regions
= fb
->nr_cbufs
;
3014 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3016 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
3017 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
3019 /* XXX: only bother if COL0/1 are read */
3020 key
->flat_shade
= rast
->flatshade
;
3022 key
->persample_interp
= rast
->force_persample_interp
;
3023 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3025 key
->coherent_fb_fetch
= true;
3027 // XXX: uint64_t input_slots_valid; - for >16 inputs
3029 // XXX: key->force_dual_color_blend for unigine
3030 // XXX: respect hint for high_quality_derivatives:1;
3034 iris_populate_cs_key(const struct iris_context
*ice
,
3035 struct brw_cs_prog_key
*key
)
3037 iris_populate_sampler_key(ice
, &key
->tex
);
3041 // XXX: these need to go in INIT_THREAD_DISPATCH_FIELDS
3042 pkt
.SamplerCount
= \
3043 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4); \
3048 KSP(const struct iris_compiled_shader
*shader
)
3050 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3051 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3054 // Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3055 // prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3056 // this WA on C0 stepping.
3058 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3059 pkt.KernelStartPointer = KSP(shader); \
3060 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3061 prog_data->binding_table.size_bytes / 4; \
3062 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3064 pkt.DispatchGRFStartRegisterForURBData = \
3065 prog_data->dispatch_grf_start_reg; \
3066 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3067 pkt.prefix##URBEntryReadOffset = 0; \
3069 pkt.StatisticsEnable = true; \
3070 pkt.Enable = true; \
3072 if (prog_data->total_scratch) { \
3073 uint32_t scratch_addr = \
3074 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3075 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3076 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3080 * Encode most of 3DSTATE_VS based on the compiled shader.
3083 iris_store_vs_state(struct iris_context
*ice
,
3084 const struct gen_device_info
*devinfo
,
3085 struct iris_compiled_shader
*shader
)
3087 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3088 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3090 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3091 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3092 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3093 vs
.SIMD8DispatchEnable
= true;
3094 vs
.UserClipDistanceCullTestEnableBitmask
=
3095 vue_prog_data
->cull_distance_mask
;
3100 * Encode most of 3DSTATE_HS based on the compiled shader.
3103 iris_store_tcs_state(struct iris_context
*ice
,
3104 const struct gen_device_info
*devinfo
,
3105 struct iris_compiled_shader
*shader
)
3107 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3108 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3109 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3111 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3112 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3114 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3115 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3116 hs
.IncludeVertexHandles
= true;
3121 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3124 iris_store_tes_state(struct iris_context
*ice
,
3125 const struct gen_device_info
*devinfo
,
3126 struct iris_compiled_shader
*shader
)
3128 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3129 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3130 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3132 uint32_t *te_state
= (void *) shader
->derived_data
;
3133 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3135 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3136 te
.Partitioning
= tes_prog_data
->partitioning
;
3137 te
.OutputTopology
= tes_prog_data
->output_topology
;
3138 te
.TEDomain
= tes_prog_data
->domain
;
3140 te
.MaximumTessellationFactorOdd
= 63.0;
3141 te
.MaximumTessellationFactorNotOdd
= 64.0;
3144 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3145 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3147 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3148 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3149 ds
.ComputeWCoordinateEnable
=
3150 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3152 ds
.UserClipDistanceCullTestEnableBitmask
=
3153 vue_prog_data
->cull_distance_mask
;
3159 * Encode most of 3DSTATE_GS based on the compiled shader.
3162 iris_store_gs_state(struct iris_context
*ice
,
3163 const struct gen_device_info
*devinfo
,
3164 struct iris_compiled_shader
*shader
)
3166 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3167 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3168 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3170 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3171 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3173 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3174 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3175 gs
.ControlDataHeaderSize
=
3176 gs_prog_data
->control_data_header_size_hwords
;
3177 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3178 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3179 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3180 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3181 gs
.ReorderMode
= TRAILING
;
3182 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3183 gs
.MaximumNumberofThreads
=
3184 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3185 : (devinfo
->max_gs_threads
- 1);
3187 if (gs_prog_data
->static_vertex_count
!= -1) {
3188 gs
.StaticOutput
= true;
3189 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3191 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3193 gs
.UserClipDistanceCullTestEnableBitmask
=
3194 vue_prog_data
->cull_distance_mask
;
3196 const int urb_entry_write_offset
= 1;
3197 const uint32_t urb_entry_output_length
=
3198 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3199 urb_entry_write_offset
;
3201 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3202 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3207 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3210 iris_store_fs_state(struct iris_context
*ice
,
3211 const struct gen_device_info
*devinfo
,
3212 struct iris_compiled_shader
*shader
)
3214 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3215 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3217 uint32_t *ps_state
= (void *) shader
->derived_data
;
3218 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3220 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3221 ps
.VectorMaskEnable
= true;
3222 //ps.SamplerCount = ...
3223 // XXX: WABTPPrefetchDisable, see above, drop at C0
3224 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3225 prog_data
->binding_table
.size_bytes
/ 4;
3226 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3227 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3229 ps
.PushConstantEnable
= prog_data
->nr_params
> 0 ||
3230 prog_data
->ubo_ranges
[0].length
> 0;
3232 /* From the documentation for this packet:
3233 * "If the PS kernel does not need the Position XY Offsets to
3234 * compute a Position Value, then this field should be programmed
3235 * to POSOFFSET_NONE."
3237 * "SW Recommendation: If the PS kernel needs the Position Offsets
3238 * to compute a Position XY value, this field should match Position
3239 * ZW Interpolation Mode to ensure a consistent position.xyzw
3242 * We only require XY sample offsets. So, this recommendation doesn't
3243 * look useful at the moment. We might need this in future.
3245 ps
.PositionXYOffsetSelect
=
3246 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3247 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
3248 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
3249 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
3251 // XXX: Disable SIMD32 with 16x MSAA
3253 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3254 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
3255 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
3256 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
3257 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3258 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
3260 ps
.KernelStartPointer0
=
3261 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
3262 ps
.KernelStartPointer1
=
3263 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
3264 ps
.KernelStartPointer2
=
3265 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
3267 if (prog_data
->total_scratch
) {
3268 uint32_t scratch_addr
=
3269 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3270 MESA_SHADER_FRAGMENT
);
3271 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3272 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3276 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3277 psx
.PixelShaderValid
= true;
3278 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3279 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
3280 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3281 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3282 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3283 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3285 if (wm_prog_data
->uses_sample_mask
) {
3286 /* TODO: conservative rasterization */
3287 if (wm_prog_data
->post_depth_coverage
)
3288 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
3290 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
3293 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3294 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3295 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3302 * Compute the size of the derived data (shader command packets).
3304 * This must match the data written by the iris_store_xs_state() functions.
3307 iris_store_cs_state(struct iris_context
*ice
,
3308 const struct gen_device_info
*devinfo
,
3309 struct iris_compiled_shader
*shader
)
3311 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3312 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3313 void *map
= shader
->derived_data
;
3315 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3316 desc
.KernelStartPointer
= KSP(shader
);
3317 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3318 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3319 desc
.SharedLocalMemorySize
=
3320 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3321 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3322 desc
.CrossThreadConstantDataReadLength
=
3323 cs_prog_data
->push
.cross_thread
.regs
;
3328 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3330 assert(cache_id
<= IRIS_CACHE_BLORP
);
3332 static const unsigned dwords
[] = {
3333 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3334 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3335 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3336 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3338 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3339 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3340 [IRIS_CACHE_BLORP
] = 0,
3343 return sizeof(uint32_t) * dwords
[cache_id
];
3347 * Create any state packets corresponding to the given shader stage
3348 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3349 * This means that we can look up a program in the in-memory cache and
3350 * get most of the state packet without having to reconstruct it.
3353 iris_store_derived_program_state(struct iris_context
*ice
,
3354 enum iris_program_cache_id cache_id
,
3355 struct iris_compiled_shader
*shader
)
3357 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3358 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3362 iris_store_vs_state(ice
, devinfo
, shader
);
3364 case IRIS_CACHE_TCS
:
3365 iris_store_tcs_state(ice
, devinfo
, shader
);
3367 case IRIS_CACHE_TES
:
3368 iris_store_tes_state(ice
, devinfo
, shader
);
3371 iris_store_gs_state(ice
, devinfo
, shader
);
3374 iris_store_fs_state(ice
, devinfo
, shader
);
3377 iris_store_cs_state(ice
, devinfo
, shader
);
3378 case IRIS_CACHE_BLORP
:
3385 /* ------------------------------------------------------------------- */
3388 * Configure the URB.
3390 * XXX: write a real comment.
3393 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
3395 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
3396 const unsigned push_size_kB
= 32;
3397 unsigned entries
[4];
3401 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3402 if (!ice
->shaders
.prog
[i
]) {
3405 struct brw_vue_prog_data
*vue_prog_data
=
3406 (void *) ice
->shaders
.prog
[i
]->prog_data
;
3407 size
[i
] = vue_prog_data
->urb_entry_size
;
3409 assert(size
[i
] != 0);
3412 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
3413 1024 * ice
->shaders
.urb_size
,
3414 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
3415 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
3416 size
, entries
, start
);
3418 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3419 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
3420 urb
._3DCommandSubOpcode
+= i
;
3421 urb
.VSURBStartingAddress
= start
[i
];
3422 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
3423 urb
.VSNumberofURBEntries
= entries
[i
];
3428 static const uint32_t push_constant_opcodes
[] = {
3429 [MESA_SHADER_VERTEX
] = 21,
3430 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3431 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3432 [MESA_SHADER_GEOMETRY
] = 22,
3433 [MESA_SHADER_FRAGMENT
] = 23,
3434 [MESA_SHADER_COMPUTE
] = 0,
3438 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3440 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3442 iris_use_pinned_bo(batch
, state_bo
, false);
3444 return ice
->state
.unbound_tex
.offset
;
3448 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3450 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3451 if (!ice
->state
.null_fb
.res
)
3452 return use_null_surface(batch
, ice
);
3454 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3456 iris_use_pinned_bo(batch
, state_bo
, false);
3458 return ice
->state
.null_fb
.offset
;
3462 * Add a surface to the validation list, as well as the buffer containing
3463 * the corresponding SURFACE_STATE.
3465 * Returns the binding table entry (offset to SURFACE_STATE).
3468 use_surface(struct iris_batch
*batch
,
3469 struct pipe_surface
*p_surf
,
3472 struct iris_surface
*surf
= (void *) p_surf
;
3474 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
3475 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
3477 return surf
->surface_state
.offset
;
3481 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
3483 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
3484 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
3486 return isv
->surface_state
.offset
;
3490 use_const_buffer(struct iris_batch
*batch
,
3491 struct iris_context
*ice
,
3492 struct iris_const_buffer
*cbuf
)
3494 if (!cbuf
->surface_state
.res
)
3495 return use_null_surface(batch
, ice
);
3497 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->data
.res
), false);
3498 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->surface_state
.res
), false);
3500 return cbuf
->surface_state
.offset
;
3504 use_ssbo(struct iris_batch
*batch
, struct iris_context
*ice
,
3505 struct iris_shader_state
*shs
, int i
)
3508 return use_null_surface(batch
, ice
);
3510 struct iris_state_ref
*surf_state
= &shs
->ssbo_surface_state
[i
];
3512 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->ssbo
[i
]), true);
3513 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3515 return surf_state
->offset
;
3519 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
3520 struct iris_shader_state
*shs
, int i
)
3522 if (!shs
->image
[i
].res
)
3523 return use_null_surface(batch
, ice
);
3525 struct iris_state_ref
*surf_state
= &shs
->image
[i
].surface_state
;
3527 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->image
[i
].res
),
3528 shs
->image
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
);
3529 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3531 return surf_state
->offset
;
3534 #define push_bt_entry(addr) \
3535 assert(addr >= binder_addr); \
3536 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
3539 * Populate the binding table for a given shader stage.
3541 * This fills out the table of pointers to surfaces required by the shader,
3542 * and also adds those buffers to the validation list so the kernel can make
3543 * resident before running our batch.
3546 iris_populate_binding_table(struct iris_context
*ice
,
3547 struct iris_batch
*batch
,
3548 gl_shader_stage stage
,
3551 const struct iris_binder
*binder
= &ice
->state
.binder
;
3552 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3556 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3557 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
3559 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
3560 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
3563 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
3565 /* TCS passthrough doesn't need a binding table. */
3566 assert(stage
== MESA_SHADER_TESS_CTRL
);
3570 if (stage
== MESA_SHADER_COMPUTE
) {
3571 /* surface for gl_NumWorkGroups */
3572 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
3573 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
3574 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
3575 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
3576 push_bt_entry(grid_state
->offset
);
3579 if (stage
== MESA_SHADER_FRAGMENT
) {
3580 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3581 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
3582 if (cso_fb
->nr_cbufs
) {
3583 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
3585 cso_fb
->cbufs
[i
] ? use_surface(batch
, cso_fb
->cbufs
[i
], true)
3586 : use_null_fb_surface(batch
, ice
);
3587 push_bt_entry(addr
);
3590 uint32_t addr
= use_null_fb_surface(batch
, ice
);
3591 push_bt_entry(addr
);
3595 //assert(prog_data->binding_table.texture_start ==
3596 //(ice->state.num_textures[stage] ? s : 0xd0d0d0d0));
3598 for (int i
= 0; i
< shs
->num_textures
; i
++) {
3599 struct iris_sampler_view
*view
= shs
->textures
[i
];
3600 uint32_t addr
= view
? use_sampler_view(batch
, view
)
3601 : use_null_surface(batch
, ice
);
3602 push_bt_entry(addr
);
3605 for (int i
= 0; i
< info
->num_images
; i
++) {
3606 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
3607 push_bt_entry(addr
);
3610 const int num_ubos
= iris_get_shader_num_ubos(ice
, stage
);
3612 for (int i
= 0; i
< num_ubos
; i
++) {
3613 uint32_t addr
= use_const_buffer(batch
, ice
, &shs
->constbuf
[i
]);
3614 push_bt_entry(addr
);
3617 /* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
3618 * for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
3619 * in st_atom_storagebuf.c so it'll compact them into one range, with
3620 * SSBOs starting at info->num_abos. Ideally it'd reset num_abos to 0 too
3622 if (info
->num_abos
+ info
->num_ssbos
> 0) {
3623 for (int i
= 0; i
< IRIS_MAX_ABOS
+ info
->num_ssbos
; i
++) {
3624 uint32_t addr
= use_ssbo(batch
, ice
, shs
, i
);
3625 push_bt_entry(addr
);
3630 // XXX: not implemented yet
3631 assert(prog_data
->binding_table
.plane_start
[1] == 0xd0d0d0d0);
3632 assert(prog_data
->binding_table
.plane_start
[2] == 0xd0d0d0d0);
3637 iris_use_optional_res(struct iris_batch
*batch
,
3638 struct pipe_resource
*res
,
3642 struct iris_bo
*bo
= iris_resource_bo(res
);
3643 iris_use_pinned_bo(batch
, bo
, writeable
);
3647 /* ------------------------------------------------------------------- */
3650 * Pin any BOs which were installed by a previous batch, and restored
3651 * via the hardware logical context mechanism.
3653 * We don't need to re-emit all state every batch - the hardware context
3654 * mechanism will save and restore it for us. This includes pointers to
3655 * various BOs...which won't exist unless we ask the kernel to pin them
3656 * by adding them to the validation list.
3658 * We can skip buffers if we've re-emitted those packets, as we're
3659 * overwriting those stale pointers with new ones, and don't actually
3660 * refer to the old BOs.
3663 iris_restore_render_saved_bos(struct iris_context
*ice
,
3664 struct iris_batch
*batch
,
3665 const struct pipe_draw_info
*draw
)
3667 // XXX: whack IRIS_SHADER_DIRTY_BINDING_TABLE on new batch
3669 const uint64_t clean
= ~ice
->state
.dirty
;
3671 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
3672 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
3675 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3676 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
3679 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
3680 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
3683 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3684 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
3687 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
3688 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
3691 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3692 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
3695 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3696 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3701 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3703 for (int i
= 0; i
< 4; i
++) {
3704 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3706 if (range
->length
== 0)
3709 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3710 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3713 iris_use_pinned_bo(batch
, res
->bo
, false);
3715 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3719 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3720 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
3721 /* Re-pin any buffers referred to by the binding table. */
3722 iris_populate_binding_table(ice
, batch
, stage
, true);
3726 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3727 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3728 struct pipe_resource
*res
= shs
->sampler_table
.res
;
3730 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3733 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3734 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
3735 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3737 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3738 iris_use_pinned_bo(batch
, bo
, false);
3741 // XXX: scratch buffer
3745 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
3746 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3748 if (cso_fb
->zsbuf
) {
3749 struct iris_resource
*zres
, *sres
;
3750 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
3752 // XXX: might not be writable...
3754 iris_use_pinned_bo(batch
, zres
->bo
, true);
3756 iris_use_pinned_bo(batch
, sres
->bo
, true);
3760 if (draw
->index_size
== 0 && ice
->state
.last_res
.index_buffer
) {
3761 /* This draw didn't emit a new index buffer, so we are inheriting the
3762 * older index buffer. This draw didn't need it, but future ones may.
3764 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
3765 iris_use_pinned_bo(batch
, bo
, false);
3768 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
3769 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
3770 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
3771 struct iris_resource
*res
= (void *) cso
->resources
[i
];
3772 iris_use_pinned_bo(batch
, res
->bo
, false);
3778 iris_restore_compute_saved_bos(struct iris_context
*ice
,
3779 struct iris_batch
*batch
,
3780 const struct pipe_grid_info
*grid
)
3782 const uint64_t clean
= ~ice
->state
.dirty
;
3784 const int stage
= MESA_SHADER_COMPUTE
;
3785 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3787 if (clean
& IRIS_DIRTY_CONSTANTS_CS
) {
3788 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3791 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3792 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[0];
3794 if (range
->length
> 0) {
3795 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3796 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3799 iris_use_pinned_bo(batch
, res
->bo
, false);
3801 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3806 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
3807 /* Re-pin any buffers referred to by the binding table. */
3808 iris_populate_binding_table(ice
, batch
, stage
, true);
3811 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
3813 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
3815 if (clean
& IRIS_DIRTY_CS
) {
3816 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3818 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3819 iris_use_pinned_bo(batch
, bo
, false);
3822 // XXX: scratch buffer
3827 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
3830 iris_update_surface_base_address(struct iris_batch
*batch
,
3831 struct iris_binder
*binder
)
3833 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
3836 flush_for_state_base_change(batch
);
3838 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
3839 // XXX: sba.SurfaceStateMemoryObjectControlState = MOCS_WB;
3840 sba
.SurfaceStateBaseAddressModifyEnable
= true;
3841 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
3844 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
3848 iris_upload_dirty_render_state(struct iris_context
*ice
,
3849 struct iris_batch
*batch
,
3850 const struct pipe_draw_info
*draw
)
3852 const uint64_t dirty
= ice
->state
.dirty
;
3854 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
3857 struct iris_genx_state
*genx
= ice
->state
.genx
;
3858 struct iris_binder
*binder
= &ice
->state
.binder
;
3859 struct brw_wm_prog_data
*wm_prog_data
= (void *)
3860 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3862 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
3863 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3864 uint32_t cc_vp_address
;
3866 /* XXX: could avoid streaming for depth_clip [0,1] case. */
3867 uint32_t *cc_vp_map
=
3868 stream_state(batch
, ice
->state
.dynamic_uploader
,
3869 &ice
->state
.last_res
.cc_vp
,
3870 4 * ice
->state
.num_viewports
*
3871 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
3872 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
3874 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
3875 cso_rast
->clip_halfz
, &zmin
, &zmax
);
3876 if (cso_rast
->depth_clip_near
)
3878 if (cso_rast
->depth_clip_far
)
3881 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
3882 ccv
.MinimumDepth
= zmin
;
3883 ccv
.MaximumDepth
= zmax
;
3886 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
3889 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
3890 ptr
.CCViewportPointer
= cc_vp_address
;
3894 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3895 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
3896 ptr
.SFClipViewportPointer
=
3897 emit_state(batch
, ice
->state
.dynamic_uploader
,
3898 &ice
->state
.last_res
.sf_cl_vp
,
3899 genx
->sf_cl_vp
, 4 * GENX(SF_CLIP_VIEWPORT_length
) *
3900 ice
->state
.num_viewports
, 64);
3906 // XXX: this is only flagged at setup, we assume a static configuration
3907 if (dirty
& IRIS_DIRTY_URB
) {
3908 iris_upload_urb_config(ice
, batch
);
3911 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
3912 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
3913 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3914 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
3915 const int header_dwords
= GENX(BLEND_STATE_length
);
3916 const int rt_dwords
= cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
);
3917 uint32_t blend_offset
;
3918 uint32_t *blend_map
=
3919 stream_state(batch
, ice
->state
.dynamic_uploader
,
3920 &ice
->state
.last_res
.blend
,
3921 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
3923 uint32_t blend_state_header
;
3924 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
3925 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
3926 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
3929 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
3930 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
3932 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
3933 ptr
.BlendStatePointer
= blend_offset
;
3934 ptr
.BlendStatePointerValid
= true;
3938 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3939 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
3942 stream_state(batch
, ice
->state
.dynamic_uploader
,
3943 &ice
->state
.last_res
.color_calc
,
3944 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
3946 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
3947 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
3948 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
3949 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
3950 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
3951 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
3952 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
3954 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3955 ptr
.ColorCalcStatePointer
= cc_offset
;
3956 ptr
.ColorCalcStatePointerValid
= true;
3960 /* Upload constants for TCS passthrough. */
3961 if ((dirty
& IRIS_DIRTY_CONSTANTS_TCS
) &&
3962 ice
->shaders
.prog
[MESA_SHADER_TESS_CTRL
] &&
3963 !ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
]) {
3964 struct iris_compiled_shader
*tes_shader
= ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
3967 /* Passthrough always copies 2 vec4s, so when uploading data we ensure
3968 * it is in the right layout for TES.
3971 struct brw_tes_prog_data
*tes_prog_data
= (void *) tes_shader
->prog_data
;
3972 switch (tes_prog_data
->domain
) {
3973 case BRW_TESS_DOMAIN_QUAD
:
3974 for (int i
= 0; i
< 4; i
++)
3975 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
3976 hdr
[3] = ice
->state
.default_inner_level
[0];
3977 hdr
[2] = ice
->state
.default_inner_level
[1];
3979 case BRW_TESS_DOMAIN_TRI
:
3980 for (int i
= 0; i
< 3; i
++)
3981 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
3982 hdr
[4] = ice
->state
.default_inner_level
[0];
3984 case BRW_TESS_DOMAIN_ISOLINE
:
3985 hdr
[7] = ice
->state
.default_outer_level
[1];
3986 hdr
[6] = ice
->state
.default_outer_level
[0];
3990 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
3991 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
3992 u_upload_data(ice
->ctx
.const_uploader
, 0, sizeof(hdr
), 32,
3993 &hdr
[0], &cbuf
->data
.offset
,
3997 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3998 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4001 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4002 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4007 if (shs
->cbuf0_needs_upload
)
4008 upload_uniforms(ice
, stage
);
4010 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4012 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4013 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4015 /* The Skylake PRM contains the following restriction:
4017 * "The driver must ensure The following case does not occur
4018 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4019 * buffer 3 read length equal to zero committed followed by a
4020 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4023 * To avoid this, we program the buffers in the highest slots.
4024 * This way, slot 0 is only used if slot 3 is also used.
4028 for (int i
= 3; i
>= 0; i
--) {
4029 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4031 if (range
->length
== 0)
4034 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4035 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
4037 assert(cbuf
->data
.offset
% 32 == 0);
4039 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4040 pkt
.ConstantBody
.Buffer
[n
] =
4041 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->data
.offset
)
4042 : ro_bo(batch
->screen
->workaround_bo
, 0);
4049 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4050 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4051 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4052 ptr
._3DCommandSubOpcode
= 38 + stage
;
4053 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4058 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4059 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4060 iris_populate_binding_table(ice
, batch
, stage
, false);
4064 if (ice
->state
.need_border_colors
)
4065 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4067 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4068 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4069 !ice
->shaders
.prog
[stage
])
4072 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4073 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4075 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4077 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4078 ptr
._3DCommandSubOpcode
= 43 + stage
;
4079 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4083 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4084 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4086 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4087 if (ice
->state
.framebuffer
.samples
> 0)
4088 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4092 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4093 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4094 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
4098 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4099 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4102 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4105 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4106 iris_use_pinned_bo(batch
, cache
->bo
, false);
4107 iris_batch_emit(batch
, shader
->derived_data
,
4108 iris_derived_program_state_size(stage
));
4110 if (stage
== MESA_SHADER_TESS_EVAL
) {
4111 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4112 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4113 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4114 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4115 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4120 if (ice
->state
.streamout_active
) {
4121 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4122 iris_batch_emit(batch
, genx
->so_buffers
,
4123 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4124 for (int i
= 0; i
< 4; i
++) {
4125 struct iris_stream_output_target
*tgt
=
4126 (void *) ice
->state
.so_target
[i
];
4128 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4130 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4136 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
4137 uint32_t *decl_list
=
4138 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
4139 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
4142 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4143 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4145 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
4146 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
4147 sol
.SOFunctionEnable
= true;
4148 sol
.SOStatisticsEnable
= true;
4150 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
4151 !ice
->state
.prims_generated_query_active
;
4152 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
4155 assert(ice
->state
.streamout
);
4157 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
4158 GENX(3DSTATE_STREAMOUT_length
));
4161 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4162 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
4166 if (dirty
& IRIS_DIRTY_CLIP
) {
4167 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4168 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4170 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
4171 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
4172 if (wm_prog_data
->barycentric_interp_modes
&
4173 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
4174 cl
.NonPerspectiveBarycentricEnable
= true;
4176 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
4177 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
4179 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
4180 ARRAY_SIZE(cso_rast
->clip
));
4183 if (dirty
& IRIS_DIRTY_RASTER
) {
4184 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4185 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
4186 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
4190 /* XXX: FS program updates needs to flag IRIS_DIRTY_WM */
4191 if (dirty
& IRIS_DIRTY_WM
) {
4192 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4193 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
4195 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
4196 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4198 wm
.BarycentricInterpolationMode
=
4199 wm_prog_data
->barycentric_interp_modes
;
4201 if (wm_prog_data
->early_fragment_tests
)
4202 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
4203 else if (wm_prog_data
->has_side_effects
)
4204 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
4206 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
4209 if (dirty
& IRIS_DIRTY_SBE
) {
4210 iris_emit_sbe(batch
, ice
);
4213 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
4214 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4215 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4216 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
4217 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
4218 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
4219 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4222 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
4223 ARRAY_SIZE(cso_blend
->ps_blend
));
4226 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
4227 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4228 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4230 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
4231 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
4232 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4233 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4235 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
4238 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
4239 uint32_t scissor_offset
=
4240 emit_state(batch
, ice
->state
.dynamic_uploader
,
4241 &ice
->state
.last_res
.scissor
,
4242 ice
->state
.scissors
,
4243 sizeof(struct pipe_scissor_state
) *
4244 ice
->state
.num_viewports
, 32);
4246 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
4247 ptr
.ScissorRectPointer
= scissor_offset
;
4251 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
4252 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4253 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
4255 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
4257 if (cso_fb
->zsbuf
) {
4258 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
4259 // XXX: depth might not be writable...
4260 iris_use_pinned_bo(batch
, zres
->bo
, true);
4264 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
4265 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
4266 for (int i
= 0; i
< 32; i
++) {
4267 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
4272 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
4273 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4274 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
4277 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
4278 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
4279 topo
.PrimitiveTopologyType
=
4280 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
4284 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4285 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
4286 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
4288 if (cso
->num_buffers
> 0) {
4289 iris_batch_emit(batch
, cso
->vertex_buffers
, sizeof(uint32_t) *
4290 (1 + vb_dwords
* cso
->num_buffers
));
4292 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
4293 struct iris_resource
*res
= (void *) cso
->resources
[i
];
4295 iris_use_pinned_bo(batch
, res
->bo
, false);
4300 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
4301 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4302 const unsigned entries
= MAX2(cso
->count
, 1);
4303 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
4304 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
4305 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
4306 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
4309 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
4310 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
4311 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
4312 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4314 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
4315 if (vs_prog_data
->uses_vertexid
) {
4316 sgv
.VertexIDEnable
= true;
4317 sgv
.VertexIDComponentNumber
= 2;
4318 sgv
.VertexIDElementOffset
= cso
->count
;
4321 if (vs_prog_data
->uses_instanceid
) {
4322 sgv
.InstanceIDEnable
= true;
4323 sgv
.InstanceIDComponentNumber
= 3;
4324 sgv
.InstanceIDElementOffset
= cso
->count
;
4329 if (dirty
& IRIS_DIRTY_VF
) {
4330 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
4331 if (draw
->primitive_restart
) {
4332 vf
.IndexedDrawCutIndexEnable
= true;
4333 vf
.CutIndex
= draw
->restart_index
;
4338 // XXX: Gen8 - PMA fix
4342 iris_upload_render_state(struct iris_context
*ice
,
4343 struct iris_batch
*batch
,
4344 const struct pipe_draw_info
*draw
)
4346 /* Always pin the binder. If we're emitting new binding table pointers,
4347 * we need it. If not, we're probably inheriting old tables via the
4348 * context, and need it anyway. Since true zero-bindings cases are
4349 * practically non-existent, just pin it and avoid last_res tracking.
4351 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
4353 iris_upload_dirty_render_state(ice
, batch
, draw
);
4355 if (draw
->index_size
> 0) {
4358 if (draw
->has_user_indices
) {
4359 u_upload_data(ice
->ctx
.stream_uploader
, 0,
4360 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
4361 &offset
, &ice
->state
.last_res
.index_buffer
);
4363 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
4364 draw
->index
.resource
);
4368 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4370 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
4371 ib
.IndexFormat
= draw
->index_size
>> 1;
4373 ib
.BufferSize
= bo
->size
;
4374 ib
.BufferStartingAddress
= ro_bo(bo
, offset
);
4378 #define _3DPRIM_END_OFFSET 0x2420
4379 #define _3DPRIM_START_VERTEX 0x2430
4380 #define _3DPRIM_VERTEX_COUNT 0x2434
4381 #define _3DPRIM_INSTANCE_COUNT 0x2438
4382 #define _3DPRIM_START_INSTANCE 0x243C
4383 #define _3DPRIM_BASE_VERTEX 0x2440
4385 if (draw
->indirect
) {
4386 /* We don't support this MultidrawIndirect. */
4387 assert(!draw
->indirect
->indirect_draw_count
);
4389 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
4392 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4393 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
4394 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
4396 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4397 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
4398 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
4400 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4401 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
4402 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
4404 if (draw
->index_size
) {
4405 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4406 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
4407 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4409 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4410 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4411 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
4414 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4415 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4416 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4418 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
4419 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
4425 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
4426 prim
.StartInstanceLocation
= draw
->start_instance
;
4427 prim
.InstanceCount
= draw
->instance_count
;
4428 prim
.VertexCountPerInstance
= draw
->count
;
4429 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
4431 // XXX: this is probably bonkers.
4432 prim
.StartVertexLocation
= draw
->start
;
4434 prim
.IndirectParameterEnable
= draw
->indirect
!= NULL
;
4436 if (draw
->index_size
) {
4437 prim
.BaseVertexLocation
+= draw
->index_bias
;
4439 prim
.StartVertexLocation
+= draw
->index_bias
;
4442 //prim.BaseVertexLocation = ...;
4445 if (!batch
->contains_draw
) {
4446 iris_restore_render_saved_bos(ice
, batch
, draw
);
4447 batch
->contains_draw
= true;
4452 iris_upload_compute_state(struct iris_context
*ice
,
4453 struct iris_batch
*batch
,
4454 const struct pipe_grid_info
*grid
)
4456 const uint64_t dirty
= ice
->state
.dirty
;
4457 struct iris_screen
*screen
= batch
->screen
;
4458 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
4459 struct iris_binder
*binder
= &ice
->state
.binder
;
4460 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
4461 struct iris_compiled_shader
*shader
=
4462 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
4463 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4464 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
4466 // XXX: L3 configuration not set up for SLM
4467 assert(prog_data
->total_shared
== 0);
4469 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
4470 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
4472 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
4473 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
4475 if (ice
->state
.need_border_colors
)
4476 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4478 if (dirty
& IRIS_DIRTY_CS
) {
4479 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4481 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4482 * the only bits that are changed are scoreboard related: Scoreboard
4483 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
4484 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4487 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
4489 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4490 if (prog_data
->total_scratch
) {
4491 uint32_t scratch_addr
=
4492 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
4493 MESA_SHADER_COMPUTE
);
4494 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
4495 vfe
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
4498 vfe
.MaximumNumberofThreads
=
4499 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
4501 vfe
.ResetGatewayTimer
=
4502 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4505 vfe
.NumberofURBEntries
= 2;
4506 vfe
.URBEntryAllocationSize
= 2;
4508 // XXX: Use Indirect Payload Storage?
4509 vfe
.CURBEAllocationSize
=
4510 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4511 cs_prog_data
->push
.cross_thread
.regs
, 2);
4515 // XXX: hack iris_set_constant_buffers to upload these thread counts
4516 // XXX: along with regular uniforms for compute shaders, somehow.
4518 uint32_t curbe_data_offset
= 0;
4519 // TODO: Move subgroup-id into uniforms ubo so we can push uniforms
4520 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
4521 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
4522 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
4523 struct pipe_resource
*curbe_data_res
= NULL
;
4524 uint32_t *curbe_data_map
=
4525 stream_state(batch
, ice
->state
.dynamic_uploader
, &curbe_data_res
,
4526 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
4527 &curbe_data_offset
);
4528 assert(curbe_data_map
);
4529 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
4530 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
4532 if (dirty
& IRIS_DIRTY_CONSTANTS_CS
) {
4533 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4534 curbe
.CURBETotalDataLength
=
4535 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4536 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
4540 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
4541 IRIS_DIRTY_BINDINGS_CS
|
4542 IRIS_DIRTY_CONSTANTS_CS
|
4544 struct pipe_resource
*desc_res
= NULL
;
4545 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4547 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
4548 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
4549 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
4550 idd
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
4551 idd
.CrossThreadConstantDataReadLength
=
4552 cs_prog_data
->push
.cross_thread
.regs
;
4555 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
4556 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
4558 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4559 load
.InterfaceDescriptorTotalLength
=
4560 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4561 load
.InterfaceDescriptorDataStartAddress
=
4562 emit_state(batch
, ice
->state
.dynamic_uploader
,
4563 &desc_res
, desc
, sizeof(desc
), 32);
4566 pipe_resource_reference(&desc_res
, NULL
);
4569 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
4570 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
4571 uint32_t right_mask
;
4574 right_mask
= ~0u >> (32 - remainder
);
4576 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
4578 #define GPGPU_DISPATCHDIMX 0x2500
4579 #define GPGPU_DISPATCHDIMY 0x2504
4580 #define GPGPU_DISPATCHDIMZ 0x2508
4582 if (grid
->indirect
) {
4583 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
4584 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
4585 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4586 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
4587 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
4589 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4590 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
4591 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
4593 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4594 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
4595 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
4599 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
4600 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
4601 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
4602 ggw
.ThreadDepthCounterMaximum
= 0;
4603 ggw
.ThreadHeightCounterMaximum
= 0;
4604 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
4605 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
4606 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
4607 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
4608 ggw
.RightExecutionMask
= right_mask
;
4609 ggw
.BottomExecutionMask
= 0xffffffff;
4612 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4614 if (!batch
->contains_draw
) {
4615 iris_restore_compute_saved_bos(ice
, batch
, grid
);
4616 batch
->contains_draw
= true;
4621 * State module teardown.
4624 iris_destroy_state(struct iris_context
*ice
)
4626 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
4628 // XXX: unreference resources/surfaces.
4629 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
4630 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
4632 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
4634 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
4635 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4636 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
4638 free(ice
->state
.genx
);
4640 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
4641 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
4642 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
4643 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
4644 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
4645 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
4648 /* ------------------------------------------------------------------- */
4651 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
4654 _iris_emit_lri(batch
, reg
, val
);
4658 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
4661 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
4662 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
4666 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
4669 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
4670 struct iris_bo
*bo
, uint32_t offset
)
4672 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4673 lrm
.RegisterAddress
= reg
;
4674 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
4679 * Load a 64-bit value from a buffer into a MMIO register via
4680 * two MI_LOAD_REGISTER_MEM commands.
4683 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
4684 struct iris_bo
*bo
, uint32_t offset
)
4686 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
4687 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
4691 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
4692 struct iris_bo
*bo
, uint32_t offset
,
4695 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
4696 srm
.RegisterAddress
= reg
;
4697 srm
.MemoryAddress
= rw_bo(bo
, offset
);
4698 srm
.PredicateEnable
= predicated
;
4703 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
4704 struct iris_bo
*bo
, uint32_t offset
,
4707 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
4708 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
4712 iris_store_data_imm32(struct iris_batch
*batch
,
4713 struct iris_bo
*bo
, uint32_t offset
,
4716 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
4717 sdi
.Address
= rw_bo(bo
, offset
);
4718 sdi
.ImmediateData
= imm
;
4723 iris_store_data_imm64(struct iris_batch
*batch
,
4724 struct iris_bo
*bo
, uint32_t offset
,
4727 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
4728 * 2 in genxml but it's actually variable length and we need 5 DWords.
4730 void *map
= iris_get_command_space(batch
, 4 * 5);
4731 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
4732 sdi
.DWordLength
= 5 - 2;
4733 sdi
.Address
= rw_bo(bo
, offset
);
4734 sdi
.ImmediateData
= imm
;
4739 iris_copy_mem_mem(struct iris_batch
*batch
,
4740 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
4741 struct iris_bo
*src_bo
, uint32_t src_offset
,
4744 /* MI_COPY_MEM_MEM operates on DWords. */
4745 assert(bytes
% 4 == 0);
4746 assert(dst_offset
% 4 == 0);
4747 assert(src_offset
% 4 == 0);
4749 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
4750 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
4751 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
4752 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
4757 /* ------------------------------------------------------------------- */
4760 flags_to_post_sync_op(uint32_t flags
)
4762 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
4763 return WriteImmediateData
;
4765 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
4766 return WritePSDepthCount
;
4768 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
4769 return WriteTimestamp
;
4775 * Do the given flags have a Post Sync or LRI Post Sync operation?
4777 static enum pipe_control_flags
4778 get_post_sync_flags(enum pipe_control_flags flags
)
4780 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
4781 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
4782 PIPE_CONTROL_WRITE_TIMESTAMP
|
4783 PIPE_CONTROL_LRI_POST_SYNC_OP
;
4785 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
4786 * "LRI Post Sync Operation". So more than one bit set would be illegal.
4788 assert(util_bitcount(flags
) <= 1);
4793 // XXX: compute support
4794 #define IS_COMPUTE_PIPELINE(batch) (batch->engine != I915_EXEC_RENDER)
4797 * Emit a series of PIPE_CONTROL commands, taking into account any
4798 * workarounds necessary to actually accomplish the caller's request.
4800 * Unless otherwise noted, spec quotations in this function come from:
4802 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
4803 * Restrictions for PIPE_CONTROL.
4805 * You should not use this function directly. Use the helpers in
4806 * iris_pipe_control.c instead, which may split the pipe control further.
4809 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
4810 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
4812 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
4813 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
4814 enum pipe_control_flags non_lri_post_sync_flags
=
4815 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
4817 /* Recursive PIPE_CONTROL workarounds --------------------------------
4818 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
4820 * We do these first because we want to look at the original operation,
4821 * rather than any workarounds we set.
4823 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
4824 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
4825 * lists several workarounds:
4827 * "Project: SKL, KBL, BXT
4829 * If the VF Cache Invalidation Enable is set to a 1 in a
4830 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
4831 * sets to 0, with the VF Cache Invalidation Enable set to 0
4832 * needs to be sent prior to the PIPE_CONTROL with VF Cache
4833 * Invalidation Enable set to a 1."
4835 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
4838 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
4839 /* Project: SKL / Argument: LRI Post Sync Operation [23]
4841 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
4842 * programmed prior to programming a PIPECONTROL command with "LRI
4843 * Post Sync Operation" in GPGPU mode of operation (i.e when
4844 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
4846 * The same text exists a few rows below for Post Sync Op.
4848 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
4851 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
4853 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
4854 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
4855 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
4857 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
4861 /* "Flush Types" workarounds ---------------------------------------------
4862 * We do these now because they may add post-sync operations or CS stalls.
4865 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
4866 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
4868 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
4869 * 'Write PS Depth Count' or 'Write Timestamp'."
4872 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
4873 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
4874 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
4875 bo
= batch
->screen
->workaround_bo
;
4879 /* #1130 from Gen10 workarounds page:
4881 * "Enable Depth Stall on every Post Sync Op if Render target Cache
4882 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
4883 * board stall if Render target cache flush is enabled."
4885 * Applicable to CNL B0 and C0 steppings only.
4887 * The wording here is unclear, and this workaround doesn't look anything
4888 * like the internal bug report recommendations, but leave it be for now...
4890 if (GEN_GEN
== 10) {
4891 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
4892 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
4893 } else if (flags
& non_lri_post_sync_flags
) {
4894 flags
|= PIPE_CONTROL_DEPTH_STALL
;
4898 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
4899 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
4901 * "This bit must be DISABLED for operations other than writing
4904 * This seems like nonsense. An Ivybridge workaround requires us to
4905 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
4906 * operation. Gen8+ requires us to emit depth stalls and depth cache
4907 * flushes together. So, it's hard to imagine this means anything other
4908 * than "we originally intended this to be used for PS_DEPTH_COUNT".
4910 * We ignore the supposed restriction and do nothing.
4914 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
4915 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
4916 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
4918 * "This bit must be DISABLED for End-of-pipe (Read) fences,
4919 * PS_DEPTH_COUNT or TIMESTAMP queries."
4921 * TODO: Implement end-of-pipe checking.
4923 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
4924 PIPE_CONTROL_WRITE_TIMESTAMP
)));
4927 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
4928 /* From the PIPE_CONTROL instruction table, bit 1:
4930 * "This bit is ignored if Depth Stall Enable is set.
4931 * Further, the render cache is not flushed even if Write Cache
4932 * Flush Enable bit is set."
4934 * We assert that the caller doesn't do this combination, to try and
4935 * prevent mistakes. It shouldn't hurt the GPU, though.
4937 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
4938 * and "Render Target Flush" combo is explicitly required for BTI
4939 * update workarounds.
4941 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
4942 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
4945 /* PIPE_CONTROL page workarounds ------------------------------------- */
4947 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
4948 /* From the PIPE_CONTROL page itself:
4951 * Restriction: Pipe_control with CS-stall bit set must be issued
4952 * before a pipe-control command that has the State Cache
4953 * Invalidate bit set."
4955 flags
|= PIPE_CONTROL_CS_STALL
;
4958 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
4959 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
4962 * SW must always program Post-Sync Operation to "Write Immediate
4963 * Data" when Flush LLC is set."
4965 * For now, we just require the caller to do it.
4967 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
4970 /* "Post-Sync Operation" workarounds -------------------------------- */
4972 /* Project: All / Argument: Global Snapshot Count Reset [19]
4974 * "This bit must not be exercised on any product.
4975 * Requires stall bit ([20] of DW1) set."
4977 * We don't use this, so we just assert that it isn't used. The
4978 * PIPE_CONTROL instruction page indicates that they intended this
4979 * as a debug feature and don't think it is useful in production,
4980 * but it may actually be usable, should we ever want to.
4982 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
4984 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
4985 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
4986 /* Project: All / Arguments:
4988 * - Generic Media State Clear [16]
4989 * - Indirect State Pointers Disable [16]
4991 * "Requires stall bit ([20] of DW1) set."
4993 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
4994 * State Clear) says:
4996 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
4997 * programmed prior to programming a PIPECONTROL command with "Media
4998 * State Clear" set in GPGPU mode of operation"
5000 * This is a subset of the earlier rule, so there's nothing to do.
5002 flags
|= PIPE_CONTROL_CS_STALL
;
5005 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
5006 /* Project: All / Argument: Store Data Index
5008 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5011 * For now, we just assert that the caller does this. We might want to
5012 * automatically add a write to the workaround BO...
5014 assert(non_lri_post_sync_flags
!= 0);
5017 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
5018 /* Project: All / Argument: Sync GFDT
5020 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5021 * than '0' or 0x2520[13] must be set."
5023 * For now, we just assert that the caller does this.
5025 assert(non_lri_post_sync_flags
!= 0);
5028 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
5029 /* Project: IVB+ / Argument: TLB inv
5031 * "Requires stall bit ([20] of DW1) set."
5033 * Also, from the PIPE_CONTROL instruction table:
5036 * Post Sync Operation or CS stall must be set to ensure a TLB
5037 * invalidation occurs. Otherwise no cycle will occur to the TLB
5038 * cache to invalidate."
5040 * This is not a subset of the earlier rule, so there's nothing to do.
5042 flags
|= PIPE_CONTROL_CS_STALL
;
5045 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
5046 /* TODO: The big Skylake GT4 post sync op workaround */
5049 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
5051 if (IS_COMPUTE_PIPELINE(batch
)) {
5052 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
5053 /* Project: SKL+ / Argument: Tex Invalidate
5054 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
5056 flags
|= PIPE_CONTROL_CS_STALL
;
5059 if (GEN_GEN
== 8 && (post_sync_flags
||
5060 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
5061 PIPE_CONTROL_DEPTH_STALL
|
5062 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5063 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5064 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
5065 /* Project: BDW / Arguments:
5067 * - LRI Post Sync Operation [23]
5068 * - Post Sync Op [15:14]
5070 * - Depth Stall [13]
5071 * - Render Target Cache Flush [12]
5072 * - Depth Cache Flush [0]
5073 * - DC Flush Enable [5]
5075 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
5078 flags
|= PIPE_CONTROL_CS_STALL
;
5080 /* Also, from the PIPE_CONTROL instruction table, bit 20:
5083 * This bit must be always set when PIPE_CONTROL command is
5084 * programmed by GPGPU and MEDIA workloads, except for the cases
5085 * when only Read Only Cache Invalidation bits are set (State
5086 * Cache Invalidation Enable, Instruction cache Invalidation
5087 * Enable, Texture Cache Invalidation Enable, Constant Cache
5088 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
5089 * need not implemented when FF_DOP_CG is disable via "Fixed
5090 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
5092 * It sounds like we could avoid CS stalls in some cases, but we
5093 * don't currently bother. This list isn't exactly the list above,
5099 /* "Stall" workarounds ----------------------------------------------
5100 * These have to come after the earlier ones because we may have added
5101 * some additional CS stalls above.
5104 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
5105 /* Project: PRE-SKL, VLV, CHV
5107 * "[All Stepping][All SKUs]:
5109 * One of the following must also be set:
5111 * - Render Target Cache Flush Enable ([12] of DW1)
5112 * - Depth Cache Flush Enable ([0] of DW1)
5113 * - Stall at Pixel Scoreboard ([1] of DW1)
5114 * - Depth Stall ([13] of DW1)
5115 * - Post-Sync Operation ([13] of DW1)
5116 * - DC Flush Enable ([5] of DW1)"
5118 * If we don't already have one of those bits set, we choose to add
5119 * "Stall at Pixel Scoreboard". Some of the other bits require a
5120 * CS stall as a workaround (see above), which would send us into
5121 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
5122 * appears to be safe, so we choose that.
5124 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5125 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5126 PIPE_CONTROL_WRITE_IMMEDIATE
|
5127 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5128 PIPE_CONTROL_WRITE_TIMESTAMP
|
5129 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
5130 PIPE_CONTROL_DEPTH_STALL
|
5131 PIPE_CONTROL_DATA_CACHE_FLUSH
;
5132 if (!(flags
& wa_bits
))
5133 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5136 /* Emit --------------------------------------------------------------- */
5138 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
5139 pc
.LRIPostSyncOperation
= NoLRIOperation
;
5140 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
5141 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
5142 pc
.StoreDataIndex
= 0;
5143 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
5144 pc
.GlobalSnapshotCountReset
=
5145 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
5146 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
5147 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
5148 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5149 pc
.RenderTargetCacheFlushEnable
=
5150 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
5151 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
5152 pc
.StateCacheInvalidationEnable
=
5153 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
5154 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
5155 pc
.ConstantCacheInvalidationEnable
=
5156 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
5157 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
5158 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
5159 pc
.InstructionCacheInvalidateEnable
=
5160 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
5161 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
5162 pc
.IndirectStatePointersDisable
=
5163 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
5164 pc
.TextureCacheInvalidationEnable
=
5165 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
5166 pc
.Address
= rw_bo(bo
, offset
);
5167 pc
.ImmediateData
= imm
;
5172 genX(init_state
)(struct iris_context
*ice
)
5174 struct pipe_context
*ctx
= &ice
->ctx
;
5175 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
5177 ctx
->create_blend_state
= iris_create_blend_state
;
5178 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
5179 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
5180 ctx
->create_sampler_state
= iris_create_sampler_state
;
5181 ctx
->create_sampler_view
= iris_create_sampler_view
;
5182 ctx
->create_surface
= iris_create_surface
;
5183 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
5184 ctx
->bind_blend_state
= iris_bind_blend_state
;
5185 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
5186 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
5187 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
5188 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
5189 ctx
->delete_blend_state
= iris_delete_state
;
5190 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
5191 ctx
->delete_fs_state
= iris_delete_state
;
5192 ctx
->delete_rasterizer_state
= iris_delete_state
;
5193 ctx
->delete_sampler_state
= iris_delete_state
;
5194 ctx
->delete_vertex_elements_state
= iris_delete_state
;
5195 ctx
->delete_tcs_state
= iris_delete_state
;
5196 ctx
->delete_tes_state
= iris_delete_state
;
5197 ctx
->delete_gs_state
= iris_delete_state
;
5198 ctx
->delete_vs_state
= iris_delete_state
;
5199 ctx
->set_blend_color
= iris_set_blend_color
;
5200 ctx
->set_clip_state
= iris_set_clip_state
;
5201 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
5202 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
5203 ctx
->set_shader_images
= iris_set_shader_images
;
5204 ctx
->set_sampler_views
= iris_set_sampler_views
;
5205 ctx
->set_tess_state
= iris_set_tess_state
;
5206 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
5207 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
5208 ctx
->set_sample_mask
= iris_set_sample_mask
;
5209 ctx
->set_scissor_states
= iris_set_scissor_states
;
5210 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
5211 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
5212 ctx
->set_viewport_states
= iris_set_viewport_states
;
5213 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
5214 ctx
->surface_destroy
= iris_surface_destroy
;
5215 ctx
->draw_vbo
= iris_draw_vbo
;
5216 ctx
->launch_grid
= iris_launch_grid
;
5217 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
5218 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
5219 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
5221 ice
->vtbl
.destroy_state
= iris_destroy_state
;
5222 ice
->vtbl
.init_render_context
= iris_init_render_context
;
5223 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
5224 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
5225 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
5226 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
5227 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
5228 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
5229 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
5230 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
5231 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
5232 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
5233 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
5234 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
5235 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
5236 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
5237 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
5238 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
5239 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
5240 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
5241 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
5242 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
5243 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
5244 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
5245 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
5247 ice
->state
.dirty
= ~0ull;
5249 ice
->state
.statistics_counters_enabled
= true;
5251 ice
->state
.sample_mask
= 0xffff;
5252 ice
->state
.num_viewports
= 1;
5253 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
5255 /* Make a 1x1x1 null surface for unbound textures */
5256 void *null_surf_map
=
5257 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
5258 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
5259 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
5260 ice
->state
.unbound_tex
.offset
+=
5261 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
5263 /* Default all scissor rectangles to be empty regions. */
5264 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
5265 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
5266 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,