2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "intel/common/gen_sample_positions.h"
43 #include "iris_batch.h"
44 #include "iris_context.h"
45 #include "iris_pipe.h"
46 #include "iris_resource.h"
48 #define __gen_address_type struct iris_address
49 #define __gen_user_data struct iris_batch
52 __gen_combine_address(struct iris_batch
*batch
, void *location
,
53 struct iris_address addr
, uint32_t delta
)
56 return addr
.offset
+ delta
;
58 return iris_batch_reloc(batch
, location
- batch
->cmdbuf
.map
, addr
.bo
,
59 addr
.offset
+ delta
, addr
.reloc_flags
);
62 #define __genxml_cmd_length(cmd) cmd ## _length
63 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
64 #define __genxml_cmd_header(cmd) cmd ## _header
65 #define __genxml_cmd_pack(cmd) cmd ## _pack
68 get_command_space(struct iris_batch
*batch
, unsigned bytes
)
70 iris_require_command_space(batch
, bytes
);
71 void *map
= batch
->cmdbuf
.map_next
;
72 batch
->cmdbuf
.map_next
+= bytes
;
76 #define iris_pack_command(cmd, dst, name) \
77 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
78 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
79 ({ __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name); \
83 #define iris_pack_state(cmd, dst, name) \
84 for (struct cmd name = {}, \
85 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
86 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
89 #define iris_emit_cmd(batch, cmd, name) \
90 iris_pack_command(cmd, get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
92 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
94 uint32_t *dw = get_command_space(batch, 4 * num_dwords); \
95 for (uint32_t i = 0; i < num_dwords; i++) \
96 dw[i] = (dwords0)[i] | (dwords1)[i]; \
97 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
100 #define iris_emit_with_addr(batch, dwords, num_dw, addr_field, addr) \
102 STATIC_ASSERT((GENX(addr_field) % 64) == 0); \
103 assert(num_dw <= ARRAY_SIZE(dwords)); \
104 int addr_idx = GENX(addr_field) / 32; \
105 uint32_t *dw = get_command_space(batch, 4 * num_dw); \
106 for (uint32_t i = 0; i < addr_idx; i++) { \
107 dw[i] = (dwords)[i]; \
109 uint64_t *qw = (uint64_t *) &dw[addr_idx]; \
110 qw = iris_batch_reloc(batch, qw - batch->cmdbuf.map, addr.bo, \
111 addr.offset + (dwords)[addr_idx + 1], \
113 for (uint32_t i = addr_idx + 1; i < num_dw; i++) { \
114 dw[i] = (dwords)[i]; \
116 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dw * 4)); \
119 #include "genxml/genX_pack.h"
120 #include "genxml/gen_macros.h"
121 #include "genxml/genX_bits.h"
123 #define MOCS_WB (2 << 1)
125 UNUSED
static void pipe_asserts()
127 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
129 /* pipe_logicop happens to match the hardware. */
130 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
131 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
132 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
133 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
134 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
135 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
136 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
137 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
138 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
139 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
140 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
141 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
142 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
143 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
144 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
145 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
147 /* pipe_blend_func happens to match the hardware. */
148 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
149 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
150 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
151 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
152 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
153 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
160 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
161 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
162 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
163 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
164 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
165 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
166 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
168 /* pipe_blend_func happens to match the hardware. */
169 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
170 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
171 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
172 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
173 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
175 /* pipe_stencil_op happens to match the hardware. */
176 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
177 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
178 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
179 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
180 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
181 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
182 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
183 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
188 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
190 static const unsigned map
[] = {
191 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
192 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
193 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
194 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
195 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
196 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
197 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
198 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
199 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
200 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
201 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
202 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
203 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
204 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
205 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
208 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
212 translate_compare_func(enum pipe_compare_func pipe_func
)
214 static const unsigned map
[] = {
215 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
216 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
217 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
218 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
219 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
220 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
221 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
222 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
224 return map
[pipe_func
];
228 translate_shadow_func(enum pipe_compare_func pipe_func
)
230 /* Gallium specifies the result of shadow comparisons as:
232 * 1 if ref <op> texel,
237 * 0 if texel <op> ref,
240 * So we need to flip the operator and also negate.
242 static const unsigned map
[] = {
243 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
244 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
245 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
246 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
247 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
248 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
249 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
250 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
252 return map
[pipe_func
];
256 translate_cull_mode(unsigned pipe_face
)
258 static const unsigned map
[4] = {
259 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
260 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
261 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
262 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
264 return map
[pipe_face
];
268 translate_fill_mode(unsigned pipe_polymode
)
270 static const unsigned map
[4] = {
271 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
272 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
273 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
274 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
276 return map
[pipe_polymode
];
279 static struct iris_address
280 ro_bo(struct iris_bo
*bo
, uint32_t offset
)
282 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
286 iris_upload_initial_gpu_state(struct iris_context
*ice
,
287 struct iris_batch
*batch
)
289 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
290 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
291 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
293 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
294 GEN_SAMPLE_POS_1X(pat
._1xSample
);
295 GEN_SAMPLE_POS_2X(pat
._2xSample
);
296 GEN_SAMPLE_POS_4X(pat
._4xSample
);
297 GEN_SAMPLE_POS_8X(pat
._8xSample
);
298 GEN_SAMPLE_POS_16X(pat
._16xSample
);
300 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
301 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
302 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
303 /* XXX: may need to set an offset for origin-UL framebuffers */
304 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
306 /* Just assign a static partitioning. */
307 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
308 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
309 alloc
._3DCommandSubOpcode
= 18 + i
;
310 alloc
.ConstantBufferOffset
= 6 * i
;
311 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
317 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
322 iris_set_blend_color(struct pipe_context
*ctx
,
323 const struct pipe_blend_color
*state
)
325 struct iris_context
*ice
= (struct iris_context
*) ctx
;
327 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
328 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
331 struct iris_blend_state
{
332 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
333 uint32_t blend_state
[GENX(BLEND_STATE_length
)];
334 uint32_t blend_entries
[BRW_MAX_DRAW_BUFFERS
*
335 GENX(BLEND_STATE_ENTRY_length
)];
339 iris_create_blend_state(struct pipe_context
*ctx
,
340 const struct pipe_blend_state
*state
)
342 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
344 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
345 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
346 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
347 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
348 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
349 bs
.ColorDitherEnable
= state
->dither
;
350 //bs.AlphaTestEnable = <comes from alpha state> :(
351 //bs.AlphaTestFunction = <comes from alpha state> :(
354 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
355 //pb.HasWriteableRT = <comes from somewhere> :(
356 //pb.AlphaTestEnable = <comes from alpha state> :(
357 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
358 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
360 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
362 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
363 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
364 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
365 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
368 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
369 iris_pack_state(GENX(BLEND_STATE_ENTRY
), &cso
->blend_entries
[i
], be
) {
370 be
.LogicOpEnable
= state
->logicop_enable
;
371 be
.LogicOpFunction
= state
->logicop_func
;
373 be
.PreBlendSourceOnlyClampEnable
= false;
374 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
375 be
.PreBlendColorClampEnable
= true;
376 be
.PostBlendColorClampEnable
= true;
378 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
380 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
381 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
382 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
383 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
384 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
385 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
387 be
.WriteDisableRed
= state
->rt
[i
].colormask
& PIPE_MASK_R
;
388 be
.WriteDisableGreen
= state
->rt
[i
].colormask
& PIPE_MASK_G
;
389 be
.WriteDisableBlue
= state
->rt
[i
].colormask
& PIPE_MASK_B
;
390 be
.WriteDisableAlpha
= state
->rt
[i
].colormask
& PIPE_MASK_A
;
398 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
400 struct iris_context
*ice
= (struct iris_context
*) ctx
;
401 ice
->state
.cso_blend
= state
;
402 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
403 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
406 struct iris_depth_stencil_alpha_state
{
407 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
408 uint32_t cc_vp
[GENX(CC_VIEWPORT_length
)];
410 struct pipe_alpha_state alpha
; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
414 iris_create_zsa_state(struct pipe_context
*ctx
,
415 const struct pipe_depth_stencil_alpha_state
*state
)
417 struct iris_depth_stencil_alpha_state
*cso
=
418 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
420 cso
->alpha
= state
->alpha
;
422 bool two_sided_stencil
= state
->stencil
[1].enabled
;
424 /* The state tracker needs to optimize away EQUAL writes for us. */
425 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
427 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
428 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
429 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
430 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
431 wmds
.StencilTestFunction
=
432 translate_compare_func(state
->stencil
[0].func
);
433 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
434 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
435 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
436 wmds
.BackfaceStencilTestFunction
=
437 translate_compare_func(state
->stencil
[1].func
);
438 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
439 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
440 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
441 wmds
.StencilBufferWriteEnable
=
442 state
->stencil
[0].writemask
!= 0 ||
443 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
444 wmds
.DepthTestEnable
= state
->depth
.enabled
;
445 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
446 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
447 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
448 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
449 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
450 /* wmds.[Backface]StencilReferenceValue are merged later */
453 iris_pack_state(GENX(CC_VIEWPORT
), cso
->cc_vp
, ccvp
) {
454 ccvp
.MinimumDepth
= state
->depth
.bounds_min
;
455 ccvp
.MaximumDepth
= state
->depth
.bounds_max
;
462 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
464 struct iris_context
*ice
= (struct iris_context
*) ctx
;
465 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
466 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
469 if (!old_cso
|| old_cso
->alpha
.ref_value
!= new_cso
->alpha
.ref_value
) {
470 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
474 ice
->state
.cso_zsa
= new_cso
;
475 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
476 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
479 struct iris_rasterizer_state
{
480 uint32_t sf
[GENX(3DSTATE_SF_length
)];
481 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
482 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
483 uint32_t wm
[GENX(3DSTATE_WM_length
)];
484 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
486 bool flatshade
; /* for shader state */
487 bool light_twoside
; /* for shader state */
488 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
489 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
490 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
494 iris_create_rasterizer_state(struct pipe_context
*ctx
,
495 const struct pipe_rasterizer_state
*state
)
497 struct iris_rasterizer_state
*cso
=
498 malloc(sizeof(struct iris_rasterizer_state
));
501 sprite_coord_mode
-> SBE PointSpriteTextureCoordinateOrigin
502 sprite_coord_enable
-> SBE PointSpriteTextureCoordinateEnable
503 point_quad_rasterization
-> SBE
?
508 force_persample_interp
- ?
511 offset_units_unscaled
- cap
not exposed
515 cso
->flatshade
= state
->flatshade
;
516 cso
->light_twoside
= state
->light_twoside
;
517 cso
->rasterizer_discard
= state
->rasterizer_discard
;
518 cso
->half_pixel_center
= state
->half_pixel_center
;
520 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
521 sf
.StatisticsEnable
= true;
522 sf
.ViewportTransformEnable
= true;
523 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
524 sf
.LineEndCapAntialiasingRegionWidth
=
525 state
->line_smooth
? _10pixels
: _05pixels
;
526 sf
.LastPixelEnable
= state
->line_last_pixel
;
527 sf
.LineWidth
= state
->line_width
;
528 sf
.SmoothPointEnable
= state
->point_smooth
;
529 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
530 sf
.PointWidth
= state
->point_size
;
532 if (state
->flatshade_first
) {
533 sf
.TriangleStripListProvokingVertexSelect
= 2;
534 sf
.TriangleFanProvokingVertexSelect
= 2;
535 sf
.LineStripListProvokingVertexSelect
= 1;
537 sf
.TriangleFanProvokingVertexSelect
= 1;
542 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
543 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
544 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
545 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
546 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
547 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
548 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
549 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
550 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
551 rr
.GlobalDepthOffsetConstant
= state
->offset_units
;
552 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
553 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
554 rr
.SmoothPointEnable
= state
->point_smooth
;
555 rr
.AntialiasingEnable
= state
->line_smooth
;
556 rr
.ScissorRectangleEnable
= state
->scissor
;
557 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
558 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
559 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
562 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
563 cl
.StatisticsEnable
= true;
564 cl
.EarlyCullEnable
= true;
565 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
566 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
567 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
568 cl
.GuardbandClipTestEnable
= true;
569 cl
.ClipMode
= CLIPMODE_NORMAL
;
570 cl
.ClipEnable
= true;
571 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
572 cl
.MinimumPointWidth
= 0.125;
573 cl
.MaximumPointWidth
= 255.875;
574 //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
575 //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
577 if (state
->flatshade_first
) {
578 cl
.TriangleStripListProvokingVertexSelect
= 2;
579 cl
.TriangleFanProvokingVertexSelect
= 2;
580 cl
.LineStripListProvokingVertexSelect
= 1;
582 cl
.TriangleFanProvokingVertexSelect
= 1;
586 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
587 wm
.LineAntialiasingRegionWidth
= _10pixels
;
588 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
589 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
590 wm
.StatisticsEnable
= true;
591 wm
.LineStippleEnable
= state
->line_stipple_enable
;
592 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
593 // wm.BarycentricInterpolationMode = <comes from FS program> :(
594 // wm.EarlyDepthStencilControl = <comes from FS program> :(
597 /* Remap from 0..255 back to 1..256 */
598 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
600 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
601 line
.LineStipplePattern
= state
->line_stipple_pattern
;
602 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
603 line
.LineStippleRepeatCount
= line_stipple_factor
;
610 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
612 struct iris_context
*ice
= (struct iris_context
*) ctx
;
613 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
614 struct iris_rasterizer_state
*new_cso
= state
;
617 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
618 if (!old_cso
|| memcmp(old_cso
->line_stipple
, new_cso
->line_stipple
,
619 sizeof(old_cso
->line_stipple
)) != 0) {
620 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
624 old_cso
->half_pixel_center
!= new_cso
->half_pixel_center
) {
625 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
629 ice
->state
.cso_rast
= new_cso
;
630 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
634 translate_wrap(unsigned pipe_wrap
)
636 static const unsigned map
[] = {
637 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
638 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
639 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
640 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
641 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
642 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
643 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1, // XXX: ???
644 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1, // XXX: ???
646 return map
[pipe_wrap
];
650 * Return true if the given wrap mode requires the border color to exist.
653 wrap_mode_needs_border_color(unsigned wrap_mode
)
655 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
659 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
661 static const unsigned map
[] = {
662 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
663 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
664 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
666 return map
[pipe_mip
];
669 struct iris_sampler_state
{
670 struct pipe_sampler_state base
;
672 bool needs_border_color
;
674 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
678 iris_create_sampler_state(struct pipe_context
*pctx
,
679 const struct pipe_sampler_state
*state
)
681 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
686 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
687 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
689 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
690 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
691 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
693 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
694 wrap_mode_needs_border_color(wrap_t
) ||
695 wrap_mode_needs_border_color(wrap_r
);
697 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
698 samp
.TCXAddressControlMode
= wrap_s
;
699 samp
.TCYAddressControlMode
= wrap_t
;
700 samp
.TCZAddressControlMode
= wrap_r
;
701 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
702 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
703 samp
.MinModeFilter
= state
->min_img_filter
;
704 samp
.MagModeFilter
= state
->mag_img_filter
;
705 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
706 samp
.MaximumAnisotropy
= RATIO21
;
708 if (state
->max_anisotropy
>= 2) {
709 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
710 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
711 samp
.AnisotropicAlgorithm
= EWAApproximation
;
714 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
715 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
717 samp
.MaximumAnisotropy
=
718 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
721 /* Set address rounding bits if not using nearest filtering. */
722 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
723 samp
.UAddressMinFilterRoundingEnable
= true;
724 samp
.VAddressMinFilterRoundingEnable
= true;
725 samp
.RAddressMinFilterRoundingEnable
= true;
728 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
729 samp
.UAddressMagFilterRoundingEnable
= true;
730 samp
.VAddressMagFilterRoundingEnable
= true;
731 samp
.RAddressMagFilterRoundingEnable
= true;
734 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
735 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
737 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
739 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
740 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
741 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
742 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
744 //samp.BorderColorPointer = <<comes from elsewhere>>
751 iris_bind_sampler_states(struct pipe_context
*ctx
,
752 enum pipe_shader_type p_stage
,
753 unsigned start
, unsigned count
,
756 struct iris_context
*ice
= (struct iris_context
*) ctx
;
757 gl_shader_stage stage
= stage_from_pipe(p_stage
);
759 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
761 for (int i
= 0; i
< count
; i
++) {
762 ice
->state
.samplers
[stage
][start
+ i
] = states
[i
];
765 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
768 struct iris_sampler_view
{
769 struct pipe_sampler_view pipe
;
770 struct isl_view view
;
771 uint32_t surface_state
[GENX(RENDER_SURFACE_STATE_length
)];
775 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
776 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
778 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
781 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
783 * which is simply adding 4 then modding by 8 (or anding with 7).
785 * We then may need to apply workarounds for textureGather hardware bugs.
787 static enum isl_channel_select
788 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
790 return (swizzle
+ 4) & 7;
793 static struct pipe_sampler_view
*
794 iris_create_sampler_view(struct pipe_context
*ctx
,
795 struct pipe_resource
*tex
,
796 const struct pipe_sampler_view
*tmpl
)
798 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
799 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
800 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
805 /* initialize base object */
807 isv
->pipe
.context
= ctx
;
808 isv
->pipe
.texture
= NULL
;
809 pipe_reference_init(&isv
->pipe
.reference
, 1);
810 pipe_resource_reference(&isv
->pipe
.texture
, tex
);
812 /* XXX: do we need brw_get_texture_swizzle hacks here? */
814 isv
->view
= (struct isl_view
) {
815 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
816 .base_level
= tmpl
->u
.tex
.first_level
,
817 .levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1,
818 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
819 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
820 .swizzle
= (struct isl_swizzle
) {
821 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
822 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
823 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
824 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
826 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
829 isl_surf_fill_state(&screen
->isl_dev
, isv
->surface_state
,
830 .surf
= &itex
->surf
, .view
= &isv
->view
,
834 // .clear_color = clear_color,
839 struct iris_surface
{
840 struct pipe_surface pipe
;
841 struct isl_view view
;
842 uint32_t surface_state
[GENX(RENDER_SURFACE_STATE_length
)];
845 static struct pipe_surface
*
846 iris_create_surface(struct pipe_context
*ctx
,
847 struct pipe_resource
*tex
,
848 const struct pipe_surface
*tmpl
)
850 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
851 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
852 struct pipe_surface
*psurf
= &surf
->pipe
;
853 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
858 pipe_reference_init(&psurf
->reference
, 1);
859 pipe_resource_reference(&psurf
->texture
, tex
);
860 psurf
->context
= ctx
;
861 psurf
->format
= tmpl
->format
;
862 psurf
->width
= tex
->width0
;
863 psurf
->height
= tex
->height0
;
864 psurf
->texture
= tex
;
865 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
866 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
867 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
869 surf
->view
= (struct isl_view
) {
870 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
871 .base_level
= tmpl
->u
.tex
.level
,
873 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
874 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
875 .swizzle
= ISL_SWIZZLE_IDENTITY
,
876 // XXX: DEPTH_BIt, STENCIL_BIT...CUBE_BIT? Other bits?!
877 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
880 isl_surf_fill_state(&screen
->isl_dev
, surf
->surface_state
,
881 .surf
= &itex
->surf
, .view
= &surf
->view
,
885 // .clear_color = clear_color,
891 iris_set_sampler_views(struct pipe_context
*ctx
,
892 enum pipe_shader_type shader
,
893 unsigned start
, unsigned count
,
894 struct pipe_sampler_view
**views
)
899 iris_set_clip_state(struct pipe_context
*ctx
,
900 const struct pipe_clip_state
*state
)
905 iris_set_polygon_stipple(struct pipe_context
*ctx
,
906 const struct pipe_poly_stipple
*state
)
908 struct iris_context
*ice
= (struct iris_context
*) ctx
;
909 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
910 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
914 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
916 struct iris_context
*ice
= (struct iris_context
*) ctx
;
918 ice
->state
.sample_mask
= sample_mask
;
919 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
923 iris_set_scissor_states(struct pipe_context
*ctx
,
925 unsigned num_scissors
,
926 const struct pipe_scissor_state
*state
)
928 struct iris_context
*ice
= (struct iris_context
*) ctx
;
931 ice
->state
.num_scissors
= num_scissors
;
933 for (unsigned i
= start_slot
; i
< start_slot
+ num_scissors
; i
++) {
934 ice
->state
.scissors
[i
] = *state
;
937 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
941 iris_set_stencil_ref(struct pipe_context
*ctx
,
942 const struct pipe_stencil_ref
*state
)
944 struct iris_context
*ice
= (struct iris_context
*) ctx
;
945 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
946 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
950 struct iris_viewport_state
{
951 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
)];
955 extent_from_matrix(const struct pipe_viewport_state
*state
, int axis
)
957 return fabsf(state
->scale
[axis
]) * state
->translate
[axis
];
962 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
963 float m00
, float m11
, float m30
, float m31
,
964 float *xmin
, float *xmax
,
965 float *ymin
, float *ymax
)
967 /* According to the "Vertex X,Y Clamping and Quantization" section of the
968 * Strips and Fans documentation:
970 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
971 * fixed-point "guardband" range supported by the rasterization hardware"
975 * "In almost all circumstances, if an object’s vertices are actually
976 * modified by this clamping (i.e., had X or Y coordinates outside of
977 * the guardband extent the rendered object will not match the intended
978 * result. Therefore software should take steps to ensure that this does
979 * not happen - e.g., by clipping objects such that they do not exceed
980 * these limits after the Drawing Rectangle is applied."
982 * I believe the fundamental restriction is that the rasterizer (in
983 * the SF/WM stages) have a limit on the number of pixels that can be
984 * rasterized. We need to ensure any coordinates beyond the rasterizer
985 * limit are handled by the clipper. So effectively that limit becomes
986 * the clipper's guardband size.
990 * "In addition, in order to be correctly rendered, objects must have a
991 * screenspace bounding box not exceeding 8K in the X or Y direction.
992 * This additional restriction must also be comprehended by software,
993 * i.e., enforced by use of clipping."
995 * This makes no sense. Gen7+ hardware supports 16K render targets,
996 * and you definitely need to be able to draw polygons that fill the
997 * surface. Our assumption is that the rasterizer was limited to 8K
998 * on Sandybridge, which only supports 8K surfaces, and it was actually
999 * increased to 16K on Ivybridge and later.
1001 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1003 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1005 if (m00
!= 0 && m11
!= 0) {
1006 /* First, we compute the screen-space render area */
1007 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1008 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1009 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1010 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1012 /* We want the guardband to be centered on that */
1013 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1014 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1015 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1016 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1018 /* Now we need it in native device coordinates */
1019 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1020 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1021 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1022 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1024 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1025 * flipped upside-down. X should be fine though.
1027 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1028 *xmin
= ndc_gb_xmin
;
1029 *xmax
= ndc_gb_xmax
;
1030 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1031 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1033 /* The viewport scales to 0, so nothing will be rendered. */
1043 iris_set_viewport_states(struct pipe_context
*ctx
,
1044 unsigned start_slot
,
1045 unsigned num_viewports
,
1046 const struct pipe_viewport_state
*state
)
1048 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1049 struct iris_viewport_state
*cso
=
1050 malloc(sizeof(struct iris_viewport_state
));
1052 for (unsigned i
= start_slot
; i
< start_slot
+ num_viewports
; i
++) {
1053 float x_extent
= extent_from_matrix(&state
[i
], 0);
1054 float y_extent
= extent_from_matrix(&state
[i
], 1);
1056 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), cso
->sf_cl_vp
, vp
) {
1057 vp
.ViewportMatrixElementm00
= state
[i
].scale
[0];
1058 vp
.ViewportMatrixElementm11
= state
[i
].scale
[1];
1059 vp
.ViewportMatrixElementm22
= state
[i
].scale
[2];
1060 vp
.ViewportMatrixElementm30
= state
[i
].translate
[0];
1061 vp
.ViewportMatrixElementm31
= state
[i
].translate
[1];
1062 vp
.ViewportMatrixElementm32
= state
[i
].translate
[2];
1063 /* XXX: in i965 this is computed based on the drawbuffer size,
1064 * but we don't have that here...
1066 vp
.XMinClipGuardband
= -1.0;
1067 vp
.XMaxClipGuardband
= 1.0;
1068 vp
.YMinClipGuardband
= -1.0;
1069 vp
.YMaxClipGuardband
= 1.0;
1070 vp
.XMinViewPort
= -x_extent
;
1071 vp
.XMaxViewPort
= x_extent
;
1072 vp
.YMinViewPort
= -y_extent
;
1073 vp
.YMaxViewPort
= y_extent
;
1077 ice
->state
.cso_vp
= cso
;
1079 ice
->state
.num_viewports
= num_viewports
;
1080 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1083 struct iris_depth_state
1085 uint32_t depth_buffer
[GENX(3DSTATE_DEPTH_BUFFER_length
)];
1086 uint32_t hier_depth_buffer
[GENX(3DSTATE_HIER_DEPTH_BUFFER_length
)];
1087 uint32_t stencil_buffer
[GENX(3DSTATE_STENCIL_BUFFER_length
)];
1091 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1092 const struct pipe_framebuffer_state
*state
)
1094 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1095 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1097 if (cso
->samples
!= state
->samples
) {
1098 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1101 cso
->width
= state
->width
;
1102 cso
->height
= state
->height
;
1103 cso
->layers
= state
->layers
;
1104 cso
->samples
= state
->samples
;
1107 for (i
= 0; i
< state
->nr_cbufs
; i
++)
1108 pipe_surface_reference(&cso
->cbufs
[i
], state
->cbufs
[i
]);
1109 for (; i
< cso
->nr_cbufs
; i
++)
1110 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
1112 cso
->nr_cbufs
= state
->nr_cbufs
;
1114 pipe_surface_reference(&cso
->zsbuf
, state
->zsbuf
);
1116 struct isl_depth_stencil_hiz_emit_info info
= {
1120 // XXX: depth buffers
1124 iris_set_constant_buffer(struct pipe_context
*ctx
,
1125 enum pipe_shader_type shader
, uint index
,
1126 const struct pipe_constant_buffer
*cb
)
1132 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1133 struct pipe_sampler_view
*state
)
1135 pipe_resource_reference(&state
->texture
, NULL
);
1141 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*surface
)
1143 pipe_resource_reference(&surface
->texture
, NULL
);
1148 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1153 struct iris_vertex_buffer_state
{
1154 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
1155 struct iris_address bos
[33];
1156 unsigned num_buffers
;
1160 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
1163 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
1164 iris_bo_unreference(cso
->bos
[i
].bo
);
1170 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1171 unsigned start_slot
, unsigned count
,
1172 const struct pipe_vertex_buffer
*buffers
)
1174 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1175 struct iris_vertex_buffer_state
*cso
=
1176 malloc(sizeof(struct iris_vertex_buffer_state
));
1178 /* If there are no buffers, do nothing. We can leave the stale
1179 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1180 * elements that point to them, it should be fine.
1185 iris_free_vertex_buffers(ice
->state
.cso_vertex_buffers
);
1187 cso
->num_buffers
= count
;
1189 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1190 vb
.DWordLength
= 4 * cso
->num_buffers
- 1;
1193 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1195 for (unsigned i
= 0; i
< count
; i
++) {
1196 assert(!buffers
[i
].is_user_buffer
);
1198 struct iris_resource
*res
= (void *) buffers
[i
].buffer
.resource
;
1199 iris_bo_reference(res
->bo
);
1200 cso
->bos
[i
] = ro_bo(res
->bo
, buffers
[i
].buffer_offset
);
1202 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1203 vb
.VertexBufferIndex
= start_slot
+ i
;
1205 vb
.AddressModifyEnable
= true;
1206 vb
.BufferPitch
= buffers
[i
].stride
;
1207 vb
.BufferSize
= res
->bo
->size
;
1208 /* vb.BufferStartingAddress is filled in at draw time */
1211 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1214 ice
->state
.cso_vertex_buffers
= cso
;
1215 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1218 struct iris_vertex_element_state
{
1219 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1220 uint32_t vf_instancing
[GENX(3DSTATE_VF_INSTANCING_length
)][33];
1225 iris_create_vertex_elements(struct pipe_context
*ctx
,
1227 const struct pipe_vertex_element
*state
)
1229 struct iris_vertex_element_state
*cso
=
1230 malloc(sizeof(struct iris_vertex_element_state
));
1235 * - create edge flag one
1237 * - if those are necessary, use count + 1/2/3... OR in the length
1239 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
);
1241 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1243 for (int i
= 0; i
< count
; i
++) {
1244 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1245 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1247 ve
.SourceElementOffset
= state
[i
].src_offset
;
1248 ve
.SourceElementFormat
=
1249 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1252 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->vf_instancing
[i
], vi
) {
1253 vi
.VertexElementIndex
= i
;
1254 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1255 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1258 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1265 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
1267 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1269 ice
->state
.cso_vertex_elements
= state
;
1270 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
1274 iris_create_compute_state(struct pipe_context
*ctx
,
1275 const struct pipe_compute_state
*state
)
1280 static struct pipe_stream_output_target
*
1281 iris_create_stream_output_target(struct pipe_context
*ctx
,
1282 struct pipe_resource
*res
,
1283 unsigned buffer_offset
,
1284 unsigned buffer_size
)
1286 struct pipe_stream_output_target
*t
=
1287 CALLOC_STRUCT(pipe_stream_output_target
);
1291 pipe_reference_init(&t
->reference
, 1);
1292 pipe_resource_reference(&t
->buffer
, res
);
1293 t
->buffer_offset
= buffer_offset
;
1294 t
->buffer_size
= buffer_size
;
1299 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
1300 struct pipe_stream_output_target
*t
)
1302 pipe_resource_reference(&t
->buffer
, NULL
);
1307 iris_set_stream_output_targets(struct pipe_context
*ctx
,
1308 unsigned num_targets
,
1309 struct pipe_stream_output_target
**targets
,
1310 const unsigned *offsets
)
1315 iris_setup_state_base_address(struct iris_context
*ice
,
1316 struct iris_batch
*batch
,
1317 struct iris_bo
*instruction_bo
)
1319 if (!(ice
->state
.dirty
& IRIS_DIRTY_STATE_BASE_ADDRESS
))
1322 //iris_batchbuffer_flush(...)
1324 ice
->state
.dirty
&= ~IRIS_DIRTY_STATE_BASE_ADDRESS
;
1326 /* XXX: PIPE_CONTROLs */
1328 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
1330 // XXX: MOCS is stupid for this.
1331 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
1332 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
1333 sba
.SurfaceStateMemoryObjectControlState
= MOCS_WB
;
1334 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
1335 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
1336 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
1337 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
1340 sba
.GeneralStateBaseAddressModifyEnable
= true;
1341 sba
.SurfaceStateBaseAddressModifyEnable
= true;
1342 sba
.DynamicStateBaseAddressModifyEnable
= true;
1343 sba
.IndirectObjectBaseAddressModifyEnable
= true;
1344 sba
.InstructionBaseAddressModifyEnable
= true;
1345 sba
.GeneralStateBufferSizeModifyEnable
= true;
1346 sba
.DynamicStateBufferSizeModifyEnable
= true;
1347 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
1348 sba
.IndirectObjectBufferSizeModifyEnable
= true;
1349 sba
.InstructionBuffersizeModifyEnable
= true;
1351 sba
.SurfaceStateBaseAddress
= ro_bo(batch
->statebuf
.bo
, 0);
1352 sba
.DynamicStateBaseAddress
= ro_bo(batch
->statebuf
.bo
, 0);
1353 sba
.InstructionBaseAddress
= ro_bo(instruction_bo
, 0);
1355 sba
.GeneralStateBufferSize
= 0xfffff000;
1356 sba
.DynamicStateBufferSize
= ALIGN(MAX_STATE_SIZE
, 4096);
1357 sba
.IndirectObjectBufferSize
= 0xfffff000;
1358 sba
.InstructionBufferSize
= ALIGN(ice
->shaders
.cache
.bo
->size
, 4096);
1359 sba
.BindlessSurfaceStateSize
= 0;
1364 iris_upload_render_state(struct iris_context
*ice
,
1365 struct iris_batch
*batch
,
1366 const struct pipe_draw_info
*draw
)
1368 const uint64_t dirty
= ice
->state
.dirty
;
1370 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
1371 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1372 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
1374 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1375 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
1376 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
1377 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
1379 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
1382 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
1383 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1384 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
1385 ptr
.CCViewportPointer
=
1386 iris_emit_state(batch
, cso
->cc_vp
, sizeof(cso
->cc_vp
), 32);
1390 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
1391 struct iris_blend_state
*cso
= ice
->state
.cso_blend
;
1392 iris_batch_emit(batch
, cso
->ps_blend
, sizeof(cso
->ps_blend
));
1395 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
1396 //struct iris_blend_state *cso = ice->state.cso_blend;
1397 // XXX: 3DSTATE_BLEND_STATE_POINTERS - BLEND_STATE
1398 // -> from iris_blend_state (most) + iris_depth_stencil_alpha_state
1399 // (alpha test function/enable) + has writeable RT from ???????
1402 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
1403 struct iris_viewport_state
*cso
= ice
->state
.cso_vp
;
1404 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
1405 ptr
.SFClipViewportPointer
=
1406 iris_emit_state(batch
, cso
->sf_cl_vp
, sizeof(cso
->sf_cl_vp
), 64);
1410 if (dirty
& IRIS_DIRTY_CLIP
) {
1411 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
1413 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
1414 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
1415 //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
1416 //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
1417 // also userclip stuffs...
1419 iris_emit_merge(batch
, cso
->clip
, dynamic_clip
, ARRAY_SIZE(cso
->clip
));
1422 if (dirty
& IRIS_DIRTY_RASTER
) {
1423 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
1424 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
1425 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
1428 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
1429 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
1430 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
1433 if (dirty
& IRIS_DIRTY_SCISSOR
) {
1434 uint32_t scissor_offset
=
1435 iris_emit_state(batch
, ice
->state
.scissors
,
1436 sizeof(struct pipe_scissor_state
) *
1437 ice
->state
.num_scissors
, 32);
1439 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
1440 ptr
.ScissorRectPointer
= scissor_offset
;
1444 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
1445 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
1446 for (int i
= 0; i
< 32; i
++) {
1447 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
1452 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
1453 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1456 iris_alloc_state(batch
,
1457 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
1459 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
1460 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
1461 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
1462 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
1463 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
1464 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
1465 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
1467 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1468 ptr
.ColorCalcStatePointer
= cc_offset
;
1469 ptr
.ColorCalcStatePointerValid
= true;
1473 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
1474 struct iris_vertex_buffer_state
*cso
= ice
->state
.cso_vertex_buffers
;
1476 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_length
) == 4);
1477 STATIC_ASSERT((GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) % 32) == 0);
1479 uint64_t *addr
= batch
->cmdbuf
.map_next
+ sizeof(uint32_t) *
1480 (GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) / 32);
1481 uint32_t *delta
= cso
->vertex_buffers
+
1482 (1 + GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) / 32);
1484 iris_batch_emit(batch
, cso
->vertex_buffers
,
1485 sizeof(uint32_t) * (1 + 4 * cso
->num_buffers
));
1487 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
1488 *addr
= iris_batch_reloc(batch
, (void *) addr
- batch
->cmdbuf
.map
,
1489 cso
->bos
[i
].bo
, cso
->bos
[i
].offset
+
1490 *delta
, cso
->bos
[i
].reloc_flags
);
1491 addr
= (void *) addr
+ 16;
1492 delta
= (void *) delta
+ 16;
1496 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
1497 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
1498 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
1499 (1 + cso
->count
* GENX(VERTEX_ELEMENT_STATE_length
)));
1500 for (int i
= 0; i
< cso
->count
; i
++) {
1501 iris_batch_emit(batch
, cso
->vf_instancing
[i
], sizeof(uint32_t) *
1502 (cso
->count
* GENX(3DSTATE_VF_INSTANCING_length
)));
1504 for (int i
= 0; i
< cso
->count
; i
++) {
1505 /* TODO: vertexid, instanceid support */
1506 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
);
1510 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
1511 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1513 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
1514 if (ice
->state
.framebuffer
.samples
> 0)
1515 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
1519 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
1520 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
1521 ms
.SampleMask
= ice
->state
.sample_mask
;
1525 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
1526 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)))
1529 // XXX: get sampler count from shader; don't emit them all...
1530 const int count
= IRIS_MAX_TEXTURE_SAMPLERS
;
1533 uint32_t *map
= iris_alloc_state(batch
,
1534 count
* 4 * GENX(SAMPLER_STATE_length
),
1537 for (int i
= 0; i
< count
; i
++) {
1538 // XXX: when we have a correct count, these better be bound
1539 if (!ice
->state
.samplers
[stage
][i
])
1541 memcpy(map
, ice
->state
.samplers
[stage
][i
]->sampler_state
,
1542 4 * GENX(SAMPLER_STATE_length
));
1543 map
+= GENX(SAMPLER_STATE_length
);
1546 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
1547 ptr
._3DCommandSubOpcode
= 43 + stage
;
1548 ptr
.PointertoVSSamplerState
= offset
;
1553 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
1554 topo
.PrimitiveTopologyType
=
1555 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
1560 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
1561 if (draw
->primitive_restart
) {
1562 vf
.IndexedDrawCutIndexEnable
= true;
1563 vf
.CutIndex
= draw
->restart_index
;
1568 // draw->index_size > 0
1569 if (draw
->index_size
> 0) {
1570 struct iris_resource
*res
= (struct iris_resource
*)draw
->index
.resource
;
1572 assert(!draw
->has_user_indices
);
1574 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
1575 ib
.IndexFormat
= draw
->index_size
;
1577 ib
.BufferSize
= res
->bo
->size
;
1578 // XXX: gah, addresses :( need two different combine address funcs
1579 // ib.BufferStartingAddress = res->bo;
1583 assert(!draw
->indirect
); // XXX: indirect support
1585 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
1586 prim
.StartInstanceLocation
= draw
->start_instance
;
1587 prim
.InstanceCount
= draw
->instance_count
;
1588 prim
.VertexCountPerInstance
= draw
->count
;
1589 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
1591 // XXX: this is probably bonkers.
1592 prim
.StartVertexLocation
= draw
->start
;
1594 if (draw
->index_size
) {
1595 prim
.BaseVertexLocation
+= draw
->index_bias
;
1597 prim
.StartVertexLocation
+= draw
->index_bias
;
1600 //prim.BaseVertexLocation = ...;
1608 3DSTATE_CONSTANT_
* - push constants
1616 - render targets
- write
and read
1617 3DSTATE_BINDING_TABLE_POINTERS_
*
1629 3DSTATE_SO_DECL_LIST
1632 -> iris_raster_state
+ FS
state (barycentric
, EDSC
)
1634 -> iris_raster_state (point sprite texture coordinate origin
)
1635 -> bunch of shader state
...
1639 3DSTATE_DEPTH_BUFFER
1640 3DSTATE_HIER_DEPTH_BUFFER
1641 3DSTATE_STENCIL_BUFFER
1642 3DSTATE_CLEAR_PARAMS
1643 -> iris_framebuffer_state
?
1648 iris_bind_state(struct pipe_context
*ctx
, void *state
)
1653 iris_destroy_state(struct iris_context
*ice
)
1655 // XXX: unreference resources/surfaces.
1656 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
1657 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
1659 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
1663 iris_init_state(struct iris_context
*ice
)
1665 struct pipe_context
*ctx
= &ice
->ctx
;
1667 ice
->state
.dirty
= ~0ull;
1669 ctx
->create_blend_state
= iris_create_blend_state
;
1670 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
1671 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
1672 ctx
->create_sampler_state
= iris_create_sampler_state
;
1673 ctx
->create_sampler_view
= iris_create_sampler_view
;
1674 ctx
->create_surface
= iris_create_surface
;
1675 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
1676 ctx
->create_compute_state
= iris_create_compute_state
;
1677 ctx
->bind_blend_state
= iris_bind_blend_state
;
1678 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
1679 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
1680 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
1681 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
1682 ctx
->bind_compute_state
= iris_bind_state
;
1683 ctx
->delete_blend_state
= iris_delete_state
;
1684 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
1685 ctx
->delete_fs_state
= iris_delete_state
;
1686 ctx
->delete_rasterizer_state
= iris_delete_state
;
1687 ctx
->delete_sampler_state
= iris_delete_state
;
1688 ctx
->delete_vertex_elements_state
= iris_delete_state
;
1689 ctx
->delete_compute_state
= iris_delete_state
;
1690 ctx
->delete_tcs_state
= iris_delete_state
;
1691 ctx
->delete_tes_state
= iris_delete_state
;
1692 ctx
->delete_gs_state
= iris_delete_state
;
1693 ctx
->delete_vs_state
= iris_delete_state
;
1694 ctx
->set_blend_color
= iris_set_blend_color
;
1695 ctx
->set_clip_state
= iris_set_clip_state
;
1696 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
1697 ctx
->set_sampler_views
= iris_set_sampler_views
;
1698 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
1699 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
1700 ctx
->set_sample_mask
= iris_set_sample_mask
;
1701 ctx
->set_scissor_states
= iris_set_scissor_states
;
1702 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
1703 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
1704 ctx
->set_viewport_states
= iris_set_viewport_states
;
1705 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
1706 ctx
->surface_destroy
= iris_surface_destroy
;
1707 ctx
->draw_vbo
= iris_draw_vbo
;
1708 ctx
->launch_grid
= iris_launch_grid
;
1709 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
1710 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
1711 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;