2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
31 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
37 #include "pipe/p_defines.h"
38 #include "pipe/p_state.h"
39 #include "pipe/p_context.h"
40 #include "pipe/p_screen.h"
41 #include "util/u_inlines.h"
42 #include "util/u_format.h"
43 #include "util/u_framebuffer.h"
44 #include "util/u_transfer.h"
45 #include "util/u_upload_mgr.h"
46 #include "util/u_viewport.h"
49 #include "intel/compiler/brw_compiler.h"
50 #include "intel/common/gen_l3_config.h"
51 #include "intel/common/gen_sample_positions.h"
52 #include "iris_batch.h"
53 #include "iris_context.h"
54 #include "iris_pipe.h"
55 #include "iris_resource.h"
57 #define __gen_address_type struct iris_address
58 #define __gen_user_data struct iris_batch
60 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
63 __gen_combine_address(struct iris_batch
*batch
, void *location
,
64 struct iris_address addr
, uint32_t delta
)
66 uint64_t result
= addr
.offset
+ delta
;
69 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
70 /* Assume this is a general address, not relative to a base. */
71 result
+= addr
.bo
->gtt_offset
;
77 #define __genxml_cmd_length(cmd) cmd ## _length
78 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
79 #define __genxml_cmd_header(cmd) cmd ## _header
80 #define __genxml_cmd_pack(cmd) cmd ## _pack
82 #define _iris_pack_command(batch, cmd, dst, name) \
83 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
84 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
85 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
89 #define iris_pack_command(cmd, dst, name) \
90 _iris_pack_command(NULL, cmd, dst, name)
92 #define iris_pack_state(cmd, dst, name) \
93 for (struct cmd name = {}, \
94 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
95 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
98 #define iris_emit_cmd(batch, cmd, name) \
99 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
101 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
103 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
104 for (uint32_t i = 0; i < num_dwords; i++) \
105 dw[i] = (dwords0)[i] | (dwords1)[i]; \
106 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
109 #include "genxml/genX_pack.h"
110 #include "genxml/gen_macros.h"
111 #include "genxml/genX_bits.h"
113 #define MOCS_WB (2 << 1)
115 UNUSED
static void pipe_asserts()
117 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
119 /* pipe_logicop happens to match the hardware. */
120 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
121 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
122 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
123 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
124 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
125 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
126 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
127 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
128 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
129 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
130 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
131 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
132 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
133 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
134 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
135 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
137 /* pipe_blend_func happens to match the hardware. */
138 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
139 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
140 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
141 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
142 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
143 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
144 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
145 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
146 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
147 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
148 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
149 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
150 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
151 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
152 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
153 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
158 /* pipe_blend_func happens to match the hardware. */
159 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
160 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
161 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
162 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
163 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
165 /* pipe_stencil_op happens to match the hardware. */
166 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
167 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
168 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
169 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
170 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
171 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
172 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
173 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
175 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
176 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
177 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
182 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
184 static const unsigned map
[] = {
185 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
186 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
187 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
188 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
189 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
190 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
191 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
192 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
193 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
194 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
195 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
196 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
197 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
198 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
199 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
202 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
206 translate_compare_func(enum pipe_compare_func pipe_func
)
208 static const unsigned map
[] = {
209 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
210 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
211 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
212 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
213 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
214 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
215 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
216 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
218 return map
[pipe_func
];
222 translate_shadow_func(enum pipe_compare_func pipe_func
)
224 /* Gallium specifies the result of shadow comparisons as:
226 * 1 if ref <op> texel,
231 * 0 if texel <op> ref,
234 * So we need to flip the operator and also negate.
236 static const unsigned map
[] = {
237 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
238 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
239 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
240 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
241 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
242 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
243 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
244 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
246 return map
[pipe_func
];
250 translate_cull_mode(unsigned pipe_face
)
252 static const unsigned map
[4] = {
253 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
254 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
255 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
256 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
258 return map
[pipe_face
];
262 translate_fill_mode(unsigned pipe_polymode
)
264 static const unsigned map
[4] = {
265 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
266 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
267 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
268 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
270 return map
[pipe_polymode
];
273 static struct iris_address
274 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
277 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
280 static struct iris_address
281 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
284 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
288 upload_state(struct u_upload_mgr
*uploader
,
289 struct iris_state_ref
*ref
,
294 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
299 stream_state(struct iris_batch
*batch
,
300 struct u_upload_mgr
*uploader
,
301 struct pipe_resource
**out_res
,
304 uint32_t *out_offset
)
308 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
310 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
311 iris_use_pinned_bo(batch
, bo
, false);
313 *out_offset
+= iris_bo_offset_from_base_address(bo
);
319 emit_state(struct iris_batch
*batch
,
320 struct u_upload_mgr
*uploader
,
321 struct pipe_resource
**out_res
,
328 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
331 memcpy(map
, data
, size
);
336 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
337 #define cso_changed_memcmp(x) \
338 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
341 iris_init_render_context(struct iris_screen
*screen
,
342 struct iris_batch
*batch
,
343 struct iris_vtable
*vtbl
,
344 struct pipe_debug_callback
*dbg
)
346 iris_init_batch(batch
, screen
, vtbl
, dbg
, I915_EXEC_RENDER
);
348 /* XXX: PIPE_CONTROLs */
350 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
352 // XXX: MOCS is stupid for this.
353 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
354 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
355 sba
.SurfaceStateMemoryObjectControlState
= MOCS_WB
;
356 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
357 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
358 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
359 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
362 sba
.GeneralStateBaseAddressModifyEnable
= true;
363 sba
.SurfaceStateBaseAddressModifyEnable
= true;
364 sba
.DynamicStateBaseAddressModifyEnable
= true;
365 sba
.IndirectObjectBaseAddressModifyEnable
= true;
366 sba
.InstructionBaseAddressModifyEnable
= true;
367 sba
.GeneralStateBufferSizeModifyEnable
= true;
368 sba
.DynamicStateBufferSizeModifyEnable
= true;
369 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
370 sba
.IndirectObjectBufferSizeModifyEnable
= true;
371 sba
.InstructionBuffersizeModifyEnable
= true;
373 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
374 sba
.SurfaceStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SURFACE_START
);
375 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
377 sba
.GeneralStateBufferSize
= 0xfffff;
378 sba
.IndirectObjectBufferSize
= 0xfffff;
379 sba
.InstructionBufferSize
= 0xfffff;
380 sba
.DynamicStateBufferSize
= 0xfffff;
383 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
384 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
385 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
387 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
388 GEN_SAMPLE_POS_1X(pat
._1xSample
);
389 GEN_SAMPLE_POS_2X(pat
._2xSample
);
390 GEN_SAMPLE_POS_4X(pat
._4xSample
);
391 GEN_SAMPLE_POS_8X(pat
._8xSample
);
392 GEN_SAMPLE_POS_16X(pat
._16xSample
);
394 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
395 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
396 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
397 /* XXX: may need to set an offset for origin-UL framebuffers */
398 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
400 /* Just assign a static partitioning. */
401 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
402 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
403 alloc
._3DCommandSubOpcode
= 18 + i
;
404 alloc
.ConstantBufferOffset
= 6 * i
;
405 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
410 struct iris_vertex_buffer_state
{
411 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
412 struct pipe_resource
*resources
[33];
413 unsigned num_buffers
;
416 struct iris_depth_buffer_state
{
417 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
418 GENX(3DSTATE_STENCIL_BUFFER_length
) +
419 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
420 GENX(3DSTATE_CLEAR_PARAMS_length
)];
424 * State that can't be stored directly in iris_context because the data
425 * layout varies per generation.
427 struct iris_genx_state
{
428 /** SF_CLIP_VIEWPORT */
429 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
) * IRIS_MAX_VIEWPORTS
];
431 struct iris_vertex_buffer_state vertex_buffers
;
432 struct iris_depth_buffer_state depth_buffer
;
434 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
435 uint32_t streamout
[4 * GENX(3DSTATE_STREAMOUT_length
)];
439 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
444 iris_set_blend_color(struct pipe_context
*ctx
,
445 const struct pipe_blend_color
*state
)
447 struct iris_context
*ice
= (struct iris_context
*) ctx
;
449 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
450 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
453 struct iris_blend_state
{
454 /** Partial 3DSTATE_PS_BLEND */
455 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
457 /** Partial BLEND_STATE */
458 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
459 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
461 bool alpha_to_coverage
; /* for shader key */
465 iris_create_blend_state(struct pipe_context
*ctx
,
466 const struct pipe_blend_state
*state
)
468 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
469 uint32_t *blend_state
= cso
->blend_state
;
471 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
473 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
474 /* pb.HasWriteableRT is filled in at draw time. */
475 /* pb.AlphaTestEnable is filled in at draw time. */
476 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
477 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
479 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
481 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
482 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
483 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
484 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
487 iris_pack_state(GENX(BLEND_STATE
), blend_state
, bs
) {
488 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
489 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
490 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
491 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
492 bs
.ColorDitherEnable
= state
->dither
;
493 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
496 blend_state
+= GENX(BLEND_STATE_length
);
498 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
499 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_state
, be
) {
500 be
.LogicOpEnable
= state
->logicop_enable
;
501 be
.LogicOpFunction
= state
->logicop_func
;
503 be
.PreBlendSourceOnlyClampEnable
= false;
504 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
505 be
.PreBlendColorClampEnable
= true;
506 be
.PostBlendColorClampEnable
= true;
508 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
510 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
511 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
512 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
513 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
514 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
515 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
517 be
.WriteDisableRed
= !(state
->rt
[i
].colormask
& PIPE_MASK_R
);
518 be
.WriteDisableGreen
= !(state
->rt
[i
].colormask
& PIPE_MASK_G
);
519 be
.WriteDisableBlue
= !(state
->rt
[i
].colormask
& PIPE_MASK_B
);
520 be
.WriteDisableAlpha
= !(state
->rt
[i
].colormask
& PIPE_MASK_A
);
522 blend_state
+= GENX(BLEND_STATE_ENTRY_length
);
529 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
531 struct iris_context
*ice
= (struct iris_context
*) ctx
;
532 ice
->state
.cso_blend
= state
;
533 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
534 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
535 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
538 struct iris_depth_stencil_alpha_state
{
539 /** Partial 3DSTATE_WM_DEPTH_STENCIL */
540 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
542 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE */
543 struct pipe_alpha_state alpha
;
547 iris_create_zsa_state(struct pipe_context
*ctx
,
548 const struct pipe_depth_stencil_alpha_state
*state
)
550 struct iris_depth_stencil_alpha_state
*cso
=
551 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
553 cso
->alpha
= state
->alpha
;
555 bool two_sided_stencil
= state
->stencil
[1].enabled
;
557 /* The state tracker needs to optimize away EQUAL writes for us. */
558 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
560 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
561 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
562 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
563 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
564 wmds
.StencilTestFunction
=
565 translate_compare_func(state
->stencil
[0].func
);
566 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
567 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
568 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
569 wmds
.BackfaceStencilTestFunction
=
570 translate_compare_func(state
->stencil
[1].func
);
571 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
572 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
573 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
574 wmds
.StencilBufferWriteEnable
=
575 state
->stencil
[0].writemask
!= 0 ||
576 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
577 wmds
.DepthTestEnable
= state
->depth
.enabled
;
578 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
579 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
580 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
581 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
582 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
583 /* wmds.[Backface]StencilReferenceValue are merged later */
590 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
592 struct iris_context
*ice
= (struct iris_context
*) ctx
;
593 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
594 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
597 if (cso_changed(alpha
.ref_value
))
598 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
600 if (cso_changed(alpha
.enabled
))
601 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
604 ice
->state
.cso_zsa
= new_cso
;
605 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
606 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
607 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
610 struct iris_rasterizer_state
{
611 uint32_t sf
[GENX(3DSTATE_SF_length
)];
612 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
613 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
614 uint32_t wm
[GENX(3DSTATE_WM_length
)];
615 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
617 bool clip_halfz
; /* for CC_VIEWPORT */
618 bool depth_clip_near
; /* for CC_VIEWPORT */
619 bool depth_clip_far
; /* for CC_VIEWPORT */
620 bool flatshade
; /* for shader state */
621 bool flatshade_first
; /* for stream output */
622 bool clamp_fragment_color
; /* for shader state */
623 bool light_twoside
; /* for shader state */
624 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
625 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
626 bool line_stipple_enable
;
627 bool poly_stipple_enable
;
629 bool force_persample_interp
;
630 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
631 uint16_t sprite_coord_enable
;
635 iris_create_rasterizer_state(struct pipe_context
*ctx
,
636 const struct pipe_rasterizer_state
*state
)
638 struct iris_rasterizer_state
*cso
=
639 malloc(sizeof(struct iris_rasterizer_state
));
642 point_quad_rasterization
-> SBE
?
647 force_persample_interp
- ?
650 offset_units_unscaled
- cap
not exposed
654 cso
->multisample
= state
->multisample
;
655 cso
->force_persample_interp
= state
->force_persample_interp
;
656 cso
->clip_halfz
= state
->clip_halfz
;
657 cso
->depth_clip_near
= state
->depth_clip_near
;
658 cso
->depth_clip_far
= state
->depth_clip_far
;
659 cso
->flatshade
= state
->flatshade
;
660 cso
->flatshade_first
= state
->flatshade_first
;
661 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
662 cso
->light_twoside
= state
->light_twoside
;
663 cso
->rasterizer_discard
= state
->rasterizer_discard
;
664 cso
->half_pixel_center
= state
->half_pixel_center
;
665 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
666 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
667 cso
->line_stipple_enable
= state
->line_stipple_enable
;
668 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
670 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
671 sf
.StatisticsEnable
= true;
672 sf
.ViewportTransformEnable
= true;
673 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
674 sf
.LineEndCapAntialiasingRegionWidth
=
675 state
->line_smooth
? _10pixels
: _05pixels
;
676 sf
.LastPixelEnable
= state
->line_last_pixel
;
677 sf
.LineWidth
= state
->line_width
;
678 sf
.SmoothPointEnable
= state
->point_smooth
;
679 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
680 sf
.PointWidth
= state
->point_size
;
682 if (state
->flatshade_first
) {
683 sf
.TriangleFanProvokingVertexSelect
= 1;
685 sf
.TriangleStripListProvokingVertexSelect
= 2;
686 sf
.TriangleFanProvokingVertexSelect
= 2;
687 sf
.LineStripListProvokingVertexSelect
= 1;
691 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
692 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
693 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
694 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
695 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
696 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
697 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
698 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
699 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
700 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
701 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
702 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
703 rr
.SmoothPointEnable
= state
->point_smooth
;
704 rr
.AntialiasingEnable
= state
->line_smooth
;
705 rr
.ScissorRectangleEnable
= state
->scissor
;
706 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
707 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
708 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
711 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
712 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
713 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
715 cl
.StatisticsEnable
= true;
716 cl
.EarlyCullEnable
= true;
717 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
718 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
719 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
720 cl
.GuardbandClipTestEnable
= true;
721 cl
.ClipMode
= CLIPMODE_NORMAL
;
722 cl
.ClipEnable
= true;
723 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
724 cl
.MinimumPointWidth
= 0.125;
725 cl
.MaximumPointWidth
= 255.875;
727 if (state
->flatshade_first
) {
728 cl
.TriangleFanProvokingVertexSelect
= 1;
730 cl
.TriangleStripListProvokingVertexSelect
= 2;
731 cl
.TriangleFanProvokingVertexSelect
= 2;
732 cl
.LineStripListProvokingVertexSelect
= 1;
736 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
737 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
738 * filled in at draw time from the FS program.
740 wm
.LineAntialiasingRegionWidth
= _10pixels
;
741 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
742 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
743 wm
.StatisticsEnable
= true;
744 wm
.LineStippleEnable
= state
->line_stipple_enable
;
745 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
748 /* Remap from 0..255 back to 1..256 */
749 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
751 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
752 line
.LineStipplePattern
= state
->line_stipple_pattern
;
753 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
754 line
.LineStippleRepeatCount
= line_stipple_factor
;
761 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
763 struct iris_context
*ice
= (struct iris_context
*) ctx
;
764 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
765 struct iris_rasterizer_state
*new_cso
= state
;
768 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
769 if (cso_changed_memcmp(line_stipple
))
770 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
772 if (cso_changed(half_pixel_center
))
773 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
775 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
776 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
778 if (cso_changed(rasterizer_discard
) || cso_changed(flatshade_first
))
779 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
781 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
782 cso_changed(clip_halfz
))
783 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
786 ice
->state
.cso_rast
= new_cso
;
787 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
788 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
789 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
793 translate_wrap(unsigned pipe_wrap
)
795 static const unsigned map
[] = {
796 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
797 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
798 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
799 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
800 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
801 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
803 /* These are unsupported. */
804 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
805 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
807 return map
[pipe_wrap
];
811 * Return true if the given wrap mode requires the border color to exist.
814 wrap_mode_needs_border_color(unsigned wrap_mode
)
816 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
820 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
822 static const unsigned map
[] = {
823 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
824 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
825 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
827 return map
[pipe_mip
];
830 struct iris_sampler_state
{
831 struct pipe_sampler_state base
;
833 bool needs_border_color
;
835 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
839 iris_create_sampler_state(struct pipe_context
*ctx
,
840 const struct pipe_sampler_state
*state
)
842 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
847 memcpy(&cso
->base
, state
, sizeof(*state
));
849 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
850 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
852 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
853 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
854 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
856 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
857 wrap_mode_needs_border_color(wrap_t
) ||
858 wrap_mode_needs_border_color(wrap_r
);
860 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
861 samp
.TCXAddressControlMode
= wrap_s
;
862 samp
.TCYAddressControlMode
= wrap_t
;
863 samp
.TCZAddressControlMode
= wrap_r
;
864 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
865 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
866 samp
.MinModeFilter
= state
->min_img_filter
;
867 samp
.MagModeFilter
= state
->mag_img_filter
;
868 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
869 samp
.MaximumAnisotropy
= RATIO21
;
871 if (state
->max_anisotropy
>= 2) {
872 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
873 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
874 samp
.AnisotropicAlgorithm
= EWAApproximation
;
877 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
878 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
880 samp
.MaximumAnisotropy
=
881 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
884 /* Set address rounding bits if not using nearest filtering. */
885 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
886 samp
.UAddressMinFilterRoundingEnable
= true;
887 samp
.VAddressMinFilterRoundingEnable
= true;
888 samp
.RAddressMinFilterRoundingEnable
= true;
891 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
892 samp
.UAddressMagFilterRoundingEnable
= true;
893 samp
.VAddressMagFilterRoundingEnable
= true;
894 samp
.RAddressMagFilterRoundingEnable
= true;
897 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
898 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
900 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
902 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
903 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
904 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
905 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
907 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
914 iris_bind_sampler_states(struct pipe_context
*ctx
,
915 enum pipe_shader_type p_stage
,
916 unsigned start
, unsigned count
,
919 struct iris_context
*ice
= (struct iris_context
*) ctx
;
920 gl_shader_stage stage
= stage_from_pipe(p_stage
);
922 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
923 ice
->state
.num_samplers
[stage
] =
924 MAX2(ice
->state
.num_samplers
[stage
], start
+ count
);
926 for (int i
= 0; i
< count
; i
++) {
927 ice
->state
.samplers
[stage
][start
+ i
] = states
[i
];
930 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
931 * in the dynamic state memory zone, so we can point to it via the
932 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
934 void *map
= upload_state(ice
->state
.dynamic_uploader
,
935 &ice
->state
.sampler_table
[stage
],
936 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
940 struct pipe_resource
*res
= ice
->state
.sampler_table
[stage
].res
;
941 ice
->state
.sampler_table
[stage
].offset
+=
942 iris_bo_offset_from_base_address(iris_resource_bo(res
));
944 /* Make sure all land in the same BO */
945 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
947 for (int i
= 0; i
< count
; i
++) {
948 struct iris_sampler_state
*state
= ice
->state
.samplers
[stage
][i
];
950 /* Save a pointer to the iris_sampler_state, a few fields need
951 * to inform draw-time decisions.
953 ice
->state
.samplers
[stage
][start
+ i
] = state
;
956 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
957 } else if (!state
->needs_border_color
) {
958 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
960 ice
->state
.need_border_colors
= true;
962 /* Stream out the border color and merge the pointer. */
964 iris_upload_border_color(ice
, &state
->base
.border_color
);
966 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
967 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
968 dyns
.BorderColorPointer
= offset
;
971 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
972 ((uint32_t *) map
)[j
] = state
->sampler_state
[j
] | dynamic
[j
];
975 map
+= GENX(SAMPLER_STATE_length
);
978 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
981 struct iris_sampler_view
{
982 struct pipe_sampler_view pipe
;
983 struct isl_view view
;
985 /** The resource (BO) holding our SURFACE_STATE. */
986 struct iris_state_ref surface_state
;
990 * Convert an swizzle enumeration (i.e. PIPE_SWIZZLE_X) to one of the Gen7.5+
991 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
993 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
996 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
998 * which is simply adding 4 then modding by 8 (or anding with 7).
1000 * We then may need to apply workarounds for textureGather hardware bugs.
1002 static enum isl_channel_select
1003 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
1005 return (swizzle
+ 4) & 7;
1008 static struct pipe_sampler_view
*
1009 iris_create_sampler_view(struct pipe_context
*ctx
,
1010 struct pipe_resource
*tex
,
1011 const struct pipe_sampler_view
*tmpl
)
1013 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1014 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1015 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
1016 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1021 /* initialize base object */
1023 isv
->pipe
.context
= ctx
;
1024 isv
->pipe
.texture
= NULL
;
1025 pipe_reference_init(&isv
->pipe
.reference
, 1);
1026 pipe_resource_reference(&isv
->pipe
.texture
, tex
);
1028 void *map
= upload_state(ice
->state
.surface_uploader
, &isv
->surface_state
,
1029 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1033 struct iris_bo
*state_bo
= iris_resource_bo(isv
->surface_state
.res
);
1034 isv
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1036 /* XXX: do we need brw_get_texture_swizzle hacks here? */
1037 isv
->view
= (struct isl_view
) {
1038 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
1039 .swizzle
= (struct isl_swizzle
) {
1040 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
1041 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
1042 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
1043 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
1045 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
1046 (itex
->surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
),
1049 if (tmpl
->target
!= PIPE_BUFFER
) {
1050 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1051 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1052 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1053 isv
->view
.array_len
=
1054 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1056 isl_surf_fill_state(&screen
->isl_dev
, map
,
1057 .surf
= &itex
->surf
, .view
= &isv
->view
,
1059 .address
= itex
->bo
->gtt_offset
);
1061 // .clear_color = clear_color,
1063 // XXX: what to do about isv->view? other drivers don't use it for bufs
1064 isl_buffer_fill_state(&screen
->isl_dev
, map
,
1065 .address
= itex
->bo
->gtt_offset
+
1067 // XXX: buffer_texture_range_size from i965?
1068 .size_B
= tmpl
->u
.buf
.size
,
1069 .format
= isv
->view
.format
,
1070 .stride_B
= itex
->surf
.row_pitch_B
,
1077 static struct pipe_surface
*
1078 iris_create_surface(struct pipe_context
*ctx
,
1079 struct pipe_resource
*tex
,
1080 const struct pipe_surface
*tmpl
)
1082 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1083 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1084 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1085 struct pipe_surface
*psurf
= &surf
->pipe
;
1086 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1091 pipe_reference_init(&psurf
->reference
, 1);
1092 pipe_resource_reference(&psurf
->texture
, tex
);
1093 psurf
->context
= ctx
;
1094 psurf
->format
= tmpl
->format
;
1095 psurf
->width
= tex
->width0
;
1096 psurf
->height
= tex
->height0
;
1097 psurf
->texture
= tex
;
1098 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1099 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1100 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1104 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1105 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1106 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1108 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1110 surf
->view
= (struct isl_view
) {
1111 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
1112 .base_level
= tmpl
->u
.tex
.level
,
1114 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1115 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1116 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1120 /* Bail early for depth/stencil */
1121 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1122 ISL_SURF_USAGE_STENCIL_BIT
))
1126 void *map
= upload_state(ice
->state
.surface_uploader
, &surf
->surface_state
,
1127 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1131 struct iris_bo
*state_bo
= iris_resource_bo(surf
->surface_state
.res
);
1132 surf
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1134 isl_surf_fill_state(&screen
->isl_dev
, map
,
1135 .surf
= &res
->surf
, .view
= &surf
->view
,
1137 .address
= res
->bo
->gtt_offset
);
1139 // .clear_color = clear_color,
1145 iris_set_sampler_views(struct pipe_context
*ctx
,
1146 enum pipe_shader_type p_stage
,
1147 unsigned start
, unsigned count
,
1148 struct pipe_sampler_view
**views
)
1150 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1151 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1154 for (i
= 0; i
< count
; i
++) {
1155 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1156 &ice
->state
.textures
[stage
][i
], views
[i
]);
1158 for (; i
< ice
->state
.num_textures
[stage
]; i
++) {
1159 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1160 &ice
->state
.textures
[stage
][i
], NULL
);
1163 ice
->state
.num_textures
[stage
] = count
;
1165 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
1169 iris_set_clip_state(struct pipe_context
*ctx
,
1170 const struct pipe_clip_state
*state
)
1175 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1176 const struct pipe_poly_stipple
*state
)
1178 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1179 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1180 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1184 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1186 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1188 ice
->state
.sample_mask
= sample_mask
== 0xffffffff ? 1 : sample_mask
;
1189 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1193 iris_set_scissor_states(struct pipe_context
*ctx
,
1194 unsigned start_slot
,
1195 unsigned num_scissors
,
1196 const struct pipe_scissor_state
*states
)
1198 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1200 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1201 ice
->state
.scissors
[start_slot
+ i
] = states
[i
];
1204 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1208 iris_set_stencil_ref(struct pipe_context
*ctx
,
1209 const struct pipe_stencil_ref
*state
)
1211 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1212 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1213 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1217 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1219 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1224 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1225 float m00
, float m11
, float m30
, float m31
,
1226 float *xmin
, float *xmax
,
1227 float *ymin
, float *ymax
)
1229 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1230 * Strips and Fans documentation:
1232 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1233 * fixed-point "guardband" range supported by the rasterization hardware"
1237 * "In almost all circumstances, if an object’s vertices are actually
1238 * modified by this clamping (i.e., had X or Y coordinates outside of
1239 * the guardband extent the rendered object will not match the intended
1240 * result. Therefore software should take steps to ensure that this does
1241 * not happen - e.g., by clipping objects such that they do not exceed
1242 * these limits after the Drawing Rectangle is applied."
1244 * I believe the fundamental restriction is that the rasterizer (in
1245 * the SF/WM stages) have a limit on the number of pixels that can be
1246 * rasterized. We need to ensure any coordinates beyond the rasterizer
1247 * limit are handled by the clipper. So effectively that limit becomes
1248 * the clipper's guardband size.
1250 * It goes on to say:
1252 * "In addition, in order to be correctly rendered, objects must have a
1253 * screenspace bounding box not exceeding 8K in the X or Y direction.
1254 * This additional restriction must also be comprehended by software,
1255 * i.e., enforced by use of clipping."
1257 * This makes no sense. Gen7+ hardware supports 16K render targets,
1258 * and you definitely need to be able to draw polygons that fill the
1259 * surface. Our assumption is that the rasterizer was limited to 8K
1260 * on Sandybridge, which only supports 8K surfaces, and it was actually
1261 * increased to 16K on Ivybridge and later.
1263 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1265 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1267 if (m00
!= 0 && m11
!= 0) {
1268 /* First, we compute the screen-space render area */
1269 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1270 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1271 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1272 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1274 /* We want the guardband to be centered on that */
1275 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1276 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1277 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1278 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1280 /* Now we need it in native device coordinates */
1281 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1282 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1283 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1284 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1286 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1287 * flipped upside-down. X should be fine though.
1289 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1290 *xmin
= ndc_gb_xmin
;
1291 *xmax
= ndc_gb_xmax
;
1292 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1293 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1295 /* The viewport scales to 0, so nothing will be rendered. */
1305 iris_set_viewport_states(struct pipe_context
*ctx
,
1306 unsigned start_slot
,
1308 const struct pipe_viewport_state
*states
)
1310 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1311 struct iris_genx_state
*genx
= ice
->state
.genx
;
1312 uint32_t *vp_map
= &genx
->sf_cl_vp
[start_slot
];
1314 for (unsigned i
= 0; i
< count
; i
++) {
1315 const struct pipe_viewport_state
*state
= &states
[i
];
1317 memcpy(&ice
->state
.viewports
[start_slot
+ i
], state
, sizeof(*state
));
1319 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
1320 vp
.ViewportMatrixElementm00
= state
->scale
[0];
1321 vp
.ViewportMatrixElementm11
= state
->scale
[1];
1322 vp
.ViewportMatrixElementm22
= state
->scale
[2];
1323 vp
.ViewportMatrixElementm30
= state
->translate
[0];
1324 vp
.ViewportMatrixElementm31
= state
->translate
[1];
1325 vp
.ViewportMatrixElementm32
= state
->translate
[2];
1326 /* XXX: in i965 this is computed based on the drawbuffer size,
1327 * but we don't have that here...
1329 vp
.XMinClipGuardband
= -1.0;
1330 vp
.XMaxClipGuardband
= 1.0;
1331 vp
.YMinClipGuardband
= -1.0;
1332 vp
.YMaxClipGuardband
= 1.0;
1333 vp
.XMinViewPort
= viewport_extent(state
, 0, -1.0f
);
1334 vp
.XMaxViewPort
= viewport_extent(state
, 0, 1.0f
) - 1;
1335 vp
.YMinViewPort
= viewport_extent(state
, 1, -1.0f
);
1336 vp
.YMaxViewPort
= viewport_extent(state
, 1, 1.0f
) - 1;
1339 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
1342 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1344 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
1345 !ice
->state
.cso_rast
->depth_clip_far
))
1346 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1350 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1351 const struct pipe_framebuffer_state
*state
)
1353 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1354 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1355 struct isl_device
*isl_dev
= &screen
->isl_dev
;
1356 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1358 if (cso
->samples
!= state
->samples
) {
1359 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1362 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
1363 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1366 if ((cso
->layers
== 0) != (state
->layers
== 0)) {
1367 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1370 util_copy_framebuffer_state(cso
, state
);
1372 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
1374 struct isl_view view
= {
1377 .base_array_layer
= 0,
1379 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1382 struct isl_depth_stencil_hiz_emit_info info
= {
1387 struct iris_resource
*zres
=
1388 (void *) (cso
->zsbuf
? cso
->zsbuf
->texture
: NULL
);
1391 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
1393 info
.depth_surf
= &zres
->surf
;
1394 info
.depth_address
= zres
->bo
->gtt_offset
;
1396 view
.format
= zres
->surf
.format
;
1398 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
1399 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
1401 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
1403 info
.hiz_usage
= ISL_AUX_USAGE_NONE
;
1408 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
1409 info
.stencil_surf
= &stencil_mt
->surf
;
1412 view
.base_level
= stencil_irb
->mt_level
- stencil_irb
->mt
->first_level
;
1413 view
.base_array_layer
= stencil_irb
->mt_layer
;
1414 view
.array_len
= MAX2(stencil_irb
->layer_count
, 1);
1415 view
.format
= stencil_mt
->surf
.format
;
1418 uint32_t stencil_offset
= 0;
1419 info
.stencil_address
= stencil_mt
->bo
->gtt_offset
+ stencil_mt
->offset
;
1423 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
1425 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
1427 /* Render target change */
1428 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
1430 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
1434 iris_set_constant_buffer(struct pipe_context
*ctx
,
1435 enum pipe_shader_type p_stage
, unsigned index
,
1436 const struct pipe_constant_buffer
*input
)
1438 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1439 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1440 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1441 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
1442 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
1444 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1445 if (input
->user_buffer
) {
1446 u_upload_data(ctx
->const_uploader
, 0, input
->buffer_size
, 32,
1447 input
->user_buffer
, &cbuf
->data
.offset
,
1450 pipe_resource_reference(&cbuf
->data
.res
, input
->buffer
);
1453 // XXX: these are not retained forever, use a separate uploader?
1455 upload_state(ice
->state
.surface_uploader
, &cbuf
->surface_state
,
1456 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1457 if (!unlikely(map
)) {
1458 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
1462 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
1463 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state
.res
);
1464 cbuf
->surface_state
.offset
+= iris_bo_offset_from_base_address(surf_bo
);
1466 isl_buffer_fill_state(&screen
->isl_dev
, map
,
1467 .address
= res
->bo
->gtt_offset
+ cbuf
->data
.offset
,
1468 .size_B
= input
->buffer_size
,
1469 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
1473 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
1474 pipe_resource_reference(&cbuf
->surface_state
.res
, NULL
);
1477 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
1478 // XXX: maybe not necessary all the time...?
1479 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1483 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1484 struct pipe_sampler_view
*state
)
1486 struct iris_sampler_view
*isv
= (void *) state
;
1487 pipe_resource_reference(&state
->texture
, NULL
);
1488 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1494 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1496 struct iris_surface
*surf
= (void *) p_surf
;
1497 pipe_resource_reference(&p_surf
->texture
, NULL
);
1498 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
1503 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1509 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
1511 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
1512 pipe_resource_reference(&cso
->resources
[i
], NULL
);
1516 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1517 unsigned start_slot
, unsigned count
,
1518 const struct pipe_vertex_buffer
*buffers
)
1520 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1521 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
1523 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
1528 cso
->num_buffers
= count
;
1530 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1531 vb
.DWordLength
= 4 * MAX2(cso
->num_buffers
, 1) - 1;
1534 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1537 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1538 vb
.VertexBufferIndex
= start_slot
;
1539 vb
.NullVertexBuffer
= true;
1540 vb
.AddressModifyEnable
= true;
1544 for (unsigned i
= 0; i
< count
; i
++) {
1545 assert(!buffers
[i
].is_user_buffer
);
1547 pipe_resource_reference(&cso
->resources
[i
], buffers
[i
].buffer
.resource
);
1548 struct iris_resource
*res
= (void *) cso
->resources
[i
];
1550 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1551 vb
.VertexBufferIndex
= start_slot
+ i
;
1553 vb
.AddressModifyEnable
= true;
1554 vb
.BufferPitch
= buffers
[i
].stride
;
1555 vb
.BufferSize
= res
->bo
->size
;
1556 vb
.BufferStartingAddress
=
1557 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffers
[i
].buffer_offset
);
1560 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1563 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1566 struct iris_vertex_element_state
{
1567 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1568 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
1573 iris_create_vertex_elements(struct pipe_context
*ctx
,
1575 const struct pipe_vertex_element
*state
)
1577 struct iris_vertex_element_state
*cso
=
1578 malloc(sizeof(struct iris_vertex_element_state
));
1580 cso
->count
= MAX2(count
, 1);
1583 * - create edge flag one
1585 * - if those are necessary, use count + 1/2/3... OR in the length
1587 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
1588 ve
.DWordLength
= 1 + GENX(VERTEX_ELEMENT_STATE_length
) * cso
->count
- 2;
1591 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1592 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
1595 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1597 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
1598 ve
.Component0Control
= VFCOMP_STORE_0
;
1599 ve
.Component1Control
= VFCOMP_STORE_0
;
1600 ve
.Component2Control
= VFCOMP_STORE_0
;
1601 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
1604 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
1608 for (int i
= 0; i
< count
; i
++) {
1609 enum isl_format isl_format
=
1610 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1611 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
1612 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
1614 switch (isl_format_get_num_channels(isl_format
)) {
1615 case 0: comp
[0] = VFCOMP_STORE_0
;
1616 case 1: comp
[1] = VFCOMP_STORE_0
;
1617 case 2: comp
[2] = VFCOMP_STORE_0
;
1619 comp
[3] = isl_format_has_int_channel(isl_format
) ? VFCOMP_STORE_1_INT
1620 : VFCOMP_STORE_1_FP
;
1623 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1624 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1626 ve
.SourceElementOffset
= state
[i
].src_offset
;
1627 ve
.SourceElementFormat
= isl_format
;
1628 ve
.Component0Control
= comp
[0];
1629 ve
.Component1Control
= comp
[1];
1630 ve
.Component2Control
= comp
[2];
1631 ve
.Component3Control
= comp
[3];
1634 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
1635 vi
.VertexElementIndex
= i
;
1636 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1637 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1640 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1641 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
1648 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
1650 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1652 ice
->state
.cso_vertex_elements
= state
;
1653 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
1657 iris_create_compute_state(struct pipe_context
*ctx
,
1658 const struct pipe_compute_state
*state
)
1663 struct iris_stream_output_target
{
1664 struct pipe_stream_output_target base
;
1666 uint32_t so_buffer
[GENX(3DSTATE_SO_BUFFER_length
)];
1668 struct iris_state_ref offset
;
1671 static struct pipe_stream_output_target
*
1672 iris_create_stream_output_target(struct pipe_context
*ctx
,
1673 struct pipe_resource
*res
,
1674 unsigned buffer_offset
,
1675 unsigned buffer_size
)
1677 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
1681 pipe_reference_init(&cso
->base
.reference
, 1);
1682 pipe_resource_reference(&cso
->base
.buffer
, res
);
1683 cso
->base
.buffer_offset
= buffer_offset
;
1684 cso
->base
.buffer_size
= buffer_size
;
1685 cso
->base
.context
= ctx
;
1687 upload_state(ctx
->stream_uploader
, &cso
->offset
, 4, 4);
1689 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), cso
->so_buffer
, sob
) {
1690 sob
.SurfaceBaseAddress
=
1691 rw_bo(NULL
, iris_resource_bo(res
)->gtt_offset
+ buffer_offset
);
1692 sob
.SOBufferEnable
= true;
1693 sob
.StreamOffsetWriteEnable
= true;
1694 sob
.StreamOutputBufferOffsetAddressEnable
= true;
1695 sob
.MOCS
= MOCS_WB
; // XXX: MOCS
1697 sob
.SurfaceSize
= MAX2(buffer_size
/ 4, 1) - 1;
1698 sob
.StreamOutputBufferOffsetAddress
=
1699 rw_bo(NULL
, iris_resource_bo(cso
->offset
.res
)->gtt_offset
+ cso
->offset
.offset
);
1701 /* .SOBufferIndex and .StreamOffset are filled in later */
1708 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
1709 struct pipe_stream_output_target
*state
)
1711 struct iris_stream_output_target
*cso
= (void *) state
;
1713 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
1714 pipe_resource_reference(&cso
->offset
.res
, NULL
);
1720 iris_set_stream_output_targets(struct pipe_context
*ctx
,
1721 unsigned num_targets
,
1722 struct pipe_stream_output_target
**targets
,
1723 const unsigned *offsets
)
1725 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1726 struct iris_genx_state
*genx
= ice
->state
.genx
;
1727 uint32_t *so_buffers
= genx
->so_buffers
;
1729 const bool active
= num_targets
> 0;
1730 if (ice
->state
.streamout_active
!= active
) {
1731 ice
->state
.streamout_active
= active
;
1732 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1735 for (int i
= 0; i
< 4; i
++) {
1736 pipe_so_target_reference(&ice
->state
.so_target
[i
],
1737 i
< num_targets
? targets
[i
] : NULL
);
1740 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
1744 for (unsigned i
= 0; i
< 4; i
++,
1745 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
1747 if (i
>= num_targets
|| !targets
[i
]) {
1748 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
1749 sob
.SOBufferIndex
= i
;
1753 /* Note that offsets[i] will either be 0, causing us to zero
1754 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
1755 * "continue appending at the existing offset."
1757 assert(offsets
[i
] == 0 || offsets
[i
] == 0xFFFFFFFF);
1759 uint32_t dynamic
[GENX(3DSTATE_SO_BUFFER_length
)];
1760 iris_pack_state(GENX(3DSTATE_SO_BUFFER
), dynamic
, dyns
) {
1761 dyns
.SOBufferIndex
= i
;
1762 dyns
.StreamOffset
= offsets
[i
];
1765 struct iris_stream_output_target
*tgt
= (void *) targets
[i
];
1766 for (uint32_t j
= 0; j
< GENX(3DSTATE_SO_BUFFER_length
); j
++) {
1767 so_buffers
[j
] = tgt
->so_buffer
[j
] | dynamic
[j
];
1771 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
1775 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
1776 const struct brw_vue_map
*vue_map
)
1778 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
1779 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
1780 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
1781 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
1783 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
1785 memset(so_decl
, 0, sizeof(so_decl
));
1787 /* Construct the list of SO_DECLs to be emitted. The formatting of the
1788 * command feels strange -- each dword pair contains a SO_DECL per stream.
1790 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
1791 const struct pipe_stream_output
*output
= &info
->output
[i
];
1792 const int buffer
= output
->output_buffer
;
1793 const int varying
= output
->register_index
;
1794 const unsigned stream_id
= output
->stream
;
1795 assert(stream_id
< MAX_VERTEX_STREAMS
);
1797 buffer_mask
[stream_id
] |= 1 << buffer
;
1799 assert(vue_map
->varying_to_slot
[varying
] >= 0);
1801 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
1802 * array. Instead, it simply increments DstOffset for the following
1803 * input by the number of components that should be skipped.
1805 * Our hardware is unusual in that it requires us to program SO_DECLs
1806 * for fake "hole" components, rather than simply taking the offset
1807 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
1808 * program as many size = 4 holes as we can, then a final hole to
1809 * accommodate the final 1, 2, or 3 remaining.
1811 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
1813 while (skip_components
> 0) {
1814 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
1816 .OutputBufferSlot
= output
->output_buffer
,
1817 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
1819 skip_components
-= 4;
1822 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
1824 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
1825 .OutputBufferSlot
= output
->output_buffer
,
1826 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
1828 ((1 << output
->num_components
) - 1) << output
->start_component
,
1831 if (decls
[stream_id
] > max_decls
)
1832 max_decls
= decls
[stream_id
];
1835 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
1836 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
1837 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
1839 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
1840 int urb_entry_read_offset
= 0;
1841 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
1842 urb_entry_read_offset
;
1844 /* We always read the whole vertex. This could be reduced at some
1845 * point by reading less and offsetting the register index in the
1848 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
1849 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
1850 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
1851 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
1852 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
1853 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
1854 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
1855 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
1857 /* Set buffer pitches; 0 means unbound. */
1858 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
1859 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
1860 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
1861 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
1864 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
1865 list
.DWordLength
= 3 + 2 * max_decls
- 2;
1866 list
.StreamtoBufferSelects0
= buffer_mask
[0];
1867 list
.StreamtoBufferSelects1
= buffer_mask
[1];
1868 list
.StreamtoBufferSelects2
= buffer_mask
[2];
1869 list
.StreamtoBufferSelects3
= buffer_mask
[3];
1870 list
.NumEntries0
= decls
[0];
1871 list
.NumEntries1
= decls
[1];
1872 list
.NumEntries2
= decls
[2];
1873 list
.NumEntries3
= decls
[3];
1876 for (int i
= 0; i
< max_decls
; i
++) {
1877 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
1878 entry
.Stream0Decl
= so_decl
[0][i
];
1879 entry
.Stream1Decl
= so_decl
[1][i
];
1880 entry
.Stream2Decl
= so_decl
[2][i
];
1881 entry
.Stream3Decl
= so_decl
[3][i
];
1889 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
1890 const struct brw_vue_map
*last_vue_map
,
1891 bool two_sided_color
,
1892 unsigned *out_offset
,
1893 unsigned *out_length
)
1895 /* The compiler computes the first URB slot without considering COL/BFC
1896 * swizzling (because it doesn't know whether it's enabled), so we need
1897 * to do that here too. This may result in a smaller offset, which
1900 const unsigned first_slot
=
1901 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
1903 /* This becomes the URB read offset (counted in pairs of slots). */
1904 assert(first_slot
% 2 == 0);
1905 *out_offset
= first_slot
/ 2;
1907 /* We need to adjust the inputs read to account for front/back color
1908 * swizzling, as it can make the URB length longer.
1910 for (int c
= 0; c
<= 1; c
++) {
1911 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
1912 /* If two sided color is enabled, the fragment shader's gl_Color
1913 * (COL0) input comes from either the gl_FrontColor (COL0) or
1914 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
1916 if (two_sided_color
)
1917 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1919 /* If front color isn't written, we opt to give them back color
1920 * instead of an undefined value. Switch from COL to BFC.
1922 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
1923 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
1924 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1929 /* Compute the minimum URB Read Length necessary for the FS inputs.
1931 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1932 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1934 * "This field should be set to the minimum length required to read the
1935 * maximum source attribute. The maximum source attribute is indicated
1936 * by the maximum value of the enabled Attribute # Source Attribute if
1937 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1938 * enable is not set.
1939 * read_length = ceiling((max_source_attr + 1) / 2)
1941 * [errata] Corruption/Hang possible if length programmed larger than
1944 * Similar text exists for Ivy Bridge.
1946 * We find the last URB slot that's actually read by the FS.
1948 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
1949 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
1950 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
1953 /* The URB read length is the difference of the two, counted in pairs. */
1954 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
1958 iris_emit_sbe_swiz(struct iris_batch
*batch
,
1959 const struct iris_context
*ice
,
1960 unsigned urb_read_offset
)
1962 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
1963 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
1964 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
1965 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
1966 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
1968 /* XXX: this should be generated when putting programs in place */
1970 // XXX: raster->sprite_coord_enable
1972 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
1973 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
1974 if (input_index
< 0 || input_index
>= 16)
1977 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
1978 &attr_overrides
[input_index
];
1980 /* Viewport and Layer are stored in the VUE header. We need to override
1981 * them to zero if earlier stages didn't write them, as GL requires that
1982 * they read back as zero when not explicitly set.
1985 case VARYING_SLOT_VIEWPORT
:
1986 case VARYING_SLOT_LAYER
:
1987 attr
->ComponentOverrideX
= true;
1988 attr
->ComponentOverrideW
= true;
1989 attr
->ConstantSource
= CONST_0000
;
1991 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
1992 attr
->ComponentOverrideY
= true;
1993 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
1994 attr
->ComponentOverrideZ
= true;
1997 case VARYING_SLOT_PRIMITIVE_ID
:
1998 attr
->ComponentOverrideX
= true;
1999 attr
->ComponentOverrideY
= true;
2000 attr
->ComponentOverrideZ
= true;
2001 attr
->ComponentOverrideW
= true;
2002 attr
->ConstantSource
= PRIM_ID
;
2009 int slot
= vue_map
->varying_to_slot
[fs_attr
];
2011 /* If there was only a back color written but not front, use back
2012 * as the color instead of undefined.
2014 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
2015 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
2016 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
2017 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
2019 /* Not written by the previous stage - undefined. */
2021 attr
->ComponentOverrideX
= true;
2022 attr
->ComponentOverrideY
= true;
2023 attr
->ComponentOverrideZ
= true;
2024 attr
->ComponentOverrideW
= true;
2025 attr
->ConstantSource
= CONST_0001_FLOAT
;
2029 /* Compute the location of the attribute relative to the read offset,
2030 * which is counted in 256-bit increments (two 128-bit VUE slots).
2032 const int source_attr
= slot
- 2 * urb_read_offset
;
2033 assert(source_attr
>= 0 && source_attr
<= 32);
2034 attr
->SourceAttribute
= source_attr
;
2036 /* If we are doing two-sided color, and the VUE slot following this one
2037 * represents a back-facing color, then we need to instruct the SF unit
2038 * to do back-facing swizzling.
2040 if (cso_rast
->light_twoside
&&
2041 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
2042 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
2043 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
2044 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
2045 attr
->SwizzleSelect
= INPUTATTR_FACING
;
2048 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
2049 for (int i
= 0; i
< 16; i
++)
2050 sbes
.Attribute
[i
] = attr_overrides
[i
];
2055 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
2057 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2058 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2059 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2060 struct pipe_shader_state
*p_fs
=
2061 (void *) ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
2062 assert(p_fs
->type
== PIPE_SHADER_IR_NIR
);
2063 nir_shader
*fs_nir
= p_fs
->ir
.nir
;
2065 unsigned urb_read_offset
, urb_read_length
;
2066 iris_compute_sbe_urb_read_interval(fs_nir
->info
.inputs_read
,
2067 ice
->shaders
.last_vue_map
,
2068 cso_rast
->light_twoside
,
2069 &urb_read_offset
, &urb_read_length
);
2071 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
2072 sbe
.AttributeSwizzleEnable
= true;
2073 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2074 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
2075 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
2076 sbe
.VertexURBEntryReadLength
= urb_read_length
;
2077 sbe
.ForceVertexURBEntryReadOffset
= true;
2078 sbe
.ForceVertexURBEntryReadLength
= true;
2079 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
2081 for (int i
= 0; i
< 32; i
++) {
2082 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
2086 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
);
2090 iris_bind_compute_state(struct pipe_context
*ctx
, void *state
)
2095 iris_populate_sampler_key(const struct iris_context
*ice
,
2096 struct brw_sampler_prog_key_data
*key
)
2098 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
2099 key
->swizzles
[i
] = 0x688; /* XYZW */
2104 iris_populate_vs_key(const struct iris_context
*ice
,
2105 struct brw_vs_prog_key
*key
)
2107 iris_populate_sampler_key(ice
, &key
->tex
);
2111 iris_populate_tcs_key(const struct iris_context
*ice
,
2112 struct brw_tcs_prog_key
*key
)
2114 iris_populate_sampler_key(ice
, &key
->tex
);
2118 iris_populate_tes_key(const struct iris_context
*ice
,
2119 struct brw_tes_prog_key
*key
)
2121 iris_populate_sampler_key(ice
, &key
->tex
);
2125 iris_populate_gs_key(const struct iris_context
*ice
,
2126 struct brw_gs_prog_key
*key
)
2128 iris_populate_sampler_key(ice
, &key
->tex
);
2132 iris_populate_fs_key(const struct iris_context
*ice
,
2133 struct brw_wm_prog_key
*key
)
2135 iris_populate_sampler_key(ice
, &key
->tex
);
2137 /* XXX: dirty flags? */
2138 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
2139 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
2140 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
2141 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
2143 key
->nr_color_regions
= fb
->nr_cbufs
;
2145 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
2147 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
2148 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
2150 /* XXX: only bother if COL0/1 are read */
2151 key
->flat_shade
= rast
->flatshade
;
2153 key
->persample_interp
= rast
->force_persample_interp
;
2154 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
2156 key
->coherent_fb_fetch
= true;
2158 // XXX: uint64_t input_slots_valid; - for >16 inputs
2160 // XXX: key->force_dual_color_blend for unigine
2161 // XXX: respect hint for high_quality_derivatives:1;
2165 // XXX: these need to go in INIT_THREAD_DISPATCH_FIELDS
2166 pkt
.SamplerCount
= \
2167 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4); \
2168 pkt
.PerThreadScratchSpace
= prog_data
->total_scratch
== 0 ? 0 : \
2169 ffs(stage_state
->per_thread_scratch
) - 11; \
2174 KSP(const struct iris_compiled_shader
*shader
)
2176 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
2177 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
2180 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2181 pkt.KernelStartPointer = KSP(shader); \
2182 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
2183 pkt.FloatingPointMode = prog_data->use_alt_mode; \
2185 pkt.DispatchGRFStartRegisterForURBData = \
2186 prog_data->dispatch_grf_start_reg; \
2187 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2188 pkt.prefix##URBEntryReadOffset = 0; \
2190 pkt.StatisticsEnable = true; \
2194 iris_store_vs_state(const struct gen_device_info
*devinfo
,
2195 struct iris_compiled_shader
*shader
)
2197 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2198 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2200 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
2201 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2202 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2203 vs
.SIMD8DispatchEnable
= true;
2204 vs
.UserClipDistanceCullTestEnableBitmask
=
2205 vue_prog_data
->cull_distance_mask
;
2210 iris_store_tcs_state(const struct gen_device_info
*devinfo
,
2211 struct iris_compiled_shader
*shader
)
2213 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2214 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2215 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
2217 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
2218 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
2220 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
2221 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
2222 hs
.IncludeVertexHandles
= true;
2227 iris_store_tes_state(const struct gen_device_info
*devinfo
,
2228 struct iris_compiled_shader
*shader
)
2230 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2231 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2232 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
2234 uint32_t *te_state
= (void *) shader
->derived_data
;
2235 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
2237 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
2238 te
.Partitioning
= tes_prog_data
->partitioning
;
2239 te
.OutputTopology
= tes_prog_data
->output_topology
;
2240 te
.TEDomain
= tes_prog_data
->domain
;
2242 te
.MaximumTessellationFactorOdd
= 63.0;
2243 te
.MaximumTessellationFactorNotOdd
= 64.0;
2246 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
2247 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
2249 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
2250 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
2251 ds
.ComputeWCoordinateEnable
=
2252 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
2254 ds
.UserClipDistanceCullTestEnableBitmask
=
2255 vue_prog_data
->cull_distance_mask
;
2261 iris_store_gs_state(const struct gen_device_info
*devinfo
,
2262 struct iris_compiled_shader
*shader
)
2264 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2265 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2266 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
2268 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
2269 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2271 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2272 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2273 gs
.ControlDataHeaderSize
=
2274 gs_prog_data
->control_data_header_size_hwords
;
2275 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2276 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
2277 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2278 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2279 gs
.ReorderMode
= TRAILING
;
2280 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2281 gs
.MaximumNumberofThreads
=
2282 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2283 : (devinfo
->max_gs_threads
- 1);
2285 if (gs_prog_data
->static_vertex_count
!= -1) {
2286 gs
.StaticOutput
= true;
2287 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2289 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2291 gs
.UserClipDistanceCullTestEnableBitmask
=
2292 vue_prog_data
->cull_distance_mask
;
2294 const int urb_entry_write_offset
= 1;
2295 const uint32_t urb_entry_output_length
=
2296 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2297 urb_entry_write_offset
;
2299 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2300 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2305 iris_store_fs_state(const struct gen_device_info
*devinfo
,
2306 struct iris_compiled_shader
*shader
)
2308 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2309 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
2311 uint32_t *ps_state
= (void *) shader
->derived_data
;
2312 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
2314 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
2315 ps
.VectorMaskEnable
= true;
2316 //ps.SamplerCount = ...
2317 ps
.BindingTableEntryCount
= prog_data
->binding_table
.size_bytes
/ 4;
2318 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
2319 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
2321 ps
.PushConstantEnable
= prog_data
->nr_params
> 0 ||
2322 prog_data
->ubo_ranges
[0].length
> 0;
2324 /* From the documentation for this packet:
2325 * "If the PS kernel does not need the Position XY Offsets to
2326 * compute a Position Value, then this field should be programmed
2327 * to POSOFFSET_NONE."
2329 * "SW Recommendation: If the PS kernel needs the Position Offsets
2330 * to compute a Position XY value, this field should match Position
2331 * ZW Interpolation Mode to ensure a consistent position.xyzw
2334 * We only require XY sample offsets. So, this recommendation doesn't
2335 * look useful at the moment. We might need this in future.
2337 ps
.PositionXYOffsetSelect
=
2338 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
2339 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
2340 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
2341 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
2343 // XXX: Disable SIMD32 with 16x MSAA
2345 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
2346 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
2347 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
2348 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
2349 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
2350 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
2352 ps
.KernelStartPointer0
=
2353 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
2354 ps
.KernelStartPointer1
=
2355 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
2356 ps
.KernelStartPointer2
=
2357 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
2360 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
2361 psx
.PixelShaderValid
= true;
2362 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
2363 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
2364 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
2365 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
2366 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
2367 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
2369 if (wm_prog_data
->uses_sample_mask
) {
2370 /* TODO: conservative rasterization */
2371 if (wm_prog_data
->post_depth_coverage
)
2372 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
2374 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
2377 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
2378 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
2379 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
2386 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
2388 assert(cache_id
<= IRIS_CACHE_BLORP
);
2390 static const unsigned dwords
[] = {
2391 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
2392 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
2393 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
2394 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
2396 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
2397 [IRIS_CACHE_CS
] = 0,
2398 [IRIS_CACHE_BLORP
] = 0,
2401 return sizeof(uint32_t) * dwords
[cache_id
];
2405 iris_store_derived_program_state(const struct gen_device_info
*devinfo
,
2406 enum iris_program_cache_id cache_id
,
2407 struct iris_compiled_shader
*shader
)
2411 iris_store_vs_state(devinfo
, shader
);
2413 case IRIS_CACHE_TCS
:
2414 iris_store_tcs_state(devinfo
, shader
);
2416 case IRIS_CACHE_TES
:
2417 iris_store_tes_state(devinfo
, shader
);
2420 iris_store_gs_state(devinfo
, shader
);
2423 iris_store_fs_state(devinfo
, shader
);
2426 case IRIS_CACHE_BLORP
:
2434 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
2436 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
2437 const unsigned push_size_kB
= 32;
2438 unsigned entries
[4];
2442 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2443 if (!ice
->shaders
.prog
[i
]) {
2446 struct brw_vue_prog_data
*vue_prog_data
=
2447 (void *) ice
->shaders
.prog
[i
]->prog_data
;
2448 size
[i
] = vue_prog_data
->urb_entry_size
;
2450 assert(size
[i
] != 0);
2453 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
2454 1024 * ice
->shaders
.urb_size
,
2455 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
2456 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
2457 size
, entries
, start
);
2459 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2460 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
2461 urb
._3DCommandSubOpcode
+= i
;
2462 urb
.VSURBStartingAddress
= start
[i
];
2463 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
2464 urb
.VSNumberofURBEntries
= entries
[i
];
2469 static const uint32_t push_constant_opcodes
[] = {
2470 [MESA_SHADER_VERTEX
] = 21,
2471 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2472 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2473 [MESA_SHADER_GEOMETRY
] = 22,
2474 [MESA_SHADER_FRAGMENT
] = 23,
2475 [MESA_SHADER_COMPUTE
] = 0,
2479 * Add a surface to the validation list, as well as the buffer containing
2480 * the corresponding SURFACE_STATE.
2482 * Returns the binding table entry (offset to SURFACE_STATE).
2485 use_surface(struct iris_batch
*batch
,
2486 struct pipe_surface
*p_surf
,
2489 struct iris_surface
*surf
= (void *) p_surf
;
2491 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
2492 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
2494 return surf
->surface_state
.offset
;
2498 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
2500 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->pipe
.texture
), false);
2501 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
2503 return isv
->surface_state
.offset
;
2507 use_const_buffer(struct iris_batch
*batch
, struct iris_const_buffer
*cbuf
)
2509 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->data
.res
), false);
2510 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->surface_state
.res
), false);
2512 return cbuf
->surface_state
.offset
;
2516 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
2518 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
2520 iris_use_pinned_bo(batch
, state_bo
, false);
2522 return ice
->state
.unbound_tex
.offset
;
2526 iris_populate_binding_table(struct iris_context
*ice
,
2527 struct iris_batch
*batch
,
2528 gl_shader_stage stage
)
2530 const struct iris_binder
*binder
= &batch
->binder
;
2531 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2537 // - ubos/ssbos/abos
2540 // - render targets - write and read
2542 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
2543 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
2546 if (stage
== MESA_SHADER_FRAGMENT
) {
2547 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2548 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
2549 bt_map
[s
++] = use_surface(batch
, cso_fb
->cbufs
[i
], true);
2553 //assert(prog_data->binding_table.texture_start ==
2554 //(ice->state.num_textures[stage] ? s : 0xd0d0d0d0));
2556 for (int i
= 0; i
< ice
->state
.num_textures
[stage
]; i
++) {
2557 struct iris_sampler_view
*view
= ice
->state
.textures
[stage
][i
];
2558 bt_map
[s
++] = view
? use_sampler_view(batch
, view
)
2559 : use_null_surface(batch
, ice
);
2562 // XXX: want the number of BTE's to shorten this loop
2563 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2564 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
2565 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[i
];
2566 if (!cbuf
->surface_state
.res
)
2569 bt_map
[s
++] = use_const_buffer(batch
, cbuf
);
2572 // XXX: not implemented yet
2573 assert(prog_data
->binding_table
.pull_constants_start
== 0xd0d0d0d0);
2574 assert(prog_data
->binding_table
.ubo_start
== 0xd0d0d0d0);
2575 assert(prog_data
->binding_table
.ssbo_start
== 0xd0d0d0d0);
2576 assert(prog_data
->binding_table
.image_start
== 0xd0d0d0d0);
2577 assert(prog_data
->binding_table
.shader_time_start
== 0xd0d0d0d0);
2578 //assert(prog_data->binding_table.plane_start[1] == 0xd0d0d0d0);
2579 //assert(prog_data->binding_table.plane_start[2] == 0xd0d0d0d0);
2584 iris_use_optional_res(struct iris_batch
*batch
,
2585 struct pipe_resource
*res
,
2589 struct iris_bo
*bo
= iris_resource_bo(res
);
2590 iris_use_pinned_bo(batch
, bo
, writeable
);
2596 * Pin any BOs which were installed by a previous batch, and restored
2597 * via the hardware logical context mechanism.
2599 * We don't need to re-emit all state every batch - the hardware context
2600 * mechanism will save and restore it for us. This includes pointers to
2601 * various BOs...which won't exist unless we ask the kernel to pin them
2602 * by adding them to the validation list.
2604 * We can skip buffers if we've re-emitted those packets, as we're
2605 * overwriting those stale pointers with new ones, and don't actually
2606 * refer to the old BOs.
2609 iris_restore_context_saved_bos(struct iris_context
*ice
,
2610 struct iris_batch
*batch
,
2611 const struct pipe_draw_info
*draw
)
2613 // XXX: whack IRIS_SHADER_DIRTY_BINDING_TABLE on new batch
2615 const uint64_t clean
= ~ice
->state
.dirty
;
2617 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
2618 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
2621 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
2622 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
2625 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
2626 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
2629 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
2630 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
2633 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
2634 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
2637 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2638 if (clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
))
2641 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2642 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2647 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
2649 for (int i
= 0; i
< 4; i
++) {
2650 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2652 if (range
->length
== 0)
2655 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
2656 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2659 iris_use_pinned_bo(batch
, res
->bo
, false);
2661 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
2665 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2666 struct pipe_resource
*res
= ice
->state
.sampler_table
[stage
].res
;
2668 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
2671 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2672 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
2673 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2675 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
2676 iris_use_pinned_bo(batch
, bo
, false);
2679 // XXX: scratch buffer
2683 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
2684 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2686 if (cso_fb
->zsbuf
) {
2687 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
2688 // XXX: depth might not be writable...
2689 iris_use_pinned_bo(batch
, zres
->bo
, true);
2693 if (draw
->index_size
> 0) {
2694 // XXX: index buffer
2697 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
2698 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
2699 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
2700 struct iris_resource
*res
= (void *) cso
->resources
[i
];
2701 iris_use_pinned_bo(batch
, res
->bo
, false);
2707 iris_upload_render_state(struct iris_context
*ice
,
2708 struct iris_batch
*batch
,
2709 const struct pipe_draw_info
*draw
)
2711 const uint64_t dirty
= ice
->state
.dirty
;
2713 struct iris_genx_state
*genx
= ice
->state
.genx
;
2714 struct brw_wm_prog_data
*wm_prog_data
= (void *)
2715 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2717 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
2718 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2719 uint32_t cc_vp_address
;
2721 /* XXX: could avoid streaming for depth_clip [0,1] case. */
2722 uint32_t *cc_vp_map
=
2723 stream_state(batch
, ice
->state
.dynamic_uploader
,
2724 &ice
->state
.last_res
.cc_vp
,
2725 4 * ice
->state
.num_viewports
*
2726 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
2727 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
2729 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
2730 cso_rast
->clip_halfz
, &zmin
, &zmax
);
2731 if (cso_rast
->depth_clip_near
)
2733 if (cso_rast
->depth_clip_far
)
2736 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
2737 ccv
.MinimumDepth
= zmin
;
2738 ccv
.MaximumDepth
= zmax
;
2741 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
2744 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2745 ptr
.CCViewportPointer
= cc_vp_address
;
2749 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
2750 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2751 ptr
.SFClipViewportPointer
=
2752 emit_state(batch
, ice
->state
.dynamic_uploader
,
2753 &ice
->state
.last_res
.sf_cl_vp
,
2754 genx
->sf_cl_vp
, 4 * GENX(SF_CLIP_VIEWPORT_length
) *
2755 ice
->state
.num_viewports
, 64);
2761 // XXX: this is only flagged at setup, we assume a static configuration
2762 if (dirty
& IRIS_DIRTY_URB
) {
2763 iris_upload_urb_config(ice
, batch
);
2766 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
2767 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2768 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2769 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2770 const int num_dwords
= 4 * (GENX(BLEND_STATE_length
) +
2771 cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
));
2772 uint32_t blend_offset
;
2773 uint32_t *blend_map
=
2774 stream_state(batch
, ice
->state
.dynamic_uploader
,
2775 &ice
->state
.last_res
.blend
,
2776 4 * num_dwords
, 64, &blend_offset
);
2778 uint32_t blend_state_header
;
2779 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
2780 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2781 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
2784 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
2785 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1],
2786 sizeof(cso_blend
->blend_state
) - sizeof(uint32_t));
2788 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2789 ptr
.BlendStatePointer
= blend_offset
;
2790 ptr
.BlendStatePointerValid
= true;
2794 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
2795 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2798 stream_state(batch
, ice
->state
.dynamic_uploader
,
2799 &ice
->state
.last_res
.color_calc
,
2800 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
2802 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
2803 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
2804 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
2805 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
2806 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
2807 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
2808 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
2810 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2811 ptr
.ColorCalcStatePointer
= cc_offset
;
2812 ptr
.ColorCalcStatePointerValid
= true;
2816 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2817 // XXX: wrong dirty tracking...
2818 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
2821 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2822 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2827 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
2829 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2830 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2832 /* The Skylake PRM contains the following restriction:
2834 * "The driver must ensure The following case does not occur
2835 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2836 * buffer 3 read length equal to zero committed followed by a
2837 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2840 * To avoid this, we program the buffers in the highest slots.
2841 * This way, slot 0 is only used if slot 3 is also used.
2845 for (int i
= 3; i
>= 0; i
--) {
2846 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2848 if (range
->length
== 0)
2851 // XXX: is range->block a constbuf index? it would be nice
2852 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
2853 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2855 assert(cbuf
->data
.offset
% 32 == 0);
2857 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
2858 pkt
.ConstantBody
.Buffer
[n
] =
2859 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->data
.offset
)
2860 : ro_bo(batch
->screen
->workaround_bo
, 0);
2867 struct iris_binder
*binder
= &batch
->binder
;
2869 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2870 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
2871 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
2872 ptr
._3DCommandSubOpcode
= 38 + stage
;
2873 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
2878 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2879 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
2880 iris_populate_binding_table(ice
, batch
, stage
);
2884 if (ice
->state
.need_border_colors
)
2885 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
2887 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2888 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
2889 !ice
->shaders
.prog
[stage
])
2892 struct pipe_resource
*res
= ice
->state
.sampler_table
[stage
].res
;
2894 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
2896 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
2897 ptr
._3DCommandSubOpcode
= 43 + stage
;
2898 ptr
.PointertoVSSamplerState
= ice
->state
.sampler_table
[stage
].offset
;
2902 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
2903 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
2905 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
2906 if (ice
->state
.framebuffer
.samples
> 0)
2907 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
2911 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
2912 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
2913 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
2917 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2918 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
2921 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2924 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
2925 iris_use_pinned_bo(batch
, cache
->bo
, false);
2926 iris_batch_emit(batch
, shader
->derived_data
,
2927 iris_derived_program_state_size(stage
));
2929 if (stage
== MESA_SHADER_TESS_EVAL
) {
2930 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
2931 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
2932 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
2933 } else if (stage
== MESA_SHADER_GEOMETRY
) {
2934 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
2939 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
2940 iris_batch_emit(batch
, genx
->so_buffers
,
2941 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
2942 for (int i
= 0; i
< 4; i
++) {
2943 struct iris_stream_output_target
*tgt
=
2944 (void *) ice
->state
.so_target
[i
];
2946 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
2948 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
), true);
2953 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
2954 uint32_t *decl_list
=
2955 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
2956 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
2959 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
2960 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2962 if (!ice
->state
.streamout_active
) {
2963 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
2965 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
2966 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
2967 sol
.SOFunctionEnable
= true;
2968 sol
.SOStatisticsEnable
= true;
2970 // XXX: GL_PRIMITIVES_GENERATED query
2971 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
;
2972 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
2975 assert(ice
->state
.streamout
);
2977 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
2978 GENX(3DSTATE_STREAMOUT_length
));
2982 if (dirty
& IRIS_DIRTY_CLIP
) {
2983 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2984 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2986 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
2987 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
2988 if (wm_prog_data
->barycentric_interp_modes
&
2989 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
2990 cl
.NonPerspectiveBarycentricEnable
= true;
2992 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
2993 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
2995 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
2996 ARRAY_SIZE(cso_rast
->clip
));
2999 if (dirty
& IRIS_DIRTY_RASTER
) {
3000 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
3001 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
3002 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
3006 /* XXX: FS program updates needs to flag IRIS_DIRTY_WM */
3007 if (dirty
& IRIS_DIRTY_WM
) {
3008 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
3009 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
3011 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
3012 wm
.BarycentricInterpolationMode
=
3013 wm_prog_data
->barycentric_interp_modes
;
3015 if (wm_prog_data
->early_fragment_tests
)
3016 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
3017 else if (wm_prog_data
->has_side_effects
)
3018 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
3020 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
3024 // XXX: 3DSTATE_SBE, 3DSTATE_SBE_SWIZ
3025 // -> iris_raster_state (point sprite texture coordinate origin)
3026 // -> bunch of shader state...
3027 iris_emit_sbe(batch
, ice
);
3030 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
3031 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
3032 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
3033 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
3034 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
3035 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
3036 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
3039 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
3040 ARRAY_SIZE(cso_blend
->ps_blend
));
3043 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
3044 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
3045 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
3047 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
3048 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
3049 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
3050 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
3052 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
3055 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
3056 uint32_t scissor_offset
=
3057 emit_state(batch
, ice
->state
.dynamic_uploader
,
3058 &ice
->state
.last_res
.scissor
,
3059 ice
->state
.scissors
,
3060 sizeof(struct pipe_scissor_state
) *
3061 ice
->state
.num_viewports
, 32);
3063 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
3064 ptr
.ScissorRectPointer
= scissor_offset
;
3068 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
3069 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3070 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
3072 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
3074 if (cso_fb
->zsbuf
) {
3075 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
3076 // XXX: depth might not be writable...
3077 iris_use_pinned_bo(batch
, zres
->bo
, true);
3081 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
3082 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
3083 for (int i
= 0; i
< 32; i
++) {
3084 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
3089 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
3090 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
3091 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
3095 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
3096 topo
.PrimitiveTopologyType
=
3097 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
3101 if (draw
->index_size
> 0) {
3102 struct iris_resource
*res
= NULL
;
3105 if (draw
->has_user_indices
) {
3106 u_upload_data(ice
->ctx
.stream_uploader
, 0,
3107 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
3108 &offset
, (struct pipe_resource
**) &res
);
3110 res
= (struct iris_resource
*) draw
->index
.resource
;
3114 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
3115 ib
.IndexFormat
= draw
->index_size
>> 1;
3117 ib
.BufferSize
= res
->bo
->size
;
3118 ib
.BufferStartingAddress
= ro_bo(res
->bo
, offset
);
3122 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
3123 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
3124 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
3126 if (cso
->num_buffers
> 0) {
3127 iris_batch_emit(batch
, cso
->vertex_buffers
, sizeof(uint32_t) *
3128 (1 + vb_dwords
* cso
->num_buffers
));
3130 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
3131 struct iris_resource
*res
= (void *) cso
->resources
[i
];
3132 iris_use_pinned_bo(batch
, res
->bo
, false);
3137 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
3138 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
3139 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
3140 (1 + cso
->count
* GENX(VERTEX_ELEMENT_STATE_length
)));
3141 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
3142 cso
->count
* GENX(3DSTATE_VF_INSTANCING_length
));
3143 for (int i
= 0; i
< cso
->count
; i
++) {
3144 /* TODO: vertexid, instanceid support */
3145 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
);
3150 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
3151 if (draw
->primitive_restart
) {
3152 vf
.IndexedDrawCutIndexEnable
= true;
3153 vf
.CutIndex
= draw
->restart_index
;
3158 // XXX: Gen8 - PMA fix
3160 #define _3DPRIM_END_OFFSET 0x2420
3161 #define _3DPRIM_START_VERTEX 0x2430
3162 #define _3DPRIM_VERTEX_COUNT 0x2434
3163 #define _3DPRIM_INSTANCE_COUNT 0x2438
3164 #define _3DPRIM_START_INSTANCE 0x243C
3165 #define _3DPRIM_BASE_VERTEX 0x2440
3167 if (draw
->indirect
) {
3168 /* We don't support this MultidrawIndirect. */
3169 assert(!draw
->indirect
->indirect_draw_count
);
3171 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
3174 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3175 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
3176 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
3178 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3179 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
3180 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
3182 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3183 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
3184 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
3186 if (draw
->index_size
) {
3187 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3188 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
3189 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
3191 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3192 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
3193 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
3196 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3197 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
3198 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
3200 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3201 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
3207 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
3208 prim
.StartInstanceLocation
= draw
->start_instance
;
3209 prim
.InstanceCount
= draw
->instance_count
;
3210 prim
.VertexCountPerInstance
= draw
->count
;
3211 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
3213 // XXX: this is probably bonkers.
3214 prim
.StartVertexLocation
= draw
->start
;
3216 prim
.IndirectParameterEnable
= draw
->indirect
!= NULL
;
3218 if (draw
->index_size
) {
3219 prim
.BaseVertexLocation
+= draw
->index_bias
;
3221 prim
.StartVertexLocation
+= draw
->index_bias
;
3224 //prim.BaseVertexLocation = ...;
3227 if (!batch
->contains_draw
) {
3228 iris_restore_context_saved_bos(ice
, batch
, draw
);
3229 batch
->contains_draw
= true;
3234 * State module teardown.
3237 iris_destroy_state(struct iris_context
*ice
)
3239 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
3241 // XXX: unreference resources/surfaces.
3242 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
3243 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
3245 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
3247 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
3248 pipe_resource_reference(&ice
->state
.sampler_table
[stage
].res
, NULL
);
3250 free(ice
->state
.genx
);
3252 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
3253 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
3254 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
3255 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
3256 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
3260 flags_to_post_sync_op(uint32_t flags
)
3262 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
3263 return WriteImmediateData
;
3265 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
3266 return WritePSDepthCount
;
3268 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
3269 return WriteTimestamp
;
3275 * Do the given flags have a Post Sync or LRI Post Sync operation?
3277 static enum pipe_control_flags
3278 get_post_sync_flags(enum pipe_control_flags flags
)
3280 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
3281 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
3282 PIPE_CONTROL_WRITE_TIMESTAMP
|
3283 PIPE_CONTROL_LRI_POST_SYNC_OP
;
3285 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
3286 * "LRI Post Sync Operation". So more than one bit set would be illegal.
3288 assert(util_bitcount(flags
) <= 1);
3293 // XXX: compute support
3294 #define IS_COMPUTE_PIPELINE(batch) (batch->ring != I915_EXEC_RENDER)
3297 * Emit a series of PIPE_CONTROL commands, taking into account any
3298 * workarounds necessary to actually accomplish the caller's request.
3300 * Unless otherwise noted, spec quotations in this function come from:
3302 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
3303 * Restrictions for PIPE_CONTROL.
3306 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
3307 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
3309 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
3310 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
3311 enum pipe_control_flags non_lri_post_sync_flags
=
3312 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
3314 /* Recursive PIPE_CONTROL workarounds --------------------------------
3315 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
3317 * We do these first because we want to look at the original operation,
3318 * rather than any workarounds we set.
3320 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
3321 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
3322 * lists several workarounds:
3324 * "Project: SKL, KBL, BXT
3326 * If the VF Cache Invalidation Enable is set to a 1 in a
3327 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
3328 * sets to 0, with the VF Cache Invalidation Enable set to 0
3329 * needs to be sent prior to the PIPE_CONTROL with VF Cache
3330 * Invalidation Enable set to a 1."
3332 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
3335 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
3336 /* Project: SKL / Argument: LRI Post Sync Operation [23]
3338 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
3339 * programmed prior to programming a PIPECONTROL command with "LRI
3340 * Post Sync Operation" in GPGPU mode of operation (i.e when
3341 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
3343 * The same text exists a few rows below for Post Sync Op.
3345 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
3348 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
3350 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
3351 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
3352 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
3354 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
3358 /* "Flush Types" workarounds ---------------------------------------------
3359 * We do these now because they may add post-sync operations or CS stalls.
3362 if (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
3363 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
3365 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
3366 * 'Write PS Depth Count' or 'Write Timestamp'."
3369 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3370 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3371 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3372 bo
= batch
->screen
->workaround_bo
;
3376 /* #1130 from Gen10 workarounds page:
3378 * "Enable Depth Stall on every Post Sync Op if Render target Cache
3379 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
3380 * board stall if Render target cache flush is enabled."
3382 * Applicable to CNL B0 and C0 steppings only.
3384 * The wording here is unclear, and this workaround doesn't look anything
3385 * like the internal bug report recommendations, but leave it be for now...
3387 if (GEN_GEN
== 10) {
3388 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
3389 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
3390 } else if (flags
& non_lri_post_sync_flags
) {
3391 flags
|= PIPE_CONTROL_DEPTH_STALL
;
3395 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
3396 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
3398 * "This bit must be DISABLED for operations other than writing
3401 * This seems like nonsense. An Ivybridge workaround requires us to
3402 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
3403 * operation. Gen8+ requires us to emit depth stalls and depth cache
3404 * flushes together. So, it's hard to imagine this means anything other
3405 * than "we originally intended this to be used for PS_DEPTH_COUNT".
3407 * We ignore the supposed restriction and do nothing.
3411 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
3412 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
3413 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
3415 * "This bit must be DISABLED for End-of-pipe (Read) fences,
3416 * PS_DEPTH_COUNT or TIMESTAMP queries."
3418 * TODO: Implement end-of-pipe checking.
3420 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
3421 PIPE_CONTROL_WRITE_TIMESTAMP
)));
3424 if (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) {
3425 /* From the PIPE_CONTROL instruction table, bit 1:
3427 * "This bit is ignored if Depth Stall Enable is set.
3428 * Further, the render cache is not flushed even if Write Cache
3429 * Flush Enable bit is set."
3431 * We assert that the caller doesn't do this combination, to try and
3432 * prevent mistakes. It shouldn't hurt the GPU, though.
3434 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
3435 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
3438 /* PIPE_CONTROL page workarounds ------------------------------------- */
3440 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
3441 /* From the PIPE_CONTROL page itself:
3444 * Restriction: Pipe_control with CS-stall bit set must be issued
3445 * before a pipe-control command that has the State Cache
3446 * Invalidate bit set."
3448 flags
|= PIPE_CONTROL_CS_STALL
;
3451 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
3452 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
3455 * SW must always program Post-Sync Operation to "Write Immediate
3456 * Data" when Flush LLC is set."
3458 * For now, we just require the caller to do it.
3460 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
3463 /* "Post-Sync Operation" workarounds -------------------------------- */
3465 /* Project: All / Argument: Global Snapshot Count Reset [19]
3467 * "This bit must not be exercised on any product.
3468 * Requires stall bit ([20] of DW1) set."
3470 * We don't use this, so we just assert that it isn't used. The
3471 * PIPE_CONTROL instruction page indicates that they intended this
3472 * as a debug feature and don't think it is useful in production,
3473 * but it may actually be usable, should we ever want to.
3475 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
3477 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
3478 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
3479 /* Project: All / Arguments:
3481 * - Generic Media State Clear [16]
3482 * - Indirect State Pointers Disable [16]
3484 * "Requires stall bit ([20] of DW1) set."
3486 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
3487 * State Clear) says:
3489 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
3490 * programmed prior to programming a PIPECONTROL command with "Media
3491 * State Clear" set in GPGPU mode of operation"
3493 * This is a subset of the earlier rule, so there's nothing to do.
3495 flags
|= PIPE_CONTROL_CS_STALL
;
3498 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
3499 /* Project: All / Argument: Store Data Index
3501 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
3504 * For now, we just assert that the caller does this. We might want to
3505 * automatically add a write to the workaround BO...
3507 assert(non_lri_post_sync_flags
!= 0);
3510 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
3511 /* Project: All / Argument: Sync GFDT
3513 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
3514 * than '0' or 0x2520[13] must be set."
3516 * For now, we just assert that the caller does this.
3518 assert(non_lri_post_sync_flags
!= 0);
3521 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
3522 /* Project: IVB+ / Argument: TLB inv
3524 * "Requires stall bit ([20] of DW1) set."
3526 * Also, from the PIPE_CONTROL instruction table:
3529 * Post Sync Operation or CS stall must be set to ensure a TLB
3530 * invalidation occurs. Otherwise no cycle will occur to the TLB
3531 * cache to invalidate."
3533 * This is not a subset of the earlier rule, so there's nothing to do.
3535 flags
|= PIPE_CONTROL_CS_STALL
;
3538 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
3539 /* TODO: The big Skylake GT4 post sync op workaround */
3542 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
3544 if (IS_COMPUTE_PIPELINE(batch
)) {
3545 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
3546 /* Project: SKL+ / Argument: Tex Invalidate
3547 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
3549 flags
|= PIPE_CONTROL_CS_STALL
;
3552 if (GEN_GEN
== 8 && (post_sync_flags
||
3553 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
3554 PIPE_CONTROL_DEPTH_STALL
|
3555 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
3556 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
3557 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
3558 /* Project: BDW / Arguments:
3560 * - LRI Post Sync Operation [23]
3561 * - Post Sync Op [15:14]
3563 * - Depth Stall [13]
3564 * - Render Target Cache Flush [12]
3565 * - Depth Cache Flush [0]
3566 * - DC Flush Enable [5]
3568 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
3571 flags
|= PIPE_CONTROL_CS_STALL
;
3573 /* Also, from the PIPE_CONTROL instruction table, bit 20:
3576 * This bit must be always set when PIPE_CONTROL command is
3577 * programmed by GPGPU and MEDIA workloads, except for the cases
3578 * when only Read Only Cache Invalidation bits are set (State
3579 * Cache Invalidation Enable, Instruction cache Invalidation
3580 * Enable, Texture Cache Invalidation Enable, Constant Cache
3581 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
3582 * need not implemented when FF_DOP_CG is disable via "Fixed
3583 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
3585 * It sounds like we could avoid CS stalls in some cases, but we
3586 * don't currently bother. This list isn't exactly the list above,
3592 /* "Stall" workarounds ----------------------------------------------
3593 * These have to come after the earlier ones because we may have added
3594 * some additional CS stalls above.
3597 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
3598 /* Project: PRE-SKL, VLV, CHV
3600 * "[All Stepping][All SKUs]:
3602 * One of the following must also be set:
3604 * - Render Target Cache Flush Enable ([12] of DW1)
3605 * - Depth Cache Flush Enable ([0] of DW1)
3606 * - Stall at Pixel Scoreboard ([1] of DW1)
3607 * - Depth Stall ([13] of DW1)
3608 * - Post-Sync Operation ([13] of DW1)
3609 * - DC Flush Enable ([5] of DW1)"
3611 * If we don't already have one of those bits set, we choose to add
3612 * "Stall at Pixel Scoreboard". Some of the other bits require a
3613 * CS stall as a workaround (see above), which would send us into
3614 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
3615 * appears to be safe, so we choose that.
3617 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
3618 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
3619 PIPE_CONTROL_WRITE_IMMEDIATE
|
3620 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
3621 PIPE_CONTROL_WRITE_TIMESTAMP
|
3622 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
3623 PIPE_CONTROL_DEPTH_STALL
|
3624 PIPE_CONTROL_DATA_CACHE_FLUSH
;
3625 if (!(flags
& wa_bits
))
3626 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
3629 /* Emit --------------------------------------------------------------- */
3631 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
3632 pc
.LRIPostSyncOperation
= NoLRIOperation
;
3633 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
3634 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
3635 pc
.StoreDataIndex
= 0;
3636 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
3637 pc
.GlobalSnapshotCountReset
=
3638 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
3639 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
3640 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
3641 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
3642 pc
.RenderTargetCacheFlushEnable
=
3643 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
3644 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
3645 pc
.StateCacheInvalidationEnable
=
3646 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
3647 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
3648 pc
.ConstantCacheInvalidationEnable
=
3649 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
3650 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
3651 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
3652 pc
.InstructionCacheInvalidateEnable
=
3653 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
3654 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
3655 pc
.IndirectStatePointersDisable
=
3656 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
3657 pc
.TextureCacheInvalidationEnable
=
3658 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
3659 pc
.Address
= ro_bo(bo
, offset
);
3660 pc
.ImmediateData
= imm
;
3665 genX(init_state
)(struct iris_context
*ice
)
3667 struct pipe_context
*ctx
= &ice
->ctx
;
3668 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
3670 ctx
->create_blend_state
= iris_create_blend_state
;
3671 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
3672 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
3673 ctx
->create_sampler_state
= iris_create_sampler_state
;
3674 ctx
->create_sampler_view
= iris_create_sampler_view
;
3675 ctx
->create_surface
= iris_create_surface
;
3676 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
3677 ctx
->create_compute_state
= iris_create_compute_state
;
3678 ctx
->bind_blend_state
= iris_bind_blend_state
;
3679 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
3680 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
3681 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
3682 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
3683 ctx
->bind_compute_state
= iris_bind_compute_state
;
3684 ctx
->delete_blend_state
= iris_delete_state
;
3685 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
3686 ctx
->delete_fs_state
= iris_delete_state
;
3687 ctx
->delete_rasterizer_state
= iris_delete_state
;
3688 ctx
->delete_sampler_state
= iris_delete_state
;
3689 ctx
->delete_vertex_elements_state
= iris_delete_state
;
3690 ctx
->delete_compute_state
= iris_delete_state
;
3691 ctx
->delete_tcs_state
= iris_delete_state
;
3692 ctx
->delete_tes_state
= iris_delete_state
;
3693 ctx
->delete_gs_state
= iris_delete_state
;
3694 ctx
->delete_vs_state
= iris_delete_state
;
3695 ctx
->set_blend_color
= iris_set_blend_color
;
3696 ctx
->set_clip_state
= iris_set_clip_state
;
3697 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
3698 ctx
->set_sampler_views
= iris_set_sampler_views
;
3699 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
3700 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
3701 ctx
->set_sample_mask
= iris_set_sample_mask
;
3702 ctx
->set_scissor_states
= iris_set_scissor_states
;
3703 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
3704 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
3705 ctx
->set_viewport_states
= iris_set_viewport_states
;
3706 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
3707 ctx
->surface_destroy
= iris_surface_destroy
;
3708 ctx
->draw_vbo
= iris_draw_vbo
;
3709 ctx
->launch_grid
= iris_launch_grid
;
3710 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
3711 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
3712 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
3714 ice
->vtbl
.destroy_state
= iris_destroy_state
;
3715 ice
->vtbl
.init_render_context
= iris_init_render_context
;
3716 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
3717 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
3718 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
3719 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
3720 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
3721 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
3722 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
3723 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
3724 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
3725 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
3727 ice
->state
.dirty
= ~0ull;
3729 ice
->state
.num_viewports
= 1;
3730 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
3732 /* Make a 1x1x1 null surface for unbound textures */
3733 void *null_surf_map
=
3734 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
3735 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
3736 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));