2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "intel/common/gen_sample_positions.h"
43 #include "iris_batch.h"
44 #include "iris_context.h"
45 #include "iris_resource.h"
47 #define __gen_address_type unsigned
48 #define __gen_user_data void
51 __gen_combine_address(void *user_data
, void *location
,
52 unsigned address
, uint32_t delta
)
57 #define __genxml_cmd_length(cmd) cmd ## _length
58 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
59 #define __genxml_cmd_header(cmd) cmd ## _header
60 #define __genxml_cmd_pack(cmd) cmd ## _pack
62 #define iris_pack_command(cmd, dst, name) \
63 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
64 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
65 ({ __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name); \
66 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __genxml_cmd_length(cmd) * 4)); \
70 #define iris_pack_state(cmd, dst, name) \
71 for (struct cmd name = {}, \
72 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
73 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
76 #define iris_emit_cmd(batch, cmd, name) \
77 iris_require_command_space(batch, 4 * __genxml_cmd_length(cmd)); \
78 iris_pack_command(cmd, batch->cmdbuf.map_next, name)
80 #define iris_emit_merge(batch, dwords0, dwords1) \
82 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
84 iris_require_command_space(batch, ARRAY_SIZE(dwords0)); \
85 uint32_t *dw = batch->cmdbuf.map_next; \
86 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
87 dw[i] = (dwords0)[i] | (dwords1)[i]; \
88 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4)); \
91 #include "genxml/genX_pack.h"
92 #include "genxml/gen_macros.h"
94 #define MOCS_WB (2 << 1)
96 UNUSED
static void pipe_asserts()
98 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
100 /* pipe_logicop happens to match the hardware. */
101 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
102 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
103 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
104 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
105 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
106 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
107 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
108 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
109 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
110 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
111 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
112 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
113 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
114 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
115 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
116 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
118 /* pipe_blend_func happens to match the hardware. */
119 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
120 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
121 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
122 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
123 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
124 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
125 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
126 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
127 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
128 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
129 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
130 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
131 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
132 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
133 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
134 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
135 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
136 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
137 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
139 /* pipe_blend_func happens to match the hardware. */
140 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
141 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
142 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
143 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
144 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
146 /* pipe_stencil_op happens to match the hardware. */
147 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
148 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
149 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
150 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
151 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
152 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
153 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
154 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
159 translate_compare_func(enum pipe_compare_func pipe_func
)
161 static const unsigned map
[] = {
162 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
163 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
164 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
165 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
166 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
167 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
168 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
169 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
171 return map
[pipe_func
];
175 translate_shadow_func(enum pipe_compare_func pipe_func
)
177 /* Gallium specifies the result of shadow comparisons as:
179 * 1 if ref <op> texel,
184 * 0 if texel <op> ref,
187 * So we need to flip the operator and also negate.
189 static const unsigned map
[] = {
190 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
191 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
192 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
193 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
194 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
195 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
196 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
197 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
199 return map
[pipe_func
];
203 translate_cull_mode(unsigned pipe_face
)
205 static const unsigned map
[4] = {
206 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
207 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
208 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
209 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
211 return map
[pipe_face
];
215 translate_fill_mode(unsigned pipe_polymode
)
217 static const unsigned map
[4] = {
218 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
219 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
220 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
221 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
223 return map
[pipe_polymode
];
227 iris_upload_initial_gpu_state(struct iris_context
*ice
,
228 struct iris_batch
*batch
)
230 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
231 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
232 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
234 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
235 GEN_SAMPLE_POS_1X(pat
._1xSample
);
236 GEN_SAMPLE_POS_2X(pat
._2xSample
);
237 GEN_SAMPLE_POS_4X(pat
._4xSample
);
238 GEN_SAMPLE_POS_8X(pat
._8xSample
);
239 GEN_SAMPLE_POS_16X(pat
._16xSample
);
241 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
242 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
243 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
244 /* XXX: may need to set an offset for origin-UL framebuffers */
245 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
249 iris_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
254 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
259 iris_set_blend_color(struct pipe_context
*ctx
,
260 const struct pipe_blend_color
*state
)
262 struct iris_context
*ice
= (struct iris_context
*) ctx
;
264 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
265 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
268 struct iris_blend_state
{
269 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
270 uint32_t blend_state
[GENX(BLEND_STATE_length
)];
271 uint32_t blend_entries
[BRW_MAX_DRAW_BUFFERS
*
272 GENX(BLEND_STATE_ENTRY_length
)];
276 iris_create_blend_state(struct pipe_context
*ctx
,
277 const struct pipe_blend_state
*state
)
279 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
281 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
282 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
283 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
284 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
285 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
286 bs
.ColorDitherEnable
= state
->dither
;
287 //bs.AlphaTestEnable = <comes from alpha state> :(
288 //bs.AlphaTestFunction = <comes from alpha state> :(
291 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
292 //pb.HasWriteableRT = <comes from somewhere> :(
293 //pb.AlphaTestEnable = <comes from alpha state> :(
294 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
295 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
297 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
299 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
300 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
301 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
302 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
305 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
306 iris_pack_state(GENX(BLEND_STATE_ENTRY
), &cso
->blend_entries
[i
], be
) {
307 be
.LogicOpEnable
= state
->logicop_enable
;
308 be
.LogicOpFunction
= state
->logicop_func
;
310 be
.PreBlendSourceOnlyClampEnable
= false;
311 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
312 be
.PreBlendColorClampEnable
= true;
313 be
.PostBlendColorClampEnable
= true;
315 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
317 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
318 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
319 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
320 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
321 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
322 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
324 be
.WriteDisableRed
= state
->rt
[i
].colormask
& PIPE_MASK_R
;
325 be
.WriteDisableGreen
= state
->rt
[i
].colormask
& PIPE_MASK_G
;
326 be
.WriteDisableBlue
= state
->rt
[i
].colormask
& PIPE_MASK_B
;
327 be
.WriteDisableAlpha
= state
->rt
[i
].colormask
& PIPE_MASK_A
;
335 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
337 struct iris_context
*ice
= (struct iris_context
*) ctx
;
338 ice
->state
.cso_blend
= state
;
339 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
340 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
343 struct iris_depth_stencil_alpha_state
{
344 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
345 uint32_t cc_vp
[GENX(CC_VIEWPORT_length
)];
347 struct pipe_alpha_state alpha
; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
351 iris_create_zsa_state(struct pipe_context
*ctx
,
352 const struct pipe_depth_stencil_alpha_state
*state
)
354 struct iris_depth_stencil_alpha_state
*cso
=
355 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
357 cso
->alpha
= state
->alpha
;
359 bool two_sided_stencil
= state
->stencil
[1].enabled
;
361 /* The state tracker needs to optimize away EQUAL writes for us. */
362 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
364 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
365 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
366 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
367 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
368 wmds
.StencilTestFunction
=
369 translate_compare_func(state
->stencil
[0].func
);
370 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
371 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
372 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
373 wmds
.BackfaceStencilTestFunction
=
374 translate_compare_func(state
->stencil
[1].func
);
375 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
376 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
377 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
378 wmds
.StencilBufferWriteEnable
=
379 state
->stencil
[0].writemask
!= 0 ||
380 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
381 wmds
.DepthTestEnable
= state
->depth
.enabled
;
382 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
383 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
384 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
385 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
386 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
387 /* wmds.[Backface]StencilReferenceValue are merged later */
390 iris_pack_state(GENX(CC_VIEWPORT
), cso
->cc_vp
, ccvp
) {
391 ccvp
.MinimumDepth
= state
->depth
.bounds_min
;
392 ccvp
.MaximumDepth
= state
->depth
.bounds_max
;
399 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
401 struct iris_context
*ice
= (struct iris_context
*) ctx
;
402 ice
->state
.cso_zsa
= state
;
403 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
404 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
407 struct iris_rasterizer_state
{
408 uint32_t sf
[GENX(3DSTATE_SF_length
)];
409 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
410 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
411 uint32_t wm
[GENX(3DSTATE_WM_length
)];
413 bool flatshade
; /* for shader state */
414 bool light_twoside
; /* for shader state */
415 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
416 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
417 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
419 uint8_t line_stipple_factor
;
420 uint16_t line_stipple_pattern
;
424 iris_create_rasterizer_state(struct pipe_context
*ctx
,
425 const struct pipe_rasterizer_state
*state
)
427 struct iris_rasterizer_state
*cso
=
428 malloc(sizeof(struct iris_rasterizer_state
));
431 sprite_coord_mode
-> SBE PointSpriteTextureCoordinateOrigin
432 sprite_coord_enable
-> SBE PointSpriteTextureCoordinateEnable
433 point_quad_rasterization
-> SBE
?
438 force_persample_interp
- ?
441 offset_units_unscaled
- cap
not exposed
444 unsigned line_stipple_factor
:8; /**< [1..256] actually */
445 unsigned line_stipple_pattern
:16;
448 cso
->flatshade
= state
->flatshade
;
449 cso
->light_twoside
= state
->light_twoside
;
450 cso
->rasterizer_discard
= state
->rasterizer_discard
;
451 cso
->line_stipple_factor
= state
->line_stipple_factor
;
452 cso
->line_stipple_pattern
= state
->line_stipple_pattern
;
453 // for 3DSTATE_MULTISAMPLE, if we want it.
454 cso
->half_pixel_center
= state
->half_pixel_center
;
456 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
457 sf
.StatisticsEnable
= true;
458 sf
.ViewportTransformEnable
= true;
459 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
460 sf
.LineEndCapAntialiasingRegionWidth
=
461 state
->line_smooth
? _10pixels
: _05pixels
;
462 sf
.LastPixelEnable
= state
->line_last_pixel
;
463 sf
.LineWidth
= state
->line_width
;
464 sf
.SmoothPointEnable
= state
->point_smooth
;
465 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
466 sf
.PointWidth
= state
->point_size
;
468 if (state
->flatshade_first
) {
469 sf
.TriangleStripListProvokingVertexSelect
= 2;
470 sf
.TriangleFanProvokingVertexSelect
= 2;
471 sf
.LineStripListProvokingVertexSelect
= 1;
473 sf
.TriangleFanProvokingVertexSelect
= 1;
478 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
479 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
480 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
481 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
482 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
483 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
484 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
485 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
486 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
487 rr
.GlobalDepthOffsetConstant
= state
->offset_units
;
488 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
489 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
490 rr
.SmoothPointEnable
= state
->point_smooth
;
491 rr
.AntialiasingEnable
= state
->line_smooth
;
492 rr
.ScissorRectangleEnable
= state
->scissor
;
493 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
494 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
495 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
498 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
499 cl
.StatisticsEnable
= true;
500 cl
.EarlyCullEnable
= true;
501 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
502 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
503 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
504 cl
.GuardbandClipTestEnable
= true;
505 cl
.ClipMode
= CLIPMODE_NORMAL
;
506 cl
.ClipEnable
= true;
507 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
508 cl
.MinimumPointWidth
= 0.125;
509 cl
.MaximumPointWidth
= 255.875;
510 //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
511 //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
513 if (state
->flatshade_first
) {
514 cl
.TriangleStripListProvokingVertexSelect
= 2;
515 cl
.TriangleFanProvokingVertexSelect
= 2;
516 cl
.LineStripListProvokingVertexSelect
= 1;
518 cl
.TriangleFanProvokingVertexSelect
= 1;
522 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
523 wm
.LineAntialiasingRegionWidth
= _10pixels
;
524 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
525 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
526 wm
.StatisticsEnable
= true;
527 wm
.LineStippleEnable
= state
->line_stipple_enable
;
528 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
529 // wm.BarycentricInterpolationMode = <comes from FS program> :(
530 // wm.EarlyDepthStencilControl = <comes from FS program> :(
537 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
539 struct iris_context
*ice
= (struct iris_context
*) ctx
;
540 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
541 struct iris_rasterizer_state
*new_cso
= state
;
543 /* Avoid re-emitting 3DSTATE_LINE_STIPPLE if we can, it's non-pipelined */
544 if (old_cso
->line_stipple_factor
!= new_cso
->line_stipple_factor
||
545 old_cso
->line_stipple_pattern
!= new_cso
->line_stipple_pattern
) {
546 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
549 if (old_cso
->half_pixel_center
!= new_cso
->half_pixel_center
) {
550 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
553 ice
->state
.cso_rast
= new_cso
;
554 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
558 translate_wrap(unsigned pipe_wrap
)
560 static const unsigned map
[] = {
561 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
562 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
563 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
564 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
565 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
566 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
567 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1, // XXX: ???
568 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1, // XXX: ???
570 return map
[pipe_wrap
];
574 * Return true if the given wrap mode requires the border color to exist.
577 wrap_mode_needs_border_color(unsigned wrap_mode
)
579 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
583 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
585 static const unsigned map
[] = {
586 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
587 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
588 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
590 return map
[pipe_mip
];
593 struct iris_sampler_state
{
594 struct pipe_sampler_state base
;
596 bool needs_border_color
;
598 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
602 iris_create_sampler_state(struct pipe_context
*pctx
,
603 const struct pipe_sampler_state
*state
)
605 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
610 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
611 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
613 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
614 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
615 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
617 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
618 wrap_mode_needs_border_color(wrap_t
) ||
619 wrap_mode_needs_border_color(wrap_r
);
621 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
622 samp
.TCXAddressControlMode
= wrap_s
;
623 samp
.TCYAddressControlMode
= wrap_t
;
624 samp
.TCZAddressControlMode
= wrap_r
;
625 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
626 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
627 samp
.MinModeFilter
= state
->min_img_filter
;
628 samp
.MagModeFilter
= state
->mag_img_filter
;
629 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
630 samp
.MaximumAnisotropy
= RATIO21
;
632 if (state
->max_anisotropy
>= 2) {
633 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
634 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
635 samp
.AnisotropicAlgorithm
= EWAApproximation
;
638 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
639 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
641 samp
.MaximumAnisotropy
=
642 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
645 /* Set address rounding bits if not using nearest filtering. */
646 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
647 samp
.UAddressMinFilterRoundingEnable
= true;
648 samp
.VAddressMinFilterRoundingEnable
= true;
649 samp
.RAddressMinFilterRoundingEnable
= true;
652 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
653 samp
.UAddressMagFilterRoundingEnable
= true;
654 samp
.VAddressMagFilterRoundingEnable
= true;
655 samp
.RAddressMagFilterRoundingEnable
= true;
658 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
659 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
661 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
663 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
664 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
665 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
666 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
668 //samp.BorderColorPointer = <<comes from elsewhere>>
674 struct iris_sampler_view
{
675 struct pipe_sampler_view pipe
;
676 struct isl_view view
;
677 uint32_t surface_state
[GENX(RENDER_SURFACE_STATE_length
)];
681 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
682 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
684 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
687 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
689 * which is simply adding 4 then modding by 8 (or anding with 7).
691 * We then may need to apply workarounds for textureGather hardware bugs.
693 static enum isl_channel_select
694 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
696 return (swizzle
+ 4) & 7;
699 static struct pipe_sampler_view
*
700 iris_create_sampler_view(struct pipe_context
*ctx
,
701 struct pipe_resource
*tex
,
702 const struct pipe_sampler_view
*tmpl
)
704 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
705 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
706 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
711 /* initialize base object */
713 isv
->pipe
.context
= ctx
;
714 isv
->pipe
.texture
= NULL
;
715 pipe_reference_init(&isv
->pipe
.reference
, 1);
716 pipe_resource_reference(&isv
->pipe
.texture
, tex
);
718 /* XXX: do we need brw_get_texture_swizzle hacks here? */
720 isv
->view
= (struct isl_view
) {
721 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
722 .base_level
= tmpl
->u
.tex
.first_level
,
723 .levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1,
724 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
725 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
726 .swizzle
= (struct isl_swizzle
) {
727 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
728 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
729 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
730 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
732 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
735 isl_surf_fill_state(&screen
->isl_dev
, isv
->surface_state
,
736 .surf
= &itex
->surf
, .view
= &isv
->view
,
740 // .clear_color = clear_color,
745 struct iris_surface
{
746 struct pipe_surface pipe
;
747 struct isl_view view
;
748 uint32_t surface_state
[GENX(RENDER_SURFACE_STATE_length
)];
751 static struct pipe_surface
*
752 iris_create_surface(struct pipe_context
*ctx
,
753 struct pipe_resource
*tex
,
754 const struct pipe_surface
*tmpl
)
756 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
757 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
758 struct pipe_surface
*psurf
= &surf
->pipe
;
759 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
764 pipe_reference_init(&psurf
->reference
, 1);
765 pipe_resource_reference(&psurf
->texture
, tex
);
766 psurf
->context
= ctx
;
767 psurf
->format
= tmpl
->format
;
768 psurf
->width
= tex
->width0
;
769 psurf
->height
= tex
->height0
;
770 psurf
->texture
= tex
;
771 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
772 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
773 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
775 surf
->view
= (struct isl_view
) {
776 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
777 .base_level
= tmpl
->u
.tex
.level
,
779 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
780 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
781 .swizzle
= ISL_SWIZZLE_IDENTITY
,
782 // XXX: DEPTH_BIt, STENCIL_BIT...CUBE_BIT? Other bits?!
783 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
786 isl_surf_fill_state(&screen
->isl_dev
, surf
->surface_state
,
787 .surf
= &itex
->surf
, .view
= &surf
->view
,
791 // .clear_color = clear_color,
797 iris_set_sampler_views(struct pipe_context
*ctx
,
798 enum pipe_shader_type shader
,
799 unsigned start
, unsigned count
,
800 struct pipe_sampler_view
**views
)
805 iris_bind_sampler_states(struct pipe_context
*ctx
,
806 enum pipe_shader_type shader
,
807 unsigned start
, unsigned count
,
813 iris_set_clip_state(struct pipe_context
*ctx
,
814 const struct pipe_clip_state
*state
)
819 iris_set_polygon_stipple(struct pipe_context
*ctx
,
820 const struct pipe_poly_stipple
*state
)
822 struct iris_context
*ice
= (struct iris_context
*) ctx
;
823 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
824 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
828 iris_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
833 iris_set_scissor_states(struct pipe_context
*ctx
,
835 unsigned num_scissors
,
836 const struct pipe_scissor_state
*state
)
838 struct iris_context
*ice
= (struct iris_context
*) ctx
;
841 ice
->state
.num_scissors
= num_scissors
;
843 for (unsigned i
= start_slot
; i
< start_slot
+ num_scissors
; i
++) {
844 ice
->state
.scissors
[i
] = *state
;
847 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
851 iris_set_stencil_ref(struct pipe_context
*ctx
,
852 const struct pipe_stencil_ref
*state
)
854 struct iris_context
*ice
= (struct iris_context
*) ctx
;
855 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
856 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
860 struct iris_viewport_state
{
861 uint32_t sf_cl_vp
[GENX(3DSTATE_SF_length
)];
865 extent_from_matrix(const struct pipe_viewport_state
*state
, int axis
)
867 return fabsf(state
->scale
[axis
]) * state
->translate
[axis
];
872 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
873 float m00
, float m11
, float m30
, float m31
,
874 float *xmin
, float *xmax
,
875 float *ymin
, float *ymax
)
877 /* According to the "Vertex X,Y Clamping and Quantization" section of the
878 * Strips and Fans documentation:
880 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
881 * fixed-point "guardband" range supported by the rasterization hardware"
885 * "In almost all circumstances, if an object’s vertices are actually
886 * modified by this clamping (i.e., had X or Y coordinates outside of
887 * the guardband extent the rendered object will not match the intended
888 * result. Therefore software should take steps to ensure that this does
889 * not happen - e.g., by clipping objects such that they do not exceed
890 * these limits after the Drawing Rectangle is applied."
892 * I believe the fundamental restriction is that the rasterizer (in
893 * the SF/WM stages) have a limit on the number of pixels that can be
894 * rasterized. We need to ensure any coordinates beyond the rasterizer
895 * limit are handled by the clipper. So effectively that limit becomes
896 * the clipper's guardband size.
900 * "In addition, in order to be correctly rendered, objects must have a
901 * screenspace bounding box not exceeding 8K in the X or Y direction.
902 * This additional restriction must also be comprehended by software,
903 * i.e., enforced by use of clipping."
905 * This makes no sense. Gen7+ hardware supports 16K render targets,
906 * and you definitely need to be able to draw polygons that fill the
907 * surface. Our assumption is that the rasterizer was limited to 8K
908 * on Sandybridge, which only supports 8K surfaces, and it was actually
909 * increased to 16K on Ivybridge and later.
911 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
913 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
915 if (m00
!= 0 && m11
!= 0) {
916 /* First, we compute the screen-space render area */
917 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
918 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
919 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
920 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
922 /* We want the guardband to be centered on that */
923 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
924 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
925 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
926 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
928 /* Now we need it in native device coordinates */
929 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
930 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
931 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
932 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
934 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
935 * flipped upside-down. X should be fine though.
937 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
940 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
941 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
943 /* The viewport scales to 0, so nothing will be rendered. */
953 iris_set_viewport_states(struct pipe_context
*ctx
,
955 unsigned num_viewports
,
956 const struct pipe_viewport_state
*state
)
958 struct iris_context
*ice
= (struct iris_context
*) ctx
;
959 struct iris_viewport_state
*cso
=
960 malloc(sizeof(struct iris_viewport_state
));
962 for (unsigned i
= start_slot
; i
< start_slot
+ num_viewports
; i
++) {
963 float x_extent
= extent_from_matrix(&state
[i
], 0);
964 float y_extent
= extent_from_matrix(&state
[i
], 1);
966 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), cso
->sf_cl_vp
, vp
) {
967 vp
.ViewportMatrixElementm00
= state
[i
].scale
[0];
968 vp
.ViewportMatrixElementm11
= state
[i
].scale
[1];
969 vp
.ViewportMatrixElementm22
= state
[i
].scale
[2];
970 vp
.ViewportMatrixElementm30
= state
[i
].translate
[0];
971 vp
.ViewportMatrixElementm31
= state
[i
].translate
[1];
972 vp
.ViewportMatrixElementm32
= state
[i
].translate
[2];
973 /* XXX: in i965 this is computed based on the drawbuffer size,
974 * but we don't have that here...
976 vp
.XMinClipGuardband
= -1.0;
977 vp
.XMaxClipGuardband
= 1.0;
978 vp
.YMinClipGuardband
= -1.0;
979 vp
.YMaxClipGuardband
= 1.0;
980 vp
.XMinViewPort
= -x_extent
;
981 vp
.XMaxViewPort
= x_extent
;
982 vp
.YMinViewPort
= -y_extent
;
983 vp
.YMaxViewPort
= y_extent
;
987 ice
->state
.cso_vp
= cso
;
989 ice
->state
.num_viewports
= num_viewports
;
990 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
994 iris_set_framebuffer_state(struct pipe_context
*ctx
,
995 const struct pipe_framebuffer_state
*state
)
997 struct iris_context
*ice
= (struct iris_context
*) ctx
;
998 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1000 if (cso
->samples
!= state
->samples
) {
1001 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1004 cso
->width
= state
->width
;
1005 cso
->height
= state
->height
;
1006 cso
->layers
= state
->layers
;
1007 cso
->samples
= state
->samples
;
1010 for (i
= 0; i
< state
->nr_cbufs
; i
++)
1011 pipe_surface_reference(&cso
->cbufs
[i
], state
->cbufs
[i
]);
1012 for (; i
< cso
->nr_cbufs
; i
++)
1013 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
1015 cso
->nr_cbufs
= state
->nr_cbufs
;
1017 pipe_surface_reference(&cso
->zsbuf
, state
->zsbuf
);
1022 iris_set_constant_buffer(struct pipe_context
*ctx
,
1023 enum pipe_shader_type shader
, uint index
,
1024 const struct pipe_constant_buffer
*cb
)
1030 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1031 struct pipe_sampler_view
*state
)
1033 pipe_resource_reference(&state
->texture
, NULL
);
1039 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*surface
)
1041 pipe_resource_reference(&surface
->texture
, NULL
);
1046 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1051 struct iris_vertex_buffer_state
{
1052 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
1053 unsigned length
; /* length of 3DSTATE_VERTEX_BUFFERS in DWords */
1057 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1058 unsigned start_slot
, unsigned count
,
1059 const struct pipe_vertex_buffer
*buffers
)
1061 struct iris_vertex_buffer_state
*cso
=
1062 malloc(sizeof(struct iris_vertex_buffer_state
));
1064 cso
->length
= 4 * count
- 1;
1066 iris_pack_state(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1067 vb
.DWordLength
= cso
->length
;
1070 /* If there are no buffers, do nothing. We can leave the stale
1071 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1072 * elements that point to them, it should be fine.
1077 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1079 for (unsigned i
= 0; i
< count
; i
++) {
1080 assert(!buffers
[i
].is_user_buffer
);
1082 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1083 vb
.VertexBufferIndex
= start_slot
+ i
;
1085 vb
.AddressModifyEnable
= true;
1086 vb
.BufferPitch
= buffers
[i
].stride
;
1087 //vb.BufferStartingAddress = ro_bo(bo, buffers[i].buffer_offset);
1088 //vb.BufferSize = bo->size;
1091 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1094 /* XXX: actually do something with this! */
1097 struct iris_vertex_element_state
{
1098 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1099 uint32_t vf_instancing
[GENX(3DSTATE_VF_INSTANCING_length
)][33];
1104 iris_create_vertex_elements(struct pipe_context
*ctx
,
1106 const struct pipe_vertex_element
*state
)
1108 struct iris_vertex_element_state
*cso
=
1109 malloc(sizeof(struct iris_vertex_element_state
));
1114 * - create edge flag one
1116 * - if those are necessary, use count + 1/2/3... OR in the length
1118 iris_pack_state(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
);
1120 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1122 for (int i
= 0; i
< count
; i
++) {
1123 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1124 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1126 ve
.SourceElementOffset
= state
[i
].src_offset
;
1127 ve
.SourceElementFormat
=
1128 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1131 iris_pack_state(GENX(3DSTATE_VF_INSTANCING
), cso
->vf_instancing
[i
], vi
) {
1132 vi
.VertexElementIndex
= i
;
1133 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1134 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1137 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1144 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
1146 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1148 ice
->state
.cso_vertex_elements
= state
;
1149 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
1153 iris_create_compute_state(struct pipe_context
*ctx
,
1154 const struct pipe_compute_state
*state
)
1159 static struct pipe_stream_output_target
*
1160 iris_create_stream_output_target(struct pipe_context
*ctx
,
1161 struct pipe_resource
*res
,
1162 unsigned buffer_offset
,
1163 unsigned buffer_size
)
1165 struct pipe_stream_output_target
*t
=
1166 CALLOC_STRUCT(pipe_stream_output_target
);
1170 pipe_reference_init(&t
->reference
, 1);
1171 pipe_resource_reference(&t
->buffer
, res
);
1172 t
->buffer_offset
= buffer_offset
;
1173 t
->buffer_size
= buffer_size
;
1178 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
1179 struct pipe_stream_output_target
*t
)
1181 pipe_resource_reference(&t
->buffer
, NULL
);
1186 iris_set_stream_output_targets(struct pipe_context
*ctx
,
1187 unsigned num_targets
,
1188 struct pipe_stream_output_target
**targets
,
1189 const unsigned *offsets
)
1194 iris_upload_render_state(struct iris_context
*ice
, struct iris_batch
*batch
)
1196 const uint64_t dirty
= ice
->state
.dirty
;
1198 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
1199 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1200 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
1202 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1203 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
1204 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
1205 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
1207 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
);
1210 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
1211 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1212 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
1213 ptr
.CCViewportPointer
=
1214 iris_emit_state(batch
, cso
->cc_vp
, sizeof(cso
->cc_vp
), 32);
1218 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
1219 struct iris_blend_state
*cso
= ice
->state
.cso_blend
;
1220 iris_batch_emit(batch
, cso
->ps_blend
, sizeof(cso
->ps_blend
));
1223 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
1224 //struct iris_blend_state *cso = ice->state.cso_blend;
1225 // XXX: 3DSTATE_BLEND_STATE_POINTERS - BLEND_STATE
1226 // -> from iris_blend_state (most) + iris_depth_stencil_alpha_state
1227 // (alpha test function/enable) + has writeable RT from ???????
1230 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
1231 struct iris_viewport_state
*cso
= ice
->state
.cso_vp
;
1232 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
1233 ptr
.SFClipViewportPointer
=
1234 iris_emit_state(batch
, cso
->sf_cl_vp
, sizeof(cso
->sf_cl_vp
), 64);
1238 if (dirty
& IRIS_DIRTY_CLIP
) {
1239 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
1241 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
1242 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
1243 //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
1244 //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
1245 // also userclip stuffs...
1247 iris_emit_merge(batch
, cso
->clip
, dynamic_clip
);
1250 if (dirty
& IRIS_DIRTY_RASTER
) {
1251 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
1252 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
1253 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
1256 if (dirty
& IRIS_DIRTY_SCISSOR
) {
1257 uint32_t scissor_offset
=
1258 iris_emit_state(batch
, ice
->state
.scissors
,
1259 sizeof(struct pipe_scissor_state
) *
1260 ice
->state
.num_scissors
, 32);
1262 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
1263 ptr
.ScissorRectPointer
= scissor_offset
;
1267 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
1268 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
1269 for (int i
= 0; i
< 32; i
++) {
1270 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
1275 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
1276 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
1277 iris_emit_cmd(batch
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
1278 line
.LineStipplePattern
= cso
->line_stipple_pattern
;
1279 line
.LineStippleInverseRepeatCount
= 1.0f
/ cso
->line_stipple_factor
;
1280 line
.LineStippleRepeatCount
= cso
->line_stipple_factor
;
1284 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
1285 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
1286 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
1287 (1 + cso
->count
* GENX(VERTEX_ELEMENT_STATE_length
)));
1288 for (int i
= 0; i
< cso
->count
; i
++) {
1289 iris_batch_emit(batch
, cso
->vf_instancing
[i
],
1290 sizeof(cso
->vf_instancing
[0]));
1292 for (int i
= 0; i
< cso
->count
; i
++) {
1293 /* TODO: vertexid, instanceid support */
1294 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
);
1298 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
1299 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1301 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
1302 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
1309 3DSTATE_PUSH_CONSTANT_ALLOC_
*
1313 3DSTATE_CC_STATE_POINTERS
- COLOR_CALC_STATE
1314 -> from ice
->state
.blend_color
+ iris_depth_stencil_alpha_state
1317 3DSTATE_CONSTANT_
* - push constants
1325 - render targets
- write
and read
1326 3DSTATE_BINDING_TABLE_POINTERS_
*
1329 3DSTATE_SAMPLER_STATE_POINTERS_
*
1344 3DSTATE_SO_DECL_LIST
1347 -> iris_raster_state
+ FS
state (barycentric
, EDSC
)
1349 -> iris_raster_state (point sprite texture coordinate origin
)
1350 -> bunch of shader state
...
1354 3DSTATE_DEPTH_BUFFER
1355 3DSTATE_HIER_DEPTH_BUFFER
1356 3DSTATE_STENCIL_BUFFER
1357 3DSTATE_CLEAR_PARAMS
1358 -> iris_framebuffer_state
?
1361 -> pipe_draw_info (prim_mode
)
1363 -> pipe_draw_info (restart_index
, primitive_restart
)
1365 3DSTATE_INDEX_BUFFER
1366 -> pipe_draw_info (index
)
1367 3DSTATE_VERTEX_BUFFERS
1368 -> pipe_vertex_buffer (set_vertex_buffer hook
)
1369 3DSTATE_VF_COMPONENT_PACKING
1378 iris_bind_state(struct pipe_context
*ctx
, void *state
)
1383 iris_destroy_state(struct iris_context
*ice
)
1385 // XXX: unreference resources/surfaces.
1386 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
1387 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
1389 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
1393 iris_init_state_functions(struct pipe_context
*ctx
)
1395 ctx
->create_blend_state
= iris_create_blend_state
;
1396 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
1397 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
1398 ctx
->create_sampler_state
= iris_create_sampler_state
;
1399 ctx
->create_sampler_view
= iris_create_sampler_view
;
1400 ctx
->create_surface
= iris_create_surface
;
1401 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
1402 ctx
->create_compute_state
= iris_create_compute_state
;
1403 ctx
->bind_blend_state
= iris_bind_blend_state
;
1404 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
1405 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
1406 ctx
->bind_fs_state
= iris_bind_state
;
1407 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
1408 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
1409 ctx
->bind_compute_state
= iris_bind_state
;
1410 ctx
->bind_tcs_state
= iris_bind_state
;
1411 ctx
->bind_tes_state
= iris_bind_state
;
1412 ctx
->bind_gs_state
= iris_bind_state
;
1413 ctx
->bind_vs_state
= iris_bind_state
;
1414 ctx
->delete_blend_state
= iris_delete_state
;
1415 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
1416 ctx
->delete_fs_state
= iris_delete_state
;
1417 ctx
->delete_rasterizer_state
= iris_delete_state
;
1418 ctx
->delete_sampler_state
= iris_delete_state
;
1419 ctx
->delete_vertex_elements_state
= iris_delete_state
;
1420 ctx
->delete_compute_state
= iris_delete_state
;
1421 ctx
->delete_tcs_state
= iris_delete_state
;
1422 ctx
->delete_tes_state
= iris_delete_state
;
1423 ctx
->delete_gs_state
= iris_delete_state
;
1424 ctx
->delete_vs_state
= iris_delete_state
;
1425 ctx
->set_blend_color
= iris_set_blend_color
;
1426 ctx
->set_clip_state
= iris_set_clip_state
;
1427 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
1428 ctx
->set_sampler_views
= iris_set_sampler_views
;
1429 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
1430 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
1431 ctx
->set_sample_mask
= iris_set_sample_mask
;
1432 ctx
->set_scissor_states
= iris_set_scissor_states
;
1433 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
1434 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
1435 ctx
->set_viewport_states
= iris_set_viewport_states
;
1436 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
1437 ctx
->surface_destroy
= iris_surface_destroy
;
1438 ctx
->draw_vbo
= iris_draw_vbo
;
1439 ctx
->launch_grid
= iris_launch_grid
;
1440 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
1441 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
1442 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;