2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
31 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
37 #include "pipe/p_defines.h"
38 #include "pipe/p_state.h"
39 #include "pipe/p_context.h"
40 #include "pipe/p_screen.h"
41 #include "util/u_inlines.h"
42 #include "util/u_format.h"
43 #include "util/u_framebuffer.h"
44 #include "util/u_transfer.h"
45 #include "util/u_upload_mgr.h"
48 #include "intel/compiler/brw_compiler.h"
49 #include "intel/common/gen_l3_config.h"
50 #include "intel/common/gen_sample_positions.h"
51 #include "iris_batch.h"
52 #include "iris_context.h"
53 #include "iris_pipe.h"
54 #include "iris_resource.h"
56 #define __gen_address_type struct iris_address
57 #define __gen_user_data struct iris_batch
59 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
62 __gen_combine_address(struct iris_batch
*batch
, void *location
,
63 struct iris_address addr
, uint32_t delta
)
65 uint64_t result
= addr
.offset
+ delta
;
68 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
69 /* Assume this is a general address, not relative to a base. */
70 result
+= addr
.bo
->gtt_offset
;
76 #define __genxml_cmd_length(cmd) cmd ## _length
77 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
78 #define __genxml_cmd_header(cmd) cmd ## _header
79 #define __genxml_cmd_pack(cmd) cmd ## _pack
81 #define _iris_pack_command(batch, cmd, dst, name) \
82 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
83 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
84 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
88 #define iris_pack_command(cmd, dst, name) \
89 _iris_pack_command(NULL, cmd, dst, name)
91 #define iris_pack_state(cmd, dst, name) \
92 for (struct cmd name = {}, \
93 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
94 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
97 #define iris_emit_cmd(batch, cmd, name) \
98 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
100 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
102 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
103 for (uint32_t i = 0; i < num_dwords; i++) \
104 dw[i] = (dwords0)[i] | (dwords1)[i]; \
105 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
108 #include "genxml/genX_pack.h"
109 #include "genxml/gen_macros.h"
110 #include "genxml/genX_bits.h"
112 #define MOCS_WB (2 << 1)
114 UNUSED
static void pipe_asserts()
116 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
118 /* pipe_logicop happens to match the hardware. */
119 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
120 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
121 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
122 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
123 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
124 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
125 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
126 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
127 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
128 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
129 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
130 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
131 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
132 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
133 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
134 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
136 /* pipe_blend_func happens to match the hardware. */
137 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
138 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
139 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
140 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
141 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
142 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
143 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
144 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
145 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
146 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
147 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
148 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
149 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
150 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
151 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
152 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
153 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
157 /* pipe_blend_func happens to match the hardware. */
158 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
159 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
160 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
161 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
162 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
164 /* pipe_stencil_op happens to match the hardware. */
165 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
166 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
167 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
168 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
169 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
170 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
171 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
172 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
174 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
175 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
176 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
181 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
183 static const unsigned map
[] = {
184 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
185 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
186 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
187 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
188 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
189 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
190 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
191 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
192 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
193 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
194 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
195 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
196 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
197 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
198 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
201 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
205 translate_compare_func(enum pipe_compare_func pipe_func
)
207 static const unsigned map
[] = {
208 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
209 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
210 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
211 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
212 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
213 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
214 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
215 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
217 return map
[pipe_func
];
221 translate_shadow_func(enum pipe_compare_func pipe_func
)
223 /* Gallium specifies the result of shadow comparisons as:
225 * 1 if ref <op> texel,
230 * 0 if texel <op> ref,
233 * So we need to flip the operator and also negate.
235 static const unsigned map
[] = {
236 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
237 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
238 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
239 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
240 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
241 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
242 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
243 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
245 return map
[pipe_func
];
249 translate_cull_mode(unsigned pipe_face
)
251 static const unsigned map
[4] = {
252 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
253 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
254 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
255 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
257 return map
[pipe_face
];
261 translate_fill_mode(unsigned pipe_polymode
)
263 static const unsigned map
[4] = {
264 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
265 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
266 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
267 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
269 return map
[pipe_polymode
];
272 static struct iris_address
273 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
276 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
280 stream_state(struct iris_batch
*batch
,
281 struct u_upload_mgr
*uploader
,
282 struct pipe_resource
**out_res
,
285 uint32_t *out_offset
)
289 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
291 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
292 iris_use_pinned_bo(batch
, bo
, false);
294 *out_offset
+= iris_bo_offset_from_base_address(bo
);
300 emit_state(struct iris_batch
*batch
,
301 struct u_upload_mgr
*uploader
,
302 struct pipe_resource
**out_res
,
309 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
312 memcpy(map
, data
, size
);
317 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
318 #define cso_changed_memcmp(x) \
319 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
322 iris_init_render_context(struct iris_screen
*screen
,
323 struct iris_batch
*batch
,
324 struct iris_vtable
*vtbl
,
325 struct pipe_debug_callback
*dbg
)
327 iris_init_batch(batch
, screen
, vtbl
, dbg
, I915_EXEC_RENDER
);
329 /* XXX: PIPE_CONTROLs */
331 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
333 // XXX: MOCS is stupid for this.
334 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
335 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
336 sba
.SurfaceStateMemoryObjectControlState
= MOCS_WB
;
337 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
338 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
339 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
340 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
343 sba
.GeneralStateBaseAddressModifyEnable
= true;
344 sba
.SurfaceStateBaseAddressModifyEnable
= true;
345 sba
.DynamicStateBaseAddressModifyEnable
= true;
346 sba
.IndirectObjectBaseAddressModifyEnable
= true;
347 sba
.InstructionBaseAddressModifyEnable
= true;
348 sba
.GeneralStateBufferSizeModifyEnable
= true;
349 sba
.DynamicStateBufferSizeModifyEnable
= true;
350 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
351 sba
.IndirectObjectBufferSizeModifyEnable
= true;
352 sba
.InstructionBuffersizeModifyEnable
= true;
354 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
355 sba
.SurfaceStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SURFACE_START
);
356 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
358 sba
.GeneralStateBufferSize
= 0xfffff;
359 sba
.IndirectObjectBufferSize
= 0xfffff;
360 sba
.InstructionBufferSize
= 0xfffff;
361 sba
.DynamicStateBufferSize
= 0xfffff;
364 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
365 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
366 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
368 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
369 GEN_SAMPLE_POS_1X(pat
._1xSample
);
370 GEN_SAMPLE_POS_2X(pat
._2xSample
);
371 GEN_SAMPLE_POS_4X(pat
._4xSample
);
372 GEN_SAMPLE_POS_8X(pat
._8xSample
);
373 GEN_SAMPLE_POS_16X(pat
._16xSample
);
375 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
376 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
377 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
378 /* XXX: may need to set an offset for origin-UL framebuffers */
379 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
381 /* Just assign a static partitioning. */
382 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
383 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
384 alloc
._3DCommandSubOpcode
= 18 + i
;
385 alloc
.ConstantBufferOffset
= 6 * i
;
386 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
392 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
397 iris_set_blend_color(struct pipe_context
*ctx
,
398 const struct pipe_blend_color
*state
)
400 struct iris_context
*ice
= (struct iris_context
*) ctx
;
402 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
403 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
406 struct iris_blend_state
{
407 /** Partial 3DSTATE_PS_BLEND */
408 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
410 /** Partial BLEND_STATE */
411 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
412 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
414 bool alpha_to_coverage
; /* for shader key */
418 iris_create_blend_state(struct pipe_context
*ctx
,
419 const struct pipe_blend_state
*state
)
421 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
422 uint32_t *blend_state
= cso
->blend_state
;
424 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
426 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
427 /* pb.HasWriteableRT is filled in at draw time. */
428 /* pb.AlphaTestEnable is filled in at draw time. */
429 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
430 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
432 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
434 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
435 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
436 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
437 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
440 iris_pack_state(GENX(BLEND_STATE
), blend_state
, bs
) {
441 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
442 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
443 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
444 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
445 bs
.ColorDitherEnable
= state
->dither
;
446 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
449 blend_state
+= GENX(BLEND_STATE_length
);
451 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
452 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_state
, be
) {
453 be
.LogicOpEnable
= state
->logicop_enable
;
454 be
.LogicOpFunction
= state
->logicop_func
;
456 be
.PreBlendSourceOnlyClampEnable
= false;
457 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
458 be
.PreBlendColorClampEnable
= true;
459 be
.PostBlendColorClampEnable
= true;
461 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
463 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
464 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
465 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
466 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
467 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
468 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
470 be
.WriteDisableRed
= !(state
->rt
[i
].colormask
& PIPE_MASK_R
);
471 be
.WriteDisableGreen
= !(state
->rt
[i
].colormask
& PIPE_MASK_G
);
472 be
.WriteDisableBlue
= !(state
->rt
[i
].colormask
& PIPE_MASK_B
);
473 be
.WriteDisableAlpha
= !(state
->rt
[i
].colormask
& PIPE_MASK_A
);
475 blend_state
+= GENX(BLEND_STATE_ENTRY_length
);
482 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
484 struct iris_context
*ice
= (struct iris_context
*) ctx
;
485 ice
->state
.cso_blend
= state
;
486 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
487 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
490 struct iris_depth_stencil_alpha_state
{
491 /** Partial 3DSTATE_WM_DEPTH_STENCIL */
492 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
494 /** Complete CC_VIEWPORT */
495 uint32_t cc_vp
[GENX(CC_VIEWPORT_length
)];
497 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE */
498 struct pipe_alpha_state alpha
;
502 iris_create_zsa_state(struct pipe_context
*ctx
,
503 const struct pipe_depth_stencil_alpha_state
*state
)
505 struct iris_depth_stencil_alpha_state
*cso
=
506 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
508 cso
->alpha
= state
->alpha
;
510 bool two_sided_stencil
= state
->stencil
[1].enabled
;
512 /* The state tracker needs to optimize away EQUAL writes for us. */
513 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
515 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
516 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
517 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
518 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
519 wmds
.StencilTestFunction
=
520 translate_compare_func(state
->stencil
[0].func
);
521 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
522 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
523 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
524 wmds
.BackfaceStencilTestFunction
=
525 translate_compare_func(state
->stencil
[1].func
);
526 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
527 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
528 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
529 wmds
.StencilBufferWriteEnable
=
530 state
->stencil
[0].writemask
!= 0 ||
531 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
532 wmds
.DepthTestEnable
= state
->depth
.enabled
;
533 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
534 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
535 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
536 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
537 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
538 /* wmds.[Backface]StencilReferenceValue are merged later */
541 iris_pack_state(GENX(CC_VIEWPORT
), cso
->cc_vp
, ccvp
) {
542 ccvp
.MinimumDepth
= state
->depth
.bounds_min
;
543 ccvp
.MaximumDepth
= state
->depth
.bounds_max
;
550 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
552 struct iris_context
*ice
= (struct iris_context
*) ctx
;
553 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
554 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
557 if (cso_changed(alpha
.ref_value
))
558 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
560 if (cso_changed(alpha
.enabled
))
561 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
564 ice
->state
.cso_zsa
= new_cso
;
565 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
566 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
569 struct iris_rasterizer_state
{
570 uint32_t sf
[GENX(3DSTATE_SF_length
)];
571 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
572 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
573 uint32_t wm
[GENX(3DSTATE_WM_length
)];
574 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
576 bool flatshade
; /* for shader state */
577 bool clamp_fragment_color
; /* for shader state */
578 bool light_twoside
; /* for shader state */
579 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
580 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
581 bool line_stipple_enable
;
582 bool poly_stipple_enable
;
583 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
584 uint16_t sprite_coord_enable
;
588 iris_create_rasterizer_state(struct pipe_context
*ctx
,
589 const struct pipe_rasterizer_state
*state
)
591 struct iris_rasterizer_state
*cso
=
592 malloc(sizeof(struct iris_rasterizer_state
));
595 point_quad_rasterization
-> SBE
?
600 force_persample_interp
- ?
603 offset_units_unscaled
- cap
not exposed
607 cso
->flatshade
= state
->flatshade
;
608 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
609 cso
->light_twoside
= state
->light_twoside
;
610 cso
->rasterizer_discard
= state
->rasterizer_discard
;
611 cso
->half_pixel_center
= state
->half_pixel_center
;
612 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
613 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
614 cso
->line_stipple_enable
= state
->line_stipple_enable
;
615 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
617 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
618 sf
.StatisticsEnable
= true;
619 sf
.ViewportTransformEnable
= true;
620 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
621 sf
.LineEndCapAntialiasingRegionWidth
=
622 state
->line_smooth
? _10pixels
: _05pixels
;
623 sf
.LastPixelEnable
= state
->line_last_pixel
;
624 sf
.LineWidth
= state
->line_width
;
625 sf
.SmoothPointEnable
= state
->point_smooth
;
626 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
627 sf
.PointWidth
= state
->point_size
;
629 if (state
->flatshade_first
) {
630 sf
.TriangleStripListProvokingVertexSelect
= 2;
631 sf
.TriangleFanProvokingVertexSelect
= 2;
632 sf
.LineStripListProvokingVertexSelect
= 1;
634 sf
.TriangleFanProvokingVertexSelect
= 1;
638 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
639 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
640 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
641 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
642 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
643 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
644 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
645 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
646 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
647 rr
.GlobalDepthOffsetConstant
= state
->offset_units
;
648 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
649 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
650 rr
.SmoothPointEnable
= state
->point_smooth
;
651 rr
.AntialiasingEnable
= state
->line_smooth
;
652 rr
.ScissorRectangleEnable
= state
->scissor
;
653 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
654 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
655 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
658 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
659 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
660 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
662 cl
.StatisticsEnable
= true;
663 cl
.EarlyCullEnable
= true;
664 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
665 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
666 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
667 cl
.GuardbandClipTestEnable
= true;
668 cl
.ClipMode
= CLIPMODE_NORMAL
;
669 cl
.ClipEnable
= true;
670 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
671 cl
.MinimumPointWidth
= 0.125;
672 cl
.MaximumPointWidth
= 255.875;
674 if (state
->flatshade_first
) {
675 cl
.TriangleStripListProvokingVertexSelect
= 2;
676 cl
.TriangleFanProvokingVertexSelect
= 2;
677 cl
.LineStripListProvokingVertexSelect
= 1;
679 cl
.TriangleFanProvokingVertexSelect
= 1;
683 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
684 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
685 * filled in at draw time from the FS program.
687 wm
.LineAntialiasingRegionWidth
= _10pixels
;
688 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
689 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
690 wm
.StatisticsEnable
= true;
691 wm
.LineStippleEnable
= state
->line_stipple_enable
;
692 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
695 /* Remap from 0..255 back to 1..256 */
696 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
698 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
699 line
.LineStipplePattern
= state
->line_stipple_pattern
;
700 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
701 line
.LineStippleRepeatCount
= line_stipple_factor
;
708 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
710 struct iris_context
*ice
= (struct iris_context
*) ctx
;
711 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
712 struct iris_rasterizer_state
*new_cso
= state
;
715 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
716 if (cso_changed_memcmp(line_stipple
))
717 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
719 if (cso_changed(half_pixel_center
))
720 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
722 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
723 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
726 ice
->state
.cso_rast
= new_cso
;
727 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
731 translate_wrap(unsigned pipe_wrap
)
733 static const unsigned map
[] = {
734 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
735 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
736 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
737 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
738 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
739 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
740 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1, // XXX: ???
741 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1, // XXX: ???
743 return map
[pipe_wrap
];
747 * Return true if the given wrap mode requires the border color to exist.
750 wrap_mode_needs_border_color(unsigned wrap_mode
)
752 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
756 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
758 static const unsigned map
[] = {
759 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
760 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
761 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
763 return map
[pipe_mip
];
766 struct iris_sampler_state
{
767 struct pipe_sampler_state base
;
769 bool needs_border_color
;
771 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
775 iris_create_sampler_state(struct pipe_context
*pctx
,
776 const struct pipe_sampler_state
*state
)
778 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
783 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
784 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
786 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
787 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
788 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
790 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
791 wrap_mode_needs_border_color(wrap_t
) ||
792 wrap_mode_needs_border_color(wrap_r
);
794 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
795 samp
.TCXAddressControlMode
= wrap_s
;
796 samp
.TCYAddressControlMode
= wrap_t
;
797 samp
.TCZAddressControlMode
= wrap_r
;
798 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
799 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
800 samp
.MinModeFilter
= state
->min_img_filter
;
801 samp
.MagModeFilter
= state
->mag_img_filter
;
802 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
803 samp
.MaximumAnisotropy
= RATIO21
;
805 if (state
->max_anisotropy
>= 2) {
806 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
807 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
808 samp
.AnisotropicAlgorithm
= EWAApproximation
;
811 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
812 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
814 samp
.MaximumAnisotropy
=
815 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
818 /* Set address rounding bits if not using nearest filtering. */
819 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
820 samp
.UAddressMinFilterRoundingEnable
= true;
821 samp
.VAddressMinFilterRoundingEnable
= true;
822 samp
.RAddressMinFilterRoundingEnable
= true;
825 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
826 samp
.UAddressMagFilterRoundingEnable
= true;
827 samp
.VAddressMagFilterRoundingEnable
= true;
828 samp
.RAddressMagFilterRoundingEnable
= true;
831 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
832 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
834 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
836 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
837 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
838 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
839 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
841 //samp.BorderColorPointer = <<comes from elsewhere>>
848 iris_bind_sampler_states(struct pipe_context
*ctx
,
849 enum pipe_shader_type p_stage
,
850 unsigned start
, unsigned count
,
853 struct iris_context
*ice
= (struct iris_context
*) ctx
;
854 gl_shader_stage stage
= stage_from_pipe(p_stage
);
856 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
858 /* Assemble the SAMPLER_STATEs into a contiguous chunk of memory
859 * relative to Dynamic State Base Address.
862 u_upload_alloc(ice
->state
.dynamic_uploader
, 0,
863 count
* 4 * GENX(SAMPLER_STATE_length
), 32,
864 &ice
->state
.sampler_table_offset
[stage
],
865 &ice
->state
.sampler_table_resource
[stage
],
870 struct pipe_resource
*res
= ice
->state
.sampler_table_resource
[stage
];
871 ice
->state
.sampler_table_offset
[stage
] +=
872 iris_bo_offset_from_base_address(iris_resource_bo(res
));
874 for (int i
= 0; i
< count
; i
++) {
875 struct iris_sampler_state
*state
= states
[i
];
877 /* Save a pointer to the iris_sampler_state, a few fields need
878 * to inform draw-time decisions.
880 ice
->state
.samplers
[stage
][start
+ i
] = state
;
883 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
885 map
+= GENX(SAMPLER_STATE_length
);
888 ice
->state
.num_samplers
[stage
] = count
;
890 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
893 struct iris_sampler_view
{
894 struct pipe_sampler_view pipe
;
895 struct isl_view view
;
897 /** The resource (BO) holding our SURFACE_STATE. */
898 struct pipe_resource
*surface_state_resource
;
899 unsigned surface_state_offset
;
903 * Convert an swizzle enumeration (i.e. PIPE_SWIZZLE_X) to one of the Gen7.5+
904 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
906 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
909 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
911 * which is simply adding 4 then modding by 8 (or anding with 7).
913 * We then may need to apply workarounds for textureGather hardware bugs.
915 static enum isl_channel_select
916 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
918 return (swizzle
+ 4) & 7;
921 static struct pipe_sampler_view
*
922 iris_create_sampler_view(struct pipe_context
*ctx
,
923 struct pipe_resource
*tex
,
924 const struct pipe_sampler_view
*tmpl
)
926 struct iris_context
*ice
= (struct iris_context
*) ctx
;
927 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
928 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
929 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
934 /* initialize base object */
936 isv
->pipe
.context
= ctx
;
937 isv
->pipe
.texture
= NULL
;
938 pipe_reference_init(&isv
->pipe
.reference
, 1);
939 pipe_resource_reference(&isv
->pipe
.texture
, tex
);
941 /* XXX: do we need brw_get_texture_swizzle hacks here? */
943 isv
->view
= (struct isl_view
) {
944 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
945 .base_level
= tmpl
->u
.tex
.first_level
,
946 .levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1,
947 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
948 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
949 .swizzle
= (struct isl_swizzle
) {
950 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
951 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
952 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
953 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
955 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
959 u_upload_alloc(ice
->state
.surface_uploader
, 0,
960 4 * GENX(RENDER_SURFACE_STATE_length
), 64,
961 &isv
->surface_state_offset
,
962 &isv
->surface_state_resource
,
967 struct iris_bo
*state_bo
= iris_resource_bo(isv
->surface_state_resource
);
968 isv
->surface_state_offset
+= iris_bo_offset_from_base_address(state_bo
);
970 isl_surf_fill_state(&screen
->isl_dev
, map
,
971 .surf
= &itex
->surf
, .view
= &isv
->view
,
973 .address
= itex
->bo
->gtt_offset
);
975 // .clear_color = clear_color,
980 struct iris_surface
{
981 struct pipe_surface pipe
;
982 struct isl_view view
;
984 /** The resource (BO) holding our SURFACE_STATE. */
985 struct pipe_resource
*surface_state_resource
;
986 unsigned surface_state_offset
;
988 // uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
991 static struct pipe_surface
*
992 iris_create_surface(struct pipe_context
*ctx
,
993 struct pipe_resource
*tex
,
994 const struct pipe_surface
*tmpl
)
996 struct iris_context
*ice
= (struct iris_context
*) ctx
;
997 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
998 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
999 struct pipe_surface
*psurf
= &surf
->pipe
;
1000 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1005 pipe_reference_init(&psurf
->reference
, 1);
1006 pipe_resource_reference(&psurf
->texture
, tex
);
1007 psurf
->context
= ctx
;
1008 psurf
->format
= tmpl
->format
;
1009 psurf
->width
= tex
->width0
;
1010 psurf
->height
= tex
->height0
;
1011 psurf
->texture
= tex
;
1012 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1013 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1014 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1018 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1019 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1020 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1022 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1024 surf
->view
= (struct isl_view
) {
1025 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
1026 .base_level
= tmpl
->u
.tex
.level
,
1028 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1029 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1030 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1034 /* Bail early for depth/stencil */
1035 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1036 ISL_SURF_USAGE_STENCIL_BIT
))
1040 u_upload_alloc(ice
->state
.surface_uploader
, 0,
1041 4 * GENX(RENDER_SURFACE_STATE_length
), 64,
1042 &surf
->surface_state_offset
,
1043 &surf
->surface_state_resource
,
1048 struct iris_bo
*state_bo
= iris_resource_bo(surf
->surface_state_resource
);
1049 surf
->surface_state_offset
+= iris_bo_offset_from_base_address(state_bo
);
1051 isl_surf_fill_state(&screen
->isl_dev
, map
,
1052 .surf
= &res
->surf
, .view
= &surf
->view
,
1054 .address
= res
->bo
->gtt_offset
);
1056 // .clear_color = clear_color,
1062 iris_set_sampler_views(struct pipe_context
*ctx
,
1063 enum pipe_shader_type p_stage
,
1064 unsigned start
, unsigned count
,
1065 struct pipe_sampler_view
**views
)
1067 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1068 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1071 for (i
= 0; i
< count
; i
++) {
1072 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1073 &ice
->state
.textures
[stage
][i
], views
[i
]);
1075 for (; i
< ice
->state
.num_textures
[stage
]; i
++) {
1076 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1077 &ice
->state
.textures
[stage
][i
], NULL
);
1080 ice
->state
.num_textures
[stage
] = count
;
1082 // XXX: ice->state.dirty |= (IRIS_DIRTY_BINDING_TABLE_VS << stage);
1086 iris_set_clip_state(struct pipe_context
*ctx
,
1087 const struct pipe_clip_state
*state
)
1092 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1093 const struct pipe_poly_stipple
*state
)
1095 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1096 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1097 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1101 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1103 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1105 ice
->state
.sample_mask
= sample_mask
;
1106 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1110 iris_set_scissor_states(struct pipe_context
*ctx
,
1111 unsigned start_slot
,
1112 unsigned num_scissors
,
1113 const struct pipe_scissor_state
*states
)
1115 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1117 ice
->state
.num_scissors
= num_scissors
;
1119 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1120 ice
->state
.scissors
[start_slot
+ i
] = states
[i
];
1123 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1127 iris_set_stencil_ref(struct pipe_context
*ctx
,
1128 const struct pipe_stencil_ref
*state
)
1130 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1131 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1132 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1136 struct iris_viewport_state
{
1137 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
) * IRIS_MAX_VIEWPORTS
];
1141 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1143 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1148 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1149 float m00
, float m11
, float m30
, float m31
,
1150 float *xmin
, float *xmax
,
1151 float *ymin
, float *ymax
)
1153 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1154 * Strips and Fans documentation:
1156 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1157 * fixed-point "guardband" range supported by the rasterization hardware"
1161 * "In almost all circumstances, if an object’s vertices are actually
1162 * modified by this clamping (i.e., had X or Y coordinates outside of
1163 * the guardband extent the rendered object will not match the intended
1164 * result. Therefore software should take steps to ensure that this does
1165 * not happen - e.g., by clipping objects such that they do not exceed
1166 * these limits after the Drawing Rectangle is applied."
1168 * I believe the fundamental restriction is that the rasterizer (in
1169 * the SF/WM stages) have a limit on the number of pixels that can be
1170 * rasterized. We need to ensure any coordinates beyond the rasterizer
1171 * limit are handled by the clipper. So effectively that limit becomes
1172 * the clipper's guardband size.
1174 * It goes on to say:
1176 * "In addition, in order to be correctly rendered, objects must have a
1177 * screenspace bounding box not exceeding 8K in the X or Y direction.
1178 * This additional restriction must also be comprehended by software,
1179 * i.e., enforced by use of clipping."
1181 * This makes no sense. Gen7+ hardware supports 16K render targets,
1182 * and you definitely need to be able to draw polygons that fill the
1183 * surface. Our assumption is that the rasterizer was limited to 8K
1184 * on Sandybridge, which only supports 8K surfaces, and it was actually
1185 * increased to 16K on Ivybridge and later.
1187 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1189 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1191 if (m00
!= 0 && m11
!= 0) {
1192 /* First, we compute the screen-space render area */
1193 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1194 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1195 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1196 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1198 /* We want the guardband to be centered on that */
1199 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1200 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1201 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1202 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1204 /* Now we need it in native device coordinates */
1205 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1206 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1207 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1208 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1210 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1211 * flipped upside-down. X should be fine though.
1213 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1214 *xmin
= ndc_gb_xmin
;
1215 *xmax
= ndc_gb_xmax
;
1216 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1217 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1219 /* The viewport scales to 0, so nothing will be rendered. */
1229 iris_set_viewport_states(struct pipe_context
*ctx
,
1230 unsigned start_slot
,
1231 unsigned num_viewports
,
1232 const struct pipe_viewport_state
*state
)
1234 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1235 struct iris_viewport_state
*cso
=
1236 malloc(sizeof(struct iris_viewport_state
));
1237 uint32_t *vp_map
= &cso
->sf_cl_vp
[start_slot
];
1239 // XXX: sf_cl_vp is only big enough for one slot, we don't iterate right
1240 for (unsigned i
= 0; i
< num_viewports
; i
++) {
1241 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
1242 vp
.ViewportMatrixElementm00
= state
[i
].scale
[0];
1243 vp
.ViewportMatrixElementm11
= state
[i
].scale
[1];
1244 vp
.ViewportMatrixElementm22
= state
[i
].scale
[2];
1245 vp
.ViewportMatrixElementm30
= state
[i
].translate
[0];
1246 vp
.ViewportMatrixElementm31
= state
[i
].translate
[1];
1247 vp
.ViewportMatrixElementm32
= state
[i
].translate
[2];
1248 /* XXX: in i965 this is computed based on the drawbuffer size,
1249 * but we don't have that here...
1251 vp
.XMinClipGuardband
= -1.0;
1252 vp
.XMaxClipGuardband
= 1.0;
1253 vp
.YMinClipGuardband
= -1.0;
1254 vp
.YMaxClipGuardband
= 1.0;
1255 vp
.XMinViewPort
= viewport_extent(&state
[i
], 0, -1.0f
);
1256 vp
.XMaxViewPort
= viewport_extent(&state
[i
], 0, 1.0f
) - 1;
1257 vp
.YMinViewPort
= viewport_extent(&state
[i
], 1, -1.0f
);
1258 vp
.YMaxViewPort
= viewport_extent(&state
[i
], 1, 1.0f
) - 1;
1261 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
1264 ice
->state
.cso_vp
= cso
;
1265 ice
->state
.num_viewports
= num_viewports
;
1266 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1269 struct iris_depth_buffer_state
1271 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
1272 GENX(3DSTATE_STENCIL_BUFFER_length
) +
1273 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
1274 GENX(3DSTATE_CLEAR_PARAMS_length
)];
1278 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1279 const struct pipe_framebuffer_state
*state
)
1281 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1282 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1283 struct isl_device
*isl_dev
= &screen
->isl_dev
;
1284 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1286 if (cso
->samples
!= state
->samples
) {
1287 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1290 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
1291 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1294 util_copy_framebuffer_state(cso
, state
);
1296 struct iris_depth_buffer_state
*cso_z
=
1297 malloc(sizeof(struct iris_depth_buffer_state
));
1299 struct isl_view view
= {
1302 .base_array_layer
= 0,
1304 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1307 struct isl_depth_stencil_hiz_emit_info info
= {
1312 struct iris_resource
*zres
=
1313 (void *) (cso
->zsbuf
? cso
->zsbuf
->texture
: NULL
);
1316 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
1318 info
.depth_surf
= &zres
->surf
;
1319 info
.depth_address
= zres
->bo
->gtt_offset
;
1321 view
.format
= zres
->surf
.format
;
1323 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
1324 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
1326 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
1328 info
.hiz_usage
= ISL_AUX_USAGE_NONE
;
1333 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
1334 info
.stencil_surf
= &stencil_mt
->surf
;
1337 view
.base_level
= stencil_irb
->mt_level
- stencil_irb
->mt
->first_level
;
1338 view
.base_array_layer
= stencil_irb
->mt_layer
;
1339 view
.array_len
= MAX2(stencil_irb
->layer_count
, 1);
1340 view
.format
= stencil_mt
->surf
.format
;
1343 uint32_t stencil_offset
= 0;
1344 info
.stencil_address
= stencil_mt
->bo
->gtt_offset
+ stencil_mt
->offset
;
1348 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
1350 ice
->state
.cso_depthbuffer
= cso_z
;
1351 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
1355 iris_set_constant_buffer(struct pipe_context
*ctx
,
1356 enum pipe_shader_type p_stage
, unsigned index
,
1357 const struct pipe_constant_buffer
*input
)
1359 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1360 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1361 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1362 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
1363 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
1365 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1366 if (input
->user_buffer
) {
1367 u_upload_data(ctx
->const_uploader
, 0, input
->buffer_size
, 32,
1368 input
->user_buffer
, &cbuf
->offset
, &cbuf
->resource
);
1370 pipe_resource_reference(&cbuf
->resource
, input
->buffer
);
1374 // XXX: these are not retained forever, use a separate uploader?
1375 u_upload_alloc(ice
->state
.surface_uploader
, 0,
1376 4 * GENX(RENDER_SURFACE_STATE_length
), 64,
1377 &cbuf
->surface_state_offset
,
1378 &cbuf
->surface_state_resource
,
1380 if (!unlikely(map
)) {
1381 pipe_resource_reference(&cbuf
->resource
, NULL
);
1385 struct iris_resource
*res
= (void *) cbuf
->resource
;
1386 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state_resource
);
1387 cbuf
->surface_state_offset
+= iris_bo_offset_from_base_address(surf_bo
);
1389 isl_buffer_fill_state(&screen
->isl_dev
, map
,
1390 .address
= res
->bo
->gtt_offset
+ cbuf
->offset
,
1391 .size_B
= input
->buffer_size
,
1392 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
1396 pipe_resource_reference(&cbuf
->resource
, NULL
);
1397 pipe_resource_reference(&cbuf
->surface_state_resource
, NULL
);
1402 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1403 struct pipe_sampler_view
*state
)
1405 struct iris_sampler_view
*isv
= (void *) state
;
1406 pipe_resource_reference(&state
->texture
, NULL
);
1407 pipe_resource_reference(&isv
->surface_state_resource
, NULL
);
1413 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1415 struct iris_surface
*surf
= (void *) p_surf
;
1416 pipe_resource_reference(&p_surf
->texture
, NULL
);
1417 pipe_resource_reference(&surf
->surface_state_resource
, NULL
);
1422 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1427 struct iris_vertex_buffer_state
{
1428 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
1429 struct iris_bo
*bos
[33];
1430 unsigned num_buffers
;
1434 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
1437 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
1438 iris_bo_unreference(cso
->bos
[i
]);
1444 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1445 unsigned start_slot
, unsigned count
,
1446 const struct pipe_vertex_buffer
*buffers
)
1448 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1449 struct iris_vertex_buffer_state
*cso
=
1450 malloc(sizeof(struct iris_vertex_buffer_state
));
1452 /* If there are no buffers, do nothing. We can leave the stale
1453 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1454 * elements that point to them, it should be fine.
1459 iris_free_vertex_buffers(ice
->state
.cso_vertex_buffers
);
1461 cso
->num_buffers
= count
;
1463 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1464 vb
.DWordLength
= 4 * cso
->num_buffers
- 1;
1467 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1469 for (unsigned i
= 0; i
< count
; i
++) {
1470 assert(!buffers
[i
].is_user_buffer
);
1472 struct iris_resource
*res
= (void *) buffers
[i
].buffer
.resource
;
1473 iris_bo_reference(res
->bo
);
1474 cso
->bos
[i
] = res
->bo
;
1476 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1477 vb
.VertexBufferIndex
= start_slot
+ i
;
1479 vb
.AddressModifyEnable
= true;
1480 vb
.BufferPitch
= buffers
[i
].stride
;
1481 vb
.BufferSize
= res
->bo
->size
;
1482 vb
.BufferStartingAddress
=
1483 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffers
[i
].buffer_offset
);
1486 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1489 ice
->state
.cso_vertex_buffers
= cso
;
1490 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1493 struct iris_vertex_element_state
{
1494 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1495 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
1500 iris_create_vertex_elements(struct pipe_context
*ctx
,
1502 const struct pipe_vertex_element
*state
)
1504 struct iris_vertex_element_state
*cso
=
1505 malloc(sizeof(struct iris_vertex_element_state
));
1510 * - create edge flag one
1512 * - if those are necessary, use count + 1/2/3... OR in the length
1514 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
1516 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
1519 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1520 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
1522 for (int i
= 0; i
< count
; i
++) {
1523 enum isl_format isl_format
=
1524 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1525 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
1526 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
1528 switch (isl_format_get_num_channels(isl_format
)) {
1529 case 0: comp
[0] = VFCOMP_STORE_0
;
1530 case 1: comp
[1] = VFCOMP_STORE_0
;
1531 case 2: comp
[2] = VFCOMP_STORE_0
;
1533 comp
[3] = isl_format_has_int_channel(isl_format
) ? VFCOMP_STORE_1_INT
1534 : VFCOMP_STORE_1_FP
;
1537 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1538 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1540 ve
.SourceElementOffset
= state
[i
].src_offset
;
1541 ve
.SourceElementFormat
= isl_format
;
1542 ve
.Component0Control
= comp
[0];
1543 ve
.Component1Control
= comp
[1];
1544 ve
.Component2Control
= comp
[2];
1545 ve
.Component3Control
= comp
[3];
1548 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
1549 vi
.VertexElementIndex
= i
;
1550 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1551 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1554 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1555 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
1562 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
1564 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1566 ice
->state
.cso_vertex_elements
= state
;
1567 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
1571 iris_create_compute_state(struct pipe_context
*ctx
,
1572 const struct pipe_compute_state
*state
)
1577 static struct pipe_stream_output_target
*
1578 iris_create_stream_output_target(struct pipe_context
*ctx
,
1579 struct pipe_resource
*res
,
1580 unsigned buffer_offset
,
1581 unsigned buffer_size
)
1583 struct pipe_stream_output_target
*t
=
1584 CALLOC_STRUCT(pipe_stream_output_target
);
1588 pipe_reference_init(&t
->reference
, 1);
1589 pipe_resource_reference(&t
->buffer
, res
);
1590 t
->buffer_offset
= buffer_offset
;
1591 t
->buffer_size
= buffer_size
;
1596 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
1597 struct pipe_stream_output_target
*t
)
1599 pipe_resource_reference(&t
->buffer
, NULL
);
1604 iris_set_stream_output_targets(struct pipe_context
*ctx
,
1605 unsigned num_targets
,
1606 struct pipe_stream_output_target
**targets
,
1607 const unsigned *offsets
)
1612 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
1613 const struct brw_vue_map
*last_vue_map
,
1614 bool two_sided_color
,
1615 unsigned *out_offset
,
1616 unsigned *out_length
)
1618 /* The compiler computes the first URB slot without considering COL/BFC
1619 * swizzling (because it doesn't know whether it's enabled), so we need
1620 * to do that here too. This may result in a smaller offset, which
1623 const unsigned first_slot
=
1624 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
1626 /* This becomes the URB read offset (counted in pairs of slots). */
1627 assert(first_slot
% 2 == 0);
1628 *out_offset
= first_slot
/ 2;
1630 /* We need to adjust the inputs read to account for front/back color
1631 * swizzling, as it can make the URB length longer.
1633 for (int c
= 0; c
<= 1; c
++) {
1634 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
1635 /* If two sided color is enabled, the fragment shader's gl_Color
1636 * (COL0) input comes from either the gl_FrontColor (COL0) or
1637 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
1639 if (two_sided_color
)
1640 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1642 /* If front color isn't written, we opt to give them back color
1643 * instead of an undefined value. Switch from COL to BFC.
1645 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
1646 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
1647 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1652 /* Compute the minimum URB Read Length necessary for the FS inputs.
1654 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1655 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1657 * "This field should be set to the minimum length required to read the
1658 * maximum source attribute. The maximum source attribute is indicated
1659 * by the maximum value of the enabled Attribute # Source Attribute if
1660 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1661 * enable is not set.
1662 * read_length = ceiling((max_source_attr + 1) / 2)
1664 * [errata] Corruption/Hang possible if length programmed larger than
1667 * Similar text exists for Ivy Bridge.
1669 * We find the last URB slot that's actually read by the FS.
1671 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
1672 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
1673 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
1676 /* The URB read length is the difference of the two, counted in pairs. */
1677 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
1681 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
1683 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
1684 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
1685 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
1686 struct pipe_shader_state
*p_fs
=
1687 (void *) ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1688 assert(p_fs
->type
== PIPE_SHADER_IR_NIR
);
1689 nir_shader
*fs_nir
= p_fs
->ir
.nir
;
1691 unsigned urb_read_offset
, urb_read_length
;
1692 iris_compute_sbe_urb_read_interval(fs_nir
->info
.inputs_read
,
1693 ice
->shaders
.last_vue_map
,
1694 cso_rast
->light_twoside
,
1695 &urb_read_offset
, &urb_read_length
);
1697 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
1698 sbe
.AttributeSwizzleEnable
= true;
1699 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1700 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
1701 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
1702 sbe
.VertexURBEntryReadLength
= urb_read_length
;
1703 sbe
.ForceVertexURBEntryReadOffset
= true;
1704 sbe
.ForceVertexURBEntryReadLength
= true;
1705 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1707 for (int i
= 0; i
< 32; i
++) {
1708 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
1714 iris_bind_compute_state(struct pipe_context
*ctx
, void *state
)
1719 iris_populate_sampler_key(const struct iris_context
*ice
,
1720 struct brw_sampler_prog_key_data
*key
)
1722 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
1723 key
->swizzles
[i
] = 0x688; /* XYZW */
1728 iris_populate_vs_key(const struct iris_context
*ice
,
1729 struct brw_vs_prog_key
*key
)
1731 memset(key
, 0, sizeof(*key
));
1732 iris_populate_sampler_key(ice
, &key
->tex
);
1736 iris_populate_tcs_key(const struct iris_context
*ice
,
1737 struct brw_tcs_prog_key
*key
)
1739 memset(key
, 0, sizeof(*key
));
1740 iris_populate_sampler_key(ice
, &key
->tex
);
1744 iris_populate_tes_key(const struct iris_context
*ice
,
1745 struct brw_tes_prog_key
*key
)
1747 memset(key
, 0, sizeof(*key
));
1748 iris_populate_sampler_key(ice
, &key
->tex
);
1752 iris_populate_gs_key(const struct iris_context
*ice
,
1753 struct brw_gs_prog_key
*key
)
1755 memset(key
, 0, sizeof(*key
));
1756 iris_populate_sampler_key(ice
, &key
->tex
);
1760 iris_populate_fs_key(const struct iris_context
*ice
,
1761 struct brw_wm_prog_key
*key
)
1763 memset(key
, 0, sizeof(*key
));
1764 iris_populate_sampler_key(ice
, &key
->tex
);
1766 /* XXX: dirty flags? */
1767 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
1768 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
1769 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
1770 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
1772 key
->nr_color_regions
= fb
->nr_cbufs
;
1774 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
1776 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
1777 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
1779 // key->force_dual_color_blend for unigine
1781 if (cso_rast
->multisample
) {
1782 key
->persample_interp
=
1783 ctx
->Multisample
.SampleShading
&&
1784 (ctx
->Multisample
.MinSampleShadingValue
*
1785 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1);
1787 key
->multisample_fbo
= fb
->samples
> 1;
1791 key
->coherent_fb_fetch
= true;
1794 //pkt.SamplerCount = \
1795 //DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1796 //pkt.PerThreadScratchSpace = prog_data->total_scratch == 0 ? 0 : \
1797 //ffs(stage_state->per_thread_scratch) - 11; \
1800 KSP(const struct iris_compiled_shader
*shader
)
1802 struct iris_resource
*res
= (void *) shader
->buffer
;
1803 return res
->bo
->gtt_offset
+ shader
->offset
;
1806 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1807 pkt.KernelStartPointer = KSP(shader); \
1808 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
1809 pkt.FloatingPointMode = prog_data->use_alt_mode; \
1811 pkt.DispatchGRFStartRegisterForURBData = \
1812 prog_data->dispatch_grf_start_reg; \
1813 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1814 pkt.prefix##URBEntryReadOffset = 0; \
1816 pkt.StatisticsEnable = true; \
1820 iris_store_vs_state(const struct gen_device_info
*devinfo
,
1821 struct iris_compiled_shader
*shader
)
1823 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1824 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1826 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
1827 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1828 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1829 vs
.SIMD8DispatchEnable
= true;
1830 vs
.UserClipDistanceCullTestEnableBitmask
=
1831 vue_prog_data
->cull_distance_mask
;
1836 iris_store_tcs_state(const struct gen_device_info
*devinfo
,
1837 struct iris_compiled_shader
*shader
)
1839 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1840 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1841 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
1843 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
1844 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
1846 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
1847 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
1848 hs
.IncludeVertexHandles
= true;
1853 iris_store_tes_state(const struct gen_device_info
*devinfo
,
1854 struct iris_compiled_shader
*shader
)
1856 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1857 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1858 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
1860 uint32_t *te_state
= (void *) shader
->derived_data
;
1861 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
1863 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
1864 te
.Partitioning
= tes_prog_data
->partitioning
;
1865 te
.OutputTopology
= tes_prog_data
->output_topology
;
1866 te
.TEDomain
= tes_prog_data
->domain
;
1868 te
.MaximumTessellationFactorOdd
= 63.0;
1869 te
.MaximumTessellationFactorNotOdd
= 64.0;
1872 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
1873 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
1875 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
1876 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
1877 ds
.ComputeWCoordinateEnable
=
1878 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
1880 ds
.UserClipDistanceCullTestEnableBitmask
=
1881 vue_prog_data
->cull_distance_mask
;
1887 iris_store_gs_state(const struct gen_device_info
*devinfo
,
1888 struct iris_compiled_shader
*shader
)
1890 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1891 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1892 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
1894 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
1895 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
1897 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
1898 gs
.OutputTopology
= gs_prog_data
->output_topology
;
1899 gs
.ControlDataHeaderSize
=
1900 gs_prog_data
->control_data_header_size_hwords
;
1901 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
1902 gs
.DispatchMode
= SIMD8
;
1903 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
1904 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
1905 gs
.ReorderMode
= TRAILING
;
1906 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
1907 gs
.MaximumNumberofThreads
=
1908 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
1909 : (devinfo
->max_gs_threads
- 1);
1911 if (gs_prog_data
->static_vertex_count
!= -1) {
1912 gs
.StaticOutput
= true;
1913 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
1915 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
1917 gs
.UserClipDistanceCullTestEnableBitmask
=
1918 vue_prog_data
->cull_distance_mask
;
1920 const int urb_entry_write_offset
= 1;
1921 const uint32_t urb_entry_output_length
=
1922 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
1923 urb_entry_write_offset
;
1925 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
1926 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
1931 iris_store_fs_state(const struct gen_device_info
*devinfo
,
1932 struct iris_compiled_shader
*shader
)
1934 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1935 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
1937 uint32_t *ps_state
= (void *) shader
->derived_data
;
1938 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
1940 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
1941 ps
.VectorMaskEnable
= true;
1942 //ps.SamplerCount = ...
1943 ps
.BindingTableEntryCount
= prog_data
->binding_table
.size_bytes
/ 4;
1944 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
1945 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
1947 ps
.PushConstantEnable
= prog_data
->nr_params
> 0 ||
1948 prog_data
->ubo_ranges
[0].length
> 0;
1950 /* From the documentation for this packet:
1951 * "If the PS kernel does not need the Position XY Offsets to
1952 * compute a Position Value, then this field should be programmed
1953 * to POSOFFSET_NONE."
1955 * "SW Recommendation: If the PS kernel needs the Position Offsets
1956 * to compute a Position XY value, this field should match Position
1957 * ZW Interpolation Mode to ensure a consistent position.xyzw
1960 * We only require XY sample offsets. So, this recommendation doesn't
1961 * look useful at the moment. We might need this in future.
1963 ps
.PositionXYOffsetSelect
=
1964 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
1965 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1966 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1967 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
1969 // XXX: Disable SIMD32 with 16x MSAA
1971 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
1972 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
1973 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
1974 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
1975 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
1976 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
1978 ps
.KernelStartPointer0
=
1979 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
1980 ps
.KernelStartPointer1
=
1981 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
1982 ps
.KernelStartPointer2
=
1983 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
1986 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
1987 psx
.PixelShaderValid
= true;
1988 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1989 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
1990 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
1991 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1992 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1993 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
1995 if (wm_prog_data
->uses_sample_mask
) {
1996 /* TODO: conservative rasterization */
1997 if (wm_prog_data
->post_depth_coverage
)
1998 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
2000 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
2003 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
2004 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
2005 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
2012 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
2014 assert(cache_id
<= IRIS_CACHE_BLORP
);
2016 static const unsigned dwords
[] = {
2017 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
2018 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
2019 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
2020 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
2022 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
2023 [IRIS_CACHE_CS
] = 0,
2024 [IRIS_CACHE_BLORP
] = 0,
2027 return sizeof(uint32_t) * dwords
[cache_id
];
2031 iris_store_derived_program_state(const struct gen_device_info
*devinfo
,
2032 enum iris_program_cache_id cache_id
,
2033 struct iris_compiled_shader
*shader
)
2037 iris_store_vs_state(devinfo
, shader
);
2039 case IRIS_CACHE_TCS
:
2040 iris_store_tcs_state(devinfo
, shader
);
2042 case IRIS_CACHE_TES
:
2043 iris_store_tes_state(devinfo
, shader
);
2046 iris_store_gs_state(devinfo
, shader
);
2049 iris_store_fs_state(devinfo
, shader
);
2052 case IRIS_CACHE_BLORP
:
2060 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
2062 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
2063 const unsigned push_size_kB
= 32;
2064 unsigned entries
[4];
2068 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2069 if (!ice
->shaders
.prog
[i
]) {
2072 struct brw_vue_prog_data
*vue_prog_data
=
2073 (void *) ice
->shaders
.prog
[i
]->prog_data
;
2074 size
[i
] = vue_prog_data
->urb_entry_size
;
2076 assert(size
[i
] != 0);
2079 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
2080 1024 * ice
->shaders
.urb_size
,
2081 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
2082 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
2083 size
, entries
, start
);
2085 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2086 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
2087 urb
._3DCommandSubOpcode
+= i
;
2088 urb
.VSURBStartingAddress
= start
[i
];
2089 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
2090 urb
.VSNumberofURBEntries
= entries
[i
];
2095 static const uint32_t push_constant_opcodes
[] = {
2096 [MESA_SHADER_VERTEX
] = 21,
2097 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2098 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2099 [MESA_SHADER_GEOMETRY
] = 22,
2100 [MESA_SHADER_FRAGMENT
] = 23,
2101 [MESA_SHADER_COMPUTE
] = 0,
2105 * Add a surface to the validation list, as well as the buffer containing
2106 * the corresponding SURFACE_STATE.
2108 * Returns the binding table entry (offset to SURFACE_STATE).
2111 use_surface(struct iris_batch
*batch
,
2112 struct pipe_surface
*p_surf
,
2115 struct iris_surface
*surf
= (void *) p_surf
;
2116 struct iris_resource
*res
= (void *) p_surf
->texture
;
2117 struct iris_resource
*state_res
= (void *) surf
->surface_state_resource
;
2118 iris_use_pinned_bo(batch
, res
->bo
, writeable
);
2119 iris_use_pinned_bo(batch
, state_res
->bo
, false);
2121 return surf
->surface_state_offset
;
2125 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
2127 struct iris_resource
*res
= (void *) isv
->pipe
.texture
;
2128 struct iris_resource
*state_res
= (void *) isv
->surface_state_resource
;
2129 iris_use_pinned_bo(batch
, res
->bo
, false);
2130 iris_use_pinned_bo(batch
, state_res
->bo
, false);
2132 return isv
->surface_state_offset
;
2136 use_const_buffer(struct iris_batch
*batch
, struct iris_const_buffer
*cbuf
)
2138 struct iris_resource
*res
= (void *) cbuf
->resource
;
2139 struct iris_resource
*state_res
= (void *) cbuf
->surface_state_resource
;
2140 iris_use_pinned_bo(batch
, res
->bo
, false);
2141 iris_use_pinned_bo(batch
, state_res
->bo
, false);
2143 return cbuf
->surface_state_offset
;
2147 iris_populate_binding_table(struct iris_context
*ice
,
2148 struct iris_batch
*batch
,
2149 gl_shader_stage stage
)
2151 const struct iris_binder
*binder
= &batch
->binder
;
2152 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2158 // - ubos/ssbos/abos
2161 // - render targets - write and read
2163 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
2164 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
2167 if (stage
== MESA_SHADER_FRAGMENT
) {
2168 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2169 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
2170 bt_map
[s
++] = use_surface(batch
, cso_fb
->cbufs
[i
], true);
2174 //assert(prog_data->binding_table.texture_start ==
2175 //(ice->state.num_textures[stage] ? s : 0xd0d0d0d0));
2177 for (int i
= 0; i
< ice
->state
.num_textures
[stage
]; i
++) {
2178 struct iris_sampler_view
*view
= ice
->state
.textures
[stage
][i
];
2179 bt_map
[s
++] = use_sampler_view(batch
, view
);
2182 // XXX: want the number of BTE's to shorten this loop
2183 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2184 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
2185 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[i
];
2186 if (!cbuf
->surface_state_resource
)
2189 bt_map
[s
++] = use_const_buffer(batch
, cbuf
);
2192 // XXX: not implemented yet
2193 assert(prog_data
->binding_table
.pull_constants_start
== 0xd0d0d0d0);
2194 assert(prog_data
->binding_table
.ubo_start
== 0xd0d0d0d0);
2195 assert(prog_data
->binding_table
.ssbo_start
== 0xd0d0d0d0);
2196 assert(prog_data
->binding_table
.image_start
== 0xd0d0d0d0);
2197 assert(prog_data
->binding_table
.shader_time_start
== 0xd0d0d0d0);
2198 //assert(prog_data->binding_table.plane_start[1] == 0xd0d0d0d0);
2199 //assert(prog_data->binding_table.plane_start[2] == 0xd0d0d0d0);
2204 iris_use_optional_res(struct iris_batch
*batch
,
2205 struct pipe_resource
*res
,
2209 struct iris_bo
*bo
= iris_resource_bo(res
);
2210 iris_use_pinned_bo(batch
, bo
, writeable
);
2216 * Pin any BOs which were installed by a previous batch, and restored
2217 * via the hardware logical context mechanism.
2219 * We don't need to re-emit all state every batch - the hardware context
2220 * mechanism will save and restore it for us. This includes pointers to
2221 * various BOs...which won't exist unless we ask the kernel to pin them
2222 * by adding them to the validation list.
2224 * We can skip buffers if we've re-emitted those packets, as we're
2225 * overwriting those stale pointers with new ones, and don't actually
2226 * refer to the old BOs.
2229 iris_restore_context_saved_bos(struct iris_context
*ice
,
2230 struct iris_batch
*batch
,
2231 const struct pipe_draw_info
*draw
)
2233 // XXX: whack IRIS_SHADER_DIRTY_BINDING_TABLE on new batch
2235 const uint64_t clean
=
2236 unlikely(INTEL_DEBUG
& DEBUG_REEMIT
) ? 0ull : ~ice
->state
.dirty
;
2238 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
2239 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
2242 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
2243 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
2246 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
2247 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
2250 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
2251 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
2254 if (clean
& IRIS_DIRTY_SCISSOR
) {
2255 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
2258 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2259 if (clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
))
2262 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2263 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2268 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
2270 for (int i
= 0; i
< 4; i
++) {
2271 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2273 if (range
->length
== 0)
2276 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
2277 struct iris_resource
*res
= (void *) cbuf
->resource
;
2279 iris_use_pinned_bo(batch
, res
->bo
, false);
2283 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2284 struct pipe_resource
*res
= ice
->state
.sampler_table_resource
[stage
];
2286 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
2289 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2290 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
2291 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2293 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->buffer
), false);
2295 // XXX: scratch buffer
2299 // XXX: 3DSTATE_SO_BUFFER
2301 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
2302 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2304 if (cso_fb
->zsbuf
) {
2305 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
2306 // XXX: depth might not be writable...
2307 iris_use_pinned_bo(batch
, zres
->bo
, true);
2311 if (draw
->index_size
> 0) {
2312 // XXX: index buffer
2315 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
2316 struct iris_vertex_buffer_state
*cso
= ice
->state
.cso_vertex_buffers
;
2317 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
2318 iris_use_pinned_bo(batch
, cso
->bos
[i
], false);
2324 iris_upload_render_state(struct iris_context
*ice
,
2325 struct iris_batch
*batch
,
2326 const struct pipe_draw_info
*draw
)
2328 const uint64_t dirty
=
2329 unlikely(INTEL_DEBUG
& DEBUG_REEMIT
) ? ~0ull : ice
->state
.dirty
;
2331 struct brw_wm_prog_data
*wm_prog_data
= (void *)
2332 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2334 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
2335 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2336 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2337 ptr
.CCViewportPointer
=
2338 emit_state(batch
, ice
->state
.dynamic_uploader
,
2339 &ice
->state
.last_res
.cc_vp
,
2340 cso
->cc_vp
, sizeof(cso
->cc_vp
), 32);
2344 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
2345 struct iris_viewport_state
*cso
= ice
->state
.cso_vp
;
2346 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2347 ptr
.SFClipViewportPointer
=
2348 emit_state(batch
, ice
->state
.dynamic_uploader
,
2349 &ice
->state
.last_res
.sf_cl_vp
,
2350 cso
->sf_cl_vp
, 4 * GENX(SF_CLIP_VIEWPORT_length
) *
2351 ice
->state
.num_viewports
, 64);
2357 if (dirty
& IRIS_DIRTY_URB
) {
2358 iris_upload_urb_config(ice
, batch
);
2361 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
2362 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2363 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2364 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2365 const int num_dwords
= 4 * (GENX(BLEND_STATE_length
) +
2366 cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
));
2367 uint32_t blend_offset
;
2368 uint32_t *blend_map
=
2369 stream_state(batch
, ice
->state
.dynamic_uploader
,
2370 &ice
->state
.last_res
.blend
,
2371 4 * num_dwords
, 64, &blend_offset
);
2373 uint32_t blend_state_header
;
2374 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
2375 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2376 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
2379 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
2380 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1],
2381 sizeof(cso_blend
->blend_state
) - sizeof(uint32_t));
2383 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2384 ptr
.BlendStatePointer
= blend_offset
;
2385 ptr
.BlendStatePointerValid
= true;
2389 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
2390 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2393 stream_state(batch
, ice
->state
.dynamic_uploader
,
2394 &ice
->state
.last_res
.color_calc
,
2395 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
2397 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
2398 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
2399 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
2400 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
2401 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
2402 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
2403 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
2405 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2406 ptr
.ColorCalcStatePointer
= cc_offset
;
2407 ptr
.ColorCalcStatePointerValid
= true;
2411 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2412 // XXX: wrong dirty tracking...
2413 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
2416 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2417 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2422 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
2424 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2425 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2427 /* The Skylake PRM contains the following restriction:
2429 * "The driver must ensure The following case does not occur
2430 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2431 * buffer 3 read length equal to zero committed followed by a
2432 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2435 * To avoid this, we program the buffers in the highest slots.
2436 * This way, slot 0 is only used if slot 3 is also used.
2440 for (int i
= 3; i
>= 0; i
--) {
2441 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2443 if (range
->length
== 0)
2446 // XXX: is range->block a constbuf index? it would be nice
2447 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
2448 struct iris_resource
*res
= (void *) cbuf
->resource
;
2450 assert(cbuf
->offset
% 32 == 0);
2452 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
2453 pkt
.ConstantBody
.Buffer
[n
] =
2454 ro_bo(res
->bo
, range
->start
* 32 + cbuf
->offset
);
2461 if (1) { // XXX: DIRTY BINDINGS
2462 const struct iris_binder
*binder
= &batch
->binder
;
2464 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2465 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
2466 ptr
._3DCommandSubOpcode
= 38 + stage
;
2467 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
2471 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2472 iris_populate_binding_table(ice
, batch
, stage
);
2476 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2477 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
2478 !ice
->shaders
.prog
[stage
])
2481 struct pipe_resource
*res
= ice
->state
.sampler_table_resource
[stage
];
2483 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
2485 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
2486 ptr
._3DCommandSubOpcode
= 43 + stage
;
2487 ptr
.PointertoVSSamplerState
= ice
->state
.sampler_table_offset
[stage
];
2491 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
2492 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
2494 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
2495 if (ice
->state
.framebuffer
.samples
> 0)
2496 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
2500 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
2501 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
2502 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
2506 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2507 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
2510 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2513 struct iris_resource
*cache
= (void *) shader
->buffer
;
2514 iris_use_pinned_bo(batch
, cache
->bo
, false);
2515 iris_batch_emit(batch
, shader
->derived_data
,
2516 iris_derived_program_state_size(stage
));
2518 if (stage
== MESA_SHADER_TESS_EVAL
) {
2519 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
2520 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
2521 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
2522 } else if (stage
== MESA_SHADER_GEOMETRY
) {
2523 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
2529 // 3DSTATE_STREAMOUT
2530 // 3DSTATE_SO_BUFFER
2531 // 3DSTATE_SO_DECL_LIST
2533 if (dirty
& IRIS_DIRTY_CLIP
) {
2534 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2535 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2537 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
2538 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
2539 if (wm_prog_data
->barycentric_interp_modes
&
2540 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
2541 cl
.NonPerspectiveBarycentricEnable
= true;
2543 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
2545 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
2546 ARRAY_SIZE(cso_rast
->clip
));
2549 if (dirty
& IRIS_DIRTY_RASTER
) {
2550 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2551 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
2552 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
2556 /* XXX: FS program updates needs to flag IRIS_DIRTY_WM */
2557 if (dirty
& IRIS_DIRTY_WM
) {
2558 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2559 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
2561 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
2562 wm
.BarycentricInterpolationMode
=
2563 wm_prog_data
->barycentric_interp_modes
;
2565 if (wm_prog_data
->early_fragment_tests
)
2566 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
2567 else if (wm_prog_data
->has_side_effects
)
2568 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
2570 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
2574 // XXX: 3DSTATE_SBE, 3DSTATE_SBE_SWIZ
2575 // -> iris_raster_state (point sprite texture coordinate origin)
2576 // -> bunch of shader state...
2577 iris_emit_sbe(batch
, ice
);
2578 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbe
) {
2582 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
2583 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2584 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2585 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
2586 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
2587 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
2588 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2591 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
2592 ARRAY_SIZE(cso_blend
->ps_blend
));
2595 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
2596 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2597 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
2599 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
2600 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
2601 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
2602 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
2604 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
2607 if (dirty
& IRIS_DIRTY_SCISSOR
) {
2608 // XXX: allocate at set_scissor time?
2609 uint32_t scissor_offset
= ice
->state
.num_scissors
== 0 ? 0 :
2610 emit_state(batch
, ice
->state
.dynamic_uploader
,
2611 &ice
->state
.last_res
.scissor
,
2612 ice
->state
.scissors
,
2613 sizeof(struct pipe_scissor_state
) *
2614 ice
->state
.num_scissors
, 32);
2616 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2617 ptr
.ScissorRectPointer
= scissor_offset
;
2621 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
2622 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2623 struct iris_depth_buffer_state
*cso_z
= ice
->state
.cso_depthbuffer
;
2625 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
2627 if (cso_fb
->zsbuf
) {
2628 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
2629 // XXX: depth might not be writable...
2630 iris_use_pinned_bo(batch
, zres
->bo
, true);
2634 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
2635 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
2636 for (int i
= 0; i
< 32; i
++) {
2637 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
2642 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
2643 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2644 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
2648 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
2649 topo
.PrimitiveTopologyType
=
2650 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
2654 if (draw
->index_size
> 0) {
2655 struct iris_resource
*res
= NULL
;
2658 if (draw
->has_user_indices
) {
2659 u_upload_data(ice
->ctx
.stream_uploader
, 0,
2660 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
2661 &offset
, (struct pipe_resource
**) &res
);
2663 res
= (struct iris_resource
*) draw
->index
.resource
;
2667 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
2668 ib
.IndexFormat
= draw
->index_size
>> 1;
2670 ib
.BufferSize
= res
->bo
->size
;
2671 ib
.BufferStartingAddress
= ro_bo(res
->bo
, offset
);
2675 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
2676 struct iris_vertex_buffer_state
*cso
= ice
->state
.cso_vertex_buffers
;
2677 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
2679 iris_batch_emit(batch
, cso
->vertex_buffers
,
2680 sizeof(uint32_t) * (1 + vb_dwords
* cso
->num_buffers
));
2682 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
2683 iris_use_pinned_bo(batch
, cso
->bos
[i
], false);
2687 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
2688 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
2689 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
2690 (1 + cso
->count
* GENX(VERTEX_ELEMENT_STATE_length
)));
2691 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
2692 cso
->count
* GENX(3DSTATE_VF_INSTANCING_length
));
2693 for (int i
= 0; i
< cso
->count
; i
++) {
2694 /* TODO: vertexid, instanceid support */
2695 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
);
2700 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
2701 if (draw
->primitive_restart
) {
2702 vf
.IndexedDrawCutIndexEnable
= true;
2703 vf
.CutIndex
= draw
->restart_index
;
2708 // XXX: Gen8 - PMA fix
2710 assert(!draw
->indirect
); // XXX: indirect support
2712 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
2713 prim
.StartInstanceLocation
= draw
->start_instance
;
2714 prim
.InstanceCount
= draw
->instance_count
;
2715 prim
.VertexCountPerInstance
= draw
->count
;
2716 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
2718 // XXX: this is probably bonkers.
2719 prim
.StartVertexLocation
= draw
->start
;
2721 if (draw
->index_size
) {
2722 prim
.BaseVertexLocation
+= draw
->index_bias
;
2724 prim
.StartVertexLocation
+= draw
->index_bias
;
2727 //prim.BaseVertexLocation = ...;
2730 if (!batch
->contains_draw
) {
2731 iris_restore_context_saved_bos(ice
, batch
, draw
);
2732 batch
->contains_draw
= true;
2737 iris_destroy_state(struct iris_context
*ice
)
2739 // XXX: unreference resources/surfaces.
2740 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
2741 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
2743 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
2747 flags_to_post_sync_op(uint32_t flags
)
2749 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
2750 return WriteImmediateData
;
2752 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
2753 return WritePSDepthCount
;
2755 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
2756 return WriteTimestamp
;
2762 * Do the given flags have a Post Sync or LRI Post Sync operation?
2764 static enum pipe_control_flags
2765 get_post_sync_flags(enum pipe_control_flags flags
)
2767 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
2768 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2769 PIPE_CONTROL_WRITE_TIMESTAMP
|
2770 PIPE_CONTROL_LRI_POST_SYNC_OP
;
2772 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
2773 * "LRI Post Sync Operation". So more than one bit set would be illegal.
2775 assert(util_bitcount(flags
) <= 1);
2780 // XXX: compute support
2781 #define IS_COMPUTE_PIPELINE(batch) (batch->ring != I915_EXEC_RENDER)
2784 * Emit a series of PIPE_CONTROL commands, taking into account any
2785 * workarounds necessary to actually accomplish the caller's request.
2787 * Unless otherwise noted, spec quotations in this function come from:
2789 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
2790 * Restrictions for PIPE_CONTROL.
2793 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
2794 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
2796 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
2797 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
2798 enum pipe_control_flags non_lri_post_sync_flags
=
2799 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
2801 /* Recursive PIPE_CONTROL workarounds --------------------------------
2802 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
2804 * We do these first because we want to look at the original operation,
2805 * rather than any workarounds we set.
2807 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
2808 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
2809 * lists several workarounds:
2811 * "Project: SKL, KBL, BXT
2813 * If the VF Cache Invalidation Enable is set to a 1 in a
2814 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
2815 * sets to 0, with the VF Cache Invalidation Enable set to 0
2816 * needs to be sent prior to the PIPE_CONTROL with VF Cache
2817 * Invalidation Enable set to a 1."
2819 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
2822 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
2823 /* Project: SKL / Argument: LRI Post Sync Operation [23]
2825 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2826 * programmed prior to programming a PIPECONTROL command with "LRI
2827 * Post Sync Operation" in GPGPU mode of operation (i.e when
2828 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2830 * The same text exists a few rows below for Post Sync Op.
2832 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
2835 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
2837 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
2838 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
2839 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
2841 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
2845 /* "Flush Types" workarounds ---------------------------------------------
2846 * We do these now because they may add post-sync operations or CS stalls.
2849 if (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
2850 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
2852 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
2853 * 'Write PS Depth Count' or 'Write Timestamp'."
2856 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
2857 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
2858 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
2859 bo
= batch
->screen
->workaround_bo
;
2863 /* #1130 from Gen10 workarounds page:
2865 * "Enable Depth Stall on every Post Sync Op if Render target Cache
2866 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
2867 * board stall if Render target cache flush is enabled."
2869 * Applicable to CNL B0 and C0 steppings only.
2871 * The wording here is unclear, and this workaround doesn't look anything
2872 * like the internal bug report recommendations, but leave it be for now...
2874 if (GEN_GEN
== 10) {
2875 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
2876 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
2877 } else if (flags
& non_lri_post_sync_flags
) {
2878 flags
|= PIPE_CONTROL_DEPTH_STALL
;
2882 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
2883 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
2885 * "This bit must be DISABLED for operations other than writing
2888 * This seems like nonsense. An Ivybridge workaround requires us to
2889 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
2890 * operation. Gen8+ requires us to emit depth stalls and depth cache
2891 * flushes together. So, it's hard to imagine this means anything other
2892 * than "we originally intended this to be used for PS_DEPTH_COUNT".
2894 * We ignore the supposed restriction and do nothing.
2898 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2899 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
2900 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
2902 * "This bit must be DISABLED for End-of-pipe (Read) fences,
2903 * PS_DEPTH_COUNT or TIMESTAMP queries."
2905 * TODO: Implement end-of-pipe checking.
2907 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2908 PIPE_CONTROL_WRITE_TIMESTAMP
)));
2911 if (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) {
2912 /* From the PIPE_CONTROL instruction table, bit 1:
2914 * "This bit is ignored if Depth Stall Enable is set.
2915 * Further, the render cache is not flushed even if Write Cache
2916 * Flush Enable bit is set."
2918 * We assert that the caller doesn't do this combination, to try and
2919 * prevent mistakes. It shouldn't hurt the GPU, though.
2921 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
2922 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
2925 /* PIPE_CONTROL page workarounds ------------------------------------- */
2927 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
2928 /* From the PIPE_CONTROL page itself:
2931 * Restriction: Pipe_control with CS-stall bit set must be issued
2932 * before a pipe-control command that has the State Cache
2933 * Invalidate bit set."
2935 flags
|= PIPE_CONTROL_CS_STALL
;
2938 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
2939 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
2942 * SW must always program Post-Sync Operation to "Write Immediate
2943 * Data" when Flush LLC is set."
2945 * For now, we just require the caller to do it.
2947 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
2950 /* "Post-Sync Operation" workarounds -------------------------------- */
2952 /* Project: All / Argument: Global Snapshot Count Reset [19]
2954 * "This bit must not be exercised on any product.
2955 * Requires stall bit ([20] of DW1) set."
2957 * We don't use this, so we just assert that it isn't used. The
2958 * PIPE_CONTROL instruction page indicates that they intended this
2959 * as a debug feature and don't think it is useful in production,
2960 * but it may actually be usable, should we ever want to.
2962 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
2964 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
2965 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
2966 /* Project: All / Arguments:
2968 * - Generic Media State Clear [16]
2969 * - Indirect State Pointers Disable [16]
2971 * "Requires stall bit ([20] of DW1) set."
2973 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
2974 * State Clear) says:
2976 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2977 * programmed prior to programming a PIPECONTROL command with "Media
2978 * State Clear" set in GPGPU mode of operation"
2980 * This is a subset of the earlier rule, so there's nothing to do.
2982 flags
|= PIPE_CONTROL_CS_STALL
;
2985 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
2986 /* Project: All / Argument: Store Data Index
2988 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
2991 * For now, we just assert that the caller does this. We might want to
2992 * automatically add a write to the workaround BO...
2994 assert(non_lri_post_sync_flags
!= 0);
2997 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
2998 /* Project: All / Argument: Sync GFDT
3000 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
3001 * than '0' or 0x2520[13] must be set."
3003 * For now, we just assert that the caller does this.
3005 assert(non_lri_post_sync_flags
!= 0);
3008 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
3009 /* Project: IVB+ / Argument: TLB inv
3011 * "Requires stall bit ([20] of DW1) set."
3013 * Also, from the PIPE_CONTROL instruction table:
3016 * Post Sync Operation or CS stall must be set to ensure a TLB
3017 * invalidation occurs. Otherwise no cycle will occur to the TLB
3018 * cache to invalidate."
3020 * This is not a subset of the earlier rule, so there's nothing to do.
3022 flags
|= PIPE_CONTROL_CS_STALL
;
3025 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
3026 /* TODO: The big Skylake GT4 post sync op workaround */
3029 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
3031 if (IS_COMPUTE_PIPELINE(batch
)) {
3032 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
3033 /* Project: SKL+ / Argument: Tex Invalidate
3034 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
3036 flags
|= PIPE_CONTROL_CS_STALL
;
3039 if (GEN_GEN
== 8 && (post_sync_flags
||
3040 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
3041 PIPE_CONTROL_DEPTH_STALL
|
3042 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
3043 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
3044 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
3045 /* Project: BDW / Arguments:
3047 * - LRI Post Sync Operation [23]
3048 * - Post Sync Op [15:14]
3050 * - Depth Stall [13]
3051 * - Render Target Cache Flush [12]
3052 * - Depth Cache Flush [0]
3053 * - DC Flush Enable [5]
3055 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
3058 flags
|= PIPE_CONTROL_CS_STALL
;
3060 /* Also, from the PIPE_CONTROL instruction table, bit 20:
3063 * This bit must be always set when PIPE_CONTROL command is
3064 * programmed by GPGPU and MEDIA workloads, except for the cases
3065 * when only Read Only Cache Invalidation bits are set (State
3066 * Cache Invalidation Enable, Instruction cache Invalidation
3067 * Enable, Texture Cache Invalidation Enable, Constant Cache
3068 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
3069 * need not implemented when FF_DOP_CG is disable via "Fixed
3070 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
3072 * It sounds like we could avoid CS stalls in some cases, but we
3073 * don't currently bother. This list isn't exactly the list above,
3079 /* "Stall" workarounds ----------------------------------------------
3080 * These have to come after the earlier ones because we may have added
3081 * some additional CS stalls above.
3084 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
3085 /* Project: PRE-SKL, VLV, CHV
3087 * "[All Stepping][All SKUs]:
3089 * One of the following must also be set:
3091 * - Render Target Cache Flush Enable ([12] of DW1)
3092 * - Depth Cache Flush Enable ([0] of DW1)
3093 * - Stall at Pixel Scoreboard ([1] of DW1)
3094 * - Depth Stall ([13] of DW1)
3095 * - Post-Sync Operation ([13] of DW1)
3096 * - DC Flush Enable ([5] of DW1)"
3098 * If we don't already have one of those bits set, we choose to add
3099 * "Stall at Pixel Scoreboard". Some of the other bits require a
3100 * CS stall as a workaround (see above), which would send us into
3101 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
3102 * appears to be safe, so we choose that.
3104 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
3105 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
3106 PIPE_CONTROL_WRITE_IMMEDIATE
|
3107 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
3108 PIPE_CONTROL_WRITE_TIMESTAMP
|
3109 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
3110 PIPE_CONTROL_DEPTH_STALL
|
3111 PIPE_CONTROL_DATA_CACHE_FLUSH
;
3112 if (!(flags
& wa_bits
))
3113 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
3116 /* Emit --------------------------------------------------------------- */
3118 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
3119 pc
.LRIPostSyncOperation
= NoLRIOperation
;
3120 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
3121 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
3122 pc
.StoreDataIndex
= 0;
3123 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
3124 pc
.GlobalSnapshotCountReset
=
3125 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
3126 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
3127 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
3128 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
3129 pc
.RenderTargetCacheFlushEnable
=
3130 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
3131 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
3132 pc
.StateCacheInvalidationEnable
=
3133 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
3134 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
3135 pc
.ConstantCacheInvalidationEnable
=
3136 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
3137 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
3138 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
3139 pc
.InstructionCacheInvalidateEnable
=
3140 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
3141 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
3142 pc
.IndirectStatePointersDisable
=
3143 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
3144 pc
.TextureCacheInvalidationEnable
=
3145 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
3146 pc
.Address
= ro_bo(bo
, offset
);
3147 pc
.ImmediateData
= imm
;
3152 genX(init_state
)(struct iris_context
*ice
)
3154 struct pipe_context
*ctx
= &ice
->ctx
;
3156 ctx
->create_blend_state
= iris_create_blend_state
;
3157 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
3158 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
3159 ctx
->create_sampler_state
= iris_create_sampler_state
;
3160 ctx
->create_sampler_view
= iris_create_sampler_view
;
3161 ctx
->create_surface
= iris_create_surface
;
3162 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
3163 ctx
->create_compute_state
= iris_create_compute_state
;
3164 ctx
->bind_blend_state
= iris_bind_blend_state
;
3165 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
3166 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
3167 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
3168 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
3169 ctx
->bind_compute_state
= iris_bind_compute_state
;
3170 ctx
->delete_blend_state
= iris_delete_state
;
3171 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
3172 ctx
->delete_fs_state
= iris_delete_state
;
3173 ctx
->delete_rasterizer_state
= iris_delete_state
;
3174 ctx
->delete_sampler_state
= iris_delete_state
;
3175 ctx
->delete_vertex_elements_state
= iris_delete_state
;
3176 ctx
->delete_compute_state
= iris_delete_state
;
3177 ctx
->delete_tcs_state
= iris_delete_state
;
3178 ctx
->delete_tes_state
= iris_delete_state
;
3179 ctx
->delete_gs_state
= iris_delete_state
;
3180 ctx
->delete_vs_state
= iris_delete_state
;
3181 ctx
->set_blend_color
= iris_set_blend_color
;
3182 ctx
->set_clip_state
= iris_set_clip_state
;
3183 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
3184 ctx
->set_sampler_views
= iris_set_sampler_views
;
3185 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
3186 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
3187 ctx
->set_sample_mask
= iris_set_sample_mask
;
3188 ctx
->set_scissor_states
= iris_set_scissor_states
;
3189 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
3190 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
3191 ctx
->set_viewport_states
= iris_set_viewport_states
;
3192 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
3193 ctx
->surface_destroy
= iris_surface_destroy
;
3194 ctx
->draw_vbo
= iris_draw_vbo
;
3195 ctx
->launch_grid
= iris_launch_grid
;
3196 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
3197 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
3198 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
3200 ice
->vtbl
.destroy_state
= iris_destroy_state
;
3201 ice
->vtbl
.init_render_context
= iris_init_render_context
;
3202 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
3203 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
3204 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
3205 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
3206 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
3207 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
3208 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
3209 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
3210 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
3212 ice
->state
.dirty
= ~0ull;