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20 * DEALINGS IN THE SOFTWARE.
26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_inlines.h"
92 #include "util/u_format.h"
93 #include "util/u_framebuffer.h"
94 #include "util/u_transfer.h"
95 #include "util/u_upload_mgr.h"
96 #include "util/u_viewport.h"
99 #include "intel/compiler/brw_compiler.h"
100 #include "intel/common/gen_l3_config.h"
101 #include "intel/common/gen_sample_positions.h"
102 #include "iris_batch.h"
103 #include "iris_context.h"
104 #include "iris_pipe.h"
105 #include "iris_resource.h"
107 #define __gen_address_type struct iris_address
108 #define __gen_user_data struct iris_batch
110 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
113 __gen_combine_address(struct iris_batch
*batch
, void *location
,
114 struct iris_address addr
, uint32_t delta
)
116 uint64_t result
= addr
.offset
+ delta
;
119 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
120 /* Assume this is a general address, not relative to a base. */
121 result
+= addr
.bo
->gtt_offset
;
127 #define __genxml_cmd_length(cmd) cmd ## _length
128 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
129 #define __genxml_cmd_header(cmd) cmd ## _header
130 #define __genxml_cmd_pack(cmd) cmd ## _pack
132 #define _iris_pack_command(batch, cmd, dst, name) \
133 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
134 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
135 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
139 #define iris_pack_command(cmd, dst, name) \
140 _iris_pack_command(NULL, cmd, dst, name)
142 #define iris_pack_state(cmd, dst, name) \
143 for (struct cmd name = {}, \
144 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
145 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
148 #define iris_emit_cmd(batch, cmd, name) \
149 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
151 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
153 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
154 for (uint32_t i = 0; i < num_dwords; i++) \
155 dw[i] = (dwords0)[i] | (dwords1)[i]; \
156 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
159 #include "genxml/genX_pack.h"
160 #include "genxml/gen_macros.h"
161 #include "genxml/genX_bits.h"
163 #define MOCS_WB (2 << 1)
166 * Statically assert that PIPE_* enums match the hardware packets.
167 * (As long as they match, we don't need to translate them.)
169 UNUSED
static void pipe_asserts()
171 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
173 /* pipe_logicop happens to match the hardware. */
174 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
175 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
176 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
177 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
178 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
179 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
180 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
181 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
182 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
183 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
184 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
185 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
186 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
187 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
188 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
189 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
191 /* pipe_blend_func happens to match the hardware. */
192 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
193 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
194 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
195 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
196 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
197 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
198 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
199 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
200 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
201 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
202 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
203 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
204 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
205 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
206 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
207 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
212 /* pipe_blend_func happens to match the hardware. */
213 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
214 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
215 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
216 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
217 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
219 /* pipe_stencil_op happens to match the hardware. */
220 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
221 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
222 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
223 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
224 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
225 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
226 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
227 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
229 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
230 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
231 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
236 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
238 static const unsigned map
[] = {
239 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
240 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
241 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
242 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
243 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
244 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
245 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
246 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
247 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
248 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
249 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
250 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
251 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
252 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
253 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
256 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
260 translate_compare_func(enum pipe_compare_func pipe_func
)
262 static const unsigned map
[] = {
263 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
264 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
265 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
266 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
267 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
268 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
269 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
270 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
272 return map
[pipe_func
];
276 translate_shadow_func(enum pipe_compare_func pipe_func
)
278 /* Gallium specifies the result of shadow comparisons as:
280 * 1 if ref <op> texel,
285 * 0 if texel <op> ref,
288 * So we need to flip the operator and also negate.
290 static const unsigned map
[] = {
291 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
292 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
293 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
294 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
295 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
296 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
297 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
298 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
300 return map
[pipe_func
];
304 translate_cull_mode(unsigned pipe_face
)
306 static const unsigned map
[4] = {
307 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
308 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
309 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
310 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
312 return map
[pipe_face
];
316 translate_fill_mode(unsigned pipe_polymode
)
318 static const unsigned map
[4] = {
319 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
320 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
321 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
322 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
324 return map
[pipe_polymode
];
328 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
330 static const unsigned map
[] = {
331 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
332 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
333 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
335 return map
[pipe_mip
];
339 translate_wrap(unsigned pipe_wrap
)
341 static const unsigned map
[] = {
342 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
343 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
344 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
345 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
346 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
347 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
349 /* These are unsupported. */
350 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
351 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
353 return map
[pipe_wrap
];
356 static struct iris_address
357 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
359 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
360 * validation list at CSO creation time, instead of draw time.
362 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
365 static struct iris_address
366 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
368 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
369 * validation list at CSO creation time, instead of draw time.
371 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
375 * Allocate space for some indirect state.
377 * Return a pointer to the map (to fill it out) and a state ref (for
378 * referring to the state in GPU commands).
381 upload_state(struct u_upload_mgr
*uploader
,
382 struct iris_state_ref
*ref
,
387 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
392 * Stream out temporary/short-lived state.
394 * This allocates space, pins the BO, and includes the BO address in the
395 * returned offset (which works because all state lives in 32-bit memory
399 stream_state(struct iris_batch
*batch
,
400 struct u_upload_mgr
*uploader
,
401 struct pipe_resource
**out_res
,
404 uint32_t *out_offset
)
408 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
410 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
411 iris_use_pinned_bo(batch
, bo
, false);
413 *out_offset
+= iris_bo_offset_from_base_address(bo
);
419 * stream_state() + memcpy.
422 emit_state(struct iris_batch
*batch
,
423 struct u_upload_mgr
*uploader
,
424 struct pipe_resource
**out_res
,
431 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
434 memcpy(map
, data
, size
);
440 * Did field 'x' change between 'old_cso' and 'new_cso'?
442 * (If so, we may want to set some dirty flags.)
444 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
445 #define cso_changed_memcmp(x) \
446 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
449 * Upload the initial GPU state for a render context.
451 * This sets some invariant state that needs to be programmed a particular
452 * way, but we never actually change.
455 iris_init_render_context(struct iris_screen
*screen
,
456 struct iris_batch
*batch
,
457 struct iris_vtable
*vtbl
,
458 struct pipe_debug_callback
*dbg
)
460 iris_init_batch(batch
, screen
, vtbl
, dbg
, I915_EXEC_RENDER
);
462 /* XXX: PIPE_CONTROLs */
464 /* We program STATE_BASE_ADDRESS once at context initialization time.
465 * Each base address points at a 4GB memory zone, and never needs to
466 * change. See iris_bufmgr.h for a description of the memory zones.
468 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
470 // XXX: MOCS is stupid for this.
471 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
472 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
473 sba
.SurfaceStateMemoryObjectControlState
= MOCS_WB
;
474 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
475 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
476 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
477 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
480 sba
.GeneralStateBaseAddressModifyEnable
= true;
481 sba
.SurfaceStateBaseAddressModifyEnable
= true;
482 sba
.DynamicStateBaseAddressModifyEnable
= true;
483 sba
.IndirectObjectBaseAddressModifyEnable
= true;
484 sba
.InstructionBaseAddressModifyEnable
= true;
485 sba
.GeneralStateBufferSizeModifyEnable
= true;
486 sba
.DynamicStateBufferSizeModifyEnable
= true;
487 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
488 sba
.IndirectObjectBufferSizeModifyEnable
= true;
489 sba
.InstructionBuffersizeModifyEnable
= true;
491 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
492 sba
.SurfaceStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SURFACE_START
);
493 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
495 sba
.GeneralStateBufferSize
= 0xfffff;
496 sba
.IndirectObjectBufferSize
= 0xfffff;
497 sba
.InstructionBufferSize
= 0xfffff;
498 sba
.DynamicStateBufferSize
= 0xfffff;
501 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
502 * changing it dynamically. We set it to the maximum size here, and
503 * instead include the render target dimensions in the viewport, so
504 * viewport extents clipping takes care of pruning stray geometry.
506 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
507 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
508 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
511 /* Set the initial MSAA sample positions. */
512 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
513 GEN_SAMPLE_POS_1X(pat
._1xSample
);
514 GEN_SAMPLE_POS_2X(pat
._2xSample
);
515 GEN_SAMPLE_POS_4X(pat
._4xSample
);
516 GEN_SAMPLE_POS_8X(pat
._8xSample
);
517 GEN_SAMPLE_POS_16X(pat
._16xSample
);
520 /* Use the legacy AA line coverage computation. */
521 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
523 /* Disable chromakeying (it's for media) */
524 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
526 /* We want regular rendering, not special HiZ operations. */
527 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
529 /* No polygon stippling offsets are necessary. */
530 // XXX: may need to set an offset for origin-UL framebuffers
531 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
533 /* Set a static partitioning of the push constant area. */
534 // XXX: this may be a bad idea...could starve the push ringbuffers...
535 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
536 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
537 alloc
._3DCommandSubOpcode
= 18 + i
;
538 alloc
.ConstantBufferOffset
= 6 * i
;
539 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
544 struct iris_vertex_buffer_state
{
545 /** The 3DSTATE_VERTEX_BUFFERS hardware packet. */
546 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
548 /** The resource to source vertex data from. */
549 struct pipe_resource
*resources
[33];
551 /** The number of bound vertex buffers. */
552 unsigned num_buffers
;
555 struct iris_depth_buffer_state
{
556 /* Depth/HiZ/Stencil related hardware packets. */
557 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
558 GENX(3DSTATE_STENCIL_BUFFER_length
) +
559 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
560 GENX(3DSTATE_CLEAR_PARAMS_length
)];
564 * Generation-specific context state (ice->state.genx->...).
566 * Most state can go in iris_context directly, but these encode hardware
567 * packets which vary by generation.
569 struct iris_genx_state
{
570 /** SF_CLIP_VIEWPORT */
571 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
) * IRIS_MAX_VIEWPORTS
];
573 struct iris_vertex_buffer_state vertex_buffers
;
574 struct iris_depth_buffer_state depth_buffer
;
576 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
577 uint32_t streamout
[4 * GENX(3DSTATE_STREAMOUT_length
)];
580 // XXX: move this to iris_draw.c
582 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
587 * The pipe->set_blend_color() driver hook.
589 * This corresponds to our COLOR_CALC_STATE.
592 iris_set_blend_color(struct pipe_context
*ctx
,
593 const struct pipe_blend_color
*state
)
595 struct iris_context
*ice
= (struct iris_context
*) ctx
;
597 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
598 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
599 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
603 * Gallium CSO for blend state (see pipe_blend_state).
605 struct iris_blend_state
{
606 /** Partial 3DSTATE_PS_BLEND */
607 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
609 /** Partial BLEND_STATE */
610 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
611 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
613 bool alpha_to_coverage
; /* for shader key */
617 * The pipe->create_blend_state() driver hook.
619 * Translates a pipe_blend_state into iris_blend_state.
622 iris_create_blend_state(struct pipe_context
*ctx
,
623 const struct pipe_blend_state
*state
)
625 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
626 uint32_t *blend_state
= cso
->blend_state
;
628 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
630 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
631 /* pb.HasWriteableRT is filled in at draw time. */
632 /* pb.AlphaTestEnable is filled in at draw time. */
633 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
634 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
636 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
638 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
639 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
640 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
641 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
644 iris_pack_state(GENX(BLEND_STATE
), blend_state
, bs
) {
645 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
646 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
647 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
648 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
649 bs
.ColorDitherEnable
= state
->dither
;
650 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
653 blend_state
+= GENX(BLEND_STATE_length
);
655 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
656 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_state
, be
) {
657 be
.LogicOpEnable
= state
->logicop_enable
;
658 be
.LogicOpFunction
= state
->logicop_func
;
660 be
.PreBlendSourceOnlyClampEnable
= false;
661 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
662 be
.PreBlendColorClampEnable
= true;
663 be
.PostBlendColorClampEnable
= true;
665 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
667 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
668 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
669 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
670 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
671 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
672 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
674 be
.WriteDisableRed
= !(state
->rt
[i
].colormask
& PIPE_MASK_R
);
675 be
.WriteDisableGreen
= !(state
->rt
[i
].colormask
& PIPE_MASK_G
);
676 be
.WriteDisableBlue
= !(state
->rt
[i
].colormask
& PIPE_MASK_B
);
677 be
.WriteDisableAlpha
= !(state
->rt
[i
].colormask
& PIPE_MASK_A
);
679 blend_state
+= GENX(BLEND_STATE_ENTRY_length
);
686 * The pipe->bind_blend_state() driver hook.
688 * Bind a blending CSO and flag related dirty bits.
691 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
693 struct iris_context
*ice
= (struct iris_context
*) ctx
;
694 ice
->state
.cso_blend
= state
;
695 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
696 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
697 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
701 * Gallium CSO for depth, stencil, and alpha testing state.
703 struct iris_depth_stencil_alpha_state
{
704 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
705 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
707 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
708 struct pipe_alpha_state alpha
;
710 /** Outbound to resolve and cache set tracking. */
711 bool depth_writes_enabled
;
712 bool stencil_writes_enabled
;
716 * The pipe->create_depth_stencil_alpha_state() driver hook.
718 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
719 * testing state since we need pieces of it in a variety of places.
722 iris_create_zsa_state(struct pipe_context
*ctx
,
723 const struct pipe_depth_stencil_alpha_state
*state
)
725 struct iris_depth_stencil_alpha_state
*cso
=
726 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
728 bool two_sided_stencil
= state
->stencil
[1].enabled
;
730 cso
->alpha
= state
->alpha
;
731 cso
->depth_writes_enabled
= state
->depth
.writemask
;
732 cso
->stencil_writes_enabled
=
733 state
->stencil
[0].writemask
!= 0 ||
734 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 1);
736 /* The state tracker needs to optimize away EQUAL writes for us. */
737 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
739 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
740 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
741 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
742 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
743 wmds
.StencilTestFunction
=
744 translate_compare_func(state
->stencil
[0].func
);
745 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
746 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
747 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
748 wmds
.BackfaceStencilTestFunction
=
749 translate_compare_func(state
->stencil
[1].func
);
750 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
751 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
752 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
753 wmds
.StencilBufferWriteEnable
=
754 state
->stencil
[0].writemask
!= 0 ||
755 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
756 wmds
.DepthTestEnable
= state
->depth
.enabled
;
757 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
758 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
759 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
760 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
761 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
762 /* wmds.[Backface]StencilReferenceValue are merged later */
769 * The pipe->bind_depth_stencil_alpha_state() driver hook.
771 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
774 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
776 struct iris_context
*ice
= (struct iris_context
*) ctx
;
777 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
778 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
781 if (cso_changed(alpha
.ref_value
))
782 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
784 if (cso_changed(alpha
.enabled
))
785 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
787 if (cso_changed(alpha
.func
))
788 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
790 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
791 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
794 ice
->state
.cso_zsa
= new_cso
;
795 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
796 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
797 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
801 * Gallium CSO for rasterizer state.
803 struct iris_rasterizer_state
{
804 uint32_t sf
[GENX(3DSTATE_SF_length
)];
805 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
806 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
807 uint32_t wm
[GENX(3DSTATE_WM_length
)];
808 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
810 bool clip_halfz
; /* for CC_VIEWPORT */
811 bool depth_clip_near
; /* for CC_VIEWPORT */
812 bool depth_clip_far
; /* for CC_VIEWPORT */
813 bool flatshade
; /* for shader state */
814 bool flatshade_first
; /* for stream output */
815 bool clamp_fragment_color
; /* for shader state */
816 bool light_twoside
; /* for shader state */
817 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
818 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
819 bool line_stipple_enable
;
820 bool poly_stipple_enable
;
822 bool force_persample_interp
;
823 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
824 uint16_t sprite_coord_enable
;
828 * The pipe->create_rasterizer_state() driver hook.
831 iris_create_rasterizer_state(struct pipe_context
*ctx
,
832 const struct pipe_rasterizer_state
*state
)
834 struct iris_rasterizer_state
*cso
=
835 malloc(sizeof(struct iris_rasterizer_state
));
838 point_quad_rasterization
-> SBE
?
843 force_persample_interp
- ?
846 offset_units_unscaled
- cap
not exposed
850 // XXX: it may make more sense just to store the pipe_rasterizer_state,
851 // we're copying a lot of booleans here. But we don't need all of them...
853 cso
->multisample
= state
->multisample
;
854 cso
->force_persample_interp
= state
->force_persample_interp
;
855 cso
->clip_halfz
= state
->clip_halfz
;
856 cso
->depth_clip_near
= state
->depth_clip_near
;
857 cso
->depth_clip_far
= state
->depth_clip_far
;
858 cso
->flatshade
= state
->flatshade
;
859 cso
->flatshade_first
= state
->flatshade_first
;
860 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
861 cso
->light_twoside
= state
->light_twoside
;
862 cso
->rasterizer_discard
= state
->rasterizer_discard
;
863 cso
->half_pixel_center
= state
->half_pixel_center
;
864 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
865 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
866 cso
->line_stipple_enable
= state
->line_stipple_enable
;
867 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
869 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
870 sf
.StatisticsEnable
= true;
871 sf
.ViewportTransformEnable
= true;
872 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
873 sf
.LineEndCapAntialiasingRegionWidth
=
874 state
->line_smooth
? _10pixels
: _05pixels
;
875 sf
.LastPixelEnable
= state
->line_last_pixel
;
876 sf
.LineWidth
= state
->line_width
;
877 sf
.SmoothPointEnable
= state
->point_smooth
;
878 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
879 sf
.PointWidth
= state
->point_size
;
881 if (state
->flatshade_first
) {
882 sf
.TriangleFanProvokingVertexSelect
= 1;
884 sf
.TriangleStripListProvokingVertexSelect
= 2;
885 sf
.TriangleFanProvokingVertexSelect
= 2;
886 sf
.LineStripListProvokingVertexSelect
= 1;
890 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
891 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
892 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
893 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
894 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
895 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
896 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
897 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
898 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
899 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
900 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
901 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
902 rr
.SmoothPointEnable
= state
->point_smooth
;
903 rr
.AntialiasingEnable
= state
->line_smooth
;
904 rr
.ScissorRectangleEnable
= state
->scissor
;
905 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
906 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
907 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
910 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
911 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
912 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
914 cl
.StatisticsEnable
= true;
915 cl
.EarlyCullEnable
= true;
916 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
917 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
918 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
919 cl
.GuardbandClipTestEnable
= true;
920 cl
.ClipMode
= CLIPMODE_NORMAL
;
921 cl
.ClipEnable
= true;
922 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
923 cl
.MinimumPointWidth
= 0.125;
924 cl
.MaximumPointWidth
= 255.875;
926 if (state
->flatshade_first
) {
927 cl
.TriangleFanProvokingVertexSelect
= 1;
929 cl
.TriangleStripListProvokingVertexSelect
= 2;
930 cl
.TriangleFanProvokingVertexSelect
= 2;
931 cl
.LineStripListProvokingVertexSelect
= 1;
935 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
936 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
937 * filled in at draw time from the FS program.
939 wm
.LineAntialiasingRegionWidth
= _10pixels
;
940 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
941 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
942 wm
.StatisticsEnable
= true;
943 wm
.LineStippleEnable
= state
->line_stipple_enable
;
944 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
947 /* Remap from 0..255 back to 1..256 */
948 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
950 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
951 line
.LineStipplePattern
= state
->line_stipple_pattern
;
952 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
953 line
.LineStippleRepeatCount
= line_stipple_factor
;
960 * The pipe->bind_rasterizer_state() driver hook.
962 * Bind a rasterizer CSO and flag related dirty bits.
965 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
967 struct iris_context
*ice
= (struct iris_context
*) ctx
;
968 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
969 struct iris_rasterizer_state
*new_cso
= state
;
972 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
973 if (cso_changed_memcmp(line_stipple
))
974 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
976 if (cso_changed(half_pixel_center
))
977 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
979 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
980 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
982 if (cso_changed(rasterizer_discard
) || cso_changed(flatshade_first
))
983 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
985 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
986 cso_changed(clip_halfz
))
987 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
989 if (cso_changed(sprite_coord_enable
) || cso_changed(light_twoside
))
990 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
993 ice
->state
.cso_rast
= new_cso
;
994 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
995 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
996 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1000 * Return true if the given wrap mode requires the border color to exist.
1002 * (We can skip uploading it if the sampler isn't going to use it.)
1005 wrap_mode_needs_border_color(unsigned wrap_mode
)
1007 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1011 * Gallium CSO for sampler state.
1013 struct iris_sampler_state
{
1014 // XXX: do we need this
1015 struct pipe_sampler_state base
;
1017 bool needs_border_color
;
1019 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1023 * The pipe->create_sampler_state() driver hook.
1025 * We fill out SAMPLER_STATE (except for the border color pointer), and
1026 * store that on the CPU. It doesn't make sense to upload it to a GPU
1027 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1028 * all bound sampler states to be in contiguous memor.
1031 iris_create_sampler_state(struct pipe_context
*ctx
,
1032 const struct pipe_sampler_state
*state
)
1034 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1039 memcpy(&cso
->base
, state
, sizeof(*state
));
1041 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1042 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1044 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1045 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1046 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1048 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1049 wrap_mode_needs_border_color(wrap_t
) ||
1050 wrap_mode_needs_border_color(wrap_r
);
1052 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1053 samp
.TCXAddressControlMode
= wrap_s
;
1054 samp
.TCYAddressControlMode
= wrap_t
;
1055 samp
.TCZAddressControlMode
= wrap_r
;
1056 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1057 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1058 samp
.MinModeFilter
= state
->min_img_filter
;
1059 samp
.MagModeFilter
= state
->mag_img_filter
;
1060 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1061 samp
.MaximumAnisotropy
= RATIO21
;
1063 if (state
->max_anisotropy
>= 2) {
1064 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1065 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1066 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1069 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1070 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1072 samp
.MaximumAnisotropy
=
1073 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1076 /* Set address rounding bits if not using nearest filtering. */
1077 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1078 samp
.UAddressMinFilterRoundingEnable
= true;
1079 samp
.VAddressMinFilterRoundingEnable
= true;
1080 samp
.RAddressMinFilterRoundingEnable
= true;
1083 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1084 samp
.UAddressMagFilterRoundingEnable
= true;
1085 samp
.VAddressMagFilterRoundingEnable
= true;
1086 samp
.RAddressMagFilterRoundingEnable
= true;
1089 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1090 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1092 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1094 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1095 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
1096 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1097 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1099 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1106 * The pipe->bind_sampler_states() driver hook.
1108 * Now that we know all the sampler states, we upload them all into a
1109 * contiguous area of GPU memory, for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1110 * We also fill out the border color state pointers at this point.
1112 * We could defer this work to draw time, but we assume that binding
1113 * will be less frequent than drawing.
1115 // XXX: this may be a bad idea, need to make sure that st/mesa calls us
1116 // XXX: with the complete set of shaders. If it makes multiple calls to
1117 // XXX: things one at a time, we could waste a lot of time assembling things.
1118 // XXX: it doesn't even BUY us anything to do it here, because we only flag
1119 // XXX: IRIS_DIRTY_SAMPLER_STATE when this is called...
1121 iris_bind_sampler_states(struct pipe_context
*ctx
,
1122 enum pipe_shader_type p_stage
,
1123 unsigned start
, unsigned count
,
1126 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1127 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1128 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1130 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1131 shs
->num_samplers
= MAX2(shs
->num_samplers
, start
+ count
);
1133 for (int i
= 0; i
< count
; i
++) {
1134 shs
->samplers
[start
+ i
] = states
[i
];
1137 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1138 * in the dynamic state memory zone, so we can point to it via the
1139 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1141 void *map
= upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
,
1142 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
1146 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1147 shs
->sampler_table
.offset
+=
1148 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1150 /* Make sure all land in the same BO */
1151 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1153 for (int i
= 0; i
< count
; i
++) {
1154 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1157 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1158 } else if (!state
->needs_border_color
) {
1159 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1161 ice
->state
.need_border_colors
= true;
1163 /* Stream out the border color and merge the pointer. */
1165 iris_upload_border_color(ice
, &state
->base
.border_color
);
1167 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1168 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1169 dyns
.BorderColorPointer
= offset
;
1172 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1173 ((uint32_t *) map
)[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1176 map
+= GENX(SAMPLER_STATE_length
);
1179 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1183 * Convert an swizzle enumeration (i.e. PIPE_SWIZZLE_X) to one of the HW's
1184 * "Shader Channel Select" enumerations (i.e. SCS_RED). The mappings are
1186 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
1189 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
1191 * which is simply adding 4 then modding by 8 (or anding with 7).
1193 static enum isl_channel_select
1194 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
1196 return (swizzle
+ 4) & 7;
1200 * The pipe->create_sampler_view() driver hook.
1202 static struct pipe_sampler_view
*
1203 iris_create_sampler_view(struct pipe_context
*ctx
,
1204 struct pipe_resource
*tex
,
1205 const struct pipe_sampler_view
*tmpl
)
1207 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1208 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1209 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
1210 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1215 /* initialize base object */
1217 isv
->base
.context
= ctx
;
1218 isv
->base
.texture
= NULL
;
1219 pipe_reference_init(&isv
->base
.reference
, 1);
1220 pipe_resource_reference(&isv
->base
.texture
, tex
);
1222 void *map
= upload_state(ice
->state
.surface_uploader
, &isv
->surface_state
,
1223 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1227 struct iris_bo
*state_bo
= iris_resource_bo(isv
->surface_state
.res
);
1228 isv
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1230 /* XXX: do we need brw_get_texture_swizzle hacks here? */
1231 isv
->view
= (struct isl_view
) {
1232 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
1233 .swizzle
= (struct isl_swizzle
) {
1234 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
1235 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
1236 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
1237 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
1239 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
1240 (itex
->surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
),
1243 /* Fill out SURFACE_STATE for this view. */
1244 if (tmpl
->target
!= PIPE_BUFFER
) {
1245 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1246 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1247 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1248 isv
->view
.array_len
=
1249 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1251 isl_surf_fill_state(&screen
->isl_dev
, map
,
1252 .surf
= &itex
->surf
, .view
= &isv
->view
,
1254 .address
= itex
->bo
->gtt_offset
);
1256 // .clear_color = clear_color,
1258 // XXX: what to do about isv->view? other drivers don't use it for bufs
1259 const struct isl_format_layout
*fmtl
=
1260 isl_format_get_layout(isv
->view
.format
);
1261 const unsigned cpp
= fmtl
->bpb
/ 8;
1263 isl_buffer_fill_state(&screen
->isl_dev
, map
,
1264 .address
= itex
->bo
->gtt_offset
+
1266 // XXX: buffer_texture_range_size from i965?
1267 .size_B
= tmpl
->u
.buf
.size
,
1268 .format
= isv
->view
.format
,
1277 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1278 struct pipe_sampler_view
*state
)
1280 struct iris_sampler_view
*isv
= (void *) state
;
1281 pipe_resource_reference(&state
->texture
, NULL
);
1282 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1287 * The pipe->create_surface() driver hook.
1289 * In Gallium nomenclature, "surfaces" are a view of a resource that
1290 * can be bound as a render target or depth/stencil buffer.
1292 static struct pipe_surface
*
1293 iris_create_surface(struct pipe_context
*ctx
,
1294 struct pipe_resource
*tex
,
1295 const struct pipe_surface
*tmpl
)
1297 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1298 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1299 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1300 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1301 struct pipe_surface
*psurf
= &surf
->base
;
1302 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1307 pipe_reference_init(&psurf
->reference
, 1);
1308 pipe_resource_reference(&psurf
->texture
, tex
);
1309 psurf
->context
= ctx
;
1310 psurf
->format
= tmpl
->format
;
1311 psurf
->width
= tex
->width0
;
1312 psurf
->height
= tex
->height0
;
1313 psurf
->texture
= tex
;
1314 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1315 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1316 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1318 isl_surf_usage_flags_t usage
= 0;
1320 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1321 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1322 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1324 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1326 enum isl_format isl_format
=
1327 iris_isl_format_for_usage(devinfo
, psurf
->format
, usage
);
1329 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1330 !isl_format_supports_rendering(devinfo
, isl_format
)) {
1331 /* Framebuffer validation will reject this invalid case, but it
1332 * hasn't had the opportunity yet. In the meantime, we need to
1333 * avoid hitting ISL asserts about unsupported formats below.
1339 surf
->view
= (struct isl_view
) {
1340 .format
= isl_format
,
1341 .base_level
= tmpl
->u
.tex
.level
,
1343 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1344 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1345 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1349 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1350 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1351 ISL_SURF_USAGE_STENCIL_BIT
))
1355 void *map
= upload_state(ice
->state
.surface_uploader
, &surf
->surface_state
,
1356 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1360 struct iris_bo
*state_bo
= iris_resource_bo(surf
->surface_state
.res
);
1361 surf
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1363 isl_surf_fill_state(&screen
->isl_dev
, map
,
1364 .surf
= &res
->surf
, .view
= &surf
->view
,
1366 .address
= res
->bo
->gtt_offset
);
1368 // .clear_color = clear_color,
1374 * The pipe->set_sampler_views() driver hook.
1377 iris_set_sampler_views(struct pipe_context
*ctx
,
1378 enum pipe_shader_type p_stage
,
1379 unsigned start
, unsigned count
,
1380 struct pipe_sampler_view
**views
)
1382 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1383 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1384 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1387 for (i
= 0; i
< count
; i
++) {
1388 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1389 &shs
->textures
[i
], views
[i
]);
1391 for (; i
< shs
->num_textures
; i
++) {
1392 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1393 &shs
->textures
[i
], NULL
);
1396 shs
->num_textures
= count
;
1398 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
1402 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1404 struct iris_surface
*surf
= (void *) p_surf
;
1405 pipe_resource_reference(&p_surf
->texture
, NULL
);
1406 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
1410 // XXX: actually implement user clip planes
1412 iris_set_clip_state(struct pipe_context
*ctx
,
1413 const struct pipe_clip_state
*state
)
1418 * The pipe->set_polygon_stipple() driver hook.
1421 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1422 const struct pipe_poly_stipple
*state
)
1424 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1425 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1426 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1430 * The pipe->set_sample_mask() driver hook.
1433 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1435 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1437 /* We only support 16x MSAA, so we have 16 bits of sample maks.
1438 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
1440 ice
->state
.sample_mask
= sample_mask
& 0xffff;
1441 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1445 * The pipe->set_scissor_states() driver hook.
1447 * This corresponds to our SCISSOR_RECT state structures. It's an
1448 * exact match, so we just store them, and memcpy them out later.
1451 iris_set_scissor_states(struct pipe_context
*ctx
,
1452 unsigned start_slot
,
1453 unsigned num_scissors
,
1454 const struct pipe_scissor_state
*states
)
1456 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1458 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1459 ice
->state
.scissors
[start_slot
+ i
] = states
[i
];
1462 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1466 * The pipe->set_stencil_ref() driver hook.
1468 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
1471 iris_set_stencil_ref(struct pipe_context
*ctx
,
1472 const struct pipe_stencil_ref
*state
)
1474 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1475 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1476 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1480 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1482 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1487 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1488 float m00
, float m11
, float m30
, float m31
,
1489 float *xmin
, float *xmax
,
1490 float *ymin
, float *ymax
)
1492 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1493 * Strips and Fans documentation:
1495 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1496 * fixed-point "guardband" range supported by the rasterization hardware"
1500 * "In almost all circumstances, if an object’s vertices are actually
1501 * modified by this clamping (i.e., had X or Y coordinates outside of
1502 * the guardband extent the rendered object will not match the intended
1503 * result. Therefore software should take steps to ensure that this does
1504 * not happen - e.g., by clipping objects such that they do not exceed
1505 * these limits after the Drawing Rectangle is applied."
1507 * I believe the fundamental restriction is that the rasterizer (in
1508 * the SF/WM stages) have a limit on the number of pixels that can be
1509 * rasterized. We need to ensure any coordinates beyond the rasterizer
1510 * limit are handled by the clipper. So effectively that limit becomes
1511 * the clipper's guardband size.
1513 * It goes on to say:
1515 * "In addition, in order to be correctly rendered, objects must have a
1516 * screenspace bounding box not exceeding 8K in the X or Y direction.
1517 * This additional restriction must also be comprehended by software,
1518 * i.e., enforced by use of clipping."
1520 * This makes no sense. Gen7+ hardware supports 16K render targets,
1521 * and you definitely need to be able to draw polygons that fill the
1522 * surface. Our assumption is that the rasterizer was limited to 8K
1523 * on Sandybridge, which only supports 8K surfaces, and it was actually
1524 * increased to 16K on Ivybridge and later.
1526 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1528 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1530 if (m00
!= 0 && m11
!= 0) {
1531 /* First, we compute the screen-space render area */
1532 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1533 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1534 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1535 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1537 /* We want the guardband to be centered on that */
1538 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1539 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1540 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1541 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1543 /* Now we need it in native device coordinates */
1544 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1545 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1546 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1547 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1549 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1550 * flipped upside-down. X should be fine though.
1552 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1553 *xmin
= ndc_gb_xmin
;
1554 *xmax
= ndc_gb_xmax
;
1555 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1556 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1558 /* The viewport scales to 0, so nothing will be rendered. */
1568 * The pipe->set_viewport_states() driver hook.
1570 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
1571 * the guardband yet, as we need the framebuffer dimensions, but we can
1572 * at least fill out the rest.
1575 iris_set_viewport_states(struct pipe_context
*ctx
,
1576 unsigned start_slot
,
1578 const struct pipe_viewport_state
*states
)
1580 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1581 struct iris_genx_state
*genx
= ice
->state
.genx
;
1582 uint32_t *vp_map
= &genx
->sf_cl_vp
[start_slot
];
1584 for (unsigned i
= 0; i
< count
; i
++) {
1585 const struct pipe_viewport_state
*state
= &states
[i
];
1587 memcpy(&ice
->state
.viewports
[start_slot
+ i
], state
, sizeof(*state
));
1589 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
1590 vp
.ViewportMatrixElementm00
= state
->scale
[0];
1591 vp
.ViewportMatrixElementm11
= state
->scale
[1];
1592 vp
.ViewportMatrixElementm22
= state
->scale
[2];
1593 vp
.ViewportMatrixElementm30
= state
->translate
[0];
1594 vp
.ViewportMatrixElementm31
= state
->translate
[1];
1595 vp
.ViewportMatrixElementm32
= state
->translate
[2];
1596 /* XXX: in i965 this is computed based on the drawbuffer size,
1597 * but we don't have that here...
1599 vp
.XMinClipGuardband
= -1.0;
1600 vp
.XMaxClipGuardband
= 1.0;
1601 vp
.YMinClipGuardband
= -1.0;
1602 vp
.YMaxClipGuardband
= 1.0;
1603 vp
.XMinViewPort
= viewport_extent(state
, 0, -1.0f
);
1604 vp
.XMaxViewPort
= viewport_extent(state
, 0, 1.0f
) - 1;
1605 vp
.YMinViewPort
= viewport_extent(state
, 1, -1.0f
);
1606 vp
.YMaxViewPort
= viewport_extent(state
, 1, 1.0f
) - 1;
1609 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
1612 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1614 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
1615 !ice
->state
.cso_rast
->depth_clip_far
))
1616 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1620 * The pipe->set_framebuffer_state() driver hook.
1622 * Sets the current draw FBO, including color render targets, depth,
1623 * and stencil buffers.
1626 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1627 const struct pipe_framebuffer_state
*state
)
1629 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1630 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1631 struct isl_device
*isl_dev
= &screen
->isl_dev
;
1632 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1633 struct iris_resource
*zres
;
1634 struct iris_resource
*stencil_res
;
1636 unsigned samples
= util_framebuffer_get_num_samples(state
);
1638 if (cso
->samples
!= samples
) {
1639 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1642 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
1643 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1646 if ((cso
->layers
== 0) != (state
->layers
== 0)) {
1647 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1650 util_copy_framebuffer_state(cso
, state
);
1651 cso
->samples
= samples
;
1653 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
1655 struct isl_view view
= {
1658 .base_array_layer
= 0,
1660 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1663 struct isl_depth_stencil_hiz_emit_info info
= {
1669 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
1672 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
1673 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
1675 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
1678 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
1680 info
.depth_surf
= &zres
->surf
;
1681 info
.depth_address
= zres
->bo
->gtt_offset
;
1682 info
.hiz_usage
= ISL_AUX_USAGE_NONE
;
1684 view
.format
= zres
->surf
.format
;
1688 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
1689 info
.stencil_surf
= &stencil_res
->surf
;
1690 info
.stencil_address
= stencil_res
->bo
->gtt_offset
;
1692 view
.format
= stencil_res
->surf
.format
;
1696 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
1698 /* Make a null surface for unbound buffers */
1699 void *null_surf_map
=
1700 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
1701 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1702 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(cso
->width
, cso
->height
, cso
->layers
? cso
->layers
: 1));
1704 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
1706 /* Render target change */
1707 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
1709 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
1713 * The pipe->set_constant_buffer() driver hook.
1715 * This uploads any constant data in user buffers, and references
1716 * any UBO resources containing constant data.
1719 iris_set_constant_buffer(struct pipe_context
*ctx
,
1720 enum pipe_shader_type p_stage
, unsigned index
,
1721 const struct pipe_constant_buffer
*input
)
1723 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1724 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1725 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1726 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1727 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
1729 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1730 if (input
->user_buffer
) {
1731 u_upload_data(ctx
->const_uploader
, 0, input
->buffer_size
, 32,
1732 input
->user_buffer
, &cbuf
->data
.offset
,
1735 pipe_resource_reference(&cbuf
->data
.res
, input
->buffer
);
1738 // XXX: these are not retained forever, use a separate uploader?
1740 upload_state(ice
->state
.surface_uploader
, &cbuf
->surface_state
,
1741 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1742 if (!unlikely(map
)) {
1743 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
1747 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
1748 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state
.res
);
1749 cbuf
->surface_state
.offset
+= iris_bo_offset_from_base_address(surf_bo
);
1751 isl_buffer_fill_state(&screen
->isl_dev
, map
,
1752 .address
= res
->bo
->gtt_offset
+ cbuf
->data
.offset
,
1753 .size_B
= input
->buffer_size
,
1754 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
1758 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
1759 pipe_resource_reference(&cbuf
->surface_state
.res
, NULL
);
1762 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
1763 // XXX: maybe not necessary all the time...?
1764 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
1765 // XXX: pull model we may need actual new bindings...
1766 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1770 * The pipe->set_shader_buffers() driver hook.
1772 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
1773 * SURFACE_STATE here, as the buffer offset may change each time.
1776 iris_set_shader_buffers(struct pipe_context
*ctx
,
1777 enum pipe_shader_type p_stage
,
1778 unsigned start_slot
, unsigned count
,
1779 const struct pipe_shader_buffer
*buffers
)
1781 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1782 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1783 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1784 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1786 for (unsigned i
= 0; i
< count
; i
++) {
1787 if (buffers
&& buffers
[i
].buffer
) {
1788 const struct pipe_shader_buffer
*buffer
= &buffers
[i
];
1789 struct iris_resource
*res
= (void *) buffer
->buffer
;
1790 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], &res
->base
);
1792 // XXX: these are not retained forever, use a separate uploader?
1794 upload_state(ice
->state
.surface_uploader
,
1795 &shs
->ssbo_surface_state
[start_slot
+ i
],
1796 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1797 if (!unlikely(map
)) {
1798 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
1802 struct iris_bo
*surf_state_bo
=
1803 iris_resource_bo(shs
->ssbo_surface_state
[start_slot
+ i
].res
);
1804 shs
->ssbo_surface_state
[start_slot
+ i
].offset
+=
1805 iris_bo_offset_from_base_address(surf_state_bo
);
1807 isl_buffer_fill_state(&screen
->isl_dev
, map
,
1809 res
->bo
->gtt_offset
+ buffer
->buffer_offset
,
1810 .size_B
= buffer
->buffer_size
,
1811 .format
= ISL_FORMAT_RAW
,
1815 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
1816 pipe_resource_reference(&shs
->ssbo_surface_state
[start_slot
+ i
].res
,
1821 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1825 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1831 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
1833 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
1834 pipe_resource_reference(&cso
->resources
[i
], NULL
);
1838 * The pipe->set_vertex_buffers() driver hook.
1840 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
1843 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1844 unsigned start_slot
, unsigned count
,
1845 const struct pipe_vertex_buffer
*buffers
)
1847 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1848 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
1850 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
1855 cso
->num_buffers
= count
;
1857 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1858 vb
.DWordLength
= 4 * MAX2(cso
->num_buffers
, 1) - 1;
1861 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1864 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1865 vb
.VertexBufferIndex
= start_slot
;
1866 vb
.NullVertexBuffer
= true;
1867 vb
.AddressModifyEnable
= true;
1871 for (unsigned i
= 0; i
< count
; i
++) {
1872 assert(!buffers
[i
].is_user_buffer
);
1874 pipe_resource_reference(&cso
->resources
[i
], buffers
[i
].buffer
.resource
);
1875 struct iris_resource
*res
= (void *) cso
->resources
[i
];
1877 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1878 vb
.VertexBufferIndex
= start_slot
+ i
;
1880 vb
.AddressModifyEnable
= true;
1881 vb
.BufferPitch
= buffers
[i
].stride
;
1882 vb
.BufferSize
= res
->bo
->size
;
1883 vb
.BufferStartingAddress
=
1884 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffers
[i
].buffer_offset
);
1887 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1890 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1894 * Gallium CSO for vertex elements.
1896 struct iris_vertex_element_state
{
1897 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1898 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
1903 * The pipe->create_vertex_elements() driver hook.
1905 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
1906 * and 3DSTATE_VF_INSTANCING commands. SGVs are handled at draw time.
1909 iris_create_vertex_elements(struct pipe_context
*ctx
,
1911 const struct pipe_vertex_element
*state
)
1913 struct iris_vertex_element_state
*cso
=
1914 malloc(sizeof(struct iris_vertex_element_state
));
1919 * - create edge flag one
1921 * - if those are necessary, use count + 1/2/3... OR in the length
1923 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
1925 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
1928 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1929 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
1932 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1934 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
1935 ve
.Component0Control
= VFCOMP_STORE_0
;
1936 ve
.Component1Control
= VFCOMP_STORE_0
;
1937 ve
.Component2Control
= VFCOMP_STORE_0
;
1938 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
1941 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
1945 for (int i
= 0; i
< count
; i
++) {
1946 enum isl_format isl_format
=
1947 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1948 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
1949 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
1951 switch (isl_format_get_num_channels(isl_format
)) {
1952 case 0: comp
[0] = VFCOMP_STORE_0
;
1953 case 1: comp
[1] = VFCOMP_STORE_0
;
1954 case 2: comp
[2] = VFCOMP_STORE_0
;
1956 comp
[3] = isl_format_has_int_channel(isl_format
) ? VFCOMP_STORE_1_INT
1957 : VFCOMP_STORE_1_FP
;
1960 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1961 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1963 ve
.SourceElementOffset
= state
[i
].src_offset
;
1964 ve
.SourceElementFormat
= isl_format
;
1965 ve
.Component0Control
= comp
[0];
1966 ve
.Component1Control
= comp
[1];
1967 ve
.Component2Control
= comp
[2];
1968 ve
.Component3Control
= comp
[3];
1971 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
1972 vi
.VertexElementIndex
= i
;
1973 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1974 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1977 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1978 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
1985 * The pipe->bind_vertex_elements_state() driver hook.
1988 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
1990 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1991 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
1992 struct iris_vertex_element_state
*new_cso
= state
;
1994 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
1995 * we need to re-emit it to ensure we're overriding the right one.
1997 if (new_cso
&& cso_changed(count
))
1998 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2000 ice
->state
.cso_vertex_elements
= state
;
2001 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2005 iris_create_compute_state(struct pipe_context
*ctx
,
2006 const struct pipe_compute_state
*state
)
2008 // XXX: actually do something
2013 * Gallium CSO for stream output (transform feedback) targets.
2015 struct iris_stream_output_target
{
2016 struct pipe_stream_output_target base
;
2018 uint32_t so_buffer
[GENX(3DSTATE_SO_BUFFER_length
)];
2020 /** Storage holding the offset where we're writing in the buffer */
2021 struct iris_state_ref offset
;
2025 * The pipe->create_stream_output_target() driver hook.
2027 * "Target" here refers to a destination buffer. We translate this into
2028 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2029 * know which buffer this represents, or whether we ought to zero the
2030 * write-offsets, or append. Those are handled in the set() hook.
2032 static struct pipe_stream_output_target
*
2033 iris_create_stream_output_target(struct pipe_context
*ctx
,
2034 struct pipe_resource
*res
,
2035 unsigned buffer_offset
,
2036 unsigned buffer_size
)
2038 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2042 pipe_reference_init(&cso
->base
.reference
, 1);
2043 pipe_resource_reference(&cso
->base
.buffer
, res
);
2044 cso
->base
.buffer_offset
= buffer_offset
;
2045 cso
->base
.buffer_size
= buffer_size
;
2046 cso
->base
.context
= ctx
;
2048 upload_state(ctx
->stream_uploader
, &cso
->offset
, 4, 4);
2050 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), cso
->so_buffer
, sob
) {
2051 sob
.SurfaceBaseAddress
=
2052 rw_bo(NULL
, iris_resource_bo(res
)->gtt_offset
+ buffer_offset
);
2053 sob
.SOBufferEnable
= true;
2054 sob
.StreamOffsetWriteEnable
= true;
2055 sob
.StreamOutputBufferOffsetAddressEnable
= true;
2056 sob
.MOCS
= MOCS_WB
; // XXX: MOCS
2058 sob
.SurfaceSize
= MAX2(buffer_size
/ 4, 1) - 1;
2059 sob
.StreamOutputBufferOffsetAddress
=
2060 rw_bo(NULL
, iris_resource_bo(cso
->offset
.res
)->gtt_offset
+ cso
->offset
.offset
);
2062 /* .SOBufferIndex and .StreamOffset are filled in later */
2069 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2070 struct pipe_stream_output_target
*state
)
2072 struct iris_stream_output_target
*cso
= (void *) state
;
2074 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2075 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2081 * The pipe->set_stream_output_targets() driver hook.
2083 * At this point, we know which targets are bound to a particular index,
2084 * and also whether we want to append or start over. We can finish the
2085 * 3DSTATE_SO_BUFFER packets we started earlier.
2088 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2089 unsigned num_targets
,
2090 struct pipe_stream_output_target
**targets
,
2091 const unsigned *offsets
)
2093 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2094 struct iris_genx_state
*genx
= ice
->state
.genx
;
2095 uint32_t *so_buffers
= genx
->so_buffers
;
2097 const bool active
= num_targets
> 0;
2098 if (ice
->state
.streamout_active
!= active
) {
2099 ice
->state
.streamout_active
= active
;
2100 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2103 for (int i
= 0; i
< 4; i
++) {
2104 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2105 i
< num_targets
? targets
[i
] : NULL
);
2108 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2112 for (unsigned i
= 0; i
< 4; i
++,
2113 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2115 if (i
>= num_targets
|| !targets
[i
]) {
2116 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
2117 sob
.SOBufferIndex
= i
;
2121 /* Note that offsets[i] will either be 0, causing us to zero
2122 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
2123 * "continue appending at the existing offset."
2125 assert(offsets
[i
] == 0 || offsets
[i
] == 0xFFFFFFFF);
2127 uint32_t dynamic
[GENX(3DSTATE_SO_BUFFER_length
)];
2128 iris_pack_state(GENX(3DSTATE_SO_BUFFER
), dynamic
, dyns
) {
2129 dyns
.SOBufferIndex
= i
;
2130 dyns
.StreamOffset
= offsets
[i
];
2133 struct iris_stream_output_target
*tgt
= (void *) targets
[i
];
2134 for (uint32_t j
= 0; j
< GENX(3DSTATE_SO_BUFFER_length
); j
++) {
2135 so_buffers
[j
] = tgt
->so_buffer
[j
] | dynamic
[j
];
2139 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
2143 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
2144 * 3DSTATE_STREAMOUT packets.
2146 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
2147 * hardware to record. We can create it entirely based on the shader, with
2148 * no dynamic state dependencies.
2150 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
2151 * state-based settings. We capture the shader-related ones here, and merge
2152 * the rest in at draw time.
2155 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
2156 const struct brw_vue_map
*vue_map
)
2158 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2159 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2160 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2161 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2163 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2165 memset(so_decl
, 0, sizeof(so_decl
));
2167 /* Construct the list of SO_DECLs to be emitted. The formatting of the
2168 * command feels strange -- each dword pair contains a SO_DECL per stream.
2170 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
2171 const struct pipe_stream_output
*output
= &info
->output
[i
];
2172 const int buffer
= output
->output_buffer
;
2173 const int varying
= output
->register_index
;
2174 const unsigned stream_id
= output
->stream
;
2175 assert(stream_id
< MAX_VERTEX_STREAMS
);
2177 buffer_mask
[stream_id
] |= 1 << buffer
;
2179 assert(vue_map
->varying_to_slot
[varying
] >= 0);
2181 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
2182 * array. Instead, it simply increments DstOffset for the following
2183 * input by the number of components that should be skipped.
2185 * Our hardware is unusual in that it requires us to program SO_DECLs
2186 * for fake "hole" components, rather than simply taking the offset
2187 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
2188 * program as many size = 4 holes as we can, then a final hole to
2189 * accommodate the final 1, 2, or 3 remaining.
2191 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
2193 while (skip_components
> 0) {
2194 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2196 .OutputBufferSlot
= output
->output_buffer
,
2197 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
2199 skip_components
-= 4;
2202 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
2204 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2205 .OutputBufferSlot
= output
->output_buffer
,
2206 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
2208 ((1 << output
->num_components
) - 1) << output
->start_component
,
2211 if (decls
[stream_id
] > max_decls
)
2212 max_decls
= decls
[stream_id
];
2215 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
2216 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
2217 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
2219 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
2220 int urb_entry_read_offset
= 0;
2221 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
2222 urb_entry_read_offset
;
2224 /* We always read the whole vertex. This could be reduced at some
2225 * point by reading less and offsetting the register index in the
2228 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
2229 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
2230 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
2231 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
2232 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
2233 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
2234 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
2235 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
2237 /* Set buffer pitches; 0 means unbound. */
2238 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
2239 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
2240 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
2241 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
2244 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
2245 list
.DWordLength
= 3 + 2 * max_decls
- 2;
2246 list
.StreamtoBufferSelects0
= buffer_mask
[0];
2247 list
.StreamtoBufferSelects1
= buffer_mask
[1];
2248 list
.StreamtoBufferSelects2
= buffer_mask
[2];
2249 list
.StreamtoBufferSelects3
= buffer_mask
[3];
2250 list
.NumEntries0
= decls
[0];
2251 list
.NumEntries1
= decls
[1];
2252 list
.NumEntries2
= decls
[2];
2253 list
.NumEntries3
= decls
[3];
2256 for (int i
= 0; i
< max_decls
; i
++) {
2257 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
2258 entry
.Stream0Decl
= so_decl
[0][i
];
2259 entry
.Stream1Decl
= so_decl
[1][i
];
2260 entry
.Stream2Decl
= so_decl
[2][i
];
2261 entry
.Stream3Decl
= so_decl
[3][i
];
2269 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
2270 const struct brw_vue_map
*last_vue_map
,
2271 bool two_sided_color
,
2272 unsigned *out_offset
,
2273 unsigned *out_length
)
2275 /* The compiler computes the first URB slot without considering COL/BFC
2276 * swizzling (because it doesn't know whether it's enabled), so we need
2277 * to do that here too. This may result in a smaller offset, which
2280 const unsigned first_slot
=
2281 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
2283 /* This becomes the URB read offset (counted in pairs of slots). */
2284 assert(first_slot
% 2 == 0);
2285 *out_offset
= first_slot
/ 2;
2287 /* We need to adjust the inputs read to account for front/back color
2288 * swizzling, as it can make the URB length longer.
2290 for (int c
= 0; c
<= 1; c
++) {
2291 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
2292 /* If two sided color is enabled, the fragment shader's gl_Color
2293 * (COL0) input comes from either the gl_FrontColor (COL0) or
2294 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
2296 if (two_sided_color
)
2297 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2299 /* If front color isn't written, we opt to give them back color
2300 * instead of an undefined value. Switch from COL to BFC.
2302 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
2303 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
2304 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2309 /* Compute the minimum URB Read Length necessary for the FS inputs.
2311 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
2312 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
2314 * "This field should be set to the minimum length required to read the
2315 * maximum source attribute. The maximum source attribute is indicated
2316 * by the maximum value of the enabled Attribute # Source Attribute if
2317 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
2318 * enable is not set.
2319 * read_length = ceiling((max_source_attr + 1) / 2)
2321 * [errata] Corruption/Hang possible if length programmed larger than
2324 * Similar text exists for Ivy Bridge.
2326 * We find the last URB slot that's actually read by the FS.
2328 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
2329 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
2330 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
2333 /* The URB read length is the difference of the two, counted in pairs. */
2334 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
2338 iris_emit_sbe_swiz(struct iris_batch
*batch
,
2339 const struct iris_context
*ice
,
2340 unsigned urb_read_offset
,
2341 unsigned sprite_coord_enables
)
2343 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
2344 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2345 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2346 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
2347 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2349 /* XXX: this should be generated when putting programs in place */
2351 // XXX: raster->sprite_coord_enable
2353 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
2354 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
2355 if (input_index
< 0 || input_index
>= 16)
2358 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
2359 &attr_overrides
[input_index
];
2361 /* Viewport and Layer are stored in the VUE header. We need to override
2362 * them to zero if earlier stages didn't write them, as GL requires that
2363 * they read back as zero when not explicitly set.
2366 case VARYING_SLOT_VIEWPORT
:
2367 case VARYING_SLOT_LAYER
:
2368 attr
->ComponentOverrideX
= true;
2369 attr
->ComponentOverrideW
= true;
2370 attr
->ConstantSource
= CONST_0000
;
2372 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
2373 attr
->ComponentOverrideY
= true;
2374 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
2375 attr
->ComponentOverrideZ
= true;
2378 case VARYING_SLOT_PRIMITIVE_ID
:
2379 attr
->ComponentOverrideX
= true;
2380 attr
->ComponentOverrideY
= true;
2381 attr
->ComponentOverrideZ
= true;
2382 attr
->ComponentOverrideW
= true;
2383 attr
->ConstantSource
= PRIM_ID
;
2390 if (sprite_coord_enables
& (1 << input_index
))
2393 int slot
= vue_map
->varying_to_slot
[fs_attr
];
2395 /* If there was only a back color written but not front, use back
2396 * as the color instead of undefined.
2398 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
2399 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
2400 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
2401 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
2403 /* Not written by the previous stage - undefined. */
2405 attr
->ComponentOverrideX
= true;
2406 attr
->ComponentOverrideY
= true;
2407 attr
->ComponentOverrideZ
= true;
2408 attr
->ComponentOverrideW
= true;
2409 attr
->ConstantSource
= CONST_0001_FLOAT
;
2413 /* Compute the location of the attribute relative to the read offset,
2414 * which is counted in 256-bit increments (two 128-bit VUE slots).
2416 const int source_attr
= slot
- 2 * urb_read_offset
;
2417 assert(source_attr
>= 0 && source_attr
<= 32);
2418 attr
->SourceAttribute
= source_attr
;
2420 /* If we are doing two-sided color, and the VUE slot following this one
2421 * represents a back-facing color, then we need to instruct the SF unit
2422 * to do back-facing swizzling.
2424 if (cso_rast
->light_twoside
&&
2425 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
2426 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
2427 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
2428 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
2429 attr
->SwizzleSelect
= INPUTATTR_FACING
;
2432 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
2433 for (int i
= 0; i
< 16; i
++)
2434 sbes
.Attribute
[i
] = attr_overrides
[i
];
2439 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
2440 const struct iris_rasterizer_state
*cso
)
2442 unsigned overrides
= 0;
2444 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
2445 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
2447 for (int i
= 0; i
< 8; i
++) {
2448 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
2449 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
2450 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
2457 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
2459 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2460 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2461 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2462 const struct shader_info
*fs_info
=
2463 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
2465 unsigned urb_read_offset
, urb_read_length
;
2466 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
2467 ice
->shaders
.last_vue_map
,
2468 cso_rast
->light_twoside
,
2469 &urb_read_offset
, &urb_read_length
);
2471 unsigned sprite_coord_overrides
=
2472 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
2474 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
2475 sbe
.AttributeSwizzleEnable
= true;
2476 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2477 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
2478 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
2479 sbe
.VertexURBEntryReadLength
= urb_read_length
;
2480 sbe
.ForceVertexURBEntryReadOffset
= true;
2481 sbe
.ForceVertexURBEntryReadLength
= true;
2482 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
2483 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
2485 for (int i
= 0; i
< 32; i
++) {
2486 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
2490 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
2494 iris_bind_compute_state(struct pipe_context
*ctx
, void *state
)
2496 // XXX: do something
2499 /* ------------------------------------------------------------------- */
2502 * Set sampler-related program key fields based on the current state.
2505 iris_populate_sampler_key(const struct iris_context
*ice
,
2506 struct brw_sampler_prog_key_data
*key
)
2508 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
2509 key
->swizzles
[i
] = 0x688; /* XYZW */
2514 * Populate VS program key fields based on the current state.
2517 iris_populate_vs_key(const struct iris_context
*ice
,
2518 struct brw_vs_prog_key
*key
)
2520 iris_populate_sampler_key(ice
, &key
->tex
);
2524 * Populate TCS program key fields based on the current state.
2527 iris_populate_tcs_key(const struct iris_context
*ice
,
2528 struct brw_tcs_prog_key
*key
)
2530 iris_populate_sampler_key(ice
, &key
->tex
);
2534 * Populate TES program key fields based on the current state.
2537 iris_populate_tes_key(const struct iris_context
*ice
,
2538 struct brw_tes_prog_key
*key
)
2540 iris_populate_sampler_key(ice
, &key
->tex
);
2544 * Populate GS program key fields based on the current state.
2547 iris_populate_gs_key(const struct iris_context
*ice
,
2548 struct brw_gs_prog_key
*key
)
2550 iris_populate_sampler_key(ice
, &key
->tex
);
2554 * Populate FS program key fields based on the current state.
2557 iris_populate_fs_key(const struct iris_context
*ice
,
2558 struct brw_wm_prog_key
*key
)
2560 iris_populate_sampler_key(ice
, &key
->tex
);
2562 /* XXX: dirty flags? */
2563 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
2564 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
2565 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
2566 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
2568 key
->nr_color_regions
= fb
->nr_cbufs
;
2570 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
2572 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
2573 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
2575 /* XXX: only bother if COL0/1 are read */
2576 key
->flat_shade
= rast
->flatshade
;
2578 key
->persample_interp
= rast
->force_persample_interp
;
2579 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
2581 key
->coherent_fb_fetch
= true;
2583 // XXX: uint64_t input_slots_valid; - for >16 inputs
2585 // XXX: key->force_dual_color_blend for unigine
2586 // XXX: respect hint for high_quality_derivatives:1;
2590 // XXX: these need to go in INIT_THREAD_DISPATCH_FIELDS
2591 pkt
.SamplerCount
= \
2592 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4); \
2593 pkt
.PerThreadScratchSpace
= prog_data
->total_scratch
== 0 ? 0 : \
2594 ffs(stage_state
->per_thread_scratch
) - 11; \
2599 KSP(const struct iris_compiled_shader
*shader
)
2601 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
2602 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
2605 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2606 pkt.KernelStartPointer = KSP(shader); \
2607 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
2608 pkt.FloatingPointMode = prog_data->use_alt_mode; \
2610 pkt.DispatchGRFStartRegisterForURBData = \
2611 prog_data->dispatch_grf_start_reg; \
2612 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2613 pkt.prefix##URBEntryReadOffset = 0; \
2615 pkt.StatisticsEnable = true; \
2619 * Encode most of 3DSTATE_VS based on the compiled shader.
2622 iris_store_vs_state(const struct gen_device_info
*devinfo
,
2623 struct iris_compiled_shader
*shader
)
2625 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2626 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2628 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
2629 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2630 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2631 vs
.SIMD8DispatchEnable
= true;
2632 vs
.UserClipDistanceCullTestEnableBitmask
=
2633 vue_prog_data
->cull_distance_mask
;
2638 * Encode most of 3DSTATE_HS based on the compiled shader.
2641 iris_store_tcs_state(const struct gen_device_info
*devinfo
,
2642 struct iris_compiled_shader
*shader
)
2644 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2645 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2646 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
2648 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
2649 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
2651 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
2652 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
2653 hs
.IncludeVertexHandles
= true;
2658 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
2661 iris_store_tes_state(const struct gen_device_info
*devinfo
,
2662 struct iris_compiled_shader
*shader
)
2664 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2665 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2666 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
2668 uint32_t *te_state
= (void *) shader
->derived_data
;
2669 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
2671 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
2672 te
.Partitioning
= tes_prog_data
->partitioning
;
2673 te
.OutputTopology
= tes_prog_data
->output_topology
;
2674 te
.TEDomain
= tes_prog_data
->domain
;
2676 te
.MaximumTessellationFactorOdd
= 63.0;
2677 te
.MaximumTessellationFactorNotOdd
= 64.0;
2680 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
2681 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
2683 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
2684 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
2685 ds
.ComputeWCoordinateEnable
=
2686 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
2688 ds
.UserClipDistanceCullTestEnableBitmask
=
2689 vue_prog_data
->cull_distance_mask
;
2695 * Encode most of 3DSTATE_GS based on the compiled shader.
2698 iris_store_gs_state(const struct gen_device_info
*devinfo
,
2699 struct iris_compiled_shader
*shader
)
2701 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2702 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2703 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
2705 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
2706 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2708 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2709 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2710 gs
.ControlDataHeaderSize
=
2711 gs_prog_data
->control_data_header_size_hwords
;
2712 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2713 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
2714 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2715 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2716 gs
.ReorderMode
= TRAILING
;
2717 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2718 gs
.MaximumNumberofThreads
=
2719 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2720 : (devinfo
->max_gs_threads
- 1);
2722 if (gs_prog_data
->static_vertex_count
!= -1) {
2723 gs
.StaticOutput
= true;
2724 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2726 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2728 gs
.UserClipDistanceCullTestEnableBitmask
=
2729 vue_prog_data
->cull_distance_mask
;
2731 const int urb_entry_write_offset
= 1;
2732 const uint32_t urb_entry_output_length
=
2733 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2734 urb_entry_write_offset
;
2736 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2737 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2742 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
2745 iris_store_fs_state(const struct gen_device_info
*devinfo
,
2746 struct iris_compiled_shader
*shader
)
2748 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2749 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
2751 uint32_t *ps_state
= (void *) shader
->derived_data
;
2752 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
2754 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
2755 ps
.VectorMaskEnable
= true;
2756 //ps.SamplerCount = ...
2757 ps
.BindingTableEntryCount
= prog_data
->binding_table
.size_bytes
/ 4;
2758 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
2759 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
2761 ps
.PushConstantEnable
= prog_data
->nr_params
> 0 ||
2762 prog_data
->ubo_ranges
[0].length
> 0;
2764 /* From the documentation for this packet:
2765 * "If the PS kernel does not need the Position XY Offsets to
2766 * compute a Position Value, then this field should be programmed
2767 * to POSOFFSET_NONE."
2769 * "SW Recommendation: If the PS kernel needs the Position Offsets
2770 * to compute a Position XY value, this field should match Position
2771 * ZW Interpolation Mode to ensure a consistent position.xyzw
2774 * We only require XY sample offsets. So, this recommendation doesn't
2775 * look useful at the moment. We might need this in future.
2777 ps
.PositionXYOffsetSelect
=
2778 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
2779 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
2780 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
2781 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
2783 // XXX: Disable SIMD32 with 16x MSAA
2785 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
2786 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
2787 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
2788 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
2789 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
2790 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
2792 ps
.KernelStartPointer0
=
2793 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
2794 ps
.KernelStartPointer1
=
2795 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
2796 ps
.KernelStartPointer2
=
2797 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
2800 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
2801 psx
.PixelShaderValid
= true;
2802 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
2803 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
2804 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
2805 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
2806 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
2807 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
2809 if (wm_prog_data
->uses_sample_mask
) {
2810 /* TODO: conservative rasterization */
2811 if (wm_prog_data
->post_depth_coverage
)
2812 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
2814 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
2817 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
2818 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
2819 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
2826 * Compute the size of the derived data (shader command packets).
2828 * This must match the data written by the iris_store_xs_state() functions.
2831 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
2833 assert(cache_id
<= IRIS_CACHE_BLORP
);
2835 static const unsigned dwords
[] = {
2836 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
2837 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
2838 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
2839 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
2841 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
2842 [IRIS_CACHE_CS
] = 0,
2843 [IRIS_CACHE_BLORP
] = 0,
2846 return sizeof(uint32_t) * dwords
[cache_id
];
2850 * Create any state packets corresponding to the given shader stage
2851 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
2852 * This means that we can look up a program in the in-memory cache and
2853 * get most of the state packet without having to reconstruct it.
2856 iris_store_derived_program_state(const struct gen_device_info
*devinfo
,
2857 enum iris_program_cache_id cache_id
,
2858 struct iris_compiled_shader
*shader
)
2862 iris_store_vs_state(devinfo
, shader
);
2864 case IRIS_CACHE_TCS
:
2865 iris_store_tcs_state(devinfo
, shader
);
2867 case IRIS_CACHE_TES
:
2868 iris_store_tes_state(devinfo
, shader
);
2871 iris_store_gs_state(devinfo
, shader
);
2874 iris_store_fs_state(devinfo
, shader
);
2877 case IRIS_CACHE_BLORP
:
2884 /* ------------------------------------------------------------------- */
2887 * Configure the URB.
2889 * XXX: write a real comment.
2892 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
2894 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
2895 const unsigned push_size_kB
= 32;
2896 unsigned entries
[4];
2900 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2901 if (!ice
->shaders
.prog
[i
]) {
2904 struct brw_vue_prog_data
*vue_prog_data
=
2905 (void *) ice
->shaders
.prog
[i
]->prog_data
;
2906 size
[i
] = vue_prog_data
->urb_entry_size
;
2908 assert(size
[i
] != 0);
2911 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
2912 1024 * ice
->shaders
.urb_size
,
2913 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
2914 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
2915 size
, entries
, start
);
2917 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2918 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
2919 urb
._3DCommandSubOpcode
+= i
;
2920 urb
.VSURBStartingAddress
= start
[i
];
2921 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
2922 urb
.VSNumberofURBEntries
= entries
[i
];
2927 static const uint32_t push_constant_opcodes
[] = {
2928 [MESA_SHADER_VERTEX
] = 21,
2929 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2930 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2931 [MESA_SHADER_GEOMETRY
] = 22,
2932 [MESA_SHADER_FRAGMENT
] = 23,
2933 [MESA_SHADER_COMPUTE
] = 0,
2937 * Add a surface to the validation list, as well as the buffer containing
2938 * the corresponding SURFACE_STATE.
2940 * Returns the binding table entry (offset to SURFACE_STATE).
2943 use_surface(struct iris_batch
*batch
,
2944 struct pipe_surface
*p_surf
,
2947 struct iris_surface
*surf
= (void *) p_surf
;
2949 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
2950 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
2952 return surf
->surface_state
.offset
;
2956 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
2958 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->base
.texture
), false);
2959 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
2961 return isv
->surface_state
.offset
;
2965 use_const_buffer(struct iris_batch
*batch
, struct iris_const_buffer
*cbuf
)
2967 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->data
.res
), false);
2968 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->surface_state
.res
), false);
2970 return cbuf
->surface_state
.offset
;
2974 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
2976 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
2978 iris_use_pinned_bo(batch
, state_bo
, false);
2980 return ice
->state
.unbound_tex
.offset
;
2984 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
2986 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
2988 iris_use_pinned_bo(batch
, state_bo
, false);
2990 return ice
->state
.null_fb
.offset
;
2994 use_ssbo(struct iris_batch
*batch
, struct iris_context
*ice
,
2995 struct iris_shader_state
*shs
, int i
)
2998 return use_null_surface(batch
, ice
);
3000 struct iris_state_ref
*surf_state
= &shs
->ssbo_surface_state
[i
];
3002 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->ssbo
[i
]), true);
3003 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3005 return surf_state
->offset
;
3009 * Populate the binding table for a given shader stage.
3011 * This fills out the table of pointers to surfaces required by the shader,
3012 * and also adds those buffers to the validation list so the kernel can make
3013 * resident before running our batch.
3016 iris_populate_binding_table(struct iris_context
*ice
,
3017 struct iris_batch
*batch
,
3018 gl_shader_stage stage
)
3020 const struct iris_binder
*binder
= &batch
->binder
;
3021 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3025 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
3026 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3028 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
3029 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
3032 if (stage
== MESA_SHADER_FRAGMENT
) {
3033 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3034 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
3035 if (cso_fb
->nr_cbufs
) {
3036 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
3037 if (cso_fb
->cbufs
[i
])
3038 bt_map
[s
++] = use_surface(batch
, cso_fb
->cbufs
[i
], true);
3040 bt_map
[s
++] = use_null_fb_surface(batch
, ice
);
3043 bt_map
[s
++] = use_null_fb_surface(batch
, ice
);
3047 //assert(prog_data->binding_table.texture_start ==
3048 //(ice->state.num_textures[stage] ? s : 0xd0d0d0d0));
3050 for (int i
= 0; i
< shs
->num_textures
; i
++) {
3051 struct iris_sampler_view
*view
= shs
->textures
[i
];
3052 bt_map
[s
++] = view
? use_sampler_view(batch
, view
)
3053 : use_null_surface(batch
, ice
);
3056 for (int i
= 0; i
< 1 + info
->num_ubos
; i
++) {
3057 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[i
];
3058 if (!cbuf
->surface_state
.res
)
3061 bt_map
[s
++] = use_const_buffer(batch
, cbuf
);
3064 /* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
3065 * for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
3066 * in st_atom_storagebuf.c so it'll compact them into one range, with
3067 * SSBOs starting at info->num_abos. Ideally it'd reset num_abos to 0 too
3069 if (info
->num_abos
+ info
->num_ssbos
> 0) {
3070 for (int i
= 0; i
< IRIS_MAX_ABOS
+ info
->num_ssbos
; i
++) {
3071 bt_map
[s
++] = use_ssbo(batch
, ice
, shs
, i
);
3076 // XXX: not implemented yet
3077 assert(prog_data
->binding_table
.image_start
== 0xd0d0d0d0);
3078 assert(prog_data
->binding_table
.plane_start
[1] == 0xd0d0d0d0);
3079 assert(prog_data
->binding_table
.plane_start
[2] == 0xd0d0d0d0);
3084 iris_use_optional_res(struct iris_batch
*batch
,
3085 struct pipe_resource
*res
,
3089 struct iris_bo
*bo
= iris_resource_bo(res
);
3090 iris_use_pinned_bo(batch
, bo
, writeable
);
3094 /* ------------------------------------------------------------------- */
3097 * Pin any BOs which were installed by a previous batch, and restored
3098 * via the hardware logical context mechanism.
3100 * We don't need to re-emit all state every batch - the hardware context
3101 * mechanism will save and restore it for us. This includes pointers to
3102 * various BOs...which won't exist unless we ask the kernel to pin them
3103 * by adding them to the validation list.
3105 * We can skip buffers if we've re-emitted those packets, as we're
3106 * overwriting those stale pointers with new ones, and don't actually
3107 * refer to the old BOs.
3110 iris_restore_context_saved_bos(struct iris_context
*ice
,
3111 struct iris_batch
*batch
,
3112 const struct pipe_draw_info
*draw
)
3114 // XXX: whack IRIS_SHADER_DIRTY_BINDING_TABLE on new batch
3116 const uint64_t clean
= ~ice
->state
.dirty
;
3118 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
3119 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
3122 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3123 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
3126 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
3127 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
3130 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3131 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
3134 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
3135 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
3138 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3139 if (clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
))
3142 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3143 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3148 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3150 for (int i
= 0; i
< 4; i
++) {
3151 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3153 if (range
->length
== 0)
3156 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3157 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3160 iris_use_pinned_bo(batch
, res
->bo
, false);
3162 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3166 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3167 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3168 struct pipe_resource
*res
= shs
->sampler_table
.res
;
3170 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3173 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3174 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
3175 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3177 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3178 iris_use_pinned_bo(batch
, bo
, false);
3181 // XXX: scratch buffer
3185 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
3186 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3188 if (cso_fb
->zsbuf
) {
3189 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
3190 // XXX: depth might not be writable...
3191 iris_use_pinned_bo(batch
, zres
->bo
, true);
3195 if (draw
->index_size
> 0) {
3196 // XXX: index buffer
3199 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
3200 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
3201 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
3202 struct iris_resource
*res
= (void *) cso
->resources
[i
];
3203 iris_use_pinned_bo(batch
, res
->bo
, false);
3209 iris_upload_render_state(struct iris_context
*ice
,
3210 struct iris_batch
*batch
,
3211 const struct pipe_draw_info
*draw
)
3213 const uint64_t dirty
= ice
->state
.dirty
;
3215 struct iris_genx_state
*genx
= ice
->state
.genx
;
3216 struct brw_wm_prog_data
*wm_prog_data
= (void *)
3217 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3219 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
3220 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3221 uint32_t cc_vp_address
;
3223 /* XXX: could avoid streaming for depth_clip [0,1] case. */
3224 uint32_t *cc_vp_map
=
3225 stream_state(batch
, ice
->state
.dynamic_uploader
,
3226 &ice
->state
.last_res
.cc_vp
,
3227 4 * ice
->state
.num_viewports
*
3228 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
3229 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
3231 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
3232 cso_rast
->clip_halfz
, &zmin
, &zmax
);
3233 if (cso_rast
->depth_clip_near
)
3235 if (cso_rast
->depth_clip_far
)
3238 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
3239 ccv
.MinimumDepth
= zmin
;
3240 ccv
.MaximumDepth
= zmax
;
3243 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
3246 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
3247 ptr
.CCViewportPointer
= cc_vp_address
;
3251 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3252 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
3253 ptr
.SFClipViewportPointer
=
3254 emit_state(batch
, ice
->state
.dynamic_uploader
,
3255 &ice
->state
.last_res
.sf_cl_vp
,
3256 genx
->sf_cl_vp
, 4 * GENX(SF_CLIP_VIEWPORT_length
) *
3257 ice
->state
.num_viewports
, 64);
3263 // XXX: this is only flagged at setup, we assume a static configuration
3264 if (dirty
& IRIS_DIRTY_URB
) {
3265 iris_upload_urb_config(ice
, batch
);
3268 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
3269 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
3270 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3271 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
3272 const int num_dwords
= 4 * (GENX(BLEND_STATE_length
) +
3273 cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
));
3274 uint32_t blend_offset
;
3275 uint32_t *blend_map
=
3276 stream_state(batch
, ice
->state
.dynamic_uploader
,
3277 &ice
->state
.last_res
.blend
,
3278 4 * num_dwords
, 64, &blend_offset
);
3280 uint32_t blend_state_header
;
3281 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
3282 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
3283 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
3286 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
3287 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1],
3288 sizeof(cso_blend
->blend_state
) - sizeof(uint32_t));
3290 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
3291 ptr
.BlendStatePointer
= blend_offset
;
3292 ptr
.BlendStatePointerValid
= true;
3296 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3297 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
3300 stream_state(batch
, ice
->state
.dynamic_uploader
,
3301 &ice
->state
.last_res
.color_calc
,
3302 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
3304 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
3305 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
3306 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
3307 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
3308 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
3309 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
3310 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
3312 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3313 ptr
.ColorCalcStatePointer
= cc_offset
;
3314 ptr
.ColorCalcStatePointerValid
= true;
3318 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3319 // XXX: wrong dirty tracking...
3320 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
3323 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3324 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3329 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3331 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3332 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3334 /* The Skylake PRM contains the following restriction:
3336 * "The driver must ensure The following case does not occur
3337 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3338 * buffer 3 read length equal to zero committed followed by a
3339 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3342 * To avoid this, we program the buffers in the highest slots.
3343 * This way, slot 0 is only used if slot 3 is also used.
3347 for (int i
= 3; i
>= 0; i
--) {
3348 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3350 if (range
->length
== 0)
3353 // XXX: is range->block a constbuf index? it would be nice
3354 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3355 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3357 assert(cbuf
->data
.offset
% 32 == 0);
3359 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3360 pkt
.ConstantBody
.Buffer
[n
] =
3361 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->data
.offset
)
3362 : ro_bo(batch
->screen
->workaround_bo
, 0);
3369 struct iris_binder
*binder
= &batch
->binder
;
3371 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3372 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
3373 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
3374 ptr
._3DCommandSubOpcode
= 38 + stage
;
3375 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
3380 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3381 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
3382 iris_populate_binding_table(ice
, batch
, stage
);
3386 if (ice
->state
.need_border_colors
)
3387 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
3389 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3390 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
3391 !ice
->shaders
.prog
[stage
])
3394 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3395 struct pipe_resource
*res
= shs
->sampler_table
.res
;
3397 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3399 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
3400 ptr
._3DCommandSubOpcode
= 43 + stage
;
3401 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
3405 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
3406 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
3408 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
3409 if (ice
->state
.framebuffer
.samples
> 0)
3410 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
3414 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
3415 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
3416 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
3420 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3421 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
3424 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3427 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
3428 iris_use_pinned_bo(batch
, cache
->bo
, false);
3429 iris_batch_emit(batch
, shader
->derived_data
,
3430 iris_derived_program_state_size(stage
));
3432 if (stage
== MESA_SHADER_TESS_EVAL
) {
3433 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
3434 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
3435 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
3436 } else if (stage
== MESA_SHADER_GEOMETRY
) {
3437 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
3442 if (ice
->state
.streamout_active
) {
3443 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
3444 iris_batch_emit(batch
, genx
->so_buffers
,
3445 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
3446 for (int i
= 0; i
< 4; i
++) {
3447 struct iris_stream_output_target
*tgt
=
3448 (void *) ice
->state
.so_target
[i
];
3450 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
3452 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
3458 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
3459 uint32_t *decl_list
=
3460 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
3461 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
3464 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
3465 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3467 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
3468 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
3469 sol
.SOFunctionEnable
= true;
3470 sol
.SOStatisticsEnable
= true;
3472 // XXX: GL_PRIMITIVES_GENERATED query
3473 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
;
3474 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
3477 assert(ice
->state
.streamout
);
3479 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
3480 GENX(3DSTATE_STREAMOUT_length
));
3483 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
3484 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
3488 if (dirty
& IRIS_DIRTY_CLIP
) {
3489 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3490 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3492 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
3493 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
3494 if (wm_prog_data
->barycentric_interp_modes
&
3495 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
3496 cl
.NonPerspectiveBarycentricEnable
= true;
3498 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
3499 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
3501 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
3502 ARRAY_SIZE(cso_rast
->clip
));
3505 if (dirty
& IRIS_DIRTY_RASTER
) {
3506 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
3507 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
3508 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
3512 /* XXX: FS program updates needs to flag IRIS_DIRTY_WM */
3513 if (dirty
& IRIS_DIRTY_WM
) {
3514 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
3515 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
3517 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
3518 wm
.BarycentricInterpolationMode
=
3519 wm_prog_data
->barycentric_interp_modes
;
3521 if (wm_prog_data
->early_fragment_tests
)
3522 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
3523 else if (wm_prog_data
->has_side_effects
)
3524 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
3526 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
3529 if (dirty
& IRIS_DIRTY_SBE
) {
3530 iris_emit_sbe(batch
, ice
);
3533 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
3534 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
3535 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
3536 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
3537 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
3538 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
3539 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
3542 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
3543 ARRAY_SIZE(cso_blend
->ps_blend
));
3546 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
3547 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
3548 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
3550 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
3551 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
3552 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
3553 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
3555 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
3558 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
3559 uint32_t scissor_offset
=
3560 emit_state(batch
, ice
->state
.dynamic_uploader
,
3561 &ice
->state
.last_res
.scissor
,
3562 ice
->state
.scissors
,
3563 sizeof(struct pipe_scissor_state
) *
3564 ice
->state
.num_viewports
, 32);
3566 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
3567 ptr
.ScissorRectPointer
= scissor_offset
;
3571 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
3572 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3573 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
3575 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
3577 if (cso_fb
->zsbuf
) {
3578 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
3579 // XXX: depth might not be writable...
3580 iris_use_pinned_bo(batch
, zres
->bo
, true);
3584 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
3585 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
3586 for (int i
= 0; i
< 32; i
++) {
3587 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
3592 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
3593 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
3594 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
3598 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
3599 topo
.PrimitiveTopologyType
=
3600 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
3604 if (draw
->index_size
> 0) {
3605 struct iris_resource
*res
= NULL
;
3608 if (draw
->has_user_indices
) {
3609 u_upload_data(ice
->ctx
.stream_uploader
, 0,
3610 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
3611 &offset
, (struct pipe_resource
**) &res
);
3613 res
= (struct iris_resource
*) draw
->index
.resource
;
3617 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
3618 ib
.IndexFormat
= draw
->index_size
>> 1;
3620 ib
.BufferSize
= res
->bo
->size
;
3621 ib
.BufferStartingAddress
= ro_bo(res
->bo
, offset
);
3625 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
3626 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
3627 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
3629 if (cso
->num_buffers
> 0) {
3630 iris_batch_emit(batch
, cso
->vertex_buffers
, sizeof(uint32_t) *
3631 (1 + vb_dwords
* cso
->num_buffers
));
3633 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
3634 struct iris_resource
*res
= (void *) cso
->resources
[i
];
3635 iris_use_pinned_bo(batch
, res
->bo
, false);
3640 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
3641 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
3642 const unsigned entries
= MAX2(cso
->count
, 1);
3643 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
3644 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
3645 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
3646 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
3649 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
3650 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
3651 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
3652 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
3654 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
3655 if (vs_prog_data
->uses_vertexid
) {
3656 sgv
.VertexIDEnable
= true;
3657 sgv
.VertexIDComponentNumber
= 2;
3658 sgv
.VertexIDElementOffset
= cso
->count
;
3661 if (vs_prog_data
->uses_instanceid
) {
3662 sgv
.InstanceIDEnable
= true;
3663 sgv
.InstanceIDComponentNumber
= 3;
3664 sgv
.InstanceIDElementOffset
= cso
->count
;
3670 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
3671 if (draw
->primitive_restart
) {
3672 vf
.IndexedDrawCutIndexEnable
= true;
3673 vf
.CutIndex
= draw
->restart_index
;
3678 // XXX: Gen8 - PMA fix
3680 #define _3DPRIM_END_OFFSET 0x2420
3681 #define _3DPRIM_START_VERTEX 0x2430
3682 #define _3DPRIM_VERTEX_COUNT 0x2434
3683 #define _3DPRIM_INSTANCE_COUNT 0x2438
3684 #define _3DPRIM_START_INSTANCE 0x243C
3685 #define _3DPRIM_BASE_VERTEX 0x2440
3687 if (draw
->indirect
) {
3688 /* We don't support this MultidrawIndirect. */
3689 assert(!draw
->indirect
->indirect_draw_count
);
3691 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
3694 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3695 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
3696 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
3698 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3699 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
3700 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
3702 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3703 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
3704 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
3706 if (draw
->index_size
) {
3707 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3708 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
3709 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
3711 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3712 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
3713 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
3716 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3717 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
3718 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
3720 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3721 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
3727 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
3728 prim
.StartInstanceLocation
= draw
->start_instance
;
3729 prim
.InstanceCount
= draw
->instance_count
;
3730 prim
.VertexCountPerInstance
= draw
->count
;
3731 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
3733 // XXX: this is probably bonkers.
3734 prim
.StartVertexLocation
= draw
->start
;
3736 prim
.IndirectParameterEnable
= draw
->indirect
!= NULL
;
3738 if (draw
->index_size
) {
3739 prim
.BaseVertexLocation
+= draw
->index_bias
;
3741 prim
.StartVertexLocation
+= draw
->index_bias
;
3744 //prim.BaseVertexLocation = ...;
3747 if (!batch
->contains_draw
) {
3748 iris_restore_context_saved_bos(ice
, batch
, draw
);
3749 batch
->contains_draw
= true;
3754 * State module teardown.
3757 iris_destroy_state(struct iris_context
*ice
)
3759 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
3761 // XXX: unreference resources/surfaces.
3762 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
3763 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
3765 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
3767 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
3768 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3769 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
3771 free(ice
->state
.genx
);
3773 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
3774 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
3775 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
3776 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
3777 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
3780 /* ------------------------------------------------------------------- */
3783 flags_to_post_sync_op(uint32_t flags
)
3785 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
3786 return WriteImmediateData
;
3788 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
3789 return WritePSDepthCount
;
3791 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
3792 return WriteTimestamp
;
3798 * Do the given flags have a Post Sync or LRI Post Sync operation?
3800 static enum pipe_control_flags
3801 get_post_sync_flags(enum pipe_control_flags flags
)
3803 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
3804 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
3805 PIPE_CONTROL_WRITE_TIMESTAMP
|
3806 PIPE_CONTROL_LRI_POST_SYNC_OP
;
3808 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
3809 * "LRI Post Sync Operation". So more than one bit set would be illegal.
3811 assert(util_bitcount(flags
) <= 1);
3816 // XXX: compute support
3817 #define IS_COMPUTE_PIPELINE(batch) (batch->engine != I915_EXEC_RENDER)
3820 * Emit a series of PIPE_CONTROL commands, taking into account any
3821 * workarounds necessary to actually accomplish the caller's request.
3823 * Unless otherwise noted, spec quotations in this function come from:
3825 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
3826 * Restrictions for PIPE_CONTROL.
3828 * You should not use this function directly. Use the helpers in
3829 * iris_pipe_control.c instead, which may split the pipe control further.
3832 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
3833 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
3835 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
3836 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
3837 enum pipe_control_flags non_lri_post_sync_flags
=
3838 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
3840 /* Recursive PIPE_CONTROL workarounds --------------------------------
3841 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
3843 * We do these first because we want to look at the original operation,
3844 * rather than any workarounds we set.
3846 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
3847 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
3848 * lists several workarounds:
3850 * "Project: SKL, KBL, BXT
3852 * If the VF Cache Invalidation Enable is set to a 1 in a
3853 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
3854 * sets to 0, with the VF Cache Invalidation Enable set to 0
3855 * needs to be sent prior to the PIPE_CONTROL with VF Cache
3856 * Invalidation Enable set to a 1."
3858 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
3861 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
3862 /* Project: SKL / Argument: LRI Post Sync Operation [23]
3864 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
3865 * programmed prior to programming a PIPECONTROL command with "LRI
3866 * Post Sync Operation" in GPGPU mode of operation (i.e when
3867 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
3869 * The same text exists a few rows below for Post Sync Op.
3871 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
3874 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
3876 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
3877 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
3878 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
3880 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
3884 /* "Flush Types" workarounds ---------------------------------------------
3885 * We do these now because they may add post-sync operations or CS stalls.
3888 if (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
3889 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
3891 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
3892 * 'Write PS Depth Count' or 'Write Timestamp'."
3895 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3896 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3897 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3898 bo
= batch
->screen
->workaround_bo
;
3902 /* #1130 from Gen10 workarounds page:
3904 * "Enable Depth Stall on every Post Sync Op if Render target Cache
3905 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
3906 * board stall if Render target cache flush is enabled."
3908 * Applicable to CNL B0 and C0 steppings only.
3910 * The wording here is unclear, and this workaround doesn't look anything
3911 * like the internal bug report recommendations, but leave it be for now...
3913 if (GEN_GEN
== 10) {
3914 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
3915 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
3916 } else if (flags
& non_lri_post_sync_flags
) {
3917 flags
|= PIPE_CONTROL_DEPTH_STALL
;
3921 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
3922 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
3924 * "This bit must be DISABLED for operations other than writing
3927 * This seems like nonsense. An Ivybridge workaround requires us to
3928 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
3929 * operation. Gen8+ requires us to emit depth stalls and depth cache
3930 * flushes together. So, it's hard to imagine this means anything other
3931 * than "we originally intended this to be used for PS_DEPTH_COUNT".
3933 * We ignore the supposed restriction and do nothing.
3937 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
3938 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
3939 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
3941 * "This bit must be DISABLED for End-of-pipe (Read) fences,
3942 * PS_DEPTH_COUNT or TIMESTAMP queries."
3944 * TODO: Implement end-of-pipe checking.
3946 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
3947 PIPE_CONTROL_WRITE_TIMESTAMP
)));
3950 if (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) {
3951 /* From the PIPE_CONTROL instruction table, bit 1:
3953 * "This bit is ignored if Depth Stall Enable is set.
3954 * Further, the render cache is not flushed even if Write Cache
3955 * Flush Enable bit is set."
3957 * We assert that the caller doesn't do this combination, to try and
3958 * prevent mistakes. It shouldn't hurt the GPU, though.
3960 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
3961 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
3964 /* PIPE_CONTROL page workarounds ------------------------------------- */
3966 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
3967 /* From the PIPE_CONTROL page itself:
3970 * Restriction: Pipe_control with CS-stall bit set must be issued
3971 * before a pipe-control command that has the State Cache
3972 * Invalidate bit set."
3974 flags
|= PIPE_CONTROL_CS_STALL
;
3977 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
3978 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
3981 * SW must always program Post-Sync Operation to "Write Immediate
3982 * Data" when Flush LLC is set."
3984 * For now, we just require the caller to do it.
3986 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
3989 /* "Post-Sync Operation" workarounds -------------------------------- */
3991 /* Project: All / Argument: Global Snapshot Count Reset [19]
3993 * "This bit must not be exercised on any product.
3994 * Requires stall bit ([20] of DW1) set."
3996 * We don't use this, so we just assert that it isn't used. The
3997 * PIPE_CONTROL instruction page indicates that they intended this
3998 * as a debug feature and don't think it is useful in production,
3999 * but it may actually be usable, should we ever want to.
4001 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
4003 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
4004 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
4005 /* Project: All / Arguments:
4007 * - Generic Media State Clear [16]
4008 * - Indirect State Pointers Disable [16]
4010 * "Requires stall bit ([20] of DW1) set."
4012 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
4013 * State Clear) says:
4015 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
4016 * programmed prior to programming a PIPECONTROL command with "Media
4017 * State Clear" set in GPGPU mode of operation"
4019 * This is a subset of the earlier rule, so there's nothing to do.
4021 flags
|= PIPE_CONTROL_CS_STALL
;
4024 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
4025 /* Project: All / Argument: Store Data Index
4027 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
4030 * For now, we just assert that the caller does this. We might want to
4031 * automatically add a write to the workaround BO...
4033 assert(non_lri_post_sync_flags
!= 0);
4036 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
4037 /* Project: All / Argument: Sync GFDT
4039 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
4040 * than '0' or 0x2520[13] must be set."
4042 * For now, we just assert that the caller does this.
4044 assert(non_lri_post_sync_flags
!= 0);
4047 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
4048 /* Project: IVB+ / Argument: TLB inv
4050 * "Requires stall bit ([20] of DW1) set."
4052 * Also, from the PIPE_CONTROL instruction table:
4055 * Post Sync Operation or CS stall must be set to ensure a TLB
4056 * invalidation occurs. Otherwise no cycle will occur to the TLB
4057 * cache to invalidate."
4059 * This is not a subset of the earlier rule, so there's nothing to do.
4061 flags
|= PIPE_CONTROL_CS_STALL
;
4064 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
4065 /* TODO: The big Skylake GT4 post sync op workaround */
4068 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
4070 if (IS_COMPUTE_PIPELINE(batch
)) {
4071 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
4072 /* Project: SKL+ / Argument: Tex Invalidate
4073 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
4075 flags
|= PIPE_CONTROL_CS_STALL
;
4078 if (GEN_GEN
== 8 && (post_sync_flags
||
4079 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
4080 PIPE_CONTROL_DEPTH_STALL
|
4081 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
4082 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
4083 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
4084 /* Project: BDW / Arguments:
4086 * - LRI Post Sync Operation [23]
4087 * - Post Sync Op [15:14]
4089 * - Depth Stall [13]
4090 * - Render Target Cache Flush [12]
4091 * - Depth Cache Flush [0]
4092 * - DC Flush Enable [5]
4094 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
4097 flags
|= PIPE_CONTROL_CS_STALL
;
4099 /* Also, from the PIPE_CONTROL instruction table, bit 20:
4102 * This bit must be always set when PIPE_CONTROL command is
4103 * programmed by GPGPU and MEDIA workloads, except for the cases
4104 * when only Read Only Cache Invalidation bits are set (State
4105 * Cache Invalidation Enable, Instruction cache Invalidation
4106 * Enable, Texture Cache Invalidation Enable, Constant Cache
4107 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
4108 * need not implemented when FF_DOP_CG is disable via "Fixed
4109 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
4111 * It sounds like we could avoid CS stalls in some cases, but we
4112 * don't currently bother. This list isn't exactly the list above,
4118 /* "Stall" workarounds ----------------------------------------------
4119 * These have to come after the earlier ones because we may have added
4120 * some additional CS stalls above.
4123 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
4124 /* Project: PRE-SKL, VLV, CHV
4126 * "[All Stepping][All SKUs]:
4128 * One of the following must also be set:
4130 * - Render Target Cache Flush Enable ([12] of DW1)
4131 * - Depth Cache Flush Enable ([0] of DW1)
4132 * - Stall at Pixel Scoreboard ([1] of DW1)
4133 * - Depth Stall ([13] of DW1)
4134 * - Post-Sync Operation ([13] of DW1)
4135 * - DC Flush Enable ([5] of DW1)"
4137 * If we don't already have one of those bits set, we choose to add
4138 * "Stall at Pixel Scoreboard". Some of the other bits require a
4139 * CS stall as a workaround (see above), which would send us into
4140 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
4141 * appears to be safe, so we choose that.
4143 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
4144 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
4145 PIPE_CONTROL_WRITE_IMMEDIATE
|
4146 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
4147 PIPE_CONTROL_WRITE_TIMESTAMP
|
4148 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
4149 PIPE_CONTROL_DEPTH_STALL
|
4150 PIPE_CONTROL_DATA_CACHE_FLUSH
;
4151 if (!(flags
& wa_bits
))
4152 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
4155 /* Emit --------------------------------------------------------------- */
4157 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
4158 pc
.LRIPostSyncOperation
= NoLRIOperation
;
4159 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
4160 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
4161 pc
.StoreDataIndex
= 0;
4162 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
4163 pc
.GlobalSnapshotCountReset
=
4164 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
4165 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
4166 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
4167 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
4168 pc
.RenderTargetCacheFlushEnable
=
4169 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
4170 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
4171 pc
.StateCacheInvalidationEnable
=
4172 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
4173 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
4174 pc
.ConstantCacheInvalidationEnable
=
4175 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
4176 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
4177 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
4178 pc
.InstructionCacheInvalidateEnable
=
4179 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
4180 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
4181 pc
.IndirectStatePointersDisable
=
4182 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
4183 pc
.TextureCacheInvalidationEnable
=
4184 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
4185 pc
.Address
= ro_bo(bo
, offset
);
4186 pc
.ImmediateData
= imm
;
4191 genX(init_state
)(struct iris_context
*ice
)
4193 struct pipe_context
*ctx
= &ice
->ctx
;
4194 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
4196 ctx
->create_blend_state
= iris_create_blend_state
;
4197 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
4198 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
4199 ctx
->create_sampler_state
= iris_create_sampler_state
;
4200 ctx
->create_sampler_view
= iris_create_sampler_view
;
4201 ctx
->create_surface
= iris_create_surface
;
4202 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
4203 ctx
->create_compute_state
= iris_create_compute_state
;
4204 ctx
->bind_blend_state
= iris_bind_blend_state
;
4205 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
4206 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
4207 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
4208 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
4209 ctx
->bind_compute_state
= iris_bind_compute_state
;
4210 ctx
->delete_blend_state
= iris_delete_state
;
4211 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
4212 ctx
->delete_fs_state
= iris_delete_state
;
4213 ctx
->delete_rasterizer_state
= iris_delete_state
;
4214 ctx
->delete_sampler_state
= iris_delete_state
;
4215 ctx
->delete_vertex_elements_state
= iris_delete_state
;
4216 ctx
->delete_compute_state
= iris_delete_state
;
4217 ctx
->delete_tcs_state
= iris_delete_state
;
4218 ctx
->delete_tes_state
= iris_delete_state
;
4219 ctx
->delete_gs_state
= iris_delete_state
;
4220 ctx
->delete_vs_state
= iris_delete_state
;
4221 ctx
->set_blend_color
= iris_set_blend_color
;
4222 ctx
->set_clip_state
= iris_set_clip_state
;
4223 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
4224 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
4225 ctx
->set_sampler_views
= iris_set_sampler_views
;
4226 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
4227 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
4228 ctx
->set_sample_mask
= iris_set_sample_mask
;
4229 ctx
->set_scissor_states
= iris_set_scissor_states
;
4230 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
4231 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
4232 ctx
->set_viewport_states
= iris_set_viewport_states
;
4233 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
4234 ctx
->surface_destroy
= iris_surface_destroy
;
4235 ctx
->draw_vbo
= iris_draw_vbo
;
4236 ctx
->launch_grid
= iris_launch_grid
;
4237 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
4238 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
4239 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
4241 ice
->vtbl
.destroy_state
= iris_destroy_state
;
4242 ice
->vtbl
.init_render_context
= iris_init_render_context
;
4243 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
4244 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
4245 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
4246 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
4247 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
4248 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
4249 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
4250 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
4251 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
4252 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
4254 ice
->state
.dirty
= ~0ull;
4256 ice
->state
.sample_mask
= 0xffff;
4257 ice
->state
.num_viewports
= 1;
4258 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
4260 /* Make a 1x1x1 null surface for unbound textures */
4261 void *null_surf_map
=
4262 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
4263 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
4264 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));