2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_inlines.h"
92 #include "util/u_format.h"
93 #include "util/u_framebuffer.h"
94 #include "util/u_transfer.h"
95 #include "util/u_upload_mgr.h"
96 #include "util/u_viewport.h"
99 #include "intel/compiler/brw_compiler.h"
100 #include "intel/common/gen_l3_config.h"
101 #include "intel/common/gen_sample_positions.h"
102 #include "iris_batch.h"
103 #include "iris_context.h"
104 #include "iris_defines.h"
105 #include "iris_pipe.h"
106 #include "iris_resource.h"
108 #define __gen_address_type struct iris_address
109 #define __gen_user_data struct iris_batch
111 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
114 __gen_combine_address(struct iris_batch
*batch
, void *location
,
115 struct iris_address addr
, uint32_t delta
)
117 uint64_t result
= addr
.offset
+ delta
;
120 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
121 /* Assume this is a general address, not relative to a base. */
122 result
+= addr
.bo
->gtt_offset
;
128 #define __genxml_cmd_length(cmd) cmd ## _length
129 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
130 #define __genxml_cmd_header(cmd) cmd ## _header
131 #define __genxml_cmd_pack(cmd) cmd ## _pack
133 #define _iris_pack_command(batch, cmd, dst, name) \
134 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
135 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
136 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
140 #define iris_pack_command(cmd, dst, name) \
141 _iris_pack_command(NULL, cmd, dst, name)
143 #define iris_pack_state(cmd, dst, name) \
144 for (struct cmd name = {}, \
145 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
146 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
149 #define iris_emit_cmd(batch, cmd, name) \
150 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
152 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
154 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
155 for (uint32_t i = 0; i < num_dwords; i++) \
156 dw[i] = (dwords0)[i] | (dwords1)[i]; \
157 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
160 #include "genxml/genX_pack.h"
161 #include "genxml/gen_macros.h"
162 #include "genxml/genX_bits.h"
165 #define MOCS_PTE 0x18
168 #define MOCS_PTE (1 << 1)
169 #define MOCS_WB (2 << 1)
173 mocs(struct iris_bo
*bo
)
175 return bo
&& bo
->external
? MOCS_PTE
: MOCS_WB
;
179 * Statically assert that PIPE_* enums match the hardware packets.
180 * (As long as they match, we don't need to translate them.)
182 UNUSED
static void pipe_asserts()
184 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
186 /* pipe_logicop happens to match the hardware. */
187 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
188 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
189 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
190 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
191 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
192 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
193 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
194 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
195 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
196 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
197 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
198 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
199 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
200 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
201 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
202 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
204 /* pipe_blend_func happens to match the hardware. */
205 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
206 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
207 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
211 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
212 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
213 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
214 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
215 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
216 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
217 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
218 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
219 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
220 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
221 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
222 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
223 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
225 /* pipe_blend_func happens to match the hardware. */
226 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
227 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
228 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
229 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
230 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
232 /* pipe_stencil_op happens to match the hardware. */
233 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
234 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
235 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
236 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
237 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
238 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
239 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
240 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
242 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
243 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
244 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
249 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
251 static const unsigned map
[] = {
252 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
253 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
254 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
255 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
256 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
257 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
258 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
259 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
260 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
261 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
262 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
263 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
264 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
265 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
266 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
269 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
273 translate_compare_func(enum pipe_compare_func pipe_func
)
275 static const unsigned map
[] = {
276 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
277 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
278 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
279 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
280 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
281 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
282 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
283 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
285 return map
[pipe_func
];
289 translate_shadow_func(enum pipe_compare_func pipe_func
)
291 /* Gallium specifies the result of shadow comparisons as:
293 * 1 if ref <op> texel,
298 * 0 if texel <op> ref,
301 * So we need to flip the operator and also negate.
303 static const unsigned map
[] = {
304 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
305 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
306 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
307 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
308 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
309 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
310 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
311 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
313 return map
[pipe_func
];
317 translate_cull_mode(unsigned pipe_face
)
319 static const unsigned map
[4] = {
320 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
321 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
322 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
323 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
325 return map
[pipe_face
];
329 translate_fill_mode(unsigned pipe_polymode
)
331 static const unsigned map
[4] = {
332 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
333 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
334 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
335 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
337 return map
[pipe_polymode
];
341 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
343 static const unsigned map
[] = {
344 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
345 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
346 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
348 return map
[pipe_mip
];
352 translate_wrap(unsigned pipe_wrap
)
354 static const unsigned map
[] = {
355 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
356 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
357 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
358 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
359 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
360 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
362 /* These are unsupported. */
363 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
364 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
366 return map
[pipe_wrap
];
369 static struct iris_address
370 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
372 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
373 * validation list at CSO creation time, instead of draw time.
375 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
378 static struct iris_address
379 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
381 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
382 * validation list at CSO creation time, instead of draw time.
384 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
388 * Allocate space for some indirect state.
390 * Return a pointer to the map (to fill it out) and a state ref (for
391 * referring to the state in GPU commands).
394 upload_state(struct u_upload_mgr
*uploader
,
395 struct iris_state_ref
*ref
,
400 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
405 * Stream out temporary/short-lived state.
407 * This allocates space, pins the BO, and includes the BO address in the
408 * returned offset (which works because all state lives in 32-bit memory
412 stream_state(struct iris_batch
*batch
,
413 struct u_upload_mgr
*uploader
,
414 struct pipe_resource
**out_res
,
417 uint32_t *out_offset
)
421 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
423 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
424 iris_use_pinned_bo(batch
, bo
, false);
426 *out_offset
+= iris_bo_offset_from_base_address(bo
);
432 * stream_state() + memcpy.
435 emit_state(struct iris_batch
*batch
,
436 struct u_upload_mgr
*uploader
,
437 struct pipe_resource
**out_res
,
444 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
447 memcpy(map
, data
, size
);
453 * Did field 'x' change between 'old_cso' and 'new_cso'?
455 * (If so, we may want to set some dirty flags.)
457 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
458 #define cso_changed_memcmp(x) \
459 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
462 flush_for_state_base_change(struct iris_batch
*batch
)
464 /* Flush before emitting STATE_BASE_ADDRESS.
466 * This isn't documented anywhere in the PRM. However, it seems to be
467 * necessary prior to changing the surface state base adress. We've
468 * seen issues in Vulkan where we get GPU hangs when using multi-level
469 * command buffers which clear depth, reset state base address, and then
472 * Normally, in GL, we would trust the kernel to do sufficient stalls
473 * and flushes prior to executing our batch. However, it doesn't seem
474 * as if the kernel's flushing is always sufficient and we don't want to
477 * We make this an end-of-pipe sync instead of a normal flush because we
478 * do not know the current status of the GPU. On Haswell at least,
479 * having a fast-clear operation in flight at the same time as a normal
480 * rendering operation can cause hangs. Since the kernel's flushing is
481 * insufficient, we need to ensure that any rendering operations from
482 * other processes are definitely complete before we try to do our own
483 * rendering. It's a bit of a big hammer but it appears to work.
485 iris_emit_end_of_pipe_sync(batch
,
486 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
487 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
488 PIPE_CONTROL_DATA_CACHE_FLUSH
);
492 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
494 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
495 lri
.RegisterOffset
= reg
;
499 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
502 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
504 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
505 lrr
.SourceRegisterAddress
= src
;
506 lrr
.DestinationRegisterAddress
= dst
;
511 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
513 #if GEN_GEN >= 8 && GEN_GEN < 10
514 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
516 * Software must clear the COLOR_CALC_STATE Valid field in
517 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
518 * with Pipeline Select set to GPGPU.
520 * The internal hardware docs recommend the same workaround for Gen9
523 if (pipeline
== GPGPU
)
524 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
528 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
529 * PIPELINE_SELECT [DevBWR+]":
533 * Software must ensure all the write caches are flushed through a
534 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
535 * command to invalidate read only caches prior to programming
536 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
538 iris_emit_pipe_control_flush(batch
,
539 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
540 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
541 PIPE_CONTROL_DATA_CACHE_FLUSH
|
542 PIPE_CONTROL_CS_STALL
);
544 iris_emit_pipe_control_flush(batch
,
545 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
546 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
547 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
548 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
550 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
554 sel
.PipelineSelection
= pipeline
;
559 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
564 * "This chicken bit works around a hardware issue with barrier
565 * logic encountered when switching between GPGPU and 3D pipelines.
566 * To workaround the issue, this mode bit should be set after a
567 * pipeline is selected."
570 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
571 reg
.GLKBarrierMode
= value
;
572 reg
.GLKBarrierModeMask
= 1;
574 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
579 init_state_base_address(struct iris_batch
*batch
)
581 flush_for_state_base_change(batch
);
583 /* We program most base addresses once at context initialization time.
584 * Each base address points at a 4GB memory zone, and never needs to
585 * change. See iris_bufmgr.h for a description of the memory zones.
587 * The one exception is Surface State Base Address, which needs to be
588 * updated occasionally. See iris_binder.c for the details there.
590 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
591 sba
.GeneralStateMOCS
= MOCS_WB
;
592 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
593 sba
.DynamicStateMOCS
= MOCS_WB
;
594 sba
.IndirectObjectMOCS
= MOCS_WB
;
595 sba
.InstructionMOCS
= MOCS_WB
;
597 sba
.GeneralStateBaseAddressModifyEnable
= true;
598 sba
.DynamicStateBaseAddressModifyEnable
= true;
599 sba
.IndirectObjectBaseAddressModifyEnable
= true;
600 sba
.InstructionBaseAddressModifyEnable
= true;
601 sba
.GeneralStateBufferSizeModifyEnable
= true;
602 sba
.DynamicStateBufferSizeModifyEnable
= true;
604 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
605 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
607 sba
.IndirectObjectBufferSizeModifyEnable
= true;
608 sba
.InstructionBuffersizeModifyEnable
= true;
610 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
611 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
613 sba
.GeneralStateBufferSize
= 0xfffff;
614 sba
.IndirectObjectBufferSize
= 0xfffff;
615 sba
.InstructionBufferSize
= 0xfffff;
616 sba
.DynamicStateBufferSize
= 0xfffff;
621 * Upload the initial GPU state for a render context.
623 * This sets some invariant state that needs to be programmed a particular
624 * way, but we never actually change.
627 iris_init_render_context(struct iris_screen
*screen
,
628 struct iris_batch
*batch
,
629 struct iris_vtable
*vtbl
,
630 struct pipe_debug_callback
*dbg
)
632 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
635 emit_pipeline_select(batch
, _3D
);
637 init_state_base_address(batch
);
640 // XXX: INSTPM on Gen8
641 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
642 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
643 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
645 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
647 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
648 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
649 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
651 iris_emit_lri(batch
, INSTPM
, reg_val
);
655 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
656 reg
.FloatBlendOptimizationEnable
= true;
657 reg
.FloatBlendOptimizationEnableMask
= true;
658 reg
.PartialResolveDisableInVC
= true;
659 reg
.PartialResolveDisableInVCMask
= true;
661 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
663 if (devinfo
->is_geminilake
)
664 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
668 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
669 reg
.HeaderlessMessageforPreemptableContexts
= 1;
670 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
672 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
677 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
678 * changing it dynamically. We set it to the maximum size here, and
679 * instead include the render target dimensions in the viewport, so
680 * viewport extents clipping takes care of pruning stray geometry.
682 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
683 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
684 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
687 /* Set the initial MSAA sample positions. */
688 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
689 GEN_SAMPLE_POS_1X(pat
._1xSample
);
690 GEN_SAMPLE_POS_2X(pat
._2xSample
);
691 GEN_SAMPLE_POS_4X(pat
._4xSample
);
692 GEN_SAMPLE_POS_8X(pat
._8xSample
);
694 GEN_SAMPLE_POS_16X(pat
._16xSample
);
698 /* Use the legacy AA line coverage computation. */
699 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
701 /* Disable chromakeying (it's for media) */
702 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
704 /* We want regular rendering, not special HiZ operations. */
705 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
707 /* No polygon stippling offsets are necessary. */
708 // XXX: may need to set an offset for origin-UL framebuffers
709 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
711 /* Set a static partitioning of the push constant area. */
712 // XXX: this may be a bad idea...could starve the push ringbuffers...
713 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
714 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
715 alloc
._3DCommandSubOpcode
= 18 + i
;
716 alloc
.ConstantBufferOffset
= 6 * i
;
717 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
723 iris_init_compute_context(struct iris_screen
*screen
,
724 struct iris_batch
*batch
,
725 struct iris_vtable
*vtbl
,
726 struct pipe_debug_callback
*dbg
)
728 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
730 emit_pipeline_select(batch
, GPGPU
);
732 const bool has_slm
= true;
733 const bool wants_dc_cache
= true;
735 const struct gen_l3_weights w
=
736 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
737 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
740 iris_pack_state(GENX(L3CNTLREG
), ®_val
, reg
) {
741 reg
.SLMEnable
= has_slm
;
743 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
744 * in L3CNTLREG register. The default setting of the bit is not the
745 * desirable behavior.
747 reg
.ErrorDetectionBehaviorControl
= true;
749 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
750 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
751 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
752 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
754 iris_emit_lri(batch
, L3CNTLREG
, reg_val
);
756 init_state_base_address(batch
);
759 if (devinfo
->is_geminilake
)
760 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
764 struct iris_vertex_buffer_state
{
765 /** The VERTEX_BUFFER_STATE hardware structure. */
766 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
768 /** The resource to source vertex data from. */
769 struct pipe_resource
*resource
;
772 struct iris_depth_buffer_state
{
773 /* Depth/HiZ/Stencil related hardware packets. */
774 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
775 GENX(3DSTATE_STENCIL_BUFFER_length
) +
776 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
777 GENX(3DSTATE_CLEAR_PARAMS_length
)];
781 * Generation-specific context state (ice->state.genx->...).
783 * Most state can go in iris_context directly, but these encode hardware
784 * packets which vary by generation.
786 struct iris_genx_state
{
787 struct iris_vertex_buffer_state vertex_buffers
[33];
789 /** The number of bound vertex buffers. */
790 uint64_t bound_vertex_buffers
;
792 struct iris_depth_buffer_state depth_buffer
;
794 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
798 * The pipe->set_blend_color() driver hook.
800 * This corresponds to our COLOR_CALC_STATE.
803 iris_set_blend_color(struct pipe_context
*ctx
,
804 const struct pipe_blend_color
*state
)
806 struct iris_context
*ice
= (struct iris_context
*) ctx
;
808 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
809 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
810 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
814 * Gallium CSO for blend state (see pipe_blend_state).
816 struct iris_blend_state
{
817 /** Partial 3DSTATE_PS_BLEND */
818 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
820 /** Partial BLEND_STATE */
821 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
822 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
824 bool alpha_to_coverage
; /* for shader key */
826 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
827 uint8_t blend_enables
;
830 static enum pipe_blendfactor
831 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
834 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
835 return PIPE_BLENDFACTOR_ONE
;
837 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
838 return PIPE_BLENDFACTOR_ZERO
;
845 * The pipe->create_blend_state() driver hook.
847 * Translates a pipe_blend_state into iris_blend_state.
850 iris_create_blend_state(struct pipe_context
*ctx
,
851 const struct pipe_blend_state
*state
)
853 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
854 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
856 cso
->blend_enables
= 0;
857 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
859 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
861 bool indep_alpha_blend
= false;
863 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
864 const struct pipe_rt_blend_state
*rt
=
865 &state
->rt
[state
->independent_blend_enable
? i
: 0];
867 enum pipe_blendfactor src_rgb
=
868 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
869 enum pipe_blendfactor src_alpha
=
870 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
871 enum pipe_blendfactor dst_rgb
=
872 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
873 enum pipe_blendfactor dst_alpha
=
874 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
876 if (rt
->rgb_func
!= rt
->alpha_func
||
877 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
878 indep_alpha_blend
= true;
880 if (rt
->blend_enable
)
881 cso
->blend_enables
|= 1u << i
;
883 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
884 be
.LogicOpEnable
= state
->logicop_enable
;
885 be
.LogicOpFunction
= state
->logicop_func
;
887 be
.PreBlendSourceOnlyClampEnable
= false;
888 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
889 be
.PreBlendColorClampEnable
= true;
890 be
.PostBlendColorClampEnable
= true;
892 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
894 be
.ColorBlendFunction
= rt
->rgb_func
;
895 be
.AlphaBlendFunction
= rt
->alpha_func
;
896 be
.SourceBlendFactor
= src_rgb
;
897 be
.SourceAlphaBlendFactor
= src_alpha
;
898 be
.DestinationBlendFactor
= dst_rgb
;
899 be
.DestinationAlphaBlendFactor
= dst_alpha
;
901 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
902 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
903 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
904 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
906 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
909 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
910 /* pb.HasWriteableRT is filled in at draw time. */
911 /* pb.AlphaTestEnable is filled in at draw time. */
912 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
913 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
915 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
917 pb
.SourceBlendFactor
=
918 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
919 pb
.SourceAlphaBlendFactor
=
920 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
921 pb
.DestinationBlendFactor
=
922 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
923 pb
.DestinationAlphaBlendFactor
=
924 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
927 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
928 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
929 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
930 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
931 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
932 bs
.ColorDitherEnable
= state
->dither
;
933 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
941 * The pipe->bind_blend_state() driver hook.
943 * Bind a blending CSO and flag related dirty bits.
946 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
948 struct iris_context
*ice
= (struct iris_context
*) ctx
;
949 struct iris_blend_state
*cso
= state
;
951 ice
->state
.cso_blend
= cso
;
952 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
954 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
955 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
956 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
960 * Gallium CSO for depth, stencil, and alpha testing state.
962 struct iris_depth_stencil_alpha_state
{
963 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
964 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
966 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
967 struct pipe_alpha_state alpha
;
969 /** Outbound to resolve and cache set tracking. */
970 bool depth_writes_enabled
;
971 bool stencil_writes_enabled
;
975 * The pipe->create_depth_stencil_alpha_state() driver hook.
977 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
978 * testing state since we need pieces of it in a variety of places.
981 iris_create_zsa_state(struct pipe_context
*ctx
,
982 const struct pipe_depth_stencil_alpha_state
*state
)
984 struct iris_depth_stencil_alpha_state
*cso
=
985 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
987 bool two_sided_stencil
= state
->stencil
[1].enabled
;
989 cso
->alpha
= state
->alpha
;
990 cso
->depth_writes_enabled
= state
->depth
.writemask
;
991 cso
->stencil_writes_enabled
=
992 state
->stencil
[0].writemask
!= 0 ||
993 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 1);
995 /* The state tracker needs to optimize away EQUAL writes for us. */
996 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
998 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
999 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1000 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1001 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1002 wmds
.StencilTestFunction
=
1003 translate_compare_func(state
->stencil
[0].func
);
1004 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1005 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1006 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1007 wmds
.BackfaceStencilTestFunction
=
1008 translate_compare_func(state
->stencil
[1].func
);
1009 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1010 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1011 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1012 wmds
.StencilBufferWriteEnable
=
1013 state
->stencil
[0].writemask
!= 0 ||
1014 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1015 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1016 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1017 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1018 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1019 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1020 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1021 /* wmds.[Backface]StencilReferenceValue are merged later */
1028 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1030 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1033 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1035 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1036 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1037 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1040 if (cso_changed(alpha
.ref_value
))
1041 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1043 if (cso_changed(alpha
.enabled
))
1044 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1046 if (cso_changed(alpha
.func
))
1047 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1049 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1050 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1053 ice
->state
.cso_zsa
= new_cso
;
1054 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1055 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1056 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1060 * Gallium CSO for rasterizer state.
1062 struct iris_rasterizer_state
{
1063 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1064 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1065 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1066 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1067 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1069 uint8_t num_clip_plane_consts
;
1070 bool clip_halfz
; /* for CC_VIEWPORT */
1071 bool depth_clip_near
; /* for CC_VIEWPORT */
1072 bool depth_clip_far
; /* for CC_VIEWPORT */
1073 bool flatshade
; /* for shader state */
1074 bool flatshade_first
; /* for stream output */
1075 bool clamp_fragment_color
; /* for shader state */
1076 bool light_twoside
; /* for shader state */
1077 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1078 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1079 bool line_stipple_enable
;
1080 bool poly_stipple_enable
;
1082 bool force_persample_interp
;
1083 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1084 uint16_t sprite_coord_enable
;
1088 get_line_width(const struct pipe_rasterizer_state
*state
)
1090 float line_width
= state
->line_width
;
1092 /* From the OpenGL 4.4 spec:
1094 * "The actual width of non-antialiased lines is determined by rounding
1095 * the supplied width to the nearest integer, then clamping it to the
1096 * implementation-dependent maximum non-antialiased line width."
1098 if (!state
->multisample
&& !state
->line_smooth
)
1099 line_width
= roundf(state
->line_width
);
1101 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1102 /* For 1 pixel line thickness or less, the general anti-aliasing
1103 * algorithm gives up, and a garbage line is generated. Setting a
1104 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1105 * (one-pixel-wide), non-antialiased lines.
1107 * Lines rendered with zero Line Width are rasterized using the
1108 * "Grid Intersection Quantization" rules as specified by the
1109 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1118 * The pipe->create_rasterizer_state() driver hook.
1121 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1122 const struct pipe_rasterizer_state
*state
)
1124 struct iris_rasterizer_state
*cso
=
1125 malloc(sizeof(struct iris_rasterizer_state
));
1128 point_quad_rasterization
-> SBE
?
1135 offset_units_unscaled
- cap
not exposed
1139 // XXX: it may make more sense just to store the pipe_rasterizer_state,
1140 // we're copying a lot of booleans here. But we don't need all of them...
1142 cso
->multisample
= state
->multisample
;
1143 cso
->force_persample_interp
= state
->force_persample_interp
;
1144 cso
->clip_halfz
= state
->clip_halfz
;
1145 cso
->depth_clip_near
= state
->depth_clip_near
;
1146 cso
->depth_clip_far
= state
->depth_clip_far
;
1147 cso
->flatshade
= state
->flatshade
;
1148 cso
->flatshade_first
= state
->flatshade_first
;
1149 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1150 cso
->light_twoside
= state
->light_twoside
;
1151 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1152 cso
->half_pixel_center
= state
->half_pixel_center
;
1153 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1154 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1155 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1156 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1158 if (state
->clip_plane_enable
!= 0)
1159 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1161 cso
->num_clip_plane_consts
= 0;
1163 float line_width
= get_line_width(state
);
1165 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1166 sf
.StatisticsEnable
= true;
1167 sf
.ViewportTransformEnable
= true;
1168 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1169 sf
.LineEndCapAntialiasingRegionWidth
=
1170 state
->line_smooth
? _10pixels
: _05pixels
;
1171 sf
.LastPixelEnable
= state
->line_last_pixel
;
1172 sf
.LineWidth
= line_width
;
1173 sf
.SmoothPointEnable
= state
->point_smooth
|| state
->multisample
;
1174 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1175 sf
.PointWidth
= state
->point_size
;
1177 if (state
->flatshade_first
) {
1178 sf
.TriangleFanProvokingVertexSelect
= 1;
1180 sf
.TriangleStripListProvokingVertexSelect
= 2;
1181 sf
.TriangleFanProvokingVertexSelect
= 2;
1182 sf
.LineStripListProvokingVertexSelect
= 1;
1186 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1187 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1188 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1189 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1190 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1191 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1192 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1193 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1194 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1195 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1196 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1197 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1198 rr
.SmoothPointEnable
= state
->point_smooth
|| state
->multisample
;
1199 rr
.AntialiasingEnable
= state
->line_smooth
;
1200 rr
.ScissorRectangleEnable
= state
->scissor
;
1202 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1203 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1205 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1207 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
1210 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1211 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1212 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1214 cl
.EarlyCullEnable
= true;
1215 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1216 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1217 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1218 cl
.GuardbandClipTestEnable
= true;
1219 cl
.ClipEnable
= true;
1220 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
1221 cl
.MinimumPointWidth
= 0.125;
1222 cl
.MaximumPointWidth
= 255.875;
1224 if (state
->flatshade_first
) {
1225 cl
.TriangleFanProvokingVertexSelect
= 1;
1227 cl
.TriangleStripListProvokingVertexSelect
= 2;
1228 cl
.TriangleFanProvokingVertexSelect
= 2;
1229 cl
.LineStripListProvokingVertexSelect
= 1;
1233 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1234 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1235 * filled in at draw time from the FS program.
1237 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1238 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1239 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1240 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1241 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1244 /* Remap from 0..255 back to 1..256 */
1245 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1247 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1248 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1249 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1250 line
.LineStippleRepeatCount
= line_stipple_factor
;
1257 * The pipe->bind_rasterizer_state() driver hook.
1259 * Bind a rasterizer CSO and flag related dirty bits.
1262 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1264 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1265 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1266 struct iris_rasterizer_state
*new_cso
= state
;
1269 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1270 if (cso_changed_memcmp(line_stipple
))
1271 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1273 if (cso_changed(half_pixel_center
))
1274 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1276 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1277 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1279 if (cso_changed(rasterizer_discard
))
1280 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1282 if (cso_changed(flatshade_first
))
1283 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1285 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1286 cso_changed(clip_halfz
))
1287 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1289 if (cso_changed(sprite_coord_enable
) ||
1290 cso_changed(sprite_coord_mode
) ||
1291 cso_changed(light_twoside
))
1292 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1295 ice
->state
.cso_rast
= new_cso
;
1296 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1297 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1298 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1302 * Return true if the given wrap mode requires the border color to exist.
1304 * (We can skip uploading it if the sampler isn't going to use it.)
1307 wrap_mode_needs_border_color(unsigned wrap_mode
)
1309 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1313 * Gallium CSO for sampler state.
1315 struct iris_sampler_state
{
1316 union pipe_color_union border_color
;
1317 bool needs_border_color
;
1319 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1323 * The pipe->create_sampler_state() driver hook.
1325 * We fill out SAMPLER_STATE (except for the border color pointer), and
1326 * store that on the CPU. It doesn't make sense to upload it to a GPU
1327 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1328 * all bound sampler states to be in contiguous memor.
1331 iris_create_sampler_state(struct pipe_context
*ctx
,
1332 const struct pipe_sampler_state
*state
)
1334 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1339 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1340 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1342 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1343 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1344 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1346 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1348 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1349 wrap_mode_needs_border_color(wrap_t
) ||
1350 wrap_mode_needs_border_color(wrap_r
);
1352 float min_lod
= state
->min_lod
;
1353 unsigned mag_img_filter
= state
->mag_img_filter
;
1355 // XXX: explain this code ported from ilo...I don't get it at all...
1356 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1357 state
->min_lod
> 0.0f
) {
1359 mag_img_filter
= state
->min_img_filter
;
1362 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1363 samp
.TCXAddressControlMode
= wrap_s
;
1364 samp
.TCYAddressControlMode
= wrap_t
;
1365 samp
.TCZAddressControlMode
= wrap_r
;
1366 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1367 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1368 samp
.MinModeFilter
= state
->min_img_filter
;
1369 samp
.MagModeFilter
= mag_img_filter
;
1370 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1371 samp
.MaximumAnisotropy
= RATIO21
;
1373 if (state
->max_anisotropy
>= 2) {
1374 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1375 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1376 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1379 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1380 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1382 samp
.MaximumAnisotropy
=
1383 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1386 /* Set address rounding bits if not using nearest filtering. */
1387 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1388 samp
.UAddressMinFilterRoundingEnable
= true;
1389 samp
.VAddressMinFilterRoundingEnable
= true;
1390 samp
.RAddressMinFilterRoundingEnable
= true;
1393 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1394 samp
.UAddressMagFilterRoundingEnable
= true;
1395 samp
.VAddressMagFilterRoundingEnable
= true;
1396 samp
.RAddressMagFilterRoundingEnable
= true;
1399 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1400 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1402 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1404 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1405 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1406 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1407 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1409 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1416 * The pipe->bind_sampler_states() driver hook.
1418 * Now that we know all the sampler states, we upload them all into a
1419 * contiguous area of GPU memory, for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1420 * We also fill out the border color state pointers at this point.
1422 * We could defer this work to draw time, but we assume that binding
1423 * will be less frequent than drawing.
1425 // XXX: this may be a bad idea, need to make sure that st/mesa calls us
1426 // XXX: with the complete set of shaders. If it makes multiple calls to
1427 // XXX: things one at a time, we could waste a lot of time assembling things.
1428 // XXX: it doesn't even BUY us anything to do it here, because we only flag
1429 // XXX: IRIS_DIRTY_SAMPLER_STATE when this is called...
1431 iris_bind_sampler_states(struct pipe_context
*ctx
,
1432 enum pipe_shader_type p_stage
,
1433 unsigned start
, unsigned count
,
1436 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1437 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1438 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1440 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1442 for (int i
= 0; i
< count
; i
++) {
1443 shs
->samplers
[start
+ i
] = states
[i
];
1446 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1447 * in the dynamic state memory zone, so we can point to it via the
1448 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1451 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
,
1452 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
1456 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1457 shs
->sampler_table
.offset
+=
1458 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1460 /* Make sure all land in the same BO */
1461 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1463 for (int i
= 0; i
< count
; i
++) {
1464 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1467 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1468 } else if (!state
->needs_border_color
) {
1469 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1471 ice
->state
.need_border_colors
= true;
1473 /* Stream out the border color and merge the pointer. */
1475 iris_upload_border_color(ice
, &state
->border_color
);
1477 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1478 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1479 dyns
.BorderColorPointer
= offset
;
1482 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1483 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1486 map
+= GENX(SAMPLER_STATE_length
);
1489 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1492 static enum isl_channel_select
1493 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1496 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1497 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1498 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1499 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1500 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1501 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1502 default: unreachable("invalid swizzle");
1507 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1510 enum isl_format format
,
1514 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1515 const unsigned cpp
= fmtl
->bpb
/ 8;
1517 /* The ARB_texture_buffer_specification says:
1519 * "The number of texels in the buffer texture's texel array is given by
1521 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1523 * where <buffer_size> is the size of the buffer object, in basic
1524 * machine units and <components> and <base_type> are the element count
1525 * and base data type for elements, as specified in Table X.1. The
1526 * number of texels in the texel array is then clamped to the
1527 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1529 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1530 * so that when ISL divides by stride to obtain the number of texels, that
1531 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1533 unsigned final_size
=
1534 MIN3(size
, bo
->size
- offset
, IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1536 isl_buffer_fill_state(isl_dev
, map
,
1537 .address
= bo
->gtt_offset
+ offset
,
1538 .size_B
= final_size
,
1545 * Allocate a SURFACE_STATE structure.
1548 alloc_surface_states(struct u_upload_mgr
*mgr
,
1549 struct iris_state_ref
*ref
)
1551 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
1553 void *map
= upload_state(mgr
, ref
, surf_size
, 64);
1555 ref
->offset
+= iris_bo_offset_from_base_address(iris_resource_bo(ref
->res
));
1561 fill_surface_state(struct isl_device
*isl_dev
,
1563 struct iris_resource
*res
,
1564 struct isl_view
*view
)
1566 struct isl_surf_fill_state_info f
= {
1569 .mocs
= mocs(res
->bo
),
1570 .address
= res
->bo
->gtt_offset
,
1573 isl_surf_fill_state_s(isl_dev
, map
, &f
);
1577 * The pipe->create_sampler_view() driver hook.
1579 static struct pipe_sampler_view
*
1580 iris_create_sampler_view(struct pipe_context
*ctx
,
1581 struct pipe_resource
*tex
,
1582 const struct pipe_sampler_view
*tmpl
)
1584 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1585 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1586 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1587 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1592 /* initialize base object */
1594 isv
->base
.context
= ctx
;
1595 isv
->base
.texture
= NULL
;
1596 pipe_reference_init(&isv
->base
.reference
, 1);
1597 pipe_resource_reference(&isv
->base
.texture
, tex
);
1599 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1600 &isv
->surface_state
);
1604 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1605 struct iris_resource
*zres
, *sres
;
1606 const struct util_format_description
*desc
=
1607 util_format_description(tmpl
->format
);
1609 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1611 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1614 isv
->res
= (struct iris_resource
*) tex
;
1616 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1618 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1619 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1620 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1622 const struct iris_format_info fmt
=
1623 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1625 isv
->view
= (struct isl_view
) {
1627 .swizzle
= (struct isl_swizzle
) {
1628 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1629 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1630 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1631 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1636 /* Fill out SURFACE_STATE for this view. */
1637 if (tmpl
->target
!= PIPE_BUFFER
) {
1638 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1639 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1640 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1641 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1642 isv
->view
.array_len
=
1643 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1645 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->view
);
1647 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
->bo
, map
,
1648 isv
->view
.format
, tmpl
->u
.buf
.offset
,
1656 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1657 struct pipe_sampler_view
*state
)
1659 struct iris_sampler_view
*isv
= (void *) state
;
1660 pipe_resource_reference(&state
->texture
, NULL
);
1661 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1666 * The pipe->create_surface() driver hook.
1668 * In Gallium nomenclature, "surfaces" are a view of a resource that
1669 * can be bound as a render target or depth/stencil buffer.
1671 static struct pipe_surface
*
1672 iris_create_surface(struct pipe_context
*ctx
,
1673 struct pipe_resource
*tex
,
1674 const struct pipe_surface
*tmpl
)
1676 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1677 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1678 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1679 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1680 struct pipe_surface
*psurf
= &surf
->base
;
1681 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1686 pipe_reference_init(&psurf
->reference
, 1);
1687 pipe_resource_reference(&psurf
->texture
, tex
);
1688 psurf
->context
= ctx
;
1689 psurf
->format
= tmpl
->format
;
1690 psurf
->width
= tex
->width0
;
1691 psurf
->height
= tex
->height0
;
1692 psurf
->texture
= tex
;
1693 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1694 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1695 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1697 isl_surf_usage_flags_t usage
= 0;
1699 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1700 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1701 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1703 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1705 const struct iris_format_info fmt
=
1706 iris_format_for_usage(devinfo
, psurf
->format
, usage
);
1708 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1709 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1710 /* Framebuffer validation will reject this invalid case, but it
1711 * hasn't had the opportunity yet. In the meantime, we need to
1712 * avoid hitting ISL asserts about unsupported formats below.
1718 surf
->view
= (struct isl_view
) {
1720 .base_level
= tmpl
->u
.tex
.level
,
1722 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1723 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1724 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1728 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1729 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1730 ISL_SURF_USAGE_STENCIL_BIT
))
1734 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1735 &surf
->surface_state
);
1739 fill_surface_state(&screen
->isl_dev
, map
, res
, &surf
->view
);
1746 fill_default_image_param(struct brw_image_param
*param
)
1748 memset(param
, 0, sizeof(*param
));
1749 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
1750 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
1751 * detailed explanation of these parameters.
1753 param
->swizzling
[0] = 0xff;
1754 param
->swizzling
[1] = 0xff;
1758 fill_buffer_image_param(struct brw_image_param
*param
,
1759 enum pipe_format pfmt
,
1762 const unsigned cpp
= util_format_get_blocksize(pfmt
);
1764 fill_default_image_param(param
);
1765 param
->size
[0] = size
/ cpp
;
1766 param
->stride
[0] = cpp
;
1769 #define isl_surf_fill_image_param(x, ...)
1770 #define fill_default_image_param(x, ...)
1771 #define fill_buffer_image_param(x, ...)
1775 * The pipe->set_shader_images() driver hook.
1778 iris_set_shader_images(struct pipe_context
*ctx
,
1779 enum pipe_shader_type p_stage
,
1780 unsigned start_slot
, unsigned count
,
1781 const struct pipe_image_view
*p_images
)
1783 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1784 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1785 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1786 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1787 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1789 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
1791 for (unsigned i
= 0; i
< count
; i
++) {
1792 if (p_images
&& p_images
[i
].resource
) {
1793 const struct pipe_image_view
*img
= &p_images
[i
];
1794 struct iris_resource
*res
= (void *) img
->resource
;
1795 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, &res
->base
);
1797 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
1799 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
1801 // XXX: these are not retained forever, use a separate uploader?
1803 alloc_surface_states(ice
->state
.surface_uploader
,
1804 &shs
->image
[start_slot
+ i
].surface_state
);
1805 if (!unlikely(map
)) {
1806 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1810 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1811 enum isl_format isl_format
=
1812 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
1814 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
)
1815 isl_format
= isl_lower_storage_image_format(devinfo
, isl_format
);
1817 shs
->image
[start_slot
+ i
].access
= img
->shader_access
;
1819 if (res
->base
.target
!= PIPE_BUFFER
) {
1820 struct isl_view view
= {
1821 .format
= isl_format
,
1822 .base_level
= img
->u
.tex
.level
,
1824 .base_array_layer
= img
->u
.tex
.first_layer
,
1825 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
1826 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1830 fill_surface_state(&screen
->isl_dev
, map
, res
, &view
);
1831 isl_surf_fill_image_param(&screen
->isl_dev
,
1832 &shs
->image
[start_slot
+ i
].param
,
1835 fill_buffer_surface_state(&screen
->isl_dev
, res
->bo
, map
,
1836 isl_format
, img
->u
.buf
.offset
,
1838 fill_buffer_image_param(&shs
->image
[start_slot
+ i
].param
,
1839 img
->format
, img
->u
.buf
.size
);
1842 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1843 pipe_resource_reference(&shs
->image
[start_slot
+ i
].surface_state
.res
,
1845 fill_default_image_param(&shs
->image
[start_slot
+ i
].param
);
1849 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1851 /* Broadwell also needs brw_image_params re-uploaded */
1853 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
1854 shs
->cbuf0_needs_upload
= true;
1860 * The pipe->set_sampler_views() driver hook.
1863 iris_set_sampler_views(struct pipe_context
*ctx
,
1864 enum pipe_shader_type p_stage
,
1865 unsigned start
, unsigned count
,
1866 struct pipe_sampler_view
**views
)
1868 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1869 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1870 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1872 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
1874 for (unsigned i
= 0; i
< count
; i
++) {
1875 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1876 &shs
->textures
[start
+ i
], views
[i
]);
1877 struct iris_sampler_view
*view
= (void *) views
[i
];
1879 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
1880 shs
->bound_sampler_views
|= 1 << (start
+ i
);
1884 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
1888 * The pipe->set_tess_state() driver hook.
1891 iris_set_tess_state(struct pipe_context
*ctx
,
1892 const float default_outer_level
[4],
1893 const float default_inner_level
[2])
1895 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1897 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
1898 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
1900 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
1904 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1906 struct iris_surface
*surf
= (void *) p_surf
;
1907 pipe_resource_reference(&p_surf
->texture
, NULL
);
1908 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
1913 iris_set_clip_state(struct pipe_context
*ctx
,
1914 const struct pipe_clip_state
*state
)
1916 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1917 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
1919 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
1921 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
;
1922 shs
->cbuf0_needs_upload
= true;
1926 * The pipe->set_polygon_stipple() driver hook.
1929 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1930 const struct pipe_poly_stipple
*state
)
1932 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1933 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1934 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1938 * The pipe->set_sample_mask() driver hook.
1941 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1943 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1945 /* We only support 16x MSAA, so we have 16 bits of sample maks.
1946 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
1948 ice
->state
.sample_mask
= sample_mask
& 0xffff;
1949 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1953 * The pipe->set_scissor_states() driver hook.
1955 * This corresponds to our SCISSOR_RECT state structures. It's an
1956 * exact match, so we just store them, and memcpy them out later.
1959 iris_set_scissor_states(struct pipe_context
*ctx
,
1960 unsigned start_slot
,
1961 unsigned num_scissors
,
1962 const struct pipe_scissor_state
*rects
)
1964 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1966 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1967 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
1968 /* If the scissor was out of bounds and got clamped to 0 width/height
1969 * at the bounds, the subtraction of 1 from maximums could produce a
1970 * negative number and thus not clip anything. Instead, just provide
1971 * a min > max scissor inside the bounds, which produces the expected
1974 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
1975 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
1978 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
1979 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
1980 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
1985 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1989 * The pipe->set_stencil_ref() driver hook.
1991 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
1994 iris_set_stencil_ref(struct pipe_context
*ctx
,
1995 const struct pipe_stencil_ref
*state
)
1997 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1998 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2000 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2002 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2006 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2008 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2012 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2013 float m00
, float m11
, float m30
, float m31
,
2014 float *xmin
, float *xmax
,
2015 float *ymin
, float *ymax
)
2017 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2018 * Strips and Fans documentation:
2020 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2021 * fixed-point "guardband" range supported by the rasterization hardware"
2025 * "In almost all circumstances, if an object’s vertices are actually
2026 * modified by this clamping (i.e., had X or Y coordinates outside of
2027 * the guardband extent the rendered object will not match the intended
2028 * result. Therefore software should take steps to ensure that this does
2029 * not happen - e.g., by clipping objects such that they do not exceed
2030 * these limits after the Drawing Rectangle is applied."
2032 * I believe the fundamental restriction is that the rasterizer (in
2033 * the SF/WM stages) have a limit on the number of pixels that can be
2034 * rasterized. We need to ensure any coordinates beyond the rasterizer
2035 * limit are handled by the clipper. So effectively that limit becomes
2036 * the clipper's guardband size.
2038 * It goes on to say:
2040 * "In addition, in order to be correctly rendered, objects must have a
2041 * screenspace bounding box not exceeding 8K in the X or Y direction.
2042 * This additional restriction must also be comprehended by software,
2043 * i.e., enforced by use of clipping."
2045 * This makes no sense. Gen7+ hardware supports 16K render targets,
2046 * and you definitely need to be able to draw polygons that fill the
2047 * surface. Our assumption is that the rasterizer was limited to 8K
2048 * on Sandybridge, which only supports 8K surfaces, and it was actually
2049 * increased to 16K on Ivybridge and later.
2051 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2053 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2055 if (m00
!= 0 && m11
!= 0) {
2056 /* First, we compute the screen-space render area */
2057 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2058 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2059 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2060 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2062 /* We want the guardband to be centered on that */
2063 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2064 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2065 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2066 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2068 /* Now we need it in native device coordinates */
2069 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2070 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2071 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2072 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2074 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2075 * flipped upside-down. X should be fine though.
2077 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2078 *xmin
= ndc_gb_xmin
;
2079 *xmax
= ndc_gb_xmax
;
2080 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2081 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2083 /* The viewport scales to 0, so nothing will be rendered. */
2092 * The pipe->set_viewport_states() driver hook.
2094 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2095 * the guardband yet, as we need the framebuffer dimensions, but we can
2096 * at least fill out the rest.
2099 iris_set_viewport_states(struct pipe_context
*ctx
,
2100 unsigned start_slot
,
2102 const struct pipe_viewport_state
*states
)
2104 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2106 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2108 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2110 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2111 !ice
->state
.cso_rast
->depth_clip_far
))
2112 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2116 * The pipe->set_framebuffer_state() driver hook.
2118 * Sets the current draw FBO, including color render targets, depth,
2119 * and stencil buffers.
2122 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2123 const struct pipe_framebuffer_state
*state
)
2125 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2126 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2127 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2128 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2129 struct iris_resource
*zres
;
2130 struct iris_resource
*stencil_res
;
2132 unsigned samples
= util_framebuffer_get_num_samples(state
);
2133 unsigned layers
= util_framebuffer_get_num_layers(state
);
2135 if (cso
->samples
!= samples
) {
2136 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2139 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2140 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2143 if ((cso
->layers
== 0) != (layers
== 0)) {
2144 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2147 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2148 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2151 util_copy_framebuffer_state(cso
, state
);
2152 cso
->samples
= samples
;
2153 cso
->layers
= layers
;
2155 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2157 struct isl_view view
= {
2160 .base_array_layer
= 0,
2162 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2165 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
2168 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2171 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2172 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2174 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2177 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2179 info
.depth_surf
= &zres
->surf
;
2180 info
.depth_address
= zres
->bo
->gtt_offset
;
2181 info
.mocs
= mocs(zres
->bo
);
2183 view
.format
= zres
->surf
.format
;
2187 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2188 info
.stencil_surf
= &stencil_res
->surf
;
2189 info
.stencil_address
= stencil_res
->bo
->gtt_offset
;
2191 view
.format
= stencil_res
->surf
.format
;
2192 info
.mocs
= mocs(stencil_res
->bo
);
2197 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2199 /* Make a null surface for unbound buffers */
2200 void *null_surf_map
=
2201 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2202 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2203 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2204 isl_extent3d(MAX2(cso
->width
, 1),
2205 MAX2(cso
->height
, 1),
2206 cso
->layers
? cso
->layers
: 1));
2207 ice
->state
.null_fb
.offset
+=
2208 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2210 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2212 /* Render target change */
2213 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2215 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2218 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2219 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2221 /* The PIPE_CONTROL command description says:
2223 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2224 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2225 * Target Cache Flush by enabling this bit. When render target flush
2226 * is set due to new association of BTI, PS Scoreboard Stall bit must
2227 * be set in this packet."
2229 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2230 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2231 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2232 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2237 upload_ubo_surf_state(struct iris_context
*ice
,
2238 struct iris_const_buffer
*cbuf
,
2239 unsigned buffer_size
)
2241 struct pipe_context
*ctx
= &ice
->ctx
;
2242 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
2244 // XXX: these are not retained forever, use a separate uploader?
2246 upload_state(ice
->state
.surface_uploader
, &cbuf
->surface_state
,
2247 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2248 if (!unlikely(map
)) {
2249 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2253 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2254 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state
.res
);
2255 cbuf
->surface_state
.offset
+= iris_bo_offset_from_base_address(surf_bo
);
2257 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2258 .address
= res
->bo
->gtt_offset
+ cbuf
->data
.offset
,
2259 .size_B
= MIN2(buffer_size
,
2260 res
->bo
->size
- cbuf
->data
.offset
),
2261 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
2263 .mocs
= mocs(res
->bo
))
2267 * The pipe->set_constant_buffer() driver hook.
2269 * This uploads any constant data in user buffers, and references
2270 * any UBO resources containing constant data.
2273 iris_set_constant_buffer(struct pipe_context
*ctx
,
2274 enum pipe_shader_type p_stage
, unsigned index
,
2275 const struct pipe_constant_buffer
*input
)
2277 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2278 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2279 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2280 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
2282 if (input
&& input
->buffer
) {
2285 pipe_resource_reference(&cbuf
->data
.res
, input
->buffer
);
2286 cbuf
->data
.offset
= input
->buffer_offset
;
2288 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2289 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2291 upload_ubo_surf_state(ice
, cbuf
, input
->buffer_size
);
2293 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2294 pipe_resource_reference(&cbuf
->surface_state
.res
, NULL
);
2299 memcpy(&shs
->cbuf0
, input
, sizeof(shs
->cbuf0
));
2301 memset(&shs
->cbuf0
, 0, sizeof(shs
->cbuf0
));
2303 shs
->cbuf0_needs_upload
= true;
2306 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2307 // XXX: maybe not necessary all the time...?
2308 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2309 // XXX: pull model we may need actual new bindings...
2310 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2314 upload_uniforms(struct iris_context
*ice
,
2315 gl_shader_stage stage
)
2317 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2318 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
2319 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2321 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t) +
2322 shs
->cbuf0
.buffer_size
;
2324 if (upload_size
== 0)
2328 upload_state(ice
->ctx
.const_uploader
, &cbuf
->data
, upload_size
, 64);
2330 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2331 uint32_t sysval
= shader
->system_values
[i
];
2334 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
2335 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
2336 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
2337 struct brw_image_param
*param
= &shs
->image
[img
].param
;
2339 assert(offset
< sizeof(struct brw_image_param
));
2340 value
= ((uint32_t *) param
)[offset
];
2341 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
2343 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2344 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2345 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2346 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2347 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
2348 if (stage
== MESA_SHADER_TESS_CTRL
) {
2349 value
= ice
->state
.vertices_per_patch
;
2351 assert(stage
== MESA_SHADER_TESS_EVAL
);
2352 const struct shader_info
*tcs_info
=
2353 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
2356 value
= tcs_info
->tess
.tcs_vertices_out
;
2359 assert(!"unhandled system value");
2365 if (shs
->cbuf0
.user_buffer
) {
2366 memcpy(map
, shs
->cbuf0
.user_buffer
, shs
->cbuf0
.buffer_size
);
2369 upload_ubo_surf_state(ice
, cbuf
, upload_size
);
2373 * The pipe->set_shader_buffers() driver hook.
2375 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2376 * SURFACE_STATE here, as the buffer offset may change each time.
2379 iris_set_shader_buffers(struct pipe_context
*ctx
,
2380 enum pipe_shader_type p_stage
,
2381 unsigned start_slot
, unsigned count
,
2382 const struct pipe_shader_buffer
*buffers
)
2384 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2385 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2386 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2387 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2389 for (unsigned i
= 0; i
< count
; i
++) {
2390 if (buffers
&& buffers
[i
].buffer
) {
2391 const struct pipe_shader_buffer
*buffer
= &buffers
[i
];
2392 struct iris_resource
*res
= (void *) buffer
->buffer
;
2393 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], &res
->base
);
2395 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2397 // XXX: these are not retained forever, use a separate uploader?
2399 upload_state(ice
->state
.surface_uploader
,
2400 &shs
->ssbo_surface_state
[start_slot
+ i
],
2401 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2402 if (!unlikely(map
)) {
2403 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2407 struct iris_bo
*surf_state_bo
=
2408 iris_resource_bo(shs
->ssbo_surface_state
[start_slot
+ i
].res
);
2409 shs
->ssbo_surface_state
[start_slot
+ i
].offset
+=
2410 iris_bo_offset_from_base_address(surf_state_bo
);
2412 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2414 res
->bo
->gtt_offset
+ buffer
->buffer_offset
,
2416 MIN2(buffer
->buffer_size
,
2417 res
->bo
->size
- buffer
->buffer_offset
),
2418 .format
= ISL_FORMAT_RAW
,
2420 .mocs
= mocs(res
->bo
));
2422 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2423 pipe_resource_reference(&shs
->ssbo_surface_state
[start_slot
+ i
].res
,
2428 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2432 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2438 * The pipe->set_vertex_buffers() driver hook.
2440 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2443 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2444 unsigned start_slot
, unsigned count
,
2445 const struct pipe_vertex_buffer
*buffers
)
2447 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2448 struct iris_genx_state
*genx
= ice
->state
.genx
;
2450 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
2452 for (unsigned i
= 0; i
< count
; i
++) {
2453 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
2454 struct iris_vertex_buffer_state
*state
=
2455 &genx
->vertex_buffers
[start_slot
+ i
];
2458 pipe_resource_reference(&state
->resource
, NULL
);
2462 assert(!buffer
->is_user_buffer
);
2464 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
2466 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
2467 struct iris_resource
*res
= (void *) state
->resource
;
2470 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2472 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
2473 vb
.VertexBufferIndex
= start_slot
+ i
;
2474 vb
.AddressModifyEnable
= true;
2475 vb
.BufferPitch
= buffer
->stride
;
2477 vb
.BufferSize
= res
->bo
->size
;
2478 vb
.BufferStartingAddress
=
2479 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
2480 vb
.MOCS
= mocs(res
->bo
);
2482 vb
.NullVertexBuffer
= true;
2487 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2491 * Gallium CSO for vertex elements.
2493 struct iris_vertex_element_state
{
2494 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2495 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2500 * The pipe->create_vertex_elements() driver hook.
2502 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2503 * and 3DSTATE_VF_INSTANCING commands. SGVs are handled at draw time.
2506 iris_create_vertex_elements(struct pipe_context
*ctx
,
2508 const struct pipe_vertex_element
*state
)
2510 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2511 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2512 struct iris_vertex_element_state
*cso
=
2513 malloc(sizeof(struct iris_vertex_element_state
));
2518 * - create edge flag one
2520 * - if those are necessary, use count + 1/2/3... OR in the length
2522 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2524 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2527 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2528 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2531 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2533 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2534 ve
.Component0Control
= VFCOMP_STORE_0
;
2535 ve
.Component1Control
= VFCOMP_STORE_0
;
2536 ve
.Component2Control
= VFCOMP_STORE_0
;
2537 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2540 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2544 for (int i
= 0; i
< count
; i
++) {
2545 const struct iris_format_info fmt
=
2546 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2547 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2548 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2550 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2551 case 0: comp
[0] = VFCOMP_STORE_0
;
2552 case 1: comp
[1] = VFCOMP_STORE_0
;
2553 case 2: comp
[2] = VFCOMP_STORE_0
;
2555 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2556 : VFCOMP_STORE_1_FP
;
2559 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2560 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2562 ve
.SourceElementOffset
= state
[i
].src_offset
;
2563 ve
.SourceElementFormat
= fmt
.fmt
;
2564 ve
.Component0Control
= comp
[0];
2565 ve
.Component1Control
= comp
[1];
2566 ve
.Component2Control
= comp
[2];
2567 ve
.Component3Control
= comp
[3];
2570 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2571 vi
.VertexElementIndex
= i
;
2572 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2573 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2576 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2577 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2584 * The pipe->bind_vertex_elements_state() driver hook.
2587 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2589 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2590 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2591 struct iris_vertex_element_state
*new_cso
= state
;
2593 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2594 * we need to re-emit it to ensure we're overriding the right one.
2596 if (new_cso
&& cso_changed(count
))
2597 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2599 ice
->state
.cso_vertex_elements
= state
;
2600 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2604 * The pipe->create_stream_output_target() driver hook.
2606 * "Target" here refers to a destination buffer. We translate this into
2607 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2608 * know which buffer this represents, or whether we ought to zero the
2609 * write-offsets, or append. Those are handled in the set() hook.
2611 static struct pipe_stream_output_target
*
2612 iris_create_stream_output_target(struct pipe_context
*ctx
,
2613 struct pipe_resource
*p_res
,
2614 unsigned buffer_offset
,
2615 unsigned buffer_size
)
2617 struct iris_resource
*res
= (void *) p_res
;
2618 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2622 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
2624 pipe_reference_init(&cso
->base
.reference
, 1);
2625 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
2626 cso
->base
.buffer_offset
= buffer_offset
;
2627 cso
->base
.buffer_size
= buffer_size
;
2628 cso
->base
.context
= ctx
;
2630 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
2636 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2637 struct pipe_stream_output_target
*state
)
2639 struct iris_stream_output_target
*cso
= (void *) state
;
2641 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2642 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2648 * The pipe->set_stream_output_targets() driver hook.
2650 * At this point, we know which targets are bound to a particular index,
2651 * and also whether we want to append or start over. We can finish the
2652 * 3DSTATE_SO_BUFFER packets we started earlier.
2655 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2656 unsigned num_targets
,
2657 struct pipe_stream_output_target
**targets
,
2658 const unsigned *offsets
)
2660 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2661 struct iris_genx_state
*genx
= ice
->state
.genx
;
2662 uint32_t *so_buffers
= genx
->so_buffers
;
2664 const bool active
= num_targets
> 0;
2665 if (ice
->state
.streamout_active
!= active
) {
2666 ice
->state
.streamout_active
= active
;
2667 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2669 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
2670 * it's a non-pipelined command. If we're switching streamout on, we
2671 * may have missed emitting it earlier, so do so now. (We're already
2672 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
2675 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
2678 for (int i
= 0; i
< 4; i
++) {
2679 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2680 i
< num_targets
? targets
[i
] : NULL
);
2683 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2687 for (unsigned i
= 0; i
< 4; i
++,
2688 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2690 if (i
>= num_targets
|| !targets
[i
]) {
2691 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
2692 sob
.SOBufferIndex
= i
;
2696 struct iris_stream_output_target
*tgt
= (void *) targets
[i
];
2697 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
2699 /* Note that offsets[i] will either be 0, causing us to zero
2700 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
2701 * "continue appending at the existing offset."
2703 assert(offsets
[i
] == 0 || offsets
[i
] == 0xFFFFFFFF);
2705 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
2706 sob
.SurfaceBaseAddress
=
2707 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
2708 sob
.SOBufferEnable
= true;
2709 sob
.StreamOffsetWriteEnable
= true;
2710 sob
.StreamOutputBufferOffsetAddressEnable
= true;
2711 sob
.MOCS
= mocs(res
->bo
);
2713 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
2715 sob
.SOBufferIndex
= i
;
2716 sob
.StreamOffset
= offsets
[i
];
2717 sob
.StreamOutputBufferOffsetAddress
=
2718 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
2719 tgt
->offset
.offset
);
2723 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
2727 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
2728 * 3DSTATE_STREAMOUT packets.
2730 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
2731 * hardware to record. We can create it entirely based on the shader, with
2732 * no dynamic state dependencies.
2734 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
2735 * state-based settings. We capture the shader-related ones here, and merge
2736 * the rest in at draw time.
2739 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
2740 const struct brw_vue_map
*vue_map
)
2742 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2743 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2744 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2745 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2747 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2749 memset(so_decl
, 0, sizeof(so_decl
));
2751 /* Construct the list of SO_DECLs to be emitted. The formatting of the
2752 * command feels strange -- each dword pair contains a SO_DECL per stream.
2754 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
2755 const struct pipe_stream_output
*output
= &info
->output
[i
];
2756 const int buffer
= output
->output_buffer
;
2757 const int varying
= output
->register_index
;
2758 const unsigned stream_id
= output
->stream
;
2759 assert(stream_id
< MAX_VERTEX_STREAMS
);
2761 buffer_mask
[stream_id
] |= 1 << buffer
;
2763 assert(vue_map
->varying_to_slot
[varying
] >= 0);
2765 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
2766 * array. Instead, it simply increments DstOffset for the following
2767 * input by the number of components that should be skipped.
2769 * Our hardware is unusual in that it requires us to program SO_DECLs
2770 * for fake "hole" components, rather than simply taking the offset
2771 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
2772 * program as many size = 4 holes as we can, then a final hole to
2773 * accommodate the final 1, 2, or 3 remaining.
2775 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
2777 while (skip_components
> 0) {
2778 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2780 .OutputBufferSlot
= output
->output_buffer
,
2781 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
2783 skip_components
-= 4;
2786 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
2788 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2789 .OutputBufferSlot
= output
->output_buffer
,
2790 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
2792 ((1 << output
->num_components
) - 1) << output
->start_component
,
2795 if (decls
[stream_id
] > max_decls
)
2796 max_decls
= decls
[stream_id
];
2799 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
2800 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
2801 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
2803 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
2804 int urb_entry_read_offset
= 0;
2805 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
2806 urb_entry_read_offset
;
2808 /* We always read the whole vertex. This could be reduced at some
2809 * point by reading less and offsetting the register index in the
2812 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
2813 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
2814 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
2815 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
2816 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
2817 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
2818 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
2819 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
2821 /* Set buffer pitches; 0 means unbound. */
2822 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
2823 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
2824 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
2825 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
2828 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
2829 list
.DWordLength
= 3 + 2 * max_decls
- 2;
2830 list
.StreamtoBufferSelects0
= buffer_mask
[0];
2831 list
.StreamtoBufferSelects1
= buffer_mask
[1];
2832 list
.StreamtoBufferSelects2
= buffer_mask
[2];
2833 list
.StreamtoBufferSelects3
= buffer_mask
[3];
2834 list
.NumEntries0
= decls
[0];
2835 list
.NumEntries1
= decls
[1];
2836 list
.NumEntries2
= decls
[2];
2837 list
.NumEntries3
= decls
[3];
2840 for (int i
= 0; i
< max_decls
; i
++) {
2841 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
2842 entry
.Stream0Decl
= so_decl
[0][i
];
2843 entry
.Stream1Decl
= so_decl
[1][i
];
2844 entry
.Stream2Decl
= so_decl
[2][i
];
2845 entry
.Stream3Decl
= so_decl
[3][i
];
2853 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
2854 const struct brw_vue_map
*last_vue_map
,
2855 bool two_sided_color
,
2856 unsigned *out_offset
,
2857 unsigned *out_length
)
2859 /* The compiler computes the first URB slot without considering COL/BFC
2860 * swizzling (because it doesn't know whether it's enabled), so we need
2861 * to do that here too. This may result in a smaller offset, which
2864 const unsigned first_slot
=
2865 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
2867 /* This becomes the URB read offset (counted in pairs of slots). */
2868 assert(first_slot
% 2 == 0);
2869 *out_offset
= first_slot
/ 2;
2871 /* We need to adjust the inputs read to account for front/back color
2872 * swizzling, as it can make the URB length longer.
2874 for (int c
= 0; c
<= 1; c
++) {
2875 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
2876 /* If two sided color is enabled, the fragment shader's gl_Color
2877 * (COL0) input comes from either the gl_FrontColor (COL0) or
2878 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
2880 if (two_sided_color
)
2881 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2883 /* If front color isn't written, we opt to give them back color
2884 * instead of an undefined value. Switch from COL to BFC.
2886 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
2887 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
2888 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2893 /* Compute the minimum URB Read Length necessary for the FS inputs.
2895 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
2896 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
2898 * "This field should be set to the minimum length required to read the
2899 * maximum source attribute. The maximum source attribute is indicated
2900 * by the maximum value of the enabled Attribute # Source Attribute if
2901 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
2902 * enable is not set.
2903 * read_length = ceiling((max_source_attr + 1) / 2)
2905 * [errata] Corruption/Hang possible if length programmed larger than
2908 * Similar text exists for Ivy Bridge.
2910 * We find the last URB slot that's actually read by the FS.
2912 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
2913 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
2914 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
2917 /* The URB read length is the difference of the two, counted in pairs. */
2918 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
2922 iris_emit_sbe_swiz(struct iris_batch
*batch
,
2923 const struct iris_context
*ice
,
2924 unsigned urb_read_offset
,
2925 unsigned sprite_coord_enables
)
2927 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
2928 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2929 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2930 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
2931 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2933 /* XXX: this should be generated when putting programs in place */
2935 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
2936 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
2937 if (input_index
< 0 || input_index
>= 16)
2940 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
2941 &attr_overrides
[input_index
];
2942 int slot
= vue_map
->varying_to_slot
[fs_attr
];
2944 /* Viewport and Layer are stored in the VUE header. We need to override
2945 * them to zero if earlier stages didn't write them, as GL requires that
2946 * they read back as zero when not explicitly set.
2949 case VARYING_SLOT_VIEWPORT
:
2950 case VARYING_SLOT_LAYER
:
2951 attr
->ComponentOverrideX
= true;
2952 attr
->ComponentOverrideW
= true;
2953 attr
->ConstantSource
= CONST_0000
;
2955 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
2956 attr
->ComponentOverrideY
= true;
2957 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
2958 attr
->ComponentOverrideZ
= true;
2961 case VARYING_SLOT_PRIMITIVE_ID
:
2962 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
2964 attr
->ComponentOverrideX
= true;
2965 attr
->ComponentOverrideY
= true;
2966 attr
->ComponentOverrideZ
= true;
2967 attr
->ComponentOverrideW
= true;
2968 attr
->ConstantSource
= PRIM_ID
;
2976 if (sprite_coord_enables
& (1 << input_index
))
2979 /* If there was only a back color written but not front, use back
2980 * as the color instead of undefined.
2982 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
2983 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
2984 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
2985 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
2987 /* Not written by the previous stage - undefined. */
2989 attr
->ComponentOverrideX
= true;
2990 attr
->ComponentOverrideY
= true;
2991 attr
->ComponentOverrideZ
= true;
2992 attr
->ComponentOverrideW
= true;
2993 attr
->ConstantSource
= CONST_0001_FLOAT
;
2997 /* Compute the location of the attribute relative to the read offset,
2998 * which is counted in 256-bit increments (two 128-bit VUE slots).
3000 const int source_attr
= slot
- 2 * urb_read_offset
;
3001 assert(source_attr
>= 0 && source_attr
<= 32);
3002 attr
->SourceAttribute
= source_attr
;
3004 /* If we are doing two-sided color, and the VUE slot following this one
3005 * represents a back-facing color, then we need to instruct the SF unit
3006 * to do back-facing swizzling.
3008 if (cso_rast
->light_twoside
&&
3009 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3010 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3011 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3012 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3013 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3016 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3017 for (int i
= 0; i
< 16; i
++)
3018 sbes
.Attribute
[i
] = attr_overrides
[i
];
3023 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3024 const struct iris_rasterizer_state
*cso
)
3026 unsigned overrides
= 0;
3028 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
3029 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
3031 for (int i
= 0; i
< 8; i
++) {
3032 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
3033 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
3034 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
3041 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
3043 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3044 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3045 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3046 const struct shader_info
*fs_info
=
3047 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
3049 unsigned urb_read_offset
, urb_read_length
;
3050 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
3051 ice
->shaders
.last_vue_map
,
3052 cso_rast
->light_twoside
,
3053 &urb_read_offset
, &urb_read_length
);
3055 unsigned sprite_coord_overrides
=
3056 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3058 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
3059 sbe
.AttributeSwizzleEnable
= true;
3060 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3061 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3062 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3063 sbe
.VertexURBEntryReadLength
= urb_read_length
;
3064 sbe
.ForceVertexURBEntryReadOffset
= true;
3065 sbe
.ForceVertexURBEntryReadLength
= true;
3066 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3067 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
3069 for (int i
= 0; i
< 32; i
++) {
3070 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3075 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
3078 /* ------------------------------------------------------------------- */
3081 * Populate VS program key fields based on the current state.
3084 iris_populate_vs_key(const struct iris_context
*ice
,
3085 const struct shader_info
*info
,
3086 struct brw_vs_prog_key
*key
)
3088 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3090 if (info
->clip_distance_array_size
== 0 &&
3091 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)))
3092 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3096 * Populate TCS program key fields based on the current state.
3099 iris_populate_tcs_key(const struct iris_context
*ice
,
3100 struct brw_tcs_prog_key
*key
)
3105 * Populate TES program key fields based on the current state.
3108 iris_populate_tes_key(const struct iris_context
*ice
,
3109 struct brw_tes_prog_key
*key
)
3114 * Populate GS program key fields based on the current state.
3117 iris_populate_gs_key(const struct iris_context
*ice
,
3118 struct brw_gs_prog_key
*key
)
3123 * Populate FS program key fields based on the current state.
3126 iris_populate_fs_key(const struct iris_context
*ice
,
3127 struct brw_wm_prog_key
*key
)
3129 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3130 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3131 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3132 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3134 key
->nr_color_regions
= fb
->nr_cbufs
;
3136 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3138 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
3139 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
3141 /* XXX: only bother if COL0/1 are read */
3142 key
->flat_shade
= rast
->flatshade
;
3144 key
->persample_interp
= rast
->force_persample_interp
;
3145 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3147 key
->coherent_fb_fetch
= true;
3149 // XXX: key->force_dual_color_blend for unigine
3150 // XXX: respect hint for high_quality_derivatives:1;
3154 iris_populate_cs_key(const struct iris_context
*ice
,
3155 struct brw_cs_prog_key
*key
)
3160 // XXX: these need to go in INIT_THREAD_DISPATCH_FIELDS
3161 pkt
.SamplerCount
= \
3162 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4); \
3167 KSP(const struct iris_compiled_shader
*shader
)
3169 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3170 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3173 // Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3174 // prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3175 // this WA on C0 stepping.
3177 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3178 pkt.KernelStartPointer = KSP(shader); \
3179 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3180 prog_data->binding_table.size_bytes / 4; \
3181 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3183 pkt.DispatchGRFStartRegisterForURBData = \
3184 prog_data->dispatch_grf_start_reg; \
3185 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3186 pkt.prefix##URBEntryReadOffset = 0; \
3188 pkt.StatisticsEnable = true; \
3189 pkt.Enable = true; \
3191 if (prog_data->total_scratch) { \
3192 struct iris_bo *bo = \
3193 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3194 uint32_t scratch_addr = bo->gtt_offset; \
3195 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3196 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3200 * Encode most of 3DSTATE_VS based on the compiled shader.
3203 iris_store_vs_state(struct iris_context
*ice
,
3204 const struct gen_device_info
*devinfo
,
3205 struct iris_compiled_shader
*shader
)
3207 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3208 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3210 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3211 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3212 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3213 vs
.SIMD8DispatchEnable
= true;
3214 vs
.UserClipDistanceCullTestEnableBitmask
=
3215 vue_prog_data
->cull_distance_mask
;
3220 * Encode most of 3DSTATE_HS based on the compiled shader.
3223 iris_store_tcs_state(struct iris_context
*ice
,
3224 const struct gen_device_info
*devinfo
,
3225 struct iris_compiled_shader
*shader
)
3227 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3228 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3229 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3231 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3232 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3234 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3235 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3236 hs
.IncludeVertexHandles
= true;
3241 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3244 iris_store_tes_state(struct iris_context
*ice
,
3245 const struct gen_device_info
*devinfo
,
3246 struct iris_compiled_shader
*shader
)
3248 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3249 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3250 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3252 uint32_t *te_state
= (void *) shader
->derived_data
;
3253 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3255 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3256 te
.Partitioning
= tes_prog_data
->partitioning
;
3257 te
.OutputTopology
= tes_prog_data
->output_topology
;
3258 te
.TEDomain
= tes_prog_data
->domain
;
3260 te
.MaximumTessellationFactorOdd
= 63.0;
3261 te
.MaximumTessellationFactorNotOdd
= 64.0;
3264 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3265 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3267 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3268 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3269 ds
.ComputeWCoordinateEnable
=
3270 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3272 ds
.UserClipDistanceCullTestEnableBitmask
=
3273 vue_prog_data
->cull_distance_mask
;
3279 * Encode most of 3DSTATE_GS based on the compiled shader.
3282 iris_store_gs_state(struct iris_context
*ice
,
3283 const struct gen_device_info
*devinfo
,
3284 struct iris_compiled_shader
*shader
)
3286 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3287 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3288 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3290 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3291 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3293 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3294 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3295 gs
.ControlDataHeaderSize
=
3296 gs_prog_data
->control_data_header_size_hwords
;
3297 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3298 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3299 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3300 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3301 gs
.ReorderMode
= TRAILING
;
3302 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3303 gs
.MaximumNumberofThreads
=
3304 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3305 : (devinfo
->max_gs_threads
- 1);
3307 if (gs_prog_data
->static_vertex_count
!= -1) {
3308 gs
.StaticOutput
= true;
3309 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3311 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3313 gs
.UserClipDistanceCullTestEnableBitmask
=
3314 vue_prog_data
->cull_distance_mask
;
3316 const int urb_entry_write_offset
= 1;
3317 const uint32_t urb_entry_output_length
=
3318 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3319 urb_entry_write_offset
;
3321 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3322 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3327 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3330 iris_store_fs_state(struct iris_context
*ice
,
3331 const struct gen_device_info
*devinfo
,
3332 struct iris_compiled_shader
*shader
)
3334 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3335 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3337 uint32_t *ps_state
= (void *) shader
->derived_data
;
3338 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3340 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3341 ps
.VectorMaskEnable
= true;
3342 //ps.SamplerCount = ...
3343 // XXX: WABTPPrefetchDisable, see above, drop at C0
3344 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3345 prog_data
->binding_table
.size_bytes
/ 4;
3346 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3347 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3349 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
3351 /* From the documentation for this packet:
3352 * "If the PS kernel does not need the Position XY Offsets to
3353 * compute a Position Value, then this field should be programmed
3354 * to POSOFFSET_NONE."
3356 * "SW Recommendation: If the PS kernel needs the Position Offsets
3357 * to compute a Position XY value, this field should match Position
3358 * ZW Interpolation Mode to ensure a consistent position.xyzw
3361 * We only require XY sample offsets. So, this recommendation doesn't
3362 * look useful at the moment. We might need this in future.
3364 ps
.PositionXYOffsetSelect
=
3365 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3366 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
3367 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
3368 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
3370 // XXX: Disable SIMD32 with 16x MSAA
3372 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3373 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
3374 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
3375 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
3376 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3377 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
3379 ps
.KernelStartPointer0
=
3380 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
3381 ps
.KernelStartPointer1
=
3382 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
3383 ps
.KernelStartPointer2
=
3384 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
3386 if (prog_data
->total_scratch
) {
3387 struct iris_bo
*bo
=
3388 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3389 MESA_SHADER_FRAGMENT
);
3390 uint32_t scratch_addr
= bo
->gtt_offset
;
3391 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3392 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3396 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3397 psx
.PixelShaderValid
= true;
3398 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3399 // XXX: alpha test / alpha to coverage :/
3400 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
||
3401 wm_prog_data
->uses_omask
;
3402 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3403 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3404 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3405 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3406 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3409 if (wm_prog_data
->uses_sample_mask
) {
3410 /* TODO: conservative rasterization */
3411 if (wm_prog_data
->post_depth_coverage
)
3412 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
3414 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
3417 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3418 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3420 psx
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
3427 * Compute the size of the derived data (shader command packets).
3429 * This must match the data written by the iris_store_xs_state() functions.
3432 iris_store_cs_state(struct iris_context
*ice
,
3433 const struct gen_device_info
*devinfo
,
3434 struct iris_compiled_shader
*shader
)
3436 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3437 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3438 void *map
= shader
->derived_data
;
3440 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3441 desc
.KernelStartPointer
= KSP(shader
);
3442 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3443 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3444 desc
.SharedLocalMemorySize
=
3445 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3446 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3447 desc
.CrossThreadConstantDataReadLength
=
3448 cs_prog_data
->push
.cross_thread
.regs
;
3453 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3455 assert(cache_id
<= IRIS_CACHE_BLORP
);
3457 static const unsigned dwords
[] = {
3458 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3459 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3460 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3461 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3463 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3464 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3465 [IRIS_CACHE_BLORP
] = 0,
3468 return sizeof(uint32_t) * dwords
[cache_id
];
3472 * Create any state packets corresponding to the given shader stage
3473 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3474 * This means that we can look up a program in the in-memory cache and
3475 * get most of the state packet without having to reconstruct it.
3478 iris_store_derived_program_state(struct iris_context
*ice
,
3479 enum iris_program_cache_id cache_id
,
3480 struct iris_compiled_shader
*shader
)
3482 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3483 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3487 iris_store_vs_state(ice
, devinfo
, shader
);
3489 case IRIS_CACHE_TCS
:
3490 iris_store_tcs_state(ice
, devinfo
, shader
);
3492 case IRIS_CACHE_TES
:
3493 iris_store_tes_state(ice
, devinfo
, shader
);
3496 iris_store_gs_state(ice
, devinfo
, shader
);
3499 iris_store_fs_state(ice
, devinfo
, shader
);
3502 iris_store_cs_state(ice
, devinfo
, shader
);
3503 case IRIS_CACHE_BLORP
:
3510 /* ------------------------------------------------------------------- */
3513 * Configure the URB.
3515 * XXX: write a real comment.
3518 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
3520 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
3521 const unsigned push_size_kB
= 32;
3522 unsigned entries
[4];
3526 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3527 if (!ice
->shaders
.prog
[i
]) {
3530 struct brw_vue_prog_data
*vue_prog_data
=
3531 (void *) ice
->shaders
.prog
[i
]->prog_data
;
3532 size
[i
] = vue_prog_data
->urb_entry_size
;
3534 assert(size
[i
] != 0);
3537 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
3538 1024 * ice
->shaders
.urb_size
,
3539 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
3540 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
3541 size
, entries
, start
);
3543 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3544 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
3545 urb
._3DCommandSubOpcode
+= i
;
3546 urb
.VSURBStartingAddress
= start
[i
];
3547 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
3548 urb
.VSNumberofURBEntries
= entries
[i
];
3553 static const uint32_t push_constant_opcodes
[] = {
3554 [MESA_SHADER_VERTEX
] = 21,
3555 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3556 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3557 [MESA_SHADER_GEOMETRY
] = 22,
3558 [MESA_SHADER_FRAGMENT
] = 23,
3559 [MESA_SHADER_COMPUTE
] = 0,
3563 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3565 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3567 iris_use_pinned_bo(batch
, state_bo
, false);
3569 return ice
->state
.unbound_tex
.offset
;
3573 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3575 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3576 if (!ice
->state
.null_fb
.res
)
3577 return use_null_surface(batch
, ice
);
3579 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3581 iris_use_pinned_bo(batch
, state_bo
, false);
3583 return ice
->state
.null_fb
.offset
;
3587 * Add a surface to the validation list, as well as the buffer containing
3588 * the corresponding SURFACE_STATE.
3590 * Returns the binding table entry (offset to SURFACE_STATE).
3593 use_surface(struct iris_batch
*batch
,
3594 struct pipe_surface
*p_surf
,
3597 struct iris_surface
*surf
= (void *) p_surf
;
3599 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
3600 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
3602 return surf
->surface_state
.offset
;
3606 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
3608 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
3609 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
3611 return isv
->surface_state
.offset
;
3615 use_const_buffer(struct iris_batch
*batch
,
3616 struct iris_context
*ice
,
3617 struct iris_const_buffer
*cbuf
)
3619 if (!cbuf
->surface_state
.res
)
3620 return use_null_surface(batch
, ice
);
3622 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->data
.res
), false);
3623 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->surface_state
.res
), false);
3625 return cbuf
->surface_state
.offset
;
3629 use_ssbo(struct iris_batch
*batch
, struct iris_context
*ice
,
3630 struct iris_shader_state
*shs
, int i
)
3633 return use_null_surface(batch
, ice
);
3635 struct iris_state_ref
*surf_state
= &shs
->ssbo_surface_state
[i
];
3637 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->ssbo
[i
]), true);
3638 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3640 return surf_state
->offset
;
3644 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
3645 struct iris_shader_state
*shs
, int i
)
3647 if (!shs
->image
[i
].res
)
3648 return use_null_surface(batch
, ice
);
3650 struct iris_state_ref
*surf_state
= &shs
->image
[i
].surface_state
;
3652 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->image
[i
].res
),
3653 shs
->image
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
);
3654 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3656 return surf_state
->offset
;
3659 #define push_bt_entry(addr) \
3660 assert(addr >= binder_addr); \
3661 assert(s < prog_data->binding_table.size_bytes / sizeof(uint32_t)); \
3662 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
3664 #define bt_assert(section, exists) \
3665 if (!pin_only) assert(prog_data->binding_table.section == \
3666 (exists) ? s : 0xd0d0d0d0)
3669 * Populate the binding table for a given shader stage.
3671 * This fills out the table of pointers to surfaces required by the shader,
3672 * and also adds those buffers to the validation list so the kernel can make
3673 * resident before running our batch.
3676 iris_populate_binding_table(struct iris_context
*ice
,
3677 struct iris_batch
*batch
,
3678 gl_shader_stage stage
,
3681 const struct iris_binder
*binder
= &ice
->state
.binder
;
3682 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3686 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3687 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3688 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
3690 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
3691 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
3694 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
3696 /* TCS passthrough doesn't need a binding table. */
3697 assert(stage
== MESA_SHADER_TESS_CTRL
);
3701 if (stage
== MESA_SHADER_COMPUTE
) {
3702 /* surface for gl_NumWorkGroups */
3703 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
3704 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
3705 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
3706 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
3707 push_bt_entry(grid_state
->offset
);
3710 if (stage
== MESA_SHADER_FRAGMENT
) {
3711 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3712 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
3713 if (cso_fb
->nr_cbufs
) {
3714 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
3716 cso_fb
->cbufs
[i
] ? use_surface(batch
, cso_fb
->cbufs
[i
], true)
3717 : use_null_fb_surface(batch
, ice
);
3718 push_bt_entry(addr
);
3721 uint32_t addr
= use_null_fb_surface(batch
, ice
);
3722 push_bt_entry(addr
);
3726 bt_assert(texture_start
, info
->num_textures
> 0);
3728 for (int i
= 0; i
< info
->num_textures
; i
++) {
3729 struct iris_sampler_view
*view
= shs
->textures
[i
];
3730 uint32_t addr
= view
? use_sampler_view(batch
, view
)
3731 : use_null_surface(batch
, ice
);
3732 push_bt_entry(addr
);
3735 bt_assert(image_start
, info
->num_images
> 0);
3737 for (int i
= 0; i
< info
->num_images
; i
++) {
3738 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
3739 push_bt_entry(addr
);
3742 const int num_ubos
= iris_get_shader_num_ubos(ice
, stage
);
3744 bt_assert(ubo_start
, num_ubos
> 0);
3746 for (int i
= 0; i
< num_ubos
; i
++) {
3747 uint32_t addr
= use_const_buffer(batch
, ice
, &shs
->constbuf
[i
]);
3748 push_bt_entry(addr
);
3751 bt_assert(ssbo_start
, info
->num_abos
+ info
->num_ssbos
> 0);
3753 /* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
3754 * for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
3755 * in st_atom_storagebuf.c so it'll compact them into one range, with
3756 * SSBOs starting at info->num_abos. Ideally it'd reset num_abos to 0 too
3758 if (info
->num_abos
+ info
->num_ssbos
> 0) {
3759 for (int i
= 0; i
< IRIS_MAX_ABOS
+ info
->num_ssbos
; i
++) {
3760 uint32_t addr
= use_ssbo(batch
, ice
, shs
, i
);
3761 push_bt_entry(addr
);
3766 // XXX: not implemented yet
3767 bt_assert(plane_start
[1], ...);
3768 bt_assert(plane_start
[2], ...);
3773 iris_use_optional_res(struct iris_batch
*batch
,
3774 struct pipe_resource
*res
,
3778 struct iris_bo
*bo
= iris_resource_bo(res
);
3779 iris_use_pinned_bo(batch
, bo
, writeable
);
3783 /* ------------------------------------------------------------------- */
3786 * Pin any BOs which were installed by a previous batch, and restored
3787 * via the hardware logical context mechanism.
3789 * We don't need to re-emit all state every batch - the hardware context
3790 * mechanism will save and restore it for us. This includes pointers to
3791 * various BOs...which won't exist unless we ask the kernel to pin them
3792 * by adding them to the validation list.
3794 * We can skip buffers if we've re-emitted those packets, as we're
3795 * overwriting those stale pointers with new ones, and don't actually
3796 * refer to the old BOs.
3799 iris_restore_render_saved_bos(struct iris_context
*ice
,
3800 struct iris_batch
*batch
,
3801 const struct pipe_draw_info
*draw
)
3803 struct iris_genx_state
*genx
= ice
->state
.genx
;
3805 const uint64_t clean
= ~ice
->state
.dirty
;
3807 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
3808 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
3811 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3812 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
3815 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
3816 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
3819 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3820 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
3823 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
3824 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
3827 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
3828 for (int i
= 0; i
< 4; i
++) {
3829 struct iris_stream_output_target
*tgt
=
3830 (void *) ice
->state
.so_target
[i
];
3832 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
3834 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
3840 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3841 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
3844 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3845 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3850 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3852 for (int i
= 0; i
< 4; i
++) {
3853 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3855 if (range
->length
== 0)
3858 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3859 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3862 iris_use_pinned_bo(batch
, res
->bo
, false);
3864 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3868 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3869 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
3870 /* Re-pin any buffers referred to by the binding table. */
3871 iris_populate_binding_table(ice
, batch
, stage
, true);
3875 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3876 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3877 struct pipe_resource
*res
= shs
->sampler_table
.res
;
3879 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3882 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3883 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
3884 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3887 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3888 iris_use_pinned_bo(batch
, bo
, false);
3890 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3892 if (prog_data
->total_scratch
> 0) {
3893 struct iris_bo
*bo
=
3894 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
3895 iris_use_pinned_bo(batch
, bo
, true);
3901 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
3902 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3904 if (cso_fb
->zsbuf
) {
3905 struct iris_resource
*zres
, *sres
;
3906 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
3909 iris_use_pinned_bo(batch
, zres
->bo
,
3910 ice
->state
.depth_writes_enabled
);
3913 iris_use_pinned_bo(batch
, sres
->bo
,
3914 ice
->state
.stencil_writes_enabled
);
3919 if (draw
->index_size
== 0 && ice
->state
.last_res
.index_buffer
) {
3920 /* This draw didn't emit a new index buffer, so we are inheriting the
3921 * older index buffer. This draw didn't need it, but future ones may.
3923 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
3924 iris_use_pinned_bo(batch
, bo
, false);
3927 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
3928 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
3930 const int i
= u_bit_scan64(&bound
);
3931 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
3932 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3938 iris_restore_compute_saved_bos(struct iris_context
*ice
,
3939 struct iris_batch
*batch
,
3940 const struct pipe_grid_info
*grid
)
3942 const uint64_t clean
= ~ice
->state
.dirty
;
3944 const int stage
= MESA_SHADER_COMPUTE
;
3945 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3947 if (clean
& IRIS_DIRTY_CONSTANTS_CS
) {
3948 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3951 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3952 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[0];
3954 if (range
->length
> 0) {
3955 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3956 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3959 iris_use_pinned_bo(batch
, res
->bo
, false);
3961 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3966 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
3967 /* Re-pin any buffers referred to by the binding table. */
3968 iris_populate_binding_table(ice
, batch
, stage
, true);
3971 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
3973 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
3975 if (clean
& IRIS_DIRTY_CS
) {
3976 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3979 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3980 iris_use_pinned_bo(batch
, bo
, false);
3982 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3984 if (prog_data
->total_scratch
> 0) {
3985 struct iris_bo
*bo
=
3986 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
3987 iris_use_pinned_bo(batch
, bo
, true);
3994 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
3997 iris_update_surface_base_address(struct iris_batch
*batch
,
3998 struct iris_binder
*binder
)
4000 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
4003 flush_for_state_base_change(batch
);
4005 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
4006 sba
.SurfaceStateMOCS
= MOCS_WB
;
4007 sba
.SurfaceStateBaseAddressModifyEnable
= true;
4008 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
4011 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
4015 iris_upload_dirty_render_state(struct iris_context
*ice
,
4016 struct iris_batch
*batch
,
4017 const struct pipe_draw_info
*draw
)
4019 const uint64_t dirty
= ice
->state
.dirty
;
4021 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
4024 struct iris_genx_state
*genx
= ice
->state
.genx
;
4025 struct iris_binder
*binder
= &ice
->state
.binder
;
4026 struct brw_wm_prog_data
*wm_prog_data
= (void *)
4027 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
4029 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
4030 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4031 uint32_t cc_vp_address
;
4033 /* XXX: could avoid streaming for depth_clip [0,1] case. */
4034 uint32_t *cc_vp_map
=
4035 stream_state(batch
, ice
->state
.dynamic_uploader
,
4036 &ice
->state
.last_res
.cc_vp
,
4037 4 * ice
->state
.num_viewports
*
4038 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
4039 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4041 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
4042 cso_rast
->clip_halfz
, &zmin
, &zmax
);
4043 if (cso_rast
->depth_clip_near
)
4045 if (cso_rast
->depth_clip_far
)
4048 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
4049 ccv
.MinimumDepth
= zmin
;
4050 ccv
.MaximumDepth
= zmax
;
4053 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
4056 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
4057 ptr
.CCViewportPointer
= cc_vp_address
;
4061 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4062 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4063 uint32_t sf_cl_vp_address
;
4065 stream_state(batch
, ice
->state
.dynamic_uploader
,
4066 &ice
->state
.last_res
.sf_cl_vp
,
4067 4 * ice
->state
.num_viewports
*
4068 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
4070 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4071 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
4072 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
4074 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
4075 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
4076 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
4077 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
4079 calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
4080 state
->scale
[0], state
->scale
[1],
4081 state
->translate
[0], state
->translate
[1],
4082 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
4084 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
4085 vp
.ViewportMatrixElementm00
= state
->scale
[0];
4086 vp
.ViewportMatrixElementm11
= state
->scale
[1];
4087 vp
.ViewportMatrixElementm22
= state
->scale
[2];
4088 vp
.ViewportMatrixElementm30
= state
->translate
[0];
4089 vp
.ViewportMatrixElementm31
= state
->translate
[1];
4090 vp
.ViewportMatrixElementm32
= state
->translate
[2];
4091 vp
.XMinClipGuardband
= gb_xmin
;
4092 vp
.XMaxClipGuardband
= gb_xmax
;
4093 vp
.YMinClipGuardband
= gb_ymin
;
4094 vp
.YMaxClipGuardband
= gb_ymax
;
4095 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
4096 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
4097 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
4098 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
4101 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
4104 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
4105 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
4109 if (dirty
& IRIS_DIRTY_URB
) {
4110 iris_upload_urb_config(ice
, batch
);
4113 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
4114 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4115 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4116 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4117 const int header_dwords
= GENX(BLEND_STATE_length
);
4118 const int rt_dwords
= cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
);
4119 uint32_t blend_offset
;
4120 uint32_t *blend_map
=
4121 stream_state(batch
, ice
->state
.dynamic_uploader
,
4122 &ice
->state
.last_res
.blend
,
4123 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4125 uint32_t blend_state_header
;
4126 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4127 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4128 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4131 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4132 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4134 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4135 ptr
.BlendStatePointer
= blend_offset
;
4136 ptr
.BlendStatePointerValid
= true;
4140 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4141 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4143 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4147 stream_state(batch
, ice
->state
.dynamic_uploader
,
4148 &ice
->state
.last_res
.color_calc
,
4149 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4151 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4152 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4153 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4154 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4155 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4156 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4157 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4159 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4160 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4163 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4164 ptr
.ColorCalcStatePointer
= cc_offset
;
4165 ptr
.ColorCalcStatePointerValid
= true;
4169 /* Upload constants for TCS passthrough. */
4170 if ((dirty
& IRIS_DIRTY_CONSTANTS_TCS
) &&
4171 ice
->shaders
.prog
[MESA_SHADER_TESS_CTRL
] &&
4172 !ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
]) {
4173 struct iris_compiled_shader
*tes_shader
= ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
4176 /* Passthrough always copies 2 vec4s, so when uploading data we ensure
4177 * it is in the right layout for TES.
4180 struct brw_tes_prog_data
*tes_prog_data
= (void *) tes_shader
->prog_data
;
4181 switch (tes_prog_data
->domain
) {
4182 case BRW_TESS_DOMAIN_QUAD
:
4183 for (int i
= 0; i
< 4; i
++)
4184 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4185 hdr
[3] = ice
->state
.default_inner_level
[0];
4186 hdr
[2] = ice
->state
.default_inner_level
[1];
4188 case BRW_TESS_DOMAIN_TRI
:
4189 for (int i
= 0; i
< 3; i
++)
4190 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4191 hdr
[4] = ice
->state
.default_inner_level
[0];
4193 case BRW_TESS_DOMAIN_ISOLINE
:
4194 hdr
[7] = ice
->state
.default_outer_level
[1];
4195 hdr
[6] = ice
->state
.default_outer_level
[0];
4199 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
4200 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
4201 u_upload_data(ice
->ctx
.const_uploader
, 0, sizeof(hdr
), 32,
4202 &hdr
[0], &cbuf
->data
.offset
,
4206 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4207 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4210 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4211 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4216 if (shs
->cbuf0_needs_upload
)
4217 upload_uniforms(ice
, stage
);
4219 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4221 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4222 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4224 /* The Skylake PRM contains the following restriction:
4226 * "The driver must ensure The following case does not occur
4227 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4228 * buffer 3 read length equal to zero committed followed by a
4229 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4232 * To avoid this, we program the buffers in the highest slots.
4233 * This way, slot 0 is only used if slot 3 is also used.
4237 for (int i
= 3; i
>= 0; i
--) {
4238 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4240 if (range
->length
== 0)
4243 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4244 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
4246 assert(cbuf
->data
.offset
% 32 == 0);
4248 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4249 pkt
.ConstantBody
.Buffer
[n
] =
4250 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->data
.offset
)
4251 : ro_bo(batch
->screen
->workaround_bo
, 0);
4258 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4259 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4260 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4261 ptr
._3DCommandSubOpcode
= 38 + stage
;
4262 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4267 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4268 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4269 iris_populate_binding_table(ice
, batch
, stage
, false);
4273 if (ice
->state
.need_border_colors
)
4274 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4276 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4277 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4278 !ice
->shaders
.prog
[stage
])
4281 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4282 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4284 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4286 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4287 ptr
._3DCommandSubOpcode
= 43 + stage
;
4288 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4292 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4293 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4295 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4296 if (ice
->state
.framebuffer
.samples
> 0)
4297 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4301 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4302 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4303 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
4307 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4308 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4311 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4314 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4315 iris_use_pinned_bo(batch
, cache
->bo
, false);
4316 iris_batch_emit(batch
, shader
->derived_data
,
4317 iris_derived_program_state_size(stage
));
4319 if (stage
== MESA_SHADER_TESS_EVAL
) {
4320 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4321 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4322 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4323 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4324 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4329 if (ice
->state
.streamout_active
) {
4330 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4331 iris_batch_emit(batch
, genx
->so_buffers
,
4332 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4333 for (int i
= 0; i
< 4; i
++) {
4334 struct iris_stream_output_target
*tgt
=
4335 (void *) ice
->state
.so_target
[i
];
4337 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4339 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4345 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
4346 uint32_t *decl_list
=
4347 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
4348 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
4351 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4352 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4354 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
4355 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
4356 sol
.SOFunctionEnable
= true;
4357 sol
.SOStatisticsEnable
= true;
4359 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
4360 !ice
->state
.prims_generated_query_active
;
4361 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
4364 assert(ice
->state
.streamout
);
4366 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
4367 GENX(3DSTATE_STREAMOUT_length
));
4370 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4371 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
4375 if (dirty
& IRIS_DIRTY_CLIP
) {
4376 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4377 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4379 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
4380 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
4381 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4382 cl
.ClipMode
= cso_rast
->rasterizer_discard
? CLIPMODE_REJECT_ALL
4384 if (wm_prog_data
->barycentric_interp_modes
&
4385 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
4386 cl
.NonPerspectiveBarycentricEnable
= true;
4388 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
4389 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
4391 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
4392 ARRAY_SIZE(cso_rast
->clip
));
4395 if (dirty
& IRIS_DIRTY_RASTER
) {
4396 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4397 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
4398 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
4402 if (dirty
& IRIS_DIRTY_WM
) {
4403 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4404 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
4406 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
4407 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4409 wm
.BarycentricInterpolationMode
=
4410 wm_prog_data
->barycentric_interp_modes
;
4412 if (wm_prog_data
->early_fragment_tests
)
4413 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
4414 else if (wm_prog_data
->has_side_effects
)
4415 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
4417 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
4420 if (dirty
& IRIS_DIRTY_SBE
) {
4421 iris_emit_sbe(batch
, ice
);
4424 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
4425 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4426 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4427 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
4428 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
4429 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
4430 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4433 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
4434 ARRAY_SIZE(cso_blend
->ps_blend
));
4437 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
4438 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4440 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4441 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
4442 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
4443 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4444 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4446 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
4448 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
4452 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
4453 uint32_t scissor_offset
=
4454 emit_state(batch
, ice
->state
.dynamic_uploader
,
4455 &ice
->state
.last_res
.scissor
,
4456 ice
->state
.scissors
,
4457 sizeof(struct pipe_scissor_state
) *
4458 ice
->state
.num_viewports
, 32);
4460 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
4461 ptr
.ScissorRectPointer
= scissor_offset
;
4465 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
4466 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4467 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
4469 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
4471 if (cso_fb
->zsbuf
) {
4472 struct iris_resource
*zres
, *sres
;
4473 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
4476 iris_use_pinned_bo(batch
, zres
->bo
,
4477 ice
->state
.depth_writes_enabled
);
4481 iris_use_pinned_bo(batch
, sres
->bo
,
4482 ice
->state
.stencil_writes_enabled
);
4487 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
4488 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
4489 for (int i
= 0; i
< 32; i
++) {
4490 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
4495 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
4496 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4497 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
4500 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
4501 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
4502 topo
.PrimitiveTopologyType
=
4503 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
4507 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4508 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
4511 /* The VF cache designers cut corners, and made the cache key's
4512 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
4513 * 32 bits of the address. If you have two vertex buffers which get
4514 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
4515 * you can get collisions (even within a single batch).
4517 * So, we need to do a VF cache invalidate if the buffer for a VB
4518 * slot slot changes [48:32] address bits from the previous time.
4520 unsigned flush_flags
= 0;
4522 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4524 const int i
= u_bit_scan64(&bound
);
4525 uint16_t high_bits
= 0;
4527 struct iris_resource
*res
=
4528 (void *) genx
->vertex_buffers
[i
].resource
;
4530 iris_use_pinned_bo(batch
, res
->bo
, false);
4532 high_bits
= res
->bo
->gtt_offset
>> 32ull;
4533 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
4534 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
4535 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
4538 /* If the buffer was written to by streamout, we may need
4539 * to stall so those writes land and become visible to the
4542 * TODO: This may stall more than necessary.
4544 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
4545 flush_flags
|= PIPE_CONTROL_CS_STALL
;
4550 iris_emit_pipe_control_flush(batch
, flush_flags
);
4552 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
4555 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
4556 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
4557 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
4561 bound
= ice
->state
.bound_vertex_buffers
;
4563 const int i
= u_bit_scan64(&bound
);
4564 memcpy(map
, genx
->vertex_buffers
[i
].state
,
4565 sizeof(uint32_t) * vb_dwords
);
4571 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
4572 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4573 const unsigned entries
= MAX2(cso
->count
, 1);
4574 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
4575 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
4576 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
4577 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
4580 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
4581 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
4582 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
4583 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4585 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
4586 if (vs_prog_data
->uses_vertexid
) {
4587 sgv
.VertexIDEnable
= true;
4588 sgv
.VertexIDComponentNumber
= 2;
4589 sgv
.VertexIDElementOffset
= cso
->count
;
4592 if (vs_prog_data
->uses_instanceid
) {
4593 sgv
.InstanceIDEnable
= true;
4594 sgv
.InstanceIDComponentNumber
= 3;
4595 sgv
.InstanceIDElementOffset
= cso
->count
;
4600 if (dirty
& IRIS_DIRTY_VF
) {
4601 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
4602 if (draw
->primitive_restart
) {
4603 vf
.IndexedDrawCutIndexEnable
= true;
4604 vf
.CutIndex
= draw
->restart_index
;
4609 // XXX: Gen8 - PMA fix
4613 iris_upload_render_state(struct iris_context
*ice
,
4614 struct iris_batch
*batch
,
4615 const struct pipe_draw_info
*draw
)
4617 /* Always pin the binder. If we're emitting new binding table pointers,
4618 * we need it. If not, we're probably inheriting old tables via the
4619 * context, and need it anyway. Since true zero-bindings cases are
4620 * practically non-existent, just pin it and avoid last_res tracking.
4622 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
4624 if (!batch
->contains_draw
) {
4625 iris_restore_render_saved_bos(ice
, batch
, draw
);
4626 batch
->contains_draw
= true;
4629 iris_upload_dirty_render_state(ice
, batch
, draw
);
4631 if (draw
->index_size
> 0) {
4634 if (draw
->has_user_indices
) {
4635 u_upload_data(ice
->ctx
.stream_uploader
, 0,
4636 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
4637 &offset
, &ice
->state
.last_res
.index_buffer
);
4639 struct iris_resource
*res
= (void *) draw
->index
.resource
;
4640 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
4642 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
4643 draw
->index
.resource
);
4647 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4649 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
4650 ib
.IndexFormat
= draw
->index_size
>> 1;
4652 ib
.BufferSize
= bo
->size
;
4653 ib
.BufferStartingAddress
= ro_bo(bo
, offset
);
4656 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
4657 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
4658 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
4659 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_VF_CACHE_INVALIDATE
);
4660 ice
->state
.last_index_bo_high_bits
= high_bits
;
4664 #define _3DPRIM_END_OFFSET 0x2420
4665 #define _3DPRIM_START_VERTEX 0x2430
4666 #define _3DPRIM_VERTEX_COUNT 0x2434
4667 #define _3DPRIM_INSTANCE_COUNT 0x2438
4668 #define _3DPRIM_START_INSTANCE 0x243C
4669 #define _3DPRIM_BASE_VERTEX 0x2440
4671 if (draw
->indirect
) {
4672 /* We don't support this MultidrawIndirect. */
4673 assert(!draw
->indirect
->indirect_draw_count
);
4675 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
4678 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4679 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
4680 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
4682 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4683 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
4684 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
4686 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4687 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
4688 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
4690 if (draw
->index_size
) {
4691 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4692 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
4693 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4695 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4696 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4697 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
4700 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4701 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4702 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4704 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
4705 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
4709 } else if (draw
->count_from_stream_output
) {
4710 struct iris_stream_output_target
*so
=
4711 (void *) draw
->count_from_stream_output
;
4713 // XXX: avoid if possible
4714 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
4716 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4717 lrm
.RegisterAddress
= CS_GPR(0);
4719 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
4721 iris_math_div32_gpr0(ice
, batch
, so
->stride
);
4722 _iris_emit_lrr(batch
, _3DPRIM_VERTEX_COUNT
, CS_GPR(0));
4724 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
4725 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
4726 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
4727 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
4730 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
4731 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
4732 prim
.PredicateEnable
=
4733 ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
4735 if (draw
->indirect
|| draw
->count_from_stream_output
) {
4736 prim
.IndirectParameterEnable
= true;
4738 prim
.StartInstanceLocation
= draw
->start_instance
;
4739 prim
.InstanceCount
= draw
->instance_count
;
4740 prim
.VertexCountPerInstance
= draw
->count
;
4742 // XXX: this is probably bonkers.
4743 prim
.StartVertexLocation
= draw
->start
;
4745 if (draw
->index_size
) {
4746 prim
.BaseVertexLocation
+= draw
->index_bias
;
4748 prim
.StartVertexLocation
+= draw
->index_bias
;
4751 //prim.BaseVertexLocation = ...;
4757 iris_upload_compute_state(struct iris_context
*ice
,
4758 struct iris_batch
*batch
,
4759 const struct pipe_grid_info
*grid
)
4761 const uint64_t dirty
= ice
->state
.dirty
;
4762 struct iris_screen
*screen
= batch
->screen
;
4763 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
4764 struct iris_binder
*binder
= &ice
->state
.binder
;
4765 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
4766 struct iris_compiled_shader
*shader
=
4767 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
4768 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4769 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
4771 /* Always pin the binder. If we're emitting new binding table pointers,
4772 * we need it. If not, we're probably inheriting old tables via the
4773 * context, and need it anyway. Since true zero-bindings cases are
4774 * practically non-existent, just pin it and avoid last_res tracking.
4776 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
4778 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->cbuf0_needs_upload
)
4779 upload_uniforms(ice
, MESA_SHADER_COMPUTE
);
4781 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
4782 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
4784 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
4785 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
4787 if (ice
->state
.need_border_colors
)
4788 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4790 if (dirty
& IRIS_DIRTY_CS
) {
4791 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4793 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4794 * the only bits that are changed are scoreboard related: Scoreboard
4795 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
4796 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4799 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
4801 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4802 if (prog_data
->total_scratch
) {
4803 struct iris_bo
*bo
=
4804 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
4805 MESA_SHADER_COMPUTE
);
4806 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
4807 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
4810 vfe
.MaximumNumberofThreads
=
4811 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
4813 vfe
.ResetGatewayTimer
=
4814 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4817 vfe
.BypassGatewayControl
= true;
4819 vfe
.NumberofURBEntries
= 2;
4820 vfe
.URBEntryAllocationSize
= 2;
4822 // XXX: Use Indirect Payload Storage?
4823 vfe
.CURBEAllocationSize
=
4824 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4825 cs_prog_data
->push
.cross_thread
.regs
, 2);
4829 // XXX: hack iris_set_constant_buffers to upload these thread counts
4830 // XXX: along with regular uniforms for compute shaders, somehow.
4832 uint32_t curbe_data_offset
= 0;
4833 // TODO: Move subgroup-id into uniforms ubo so we can push uniforms
4834 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
4835 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
4836 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
4837 struct pipe_resource
*curbe_data_res
= NULL
;
4838 uint32_t *curbe_data_map
=
4839 stream_state(batch
, ice
->state
.dynamic_uploader
, &curbe_data_res
,
4840 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
4841 &curbe_data_offset
);
4842 assert(curbe_data_map
);
4843 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
4844 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
4846 if (dirty
& IRIS_DIRTY_CONSTANTS_CS
) {
4847 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4848 curbe
.CURBETotalDataLength
=
4849 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4850 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
4854 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
4855 IRIS_DIRTY_BINDINGS_CS
|
4856 IRIS_DIRTY_CONSTANTS_CS
|
4858 struct pipe_resource
*desc_res
= NULL
;
4859 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4861 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
4862 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
4863 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
4866 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
4867 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
4869 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4870 load
.InterfaceDescriptorTotalLength
=
4871 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4872 load
.InterfaceDescriptorDataStartAddress
=
4873 emit_state(batch
, ice
->state
.dynamic_uploader
,
4874 &desc_res
, desc
, sizeof(desc
), 32);
4877 pipe_resource_reference(&desc_res
, NULL
);
4880 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
4881 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
4882 uint32_t right_mask
;
4885 right_mask
= ~0u >> (32 - remainder
);
4887 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
4889 #define GPGPU_DISPATCHDIMX 0x2500
4890 #define GPGPU_DISPATCHDIMY 0x2504
4891 #define GPGPU_DISPATCHDIMZ 0x2508
4893 if (grid
->indirect
) {
4894 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
4895 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
4896 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4897 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
4898 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
4900 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4901 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
4902 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
4904 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4905 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
4906 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
4910 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
4911 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
4912 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
4913 ggw
.ThreadDepthCounterMaximum
= 0;
4914 ggw
.ThreadHeightCounterMaximum
= 0;
4915 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
4916 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
4917 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
4918 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
4919 ggw
.RightExecutionMask
= right_mask
;
4920 ggw
.BottomExecutionMask
= 0xffffffff;
4923 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4925 if (!batch
->contains_draw
) {
4926 iris_restore_compute_saved_bos(ice
, batch
, grid
);
4927 batch
->contains_draw
= true;
4932 * State module teardown.
4935 iris_destroy_state(struct iris_context
*ice
)
4937 struct iris_genx_state
*genx
= ice
->state
.genx
;
4939 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
4941 const int i
= u_bit_scan64(&bound_vbs
);
4942 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
4945 // XXX: unreference resources/surfaces.
4946 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
4947 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
4949 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
4951 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
4952 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4953 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
4955 free(ice
->state
.genx
);
4957 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
4959 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
4960 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
4961 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
4962 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
4963 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
4964 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
4967 /* ------------------------------------------------------------------- */
4970 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
4973 _iris_emit_lrr(batch
, dst
, src
);
4977 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
4980 _iris_emit_lrr(batch
, dst
, src
);
4981 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
4985 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
4988 _iris_emit_lri(batch
, reg
, val
);
4992 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
4995 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
4996 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
5000 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
5003 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5004 struct iris_bo
*bo
, uint32_t offset
)
5006 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5007 lrm
.RegisterAddress
= reg
;
5008 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
5013 * Load a 64-bit value from a buffer into a MMIO register via
5014 * two MI_LOAD_REGISTER_MEM commands.
5017 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5018 struct iris_bo
*bo
, uint32_t offset
)
5020 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
5021 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
5025 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5026 struct iris_bo
*bo
, uint32_t offset
,
5029 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
5030 srm
.RegisterAddress
= reg
;
5031 srm
.MemoryAddress
= rw_bo(bo
, offset
);
5032 srm
.PredicateEnable
= predicated
;
5037 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5038 struct iris_bo
*bo
, uint32_t offset
,
5041 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
5042 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
5046 iris_store_data_imm32(struct iris_batch
*batch
,
5047 struct iris_bo
*bo
, uint32_t offset
,
5050 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
5051 sdi
.Address
= rw_bo(bo
, offset
);
5052 sdi
.ImmediateData
= imm
;
5057 iris_store_data_imm64(struct iris_batch
*batch
,
5058 struct iris_bo
*bo
, uint32_t offset
,
5061 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
5062 * 2 in genxml but it's actually variable length and we need 5 DWords.
5064 void *map
= iris_get_command_space(batch
, 4 * 5);
5065 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
5066 sdi
.DWordLength
= 5 - 2;
5067 sdi
.Address
= rw_bo(bo
, offset
);
5068 sdi
.ImmediateData
= imm
;
5073 iris_copy_mem_mem(struct iris_batch
*batch
,
5074 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
5075 struct iris_bo
*src_bo
, uint32_t src_offset
,
5078 /* MI_COPY_MEM_MEM operates on DWords. */
5079 assert(bytes
% 4 == 0);
5080 assert(dst_offset
% 4 == 0);
5081 assert(src_offset
% 4 == 0);
5083 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
5084 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
5085 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
5086 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
5091 /* ------------------------------------------------------------------- */
5094 flags_to_post_sync_op(uint32_t flags
)
5096 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
5097 return WriteImmediateData
;
5099 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
5100 return WritePSDepthCount
;
5102 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
5103 return WriteTimestamp
;
5109 * Do the given flags have a Post Sync or LRI Post Sync operation?
5111 static enum pipe_control_flags
5112 get_post_sync_flags(enum pipe_control_flags flags
)
5114 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
5115 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5116 PIPE_CONTROL_WRITE_TIMESTAMP
|
5117 PIPE_CONTROL_LRI_POST_SYNC_OP
;
5119 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
5120 * "LRI Post Sync Operation". So more than one bit set would be illegal.
5122 assert(util_bitcount(flags
) <= 1);
5127 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
5130 * Emit a series of PIPE_CONTROL commands, taking into account any
5131 * workarounds necessary to actually accomplish the caller's request.
5133 * Unless otherwise noted, spec quotations in this function come from:
5135 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
5136 * Restrictions for PIPE_CONTROL.
5138 * You should not use this function directly. Use the helpers in
5139 * iris_pipe_control.c instead, which may split the pipe control further.
5142 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
5143 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
5145 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
5146 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
5147 enum pipe_control_flags non_lri_post_sync_flags
=
5148 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
5150 /* Recursive PIPE_CONTROL workarounds --------------------------------
5151 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
5153 * We do these first because we want to look at the original operation,
5154 * rather than any workarounds we set.
5156 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
5157 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
5158 * lists several workarounds:
5160 * "Project: SKL, KBL, BXT
5162 * If the VF Cache Invalidation Enable is set to a 1 in a
5163 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
5164 * sets to 0, with the VF Cache Invalidation Enable set to 0
5165 * needs to be sent prior to the PIPE_CONTROL with VF Cache
5166 * Invalidation Enable set to a 1."
5168 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
5171 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
5172 /* Project: SKL / Argument: LRI Post Sync Operation [23]
5174 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5175 * programmed prior to programming a PIPECONTROL command with "LRI
5176 * Post Sync Operation" in GPGPU mode of operation (i.e when
5177 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
5179 * The same text exists a few rows below for Post Sync Op.
5181 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
5184 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
5186 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
5187 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
5188 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
5190 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
5194 /* "Flush Types" workarounds ---------------------------------------------
5195 * We do these now because they may add post-sync operations or CS stalls.
5198 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
5199 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
5201 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
5202 * 'Write PS Depth Count' or 'Write Timestamp'."
5205 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5206 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5207 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5208 bo
= batch
->screen
->workaround_bo
;
5212 /* #1130 from Gen10 workarounds page:
5214 * "Enable Depth Stall on every Post Sync Op if Render target Cache
5215 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
5216 * board stall if Render target cache flush is enabled."
5218 * Applicable to CNL B0 and C0 steppings only.
5220 * The wording here is unclear, and this workaround doesn't look anything
5221 * like the internal bug report recommendations, but leave it be for now...
5223 if (GEN_GEN
== 10) {
5224 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
5225 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5226 } else if (flags
& non_lri_post_sync_flags
) {
5227 flags
|= PIPE_CONTROL_DEPTH_STALL
;
5231 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
5232 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
5234 * "This bit must be DISABLED for operations other than writing
5237 * This seems like nonsense. An Ivybridge workaround requires us to
5238 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
5239 * operation. Gen8+ requires us to emit depth stalls and depth cache
5240 * flushes together. So, it's hard to imagine this means anything other
5241 * than "we originally intended this to be used for PS_DEPTH_COUNT".
5243 * We ignore the supposed restriction and do nothing.
5247 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5248 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5249 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
5251 * "This bit must be DISABLED for End-of-pipe (Read) fences,
5252 * PS_DEPTH_COUNT or TIMESTAMP queries."
5254 * TODO: Implement end-of-pipe checking.
5256 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5257 PIPE_CONTROL_WRITE_TIMESTAMP
)));
5260 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5261 /* From the PIPE_CONTROL instruction table, bit 1:
5263 * "This bit is ignored if Depth Stall Enable is set.
5264 * Further, the render cache is not flushed even if Write Cache
5265 * Flush Enable bit is set."
5267 * We assert that the caller doesn't do this combination, to try and
5268 * prevent mistakes. It shouldn't hurt the GPU, though.
5270 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
5271 * and "Render Target Flush" combo is explicitly required for BTI
5272 * update workarounds.
5274 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
5275 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
5278 /* PIPE_CONTROL page workarounds ------------------------------------- */
5280 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
5281 /* From the PIPE_CONTROL page itself:
5284 * Restriction: Pipe_control with CS-stall bit set must be issued
5285 * before a pipe-control command that has the State Cache
5286 * Invalidate bit set."
5288 flags
|= PIPE_CONTROL_CS_STALL
;
5291 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
5292 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
5295 * SW must always program Post-Sync Operation to "Write Immediate
5296 * Data" when Flush LLC is set."
5298 * For now, we just require the caller to do it.
5300 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
5303 /* "Post-Sync Operation" workarounds -------------------------------- */
5305 /* Project: All / Argument: Global Snapshot Count Reset [19]
5307 * "This bit must not be exercised on any product.
5308 * Requires stall bit ([20] of DW1) set."
5310 * We don't use this, so we just assert that it isn't used. The
5311 * PIPE_CONTROL instruction page indicates that they intended this
5312 * as a debug feature and don't think it is useful in production,
5313 * but it may actually be usable, should we ever want to.
5315 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
5317 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
5318 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
5319 /* Project: All / Arguments:
5321 * - Generic Media State Clear [16]
5322 * - Indirect State Pointers Disable [16]
5324 * "Requires stall bit ([20] of DW1) set."
5326 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
5327 * State Clear) says:
5329 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5330 * programmed prior to programming a PIPECONTROL command with "Media
5331 * State Clear" set in GPGPU mode of operation"
5333 * This is a subset of the earlier rule, so there's nothing to do.
5335 flags
|= PIPE_CONTROL_CS_STALL
;
5338 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
5339 /* Project: All / Argument: Store Data Index
5341 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5344 * For now, we just assert that the caller does this. We might want to
5345 * automatically add a write to the workaround BO...
5347 assert(non_lri_post_sync_flags
!= 0);
5350 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
5351 /* Project: All / Argument: Sync GFDT
5353 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5354 * than '0' or 0x2520[13] must be set."
5356 * For now, we just assert that the caller does this.
5358 assert(non_lri_post_sync_flags
!= 0);
5361 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
5362 /* Project: IVB+ / Argument: TLB inv
5364 * "Requires stall bit ([20] of DW1) set."
5366 * Also, from the PIPE_CONTROL instruction table:
5369 * Post Sync Operation or CS stall must be set to ensure a TLB
5370 * invalidation occurs. Otherwise no cycle will occur to the TLB
5371 * cache to invalidate."
5373 * This is not a subset of the earlier rule, so there's nothing to do.
5375 flags
|= PIPE_CONTROL_CS_STALL
;
5378 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
5379 /* TODO: The big Skylake GT4 post sync op workaround */
5382 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
5384 if (IS_COMPUTE_PIPELINE(batch
)) {
5385 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
5386 /* Project: SKL+ / Argument: Tex Invalidate
5387 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
5389 flags
|= PIPE_CONTROL_CS_STALL
;
5392 if (GEN_GEN
== 8 && (post_sync_flags
||
5393 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
5394 PIPE_CONTROL_DEPTH_STALL
|
5395 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5396 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5397 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
5398 /* Project: BDW / Arguments:
5400 * - LRI Post Sync Operation [23]
5401 * - Post Sync Op [15:14]
5403 * - Depth Stall [13]
5404 * - Render Target Cache Flush [12]
5405 * - Depth Cache Flush [0]
5406 * - DC Flush Enable [5]
5408 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
5411 flags
|= PIPE_CONTROL_CS_STALL
;
5413 /* Also, from the PIPE_CONTROL instruction table, bit 20:
5416 * This bit must be always set when PIPE_CONTROL command is
5417 * programmed by GPGPU and MEDIA workloads, except for the cases
5418 * when only Read Only Cache Invalidation bits are set (State
5419 * Cache Invalidation Enable, Instruction cache Invalidation
5420 * Enable, Texture Cache Invalidation Enable, Constant Cache
5421 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
5422 * need not implemented when FF_DOP_CG is disable via "Fixed
5423 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
5425 * It sounds like we could avoid CS stalls in some cases, but we
5426 * don't currently bother. This list isn't exactly the list above,
5432 /* "Stall" workarounds ----------------------------------------------
5433 * These have to come after the earlier ones because we may have added
5434 * some additional CS stalls above.
5437 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
5438 /* Project: PRE-SKL, VLV, CHV
5440 * "[All Stepping][All SKUs]:
5442 * One of the following must also be set:
5444 * - Render Target Cache Flush Enable ([12] of DW1)
5445 * - Depth Cache Flush Enable ([0] of DW1)
5446 * - Stall at Pixel Scoreboard ([1] of DW1)
5447 * - Depth Stall ([13] of DW1)
5448 * - Post-Sync Operation ([13] of DW1)
5449 * - DC Flush Enable ([5] of DW1)"
5451 * If we don't already have one of those bits set, we choose to add
5452 * "Stall at Pixel Scoreboard". Some of the other bits require a
5453 * CS stall as a workaround (see above), which would send us into
5454 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
5455 * appears to be safe, so we choose that.
5457 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5458 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5459 PIPE_CONTROL_WRITE_IMMEDIATE
|
5460 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5461 PIPE_CONTROL_WRITE_TIMESTAMP
|
5462 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
5463 PIPE_CONTROL_DEPTH_STALL
|
5464 PIPE_CONTROL_DATA_CACHE_FLUSH
;
5465 if (!(flags
& wa_bits
))
5466 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5469 /* Emit --------------------------------------------------------------- */
5471 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
5472 pc
.LRIPostSyncOperation
= NoLRIOperation
;
5473 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
5474 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
5475 pc
.StoreDataIndex
= 0;
5476 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
5477 pc
.GlobalSnapshotCountReset
=
5478 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
5479 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
5480 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
5481 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5482 pc
.RenderTargetCacheFlushEnable
=
5483 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
5484 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
5485 pc
.StateCacheInvalidationEnable
=
5486 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
5487 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
5488 pc
.ConstantCacheInvalidationEnable
=
5489 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
5490 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
5491 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
5492 pc
.InstructionCacheInvalidateEnable
=
5493 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
5494 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
5495 pc
.IndirectStatePointersDisable
=
5496 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
5497 pc
.TextureCacheInvalidationEnable
=
5498 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
5499 pc
.Address
= rw_bo(bo
, offset
);
5500 pc
.ImmediateData
= imm
;
5505 genX(init_state
)(struct iris_context
*ice
)
5507 struct pipe_context
*ctx
= &ice
->ctx
;
5508 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
5510 ctx
->create_blend_state
= iris_create_blend_state
;
5511 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
5512 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
5513 ctx
->create_sampler_state
= iris_create_sampler_state
;
5514 ctx
->create_sampler_view
= iris_create_sampler_view
;
5515 ctx
->create_surface
= iris_create_surface
;
5516 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
5517 ctx
->bind_blend_state
= iris_bind_blend_state
;
5518 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
5519 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
5520 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
5521 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
5522 ctx
->delete_blend_state
= iris_delete_state
;
5523 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
5524 ctx
->delete_rasterizer_state
= iris_delete_state
;
5525 ctx
->delete_sampler_state
= iris_delete_state
;
5526 ctx
->delete_vertex_elements_state
= iris_delete_state
;
5527 ctx
->set_blend_color
= iris_set_blend_color
;
5528 ctx
->set_clip_state
= iris_set_clip_state
;
5529 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
5530 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
5531 ctx
->set_shader_images
= iris_set_shader_images
;
5532 ctx
->set_sampler_views
= iris_set_sampler_views
;
5533 ctx
->set_tess_state
= iris_set_tess_state
;
5534 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
5535 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
5536 ctx
->set_sample_mask
= iris_set_sample_mask
;
5537 ctx
->set_scissor_states
= iris_set_scissor_states
;
5538 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
5539 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
5540 ctx
->set_viewport_states
= iris_set_viewport_states
;
5541 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
5542 ctx
->surface_destroy
= iris_surface_destroy
;
5543 ctx
->draw_vbo
= iris_draw_vbo
;
5544 ctx
->launch_grid
= iris_launch_grid
;
5545 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
5546 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
5547 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
5549 ice
->vtbl
.destroy_state
= iris_destroy_state
;
5550 ice
->vtbl
.init_render_context
= iris_init_render_context
;
5551 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
5552 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
5553 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
5554 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
5555 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
5556 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
5557 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
5558 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
5559 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
5560 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
5561 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
5562 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
5563 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
5564 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
5565 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
5566 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
5567 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
5568 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
5569 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
5570 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
5571 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
5572 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
5573 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
5574 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
5575 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
5577 ice
->state
.dirty
= ~0ull;
5579 ice
->state
.statistics_counters_enabled
= true;
5581 ice
->state
.sample_mask
= 0xffff;
5582 ice
->state
.num_viewports
= 1;
5583 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
5585 /* Make a 1x1x1 null surface for unbound textures */
5586 void *null_surf_map
=
5587 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
5588 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
5589 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
5590 ice
->state
.unbound_tex
.offset
+=
5591 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
5593 /* Default all scissor rectangles to be empty regions. */
5594 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
5595 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
5596 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,