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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_inlines.h"
92 #include "util/u_format.h"
93 #include "util/u_framebuffer.h"
94 #include "util/u_transfer.h"
95 #include "util/u_upload_mgr.h"
96 #include "util/u_viewport.h"
97 #include "drm-uapi/i915_drm.h"
99 #include "intel/compiler/brw_compiler.h"
100 #include "intel/common/gen_l3_config.h"
101 #include "intel/common/gen_sample_positions.h"
102 #include "iris_batch.h"
103 #include "iris_context.h"
104 #include "iris_defines.h"
105 #include "iris_pipe.h"
106 #include "iris_resource.h"
108 #define __gen_address_type struct iris_address
109 #define __gen_user_data struct iris_batch
111 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
114 __gen_combine_address(struct iris_batch
*batch
, void *location
,
115 struct iris_address addr
, uint32_t delta
)
117 uint64_t result
= addr
.offset
+ delta
;
120 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
121 /* Assume this is a general address, not relative to a base. */
122 result
+= addr
.bo
->gtt_offset
;
128 #define __genxml_cmd_length(cmd) cmd ## _length
129 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
130 #define __genxml_cmd_header(cmd) cmd ## _header
131 #define __genxml_cmd_pack(cmd) cmd ## _pack
133 #define _iris_pack_command(batch, cmd, dst, name) \
134 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
135 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
136 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
140 #define iris_pack_command(cmd, dst, name) \
141 _iris_pack_command(NULL, cmd, dst, name)
143 #define iris_pack_state(cmd, dst, name) \
144 for (struct cmd name = {}, \
145 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
146 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
149 #define iris_emit_cmd(batch, cmd, name) \
150 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
152 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
154 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
155 for (uint32_t i = 0; i < num_dwords; i++) \
156 dw[i] = (dwords0)[i] | (dwords1)[i]; \
157 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
160 #include "genxml/genX_pack.h"
161 #include "genxml/gen_macros.h"
162 #include "genxml/genX_bits.h"
165 #define MOCS_PTE 0x18
168 #define MOCS_PTE (1 << 1)
169 #define MOCS_WB (2 << 1)
173 mocs(const struct iris_bo
*bo
)
175 return bo
&& bo
->external
? MOCS_PTE
: MOCS_WB
;
179 * Statically assert that PIPE_* enums match the hardware packets.
180 * (As long as they match, we don't need to translate them.)
182 UNUSED
static void pipe_asserts()
184 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
186 /* pipe_logicop happens to match the hardware. */
187 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
188 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
189 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
190 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
191 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
192 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
193 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
194 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
195 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
196 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
197 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
198 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
199 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
200 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
201 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
202 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
204 /* pipe_blend_func happens to match the hardware. */
205 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
206 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
207 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
211 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
212 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
213 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
214 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
215 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
216 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
217 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
218 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
219 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
220 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
221 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
222 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
223 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
225 /* pipe_blend_func happens to match the hardware. */
226 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
227 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
228 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
229 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
230 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
232 /* pipe_stencil_op happens to match the hardware. */
233 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
234 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
235 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
236 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
237 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
238 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
239 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
240 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
242 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
243 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
244 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
249 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
251 static const unsigned map
[] = {
252 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
253 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
254 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
255 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
256 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
257 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
258 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
259 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
260 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
261 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
262 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
263 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
264 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
265 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
266 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
269 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
273 translate_compare_func(enum pipe_compare_func pipe_func
)
275 static const unsigned map
[] = {
276 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
277 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
278 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
279 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
280 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
281 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
282 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
283 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
285 return map
[pipe_func
];
289 translate_shadow_func(enum pipe_compare_func pipe_func
)
291 /* Gallium specifies the result of shadow comparisons as:
293 * 1 if ref <op> texel,
298 * 0 if texel <op> ref,
301 * So we need to flip the operator and also negate.
303 static const unsigned map
[] = {
304 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
305 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
306 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
307 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
308 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
309 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
310 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
311 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
313 return map
[pipe_func
];
317 translate_cull_mode(unsigned pipe_face
)
319 static const unsigned map
[4] = {
320 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
321 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
322 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
323 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
325 return map
[pipe_face
];
329 translate_fill_mode(unsigned pipe_polymode
)
331 static const unsigned map
[4] = {
332 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
333 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
334 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
335 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
337 return map
[pipe_polymode
];
341 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
343 static const unsigned map
[] = {
344 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
345 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
346 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
348 return map
[pipe_mip
];
352 translate_wrap(unsigned pipe_wrap
)
354 static const unsigned map
[] = {
355 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
356 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
357 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
358 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
359 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
360 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
362 /* These are unsupported. */
363 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
364 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
366 return map
[pipe_wrap
];
369 static struct iris_address
370 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
372 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
373 * validation list at CSO creation time, instead of draw time.
375 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
378 static struct iris_address
379 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
381 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
382 * validation list at CSO creation time, instead of draw time.
384 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
388 * Allocate space for some indirect state.
390 * Return a pointer to the map (to fill it out) and a state ref (for
391 * referring to the state in GPU commands).
394 upload_state(struct u_upload_mgr
*uploader
,
395 struct iris_state_ref
*ref
,
400 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
405 * Stream out temporary/short-lived state.
407 * This allocates space, pins the BO, and includes the BO address in the
408 * returned offset (which works because all state lives in 32-bit memory
412 stream_state(struct iris_batch
*batch
,
413 struct u_upload_mgr
*uploader
,
414 struct pipe_resource
**out_res
,
417 uint32_t *out_offset
)
421 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
423 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
424 iris_use_pinned_bo(batch
, bo
, false);
426 *out_offset
+= iris_bo_offset_from_base_address(bo
);
432 * stream_state() + memcpy.
435 emit_state(struct iris_batch
*batch
,
436 struct u_upload_mgr
*uploader
,
437 struct pipe_resource
**out_res
,
444 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
447 memcpy(map
, data
, size
);
453 * Did field 'x' change between 'old_cso' and 'new_cso'?
455 * (If so, we may want to set some dirty flags.)
457 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
458 #define cso_changed_memcmp(x) \
459 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
462 flush_for_state_base_change(struct iris_batch
*batch
)
464 /* Flush before emitting STATE_BASE_ADDRESS.
466 * This isn't documented anywhere in the PRM. However, it seems to be
467 * necessary prior to changing the surface state base adress. We've
468 * seen issues in Vulkan where we get GPU hangs when using multi-level
469 * command buffers which clear depth, reset state base address, and then
472 * Normally, in GL, we would trust the kernel to do sufficient stalls
473 * and flushes prior to executing our batch. However, it doesn't seem
474 * as if the kernel's flushing is always sufficient and we don't want to
477 * We make this an end-of-pipe sync instead of a normal flush because we
478 * do not know the current status of the GPU. On Haswell at least,
479 * having a fast-clear operation in flight at the same time as a normal
480 * rendering operation can cause hangs. Since the kernel's flushing is
481 * insufficient, we need to ensure that any rendering operations from
482 * other processes are definitely complete before we try to do our own
483 * rendering. It's a bit of a big hammer but it appears to work.
485 iris_emit_end_of_pipe_sync(batch
,
486 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
487 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
488 PIPE_CONTROL_DATA_CACHE_FLUSH
);
492 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
494 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
495 lri
.RegisterOffset
= reg
;
499 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
502 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
504 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
505 lrr
.SourceRegisterAddress
= src
;
506 lrr
.DestinationRegisterAddress
= dst
;
511 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
513 #if GEN_GEN >= 8 && GEN_GEN < 10
514 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
516 * Software must clear the COLOR_CALC_STATE Valid field in
517 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
518 * with Pipeline Select set to GPGPU.
520 * The internal hardware docs recommend the same workaround for Gen9
523 if (pipeline
== GPGPU
)
524 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
528 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
529 * PIPELINE_SELECT [DevBWR+]":
533 * Software must ensure all the write caches are flushed through a
534 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
535 * command to invalidate read only caches prior to programming
536 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
538 iris_emit_pipe_control_flush(batch
,
539 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
540 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
541 PIPE_CONTROL_DATA_CACHE_FLUSH
|
542 PIPE_CONTROL_CS_STALL
);
544 iris_emit_pipe_control_flush(batch
,
545 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
546 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
547 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
548 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
550 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
554 sel
.PipelineSelection
= pipeline
;
559 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
564 * "This chicken bit works around a hardware issue with barrier
565 * logic encountered when switching between GPGPU and 3D pipelines.
566 * To workaround the issue, this mode bit should be set after a
567 * pipeline is selected."
570 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
571 reg
.GLKBarrierMode
= value
;
572 reg
.GLKBarrierModeMask
= 1;
574 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
579 init_state_base_address(struct iris_batch
*batch
)
581 flush_for_state_base_change(batch
);
583 /* We program most base addresses once at context initialization time.
584 * Each base address points at a 4GB memory zone, and never needs to
585 * change. See iris_bufmgr.h for a description of the memory zones.
587 * The one exception is Surface State Base Address, which needs to be
588 * updated occasionally. See iris_binder.c for the details there.
590 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
591 sba
.GeneralStateMOCS
= MOCS_WB
;
592 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
593 sba
.DynamicStateMOCS
= MOCS_WB
;
594 sba
.IndirectObjectMOCS
= MOCS_WB
;
595 sba
.InstructionMOCS
= MOCS_WB
;
597 sba
.GeneralStateBaseAddressModifyEnable
= true;
598 sba
.DynamicStateBaseAddressModifyEnable
= true;
599 sba
.IndirectObjectBaseAddressModifyEnable
= true;
600 sba
.InstructionBaseAddressModifyEnable
= true;
601 sba
.GeneralStateBufferSizeModifyEnable
= true;
602 sba
.DynamicStateBufferSizeModifyEnable
= true;
604 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
605 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
607 sba
.IndirectObjectBufferSizeModifyEnable
= true;
608 sba
.InstructionBuffersizeModifyEnable
= true;
610 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
611 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
613 sba
.GeneralStateBufferSize
= 0xfffff;
614 sba
.IndirectObjectBufferSize
= 0xfffff;
615 sba
.InstructionBufferSize
= 0xfffff;
616 sba
.DynamicStateBufferSize
= 0xfffff;
621 iris_emit_l3_config(struct iris_batch
*batch
, const struct gen_l3_config
*cfg
,
622 bool has_slm
, bool wants_dc_cache
)
625 iris_pack_state(GENX(L3CNTLREG
), ®_val
, reg
) {
626 reg
.SLMEnable
= has_slm
;
628 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
629 * in L3CNTLREG register. The default setting of the bit is not the
630 * desirable behavior.
632 reg
.ErrorDetectionBehaviorControl
= true;
634 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
635 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
636 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
637 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
639 iris_emit_lri(batch
, L3CNTLREG
, reg_val
);
643 iris_emit_default_l3_config(struct iris_batch
*batch
,
644 const struct gen_device_info
*devinfo
,
647 bool wants_dc_cache
= true;
648 bool has_slm
= compute
;
649 const struct gen_l3_weights w
=
650 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
651 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
652 iris_emit_l3_config(batch
, cfg
, has_slm
, wants_dc_cache
);
656 * Upload the initial GPU state for a render context.
658 * This sets some invariant state that needs to be programmed a particular
659 * way, but we never actually change.
662 iris_init_render_context(struct iris_screen
*screen
,
663 struct iris_batch
*batch
,
664 struct iris_vtable
*vtbl
,
665 struct pipe_debug_callback
*dbg
)
667 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
670 emit_pipeline_select(batch
, _3D
);
672 iris_emit_default_l3_config(batch
, devinfo
, false);
674 init_state_base_address(batch
);
677 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
678 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
679 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
681 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
683 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
684 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
685 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
687 iris_emit_lri(batch
, INSTPM
, reg_val
);
691 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
692 reg
.FloatBlendOptimizationEnable
= true;
693 reg
.FloatBlendOptimizationEnableMask
= true;
694 reg
.PartialResolveDisableInVC
= true;
695 reg
.PartialResolveDisableInVCMask
= true;
697 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
699 if (devinfo
->is_geminilake
)
700 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
704 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
705 reg
.HeaderlessMessageforPreemptableContexts
= 1;
706 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
708 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
713 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
714 * changing it dynamically. We set it to the maximum size here, and
715 * instead include the render target dimensions in the viewport, so
716 * viewport extents clipping takes care of pruning stray geometry.
718 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
719 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
720 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
723 /* Set the initial MSAA sample positions. */
724 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
725 GEN_SAMPLE_POS_1X(pat
._1xSample
);
726 GEN_SAMPLE_POS_2X(pat
._2xSample
);
727 GEN_SAMPLE_POS_4X(pat
._4xSample
);
728 GEN_SAMPLE_POS_8X(pat
._8xSample
);
730 GEN_SAMPLE_POS_16X(pat
._16xSample
);
734 /* Use the legacy AA line coverage computation. */
735 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
737 /* Disable chromakeying (it's for media) */
738 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
740 /* We want regular rendering, not special HiZ operations. */
741 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
743 /* No polygon stippling offsets are necessary. */
744 /* TODO: may need to set an offset for origin-UL framebuffers */
745 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
747 /* Set a static partitioning of the push constant area. */
748 /* TODO: this may be a bad idea...could starve the push ringbuffers... */
749 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
750 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
751 alloc
._3DCommandSubOpcode
= 18 + i
;
752 alloc
.ConstantBufferOffset
= 6 * i
;
753 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
759 iris_init_compute_context(struct iris_screen
*screen
,
760 struct iris_batch
*batch
,
761 struct iris_vtable
*vtbl
,
762 struct pipe_debug_callback
*dbg
)
764 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
766 emit_pipeline_select(batch
, GPGPU
);
768 iris_emit_default_l3_config(batch
, devinfo
, true);
770 init_state_base_address(batch
);
773 if (devinfo
->is_geminilake
)
774 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
778 struct iris_vertex_buffer_state
{
779 /** The VERTEX_BUFFER_STATE hardware structure. */
780 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
782 /** The resource to source vertex data from. */
783 struct pipe_resource
*resource
;
786 struct iris_depth_buffer_state
{
787 /* Depth/HiZ/Stencil related hardware packets. */
788 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
789 GENX(3DSTATE_STENCIL_BUFFER_length
) +
790 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
791 GENX(3DSTATE_CLEAR_PARAMS_length
)];
795 * Generation-specific context state (ice->state.genx->...).
797 * Most state can go in iris_context directly, but these encode hardware
798 * packets which vary by generation.
800 struct iris_genx_state
{
801 struct iris_vertex_buffer_state vertex_buffers
[33];
803 struct iris_depth_buffer_state depth_buffer
;
805 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
809 * The pipe->set_blend_color() driver hook.
811 * This corresponds to our COLOR_CALC_STATE.
814 iris_set_blend_color(struct pipe_context
*ctx
,
815 const struct pipe_blend_color
*state
)
817 struct iris_context
*ice
= (struct iris_context
*) ctx
;
819 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
820 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
821 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
825 * Gallium CSO for blend state (see pipe_blend_state).
827 struct iris_blend_state
{
828 /** Partial 3DSTATE_PS_BLEND */
829 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
831 /** Partial BLEND_STATE */
832 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
833 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
835 bool alpha_to_coverage
; /* for shader key */
837 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
838 uint8_t blend_enables
;
840 /** Bitfield of whether color writes are enabled for RT[i] */
841 uint8_t color_write_enables
;
844 static enum pipe_blendfactor
845 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
848 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
849 return PIPE_BLENDFACTOR_ONE
;
851 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
852 return PIPE_BLENDFACTOR_ZERO
;
859 * The pipe->create_blend_state() driver hook.
861 * Translates a pipe_blend_state into iris_blend_state.
864 iris_create_blend_state(struct pipe_context
*ctx
,
865 const struct pipe_blend_state
*state
)
867 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
868 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
870 cso
->blend_enables
= 0;
871 cso
->color_write_enables
= 0;
872 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
874 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
876 bool indep_alpha_blend
= false;
878 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
879 const struct pipe_rt_blend_state
*rt
=
880 &state
->rt
[state
->independent_blend_enable
? i
: 0];
882 enum pipe_blendfactor src_rgb
=
883 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
884 enum pipe_blendfactor src_alpha
=
885 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
886 enum pipe_blendfactor dst_rgb
=
887 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
888 enum pipe_blendfactor dst_alpha
=
889 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
891 if (rt
->rgb_func
!= rt
->alpha_func
||
892 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
893 indep_alpha_blend
= true;
895 if (rt
->blend_enable
)
896 cso
->blend_enables
|= 1u << i
;
899 cso
->color_write_enables
|= 1u << i
;
901 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
902 be
.LogicOpEnable
= state
->logicop_enable
;
903 be
.LogicOpFunction
= state
->logicop_func
;
905 be
.PreBlendSourceOnlyClampEnable
= false;
906 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
907 be
.PreBlendColorClampEnable
= true;
908 be
.PostBlendColorClampEnable
= true;
910 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
912 be
.ColorBlendFunction
= rt
->rgb_func
;
913 be
.AlphaBlendFunction
= rt
->alpha_func
;
914 be
.SourceBlendFactor
= src_rgb
;
915 be
.SourceAlphaBlendFactor
= src_alpha
;
916 be
.DestinationBlendFactor
= dst_rgb
;
917 be
.DestinationAlphaBlendFactor
= dst_alpha
;
919 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
920 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
921 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
922 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
924 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
927 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
928 /* pb.HasWriteableRT is filled in at draw time. */
929 /* pb.AlphaTestEnable is filled in at draw time. */
930 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
931 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
933 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
935 pb
.SourceBlendFactor
=
936 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
937 pb
.SourceAlphaBlendFactor
=
938 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
939 pb
.DestinationBlendFactor
=
940 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
941 pb
.DestinationAlphaBlendFactor
=
942 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
945 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
946 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
947 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
948 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
949 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
950 bs
.ColorDitherEnable
= state
->dither
;
951 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
959 * The pipe->bind_blend_state() driver hook.
961 * Bind a blending CSO and flag related dirty bits.
964 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
966 struct iris_context
*ice
= (struct iris_context
*) ctx
;
967 struct iris_blend_state
*cso
= state
;
969 ice
->state
.cso_blend
= cso
;
970 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
972 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
973 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
974 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
978 * Return true if the FS writes to any color outputs which are not disabled
982 has_writeable_rt(const struct iris_blend_state
*cso_blend
,
983 const struct shader_info
*fs_info
)
988 unsigned rt_outputs
= fs_info
->outputs_written
>> FRAG_RESULT_DATA0
;
990 if (fs_info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
))
991 rt_outputs
= (1 << BRW_MAX_DRAW_BUFFERS
) - 1;
993 return cso_blend
->color_write_enables
& rt_outputs
;
997 * Gallium CSO for depth, stencil, and alpha testing state.
999 struct iris_depth_stencil_alpha_state
{
1000 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
1001 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1003 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
1004 struct pipe_alpha_state alpha
;
1006 /** Outbound to resolve and cache set tracking. */
1007 bool depth_writes_enabled
;
1008 bool stencil_writes_enabled
;
1012 * The pipe->create_depth_stencil_alpha_state() driver hook.
1014 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
1015 * testing state since we need pieces of it in a variety of places.
1018 iris_create_zsa_state(struct pipe_context
*ctx
,
1019 const struct pipe_depth_stencil_alpha_state
*state
)
1021 struct iris_depth_stencil_alpha_state
*cso
=
1022 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
1024 bool two_sided_stencil
= state
->stencil
[1].enabled
;
1026 cso
->alpha
= state
->alpha
;
1027 cso
->depth_writes_enabled
= state
->depth
.writemask
;
1028 cso
->stencil_writes_enabled
=
1029 state
->stencil
[0].writemask
!= 0 ||
1030 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 1);
1032 /* The state tracker needs to optimize away EQUAL writes for us. */
1033 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
1035 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
1036 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1037 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1038 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1039 wmds
.StencilTestFunction
=
1040 translate_compare_func(state
->stencil
[0].func
);
1041 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1042 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1043 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1044 wmds
.BackfaceStencilTestFunction
=
1045 translate_compare_func(state
->stencil
[1].func
);
1046 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1047 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1048 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1049 wmds
.StencilBufferWriteEnable
=
1050 state
->stencil
[0].writemask
!= 0 ||
1051 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1052 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1053 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1054 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1055 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1056 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1057 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1058 /* wmds.[Backface]StencilReferenceValue are merged later */
1065 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1067 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1070 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1072 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1073 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1074 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1077 if (cso_changed(alpha
.ref_value
))
1078 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1080 if (cso_changed(alpha
.enabled
))
1081 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1083 if (cso_changed(alpha
.func
))
1084 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1086 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1087 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1090 ice
->state
.cso_zsa
= new_cso
;
1091 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1092 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1093 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1097 * Gallium CSO for rasterizer state.
1099 struct iris_rasterizer_state
{
1100 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1101 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1102 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1103 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1104 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1106 uint8_t num_clip_plane_consts
;
1107 bool clip_halfz
; /* for CC_VIEWPORT */
1108 bool depth_clip_near
; /* for CC_VIEWPORT */
1109 bool depth_clip_far
; /* for CC_VIEWPORT */
1110 bool flatshade
; /* for shader state */
1111 bool flatshade_first
; /* for stream output */
1112 bool clamp_fragment_color
; /* for shader state */
1113 bool light_twoside
; /* for shader state */
1114 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1115 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1116 bool line_stipple_enable
;
1117 bool poly_stipple_enable
;
1119 bool force_persample_interp
;
1120 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1121 uint16_t sprite_coord_enable
;
1125 get_line_width(const struct pipe_rasterizer_state
*state
)
1127 float line_width
= state
->line_width
;
1129 /* From the OpenGL 4.4 spec:
1131 * "The actual width of non-antialiased lines is determined by rounding
1132 * the supplied width to the nearest integer, then clamping it to the
1133 * implementation-dependent maximum non-antialiased line width."
1135 if (!state
->multisample
&& !state
->line_smooth
)
1136 line_width
= roundf(state
->line_width
);
1138 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1139 /* For 1 pixel line thickness or less, the general anti-aliasing
1140 * algorithm gives up, and a garbage line is generated. Setting a
1141 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1142 * (one-pixel-wide), non-antialiased lines.
1144 * Lines rendered with zero Line Width are rasterized using the
1145 * "Grid Intersection Quantization" rules as specified by the
1146 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1155 * The pipe->create_rasterizer_state() driver hook.
1158 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1159 const struct pipe_rasterizer_state
*state
)
1161 struct iris_rasterizer_state
*cso
=
1162 malloc(sizeof(struct iris_rasterizer_state
));
1164 cso
->multisample
= state
->multisample
;
1165 cso
->force_persample_interp
= state
->force_persample_interp
;
1166 cso
->clip_halfz
= state
->clip_halfz
;
1167 cso
->depth_clip_near
= state
->depth_clip_near
;
1168 cso
->depth_clip_far
= state
->depth_clip_far
;
1169 cso
->flatshade
= state
->flatshade
;
1170 cso
->flatshade_first
= state
->flatshade_first
;
1171 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1172 cso
->light_twoside
= state
->light_twoside
;
1173 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1174 cso
->half_pixel_center
= state
->half_pixel_center
;
1175 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1176 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1177 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1178 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1180 if (state
->clip_plane_enable
!= 0)
1181 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1183 cso
->num_clip_plane_consts
= 0;
1185 float line_width
= get_line_width(state
);
1187 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1188 sf
.StatisticsEnable
= true;
1189 sf
.ViewportTransformEnable
= true;
1190 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1191 sf
.LineEndCapAntialiasingRegionWidth
=
1192 state
->line_smooth
? _10pixels
: _05pixels
;
1193 sf
.LastPixelEnable
= state
->line_last_pixel
;
1194 sf
.LineWidth
= line_width
;
1195 sf
.SmoothPointEnable
= (state
->point_smooth
|| state
->multisample
) &&
1196 !state
->point_quad_rasterization
;
1197 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1198 sf
.PointWidth
= state
->point_size
;
1200 if (state
->flatshade_first
) {
1201 sf
.TriangleFanProvokingVertexSelect
= 1;
1203 sf
.TriangleStripListProvokingVertexSelect
= 2;
1204 sf
.TriangleFanProvokingVertexSelect
= 2;
1205 sf
.LineStripListProvokingVertexSelect
= 1;
1209 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1210 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1211 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1212 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1213 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1214 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1215 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1216 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1217 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1218 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1219 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1220 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1221 rr
.SmoothPointEnable
= state
->point_smooth
;
1222 rr
.AntialiasingEnable
= state
->line_smooth
;
1223 rr
.ScissorRectangleEnable
= state
->scissor
;
1225 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1226 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1228 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1230 /* TODO: ConservativeRasterizationEnable */
1233 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1234 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1235 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1237 cl
.EarlyCullEnable
= true;
1238 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1239 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1240 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1241 cl
.GuardbandClipTestEnable
= true;
1242 cl
.ClipEnable
= true;
1243 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
1244 cl
.MinimumPointWidth
= 0.125;
1245 cl
.MaximumPointWidth
= 255.875;
1247 if (state
->flatshade_first
) {
1248 cl
.TriangleFanProvokingVertexSelect
= 1;
1250 cl
.TriangleStripListProvokingVertexSelect
= 2;
1251 cl
.TriangleFanProvokingVertexSelect
= 2;
1252 cl
.LineStripListProvokingVertexSelect
= 1;
1256 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1257 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1258 * filled in at draw time from the FS program.
1260 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1261 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1262 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1263 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1264 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1267 /* Remap from 0..255 back to 1..256 */
1268 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1270 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1271 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1272 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1273 line
.LineStippleRepeatCount
= line_stipple_factor
;
1280 * The pipe->bind_rasterizer_state() driver hook.
1282 * Bind a rasterizer CSO and flag related dirty bits.
1285 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1287 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1288 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1289 struct iris_rasterizer_state
*new_cso
= state
;
1292 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1293 if (cso_changed_memcmp(line_stipple
))
1294 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1296 if (cso_changed(half_pixel_center
))
1297 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1299 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1300 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1302 if (cso_changed(rasterizer_discard
))
1303 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1305 if (cso_changed(flatshade_first
))
1306 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1308 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1309 cso_changed(clip_halfz
))
1310 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1312 if (cso_changed(sprite_coord_enable
) ||
1313 cso_changed(sprite_coord_mode
) ||
1314 cso_changed(light_twoside
))
1315 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1318 ice
->state
.cso_rast
= new_cso
;
1319 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1320 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1321 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1325 * Return true if the given wrap mode requires the border color to exist.
1327 * (We can skip uploading it if the sampler isn't going to use it.)
1330 wrap_mode_needs_border_color(unsigned wrap_mode
)
1332 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1336 * Gallium CSO for sampler state.
1338 struct iris_sampler_state
{
1339 union pipe_color_union border_color
;
1340 bool needs_border_color
;
1342 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1346 * The pipe->create_sampler_state() driver hook.
1348 * We fill out SAMPLER_STATE (except for the border color pointer), and
1349 * store that on the CPU. It doesn't make sense to upload it to a GPU
1350 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1351 * all bound sampler states to be in contiguous memor.
1354 iris_create_sampler_state(struct pipe_context
*ctx
,
1355 const struct pipe_sampler_state
*state
)
1357 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1362 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1363 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1365 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1366 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1367 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1369 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1371 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1372 wrap_mode_needs_border_color(wrap_t
) ||
1373 wrap_mode_needs_border_color(wrap_r
);
1375 float min_lod
= state
->min_lod
;
1376 unsigned mag_img_filter
= state
->mag_img_filter
;
1378 // XXX: explain this code ported from ilo...I don't get it at all...
1379 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1380 state
->min_lod
> 0.0f
) {
1382 mag_img_filter
= state
->min_img_filter
;
1385 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1386 samp
.TCXAddressControlMode
= wrap_s
;
1387 samp
.TCYAddressControlMode
= wrap_t
;
1388 samp
.TCZAddressControlMode
= wrap_r
;
1389 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1390 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1391 samp
.MinModeFilter
= state
->min_img_filter
;
1392 samp
.MagModeFilter
= mag_img_filter
;
1393 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1394 samp
.MaximumAnisotropy
= RATIO21
;
1396 if (state
->max_anisotropy
>= 2) {
1397 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1398 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1399 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1402 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1403 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1405 samp
.MaximumAnisotropy
=
1406 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1409 /* Set address rounding bits if not using nearest filtering. */
1410 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1411 samp
.UAddressMinFilterRoundingEnable
= true;
1412 samp
.VAddressMinFilterRoundingEnable
= true;
1413 samp
.RAddressMinFilterRoundingEnable
= true;
1416 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1417 samp
.UAddressMagFilterRoundingEnable
= true;
1418 samp
.VAddressMagFilterRoundingEnable
= true;
1419 samp
.RAddressMagFilterRoundingEnable
= true;
1422 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1423 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1425 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1427 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1428 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1429 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1430 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1432 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1439 * The pipe->bind_sampler_states() driver hook.
1441 * Now that we know all the sampler states, we upload them all into a
1442 * contiguous area of GPU memory, for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1443 * We also fill out the border color state pointers at this point.
1445 * We could defer this work to draw time, but we assume that binding
1446 * will be less frequent than drawing.
1448 // XXX: this may be a bad idea, need to make sure that st/mesa calls us
1449 // XXX: with the complete set of shaders. If it makes multiple calls to
1450 // XXX: things one at a time, we could waste a lot of time assembling things.
1451 // XXX: it doesn't even BUY us anything to do it here, because we only flag
1452 // XXX: IRIS_DIRTY_SAMPLER_STATE when this is called...
1454 iris_bind_sampler_states(struct pipe_context
*ctx
,
1455 enum pipe_shader_type p_stage
,
1456 unsigned start
, unsigned count
,
1459 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1460 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1461 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1463 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1465 for (int i
= 0; i
< count
; i
++) {
1466 shs
->samplers
[start
+ i
] = states
[i
];
1469 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1470 * in the dynamic state memory zone, so we can point to it via the
1471 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1474 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
,
1475 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
1479 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1480 shs
->sampler_table
.offset
+=
1481 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1483 /* Make sure all land in the same BO */
1484 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1486 for (int i
= 0; i
< count
; i
++) {
1487 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1490 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1491 } else if (!state
->needs_border_color
) {
1492 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1494 ice
->state
.need_border_colors
= true;
1496 /* Stream out the border color and merge the pointer. */
1498 iris_upload_border_color(ice
, &state
->border_color
);
1500 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1501 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1502 dyns
.BorderColorPointer
= offset
;
1505 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1506 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1509 map
+= GENX(SAMPLER_STATE_length
);
1512 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1515 static enum isl_channel_select
1516 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1519 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1520 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1521 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1522 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1523 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1524 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1525 default: unreachable("invalid swizzle");
1530 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1533 enum isl_format format
,
1537 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1538 const unsigned cpp
= format
== ISL_FORMAT_RAW
? 1 : fmtl
->bpb
/ 8;
1540 /* The ARB_texture_buffer_specification says:
1542 * "The number of texels in the buffer texture's texel array is given by
1544 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1546 * where <buffer_size> is the size of the buffer object, in basic
1547 * machine units and <components> and <base_type> are the element count
1548 * and base data type for elements, as specified in Table X.1. The
1549 * number of texels in the texel array is then clamped to the
1550 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1552 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1553 * so that when ISL divides by stride to obtain the number of texels, that
1554 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1556 unsigned final_size
=
1557 MIN3(size
, bo
->size
- offset
, IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1559 isl_buffer_fill_state(isl_dev
, map
,
1560 .address
= bo
->gtt_offset
+ offset
,
1561 .size_B
= final_size
,
1563 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1568 #define SURFACE_STATE_ALIGNMENT 64
1571 * Allocate several contiguous SURFACE_STATE structures, one for each
1572 * supported auxiliary surface mode.
1575 alloc_surface_states(struct u_upload_mgr
*mgr
,
1576 struct iris_state_ref
*ref
,
1577 unsigned aux_usages
)
1579 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
1581 /* If this changes, update this to explicitly align pointers */
1582 STATIC_ASSERT(surf_size
== SURFACE_STATE_ALIGNMENT
);
1584 assert(aux_usages
!= 0);
1587 upload_state(mgr
, ref
, util_bitcount(aux_usages
) * surf_size
,
1588 SURFACE_STATE_ALIGNMENT
);
1590 ref
->offset
+= iris_bo_offset_from_base_address(iris_resource_bo(ref
->res
));
1596 fill_surface_state(struct isl_device
*isl_dev
,
1598 struct iris_resource
*res
,
1599 struct isl_view
*view
,
1602 struct isl_surf_fill_state_info f
= {
1605 .mocs
= mocs(res
->bo
),
1606 .address
= res
->bo
->gtt_offset
,
1609 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1610 f
.aux_surf
= &res
->aux
.surf
;
1611 f
.aux_usage
= aux_usage
;
1612 f
.aux_address
= res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
;
1616 isl_surf_fill_state_s(isl_dev
, map
, &f
);
1620 * The pipe->create_sampler_view() driver hook.
1622 static struct pipe_sampler_view
*
1623 iris_create_sampler_view(struct pipe_context
*ctx
,
1624 struct pipe_resource
*tex
,
1625 const struct pipe_sampler_view
*tmpl
)
1627 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1628 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1629 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1630 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1635 /* initialize base object */
1637 isv
->base
.context
= ctx
;
1638 isv
->base
.texture
= NULL
;
1639 pipe_reference_init(&isv
->base
.reference
, 1);
1640 pipe_resource_reference(&isv
->base
.texture
, tex
);
1642 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1643 struct iris_resource
*zres
, *sres
;
1644 const struct util_format_description
*desc
=
1645 util_format_description(tmpl
->format
);
1647 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1649 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1652 isv
->res
= (struct iris_resource
*) tex
;
1654 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1655 &isv
->surface_state
,
1656 isv
->res
->aux
.possible_usages
);
1660 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1662 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1663 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1664 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1666 const struct iris_format_info fmt
=
1667 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1669 isv
->view
= (struct isl_view
) {
1671 .swizzle
= (struct isl_swizzle
) {
1672 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1673 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1674 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1675 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1680 /* Fill out SURFACE_STATE for this view. */
1681 if (tmpl
->target
!= PIPE_BUFFER
) {
1682 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1683 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1684 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1685 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1686 isv
->view
.array_len
=
1687 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1689 unsigned aux_modes
= isv
->res
->aux
.possible_usages
;
1691 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1693 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->view
,
1696 map
+= SURFACE_STATE_ALIGNMENT
;
1699 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
->bo
, map
,
1700 isv
->view
.format
, tmpl
->u
.buf
.offset
,
1708 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1709 struct pipe_sampler_view
*state
)
1711 struct iris_sampler_view
*isv
= (void *) state
;
1712 pipe_resource_reference(&state
->texture
, NULL
);
1713 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1718 * The pipe->create_surface() driver hook.
1720 * In Gallium nomenclature, "surfaces" are a view of a resource that
1721 * can be bound as a render target or depth/stencil buffer.
1723 static struct pipe_surface
*
1724 iris_create_surface(struct pipe_context
*ctx
,
1725 struct pipe_resource
*tex
,
1726 const struct pipe_surface
*tmpl
)
1728 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1729 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1730 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1731 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1732 struct pipe_surface
*psurf
= &surf
->base
;
1733 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1738 pipe_reference_init(&psurf
->reference
, 1);
1739 pipe_resource_reference(&psurf
->texture
, tex
);
1740 psurf
->context
= ctx
;
1741 psurf
->format
= tmpl
->format
;
1742 psurf
->width
= tex
->width0
;
1743 psurf
->height
= tex
->height0
;
1744 psurf
->texture
= tex
;
1745 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1746 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1747 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1749 isl_surf_usage_flags_t usage
= 0;
1751 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1752 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1753 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1755 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1757 const struct iris_format_info fmt
=
1758 iris_format_for_usage(devinfo
, psurf
->format
, usage
);
1760 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1761 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1762 /* Framebuffer validation will reject this invalid case, but it
1763 * hasn't had the opportunity yet. In the meantime, we need to
1764 * avoid hitting ISL asserts about unsupported formats below.
1770 surf
->view
= (struct isl_view
) {
1772 .base_level
= tmpl
->u
.tex
.level
,
1774 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1775 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1776 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1780 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1781 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1782 ISL_SURF_USAGE_STENCIL_BIT
))
1786 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1787 &surf
->surface_state
,
1788 res
->aux
.possible_usages
);
1792 unsigned aux_modes
= res
->aux
.possible_usages
;
1794 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1796 fill_surface_state(&screen
->isl_dev
, map
, res
, &surf
->view
, aux_usage
);
1798 map
+= SURFACE_STATE_ALIGNMENT
;
1806 fill_default_image_param(struct brw_image_param
*param
)
1808 memset(param
, 0, sizeof(*param
));
1809 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
1810 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
1811 * detailed explanation of these parameters.
1813 param
->swizzling
[0] = 0xff;
1814 param
->swizzling
[1] = 0xff;
1818 fill_buffer_image_param(struct brw_image_param
*param
,
1819 enum pipe_format pfmt
,
1822 const unsigned cpp
= util_format_get_blocksize(pfmt
);
1824 fill_default_image_param(param
);
1825 param
->size
[0] = size
/ cpp
;
1826 param
->stride
[0] = cpp
;
1829 #define isl_surf_fill_image_param(x, ...)
1830 #define fill_default_image_param(x, ...)
1831 #define fill_buffer_image_param(x, ...)
1835 * The pipe->set_shader_images() driver hook.
1838 iris_set_shader_images(struct pipe_context
*ctx
,
1839 enum pipe_shader_type p_stage
,
1840 unsigned start_slot
, unsigned count
,
1841 const struct pipe_image_view
*p_images
)
1843 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1844 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1845 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1846 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1847 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1849 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
1851 for (unsigned i
= 0; i
< count
; i
++) {
1852 if (p_images
&& p_images
[i
].resource
) {
1853 const struct pipe_image_view
*img
= &p_images
[i
];
1854 struct iris_resource
*res
= (void *) img
->resource
;
1855 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, &res
->base
);
1857 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
1859 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
1861 // XXX: these are not retained forever, use a separate uploader?
1863 alloc_surface_states(ice
->state
.surface_uploader
,
1864 &shs
->image
[start_slot
+ i
].surface_state
,
1865 1 << ISL_AUX_USAGE_NONE
);
1866 if (!unlikely(map
)) {
1867 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1871 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1872 enum isl_format isl_fmt
=
1873 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
1875 bool untyped_fallback
= false;
1877 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
1878 /* On Gen8, try to use typed surfaces reads (which support a
1879 * limited number of formats), and if not possible, fall back
1882 untyped_fallback
= GEN_GEN
== 8 &&
1883 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
);
1885 if (untyped_fallback
)
1886 isl_fmt
= ISL_FORMAT_RAW
;
1888 isl_fmt
= isl_lower_storage_image_format(devinfo
, isl_fmt
);
1891 shs
->image
[start_slot
+ i
].access
= img
->shader_access
;
1893 if (res
->base
.target
!= PIPE_BUFFER
) {
1894 struct isl_view view
= {
1896 .base_level
= img
->u
.tex
.level
,
1898 .base_array_layer
= img
->u
.tex
.first_layer
,
1899 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
1900 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1904 if (untyped_fallback
) {
1905 fill_buffer_surface_state(&screen
->isl_dev
, res
->bo
, map
,
1906 isl_fmt
, 0, res
->bo
->size
);
1908 /* Images don't support compression */
1909 unsigned aux_modes
= 1 << ISL_AUX_USAGE_NONE
;
1911 enum isl_aux_usage usage
= u_bit_scan(&aux_modes
);
1913 fill_surface_state(&screen
->isl_dev
, map
, res
, &view
, usage
);
1915 map
+= SURFACE_STATE_ALIGNMENT
;
1919 isl_surf_fill_image_param(&screen
->isl_dev
,
1920 &shs
->image
[start_slot
+ i
].param
,
1923 fill_buffer_surface_state(&screen
->isl_dev
, res
->bo
, map
,
1924 isl_fmt
, img
->u
.buf
.offset
,
1926 fill_buffer_image_param(&shs
->image
[start_slot
+ i
].param
,
1927 img
->format
, img
->u
.buf
.size
);
1930 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1931 pipe_resource_reference(&shs
->image
[start_slot
+ i
].surface_state
.res
,
1933 fill_default_image_param(&shs
->image
[start_slot
+ i
].param
);
1937 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1939 /* Broadwell also needs brw_image_params re-uploaded */
1941 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
1942 shs
->cbuf0_needs_upload
= true;
1948 * The pipe->set_sampler_views() driver hook.
1951 iris_set_sampler_views(struct pipe_context
*ctx
,
1952 enum pipe_shader_type p_stage
,
1953 unsigned start
, unsigned count
,
1954 struct pipe_sampler_view
**views
)
1956 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1957 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1958 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1960 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
1962 for (unsigned i
= 0; i
< count
; i
++) {
1963 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1964 &shs
->textures
[start
+ i
], views
[i
]);
1965 struct iris_sampler_view
*view
= (void *) views
[i
];
1967 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
1968 shs
->bound_sampler_views
|= 1 << (start
+ i
);
1972 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
1976 * The pipe->set_tess_state() driver hook.
1979 iris_set_tess_state(struct pipe_context
*ctx
,
1980 const float default_outer_level
[4],
1981 const float default_inner_level
[2])
1983 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1985 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
1986 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
1988 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
1992 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1994 struct iris_surface
*surf
= (void *) p_surf
;
1995 pipe_resource_reference(&p_surf
->texture
, NULL
);
1996 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2001 iris_set_clip_state(struct pipe_context
*ctx
,
2002 const struct pipe_clip_state
*state
)
2004 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2005 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
2007 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
2009 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
;
2010 shs
->cbuf0_needs_upload
= true;
2014 * The pipe->set_polygon_stipple() driver hook.
2017 iris_set_polygon_stipple(struct pipe_context
*ctx
,
2018 const struct pipe_poly_stipple
*state
)
2020 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2021 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
2022 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
2026 * The pipe->set_sample_mask() driver hook.
2029 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2031 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2033 /* We only support 16x MSAA, so we have 16 bits of sample maks.
2034 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
2036 ice
->state
.sample_mask
= sample_mask
& 0xffff;
2037 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
2041 * The pipe->set_scissor_states() driver hook.
2043 * This corresponds to our SCISSOR_RECT state structures. It's an
2044 * exact match, so we just store them, and memcpy them out later.
2047 iris_set_scissor_states(struct pipe_context
*ctx
,
2048 unsigned start_slot
,
2049 unsigned num_scissors
,
2050 const struct pipe_scissor_state
*rects
)
2052 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2054 for (unsigned i
= 0; i
< num_scissors
; i
++) {
2055 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
2056 /* If the scissor was out of bounds and got clamped to 0 width/height
2057 * at the bounds, the subtraction of 1 from maximums could produce a
2058 * negative number and thus not clip anything. Instead, just provide
2059 * a min > max scissor inside the bounds, which produces the expected
2062 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2063 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
2066 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2067 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
2068 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
2073 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
2077 * The pipe->set_stencil_ref() driver hook.
2079 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
2082 iris_set_stencil_ref(struct pipe_context
*ctx
,
2083 const struct pipe_stencil_ref
*state
)
2085 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2086 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2088 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2090 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2094 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2096 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2100 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2101 float m00
, float m11
, float m30
, float m31
,
2102 float *xmin
, float *xmax
,
2103 float *ymin
, float *ymax
)
2105 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2106 * Strips and Fans documentation:
2108 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2109 * fixed-point "guardband" range supported by the rasterization hardware"
2113 * "In almost all circumstances, if an object’s vertices are actually
2114 * modified by this clamping (i.e., had X or Y coordinates outside of
2115 * the guardband extent the rendered object will not match the intended
2116 * result. Therefore software should take steps to ensure that this does
2117 * not happen - e.g., by clipping objects such that they do not exceed
2118 * these limits after the Drawing Rectangle is applied."
2120 * I believe the fundamental restriction is that the rasterizer (in
2121 * the SF/WM stages) have a limit on the number of pixels that can be
2122 * rasterized. We need to ensure any coordinates beyond the rasterizer
2123 * limit are handled by the clipper. So effectively that limit becomes
2124 * the clipper's guardband size.
2126 * It goes on to say:
2128 * "In addition, in order to be correctly rendered, objects must have a
2129 * screenspace bounding box not exceeding 8K in the X or Y direction.
2130 * This additional restriction must also be comprehended by software,
2131 * i.e., enforced by use of clipping."
2133 * This makes no sense. Gen7+ hardware supports 16K render targets,
2134 * and you definitely need to be able to draw polygons that fill the
2135 * surface. Our assumption is that the rasterizer was limited to 8K
2136 * on Sandybridge, which only supports 8K surfaces, and it was actually
2137 * increased to 16K on Ivybridge and later.
2139 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2141 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2143 if (m00
!= 0 && m11
!= 0) {
2144 /* First, we compute the screen-space render area */
2145 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2146 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2147 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2148 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2150 /* We want the guardband to be centered on that */
2151 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2152 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2153 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2154 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2156 /* Now we need it in native device coordinates */
2157 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2158 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2159 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2160 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2162 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2163 * flipped upside-down. X should be fine though.
2165 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2166 *xmin
= ndc_gb_xmin
;
2167 *xmax
= ndc_gb_xmax
;
2168 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2169 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2171 /* The viewport scales to 0, so nothing will be rendered. */
2180 * The pipe->set_viewport_states() driver hook.
2182 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2183 * the guardband yet, as we need the framebuffer dimensions, but we can
2184 * at least fill out the rest.
2187 iris_set_viewport_states(struct pipe_context
*ctx
,
2188 unsigned start_slot
,
2190 const struct pipe_viewport_state
*states
)
2192 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2194 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2196 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2198 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2199 !ice
->state
.cso_rast
->depth_clip_far
))
2200 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2204 * The pipe->set_framebuffer_state() driver hook.
2206 * Sets the current draw FBO, including color render targets, depth,
2207 * and stencil buffers.
2210 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2211 const struct pipe_framebuffer_state
*state
)
2213 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2214 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2215 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2216 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2217 struct iris_resource
*zres
;
2218 struct iris_resource
*stencil_res
;
2220 unsigned samples
= util_framebuffer_get_num_samples(state
);
2221 unsigned layers
= util_framebuffer_get_num_layers(state
);
2223 if (cso
->samples
!= samples
) {
2224 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2227 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2228 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2231 if ((cso
->layers
== 0) != (layers
== 0)) {
2232 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2235 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2236 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2239 util_copy_framebuffer_state(cso
, state
);
2240 cso
->samples
= samples
;
2241 cso
->layers
= layers
;
2243 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2245 struct isl_view view
= {
2248 .base_array_layer
= 0,
2250 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2253 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
2256 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2259 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2260 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2262 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2265 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2267 info
.depth_surf
= &zres
->surf
;
2268 info
.depth_address
= zres
->bo
->gtt_offset
;
2269 info
.mocs
= mocs(zres
->bo
);
2271 view
.format
= zres
->surf
.format
;
2273 if (iris_resource_level_has_hiz(zres
, view
.base_level
)) {
2274 info
.hiz_usage
= ISL_AUX_USAGE_HIZ
;
2275 info
.hiz_surf
= &zres
->aux
.surf
;
2276 info
.hiz_address
= zres
->aux
.bo
->gtt_offset
;
2281 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2282 info
.stencil_surf
= &stencil_res
->surf
;
2283 info
.stencil_address
= stencil_res
->bo
->gtt_offset
;
2285 view
.format
= stencil_res
->surf
.format
;
2286 info
.mocs
= mocs(stencil_res
->bo
);
2291 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2293 /* Make a null surface for unbound buffers */
2294 void *null_surf_map
=
2295 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2296 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2297 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2298 isl_extent3d(MAX2(cso
->width
, 1),
2299 MAX2(cso
->height
, 1),
2300 cso
->layers
? cso
->layers
: 1));
2301 ice
->state
.null_fb
.offset
+=
2302 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2304 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2306 /* Render target change */
2307 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2309 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2312 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2313 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2315 /* The PIPE_CONTROL command description says:
2317 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2318 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2319 * Target Cache Flush by enabling this bit. When render target flush
2320 * is set due to new association of BTI, PS Scoreboard Stall bit must
2321 * be set in this packet."
2323 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2324 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2325 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2326 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2331 upload_ubo_surf_state(struct iris_context
*ice
,
2332 struct iris_const_buffer
*cbuf
,
2333 unsigned buffer_size
)
2335 struct pipe_context
*ctx
= &ice
->ctx
;
2336 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
2338 // XXX: these are not retained forever, use a separate uploader?
2340 upload_state(ice
->state
.surface_uploader
, &cbuf
->surface_state
,
2341 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2342 if (!unlikely(map
)) {
2343 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2347 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2348 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state
.res
);
2349 cbuf
->surface_state
.offset
+= iris_bo_offset_from_base_address(surf_bo
);
2351 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2352 .address
= res
->bo
->gtt_offset
+ cbuf
->data
.offset
,
2353 .size_B
= MIN2(buffer_size
,
2354 res
->bo
->size
- cbuf
->data
.offset
),
2355 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
2356 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2358 .mocs
= mocs(res
->bo
))
2362 * The pipe->set_constant_buffer() driver hook.
2364 * This uploads any constant data in user buffers, and references
2365 * any UBO resources containing constant data.
2368 iris_set_constant_buffer(struct pipe_context
*ctx
,
2369 enum pipe_shader_type p_stage
, unsigned index
,
2370 const struct pipe_constant_buffer
*input
)
2372 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2373 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2374 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2375 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
2377 if (input
&& input
->buffer
) {
2380 pipe_resource_reference(&cbuf
->data
.res
, input
->buffer
);
2381 cbuf
->data
.offset
= input
->buffer_offset
;
2383 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2384 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2386 upload_ubo_surf_state(ice
, cbuf
, input
->buffer_size
);
2388 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2389 pipe_resource_reference(&cbuf
->surface_state
.res
, NULL
);
2394 memcpy(&shs
->cbuf0
, input
, sizeof(shs
->cbuf0
));
2396 memset(&shs
->cbuf0
, 0, sizeof(shs
->cbuf0
));
2398 shs
->cbuf0_needs_upload
= true;
2401 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2402 // XXX: maybe not necessary all the time...?
2403 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2404 // XXX: pull model we may need actual new bindings...
2405 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2409 upload_uniforms(struct iris_context
*ice
,
2410 gl_shader_stage stage
)
2412 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2413 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
2414 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2416 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t) +
2417 shs
->cbuf0
.buffer_size
;
2419 if (upload_size
== 0)
2423 upload_state(ice
->ctx
.const_uploader
, &cbuf
->data
, upload_size
, 64);
2425 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2426 uint32_t sysval
= shader
->system_values
[i
];
2429 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
2430 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
2431 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
2432 struct brw_image_param
*param
= &shs
->image
[img
].param
;
2434 assert(offset
< sizeof(struct brw_image_param
));
2435 value
= ((uint32_t *) param
)[offset
];
2436 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
2438 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2439 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2440 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2441 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2442 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
2443 if (stage
== MESA_SHADER_TESS_CTRL
) {
2444 value
= ice
->state
.vertices_per_patch
;
2446 assert(stage
== MESA_SHADER_TESS_EVAL
);
2447 const struct shader_info
*tcs_info
=
2448 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
2451 value
= tcs_info
->tess
.tcs_vertices_out
;
2454 assert(!"unhandled system value");
2460 if (shs
->cbuf0
.user_buffer
) {
2461 memcpy(map
, shs
->cbuf0
.user_buffer
, shs
->cbuf0
.buffer_size
);
2464 upload_ubo_surf_state(ice
, cbuf
, upload_size
);
2468 * The pipe->set_shader_buffers() driver hook.
2470 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2471 * SURFACE_STATE here, as the buffer offset may change each time.
2474 iris_set_shader_buffers(struct pipe_context
*ctx
,
2475 enum pipe_shader_type p_stage
,
2476 unsigned start_slot
, unsigned count
,
2477 const struct pipe_shader_buffer
*buffers
)
2479 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2480 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2481 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2482 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2484 for (unsigned i
= 0; i
< count
; i
++) {
2485 if (buffers
&& buffers
[i
].buffer
) {
2486 const struct pipe_shader_buffer
*buffer
= &buffers
[i
];
2487 struct iris_resource
*res
= (void *) buffer
->buffer
;
2488 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], &res
->base
);
2490 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2492 // XXX: these are not retained forever, use a separate uploader?
2494 upload_state(ice
->state
.surface_uploader
,
2495 &shs
->ssbo_surface_state
[start_slot
+ i
],
2496 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2497 if (!unlikely(map
)) {
2498 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2502 struct iris_bo
*surf_state_bo
=
2503 iris_resource_bo(shs
->ssbo_surface_state
[start_slot
+ i
].res
);
2504 shs
->ssbo_surface_state
[start_slot
+ i
].offset
+=
2505 iris_bo_offset_from_base_address(surf_state_bo
);
2507 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2509 res
->bo
->gtt_offset
+ buffer
->buffer_offset
,
2511 MIN2(buffer
->buffer_size
,
2512 res
->bo
->size
- buffer
->buffer_offset
),
2513 .format
= ISL_FORMAT_RAW
,
2514 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2516 .mocs
= mocs(res
->bo
));
2518 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2519 pipe_resource_reference(&shs
->ssbo_surface_state
[start_slot
+ i
].res
,
2524 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2528 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2534 * The pipe->set_vertex_buffers() driver hook.
2536 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2539 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2540 unsigned start_slot
, unsigned count
,
2541 const struct pipe_vertex_buffer
*buffers
)
2543 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2544 struct iris_genx_state
*genx
= ice
->state
.genx
;
2546 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
2548 for (unsigned i
= 0; i
< count
; i
++) {
2549 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
2550 struct iris_vertex_buffer_state
*state
=
2551 &genx
->vertex_buffers
[start_slot
+ i
];
2554 pipe_resource_reference(&state
->resource
, NULL
);
2558 assert(!buffer
->is_user_buffer
);
2560 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
2561 struct iris_resource
*res
= (void *) state
->resource
;
2564 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
2565 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2568 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
2569 vb
.VertexBufferIndex
= start_slot
+ i
;
2570 vb
.AddressModifyEnable
= true;
2571 vb
.BufferPitch
= buffer
->stride
;
2573 vb
.BufferSize
= res
->bo
->size
;
2574 vb
.BufferStartingAddress
=
2575 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
2576 vb
.MOCS
= mocs(res
->bo
);
2578 vb
.NullVertexBuffer
= true;
2583 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2587 * Gallium CSO for vertex elements.
2589 struct iris_vertex_element_state
{
2590 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2591 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2592 uint32_t edgeflag_ve
[GENX(VERTEX_ELEMENT_STATE_length
)];
2593 uint32_t edgeflag_vfi
[GENX(3DSTATE_VF_INSTANCING_length
)];
2598 * The pipe->create_vertex_elements() driver hook.
2600 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2601 * and 3DSTATE_VF_INSTANCING commands. The vertex_elements and vf_instancing
2602 * arrays are ready to be emitted at draw time if no EdgeFlag or SGVs are
2603 * needed. In these cases we will need information available at draw time.
2604 * We setup edgeflag_ve and edgeflag_vfi as alternatives last
2605 * 3DSTATE_VERTEX_ELEMENT and 3DSTATE_VF_INSTANCING that can be used at
2606 * draw time if we detect that EdgeFlag is needed by the Vertex Shader.
2609 iris_create_vertex_elements(struct pipe_context
*ctx
,
2611 const struct pipe_vertex_element
*state
)
2613 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2614 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2615 struct iris_vertex_element_state
*cso
=
2616 malloc(sizeof(struct iris_vertex_element_state
));
2620 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2622 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2625 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2626 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2629 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2631 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2632 ve
.Component0Control
= VFCOMP_STORE_0
;
2633 ve
.Component1Control
= VFCOMP_STORE_0
;
2634 ve
.Component2Control
= VFCOMP_STORE_0
;
2635 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2638 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2642 for (int i
= 0; i
< count
; i
++) {
2643 const struct iris_format_info fmt
=
2644 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2645 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2646 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2648 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2649 case 0: comp
[0] = VFCOMP_STORE_0
;
2650 case 1: comp
[1] = VFCOMP_STORE_0
;
2651 case 2: comp
[2] = VFCOMP_STORE_0
;
2653 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2654 : VFCOMP_STORE_1_FP
;
2657 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2658 ve
.EdgeFlagEnable
= false;
2659 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2661 ve
.SourceElementOffset
= state
[i
].src_offset
;
2662 ve
.SourceElementFormat
= fmt
.fmt
;
2663 ve
.Component0Control
= comp
[0];
2664 ve
.Component1Control
= comp
[1];
2665 ve
.Component2Control
= comp
[2];
2666 ve
.Component3Control
= comp
[3];
2669 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2670 vi
.VertexElementIndex
= i
;
2671 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2672 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2675 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2676 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2679 /* An alternative version of the last VE and VFI is stored so it
2680 * can be used at draw time in case Vertex Shader uses EdgeFlag
2683 const unsigned edgeflag_index
= count
- 1;
2684 const struct iris_format_info fmt
=
2685 iris_format_for_usage(devinfo
, state
[edgeflag_index
].src_format
, 0);
2686 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), cso
->edgeflag_ve
, ve
) {
2687 ve
.EdgeFlagEnable
= true ;
2688 ve
.VertexBufferIndex
= state
[edgeflag_index
].vertex_buffer_index
;
2690 ve
.SourceElementOffset
= state
[edgeflag_index
].src_offset
;
2691 ve
.SourceElementFormat
= fmt
.fmt
;
2692 ve
.Component0Control
= VFCOMP_STORE_SRC
;
2693 ve
.Component1Control
= VFCOMP_STORE_0
;
2694 ve
.Component2Control
= VFCOMP_STORE_0
;
2695 ve
.Component3Control
= VFCOMP_STORE_0
;
2697 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->edgeflag_vfi
, vi
) {
2698 /* The vi.VertexElementIndex of the EdgeFlag Vertex Element is filled
2699 * at draw time, as it should change if SGVs are emitted.
2701 vi
.InstancingEnable
= state
[edgeflag_index
].instance_divisor
> 0;
2702 vi
.InstanceDataStepRate
= state
[edgeflag_index
].instance_divisor
;
2710 * The pipe->bind_vertex_elements_state() driver hook.
2713 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2715 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2716 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2717 struct iris_vertex_element_state
*new_cso
= state
;
2719 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2720 * we need to re-emit it to ensure we're overriding the right one.
2722 if (new_cso
&& cso_changed(count
))
2723 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2725 ice
->state
.cso_vertex_elements
= state
;
2726 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2730 * The pipe->create_stream_output_target() driver hook.
2732 * "Target" here refers to a destination buffer. We translate this into
2733 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2734 * know which buffer this represents, or whether we ought to zero the
2735 * write-offsets, or append. Those are handled in the set() hook.
2737 static struct pipe_stream_output_target
*
2738 iris_create_stream_output_target(struct pipe_context
*ctx
,
2739 struct pipe_resource
*p_res
,
2740 unsigned buffer_offset
,
2741 unsigned buffer_size
)
2743 struct iris_resource
*res
= (void *) p_res
;
2744 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2748 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
2750 pipe_reference_init(&cso
->base
.reference
, 1);
2751 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
2752 cso
->base
.buffer_offset
= buffer_offset
;
2753 cso
->base
.buffer_size
= buffer_size
;
2754 cso
->base
.context
= ctx
;
2756 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
2762 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2763 struct pipe_stream_output_target
*state
)
2765 struct iris_stream_output_target
*cso
= (void *) state
;
2767 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2768 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2774 * The pipe->set_stream_output_targets() driver hook.
2776 * At this point, we know which targets are bound to a particular index,
2777 * and also whether we want to append or start over. We can finish the
2778 * 3DSTATE_SO_BUFFER packets we started earlier.
2781 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2782 unsigned num_targets
,
2783 struct pipe_stream_output_target
**targets
,
2784 const unsigned *offsets
)
2786 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2787 struct iris_genx_state
*genx
= ice
->state
.genx
;
2788 uint32_t *so_buffers
= genx
->so_buffers
;
2790 const bool active
= num_targets
> 0;
2791 if (ice
->state
.streamout_active
!= active
) {
2792 ice
->state
.streamout_active
= active
;
2793 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2795 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
2796 * it's a non-pipelined command. If we're switching streamout on, we
2797 * may have missed emitting it earlier, so do so now. (We're already
2798 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
2801 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
2804 for (int i
= 0; i
< 4; i
++) {
2805 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2806 i
< num_targets
? targets
[i
] : NULL
);
2809 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2813 for (unsigned i
= 0; i
< 4; i
++,
2814 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2816 if (i
>= num_targets
|| !targets
[i
]) {
2817 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
2818 sob
.SOBufferIndex
= i
;
2822 struct iris_stream_output_target
*tgt
= (void *) targets
[i
];
2823 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
2825 /* Note that offsets[i] will either be 0, causing us to zero
2826 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
2827 * "continue appending at the existing offset."
2829 assert(offsets
[i
] == 0 || offsets
[i
] == 0xFFFFFFFF);
2831 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
2832 sob
.SurfaceBaseAddress
=
2833 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
2834 sob
.SOBufferEnable
= true;
2835 sob
.StreamOffsetWriteEnable
= true;
2836 sob
.StreamOutputBufferOffsetAddressEnable
= true;
2837 sob
.MOCS
= mocs(res
->bo
);
2839 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
2841 sob
.SOBufferIndex
= i
;
2842 sob
.StreamOffset
= offsets
[i
];
2843 sob
.StreamOutputBufferOffsetAddress
=
2844 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
2845 tgt
->offset
.offset
);
2849 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
2853 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
2854 * 3DSTATE_STREAMOUT packets.
2856 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
2857 * hardware to record. We can create it entirely based on the shader, with
2858 * no dynamic state dependencies.
2860 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
2861 * state-based settings. We capture the shader-related ones here, and merge
2862 * the rest in at draw time.
2865 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
2866 const struct brw_vue_map
*vue_map
)
2868 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2869 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2870 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2871 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2873 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2875 memset(so_decl
, 0, sizeof(so_decl
));
2877 /* Construct the list of SO_DECLs to be emitted. The formatting of the
2878 * command feels strange -- each dword pair contains a SO_DECL per stream.
2880 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
2881 const struct pipe_stream_output
*output
= &info
->output
[i
];
2882 const int buffer
= output
->output_buffer
;
2883 const int varying
= output
->register_index
;
2884 const unsigned stream_id
= output
->stream
;
2885 assert(stream_id
< MAX_VERTEX_STREAMS
);
2887 buffer_mask
[stream_id
] |= 1 << buffer
;
2889 assert(vue_map
->varying_to_slot
[varying
] >= 0);
2891 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
2892 * array. Instead, it simply increments DstOffset for the following
2893 * input by the number of components that should be skipped.
2895 * Our hardware is unusual in that it requires us to program SO_DECLs
2896 * for fake "hole" components, rather than simply taking the offset
2897 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
2898 * program as many size = 4 holes as we can, then a final hole to
2899 * accommodate the final 1, 2, or 3 remaining.
2901 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
2903 while (skip_components
> 0) {
2904 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2906 .OutputBufferSlot
= output
->output_buffer
,
2907 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
2909 skip_components
-= 4;
2912 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
2914 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2915 .OutputBufferSlot
= output
->output_buffer
,
2916 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
2918 ((1 << output
->num_components
) - 1) << output
->start_component
,
2921 if (decls
[stream_id
] > max_decls
)
2922 max_decls
= decls
[stream_id
];
2925 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
2926 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
2927 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
2929 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
2930 int urb_entry_read_offset
= 0;
2931 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
2932 urb_entry_read_offset
;
2934 /* We always read the whole vertex. This could be reduced at some
2935 * point by reading less and offsetting the register index in the
2938 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
2939 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
2940 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
2941 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
2942 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
2943 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
2944 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
2945 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
2947 /* Set buffer pitches; 0 means unbound. */
2948 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
2949 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
2950 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
2951 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
2954 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
2955 list
.DWordLength
= 3 + 2 * max_decls
- 2;
2956 list
.StreamtoBufferSelects0
= buffer_mask
[0];
2957 list
.StreamtoBufferSelects1
= buffer_mask
[1];
2958 list
.StreamtoBufferSelects2
= buffer_mask
[2];
2959 list
.StreamtoBufferSelects3
= buffer_mask
[3];
2960 list
.NumEntries0
= decls
[0];
2961 list
.NumEntries1
= decls
[1];
2962 list
.NumEntries2
= decls
[2];
2963 list
.NumEntries3
= decls
[3];
2966 for (int i
= 0; i
< max_decls
; i
++) {
2967 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
2968 entry
.Stream0Decl
= so_decl
[0][i
];
2969 entry
.Stream1Decl
= so_decl
[1][i
];
2970 entry
.Stream2Decl
= so_decl
[2][i
];
2971 entry
.Stream3Decl
= so_decl
[3][i
];
2979 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
2980 const struct brw_vue_map
*last_vue_map
,
2981 bool two_sided_color
,
2982 unsigned *out_offset
,
2983 unsigned *out_length
)
2985 /* The compiler computes the first URB slot without considering COL/BFC
2986 * swizzling (because it doesn't know whether it's enabled), so we need
2987 * to do that here too. This may result in a smaller offset, which
2990 const unsigned first_slot
=
2991 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
2993 /* This becomes the URB read offset (counted in pairs of slots). */
2994 assert(first_slot
% 2 == 0);
2995 *out_offset
= first_slot
/ 2;
2997 /* We need to adjust the inputs read to account for front/back color
2998 * swizzling, as it can make the URB length longer.
3000 for (int c
= 0; c
<= 1; c
++) {
3001 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
3002 /* If two sided color is enabled, the fragment shader's gl_Color
3003 * (COL0) input comes from either the gl_FrontColor (COL0) or
3004 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
3006 if (two_sided_color
)
3007 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3009 /* If front color isn't written, we opt to give them back color
3010 * instead of an undefined value. Switch from COL to BFC.
3012 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
3013 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
3014 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3019 /* Compute the minimum URB Read Length necessary for the FS inputs.
3021 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
3022 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
3024 * "This field should be set to the minimum length required to read the
3025 * maximum source attribute. The maximum source attribute is indicated
3026 * by the maximum value of the enabled Attribute # Source Attribute if
3027 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
3028 * enable is not set.
3029 * read_length = ceiling((max_source_attr + 1) / 2)
3031 * [errata] Corruption/Hang possible if length programmed larger than
3034 * Similar text exists for Ivy Bridge.
3036 * We find the last URB slot that's actually read by the FS.
3038 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
3039 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
3040 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
3043 /* The URB read length is the difference of the two, counted in pairs. */
3044 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
3048 iris_emit_sbe_swiz(struct iris_batch
*batch
,
3049 const struct iris_context
*ice
,
3050 unsigned urb_read_offset
,
3051 unsigned sprite_coord_enables
)
3053 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
3054 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3055 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3056 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
3057 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3059 /* XXX: this should be generated when putting programs in place */
3061 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
3062 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
3063 if (input_index
< 0 || input_index
>= 16)
3066 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
3067 &attr_overrides
[input_index
];
3068 int slot
= vue_map
->varying_to_slot
[fs_attr
];
3070 /* Viewport and Layer are stored in the VUE header. We need to override
3071 * them to zero if earlier stages didn't write them, as GL requires that
3072 * they read back as zero when not explicitly set.
3075 case VARYING_SLOT_VIEWPORT
:
3076 case VARYING_SLOT_LAYER
:
3077 attr
->ComponentOverrideX
= true;
3078 attr
->ComponentOverrideW
= true;
3079 attr
->ConstantSource
= CONST_0000
;
3081 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
3082 attr
->ComponentOverrideY
= true;
3083 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
3084 attr
->ComponentOverrideZ
= true;
3087 case VARYING_SLOT_PRIMITIVE_ID
:
3088 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
3090 attr
->ComponentOverrideX
= true;
3091 attr
->ComponentOverrideY
= true;
3092 attr
->ComponentOverrideZ
= true;
3093 attr
->ComponentOverrideW
= true;
3094 attr
->ConstantSource
= PRIM_ID
;
3102 if (sprite_coord_enables
& (1 << input_index
))
3105 /* If there was only a back color written but not front, use back
3106 * as the color instead of undefined.
3108 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
3109 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
3110 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
3111 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
3113 /* Not written by the previous stage - undefined. */
3115 attr
->ComponentOverrideX
= true;
3116 attr
->ComponentOverrideY
= true;
3117 attr
->ComponentOverrideZ
= true;
3118 attr
->ComponentOverrideW
= true;
3119 attr
->ConstantSource
= CONST_0001_FLOAT
;
3123 /* Compute the location of the attribute relative to the read offset,
3124 * which is counted in 256-bit increments (two 128-bit VUE slots).
3126 const int source_attr
= slot
- 2 * urb_read_offset
;
3127 assert(source_attr
>= 0 && source_attr
<= 32);
3128 attr
->SourceAttribute
= source_attr
;
3130 /* If we are doing two-sided color, and the VUE slot following this one
3131 * represents a back-facing color, then we need to instruct the SF unit
3132 * to do back-facing swizzling.
3134 if (cso_rast
->light_twoside
&&
3135 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3136 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3137 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3138 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3139 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3142 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3143 for (int i
= 0; i
< 16; i
++)
3144 sbes
.Attribute
[i
] = attr_overrides
[i
];
3149 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3150 const struct iris_rasterizer_state
*cso
)
3152 unsigned overrides
= 0;
3154 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
3155 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
3157 for (int i
= 0; i
< 8; i
++) {
3158 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
3159 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
3160 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
3167 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
3169 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3170 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3171 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3172 const struct shader_info
*fs_info
=
3173 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
3175 unsigned urb_read_offset
, urb_read_length
;
3176 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
3177 ice
->shaders
.last_vue_map
,
3178 cso_rast
->light_twoside
,
3179 &urb_read_offset
, &urb_read_length
);
3181 unsigned sprite_coord_overrides
=
3182 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3184 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
3185 sbe
.AttributeSwizzleEnable
= true;
3186 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3187 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3188 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3189 sbe
.VertexURBEntryReadLength
= urb_read_length
;
3190 sbe
.ForceVertexURBEntryReadOffset
= true;
3191 sbe
.ForceVertexURBEntryReadLength
= true;
3192 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3193 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
3195 for (int i
= 0; i
< 32; i
++) {
3196 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3201 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
3204 /* ------------------------------------------------------------------- */
3207 * Populate VS program key fields based on the current state.
3210 iris_populate_vs_key(const struct iris_context
*ice
,
3211 const struct shader_info
*info
,
3212 struct brw_vs_prog_key
*key
)
3214 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3216 if (info
->clip_distance_array_size
== 0 &&
3217 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)))
3218 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3222 * Populate TCS program key fields based on the current state.
3225 iris_populate_tcs_key(const struct iris_context
*ice
,
3226 struct brw_tcs_prog_key
*key
)
3231 * Populate TES program key fields based on the current state.
3234 iris_populate_tes_key(const struct iris_context
*ice
,
3235 struct brw_tes_prog_key
*key
)
3240 * Populate GS program key fields based on the current state.
3243 iris_populate_gs_key(const struct iris_context
*ice
,
3244 struct brw_gs_prog_key
*key
)
3249 * Populate FS program key fields based on the current state.
3252 iris_populate_fs_key(const struct iris_context
*ice
,
3253 struct brw_wm_prog_key
*key
)
3255 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3256 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3257 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3258 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3260 key
->nr_color_regions
= fb
->nr_cbufs
;
3262 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3264 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
3265 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
3267 /* XXX: only bother if COL0/1 are read */
3268 key
->flat_shade
= rast
->flatshade
;
3270 key
->persample_interp
= rast
->force_persample_interp
;
3271 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3273 key
->coherent_fb_fetch
= true;
3275 /* TODO: support key->force_dual_color_blend for Unigine */
3276 /* TODO: Respect glHint for key->high_quality_derivatives */
3280 iris_populate_cs_key(const struct iris_context
*ice
,
3281 struct brw_cs_prog_key
*key
)
3286 KSP(const struct iris_compiled_shader
*shader
)
3288 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3289 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3292 /* Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3293 * prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3294 * this WA on C0 stepping.
3296 * TODO: Fill out SamplerCount for prefetching?
3299 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3300 pkt.KernelStartPointer = KSP(shader); \
3301 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3302 prog_data->binding_table.size_bytes / 4; \
3303 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3305 pkt.DispatchGRFStartRegisterForURBData = \
3306 prog_data->dispatch_grf_start_reg; \
3307 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3308 pkt.prefix##URBEntryReadOffset = 0; \
3310 pkt.StatisticsEnable = true; \
3311 pkt.Enable = true; \
3313 if (prog_data->total_scratch) { \
3314 struct iris_bo *bo = \
3315 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3316 uint32_t scratch_addr = bo->gtt_offset; \
3317 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3318 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3322 * Encode most of 3DSTATE_VS based on the compiled shader.
3325 iris_store_vs_state(struct iris_context
*ice
,
3326 const struct gen_device_info
*devinfo
,
3327 struct iris_compiled_shader
*shader
)
3329 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3330 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3332 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3333 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3334 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3335 vs
.SIMD8DispatchEnable
= true;
3336 vs
.UserClipDistanceCullTestEnableBitmask
=
3337 vue_prog_data
->cull_distance_mask
;
3342 * Encode most of 3DSTATE_HS based on the compiled shader.
3345 iris_store_tcs_state(struct iris_context
*ice
,
3346 const struct gen_device_info
*devinfo
,
3347 struct iris_compiled_shader
*shader
)
3349 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3350 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3351 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3353 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3354 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3356 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3357 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3358 hs
.IncludeVertexHandles
= true;
3363 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3366 iris_store_tes_state(struct iris_context
*ice
,
3367 const struct gen_device_info
*devinfo
,
3368 struct iris_compiled_shader
*shader
)
3370 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3371 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3372 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3374 uint32_t *te_state
= (void *) shader
->derived_data
;
3375 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3377 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3378 te
.Partitioning
= tes_prog_data
->partitioning
;
3379 te
.OutputTopology
= tes_prog_data
->output_topology
;
3380 te
.TEDomain
= tes_prog_data
->domain
;
3382 te
.MaximumTessellationFactorOdd
= 63.0;
3383 te
.MaximumTessellationFactorNotOdd
= 64.0;
3386 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3387 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3389 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3390 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3391 ds
.ComputeWCoordinateEnable
=
3392 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3394 ds
.UserClipDistanceCullTestEnableBitmask
=
3395 vue_prog_data
->cull_distance_mask
;
3401 * Encode most of 3DSTATE_GS based on the compiled shader.
3404 iris_store_gs_state(struct iris_context
*ice
,
3405 const struct gen_device_info
*devinfo
,
3406 struct iris_compiled_shader
*shader
)
3408 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3409 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3410 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3412 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3413 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3415 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3416 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3417 gs
.ControlDataHeaderSize
=
3418 gs_prog_data
->control_data_header_size_hwords
;
3419 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3420 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3421 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3422 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3423 gs
.ReorderMode
= TRAILING
;
3424 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3425 gs
.MaximumNumberofThreads
=
3426 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3427 : (devinfo
->max_gs_threads
- 1);
3429 if (gs_prog_data
->static_vertex_count
!= -1) {
3430 gs
.StaticOutput
= true;
3431 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3433 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3435 gs
.UserClipDistanceCullTestEnableBitmask
=
3436 vue_prog_data
->cull_distance_mask
;
3438 const int urb_entry_write_offset
= 1;
3439 const uint32_t urb_entry_output_length
=
3440 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3441 urb_entry_write_offset
;
3443 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3444 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3449 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3452 iris_store_fs_state(struct iris_context
*ice
,
3453 const struct gen_device_info
*devinfo
,
3454 struct iris_compiled_shader
*shader
)
3456 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3457 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3459 uint32_t *ps_state
= (void *) shader
->derived_data
;
3460 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3462 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3463 ps
.VectorMaskEnable
= true;
3464 // XXX: WABTPPrefetchDisable, see above, drop at C0
3465 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3466 prog_data
->binding_table
.size_bytes
/ 4;
3467 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3468 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3470 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
3472 /* From the documentation for this packet:
3473 * "If the PS kernel does not need the Position XY Offsets to
3474 * compute a Position Value, then this field should be programmed
3475 * to POSOFFSET_NONE."
3477 * "SW Recommendation: If the PS kernel needs the Position Offsets
3478 * to compute a Position XY value, this field should match Position
3479 * ZW Interpolation Mode to ensure a consistent position.xyzw
3482 * We only require XY sample offsets. So, this recommendation doesn't
3483 * look useful at the moment. We might need this in future.
3485 ps
.PositionXYOffsetSelect
=
3486 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3487 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
3488 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
3489 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
3491 // XXX: Disable SIMD32 with 16x MSAA
3493 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3494 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
3495 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
3496 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
3497 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3498 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
3500 ps
.KernelStartPointer0
=
3501 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
3502 ps
.KernelStartPointer1
=
3503 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
3504 ps
.KernelStartPointer2
=
3505 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
3507 if (prog_data
->total_scratch
) {
3508 struct iris_bo
*bo
=
3509 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3510 MESA_SHADER_FRAGMENT
);
3511 uint32_t scratch_addr
= bo
->gtt_offset
;
3512 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3513 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3517 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3518 psx
.PixelShaderValid
= true;
3519 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3520 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
3521 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3522 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3523 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3524 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3525 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3528 if (wm_prog_data
->uses_sample_mask
) {
3529 /* TODO: conservative rasterization */
3530 if (wm_prog_data
->post_depth_coverage
)
3531 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
3533 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
3536 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3537 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3539 psx
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
3546 * Compute the size of the derived data (shader command packets).
3548 * This must match the data written by the iris_store_xs_state() functions.
3551 iris_store_cs_state(struct iris_context
*ice
,
3552 const struct gen_device_info
*devinfo
,
3553 struct iris_compiled_shader
*shader
)
3555 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3556 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3557 void *map
= shader
->derived_data
;
3559 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3560 desc
.KernelStartPointer
= KSP(shader
);
3561 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3562 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3563 desc
.SharedLocalMemorySize
=
3564 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3565 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3566 desc
.CrossThreadConstantDataReadLength
=
3567 cs_prog_data
->push
.cross_thread
.regs
;
3572 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3574 assert(cache_id
<= IRIS_CACHE_BLORP
);
3576 static const unsigned dwords
[] = {
3577 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3578 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3579 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3580 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3582 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3583 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3584 [IRIS_CACHE_BLORP
] = 0,
3587 return sizeof(uint32_t) * dwords
[cache_id
];
3591 * Create any state packets corresponding to the given shader stage
3592 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3593 * This means that we can look up a program in the in-memory cache and
3594 * get most of the state packet without having to reconstruct it.
3597 iris_store_derived_program_state(struct iris_context
*ice
,
3598 enum iris_program_cache_id cache_id
,
3599 struct iris_compiled_shader
*shader
)
3601 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3602 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3606 iris_store_vs_state(ice
, devinfo
, shader
);
3608 case IRIS_CACHE_TCS
:
3609 iris_store_tcs_state(ice
, devinfo
, shader
);
3611 case IRIS_CACHE_TES
:
3612 iris_store_tes_state(ice
, devinfo
, shader
);
3615 iris_store_gs_state(ice
, devinfo
, shader
);
3618 iris_store_fs_state(ice
, devinfo
, shader
);
3621 iris_store_cs_state(ice
, devinfo
, shader
);
3622 case IRIS_CACHE_BLORP
:
3629 /* ------------------------------------------------------------------- */
3632 * Configure the URB.
3634 * XXX: write a real comment.
3637 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
3639 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
3640 const unsigned push_size_kB
= 32;
3641 unsigned entries
[4];
3645 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3646 if (!ice
->shaders
.prog
[i
]) {
3649 struct brw_vue_prog_data
*vue_prog_data
=
3650 (void *) ice
->shaders
.prog
[i
]->prog_data
;
3651 size
[i
] = vue_prog_data
->urb_entry_size
;
3653 assert(size
[i
] != 0);
3656 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
3657 1024 * ice
->shaders
.urb_size
,
3658 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
3659 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
3660 size
, entries
, start
);
3662 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3663 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
3664 urb
._3DCommandSubOpcode
+= i
;
3665 urb
.VSURBStartingAddress
= start
[i
];
3666 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
3667 urb
.VSNumberofURBEntries
= entries
[i
];
3672 static const uint32_t push_constant_opcodes
[] = {
3673 [MESA_SHADER_VERTEX
] = 21,
3674 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3675 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3676 [MESA_SHADER_GEOMETRY
] = 22,
3677 [MESA_SHADER_FRAGMENT
] = 23,
3678 [MESA_SHADER_COMPUTE
] = 0,
3682 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3684 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3686 iris_use_pinned_bo(batch
, state_bo
, false);
3688 return ice
->state
.unbound_tex
.offset
;
3692 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3694 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3695 if (!ice
->state
.null_fb
.res
)
3696 return use_null_surface(batch
, ice
);
3698 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3700 iris_use_pinned_bo(batch
, state_bo
, false);
3702 return ice
->state
.null_fb
.offset
;
3706 surf_state_offset_for_aux(struct iris_resource
*res
,
3707 enum isl_aux_usage aux_usage
)
3709 return SURFACE_STATE_ALIGNMENT
*
3710 util_bitcount(res
->aux
.possible_usages
& ((1 << aux_usage
) - 1));
3714 * Add a surface to the validation list, as well as the buffer containing
3715 * the corresponding SURFACE_STATE.
3717 * Returns the binding table entry (offset to SURFACE_STATE).
3720 use_surface(struct iris_batch
*batch
,
3721 struct pipe_surface
*p_surf
,
3723 enum isl_aux_usage aux_usage
)
3725 struct iris_surface
*surf
= (void *) p_surf
;
3726 struct iris_resource
*res
= (void *) p_surf
->texture
;
3728 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
3729 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
3732 iris_use_pinned_bo(batch
, res
->aux
.bo
, writeable
);
3734 return surf
->surface_state
.offset
+
3735 surf_state_offset_for_aux(res
, aux_usage
);
3739 use_sampler_view(struct iris_context
*ice
,
3740 struct iris_batch
*batch
,
3741 struct iris_sampler_view
*isv
)
3744 enum isl_aux_usage aux_usage
=
3745 iris_resource_texture_aux_usage(ice
, isv
->res
, isv
->view
.format
, 0);
3747 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
3748 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
3750 if (isv
->res
->aux
.bo
)
3751 iris_use_pinned_bo(batch
, isv
->res
->aux
.bo
, false);
3753 return isv
->surface_state
.offset
+
3754 surf_state_offset_for_aux(isv
->res
, aux_usage
);
3758 use_const_buffer(struct iris_batch
*batch
,
3759 struct iris_context
*ice
,
3760 struct iris_const_buffer
*cbuf
)
3762 if (!cbuf
->surface_state
.res
)
3763 return use_null_surface(batch
, ice
);
3765 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->data
.res
), false);
3766 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->surface_state
.res
), false);
3768 return cbuf
->surface_state
.offset
;
3772 use_ssbo(struct iris_batch
*batch
, struct iris_context
*ice
,
3773 struct iris_shader_state
*shs
, int i
)
3776 return use_null_surface(batch
, ice
);
3778 struct iris_state_ref
*surf_state
= &shs
->ssbo_surface_state
[i
];
3780 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->ssbo
[i
]), true);
3781 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3783 return surf_state
->offset
;
3787 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
3788 struct iris_shader_state
*shs
, int i
)
3790 if (!shs
->image
[i
].res
)
3791 return use_null_surface(batch
, ice
);
3793 struct iris_resource
*res
= (void *) shs
->image
[i
].res
;
3794 struct iris_state_ref
*surf_state
= &shs
->image
[i
].surface_state
;
3795 bool write
= shs
->image
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
;
3797 iris_use_pinned_bo(batch
, res
->bo
, write
);
3798 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3801 iris_use_pinned_bo(batch
, res
->aux
.bo
, write
);
3803 return surf_state
->offset
;
3806 #define push_bt_entry(addr) \
3807 assert(addr >= binder_addr); \
3808 assert(s < prog_data->binding_table.size_bytes / sizeof(uint32_t)); \
3809 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
3811 #define bt_assert(section, exists) \
3812 if (!pin_only) assert(prog_data->binding_table.section == \
3813 (exists) ? s : 0xd0d0d0d0)
3816 * Populate the binding table for a given shader stage.
3818 * This fills out the table of pointers to surfaces required by the shader,
3819 * and also adds those buffers to the validation list so the kernel can make
3820 * resident before running our batch.
3823 iris_populate_binding_table(struct iris_context
*ice
,
3824 struct iris_batch
*batch
,
3825 gl_shader_stage stage
,
3828 const struct iris_binder
*binder
= &ice
->state
.binder
;
3829 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3833 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3834 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3835 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
3837 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
3838 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
3841 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
3843 /* TCS passthrough doesn't need a binding table. */
3844 assert(stage
== MESA_SHADER_TESS_CTRL
);
3848 if (stage
== MESA_SHADER_COMPUTE
) {
3849 /* surface for gl_NumWorkGroups */
3850 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
3851 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
3852 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
3853 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
3854 push_bt_entry(grid_state
->offset
);
3857 if (stage
== MESA_SHADER_FRAGMENT
) {
3858 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3859 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
3860 if (cso_fb
->nr_cbufs
) {
3861 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
3863 if (cso_fb
->cbufs
[i
]) {
3864 addr
= use_surface(batch
, cso_fb
->cbufs
[i
], true,
3865 ice
->state
.draw_aux_usage
[i
]);
3867 addr
= use_null_fb_surface(batch
, ice
);
3869 push_bt_entry(addr
);
3872 uint32_t addr
= use_null_fb_surface(batch
, ice
);
3873 push_bt_entry(addr
);
3877 unsigned num_textures
= util_last_bit(info
->textures_used
);
3879 bt_assert(texture_start
, num_textures
> 0);
3881 for (int i
= 0; i
< num_textures
; i
++) {
3882 struct iris_sampler_view
*view
= shs
->textures
[i
];
3883 uint32_t addr
= view
? use_sampler_view(ice
, batch
, view
)
3884 : use_null_surface(batch
, ice
);
3885 push_bt_entry(addr
);
3888 bt_assert(image_start
, info
->num_images
> 0);
3890 for (int i
= 0; i
< info
->num_images
; i
++) {
3891 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
3892 push_bt_entry(addr
);
3895 bt_assert(ubo_start
, shader
->num_cbufs
> 0);
3897 for (int i
= 0; i
< shader
->num_cbufs
; i
++) {
3898 uint32_t addr
= use_const_buffer(batch
, ice
, &shs
->constbuf
[i
]);
3899 push_bt_entry(addr
);
3902 bt_assert(ssbo_start
, info
->num_abos
+ info
->num_ssbos
> 0);
3904 /* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
3905 * for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
3906 * in st_atom_storagebuf.c so it'll compact them into one range, with
3907 * SSBOs starting at info->num_abos. Ideally it'd reset num_abos to 0 too
3909 if (info
->num_abos
+ info
->num_ssbos
> 0) {
3910 for (int i
= 0; i
< IRIS_MAX_ABOS
+ info
->num_ssbos
; i
++) {
3911 uint32_t addr
= use_ssbo(batch
, ice
, shs
, i
);
3912 push_bt_entry(addr
);
3917 /* XXX: YUV surfaces not implemented yet */
3918 bt_assert(plane_start
[1], ...);
3919 bt_assert(plane_start
[2], ...);
3924 iris_use_optional_res(struct iris_batch
*batch
,
3925 struct pipe_resource
*res
,
3929 struct iris_bo
*bo
= iris_resource_bo(res
);
3930 iris_use_pinned_bo(batch
, bo
, writeable
);
3934 /* ------------------------------------------------------------------- */
3937 * Pin any BOs which were installed by a previous batch, and restored
3938 * via the hardware logical context mechanism.
3940 * We don't need to re-emit all state every batch - the hardware context
3941 * mechanism will save and restore it for us. This includes pointers to
3942 * various BOs...which won't exist unless we ask the kernel to pin them
3943 * by adding them to the validation list.
3945 * We can skip buffers if we've re-emitted those packets, as we're
3946 * overwriting those stale pointers with new ones, and don't actually
3947 * refer to the old BOs.
3950 iris_restore_render_saved_bos(struct iris_context
*ice
,
3951 struct iris_batch
*batch
,
3952 const struct pipe_draw_info
*draw
)
3954 struct iris_genx_state
*genx
= ice
->state
.genx
;
3956 const uint64_t clean
= ~ice
->state
.dirty
;
3958 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
3959 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
3962 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3963 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
3966 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
3967 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
3970 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3971 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
3974 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
3975 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
3978 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
3979 for (int i
= 0; i
< 4; i
++) {
3980 struct iris_stream_output_target
*tgt
=
3981 (void *) ice
->state
.so_target
[i
];
3983 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
3985 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
3991 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3992 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
3995 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3996 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4001 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4003 for (int i
= 0; i
< 4; i
++) {
4004 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4006 if (range
->length
== 0)
4009 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4010 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
4013 iris_use_pinned_bo(batch
, res
->bo
, false);
4015 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4019 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4020 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4021 /* Re-pin any buffers referred to by the binding table. */
4022 iris_populate_binding_table(ice
, batch
, stage
, true);
4026 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4027 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4028 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4030 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4033 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4034 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
4035 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4038 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4039 iris_use_pinned_bo(batch
, bo
, false);
4041 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4043 if (prog_data
->total_scratch
> 0) {
4044 struct iris_bo
*bo
=
4045 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4046 iris_use_pinned_bo(batch
, bo
, true);
4052 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
4053 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4055 if (cso_fb
->zsbuf
) {
4056 struct iris_resource
*zres
, *sres
;
4057 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
4060 iris_cache_flush_for_depth(batch
, zres
->bo
);
4062 iris_use_pinned_bo(batch
, zres
->bo
,
4063 ice
->state
.depth_writes_enabled
);
4065 iris_use_pinned_bo(batch
, zres
->aux
.bo
,
4066 ice
->state
.depth_writes_enabled
);
4071 iris_cache_flush_for_depth(batch
, sres
->bo
);
4073 iris_use_pinned_bo(batch
, sres
->bo
,
4074 ice
->state
.stencil_writes_enabled
);
4079 if (draw
->index_size
== 0 && ice
->state
.last_res
.index_buffer
) {
4080 /* This draw didn't emit a new index buffer, so we are inheriting the
4081 * older index buffer. This draw didn't need it, but future ones may.
4083 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4084 iris_use_pinned_bo(batch
, bo
, false);
4087 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4088 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4090 const int i
= u_bit_scan64(&bound
);
4091 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
4092 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4098 iris_restore_compute_saved_bos(struct iris_context
*ice
,
4099 struct iris_batch
*batch
,
4100 const struct pipe_grid_info
*grid
)
4102 const uint64_t clean
= ~ice
->state
.dirty
;
4104 const int stage
= MESA_SHADER_COMPUTE
;
4105 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4107 if (clean
& IRIS_DIRTY_CONSTANTS_CS
) {
4108 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4111 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4112 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[0];
4114 if (range
->length
> 0) {
4115 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4116 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
4119 iris_use_pinned_bo(batch
, res
->bo
, false);
4121 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4126 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
4127 /* Re-pin any buffers referred to by the binding table. */
4128 iris_populate_binding_table(ice
, batch
, stage
, true);
4131 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
4133 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
4135 if (clean
& IRIS_DIRTY_CS
) {
4136 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4139 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4140 iris_use_pinned_bo(batch
, bo
, false);
4142 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4144 if (prog_data
->total_scratch
> 0) {
4145 struct iris_bo
*bo
=
4146 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4147 iris_use_pinned_bo(batch
, bo
, true);
4154 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
4157 iris_update_surface_base_address(struct iris_batch
*batch
,
4158 struct iris_binder
*binder
)
4160 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
4163 flush_for_state_base_change(batch
);
4165 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
4166 sba
.SurfaceStateMOCS
= MOCS_WB
;
4167 sba
.SurfaceStateBaseAddressModifyEnable
= true;
4168 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
4171 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
4175 iris_upload_dirty_render_state(struct iris_context
*ice
,
4176 struct iris_batch
*batch
,
4177 const struct pipe_draw_info
*draw
)
4179 const uint64_t dirty
= ice
->state
.dirty
;
4181 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
4184 struct iris_genx_state
*genx
= ice
->state
.genx
;
4185 struct iris_binder
*binder
= &ice
->state
.binder
;
4186 struct brw_wm_prog_data
*wm_prog_data
= (void *)
4187 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
4189 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
4190 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4191 uint32_t cc_vp_address
;
4193 /* XXX: could avoid streaming for depth_clip [0,1] case. */
4194 uint32_t *cc_vp_map
=
4195 stream_state(batch
, ice
->state
.dynamic_uploader
,
4196 &ice
->state
.last_res
.cc_vp
,
4197 4 * ice
->state
.num_viewports
*
4198 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
4199 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4201 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
4202 cso_rast
->clip_halfz
, &zmin
, &zmax
);
4203 if (cso_rast
->depth_clip_near
)
4205 if (cso_rast
->depth_clip_far
)
4208 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
4209 ccv
.MinimumDepth
= zmin
;
4210 ccv
.MaximumDepth
= zmax
;
4213 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
4216 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
4217 ptr
.CCViewportPointer
= cc_vp_address
;
4221 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4222 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4223 uint32_t sf_cl_vp_address
;
4225 stream_state(batch
, ice
->state
.dynamic_uploader
,
4226 &ice
->state
.last_res
.sf_cl_vp
,
4227 4 * ice
->state
.num_viewports
*
4228 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
4230 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4231 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
4232 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
4234 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
4235 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
4236 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
4237 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
4239 calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
4240 state
->scale
[0], state
->scale
[1],
4241 state
->translate
[0], state
->translate
[1],
4242 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
4244 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
4245 vp
.ViewportMatrixElementm00
= state
->scale
[0];
4246 vp
.ViewportMatrixElementm11
= state
->scale
[1];
4247 vp
.ViewportMatrixElementm22
= state
->scale
[2];
4248 vp
.ViewportMatrixElementm30
= state
->translate
[0];
4249 vp
.ViewportMatrixElementm31
= state
->translate
[1];
4250 vp
.ViewportMatrixElementm32
= state
->translate
[2];
4251 vp
.XMinClipGuardband
= gb_xmin
;
4252 vp
.XMaxClipGuardband
= gb_xmax
;
4253 vp
.YMinClipGuardband
= gb_ymin
;
4254 vp
.YMaxClipGuardband
= gb_ymax
;
4255 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
4256 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
4257 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
4258 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
4261 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
4264 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
4265 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
4269 if (dirty
& IRIS_DIRTY_URB
) {
4270 iris_upload_urb_config(ice
, batch
);
4273 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
4274 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4275 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4276 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4277 const int header_dwords
= GENX(BLEND_STATE_length
);
4279 /* Always write at least one BLEND_STATE - the final RT message will
4280 * reference BLEND_STATE[0] even if there aren't color writes. There
4281 * may still be alpha testing, computed depth, and so on.
4283 const int rt_dwords
=
4284 MAX2(cso_fb
->nr_cbufs
, 1) * GENX(BLEND_STATE_ENTRY_length
);
4286 uint32_t blend_offset
;
4287 uint32_t *blend_map
=
4288 stream_state(batch
, ice
->state
.dynamic_uploader
,
4289 &ice
->state
.last_res
.blend
,
4290 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4292 uint32_t blend_state_header
;
4293 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4294 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4295 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4298 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4299 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4301 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4302 ptr
.BlendStatePointer
= blend_offset
;
4303 ptr
.BlendStatePointerValid
= true;
4307 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4308 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4310 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4314 stream_state(batch
, ice
->state
.dynamic_uploader
,
4315 &ice
->state
.last_res
.color_calc
,
4316 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4318 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4319 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4320 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4321 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4322 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4323 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4324 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4326 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4327 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4330 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4331 ptr
.ColorCalcStatePointer
= cc_offset
;
4332 ptr
.ColorCalcStatePointerValid
= true;
4336 /* Upload constants for TCS passthrough. */
4337 if ((dirty
& IRIS_DIRTY_CONSTANTS_TCS
) &&
4338 ice
->shaders
.prog
[MESA_SHADER_TESS_CTRL
] &&
4339 !ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
]) {
4340 struct iris_compiled_shader
*tes_shader
= ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
4343 /* Passthrough always copies 2 vec4s, so when uploading data we ensure
4344 * it is in the right layout for TES.
4347 struct brw_tes_prog_data
*tes_prog_data
= (void *) tes_shader
->prog_data
;
4348 switch (tes_prog_data
->domain
) {
4349 case BRW_TESS_DOMAIN_QUAD
:
4350 for (int i
= 0; i
< 4; i
++)
4351 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4352 hdr
[3] = ice
->state
.default_inner_level
[0];
4353 hdr
[2] = ice
->state
.default_inner_level
[1];
4355 case BRW_TESS_DOMAIN_TRI
:
4356 for (int i
= 0; i
< 3; i
++)
4357 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4358 hdr
[4] = ice
->state
.default_inner_level
[0];
4360 case BRW_TESS_DOMAIN_ISOLINE
:
4361 hdr
[7] = ice
->state
.default_outer_level
[1];
4362 hdr
[6] = ice
->state
.default_outer_level
[0];
4366 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
4367 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
4368 u_upload_data(ice
->ctx
.const_uploader
, 0, sizeof(hdr
), 32,
4369 &hdr
[0], &cbuf
->data
.offset
,
4373 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4374 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4377 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4378 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4383 if (shs
->cbuf0_needs_upload
)
4384 upload_uniforms(ice
, stage
);
4386 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4388 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4389 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4391 /* The Skylake PRM contains the following restriction:
4393 * "The driver must ensure The following case does not occur
4394 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4395 * buffer 3 read length equal to zero committed followed by a
4396 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4399 * To avoid this, we program the buffers in the highest slots.
4400 * This way, slot 0 is only used if slot 3 is also used.
4404 for (int i
= 3; i
>= 0; i
--) {
4405 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4407 if (range
->length
== 0)
4410 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4411 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
4413 assert(cbuf
->data
.offset
% 32 == 0);
4415 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4416 pkt
.ConstantBody
.Buffer
[n
] =
4417 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->data
.offset
)
4418 : ro_bo(batch
->screen
->workaround_bo
, 0);
4425 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4426 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4427 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4428 ptr
._3DCommandSubOpcode
= 38 + stage
;
4429 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4434 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4435 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4436 iris_populate_binding_table(ice
, batch
, stage
, false);
4440 if (ice
->state
.need_border_colors
)
4441 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4443 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4444 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4445 !ice
->shaders
.prog
[stage
])
4448 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4449 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4451 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4453 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4454 ptr
._3DCommandSubOpcode
= 43 + stage
;
4455 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4459 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4460 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4462 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4463 if (ice
->state
.framebuffer
.samples
> 0)
4464 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4468 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4469 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4470 ms
.SampleMask
= ice
->state
.sample_mask
;
4474 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4475 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4478 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4481 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4482 iris_use_pinned_bo(batch
, cache
->bo
, false);
4483 iris_batch_emit(batch
, shader
->derived_data
,
4484 iris_derived_program_state_size(stage
));
4486 if (stage
== MESA_SHADER_TESS_EVAL
) {
4487 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4488 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4489 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4490 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4491 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4496 if (ice
->state
.streamout_active
) {
4497 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4498 iris_batch_emit(batch
, genx
->so_buffers
,
4499 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4500 for (int i
= 0; i
< 4; i
++) {
4501 struct iris_stream_output_target
*tgt
=
4502 (void *) ice
->state
.so_target
[i
];
4504 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4506 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4512 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
4513 uint32_t *decl_list
=
4514 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
4515 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
4518 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4519 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4521 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
4522 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
4523 sol
.SOFunctionEnable
= true;
4524 sol
.SOStatisticsEnable
= true;
4526 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
4527 !ice
->state
.prims_generated_query_active
;
4528 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
4531 assert(ice
->state
.streamout
);
4533 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
4534 GENX(3DSTATE_STREAMOUT_length
));
4537 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4538 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
4542 if (dirty
& IRIS_DIRTY_CLIP
) {
4543 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4544 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4546 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
4547 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
4548 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4549 cl
.ClipMode
= cso_rast
->rasterizer_discard
? CLIPMODE_REJECT_ALL
4551 if (wm_prog_data
->barycentric_interp_modes
&
4552 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
4553 cl
.NonPerspectiveBarycentricEnable
= true;
4555 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
4556 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
4558 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
4559 ARRAY_SIZE(cso_rast
->clip
));
4562 if (dirty
& IRIS_DIRTY_RASTER
) {
4563 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4564 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
4565 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
4569 if (dirty
& IRIS_DIRTY_WM
) {
4570 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4571 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
4573 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
4574 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4576 wm
.BarycentricInterpolationMode
=
4577 wm_prog_data
->barycentric_interp_modes
;
4579 if (wm_prog_data
->early_fragment_tests
)
4580 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
4581 else if (wm_prog_data
->has_side_effects
)
4582 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
4584 /* We could skip this bit if color writes are enabled. */
4585 if (wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
)
4586 wm
.ForceThreadDispatchEnable
= ForceON
;
4588 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
4591 if (dirty
& IRIS_DIRTY_SBE
) {
4592 iris_emit_sbe(batch
, ice
);
4595 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
4596 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4597 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4598 const struct shader_info
*fs_info
=
4599 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
4601 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
4602 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
4603 pb
.HasWriteableRT
= has_writeable_rt(cso_blend
, fs_info
);
4604 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4607 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
4608 ARRAY_SIZE(cso_blend
->ps_blend
));
4611 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
4612 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4614 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4615 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
4616 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
4617 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4618 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4620 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
4622 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
4626 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
4627 uint32_t scissor_offset
=
4628 emit_state(batch
, ice
->state
.dynamic_uploader
,
4629 &ice
->state
.last_res
.scissor
,
4630 ice
->state
.scissors
,
4631 sizeof(struct pipe_scissor_state
) *
4632 ice
->state
.num_viewports
, 32);
4634 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
4635 ptr
.ScissorRectPointer
= scissor_offset
;
4639 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
4640 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4641 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
4643 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
4645 if (cso_fb
->zsbuf
) {
4646 struct iris_resource
*zres
, *sres
;
4647 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
4650 iris_use_pinned_bo(batch
, zres
->bo
,
4651 ice
->state
.depth_writes_enabled
);
4653 iris_use_pinned_bo(batch
, zres
->aux
.bo
,
4654 ice
->state
.depth_writes_enabled
);
4659 iris_use_pinned_bo(batch
, sres
->bo
,
4660 ice
->state
.stencil_writes_enabled
);
4665 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
4666 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
4667 for (int i
= 0; i
< 32; i
++) {
4668 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
4673 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
4674 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4675 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
4678 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
4679 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
4680 topo
.PrimitiveTopologyType
=
4681 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
4685 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4686 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
4687 int dynamic_bound
= ice
->state
.bound_vertex_buffers
;
4689 if (ice
->state
.vs_uses_draw_params
) {
4690 if (ice
->draw
.draw_params_offset
== 0) {
4691 u_upload_data(ice
->state
.dynamic_uploader
, 0, sizeof(ice
->draw
.params
),
4692 4, &ice
->draw
.params
, &ice
->draw
.draw_params_offset
,
4693 &ice
->draw
.draw_params_res
);
4695 assert(ice
->draw
.draw_params_res
);
4697 struct iris_vertex_buffer_state
*state
=
4698 &(ice
->state
.genx
->vertex_buffers
[count
]);
4699 pipe_resource_reference(&state
->resource
, ice
->draw
.draw_params_res
);
4700 struct iris_resource
*res
= (void *) state
->resource
;
4702 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
4703 vb
.VertexBufferIndex
= count
;
4704 vb
.AddressModifyEnable
= true;
4706 vb
.BufferSize
= res
->bo
->size
- ice
->draw
.draw_params_offset
;
4707 vb
.BufferStartingAddress
=
4708 ro_bo(NULL
, res
->bo
->gtt_offset
+
4709 (int) ice
->draw
.draw_params_offset
);
4710 vb
.MOCS
= mocs(res
->bo
);
4712 dynamic_bound
|= 1ull << count
;
4716 if (ice
->state
.vs_uses_derived_draw_params
) {
4717 u_upload_data(ice
->state
.dynamic_uploader
, 0,
4718 sizeof(ice
->draw
.derived_params
), 4,
4719 &ice
->draw
.derived_params
,
4720 &ice
->draw
.derived_draw_params_offset
,
4721 &ice
->draw
.derived_draw_params_res
);
4723 struct iris_vertex_buffer_state
*state
=
4724 &(ice
->state
.genx
->vertex_buffers
[count
]);
4725 pipe_resource_reference(&state
->resource
,
4726 ice
->draw
.derived_draw_params_res
);
4727 struct iris_resource
*res
= (void *) ice
->draw
.derived_draw_params_res
;
4729 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
4730 vb
.VertexBufferIndex
= count
;
4731 vb
.AddressModifyEnable
= true;
4734 res
->bo
->size
- ice
->draw
.derived_draw_params_offset
;
4735 vb
.BufferStartingAddress
=
4736 ro_bo(NULL
, res
->bo
->gtt_offset
+
4737 (int) ice
->draw
.derived_draw_params_offset
);
4738 vb
.MOCS
= mocs(res
->bo
);
4740 dynamic_bound
|= 1ull << count
;
4745 /* The VF cache designers cut corners, and made the cache key's
4746 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
4747 * 32 bits of the address. If you have two vertex buffers which get
4748 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
4749 * you can get collisions (even within a single batch).
4751 * So, we need to do a VF cache invalidate if the buffer for a VB
4752 * slot slot changes [48:32] address bits from the previous time.
4754 unsigned flush_flags
= 0;
4756 uint64_t bound
= dynamic_bound
;
4758 const int i
= u_bit_scan64(&bound
);
4759 uint16_t high_bits
= 0;
4761 struct iris_resource
*res
=
4762 (void *) genx
->vertex_buffers
[i
].resource
;
4764 iris_use_pinned_bo(batch
, res
->bo
, false);
4766 high_bits
= res
->bo
->gtt_offset
>> 32ull;
4767 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
4768 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
|
4769 PIPE_CONTROL_CS_STALL
;
4770 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
4773 /* If the buffer was written to by streamout, we may need
4774 * to stall so those writes land and become visible to the
4777 * TODO: This may stall more than necessary.
4779 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
4780 flush_flags
|= PIPE_CONTROL_CS_STALL
;
4785 iris_emit_pipe_control_flush(batch
, flush_flags
);
4787 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
4790 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
4791 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
4792 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
4796 bound
= dynamic_bound
;
4798 const int i
= u_bit_scan64(&bound
);
4799 memcpy(map
, genx
->vertex_buffers
[i
].state
,
4800 sizeof(uint32_t) * vb_dwords
);
4806 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
4807 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4808 const unsigned entries
= MAX2(cso
->count
, 1);
4809 if (!(ice
->state
.vs_needs_sgvs_element
||
4810 ice
->state
.vs_uses_derived_draw_params
||
4811 ice
->state
.vs_needs_edge_flag
)) {
4812 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
4813 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
4815 uint32_t dynamic_ves
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
4816 const unsigned dyn_count
= cso
->count
+
4817 ice
->state
.vs_needs_sgvs_element
+
4818 ice
->state
.vs_uses_derived_draw_params
;
4820 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
),
4823 1 + GENX(VERTEX_ELEMENT_STATE_length
) * dyn_count
- 2;
4825 memcpy(&dynamic_ves
[1], &cso
->vertex_elements
[1],
4826 (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
4827 GENX(VERTEX_ELEMENT_STATE_length
) * sizeof(uint32_t));
4828 uint32_t *ve_pack_dest
=
4829 &dynamic_ves
[1 + (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
4830 GENX(VERTEX_ELEMENT_STATE_length
)];
4832 if (ice
->state
.vs_needs_sgvs_element
) {
4833 uint32_t base_ctrl
= ice
->state
.vs_uses_draw_params
?
4834 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
4835 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
4837 ve
.VertexBufferIndex
=
4838 util_bitcount64(ice
->state
.bound_vertex_buffers
);
4839 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
4840 ve
.Component0Control
= base_ctrl
;
4841 ve
.Component1Control
= base_ctrl
;
4842 ve
.Component2Control
= VFCOMP_STORE_0
;
4843 ve
.Component3Control
= VFCOMP_STORE_0
;
4845 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
4847 if (ice
->state
.vs_uses_derived_draw_params
) {
4848 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
4850 ve
.VertexBufferIndex
=
4851 util_bitcount64(ice
->state
.bound_vertex_buffers
) +
4852 ice
->state
.vs_uses_draw_params
;
4853 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
4854 ve
.Component0Control
= VFCOMP_STORE_SRC
;
4855 ve
.Component1Control
= VFCOMP_STORE_SRC
;
4856 ve
.Component2Control
= VFCOMP_STORE_0
;
4857 ve
.Component3Control
= VFCOMP_STORE_0
;
4859 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
4861 if (ice
->state
.vs_needs_edge_flag
) {
4862 for (int i
= 0; i
< GENX(VERTEX_ELEMENT_STATE_length
); i
++)
4863 ve_pack_dest
[i
] = cso
->edgeflag_ve
[i
];
4866 iris_batch_emit(batch
, &dynamic_ves
, sizeof(uint32_t) *
4867 (1 + dyn_count
* GENX(VERTEX_ELEMENT_STATE_length
)));
4870 if (!ice
->state
.vs_needs_edge_flag
) {
4871 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
4872 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
4874 assert(cso
->count
> 0);
4875 const unsigned edgeflag_index
= cso
->count
- 1;
4876 uint32_t dynamic_vfi
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
4877 memcpy(&dynamic_vfi
[0], cso
->vf_instancing
, edgeflag_index
*
4878 GENX(3DSTATE_VF_INSTANCING_length
) * sizeof(uint32_t));
4880 uint32_t *vfi_pack_dest
= &dynamic_vfi
[0] +
4881 edgeflag_index
* GENX(3DSTATE_VF_INSTANCING_length
);
4882 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
4883 vi
.VertexElementIndex
= edgeflag_index
+
4884 ice
->state
.vs_needs_sgvs_element
+
4885 ice
->state
.vs_uses_derived_draw_params
;
4887 for (int i
= 0; i
< GENX(3DSTATE_VF_INSTANCING_length
); i
++)
4888 vfi_pack_dest
[i
] |= cso
->edgeflag_vfi
[i
];
4890 iris_batch_emit(batch
, &dynamic_vfi
[0], sizeof(uint32_t) *
4891 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
4895 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
4896 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
4897 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
4898 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4900 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
4901 if (vs_prog_data
->uses_vertexid
) {
4902 sgv
.VertexIDEnable
= true;
4903 sgv
.VertexIDComponentNumber
= 2;
4904 sgv
.VertexIDElementOffset
=
4905 cso
->count
- ice
->state
.vs_needs_edge_flag
;
4908 if (vs_prog_data
->uses_instanceid
) {
4909 sgv
.InstanceIDEnable
= true;
4910 sgv
.InstanceIDComponentNumber
= 3;
4911 sgv
.InstanceIDElementOffset
=
4912 cso
->count
- ice
->state
.vs_needs_edge_flag
;
4917 if (dirty
& IRIS_DIRTY_VF
) {
4918 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
4919 if (draw
->primitive_restart
) {
4920 vf
.IndexedDrawCutIndexEnable
= true;
4921 vf
.CutIndex
= draw
->restart_index
;
4926 /* TODO: Gen8 PMA fix */
4930 iris_upload_render_state(struct iris_context
*ice
,
4931 struct iris_batch
*batch
,
4932 const struct pipe_draw_info
*draw
)
4934 /* Always pin the binder. If we're emitting new binding table pointers,
4935 * we need it. If not, we're probably inheriting old tables via the
4936 * context, and need it anyway. Since true zero-bindings cases are
4937 * practically non-existent, just pin it and avoid last_res tracking.
4939 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
4941 if (!batch
->contains_draw
) {
4942 iris_restore_render_saved_bos(ice
, batch
, draw
);
4943 batch
->contains_draw
= true;
4946 iris_upload_dirty_render_state(ice
, batch
, draw
);
4948 if (draw
->index_size
> 0) {
4951 if (draw
->has_user_indices
) {
4952 u_upload_data(ice
->ctx
.stream_uploader
, 0,
4953 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
4954 &offset
, &ice
->state
.last_res
.index_buffer
);
4956 struct iris_resource
*res
= (void *) draw
->index
.resource
;
4957 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
4959 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
4960 draw
->index
.resource
);
4964 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4966 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
4967 ib
.IndexFormat
= draw
->index_size
>> 1;
4969 ib
.BufferSize
= bo
->size
;
4970 ib
.BufferStartingAddress
= ro_bo(bo
, offset
);
4973 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
4974 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
4975 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
4976 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_VF_CACHE_INVALIDATE
|
4977 PIPE_CONTROL_CS_STALL
);
4978 ice
->state
.last_index_bo_high_bits
= high_bits
;
4982 #define _3DPRIM_END_OFFSET 0x2420
4983 #define _3DPRIM_START_VERTEX 0x2430
4984 #define _3DPRIM_VERTEX_COUNT 0x2434
4985 #define _3DPRIM_INSTANCE_COUNT 0x2438
4986 #define _3DPRIM_START_INSTANCE 0x243C
4987 #define _3DPRIM_BASE_VERTEX 0x2440
4989 if (draw
->indirect
) {
4990 /* We don't support this MultidrawIndirect. */
4991 assert(!draw
->indirect
->indirect_draw_count
);
4993 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
4996 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4997 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
4998 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
5000 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5001 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
5002 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
5004 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5005 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
5006 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
5008 if (draw
->index_size
) {
5009 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5010 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
5011 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5013 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5014 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5015 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
5018 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5019 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5020 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5022 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
5023 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
5027 } else if (draw
->count_from_stream_output
) {
5028 struct iris_stream_output_target
*so
=
5029 (void *) draw
->count_from_stream_output
;
5031 /* XXX: Replace with actual cache tracking */
5032 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
5034 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5035 lrm
.RegisterAddress
= CS_GPR(0);
5037 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
5039 iris_math_div32_gpr0(ice
, batch
, so
->stride
);
5040 _iris_emit_lrr(batch
, _3DPRIM_VERTEX_COUNT
, CS_GPR(0));
5042 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
5043 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
5044 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
5045 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
5048 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
5049 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
5050 prim
.PredicateEnable
=
5051 ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
5053 if (draw
->indirect
|| draw
->count_from_stream_output
) {
5054 prim
.IndirectParameterEnable
= true;
5056 prim
.StartInstanceLocation
= draw
->start_instance
;
5057 prim
.InstanceCount
= draw
->instance_count
;
5058 prim
.VertexCountPerInstance
= draw
->count
;
5060 // XXX: this is probably bonkers.
5061 prim
.StartVertexLocation
= draw
->start
;
5063 if (draw
->index_size
) {
5064 prim
.BaseVertexLocation
+= draw
->index_bias
;
5066 prim
.StartVertexLocation
+= draw
->index_bias
;
5069 //prim.BaseVertexLocation = ...;
5075 iris_upload_compute_state(struct iris_context
*ice
,
5076 struct iris_batch
*batch
,
5077 const struct pipe_grid_info
*grid
)
5079 const uint64_t dirty
= ice
->state
.dirty
;
5080 struct iris_screen
*screen
= batch
->screen
;
5081 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
5082 struct iris_binder
*binder
= &ice
->state
.binder
;
5083 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
5084 struct iris_compiled_shader
*shader
=
5085 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
5086 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5087 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
5089 /* Always pin the binder. If we're emitting new binding table pointers,
5090 * we need it. If not, we're probably inheriting old tables via the
5091 * context, and need it anyway. Since true zero-bindings cases are
5092 * practically non-existent, just pin it and avoid last_res tracking.
5094 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5096 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->cbuf0_needs_upload
)
5097 upload_uniforms(ice
, MESA_SHADER_COMPUTE
);
5099 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
5100 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
5102 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
5103 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
5105 if (ice
->state
.need_border_colors
)
5106 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
5108 if (dirty
& IRIS_DIRTY_CS
) {
5109 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
5111 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
5112 * the only bits that are changed are scoreboard related: Scoreboard
5113 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
5114 * these scoreboard related states, a MEDIA_STATE_FLUSH is
5117 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
5119 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
5120 if (prog_data
->total_scratch
) {
5121 struct iris_bo
*bo
=
5122 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
5123 MESA_SHADER_COMPUTE
);
5124 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
5125 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
5128 vfe
.MaximumNumberofThreads
=
5129 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
5131 vfe
.ResetGatewayTimer
=
5132 Resettingrelativetimerandlatchingtheglobaltimestamp
;
5135 vfe
.BypassGatewayControl
= true;
5137 vfe
.NumberofURBEntries
= 2;
5138 vfe
.URBEntryAllocationSize
= 2;
5140 vfe
.CURBEAllocationSize
=
5141 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
5142 cs_prog_data
->push
.cross_thread
.regs
, 2);
5146 /* TODO: Combine subgroup-id with cbuf0 so we can push regular uniforms */
5147 uint32_t curbe_data_offset
= 0;
5148 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
5149 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
5150 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
5151 struct pipe_resource
*curbe_data_res
= NULL
;
5152 uint32_t *curbe_data_map
=
5153 stream_state(batch
, ice
->state
.dynamic_uploader
, &curbe_data_res
,
5154 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
5155 &curbe_data_offset
);
5156 assert(curbe_data_map
);
5157 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
5158 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
5160 if (dirty
& IRIS_DIRTY_CONSTANTS_CS
) {
5161 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
5162 curbe
.CURBETotalDataLength
=
5163 ALIGN(cs_prog_data
->push
.total
.size
, 64);
5164 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
5168 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
5169 IRIS_DIRTY_BINDINGS_CS
|
5170 IRIS_DIRTY_CONSTANTS_CS
|
5172 struct pipe_resource
*desc_res
= NULL
;
5173 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
5175 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
5176 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
5177 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
5180 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
5181 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
5183 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
5184 load
.InterfaceDescriptorTotalLength
=
5185 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
5186 load
.InterfaceDescriptorDataStartAddress
=
5187 emit_state(batch
, ice
->state
.dynamic_uploader
,
5188 &desc_res
, desc
, sizeof(desc
), 32);
5191 pipe_resource_reference(&desc_res
, NULL
);
5194 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
5195 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
5196 uint32_t right_mask
;
5199 right_mask
= ~0u >> (32 - remainder
);
5201 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
5203 #define GPGPU_DISPATCHDIMX 0x2500
5204 #define GPGPU_DISPATCHDIMY 0x2504
5205 #define GPGPU_DISPATCHDIMZ 0x2508
5207 if (grid
->indirect
) {
5208 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
5209 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
5210 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5211 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
5212 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
5214 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5215 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
5216 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
5218 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5219 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
5220 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
5224 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
5225 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
5226 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
5227 ggw
.ThreadDepthCounterMaximum
= 0;
5228 ggw
.ThreadHeightCounterMaximum
= 0;
5229 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
5230 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
5231 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
5232 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
5233 ggw
.RightExecutionMask
= right_mask
;
5234 ggw
.BottomExecutionMask
= 0xffffffff;
5237 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
5239 if (!batch
->contains_draw
) {
5240 iris_restore_compute_saved_bos(ice
, batch
, grid
);
5241 batch
->contains_draw
= true;
5246 * State module teardown.
5249 iris_destroy_state(struct iris_context
*ice
)
5251 struct iris_genx_state
*genx
= ice
->state
.genx
;
5253 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5255 const int i
= u_bit_scan64(&bound_vbs
);
5256 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
5258 free(ice
->state
.genx
);
5260 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
5261 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
5263 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
5265 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
5266 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5267 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
5268 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
5269 pipe_resource_reference(&shs
->constbuf
[i
].data
.res
, NULL
);
5270 pipe_resource_reference(&shs
->constbuf
[i
].surface_state
.res
, NULL
);
5272 for (int i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
5273 pipe_resource_reference(&shs
->image
[i
].res
, NULL
);
5274 pipe_resource_reference(&shs
->image
[i
].surface_state
.res
, NULL
);
5276 for (int i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
5277 pipe_resource_reference(&shs
->ssbo
[i
], NULL
);
5278 pipe_resource_reference(&shs
->ssbo_surface_state
[i
].res
, NULL
);
5280 for (int i
= 0; i
< IRIS_MAX_TEXTURE_SAMPLERS
; i
++) {
5281 pipe_sampler_view_reference((struct pipe_sampler_view
**)
5282 &shs
->textures
[i
], NULL
);
5286 pipe_resource_reference(&ice
->state
.grid_size
.res
, NULL
);
5287 pipe_resource_reference(&ice
->state
.grid_surf_state
.res
, NULL
);
5289 pipe_resource_reference(&ice
->state
.null_fb
.res
, NULL
);
5290 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
5292 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
5293 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
5294 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
5295 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
5296 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
5297 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
5300 /* ------------------------------------------------------------------- */
5303 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
5306 _iris_emit_lrr(batch
, dst
, src
);
5310 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
5313 _iris_emit_lrr(batch
, dst
, src
);
5314 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
5318 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
5321 _iris_emit_lri(batch
, reg
, val
);
5325 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
5328 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
5329 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
5333 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
5336 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5337 struct iris_bo
*bo
, uint32_t offset
)
5339 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5340 lrm
.RegisterAddress
= reg
;
5341 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
5346 * Load a 64-bit value from a buffer into a MMIO register via
5347 * two MI_LOAD_REGISTER_MEM commands.
5350 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5351 struct iris_bo
*bo
, uint32_t offset
)
5353 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
5354 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
5358 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5359 struct iris_bo
*bo
, uint32_t offset
,
5362 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
5363 srm
.RegisterAddress
= reg
;
5364 srm
.MemoryAddress
= rw_bo(bo
, offset
);
5365 srm
.PredicateEnable
= predicated
;
5370 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5371 struct iris_bo
*bo
, uint32_t offset
,
5374 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
5375 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
5379 iris_store_data_imm32(struct iris_batch
*batch
,
5380 struct iris_bo
*bo
, uint32_t offset
,
5383 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
5384 sdi
.Address
= rw_bo(bo
, offset
);
5385 sdi
.ImmediateData
= imm
;
5390 iris_store_data_imm64(struct iris_batch
*batch
,
5391 struct iris_bo
*bo
, uint32_t offset
,
5394 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
5395 * 2 in genxml but it's actually variable length and we need 5 DWords.
5397 void *map
= iris_get_command_space(batch
, 4 * 5);
5398 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
5399 sdi
.DWordLength
= 5 - 2;
5400 sdi
.Address
= rw_bo(bo
, offset
);
5401 sdi
.ImmediateData
= imm
;
5406 iris_copy_mem_mem(struct iris_batch
*batch
,
5407 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
5408 struct iris_bo
*src_bo
, uint32_t src_offset
,
5411 /* MI_COPY_MEM_MEM operates on DWords. */
5412 assert(bytes
% 4 == 0);
5413 assert(dst_offset
% 4 == 0);
5414 assert(src_offset
% 4 == 0);
5416 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
5417 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
5418 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
5419 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
5424 /* ------------------------------------------------------------------- */
5427 flags_to_post_sync_op(uint32_t flags
)
5429 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
5430 return WriteImmediateData
;
5432 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
5433 return WritePSDepthCount
;
5435 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
5436 return WriteTimestamp
;
5442 * Do the given flags have a Post Sync or LRI Post Sync operation?
5444 static enum pipe_control_flags
5445 get_post_sync_flags(enum pipe_control_flags flags
)
5447 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
5448 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5449 PIPE_CONTROL_WRITE_TIMESTAMP
|
5450 PIPE_CONTROL_LRI_POST_SYNC_OP
;
5452 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
5453 * "LRI Post Sync Operation". So more than one bit set would be illegal.
5455 assert(util_bitcount(flags
) <= 1);
5460 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
5463 * Emit a series of PIPE_CONTROL commands, taking into account any
5464 * workarounds necessary to actually accomplish the caller's request.
5466 * Unless otherwise noted, spec quotations in this function come from:
5468 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
5469 * Restrictions for PIPE_CONTROL.
5471 * You should not use this function directly. Use the helpers in
5472 * iris_pipe_control.c instead, which may split the pipe control further.
5475 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
5476 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
5478 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
5479 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
5480 enum pipe_control_flags non_lri_post_sync_flags
=
5481 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
5483 /* Recursive PIPE_CONTROL workarounds --------------------------------
5484 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
5486 * We do these first because we want to look at the original operation,
5487 * rather than any workarounds we set.
5489 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
5490 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
5491 * lists several workarounds:
5493 * "Project: SKL, KBL, BXT
5495 * If the VF Cache Invalidation Enable is set to a 1 in a
5496 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
5497 * sets to 0, with the VF Cache Invalidation Enable set to 0
5498 * needs to be sent prior to the PIPE_CONTROL with VF Cache
5499 * Invalidation Enable set to a 1."
5501 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
5504 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
5505 /* Project: SKL / Argument: LRI Post Sync Operation [23]
5507 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5508 * programmed prior to programming a PIPECONTROL command with "LRI
5509 * Post Sync Operation" in GPGPU mode of operation (i.e when
5510 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
5512 * The same text exists a few rows below for Post Sync Op.
5514 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
5517 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
5519 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
5520 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
5521 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
5523 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
5527 /* "Flush Types" workarounds ---------------------------------------------
5528 * We do these now because they may add post-sync operations or CS stalls.
5531 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
5532 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
5534 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
5535 * 'Write PS Depth Count' or 'Write Timestamp'."
5538 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5539 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5540 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5541 bo
= batch
->screen
->workaround_bo
;
5545 /* #1130 from Gen10 workarounds page:
5547 * "Enable Depth Stall on every Post Sync Op if Render target Cache
5548 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
5549 * board stall if Render target cache flush is enabled."
5551 * Applicable to CNL B0 and C0 steppings only.
5553 * The wording here is unclear, and this workaround doesn't look anything
5554 * like the internal bug report recommendations, but leave it be for now...
5556 if (GEN_GEN
== 10) {
5557 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
5558 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5559 } else if (flags
& non_lri_post_sync_flags
) {
5560 flags
|= PIPE_CONTROL_DEPTH_STALL
;
5564 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
5565 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
5567 * "This bit must be DISABLED for operations other than writing
5570 * This seems like nonsense. An Ivybridge workaround requires us to
5571 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
5572 * operation. Gen8+ requires us to emit depth stalls and depth cache
5573 * flushes together. So, it's hard to imagine this means anything other
5574 * than "we originally intended this to be used for PS_DEPTH_COUNT".
5576 * We ignore the supposed restriction and do nothing.
5580 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5581 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5582 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
5584 * "This bit must be DISABLED for End-of-pipe (Read) fences,
5585 * PS_DEPTH_COUNT or TIMESTAMP queries."
5587 * TODO: Implement end-of-pipe checking.
5589 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5590 PIPE_CONTROL_WRITE_TIMESTAMP
)));
5593 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5594 /* From the PIPE_CONTROL instruction table, bit 1:
5596 * "This bit is ignored if Depth Stall Enable is set.
5597 * Further, the render cache is not flushed even if Write Cache
5598 * Flush Enable bit is set."
5600 * We assert that the caller doesn't do this combination, to try and
5601 * prevent mistakes. It shouldn't hurt the GPU, though.
5603 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
5604 * and "Render Target Flush" combo is explicitly required for BTI
5605 * update workarounds.
5607 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
5608 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
5611 /* PIPE_CONTROL page workarounds ------------------------------------- */
5613 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
5614 /* From the PIPE_CONTROL page itself:
5617 * Restriction: Pipe_control with CS-stall bit set must be issued
5618 * before a pipe-control command that has the State Cache
5619 * Invalidate bit set."
5621 flags
|= PIPE_CONTROL_CS_STALL
;
5624 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
5625 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
5628 * SW must always program Post-Sync Operation to "Write Immediate
5629 * Data" when Flush LLC is set."
5631 * For now, we just require the caller to do it.
5633 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
5636 /* "Post-Sync Operation" workarounds -------------------------------- */
5638 /* Project: All / Argument: Global Snapshot Count Reset [19]
5640 * "This bit must not be exercised on any product.
5641 * Requires stall bit ([20] of DW1) set."
5643 * We don't use this, so we just assert that it isn't used. The
5644 * PIPE_CONTROL instruction page indicates that they intended this
5645 * as a debug feature and don't think it is useful in production,
5646 * but it may actually be usable, should we ever want to.
5648 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
5650 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
5651 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
5652 /* Project: All / Arguments:
5654 * - Generic Media State Clear [16]
5655 * - Indirect State Pointers Disable [16]
5657 * "Requires stall bit ([20] of DW1) set."
5659 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
5660 * State Clear) says:
5662 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5663 * programmed prior to programming a PIPECONTROL command with "Media
5664 * State Clear" set in GPGPU mode of operation"
5666 * This is a subset of the earlier rule, so there's nothing to do.
5668 flags
|= PIPE_CONTROL_CS_STALL
;
5671 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
5672 /* Project: All / Argument: Store Data Index
5674 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5677 * For now, we just assert that the caller does this. We might want to
5678 * automatically add a write to the workaround BO...
5680 assert(non_lri_post_sync_flags
!= 0);
5683 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
5684 /* Project: All / Argument: Sync GFDT
5686 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5687 * than '0' or 0x2520[13] must be set."
5689 * For now, we just assert that the caller does this.
5691 assert(non_lri_post_sync_flags
!= 0);
5694 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
5695 /* Project: IVB+ / Argument: TLB inv
5697 * "Requires stall bit ([20] of DW1) set."
5699 * Also, from the PIPE_CONTROL instruction table:
5702 * Post Sync Operation or CS stall must be set to ensure a TLB
5703 * invalidation occurs. Otherwise no cycle will occur to the TLB
5704 * cache to invalidate."
5706 * This is not a subset of the earlier rule, so there's nothing to do.
5708 flags
|= PIPE_CONTROL_CS_STALL
;
5711 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
5712 /* TODO: The big Skylake GT4 post sync op workaround */
5715 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
5717 if (IS_COMPUTE_PIPELINE(batch
)) {
5718 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
5719 /* Project: SKL+ / Argument: Tex Invalidate
5720 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
5722 flags
|= PIPE_CONTROL_CS_STALL
;
5725 if (GEN_GEN
== 8 && (post_sync_flags
||
5726 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
5727 PIPE_CONTROL_DEPTH_STALL
|
5728 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5729 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5730 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
5731 /* Project: BDW / Arguments:
5733 * - LRI Post Sync Operation [23]
5734 * - Post Sync Op [15:14]
5736 * - Depth Stall [13]
5737 * - Render Target Cache Flush [12]
5738 * - Depth Cache Flush [0]
5739 * - DC Flush Enable [5]
5741 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
5744 flags
|= PIPE_CONTROL_CS_STALL
;
5746 /* Also, from the PIPE_CONTROL instruction table, bit 20:
5749 * This bit must be always set when PIPE_CONTROL command is
5750 * programmed by GPGPU and MEDIA workloads, except for the cases
5751 * when only Read Only Cache Invalidation bits are set (State
5752 * Cache Invalidation Enable, Instruction cache Invalidation
5753 * Enable, Texture Cache Invalidation Enable, Constant Cache
5754 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
5755 * need not implemented when FF_DOP_CG is disable via "Fixed
5756 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
5758 * It sounds like we could avoid CS stalls in some cases, but we
5759 * don't currently bother. This list isn't exactly the list above,
5765 /* "Stall" workarounds ----------------------------------------------
5766 * These have to come after the earlier ones because we may have added
5767 * some additional CS stalls above.
5770 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
5771 /* Project: PRE-SKL, VLV, CHV
5773 * "[All Stepping][All SKUs]:
5775 * One of the following must also be set:
5777 * - Render Target Cache Flush Enable ([12] of DW1)
5778 * - Depth Cache Flush Enable ([0] of DW1)
5779 * - Stall at Pixel Scoreboard ([1] of DW1)
5780 * - Depth Stall ([13] of DW1)
5781 * - Post-Sync Operation ([13] of DW1)
5782 * - DC Flush Enable ([5] of DW1)"
5784 * If we don't already have one of those bits set, we choose to add
5785 * "Stall at Pixel Scoreboard". Some of the other bits require a
5786 * CS stall as a workaround (see above), which would send us into
5787 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
5788 * appears to be safe, so we choose that.
5790 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5791 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5792 PIPE_CONTROL_WRITE_IMMEDIATE
|
5793 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5794 PIPE_CONTROL_WRITE_TIMESTAMP
|
5795 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
5796 PIPE_CONTROL_DEPTH_STALL
|
5797 PIPE_CONTROL_DATA_CACHE_FLUSH
;
5798 if (!(flags
& wa_bits
))
5799 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5802 /* Emit --------------------------------------------------------------- */
5804 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
5805 pc
.LRIPostSyncOperation
= NoLRIOperation
;
5806 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
5807 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
5808 pc
.StoreDataIndex
= 0;
5809 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
5810 pc
.GlobalSnapshotCountReset
=
5811 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
5812 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
5813 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
5814 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5815 pc
.RenderTargetCacheFlushEnable
=
5816 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
5817 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
5818 pc
.StateCacheInvalidationEnable
=
5819 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
5820 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
5821 pc
.ConstantCacheInvalidationEnable
=
5822 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
5823 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
5824 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
5825 pc
.InstructionCacheInvalidateEnable
=
5826 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
5827 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
5828 pc
.IndirectStatePointersDisable
=
5829 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
5830 pc
.TextureCacheInvalidationEnable
=
5831 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
5832 pc
.Address
= rw_bo(bo
, offset
);
5833 pc
.ImmediateData
= imm
;
5838 genX(init_state
)(struct iris_context
*ice
)
5840 struct pipe_context
*ctx
= &ice
->ctx
;
5841 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
5843 ctx
->create_blend_state
= iris_create_blend_state
;
5844 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
5845 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
5846 ctx
->create_sampler_state
= iris_create_sampler_state
;
5847 ctx
->create_sampler_view
= iris_create_sampler_view
;
5848 ctx
->create_surface
= iris_create_surface
;
5849 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
5850 ctx
->bind_blend_state
= iris_bind_blend_state
;
5851 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
5852 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
5853 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
5854 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
5855 ctx
->delete_blend_state
= iris_delete_state
;
5856 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
5857 ctx
->delete_rasterizer_state
= iris_delete_state
;
5858 ctx
->delete_sampler_state
= iris_delete_state
;
5859 ctx
->delete_vertex_elements_state
= iris_delete_state
;
5860 ctx
->set_blend_color
= iris_set_blend_color
;
5861 ctx
->set_clip_state
= iris_set_clip_state
;
5862 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
5863 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
5864 ctx
->set_shader_images
= iris_set_shader_images
;
5865 ctx
->set_sampler_views
= iris_set_sampler_views
;
5866 ctx
->set_tess_state
= iris_set_tess_state
;
5867 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
5868 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
5869 ctx
->set_sample_mask
= iris_set_sample_mask
;
5870 ctx
->set_scissor_states
= iris_set_scissor_states
;
5871 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
5872 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
5873 ctx
->set_viewport_states
= iris_set_viewport_states
;
5874 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
5875 ctx
->surface_destroy
= iris_surface_destroy
;
5876 ctx
->draw_vbo
= iris_draw_vbo
;
5877 ctx
->launch_grid
= iris_launch_grid
;
5878 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
5879 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
5880 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
5882 ice
->vtbl
.destroy_state
= iris_destroy_state
;
5883 ice
->vtbl
.init_render_context
= iris_init_render_context
;
5884 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
5885 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
5886 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
5887 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
5888 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
5889 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
5890 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
5891 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
5892 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
5893 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
5894 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
5895 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
5896 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
5897 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
5898 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
5899 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
5900 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
5901 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
5902 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
5903 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
5904 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
5905 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
5906 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
5907 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
5908 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
5909 ice
->vtbl
.mocs
= mocs
;
5911 ice
->state
.dirty
= ~0ull;
5913 ice
->state
.statistics_counters_enabled
= true;
5915 ice
->state
.sample_mask
= 0xffff;
5916 ice
->state
.num_viewports
= 1;
5917 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
5919 /* Make a 1x1x1 null surface for unbound textures */
5920 void *null_surf_map
=
5921 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
5922 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
5923 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
5924 ice
->state
.unbound_tex
.offset
+=
5925 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
5927 /* Default all scissor rectangles to be empty regions. */
5928 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
5929 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
5930 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,