2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "intel/common/gen_sample_positions.h"
43 #include "iris_batch.h"
44 #include "iris_context.h"
45 #include "iris_pipe.h"
46 #include "iris_resource.h"
48 #define __gen_address_type struct iris_address
49 #define __gen_user_data struct iris_batch
52 __gen_combine_address(struct iris_batch
*batch
, void *location
,
53 struct iris_address addr
, uint32_t delta
)
56 return addr
.offset
+ delta
;
58 return iris_batch_reloc(batch
, location
- batch
->cmdbuf
.map
, addr
.bo
,
59 addr
.offset
+ delta
, addr
.reloc_flags
);
62 #define __genxml_cmd_length(cmd) cmd ## _length
63 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
64 #define __genxml_cmd_header(cmd) cmd ## _header
65 #define __genxml_cmd_pack(cmd) cmd ## _pack
67 #define iris_pack_command(cmd, dst, name) \
68 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
69 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
70 ({ __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name); \
71 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __genxml_cmd_length(cmd) * 4)); \
75 #define iris_pack_state(cmd, dst, name) \
76 for (struct cmd name = {}, \
77 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
78 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
81 #define iris_emit_cmd(batch, cmd, name) \
82 iris_require_command_space(batch, 4 * __genxml_cmd_length(cmd)); \
83 iris_pack_command(cmd, batch->cmdbuf.map_next, name)
85 #define iris_emit_merge(batch, dwords0, dwords1) \
87 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
89 iris_require_command_space(batch, ARRAY_SIZE(dwords0)); \
90 uint32_t *dw = batch->cmdbuf.map_next; \
91 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
92 dw[i] = (dwords0)[i] | (dwords1)[i]; \
93 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4)); \
96 #include "genxml/genX_pack.h"
97 #include "genxml/gen_macros.h"
99 #define MOCS_WB (2 << 1)
101 UNUSED
static void pipe_asserts()
103 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
105 /* pipe_logicop happens to match the hardware. */
106 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
107 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
108 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
109 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
110 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
111 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
112 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
113 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
114 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
115 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
116 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
117 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
118 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
119 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
120 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
121 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
123 /* pipe_blend_func happens to match the hardware. */
124 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
125 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
126 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
127 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
128 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
129 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
130 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
131 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
132 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
133 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
134 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
135 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
136 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
137 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
138 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
139 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
140 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
141 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
142 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
144 /* pipe_blend_func happens to match the hardware. */
145 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
146 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
147 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
148 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
149 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
151 /* pipe_stencil_op happens to match the hardware. */
152 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
153 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
154 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
155 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
156 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
157 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
158 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
159 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
164 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
166 static const unsigned map
[] = {
167 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
168 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
169 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
170 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
171 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
172 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
173 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
174 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
175 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
176 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
177 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
178 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
179 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
180 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
181 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
184 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
188 translate_compare_func(enum pipe_compare_func pipe_func
)
190 static const unsigned map
[] = {
191 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
192 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
193 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
194 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
195 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
196 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
197 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
198 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
200 return map
[pipe_func
];
204 translate_shadow_func(enum pipe_compare_func pipe_func
)
206 /* Gallium specifies the result of shadow comparisons as:
208 * 1 if ref <op> texel,
213 * 0 if texel <op> ref,
216 * So we need to flip the operator and also negate.
218 static const unsigned map
[] = {
219 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
220 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
221 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
222 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
223 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
224 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
225 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
226 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
228 return map
[pipe_func
];
232 translate_cull_mode(unsigned pipe_face
)
234 static const unsigned map
[4] = {
235 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
236 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
237 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
238 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
240 return map
[pipe_face
];
244 translate_fill_mode(unsigned pipe_polymode
)
246 static const unsigned map
[4] = {
247 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
248 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
249 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
250 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
252 return map
[pipe_polymode
];
255 static struct iris_address
256 ro_bo(struct iris_bo
*bo
, uint32_t offset
)
258 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
262 iris_upload_initial_gpu_state(struct iris_context
*ice
,
263 struct iris_batch
*batch
)
265 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
266 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
267 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
269 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
270 GEN_SAMPLE_POS_1X(pat
._1xSample
);
271 GEN_SAMPLE_POS_2X(pat
._2xSample
);
272 GEN_SAMPLE_POS_4X(pat
._4xSample
);
273 GEN_SAMPLE_POS_8X(pat
._8xSample
);
274 GEN_SAMPLE_POS_16X(pat
._16xSample
);
276 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
277 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
278 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
279 /* XXX: may need to set an offset for origin-UL framebuffers */
280 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
282 /* Just assign a static partitioning. */
283 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
284 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
285 alloc
._3DCommandSubOpcode
= 18 + i
;
286 alloc
.ConstantBufferOffset
= 6 * i
;
287 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
293 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
298 iris_set_blend_color(struct pipe_context
*ctx
,
299 const struct pipe_blend_color
*state
)
301 struct iris_context
*ice
= (struct iris_context
*) ctx
;
303 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
304 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
307 struct iris_blend_state
{
308 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
309 uint32_t blend_state
[GENX(BLEND_STATE_length
)];
310 uint32_t blend_entries
[BRW_MAX_DRAW_BUFFERS
*
311 GENX(BLEND_STATE_ENTRY_length
)];
315 iris_create_blend_state(struct pipe_context
*ctx
,
316 const struct pipe_blend_state
*state
)
318 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
320 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
321 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
322 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
323 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
324 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
325 bs
.ColorDitherEnable
= state
->dither
;
326 //bs.AlphaTestEnable = <comes from alpha state> :(
327 //bs.AlphaTestFunction = <comes from alpha state> :(
330 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
331 //pb.HasWriteableRT = <comes from somewhere> :(
332 //pb.AlphaTestEnable = <comes from alpha state> :(
333 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
334 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
336 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
338 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
339 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
340 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
341 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
344 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
345 iris_pack_state(GENX(BLEND_STATE_ENTRY
), &cso
->blend_entries
[i
], be
) {
346 be
.LogicOpEnable
= state
->logicop_enable
;
347 be
.LogicOpFunction
= state
->logicop_func
;
349 be
.PreBlendSourceOnlyClampEnable
= false;
350 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
351 be
.PreBlendColorClampEnable
= true;
352 be
.PostBlendColorClampEnable
= true;
354 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
356 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
357 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
358 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
359 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
360 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
361 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
363 be
.WriteDisableRed
= state
->rt
[i
].colormask
& PIPE_MASK_R
;
364 be
.WriteDisableGreen
= state
->rt
[i
].colormask
& PIPE_MASK_G
;
365 be
.WriteDisableBlue
= state
->rt
[i
].colormask
& PIPE_MASK_B
;
366 be
.WriteDisableAlpha
= state
->rt
[i
].colormask
& PIPE_MASK_A
;
374 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
376 struct iris_context
*ice
= (struct iris_context
*) ctx
;
377 ice
->state
.cso_blend
= state
;
378 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
379 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
382 struct iris_depth_stencil_alpha_state
{
383 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
384 uint32_t cc_vp
[GENX(CC_VIEWPORT_length
)];
386 struct pipe_alpha_state alpha
; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
390 iris_create_zsa_state(struct pipe_context
*ctx
,
391 const struct pipe_depth_stencil_alpha_state
*state
)
393 struct iris_depth_stencil_alpha_state
*cso
=
394 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
396 cso
->alpha
= state
->alpha
;
398 bool two_sided_stencil
= state
->stencil
[1].enabled
;
400 /* The state tracker needs to optimize away EQUAL writes for us. */
401 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
403 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
404 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
405 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
406 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
407 wmds
.StencilTestFunction
=
408 translate_compare_func(state
->stencil
[0].func
);
409 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
410 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
411 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
412 wmds
.BackfaceStencilTestFunction
=
413 translate_compare_func(state
->stencil
[1].func
);
414 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
415 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
416 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
417 wmds
.StencilBufferWriteEnable
=
418 state
->stencil
[0].writemask
!= 0 ||
419 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
420 wmds
.DepthTestEnable
= state
->depth
.enabled
;
421 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
422 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
423 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
424 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
425 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
426 /* wmds.[Backface]StencilReferenceValue are merged later */
429 iris_pack_state(GENX(CC_VIEWPORT
), cso
->cc_vp
, ccvp
) {
430 ccvp
.MinimumDepth
= state
->depth
.bounds_min
;
431 ccvp
.MaximumDepth
= state
->depth
.bounds_max
;
438 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
440 struct iris_context
*ice
= (struct iris_context
*) ctx
;
441 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
442 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
445 if (!old_cso
|| old_cso
->alpha
.ref_value
!= new_cso
->alpha
.ref_value
) {
446 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
450 ice
->state
.cso_zsa
= new_cso
;
451 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
452 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
455 struct iris_rasterizer_state
{
456 uint32_t sf
[GENX(3DSTATE_SF_length
)];
457 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
458 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
459 uint32_t wm
[GENX(3DSTATE_WM_length
)];
460 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
462 bool flatshade
; /* for shader state */
463 bool light_twoside
; /* for shader state */
464 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
465 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
466 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
470 iris_create_rasterizer_state(struct pipe_context
*ctx
,
471 const struct pipe_rasterizer_state
*state
)
473 struct iris_rasterizer_state
*cso
=
474 malloc(sizeof(struct iris_rasterizer_state
));
477 sprite_coord_mode
-> SBE PointSpriteTextureCoordinateOrigin
478 sprite_coord_enable
-> SBE PointSpriteTextureCoordinateEnable
479 point_quad_rasterization
-> SBE
?
484 force_persample_interp
- ?
487 offset_units_unscaled
- cap
not exposed
491 cso
->flatshade
= state
->flatshade
;
492 cso
->light_twoside
= state
->light_twoside
;
493 cso
->rasterizer_discard
= state
->rasterizer_discard
;
494 cso
->half_pixel_center
= state
->half_pixel_center
;
496 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
497 sf
.StatisticsEnable
= true;
498 sf
.ViewportTransformEnable
= true;
499 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
500 sf
.LineEndCapAntialiasingRegionWidth
=
501 state
->line_smooth
? _10pixels
: _05pixels
;
502 sf
.LastPixelEnable
= state
->line_last_pixel
;
503 sf
.LineWidth
= state
->line_width
;
504 sf
.SmoothPointEnable
= state
->point_smooth
;
505 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
506 sf
.PointWidth
= state
->point_size
;
508 if (state
->flatshade_first
) {
509 sf
.TriangleStripListProvokingVertexSelect
= 2;
510 sf
.TriangleFanProvokingVertexSelect
= 2;
511 sf
.LineStripListProvokingVertexSelect
= 1;
513 sf
.TriangleFanProvokingVertexSelect
= 1;
518 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
519 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
520 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
521 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
522 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
523 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
524 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
525 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
526 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
527 rr
.GlobalDepthOffsetConstant
= state
->offset_units
;
528 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
529 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
530 rr
.SmoothPointEnable
= state
->point_smooth
;
531 rr
.AntialiasingEnable
= state
->line_smooth
;
532 rr
.ScissorRectangleEnable
= state
->scissor
;
533 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
534 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
535 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
538 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
539 cl
.StatisticsEnable
= true;
540 cl
.EarlyCullEnable
= true;
541 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
542 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
543 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
544 cl
.GuardbandClipTestEnable
= true;
545 cl
.ClipMode
= CLIPMODE_NORMAL
;
546 cl
.ClipEnable
= true;
547 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
548 cl
.MinimumPointWidth
= 0.125;
549 cl
.MaximumPointWidth
= 255.875;
550 //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
551 //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
553 if (state
->flatshade_first
) {
554 cl
.TriangleStripListProvokingVertexSelect
= 2;
555 cl
.TriangleFanProvokingVertexSelect
= 2;
556 cl
.LineStripListProvokingVertexSelect
= 1;
558 cl
.TriangleFanProvokingVertexSelect
= 1;
562 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
563 wm
.LineAntialiasingRegionWidth
= _10pixels
;
564 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
565 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
566 wm
.StatisticsEnable
= true;
567 wm
.LineStippleEnable
= state
->line_stipple_enable
;
568 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
569 // wm.BarycentricInterpolationMode = <comes from FS program> :(
570 // wm.EarlyDepthStencilControl = <comes from FS program> :(
573 /* Remap from 0..255 back to 1..256 */
574 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
576 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
577 line
.LineStipplePattern
= state
->line_stipple_pattern
;
578 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
579 line
.LineStippleRepeatCount
= line_stipple_factor
;
586 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
588 struct iris_context
*ice
= (struct iris_context
*) ctx
;
589 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
590 struct iris_rasterizer_state
*new_cso
= state
;
593 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
594 if (!old_cso
|| memcmp(old_cso
->line_stipple
, new_cso
->line_stipple
,
595 sizeof(old_cso
->line_stipple
)) != 0) {
596 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
600 old_cso
->half_pixel_center
!= new_cso
->half_pixel_center
) {
601 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
605 ice
->state
.cso_rast
= new_cso
;
606 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
610 translate_wrap(unsigned pipe_wrap
)
612 static const unsigned map
[] = {
613 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
614 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
615 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
616 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
617 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
618 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
619 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1, // XXX: ???
620 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1, // XXX: ???
622 return map
[pipe_wrap
];
626 * Return true if the given wrap mode requires the border color to exist.
629 wrap_mode_needs_border_color(unsigned wrap_mode
)
631 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
635 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
637 static const unsigned map
[] = {
638 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
639 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
640 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
642 return map
[pipe_mip
];
645 struct iris_sampler_state
{
646 struct pipe_sampler_state base
;
648 bool needs_border_color
;
650 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
654 iris_create_sampler_state(struct pipe_context
*pctx
,
655 const struct pipe_sampler_state
*state
)
657 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
662 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
663 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
665 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
666 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
667 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
669 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
670 wrap_mode_needs_border_color(wrap_t
) ||
671 wrap_mode_needs_border_color(wrap_r
);
673 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
674 samp
.TCXAddressControlMode
= wrap_s
;
675 samp
.TCYAddressControlMode
= wrap_t
;
676 samp
.TCZAddressControlMode
= wrap_r
;
677 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
678 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
679 samp
.MinModeFilter
= state
->min_img_filter
;
680 samp
.MagModeFilter
= state
->mag_img_filter
;
681 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
682 samp
.MaximumAnisotropy
= RATIO21
;
684 if (state
->max_anisotropy
>= 2) {
685 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
686 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
687 samp
.AnisotropicAlgorithm
= EWAApproximation
;
690 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
691 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
693 samp
.MaximumAnisotropy
=
694 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
697 /* Set address rounding bits if not using nearest filtering. */
698 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
699 samp
.UAddressMinFilterRoundingEnable
= true;
700 samp
.VAddressMinFilterRoundingEnable
= true;
701 samp
.RAddressMinFilterRoundingEnable
= true;
704 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
705 samp
.UAddressMagFilterRoundingEnable
= true;
706 samp
.VAddressMagFilterRoundingEnable
= true;
707 samp
.RAddressMagFilterRoundingEnable
= true;
710 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
711 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
713 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
715 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
716 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
717 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
718 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
720 //samp.BorderColorPointer = <<comes from elsewhere>>
727 iris_bind_sampler_states(struct pipe_context
*ctx
,
728 enum pipe_shader_type p_stage
,
729 unsigned start
, unsigned count
,
732 struct iris_context
*ice
= (struct iris_context
*) ctx
;
733 gl_shader_stage stage
= stage_from_pipe(p_stage
);
735 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
737 for (int i
= 0; i
< count
; i
++) {
738 ice
->state
.samplers
[stage
][start
+ i
] = states
[i
];
741 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
744 struct iris_sampler_view
{
745 struct pipe_sampler_view pipe
;
746 struct isl_view view
;
747 uint32_t surface_state
[GENX(RENDER_SURFACE_STATE_length
)];
751 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
752 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
754 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
757 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
759 * which is simply adding 4 then modding by 8 (or anding with 7).
761 * We then may need to apply workarounds for textureGather hardware bugs.
763 static enum isl_channel_select
764 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
766 return (swizzle
+ 4) & 7;
769 static struct pipe_sampler_view
*
770 iris_create_sampler_view(struct pipe_context
*ctx
,
771 struct pipe_resource
*tex
,
772 const struct pipe_sampler_view
*tmpl
)
774 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
775 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
776 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
781 /* initialize base object */
783 isv
->pipe
.context
= ctx
;
784 isv
->pipe
.texture
= NULL
;
785 pipe_reference_init(&isv
->pipe
.reference
, 1);
786 pipe_resource_reference(&isv
->pipe
.texture
, tex
);
788 /* XXX: do we need brw_get_texture_swizzle hacks here? */
790 isv
->view
= (struct isl_view
) {
791 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
792 .base_level
= tmpl
->u
.tex
.first_level
,
793 .levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1,
794 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
795 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
796 .swizzle
= (struct isl_swizzle
) {
797 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
798 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
799 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
800 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
802 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
805 isl_surf_fill_state(&screen
->isl_dev
, isv
->surface_state
,
806 .surf
= &itex
->surf
, .view
= &isv
->view
,
810 // .clear_color = clear_color,
815 struct iris_surface
{
816 struct pipe_surface pipe
;
817 struct isl_view view
;
818 uint32_t surface_state
[GENX(RENDER_SURFACE_STATE_length
)];
821 static struct pipe_surface
*
822 iris_create_surface(struct pipe_context
*ctx
,
823 struct pipe_resource
*tex
,
824 const struct pipe_surface
*tmpl
)
826 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
827 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
828 struct pipe_surface
*psurf
= &surf
->pipe
;
829 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
834 pipe_reference_init(&psurf
->reference
, 1);
835 pipe_resource_reference(&psurf
->texture
, tex
);
836 psurf
->context
= ctx
;
837 psurf
->format
= tmpl
->format
;
838 psurf
->width
= tex
->width0
;
839 psurf
->height
= tex
->height0
;
840 psurf
->texture
= tex
;
841 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
842 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
843 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
845 surf
->view
= (struct isl_view
) {
846 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
847 .base_level
= tmpl
->u
.tex
.level
,
849 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
850 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
851 .swizzle
= ISL_SWIZZLE_IDENTITY
,
852 // XXX: DEPTH_BIt, STENCIL_BIT...CUBE_BIT? Other bits?!
853 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
856 isl_surf_fill_state(&screen
->isl_dev
, surf
->surface_state
,
857 .surf
= &itex
->surf
, .view
= &surf
->view
,
861 // .clear_color = clear_color,
867 iris_set_sampler_views(struct pipe_context
*ctx
,
868 enum pipe_shader_type shader
,
869 unsigned start
, unsigned count
,
870 struct pipe_sampler_view
**views
)
875 iris_set_clip_state(struct pipe_context
*ctx
,
876 const struct pipe_clip_state
*state
)
881 iris_set_polygon_stipple(struct pipe_context
*ctx
,
882 const struct pipe_poly_stipple
*state
)
884 struct iris_context
*ice
= (struct iris_context
*) ctx
;
885 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
886 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
890 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
892 struct iris_context
*ice
= (struct iris_context
*) ctx
;
894 ice
->state
.sample_mask
= sample_mask
;
895 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
899 iris_set_scissor_states(struct pipe_context
*ctx
,
901 unsigned num_scissors
,
902 const struct pipe_scissor_state
*state
)
904 struct iris_context
*ice
= (struct iris_context
*) ctx
;
907 ice
->state
.num_scissors
= num_scissors
;
909 for (unsigned i
= start_slot
; i
< start_slot
+ num_scissors
; i
++) {
910 ice
->state
.scissors
[i
] = *state
;
913 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
917 iris_set_stencil_ref(struct pipe_context
*ctx
,
918 const struct pipe_stencil_ref
*state
)
920 struct iris_context
*ice
= (struct iris_context
*) ctx
;
921 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
922 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
926 struct iris_viewport_state
{
927 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
)];
931 extent_from_matrix(const struct pipe_viewport_state
*state
, int axis
)
933 return fabsf(state
->scale
[axis
]) * state
->translate
[axis
];
938 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
939 float m00
, float m11
, float m30
, float m31
,
940 float *xmin
, float *xmax
,
941 float *ymin
, float *ymax
)
943 /* According to the "Vertex X,Y Clamping and Quantization" section of the
944 * Strips and Fans documentation:
946 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
947 * fixed-point "guardband" range supported by the rasterization hardware"
951 * "In almost all circumstances, if an object’s vertices are actually
952 * modified by this clamping (i.e., had X or Y coordinates outside of
953 * the guardband extent the rendered object will not match the intended
954 * result. Therefore software should take steps to ensure that this does
955 * not happen - e.g., by clipping objects such that they do not exceed
956 * these limits after the Drawing Rectangle is applied."
958 * I believe the fundamental restriction is that the rasterizer (in
959 * the SF/WM stages) have a limit on the number of pixels that can be
960 * rasterized. We need to ensure any coordinates beyond the rasterizer
961 * limit are handled by the clipper. So effectively that limit becomes
962 * the clipper's guardband size.
966 * "In addition, in order to be correctly rendered, objects must have a
967 * screenspace bounding box not exceeding 8K in the X or Y direction.
968 * This additional restriction must also be comprehended by software,
969 * i.e., enforced by use of clipping."
971 * This makes no sense. Gen7+ hardware supports 16K render targets,
972 * and you definitely need to be able to draw polygons that fill the
973 * surface. Our assumption is that the rasterizer was limited to 8K
974 * on Sandybridge, which only supports 8K surfaces, and it was actually
975 * increased to 16K on Ivybridge and later.
977 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
979 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
981 if (m00
!= 0 && m11
!= 0) {
982 /* First, we compute the screen-space render area */
983 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
984 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
985 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
986 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
988 /* We want the guardband to be centered on that */
989 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
990 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
991 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
992 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
994 /* Now we need it in native device coordinates */
995 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
996 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
997 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
998 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1000 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1001 * flipped upside-down. X should be fine though.
1003 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1004 *xmin
= ndc_gb_xmin
;
1005 *xmax
= ndc_gb_xmax
;
1006 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1007 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1009 /* The viewport scales to 0, so nothing will be rendered. */
1019 iris_set_viewport_states(struct pipe_context
*ctx
,
1020 unsigned start_slot
,
1021 unsigned num_viewports
,
1022 const struct pipe_viewport_state
*state
)
1024 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1025 struct iris_viewport_state
*cso
=
1026 malloc(sizeof(struct iris_viewport_state
));
1028 for (unsigned i
= start_slot
; i
< start_slot
+ num_viewports
; i
++) {
1029 float x_extent
= extent_from_matrix(&state
[i
], 0);
1030 float y_extent
= extent_from_matrix(&state
[i
], 1);
1032 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), cso
->sf_cl_vp
, vp
) {
1033 vp
.ViewportMatrixElementm00
= state
[i
].scale
[0];
1034 vp
.ViewportMatrixElementm11
= state
[i
].scale
[1];
1035 vp
.ViewportMatrixElementm22
= state
[i
].scale
[2];
1036 vp
.ViewportMatrixElementm30
= state
[i
].translate
[0];
1037 vp
.ViewportMatrixElementm31
= state
[i
].translate
[1];
1038 vp
.ViewportMatrixElementm32
= state
[i
].translate
[2];
1039 /* XXX: in i965 this is computed based on the drawbuffer size,
1040 * but we don't have that here...
1042 vp
.XMinClipGuardband
= -1.0;
1043 vp
.XMaxClipGuardband
= 1.0;
1044 vp
.YMinClipGuardband
= -1.0;
1045 vp
.YMaxClipGuardband
= 1.0;
1046 vp
.XMinViewPort
= -x_extent
;
1047 vp
.XMaxViewPort
= x_extent
;
1048 vp
.YMinViewPort
= -y_extent
;
1049 vp
.YMaxViewPort
= y_extent
;
1053 ice
->state
.cso_vp
= cso
;
1055 ice
->state
.num_viewports
= num_viewports
;
1056 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1059 struct iris_depth_state
1061 uint32_t depth_buffer
[GENX(3DSTATE_DEPTH_BUFFER_length
)];
1062 uint32_t hier_depth_buffer
[GENX(3DSTATE_HIER_DEPTH_BUFFER_length
)];
1063 uint32_t stencil_buffer
[GENX(3DSTATE_STENCIL_BUFFER_length
)];
1067 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1068 const struct pipe_framebuffer_state
*state
)
1070 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1071 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1073 if (cso
->samples
!= state
->samples
) {
1074 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1077 cso
->width
= state
->width
;
1078 cso
->height
= state
->height
;
1079 cso
->layers
= state
->layers
;
1080 cso
->samples
= state
->samples
;
1083 for (i
= 0; i
< state
->nr_cbufs
; i
++)
1084 pipe_surface_reference(&cso
->cbufs
[i
], state
->cbufs
[i
]);
1085 for (; i
< cso
->nr_cbufs
; i
++)
1086 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
1088 cso
->nr_cbufs
= state
->nr_cbufs
;
1090 pipe_surface_reference(&cso
->zsbuf
, state
->zsbuf
);
1092 struct isl_depth_stencil_hiz_emit_info info
= {
1096 // XXX: depth buffers
1100 iris_set_constant_buffer(struct pipe_context
*ctx
,
1101 enum pipe_shader_type shader
, uint index
,
1102 const struct pipe_constant_buffer
*cb
)
1108 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1109 struct pipe_sampler_view
*state
)
1111 pipe_resource_reference(&state
->texture
, NULL
);
1117 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*surface
)
1119 pipe_resource_reference(&surface
->texture
, NULL
);
1124 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1129 struct iris_vertex_buffer_state
{
1130 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
1131 unsigned length
; /* length of 3DSTATE_VERTEX_BUFFERS in DWords */
1135 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1136 unsigned start_slot
, unsigned count
,
1137 const struct pipe_vertex_buffer
*buffers
)
1139 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1140 struct iris_vertex_buffer_state
*cso
=
1141 malloc(sizeof(struct iris_vertex_buffer_state
));
1143 cso
->length
= 4 * count
- 1;
1145 iris_pack_state(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1146 vb
.DWordLength
= cso
->length
;
1149 /* If there are no buffers, do nothing. We can leave the stale
1150 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1151 * elements that point to them, it should be fine.
1156 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1158 for (unsigned i
= 0; i
< count
; i
++) {
1159 assert(!buffers
[i
].is_user_buffer
);
1161 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1162 vb
.VertexBufferIndex
= start_slot
+ i
;
1164 vb
.AddressModifyEnable
= true;
1165 vb
.BufferPitch
= buffers
[i
].stride
;
1166 //vb.BufferStartingAddress = ro_bo(bo, buffers[i].buffer_offset);
1167 //vb.BufferSize = bo->size;
1170 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1173 ice
->state
.cso_vertex_buffers
= cso
;
1174 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1177 struct iris_vertex_element_state
{
1178 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1179 uint32_t vf_instancing
[GENX(3DSTATE_VF_INSTANCING_length
)][33];
1184 iris_create_vertex_elements(struct pipe_context
*ctx
,
1186 const struct pipe_vertex_element
*state
)
1188 struct iris_vertex_element_state
*cso
=
1189 malloc(sizeof(struct iris_vertex_element_state
));
1194 * - create edge flag one
1196 * - if those are necessary, use count + 1/2/3... OR in the length
1198 iris_pack_state(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
);
1200 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1202 for (int i
= 0; i
< count
; i
++) {
1203 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1204 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1206 ve
.SourceElementOffset
= state
[i
].src_offset
;
1207 ve
.SourceElementFormat
=
1208 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1211 iris_pack_state(GENX(3DSTATE_VF_INSTANCING
), cso
->vf_instancing
[i
], vi
) {
1212 vi
.VertexElementIndex
= i
;
1213 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1214 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1217 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1224 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
1226 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1228 ice
->state
.cso_vertex_elements
= state
;
1229 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
1233 iris_create_compute_state(struct pipe_context
*ctx
,
1234 const struct pipe_compute_state
*state
)
1239 static struct pipe_stream_output_target
*
1240 iris_create_stream_output_target(struct pipe_context
*ctx
,
1241 struct pipe_resource
*res
,
1242 unsigned buffer_offset
,
1243 unsigned buffer_size
)
1245 struct pipe_stream_output_target
*t
=
1246 CALLOC_STRUCT(pipe_stream_output_target
);
1250 pipe_reference_init(&t
->reference
, 1);
1251 pipe_resource_reference(&t
->buffer
, res
);
1252 t
->buffer_offset
= buffer_offset
;
1253 t
->buffer_size
= buffer_size
;
1258 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
1259 struct pipe_stream_output_target
*t
)
1261 pipe_resource_reference(&t
->buffer
, NULL
);
1266 iris_set_stream_output_targets(struct pipe_context
*ctx
,
1267 unsigned num_targets
,
1268 struct pipe_stream_output_target
**targets
,
1269 const unsigned *offsets
)
1274 iris_setup_state_base_address(struct iris_context
*ice
,
1275 struct iris_batch
*batch
,
1276 struct iris_bo
*instruction_bo
)
1278 if (!(ice
->state
.dirty
& IRIS_DIRTY_STATE_BASE_ADDRESS
))
1281 //iris_batchbuffer_flush(...)
1283 ice
->state
.dirty
&= ~IRIS_DIRTY_STATE_BASE_ADDRESS
;
1285 /* XXX: PIPE_CONTROLs */
1287 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
1289 // XXX: MOCS is stupid for this.
1290 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
1291 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
1292 sba
.SurfaceStateMemoryObjectControlState
= MOCS_WB
;
1293 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
1294 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
1295 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
1296 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
1299 sba
.GeneralStateBaseAddressModifyEnable
= true;
1300 sba
.SurfaceStateBaseAddressModifyEnable
= true;
1301 sba
.DynamicStateBaseAddressModifyEnable
= true;
1302 sba
.IndirectObjectBaseAddressModifyEnable
= true;
1303 sba
.InstructionBaseAddressModifyEnable
= true;
1304 sba
.GeneralStateBufferSizeModifyEnable
= true;
1305 sba
.DynamicStateBufferSizeModifyEnable
= true;
1306 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
1307 sba
.IndirectObjectBufferSizeModifyEnable
= true;
1308 sba
.InstructionBuffersizeModifyEnable
= true;
1310 sba
.SurfaceStateBaseAddress
= ro_bo(batch
->statebuf
.bo
, 0);
1311 sba
.DynamicStateBaseAddress
= ro_bo(batch
->statebuf
.bo
, 0);
1312 sba
.InstructionBaseAddress
= ro_bo(instruction_bo
, 0);
1314 sba
.GeneralStateBufferSize
= 0xfffff000;
1315 sba
.DynamicStateBufferSize
= ALIGN(MAX_STATE_SIZE
, 4096);
1316 sba
.IndirectObjectBufferSize
= 0xfffff000;
1317 sba
.InstructionBufferSize
= ALIGN(ice
->shaders
.cache
.bo
->size
, 4096);
1318 sba
.BindlessSurfaceStateSize
= 0;
1323 iris_upload_render_state(struct iris_context
*ice
,
1324 struct iris_batch
*batch
,
1325 const struct pipe_draw_info
*draw
)
1327 const uint64_t dirty
= ice
->state
.dirty
;
1329 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
1330 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1331 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
1333 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1334 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
1335 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
1336 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
1338 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
);
1341 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
1342 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1343 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
1344 ptr
.CCViewportPointer
=
1345 iris_emit_state(batch
, cso
->cc_vp
, sizeof(cso
->cc_vp
), 32);
1349 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
1350 struct iris_blend_state
*cso
= ice
->state
.cso_blend
;
1351 iris_batch_emit(batch
, cso
->ps_blend
, sizeof(cso
->ps_blend
));
1354 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
1355 //struct iris_blend_state *cso = ice->state.cso_blend;
1356 // XXX: 3DSTATE_BLEND_STATE_POINTERS - BLEND_STATE
1357 // -> from iris_blend_state (most) + iris_depth_stencil_alpha_state
1358 // (alpha test function/enable) + has writeable RT from ???????
1361 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
1362 struct iris_viewport_state
*cso
= ice
->state
.cso_vp
;
1363 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
1364 ptr
.SFClipViewportPointer
=
1365 iris_emit_state(batch
, cso
->sf_cl_vp
, sizeof(cso
->sf_cl_vp
), 64);
1369 if (dirty
& IRIS_DIRTY_CLIP
) {
1370 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
1372 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
1373 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
1374 //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
1375 //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
1376 // also userclip stuffs...
1378 iris_emit_merge(batch
, cso
->clip
, dynamic_clip
);
1381 if (dirty
& IRIS_DIRTY_RASTER
) {
1382 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
1383 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
1384 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
1387 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
1388 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
1389 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
1392 if (dirty
& IRIS_DIRTY_SCISSOR
) {
1393 uint32_t scissor_offset
=
1394 iris_emit_state(batch
, ice
->state
.scissors
,
1395 sizeof(struct pipe_scissor_state
) *
1396 ice
->state
.num_scissors
, 32);
1398 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
1399 ptr
.ScissorRectPointer
= scissor_offset
;
1403 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
1404 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
1405 for (int i
= 0; i
< 32; i
++) {
1406 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
1411 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
1412 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1415 iris_alloc_state(batch
,
1416 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
1418 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
1419 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
1420 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
1421 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
1422 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
1423 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
1424 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
1426 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1427 ptr
.ColorCalcStatePointer
= cc_offset
;
1428 ptr
.ColorCalcStatePointerValid
= true;
1432 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
1433 struct iris_vertex_buffer_state
*cso
= ice
->state
.cso_vertex_buffers
;
1435 iris_batch_emit(batch
, cso
->vertex_buffers
,
1436 sizeof(uint32_t) * cso
->length
);
1439 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
1440 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
1441 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
1442 (1 + cso
->count
* GENX(VERTEX_ELEMENT_STATE_length
)));
1443 for (int i
= 0; i
< cso
->count
; i
++) {
1444 iris_batch_emit(batch
, cso
->vf_instancing
[i
],
1445 sizeof(cso
->vf_instancing
[0]));
1447 for (int i
= 0; i
< cso
->count
; i
++) {
1448 /* TODO: vertexid, instanceid support */
1449 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
);
1453 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
1454 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1456 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
1457 if (ice
->state
.framebuffer
.samples
> 0)
1458 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
1462 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
1463 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
1464 ms
.SampleMask
= ice
->state
.sample_mask
;
1468 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
1469 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)))
1472 // XXX: get sampler count from shader; don't emit them all...
1473 const int count
= IRIS_MAX_TEXTURE_SAMPLERS
;
1476 uint32_t *map
= iris_alloc_state(batch
,
1477 count
* 4 * GENX(SAMPLER_STATE_length
),
1480 for (int i
= 0; i
< count
; i
++) {
1481 memcpy(map
, ice
->state
.samplers
[stage
][i
]->sampler_state
,
1482 4 * GENX(SAMPLER_STATE_length
));
1483 map
+= GENX(SAMPLER_STATE_length
);
1486 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
1487 ptr
._3DCommandSubOpcode
= 43 + stage
;
1488 ptr
.PointertoVSSamplerState
= offset
;
1493 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
1494 topo
.PrimitiveTopologyType
=
1495 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
1500 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
1501 if (draw
->primitive_restart
) {
1502 vf
.IndexedDrawCutIndexEnable
= true;
1503 vf
.CutIndex
= draw
->restart_index
;
1508 // draw->index_size > 0
1509 if (draw
->index_size
> 0) {
1510 struct iris_resource
*res
= (struct iris_resource
*)draw
->index
.resource
;
1512 assert(!draw
->has_user_indices
);
1514 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
1515 ib
.IndexFormat
= draw
->index_size
;
1517 ib
.BufferSize
= res
->bo
->size
;
1518 // XXX: gah, addresses :( need two different combine address funcs
1519 // ib.BufferStartingAddress = res->bo;
1523 assert(!draw
->indirect
); // XXX: indirect support
1525 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
1526 prim
.StartInstanceLocation
= draw
->start_instance
;
1527 prim
.InstanceCount
= draw
->instance_count
;
1529 // XXX: this is probably bonkers.
1530 prim
.StartVertexLocation
= draw
->start
;
1532 if (draw
->index_size
) {
1533 prim
.BaseVertexLocation
+= draw
->index_bias
;
1535 prim
.StartVertexLocation
+= draw
->index_bias
;
1538 //prim.BaseVertexLocation = ...;
1546 3DSTATE_CONSTANT_
* - push constants
1554 - render targets
- write
and read
1555 3DSTATE_BINDING_TABLE_POINTERS_
*
1567 3DSTATE_SO_DECL_LIST
1570 -> iris_raster_state
+ FS
state (barycentric
, EDSC
)
1572 -> iris_raster_state (point sprite texture coordinate origin
)
1573 -> bunch of shader state
...
1577 3DSTATE_DEPTH_BUFFER
1578 3DSTATE_HIER_DEPTH_BUFFER
1579 3DSTATE_STENCIL_BUFFER
1580 3DSTATE_CLEAR_PARAMS
1581 -> iris_framebuffer_state
?
1586 iris_bind_state(struct pipe_context
*ctx
, void *state
)
1591 iris_destroy_state(struct iris_context
*ice
)
1593 // XXX: unreference resources/surfaces.
1594 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
1595 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
1597 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
1601 iris_init_state_functions(struct pipe_context
*ctx
)
1603 ctx
->create_blend_state
= iris_create_blend_state
;
1604 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
1605 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
1606 ctx
->create_sampler_state
= iris_create_sampler_state
;
1607 ctx
->create_sampler_view
= iris_create_sampler_view
;
1608 ctx
->create_surface
= iris_create_surface
;
1609 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
1610 ctx
->create_compute_state
= iris_create_compute_state
;
1611 ctx
->bind_blend_state
= iris_bind_blend_state
;
1612 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
1613 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
1614 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
1615 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
1616 ctx
->bind_compute_state
= iris_bind_state
;
1617 ctx
->delete_blend_state
= iris_delete_state
;
1618 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
1619 ctx
->delete_fs_state
= iris_delete_state
;
1620 ctx
->delete_rasterizer_state
= iris_delete_state
;
1621 ctx
->delete_sampler_state
= iris_delete_state
;
1622 ctx
->delete_vertex_elements_state
= iris_delete_state
;
1623 ctx
->delete_compute_state
= iris_delete_state
;
1624 ctx
->delete_tcs_state
= iris_delete_state
;
1625 ctx
->delete_tes_state
= iris_delete_state
;
1626 ctx
->delete_gs_state
= iris_delete_state
;
1627 ctx
->delete_vs_state
= iris_delete_state
;
1628 ctx
->set_blend_color
= iris_set_blend_color
;
1629 ctx
->set_clip_state
= iris_set_clip_state
;
1630 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
1631 ctx
->set_sampler_views
= iris_set_sampler_views
;
1632 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
1633 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
1634 ctx
->set_sample_mask
= iris_set_sample_mask
;
1635 ctx
->set_scissor_states
= iris_set_scissor_states
;
1636 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
1637 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
1638 ctx
->set_viewport_states
= iris_set_viewport_states
;
1639 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
1640 ctx
->surface_destroy
= iris_surface_destroy
;
1641 ctx
->draw_vbo
= iris_draw_vbo
;
1642 ctx
->launch_grid
= iris_launch_grid
;
1643 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
1644 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
1645 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;