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15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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20 * DEALINGS IN THE SOFTWARE.
26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_dual_blend.h"
92 #include "util/u_inlines.h"
93 #include "util/u_format.h"
94 #include "util/u_framebuffer.h"
95 #include "util/u_transfer.h"
96 #include "util/u_upload_mgr.h"
97 #include "util/u_viewport.h"
98 #include "drm-uapi/i915_drm.h"
100 #include "intel/compiler/brw_compiler.h"
101 #include "intel/common/gen_aux_map.h"
102 #include "intel/common/gen_l3_config.h"
103 #include "intel/common/gen_sample_positions.h"
104 #include "iris_batch.h"
105 #include "iris_context.h"
106 #include "iris_defines.h"
107 #include "iris_pipe.h"
108 #include "iris_resource.h"
110 #include "iris_genx_macros.h"
111 #include "intel/common/gen_guardband.h"
114 #define MOCS_PTE 0x18
117 #define MOCS_PTE (1 << 1)
118 #define MOCS_WB (2 << 1)
122 mocs(const struct iris_bo
*bo
)
124 return bo
&& bo
->external
? MOCS_PTE
: MOCS_WB
;
128 * Statically assert that PIPE_* enums match the hardware packets.
129 * (As long as they match, we don't need to translate them.)
131 UNUSED
static void pipe_asserts()
133 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
135 /* pipe_logicop happens to match the hardware. */
136 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
137 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
138 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
139 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
140 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
141 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
142 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
143 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
144 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
145 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
146 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
147 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
148 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
149 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
150 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
151 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
153 /* pipe_blend_func happens to match the hardware. */
154 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
160 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
161 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
162 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
163 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
164 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
165 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
166 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
167 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
168 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
169 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
170 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
171 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
172 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
174 /* pipe_blend_func happens to match the hardware. */
175 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
176 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
177 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
178 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
179 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
181 /* pipe_stencil_op happens to match the hardware. */
182 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
183 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
184 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
185 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
186 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
187 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
188 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
189 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
191 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
192 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
193 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
198 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
200 static const unsigned map
[] = {
201 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
202 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
203 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
204 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
205 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
206 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
207 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
208 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
209 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
210 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
211 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
212 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
213 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
214 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
215 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
218 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
222 translate_compare_func(enum pipe_compare_func pipe_func
)
224 static const unsigned map
[] = {
225 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
226 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
227 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
228 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
229 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
230 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
231 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
232 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
234 return map
[pipe_func
];
238 translate_shadow_func(enum pipe_compare_func pipe_func
)
240 /* Gallium specifies the result of shadow comparisons as:
242 * 1 if ref <op> texel,
247 * 0 if texel <op> ref,
250 * So we need to flip the operator and also negate.
252 static const unsigned map
[] = {
253 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
254 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
255 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
256 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
257 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
258 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
259 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
260 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
262 return map
[pipe_func
];
266 translate_cull_mode(unsigned pipe_face
)
268 static const unsigned map
[4] = {
269 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
270 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
271 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
272 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
274 return map
[pipe_face
];
278 translate_fill_mode(unsigned pipe_polymode
)
280 static const unsigned map
[4] = {
281 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
282 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
283 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
284 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
286 return map
[pipe_polymode
];
290 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
292 static const unsigned map
[] = {
293 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
294 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
295 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
297 return map
[pipe_mip
];
301 translate_wrap(unsigned pipe_wrap
)
303 static const unsigned map
[] = {
304 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
305 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
306 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
307 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
308 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
309 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
311 /* These are unsupported. */
312 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
313 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
315 return map
[pipe_wrap
];
319 * Allocate space for some indirect state.
321 * Return a pointer to the map (to fill it out) and a state ref (for
322 * referring to the state in GPU commands).
325 upload_state(struct u_upload_mgr
*uploader
,
326 struct iris_state_ref
*ref
,
331 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
336 * Stream out temporary/short-lived state.
338 * This allocates space, pins the BO, and includes the BO address in the
339 * returned offset (which works because all state lives in 32-bit memory
343 stream_state(struct iris_batch
*batch
,
344 struct u_upload_mgr
*uploader
,
345 struct pipe_resource
**out_res
,
348 uint32_t *out_offset
)
352 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
354 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
355 iris_use_pinned_bo(batch
, bo
, false);
357 *out_offset
+= iris_bo_offset_from_base_address(bo
);
359 iris_record_state_size(batch
->state_sizes
, *out_offset
, size
);
365 * stream_state() + memcpy.
368 emit_state(struct iris_batch
*batch
,
369 struct u_upload_mgr
*uploader
,
370 struct pipe_resource
**out_res
,
377 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
380 memcpy(map
, data
, size
);
386 * Did field 'x' change between 'old_cso' and 'new_cso'?
388 * (If so, we may want to set some dirty flags.)
390 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
391 #define cso_changed_memcmp(x) \
392 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
395 flush_before_state_base_change(struct iris_batch
*batch
)
397 /* Flush before emitting STATE_BASE_ADDRESS.
399 * This isn't documented anywhere in the PRM. However, it seems to be
400 * necessary prior to changing the surface state base adress. We've
401 * seen issues in Vulkan where we get GPU hangs when using multi-level
402 * command buffers which clear depth, reset state base address, and then
405 * Normally, in GL, we would trust the kernel to do sufficient stalls
406 * and flushes prior to executing our batch. However, it doesn't seem
407 * as if the kernel's flushing is always sufficient and we don't want to
410 * We make this an end-of-pipe sync instead of a normal flush because we
411 * do not know the current status of the GPU. On Haswell at least,
412 * having a fast-clear operation in flight at the same time as a normal
413 * rendering operation can cause hangs. Since the kernel's flushing is
414 * insufficient, we need to ensure that any rendering operations from
415 * other processes are definitely complete before we try to do our own
416 * rendering. It's a bit of a big hammer but it appears to work.
418 iris_emit_end_of_pipe_sync(batch
,
419 "change STATE_BASE_ADDRESS (flushes)",
420 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
421 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
422 PIPE_CONTROL_DATA_CACHE_FLUSH
);
426 flush_after_state_base_change(struct iris_batch
*batch
)
428 /* After re-setting the surface state base address, we have to do some
429 * cache flusing so that the sampler engine will pick up the new
430 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
431 * Shared Function > 3D Sampler > State > State Caching (page 96):
433 * Coherency with system memory in the state cache, like the texture
434 * cache is handled partially by software. It is expected that the
435 * command stream or shader will issue Cache Flush operation or
436 * Cache_Flush sampler message to ensure that the L1 cache remains
437 * coherent with system memory.
441 * Whenever the value of the Dynamic_State_Base_Addr,
442 * Surface_State_Base_Addr are altered, the L1 state cache must be
443 * invalidated to ensure the new surface or sampler state is fetched
444 * from system memory.
446 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
447 * which, according the PIPE_CONTROL instruction documentation in the
450 * Setting this bit is independent of any other bit in this packet.
451 * This bit controls the invalidation of the L1 and L2 state caches
452 * at the top of the pipe i.e. at the parsing time.
454 * Unfortunately, experimentation seems to indicate that state cache
455 * invalidation through a PIPE_CONTROL does nothing whatsoever in
456 * regards to surface state and binding tables. In stead, it seems that
457 * invalidating the texture cache is what is actually needed.
459 * XXX: As far as we have been able to determine through
460 * experimentation, shows that flush the texture cache appears to be
461 * sufficient. The theory here is that all of the sampling/rendering
462 * units cache the binding table in the texture cache. However, we have
463 * yet to be able to actually confirm this.
465 iris_emit_end_of_pipe_sync(batch
,
466 "change STATE_BASE_ADDRESS (invalidates)",
467 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
468 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
469 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
473 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
475 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
476 lri
.RegisterOffset
= reg
;
480 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
483 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
485 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
486 lrr
.SourceRegisterAddress
= src
;
487 lrr
.DestinationRegisterAddress
= dst
;
492 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
495 _iris_emit_lrr(batch
, dst
, src
);
499 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
502 _iris_emit_lrr(batch
, dst
, src
);
503 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
507 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
510 _iris_emit_lri(batch
, reg
, val
);
514 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
517 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
518 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
522 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
525 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
526 struct iris_bo
*bo
, uint32_t offset
)
528 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
529 lrm
.RegisterAddress
= reg
;
530 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
535 * Load a 64-bit value from a buffer into a MMIO register via
536 * two MI_LOAD_REGISTER_MEM commands.
539 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
540 struct iris_bo
*bo
, uint32_t offset
)
542 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
543 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
547 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
548 struct iris_bo
*bo
, uint32_t offset
,
551 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
552 srm
.RegisterAddress
= reg
;
553 srm
.MemoryAddress
= rw_bo(bo
, offset
);
554 srm
.PredicateEnable
= predicated
;
559 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
560 struct iris_bo
*bo
, uint32_t offset
,
563 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
564 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
568 iris_store_data_imm32(struct iris_batch
*batch
,
569 struct iris_bo
*bo
, uint32_t offset
,
572 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
573 sdi
.Address
= rw_bo(bo
, offset
);
574 sdi
.ImmediateData
= imm
;
579 iris_store_data_imm64(struct iris_batch
*batch
,
580 struct iris_bo
*bo
, uint32_t offset
,
583 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
584 * 2 in genxml but it's actually variable length and we need 5 DWords.
586 void *map
= iris_get_command_space(batch
, 4 * 5);
587 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
588 sdi
.DWordLength
= 5 - 2;
589 sdi
.Address
= rw_bo(bo
, offset
);
590 sdi
.ImmediateData
= imm
;
595 iris_copy_mem_mem(struct iris_batch
*batch
,
596 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
597 struct iris_bo
*src_bo
, uint32_t src_offset
,
600 /* MI_COPY_MEM_MEM operates on DWords. */
601 assert(bytes
% 4 == 0);
602 assert(dst_offset
% 4 == 0);
603 assert(src_offset
% 4 == 0);
605 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
606 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
607 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
608 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
614 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
616 #if GEN_GEN >= 8 && GEN_GEN < 10
617 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
619 * Software must clear the COLOR_CALC_STATE Valid field in
620 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
621 * with Pipeline Select set to GPGPU.
623 * The internal hardware docs recommend the same workaround for Gen9
626 if (pipeline
== GPGPU
)
627 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
631 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
632 * PIPELINE_SELECT [DevBWR+]":
636 * Software must ensure all the write caches are flushed through a
637 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
638 * command to invalidate read only caches prior to programming
639 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
641 iris_emit_pipe_control_flush(batch
,
642 "workaround: PIPELINE_SELECT flushes (1/2)",
643 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
644 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
645 PIPE_CONTROL_DATA_CACHE_FLUSH
|
646 PIPE_CONTROL_CS_STALL
);
648 iris_emit_pipe_control_flush(batch
,
649 "workaround: PIPELINE_SELECT flushes (2/2)",
650 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
651 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
652 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
653 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
655 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
659 sel
.PipelineSelection
= pipeline
;
664 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
669 * "This chicken bit works around a hardware issue with barrier
670 * logic encountered when switching between GPGPU and 3D pipelines.
671 * To workaround the issue, this mode bit should be set after a
672 * pipeline is selected."
675 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
676 reg
.GLKBarrierMode
= value
;
677 reg
.GLKBarrierModeMask
= 1;
679 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
684 init_state_base_address(struct iris_batch
*batch
)
686 flush_before_state_base_change(batch
);
688 /* We program most base addresses once at context initialization time.
689 * Each base address points at a 4GB memory zone, and never needs to
690 * change. See iris_bufmgr.h for a description of the memory zones.
692 * The one exception is Surface State Base Address, which needs to be
693 * updated occasionally. See iris_binder.c for the details there.
695 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
696 sba
.GeneralStateMOCS
= MOCS_WB
;
697 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
698 sba
.DynamicStateMOCS
= MOCS_WB
;
699 sba
.IndirectObjectMOCS
= MOCS_WB
;
700 sba
.InstructionMOCS
= MOCS_WB
;
701 sba
.SurfaceStateMOCS
= MOCS_WB
;
703 sba
.GeneralStateBaseAddressModifyEnable
= true;
704 sba
.DynamicStateBaseAddressModifyEnable
= true;
705 sba
.IndirectObjectBaseAddressModifyEnable
= true;
706 sba
.InstructionBaseAddressModifyEnable
= true;
707 sba
.GeneralStateBufferSizeModifyEnable
= true;
708 sba
.DynamicStateBufferSizeModifyEnable
= true;
710 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
711 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
713 sba
.IndirectObjectBufferSizeModifyEnable
= true;
714 sba
.InstructionBuffersizeModifyEnable
= true;
716 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
717 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
719 sba
.GeneralStateBufferSize
= 0xfffff;
720 sba
.IndirectObjectBufferSize
= 0xfffff;
721 sba
.InstructionBufferSize
= 0xfffff;
722 sba
.DynamicStateBufferSize
= 0xfffff;
725 flush_after_state_base_change(batch
);
729 iris_emit_l3_config(struct iris_batch
*batch
, const struct gen_l3_config
*cfg
,
730 bool has_slm
, bool wants_dc_cache
)
735 #define L3_ALLOCATION_REG GENX(L3ALLOC)
736 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
738 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
739 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
742 iris_pack_state(L3_ALLOCATION_REG
, ®_val
, reg
) {
744 reg
.SLMEnable
= has_slm
;
747 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
748 * in L3CNTLREG register. The default setting of the bit is not the
749 * desirable behavior.
751 reg
.ErrorDetectionBehaviorControl
= true;
752 reg
.UseFullWays
= true;
754 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
755 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
756 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
757 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
759 _iris_emit_lri(batch
, L3_ALLOCATION_REG_num
, reg_val
);
763 iris_emit_default_l3_config(struct iris_batch
*batch
,
764 const struct gen_device_info
*devinfo
,
767 bool wants_dc_cache
= true;
768 bool has_slm
= compute
;
769 const struct gen_l3_weights w
=
770 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
771 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
772 iris_emit_l3_config(batch
, cfg
, has_slm
, wants_dc_cache
);
775 #if GEN_GEN == 9 || GEN_GEN == 10
777 iris_enable_obj_preemption(struct iris_batch
*batch
, bool enable
)
781 /* A fixed function pipe flush is required before modifying this field */
782 iris_emit_end_of_pipe_sync(batch
, enable
? "enable preemption"
783 : "disable preemption",
784 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
786 /* enable object level preemption */
787 iris_pack_state(GENX(CS_CHICKEN1
), ®_val
, reg
) {
788 reg
.ReplayMode
= enable
;
789 reg
.ReplayModeMask
= true;
791 iris_emit_lri(batch
, CS_CHICKEN1
, reg_val
);
797 iris_upload_slice_hashing_state(struct iris_batch
*batch
)
799 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
800 int subslices_delta
=
801 devinfo
->ppipe_subslices
[0] - devinfo
->ppipe_subslices
[1];
802 if (subslices_delta
== 0)
805 struct iris_context
*ice
= NULL
;
806 ice
= container_of(batch
, ice
, batches
[IRIS_BATCH_RENDER
]);
807 assert(&ice
->batches
[IRIS_BATCH_RENDER
] == batch
);
809 unsigned size
= GENX(SLICE_HASH_TABLE_length
) * 4;
810 uint32_t hash_address
;
811 struct pipe_resource
*tmp
= NULL
;
813 stream_state(batch
, ice
->state
.dynamic_uploader
, &tmp
,
814 size
, 64, &hash_address
);
815 pipe_resource_reference(&tmp
, NULL
);
817 struct GENX(SLICE_HASH_TABLE
) table0
= {
819 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
820 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
821 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
822 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
823 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
824 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
825 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
826 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
827 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
828 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
829 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
830 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
831 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
832 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
833 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
834 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }
838 struct GENX(SLICE_HASH_TABLE
) table1
= {
840 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
841 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
842 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
843 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
844 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
845 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
846 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
847 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
848 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
849 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
850 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
851 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
852 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
853 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
854 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
855 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }
859 const struct GENX(SLICE_HASH_TABLE
) *table
=
860 subslices_delta
< 0 ? &table0
: &table1
;
861 GENX(SLICE_HASH_TABLE_pack
)(NULL
, map
, table
);
863 iris_emit_cmd(batch
, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS
), ptr
) {
864 ptr
.SliceHashStatePointerValid
= true;
865 ptr
.SliceHashTableStatePointer
= hash_address
;
868 iris_emit_cmd(batch
, GENX(3DSTATE_3D_MODE
), mode
) {
869 mode
.SliceHashingTableEnable
= true;
875 iris_alloc_push_constants(struct iris_batch
*batch
)
877 /* For now, we set a static partitioning of the push constant area,
878 * assuming that all stages could be in use.
880 * TODO: Try lazily allocating the HS/DS/GS sections as needed, and
881 * see if that improves performance by offering more space to
882 * the VS/FS when those aren't in use. Also, try dynamically
883 * enabling/disabling it like i965 does. This would be more
884 * stalls and may not actually help; we don't know yet.
886 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
887 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
888 alloc
._3DCommandSubOpcode
= 18 + i
;
889 alloc
.ConstantBufferOffset
= 6 * i
;
890 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
896 * Upload the initial GPU state for a render context.
898 * This sets some invariant state that needs to be programmed a particular
899 * way, but we never actually change.
902 iris_init_render_context(struct iris_batch
*batch
)
904 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
907 emit_pipeline_select(batch
, _3D
);
909 iris_emit_default_l3_config(batch
, devinfo
, false);
911 init_state_base_address(batch
);
914 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
915 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
916 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
918 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
920 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
921 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
922 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
924 iris_emit_lri(batch
, INSTPM
, reg_val
);
928 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
929 reg
.FloatBlendOptimizationEnable
= true;
930 reg
.FloatBlendOptimizationEnableMask
= true;
931 reg
.PartialResolveDisableInVC
= true;
932 reg
.PartialResolveDisableInVCMask
= true;
934 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
936 if (devinfo
->is_geminilake
)
937 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
941 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
942 reg
.HeaderlessMessageforPreemptableContexts
= 1;
943 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
945 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
947 /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
948 iris_pack_state(GENX(HALF_SLICE_CHICKEN7
), ®_val
, reg
) {
949 reg
.EnabledTexelOffsetPrecisionFix
= 1;
950 reg
.EnabledTexelOffsetPrecisionFixMask
= 1;
952 iris_emit_lri(batch
, HALF_SLICE_CHICKEN7
, reg_val
);
954 /* Hardware specification recommends disabling repacking for the
955 * compatibility with decompression mechanism in display controller.
957 if (devinfo
->disable_ccs_repack
) {
958 iris_pack_state(GENX(CACHE_MODE_0
), ®_val
, reg
) {
959 reg
.DisableRepackingforCompression
= true;
960 reg
.DisableRepackingforCompressionMask
= true;
962 iris_emit_lri(batch
, CACHE_MODE_0
, reg_val
);
965 iris_upload_slice_hashing_state(batch
);
968 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
969 * changing it dynamically. We set it to the maximum size here, and
970 * instead include the render target dimensions in the viewport, so
971 * viewport extents clipping takes care of pruning stray geometry.
973 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
974 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
975 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
978 /* Set the initial MSAA sample positions. */
979 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
980 GEN_SAMPLE_POS_1X(pat
._1xSample
);
981 GEN_SAMPLE_POS_2X(pat
._2xSample
);
982 GEN_SAMPLE_POS_4X(pat
._4xSample
);
983 GEN_SAMPLE_POS_8X(pat
._8xSample
);
985 GEN_SAMPLE_POS_16X(pat
._16xSample
);
989 /* Use the legacy AA line coverage computation. */
990 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
992 /* Disable chromakeying (it's for media) */
993 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
995 /* We want regular rendering, not special HiZ operations. */
996 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
998 /* No polygon stippling offsets are necessary. */
999 /* TODO: may need to set an offset for origin-UL framebuffers */
1000 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
1002 iris_alloc_push_constants(batch
);
1005 /* Gen11+ is enabled for us by the kernel. */
1006 iris_enable_obj_preemption(batch
, true);
1011 iris_init_compute_context(struct iris_batch
*batch
)
1013 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
1015 emit_pipeline_select(batch
, GPGPU
);
1017 iris_emit_default_l3_config(batch
, devinfo
, true);
1019 init_state_base_address(batch
);
1022 if (devinfo
->is_geminilake
)
1023 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
1027 struct iris_vertex_buffer_state
{
1028 /** The VERTEX_BUFFER_STATE hardware structure. */
1029 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
1031 /** The resource to source vertex data from. */
1032 struct pipe_resource
*resource
;
1037 struct iris_depth_buffer_state
{
1038 /* Depth/HiZ/Stencil related hardware packets. */
1039 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
1040 GENX(3DSTATE_STENCIL_BUFFER_length
) +
1041 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
1042 GENX(3DSTATE_CLEAR_PARAMS_length
)];
1046 * Generation-specific context state (ice->state.genx->...).
1048 * Most state can go in iris_context directly, but these encode hardware
1049 * packets which vary by generation.
1051 struct iris_genx_state
{
1052 struct iris_vertex_buffer_state vertex_buffers
[33];
1053 uint32_t last_index_buffer
[GENX(3DSTATE_INDEX_BUFFER_length
)];
1055 struct iris_depth_buffer_state depth_buffer
;
1057 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
1060 bool pma_fix_enabled
;
1064 /* Is object level preemption enabled? */
1065 bool object_preemption
;
1070 struct brw_image_param image_param
[PIPE_MAX_SHADER_IMAGES
];
1072 } shaders
[MESA_SHADER_STAGES
];
1076 * The pipe->set_blend_color() driver hook.
1078 * This corresponds to our COLOR_CALC_STATE.
1081 iris_set_blend_color(struct pipe_context
*ctx
,
1082 const struct pipe_blend_color
*state
)
1084 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1086 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
1087 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
1088 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1092 * Gallium CSO for blend state (see pipe_blend_state).
1094 struct iris_blend_state
{
1095 /** Partial 3DSTATE_PS_BLEND */
1096 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
1098 /** Partial BLEND_STATE */
1099 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
1100 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
1102 bool alpha_to_coverage
; /* for shader key */
1104 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
1105 uint8_t blend_enables
;
1107 /** Bitfield of whether color writes are enabled for RT[i] */
1108 uint8_t color_write_enables
;
1110 /** Does RT[0] use dual color blending? */
1111 bool dual_color_blending
;
1114 static enum pipe_blendfactor
1115 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
1118 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
1119 return PIPE_BLENDFACTOR_ONE
;
1121 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
1122 return PIPE_BLENDFACTOR_ZERO
;
1129 * The pipe->create_blend_state() driver hook.
1131 * Translates a pipe_blend_state into iris_blend_state.
1134 iris_create_blend_state(struct pipe_context
*ctx
,
1135 const struct pipe_blend_state
*state
)
1137 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
1138 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
1140 cso
->blend_enables
= 0;
1141 cso
->color_write_enables
= 0;
1142 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
1144 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
1146 bool indep_alpha_blend
= false;
1148 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
1149 const struct pipe_rt_blend_state
*rt
=
1150 &state
->rt
[state
->independent_blend_enable
? i
: 0];
1152 enum pipe_blendfactor src_rgb
=
1153 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
1154 enum pipe_blendfactor src_alpha
=
1155 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
1156 enum pipe_blendfactor dst_rgb
=
1157 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
1158 enum pipe_blendfactor dst_alpha
=
1159 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
1161 if (rt
->rgb_func
!= rt
->alpha_func
||
1162 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
1163 indep_alpha_blend
= true;
1165 if (rt
->blend_enable
)
1166 cso
->blend_enables
|= 1u << i
;
1169 cso
->color_write_enables
|= 1u << i
;
1171 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
1172 be
.LogicOpEnable
= state
->logicop_enable
;
1173 be
.LogicOpFunction
= state
->logicop_func
;
1175 be
.PreBlendSourceOnlyClampEnable
= false;
1176 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
1177 be
.PreBlendColorClampEnable
= true;
1178 be
.PostBlendColorClampEnable
= true;
1180 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
1182 be
.ColorBlendFunction
= rt
->rgb_func
;
1183 be
.AlphaBlendFunction
= rt
->alpha_func
;
1184 be
.SourceBlendFactor
= src_rgb
;
1185 be
.SourceAlphaBlendFactor
= src_alpha
;
1186 be
.DestinationBlendFactor
= dst_rgb
;
1187 be
.DestinationAlphaBlendFactor
= dst_alpha
;
1189 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
1190 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
1191 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
1192 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
1194 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
1197 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
1198 /* pb.HasWriteableRT is filled in at draw time.
1199 * pb.AlphaTestEnable is filled in at draw time.
1201 * pb.ColorBufferBlendEnable is filled in at draw time so we can avoid
1202 * setting it when dual color blending without an appropriate shader.
1205 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1206 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1208 pb
.SourceBlendFactor
=
1209 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
1210 pb
.SourceAlphaBlendFactor
=
1211 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
1212 pb
.DestinationBlendFactor
=
1213 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
1214 pb
.DestinationAlphaBlendFactor
=
1215 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
1218 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
1219 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1220 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1221 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
1222 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
1223 bs
.ColorDitherEnable
= state
->dither
;
1224 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
1227 cso
->dual_color_blending
= util_blend_state_is_dual(state
, 0);
1233 * The pipe->bind_blend_state() driver hook.
1235 * Bind a blending CSO and flag related dirty bits.
1238 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
1240 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1241 struct iris_blend_state
*cso
= state
;
1243 ice
->state
.cso_blend
= cso
;
1244 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
1246 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1247 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1248 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1249 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
1252 ice
->state
.dirty
|= IRIS_DIRTY_PMA_FIX
;
1256 * Return true if the FS writes to any color outputs which are not disabled
1257 * via color masking.
1260 has_writeable_rt(const struct iris_blend_state
*cso_blend
,
1261 const struct shader_info
*fs_info
)
1266 unsigned rt_outputs
= fs_info
->outputs_written
>> FRAG_RESULT_DATA0
;
1268 if (fs_info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
))
1269 rt_outputs
= (1 << BRW_MAX_DRAW_BUFFERS
) - 1;
1271 return cso_blend
->color_write_enables
& rt_outputs
;
1275 * Gallium CSO for depth, stencil, and alpha testing state.
1277 struct iris_depth_stencil_alpha_state
{
1278 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
1279 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1282 uint32_t depth_bounds
[GENX(3DSTATE_DEPTH_BOUNDS_length
)];
1285 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
1286 struct pipe_alpha_state alpha
;
1288 /** Outbound to resolve and cache set tracking. */
1289 bool depth_writes_enabled
;
1290 bool stencil_writes_enabled
;
1292 /** Outbound to Gen8-9 PMA stall equations */
1293 bool depth_test_enabled
;
1297 * The pipe->create_depth_stencil_alpha_state() driver hook.
1299 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
1300 * testing state since we need pieces of it in a variety of places.
1303 iris_create_zsa_state(struct pipe_context
*ctx
,
1304 const struct pipe_depth_stencil_alpha_state
*state
)
1306 struct iris_depth_stencil_alpha_state
*cso
=
1307 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
1309 bool two_sided_stencil
= state
->stencil
[1].enabled
;
1311 cso
->alpha
= state
->alpha
;
1312 cso
->depth_writes_enabled
= state
->depth
.writemask
;
1313 cso
->depth_test_enabled
= state
->depth
.enabled
;
1314 cso
->stencil_writes_enabled
=
1315 state
->stencil
[0].writemask
!= 0 ||
1316 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1318 /* The state tracker needs to optimize away EQUAL writes for us. */
1319 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
1321 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
1322 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1323 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1324 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1325 wmds
.StencilTestFunction
=
1326 translate_compare_func(state
->stencil
[0].func
);
1327 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1328 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1329 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1330 wmds
.BackfaceStencilTestFunction
=
1331 translate_compare_func(state
->stencil
[1].func
);
1332 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1333 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1334 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1335 wmds
.StencilBufferWriteEnable
=
1336 state
->stencil
[0].writemask
!= 0 ||
1337 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1338 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1339 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1340 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1341 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1342 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1343 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1344 /* wmds.[Backface]StencilReferenceValue are merged later */
1348 iris_pack_command(GENX(3DSTATE_DEPTH_BOUNDS
), cso
->depth_bounds
, depth_bounds
) {
1349 depth_bounds
.DepthBoundsTestValueModifyDisable
= false;
1350 depth_bounds
.DepthBoundsTestEnableModifyDisable
= false;
1351 depth_bounds
.DepthBoundsTestEnable
= state
->depth
.bounds_test
;
1352 depth_bounds
.DepthBoundsTestMinValue
= state
->depth
.bounds_min
;
1353 depth_bounds
.DepthBoundsTestMaxValue
= state
->depth
.bounds_max
;
1361 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1363 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1366 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1368 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1369 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1370 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1373 if (cso_changed(alpha
.ref_value
))
1374 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1376 if (cso_changed(alpha
.enabled
))
1377 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1379 if (cso_changed(alpha
.func
))
1380 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1382 if (cso_changed(depth_writes_enabled
))
1383 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1385 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1386 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1389 if (cso_changed(depth_bounds
))
1390 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BOUNDS
;
1394 ice
->state
.cso_zsa
= new_cso
;
1395 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1396 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1397 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1400 ice
->state
.dirty
|= IRIS_DIRTY_PMA_FIX
;
1405 want_pma_fix(struct iris_context
*ice
)
1407 UNUSED
struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1408 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1409 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
1410 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
1411 const struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
1412 const struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
1413 const struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
1415 /* In very specific combinations of state, we can instruct Gen8-9 hardware
1416 * to avoid stalling at the pixel mask array. The state equations are
1417 * documented in these places:
1419 * - Gen8 Depth PMA Fix: CACHE_MODE_1::NP_PMA_FIX_ENABLE
1420 * - Gen9 Stencil PMA Fix: CACHE_MODE_0::STC PMA Optimization Enable
1422 * Both equations share some common elements:
1425 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
1426 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
1427 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
1428 * 3DSTATE_WM_HZ_OP::StencilBufferClear) &&
1431 * 3DSTATE_WM::ForceKillPix != ForceOff &&
1432 * (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
1433 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
1434 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
1435 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
1436 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable)
1438 * (Technically the stencil PMA treats ForceKillPix differently,
1439 * but I think this is a documentation oversight, and we don't
1440 * ever use it in this way, so it doesn't matter).
1443 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
1444 * 3DSTATE_RASTER::ForceSampleCount == NUMRASTSAMPLES_0 &&
1445 * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
1446 * 3DSTATE_DEPTH_BUFFER::HIZ Enable &&
1447 * 3DSTATE_WM::EDSC_Mode != EDSC_PREPS &&
1448 * 3DSTATE_PS_EXTRA::PixelShaderValid &&
1451 * These are always true:
1453 * 3DSTATE_RASTER::ForceSampleCount == NUMRASTSAMPLES_0
1454 * 3DSTATE_PS_EXTRA::PixelShaderValid
1456 * Also, we never use the normal drawing path for HiZ ops; these are true:
1458 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
1459 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
1460 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
1461 * 3DSTATE_WM_HZ_OP::StencilBufferClear)
1463 * This happens sometimes:
1465 * 3DSTATE_WM::ForceThreadDispatch != 1
1467 * However, we choose to ignore it as it either agrees with the signal
1468 * (dispatch was already enabled, so nothing out of the ordinary), or
1469 * there are no framebuffer attachments (so no depth or HiZ anyway,
1470 * meaning the PMA signal will already be disabled).
1476 struct iris_resource
*zres
, *sres
;
1477 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
, &zres
, &sres
);
1479 /* 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
1480 * 3DSTATE_DEPTH_BUFFER::HIZ Enable &&
1482 if (!zres
|| !iris_resource_level_has_hiz(zres
, cso_fb
->zsbuf
->u
.tex
.level
))
1485 /* 3DSTATE_WM::EDSC_Mode != EDSC_PREPS */
1486 if (wm_prog_data
->early_fragment_tests
)
1489 /* 3DSTATE_WM::ForceKillPix != ForceOff &&
1490 * (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
1491 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
1492 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
1493 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
1494 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable)
1496 bool killpixels
= wm_prog_data
->uses_kill
|| wm_prog_data
->uses_omask
||
1497 cso_blend
->alpha_to_coverage
|| cso_zsa
->alpha
.enabled
;
1499 /* The Gen8 depth PMA equation becomes:
1502 * 3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
1503 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE
1506 * 3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
1507 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
1508 * 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE
1512 * 3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable &&
1513 * ((killpixels && (depth_writes || stencil_writes)) ||
1514 * 3DSTATE_PS_EXTRA::PixelShaderComputedDepthMode != PSCDEPTH_OFF)
1517 if (!cso_zsa
->depth_test_enabled
)
1520 return wm_prog_data
->computed_depth_mode
!= PSCDEPTH_OFF
||
1521 (killpixels
&& (cso_zsa
->depth_writes_enabled
||
1522 (sres
&& cso_zsa
->stencil_writes_enabled
)));
1527 genX(update_pma_fix
)(struct iris_context
*ice
,
1528 struct iris_batch
*batch
,
1532 struct iris_genx_state
*genx
= ice
->state
.genx
;
1534 if (genx
->pma_fix_enabled
== enable
)
1537 genx
->pma_fix_enabled
= enable
;
1539 /* According to the Broadwell PIPE_CONTROL documentation, software should
1540 * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
1541 * prior to the LRI. If stencil buffer writes are enabled, then a Render * Cache Flush is also necessary.
1543 * The Gen9 docs say to use a depth stall rather than a command streamer
1544 * stall. However, the hardware seems to violently disagree. A full
1545 * command streamer stall seems to be needed in both cases.
1547 iris_emit_pipe_control_flush(batch
, "PMA fix change (1/2)",
1548 PIPE_CONTROL_CS_STALL
|
1549 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1550 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1553 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
1554 reg
.NPPMAFixEnable
= enable
;
1555 reg
.NPEarlyZFailsDisable
= enable
;
1556 reg
.NPPMAFixEnableMask
= true;
1557 reg
.NPEarlyZFailsDisableMask
= true;
1559 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
1561 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
1562 * Flush bits is often necessary. We do it regardless because it's easier.
1563 * The render cache flush is also necessary if stencil writes are enabled.
1565 * Again, the Gen9 docs give a different set of flushes but the Broadwell
1566 * flushes seem to work just as well.
1568 iris_emit_pipe_control_flush(batch
, "PMA fix change (1/2)",
1569 PIPE_CONTROL_DEPTH_STALL
|
1570 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1571 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1576 * Gallium CSO for rasterizer state.
1578 struct iris_rasterizer_state
{
1579 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1580 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1581 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1582 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1583 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1585 uint8_t num_clip_plane_consts
;
1586 bool clip_halfz
; /* for CC_VIEWPORT */
1587 bool depth_clip_near
; /* for CC_VIEWPORT */
1588 bool depth_clip_far
; /* for CC_VIEWPORT */
1589 bool flatshade
; /* for shader state */
1590 bool flatshade_first
; /* for stream output */
1591 bool clamp_fragment_color
; /* for shader state */
1592 bool light_twoside
; /* for shader state */
1593 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1594 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1595 bool line_stipple_enable
;
1596 bool poly_stipple_enable
;
1598 bool force_persample_interp
;
1599 bool conservative_rasterization
;
1600 bool fill_mode_point_or_line
;
1601 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1602 uint16_t sprite_coord_enable
;
1606 get_line_width(const struct pipe_rasterizer_state
*state
)
1608 float line_width
= state
->line_width
;
1610 /* From the OpenGL 4.4 spec:
1612 * "The actual width of non-antialiased lines is determined by rounding
1613 * the supplied width to the nearest integer, then clamping it to the
1614 * implementation-dependent maximum non-antialiased line width."
1616 if (!state
->multisample
&& !state
->line_smooth
)
1617 line_width
= roundf(state
->line_width
);
1619 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1620 /* For 1 pixel line thickness or less, the general anti-aliasing
1621 * algorithm gives up, and a garbage line is generated. Setting a
1622 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1623 * (one-pixel-wide), non-antialiased lines.
1625 * Lines rendered with zero Line Width are rasterized using the
1626 * "Grid Intersection Quantization" rules as specified by the
1627 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1636 * The pipe->create_rasterizer_state() driver hook.
1639 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1640 const struct pipe_rasterizer_state
*state
)
1642 struct iris_rasterizer_state
*cso
=
1643 malloc(sizeof(struct iris_rasterizer_state
));
1645 cso
->multisample
= state
->multisample
;
1646 cso
->force_persample_interp
= state
->force_persample_interp
;
1647 cso
->clip_halfz
= state
->clip_halfz
;
1648 cso
->depth_clip_near
= state
->depth_clip_near
;
1649 cso
->depth_clip_far
= state
->depth_clip_far
;
1650 cso
->flatshade
= state
->flatshade
;
1651 cso
->flatshade_first
= state
->flatshade_first
;
1652 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1653 cso
->light_twoside
= state
->light_twoside
;
1654 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1655 cso
->half_pixel_center
= state
->half_pixel_center
;
1656 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1657 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1658 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1659 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1660 cso
->conservative_rasterization
=
1661 state
->conservative_raster_mode
== PIPE_CONSERVATIVE_RASTER_POST_SNAP
;
1663 cso
->fill_mode_point_or_line
=
1664 state
->fill_front
== PIPE_POLYGON_MODE_LINE
||
1665 state
->fill_front
== PIPE_POLYGON_MODE_POINT
||
1666 state
->fill_back
== PIPE_POLYGON_MODE_LINE
||
1667 state
->fill_back
== PIPE_POLYGON_MODE_POINT
;
1669 if (state
->clip_plane_enable
!= 0)
1670 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1672 cso
->num_clip_plane_consts
= 0;
1674 float line_width
= get_line_width(state
);
1676 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1677 sf
.StatisticsEnable
= true;
1678 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1679 sf
.LineEndCapAntialiasingRegionWidth
=
1680 state
->line_smooth
? _10pixels
: _05pixels
;
1681 sf
.LastPixelEnable
= state
->line_last_pixel
;
1682 sf
.LineWidth
= line_width
;
1683 sf
.SmoothPointEnable
= (state
->point_smooth
|| state
->multisample
) &&
1684 !state
->point_quad_rasterization
;
1685 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1686 sf
.PointWidth
= state
->point_size
;
1688 if (state
->flatshade_first
) {
1689 sf
.TriangleFanProvokingVertexSelect
= 1;
1691 sf
.TriangleStripListProvokingVertexSelect
= 2;
1692 sf
.TriangleFanProvokingVertexSelect
= 2;
1693 sf
.LineStripListProvokingVertexSelect
= 1;
1697 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1698 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1699 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1700 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1701 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1702 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1703 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1704 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1705 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1706 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1707 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1708 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1709 rr
.SmoothPointEnable
= state
->point_smooth
;
1710 rr
.AntialiasingEnable
= state
->line_smooth
;
1711 rr
.ScissorRectangleEnable
= state
->scissor
;
1713 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1714 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1715 rr
.ConservativeRasterizationEnable
=
1716 cso
->conservative_rasterization
;
1718 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1722 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1723 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1724 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1726 cl
.EarlyCullEnable
= true;
1727 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1728 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1729 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1730 cl
.GuardbandClipTestEnable
= true;
1731 cl
.ClipEnable
= true;
1732 cl
.MinimumPointWidth
= 0.125;
1733 cl
.MaximumPointWidth
= 255.875;
1735 if (state
->flatshade_first
) {
1736 cl
.TriangleFanProvokingVertexSelect
= 1;
1738 cl
.TriangleStripListProvokingVertexSelect
= 2;
1739 cl
.TriangleFanProvokingVertexSelect
= 2;
1740 cl
.LineStripListProvokingVertexSelect
= 1;
1744 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1745 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1746 * filled in at draw time from the FS program.
1748 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1749 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1750 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1751 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1752 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1755 /* Remap from 0..255 back to 1..256 */
1756 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1758 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1759 if (state
->line_stipple_enable
) {
1760 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1761 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1762 line
.LineStippleRepeatCount
= line_stipple_factor
;
1770 * The pipe->bind_rasterizer_state() driver hook.
1772 * Bind a rasterizer CSO and flag related dirty bits.
1775 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1777 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1778 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1779 struct iris_rasterizer_state
*new_cso
= state
;
1782 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1783 if (cso_changed_memcmp(line_stipple
))
1784 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1786 if (cso_changed(half_pixel_center
))
1787 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1789 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1790 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1792 if (cso_changed(rasterizer_discard
))
1793 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1795 if (cso_changed(flatshade_first
))
1796 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1798 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1799 cso_changed(clip_halfz
))
1800 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1802 if (cso_changed(sprite_coord_enable
) ||
1803 cso_changed(sprite_coord_mode
) ||
1804 cso_changed(light_twoside
))
1805 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1807 if (cso_changed(conservative_rasterization
))
1808 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
1811 ice
->state
.cso_rast
= new_cso
;
1812 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1813 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1814 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1818 * Return true if the given wrap mode requires the border color to exist.
1820 * (We can skip uploading it if the sampler isn't going to use it.)
1823 wrap_mode_needs_border_color(unsigned wrap_mode
)
1825 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1829 * Gallium CSO for sampler state.
1831 struct iris_sampler_state
{
1832 union pipe_color_union border_color
;
1833 bool needs_border_color
;
1835 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1839 * The pipe->create_sampler_state() driver hook.
1841 * We fill out SAMPLER_STATE (except for the border color pointer), and
1842 * store that on the CPU. It doesn't make sense to upload it to a GPU
1843 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1844 * all bound sampler states to be in contiguous memor.
1847 iris_create_sampler_state(struct pipe_context
*ctx
,
1848 const struct pipe_sampler_state
*state
)
1850 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1855 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1856 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1858 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1859 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1860 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1862 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1864 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1865 wrap_mode_needs_border_color(wrap_t
) ||
1866 wrap_mode_needs_border_color(wrap_r
);
1868 float min_lod
= state
->min_lod
;
1869 unsigned mag_img_filter
= state
->mag_img_filter
;
1871 // XXX: explain this code ported from ilo...I don't get it at all...
1872 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1873 state
->min_lod
> 0.0f
) {
1875 mag_img_filter
= state
->min_img_filter
;
1878 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1879 samp
.TCXAddressControlMode
= wrap_s
;
1880 samp
.TCYAddressControlMode
= wrap_t
;
1881 samp
.TCZAddressControlMode
= wrap_r
;
1882 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1883 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1884 samp
.MinModeFilter
= state
->min_img_filter
;
1885 samp
.MagModeFilter
= mag_img_filter
;
1886 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1887 samp
.MaximumAnisotropy
= RATIO21
;
1889 if (state
->max_anisotropy
>= 2) {
1890 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1891 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1892 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1895 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1896 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1898 samp
.MaximumAnisotropy
=
1899 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1902 /* Set address rounding bits if not using nearest filtering. */
1903 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1904 samp
.UAddressMinFilterRoundingEnable
= true;
1905 samp
.VAddressMinFilterRoundingEnable
= true;
1906 samp
.RAddressMinFilterRoundingEnable
= true;
1909 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1910 samp
.UAddressMagFilterRoundingEnable
= true;
1911 samp
.VAddressMagFilterRoundingEnable
= true;
1912 samp
.RAddressMagFilterRoundingEnable
= true;
1915 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1916 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1918 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1920 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1921 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1922 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1923 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1925 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1932 * The pipe->bind_sampler_states() driver hook.
1935 iris_bind_sampler_states(struct pipe_context
*ctx
,
1936 enum pipe_shader_type p_stage
,
1937 unsigned start
, unsigned count
,
1940 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1941 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1942 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1944 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1948 for (int i
= 0; i
< count
; i
++) {
1949 if (shs
->samplers
[start
+ i
] != states
[i
]) {
1950 shs
->samplers
[start
+ i
] = states
[i
];
1956 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1960 * Upload the sampler states into a contiguous area of GPU memory, for
1961 * for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1963 * Also fill out the border color state pointers.
1966 iris_upload_sampler_states(struct iris_context
*ice
, gl_shader_stage stage
)
1968 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1969 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
1971 /* We assume the state tracker will call pipe->bind_sampler_states()
1972 * if the program's number of textures changes.
1974 unsigned count
= info
? util_last_bit(info
->textures_used
) : 0;
1979 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1980 * in the dynamic state memory zone, so we can point to it via the
1981 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1983 unsigned size
= count
* 4 * GENX(SAMPLER_STATE_length
);
1985 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
, size
, 32);
1989 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1990 shs
->sampler_table
.offset
+=
1991 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1993 iris_record_state_size(ice
->state
.sizes
, shs
->sampler_table
.offset
, size
);
1995 /* Make sure all land in the same BO */
1996 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1998 ice
->state
.need_border_colors
&= ~(1 << stage
);
2000 for (int i
= 0; i
< count
; i
++) {
2001 struct iris_sampler_state
*state
= shs
->samplers
[i
];
2002 struct iris_sampler_view
*tex
= shs
->textures
[i
];
2005 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
2006 } else if (!state
->needs_border_color
) {
2007 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
2009 ice
->state
.need_border_colors
|= 1 << stage
;
2011 /* We may need to swizzle the border color for format faking.
2012 * A/LA formats are faked as R/RG with 000R or R00G swizzles.
2013 * This means we need to move the border color's A channel into
2014 * the R or G channels so that those read swizzles will move it
2017 union pipe_color_union
*color
= &state
->border_color
;
2018 union pipe_color_union tmp
;
2020 enum pipe_format internal_format
= tex
->res
->internal_format
;
2022 if (util_format_is_alpha(internal_format
)) {
2023 unsigned char swz
[4] = {
2024 PIPE_SWIZZLE_W
, PIPE_SWIZZLE_0
,
2025 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
2027 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
2029 } else if (util_format_is_luminance_alpha(internal_format
) &&
2030 internal_format
!= PIPE_FORMAT_L8A8_SRGB
) {
2031 unsigned char swz
[4] = {
2032 PIPE_SWIZZLE_X
, PIPE_SWIZZLE_W
,
2033 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
2035 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
2040 /* Stream out the border color and merge the pointer. */
2041 uint32_t offset
= iris_upload_border_color(ice
, color
);
2043 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
2044 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
2045 dyns
.BorderColorPointer
= offset
;
2048 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
2049 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
2052 map
+= GENX(SAMPLER_STATE_length
);
2056 static enum isl_channel_select
2057 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
2060 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
2061 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
2062 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
2063 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
2064 case PIPE_SWIZZLE_1
: return SCS_ONE
;
2065 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
2066 default: unreachable("invalid swizzle");
2071 fill_buffer_surface_state(struct isl_device
*isl_dev
,
2072 struct iris_resource
*res
,
2074 enum isl_format format
,
2075 struct isl_swizzle swizzle
,
2079 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
2080 const unsigned cpp
= format
== ISL_FORMAT_RAW
? 1 : fmtl
->bpb
/ 8;
2082 /* The ARB_texture_buffer_specification says:
2084 * "The number of texels in the buffer texture's texel array is given by
2086 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
2088 * where <buffer_size> is the size of the buffer object, in basic
2089 * machine units and <components> and <base_type> are the element count
2090 * and base data type for elements, as specified in Table X.1. The
2091 * number of texels in the texel array is then clamped to the
2092 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
2094 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
2095 * so that when ISL divides by stride to obtain the number of texels, that
2096 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
2098 unsigned final_size
=
2099 MIN3(size
, res
->bo
->size
- res
->offset
- offset
,
2100 IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
2102 isl_buffer_fill_state(isl_dev
, map
,
2103 .address
= res
->bo
->gtt_offset
+ res
->offset
+ offset
,
2104 .size_B
= final_size
,
2108 .mocs
= mocs(res
->bo
));
2111 #define SURFACE_STATE_ALIGNMENT 64
2114 * Allocate several contiguous SURFACE_STATE structures, one for each
2115 * supported auxiliary surface mode.
2118 alloc_surface_states(struct u_upload_mgr
*mgr
,
2119 struct iris_state_ref
*ref
,
2120 unsigned aux_usages
)
2122 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
2124 /* If this changes, update this to explicitly align pointers */
2125 STATIC_ASSERT(surf_size
== SURFACE_STATE_ALIGNMENT
);
2127 assert(aux_usages
!= 0);
2130 upload_state(mgr
, ref
, util_bitcount(aux_usages
) * surf_size
,
2131 SURFACE_STATE_ALIGNMENT
);
2133 ref
->offset
+= iris_bo_offset_from_base_address(iris_resource_bo(ref
->res
));
2140 * Return an ISL surface for use with non-coherent render target reads.
2142 * In a few complex cases, we can't use the SURFACE_STATE for normal render
2143 * target writes. We need to make a separate one for sampling which refers
2144 * to the single slice of the texture being read.
2147 get_rt_read_isl_surf(const struct gen_device_info
*devinfo
,
2148 struct iris_resource
*res
,
2149 enum pipe_texture_target target
,
2150 struct isl_view
*view
,
2151 uint32_t *tile_x_sa
,
2152 uint32_t *tile_y_sa
,
2153 struct isl_surf
*surf
)
2158 const enum isl_dim_layout dim_layout
=
2159 iris_get_isl_dim_layout(devinfo
, res
->surf
.tiling
, target
);
2161 surf
->dim
= target_to_isl_surf_dim(target
);
2163 if (surf
->dim_layout
== dim_layout
)
2166 /* The layout of the specified texture target is not compatible with the
2167 * actual layout of the miptree structure in memory -- You're entering
2168 * dangerous territory, this can only possibly work if you only intended
2169 * to access a single level and slice of the texture, and the hardware
2170 * supports the tile offset feature in order to allow non-tile-aligned
2171 * base offsets, since we'll have to point the hardware to the first
2172 * texel of the level instead of relying on the usual base level/layer
2175 assert(view
->levels
== 1 && view
->array_len
== 1);
2176 assert(*tile_x_sa
== 0 && *tile_y_sa
== 0);
2178 res
->offset
+= iris_resource_get_tile_offsets(res
, view
->base_level
,
2179 view
->base_array_layer
,
2180 tile_x_sa
, tile_y_sa
);
2181 const unsigned l
= view
->base_level
;
2183 surf
->logical_level0_px
.width
= minify(surf
->logical_level0_px
.width
, l
);
2184 surf
->logical_level0_px
.height
= surf
->dim
<= ISL_SURF_DIM_1D
? 1 :
2185 minify(surf
->logical_level0_px
.height
, l
);
2186 surf
->logical_level0_px
.depth
= surf
->dim
<= ISL_SURF_DIM_2D
? 1 :
2187 minify(surf
->logical_level0_px
.depth
, l
);
2189 surf
->logical_level0_px
.array_len
= 1;
2191 surf
->dim_layout
= dim_layout
;
2193 view
->base_level
= 0;
2194 view
->base_array_layer
= 0;
2199 fill_surface_state(struct isl_device
*isl_dev
,
2201 struct iris_resource
*res
,
2202 struct isl_surf
*surf
,
2203 struct isl_view
*view
,
2208 struct isl_surf_fill_state_info f
= {
2211 .mocs
= mocs(res
->bo
),
2212 .address
= res
->bo
->gtt_offset
+ res
->offset
,
2213 .x_offset_sa
= tile_x_sa
,
2214 .y_offset_sa
= tile_y_sa
,
2217 assert(!iris_resource_unfinished_aux_import(res
));
2219 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
2220 f
.aux_surf
= &res
->aux
.surf
;
2221 f
.aux_usage
= aux_usage
;
2222 f
.aux_address
= res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
;
2224 struct iris_bo
*clear_bo
= NULL
;
2225 uint64_t clear_offset
= 0;
2227 iris_resource_get_clear_color(res
, &clear_bo
, &clear_offset
);
2229 f
.clear_address
= clear_bo
->gtt_offset
+ clear_offset
;
2230 f
.use_clear_address
= isl_dev
->info
->gen
> 9;
2234 isl_surf_fill_state_s(isl_dev
, map
, &f
);
2238 * The pipe->create_sampler_view() driver hook.
2240 static struct pipe_sampler_view
*
2241 iris_create_sampler_view(struct pipe_context
*ctx
,
2242 struct pipe_resource
*tex
,
2243 const struct pipe_sampler_view
*tmpl
)
2245 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2246 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2247 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2248 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
2253 /* initialize base object */
2255 isv
->base
.context
= ctx
;
2256 isv
->base
.texture
= NULL
;
2257 pipe_reference_init(&isv
->base
.reference
, 1);
2258 pipe_resource_reference(&isv
->base
.texture
, tex
);
2260 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
2261 struct iris_resource
*zres
, *sres
;
2262 const struct util_format_description
*desc
=
2263 util_format_description(tmpl
->format
);
2265 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
2267 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
2270 isv
->res
= (struct iris_resource
*) tex
;
2272 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
2273 &isv
->surface_state
,
2274 isv
->res
->aux
.sampler_usages
);
2278 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
2280 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
2281 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
2282 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
2284 const struct iris_format_info fmt
=
2285 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
2287 isv
->clear_color
= isv
->res
->aux
.clear_color
;
2289 isv
->view
= (struct isl_view
) {
2291 .swizzle
= (struct isl_swizzle
) {
2292 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
2293 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
2294 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
2295 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
2300 /* Fill out SURFACE_STATE for this view. */
2301 if (tmpl
->target
!= PIPE_BUFFER
) {
2302 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
2303 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
2304 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
2305 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
2306 isv
->view
.array_len
=
2307 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
2309 if (iris_resource_unfinished_aux_import(isv
->res
))
2310 iris_resource_finish_aux_import(&screen
->base
, isv
->res
);
2312 unsigned aux_modes
= isv
->res
->aux
.sampler_usages
;
2314 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
2316 /* If we have a multisampled depth buffer, do not create a sampler
2317 * surface state with HiZ.
2319 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->res
->surf
,
2320 &isv
->view
, aux_usage
, 0, 0);
2322 map
+= SURFACE_STATE_ALIGNMENT
;
2325 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
2326 isv
->view
.format
, isv
->view
.swizzle
,
2327 tmpl
->u
.buf
.offset
, tmpl
->u
.buf
.size
);
2334 iris_sampler_view_destroy(struct pipe_context
*ctx
,
2335 struct pipe_sampler_view
*state
)
2337 struct iris_sampler_view
*isv
= (void *) state
;
2338 pipe_resource_reference(&state
->texture
, NULL
);
2339 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
2344 * The pipe->create_surface() driver hook.
2346 * In Gallium nomenclature, "surfaces" are a view of a resource that
2347 * can be bound as a render target or depth/stencil buffer.
2349 static struct pipe_surface
*
2350 iris_create_surface(struct pipe_context
*ctx
,
2351 struct pipe_resource
*tex
,
2352 const struct pipe_surface
*tmpl
)
2354 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2355 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2356 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2358 isl_surf_usage_flags_t usage
= 0;
2360 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
2361 else if (util_format_is_depth_or_stencil(tmpl
->format
))
2362 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
2364 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
2366 const struct iris_format_info fmt
=
2367 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
2369 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
2370 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
2371 /* Framebuffer validation will reject this invalid case, but it
2372 * hasn't had the opportunity yet. In the meantime, we need to
2373 * avoid hitting ISL asserts about unsupported formats below.
2378 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
2379 struct pipe_surface
*psurf
= &surf
->base
;
2380 struct iris_resource
*res
= (struct iris_resource
*) tex
;
2385 pipe_reference_init(&psurf
->reference
, 1);
2386 pipe_resource_reference(&psurf
->texture
, tex
);
2387 psurf
->context
= ctx
;
2388 psurf
->format
= tmpl
->format
;
2389 psurf
->width
= tex
->width0
;
2390 psurf
->height
= tex
->height0
;
2391 psurf
->texture
= tex
;
2392 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
2393 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
2394 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
2396 uint32_t array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
2398 struct isl_view
*view
= &surf
->view
;
2399 *view
= (struct isl_view
) {
2401 .base_level
= tmpl
->u
.tex
.level
,
2403 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2404 .array_len
= array_len
,
2405 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2410 enum pipe_texture_target target
= (tex
->target
== PIPE_TEXTURE_3D
&&
2411 array_len
== 1) ? PIPE_TEXTURE_2D
:
2412 tex
->target
== PIPE_TEXTURE_1D_ARRAY
?
2413 PIPE_TEXTURE_2D_ARRAY
: tex
->target
;
2415 struct isl_view
*read_view
= &surf
->read_view
;
2416 *read_view
= (struct isl_view
) {
2418 .base_level
= tmpl
->u
.tex
.level
,
2420 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2421 .array_len
= array_len
,
2422 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2423 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
2427 surf
->clear_color
= res
->aux
.clear_color
;
2429 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
2430 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
2431 ISL_SURF_USAGE_STENCIL_BIT
))
2435 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
2436 &surf
->surface_state
,
2437 res
->aux
.possible_usages
);
2438 if (!unlikely(map
)) {
2439 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2444 void *map_read
= alloc_surface_states(ice
->state
.surface_uploader
,
2445 &surf
->surface_state_read
,
2446 res
->aux
.possible_usages
);
2447 if (!unlikely(map_read
)) {
2448 pipe_resource_reference(&surf
->surface_state_read
.res
, NULL
);
2453 if (!isl_format_is_compressed(res
->surf
.format
)) {
2454 if (iris_resource_unfinished_aux_import(res
))
2455 iris_resource_finish_aux_import(&screen
->base
, res
);
2457 /* This is a normal surface. Fill out a SURFACE_STATE for each possible
2458 * auxiliary surface mode and return the pipe_surface.
2460 unsigned aux_modes
= res
->aux
.possible_usages
;
2463 uint32_t offset
= res
->offset
;
2465 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
2466 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2467 view
, aux_usage
, 0, 0);
2468 map
+= SURFACE_STATE_ALIGNMENT
;
2471 struct isl_surf surf
;
2472 uint32_t tile_x_sa
= 0, tile_y_sa
= 0;
2473 get_rt_read_isl_surf(devinfo
, res
, target
, read_view
,
2474 &tile_x_sa
, &tile_y_sa
, &surf
);
2475 fill_surface_state(&screen
->isl_dev
, map_read
, res
, &surf
, read_view
,
2476 aux_usage
, tile_x_sa
, tile_y_sa
);
2477 /* Restore offset because we change offset in case of handling
2478 * non_coherent fb fetch
2480 res
->offset
= offset
;
2481 map_read
+= SURFACE_STATE_ALIGNMENT
;
2488 /* The resource has a compressed format, which is not renderable, but we
2489 * have a renderable view format. We must be attempting to upload blocks
2490 * of compressed data via an uncompressed view.
2492 * In this case, we can assume there are no auxiliary buffers, a single
2493 * miplevel, and that the resource is single-sampled. Gallium may try
2494 * and create an uncompressed view with multiple layers, however.
2496 assert(!isl_format_is_compressed(fmt
.fmt
));
2497 assert(res
->aux
.possible_usages
== 1 << ISL_AUX_USAGE_NONE
);
2498 assert(res
->surf
.samples
== 1);
2499 assert(view
->levels
== 1);
2501 struct isl_surf isl_surf
;
2502 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
2504 if (view
->base_level
> 0) {
2505 /* We can't rely on the hardware's miplevel selection with such
2506 * a substantial lie about the format, so we select a single image
2507 * using the Tile X/Y Offset fields. In this case, we can't handle
2508 * multiple array slices.
2510 * On Broadwell, HALIGN and VALIGN are specified in pixels and are
2511 * hard-coded to align to exactly the block size of the compressed
2512 * texture. This means that, when reinterpreted as a non-compressed
2513 * texture, the tile offsets may be anything and we can't rely on
2516 * Return NULL to force the state tracker to take fallback paths.
2518 if (view
->array_len
> 1 || GEN_GEN
== 8)
2521 const bool is_3d
= res
->surf
.dim
== ISL_SURF_DIM_3D
;
2522 isl_surf_get_image_surf(&screen
->isl_dev
, &res
->surf
,
2524 is_3d
? 0 : view
->base_array_layer
,
2525 is_3d
? view
->base_array_layer
: 0,
2527 &offset_B
, &tile_x_sa
, &tile_y_sa
);
2529 /* We use address and tile offsets to access a single level/layer
2530 * as a subimage, so reset level/layer so it doesn't offset again.
2532 view
->base_array_layer
= 0;
2533 view
->base_level
= 0;
2535 /* Level 0 doesn't require tile offsets, and the hardware can find
2536 * array slices using QPitch even with the format override, so we
2537 * can allow layers in this case. Copy the original ISL surface.
2539 memcpy(&isl_surf
, &res
->surf
, sizeof(isl_surf
));
2542 /* Scale down the image dimensions by the block size. */
2543 const struct isl_format_layout
*fmtl
=
2544 isl_format_get_layout(res
->surf
.format
);
2545 isl_surf
.format
= fmt
.fmt
;
2546 isl_surf
.logical_level0_px
= isl_surf_get_logical_level0_el(&isl_surf
);
2547 isl_surf
.phys_level0_sa
= isl_surf_get_phys_level0_el(&isl_surf
);
2548 tile_x_sa
/= fmtl
->bw
;
2549 tile_y_sa
/= fmtl
->bh
;
2551 psurf
->width
= isl_surf
.logical_level0_px
.width
;
2552 psurf
->height
= isl_surf
.logical_level0_px
.height
;
2554 struct isl_surf_fill_state_info f
= {
2557 .mocs
= mocs(res
->bo
),
2558 .address
= res
->bo
->gtt_offset
+ offset_B
,
2559 .x_offset_sa
= tile_x_sa
,
2560 .y_offset_sa
= tile_y_sa
,
2563 isl_surf_fill_state_s(&screen
->isl_dev
, map
, &f
);
2569 fill_default_image_param(struct brw_image_param
*param
)
2571 memset(param
, 0, sizeof(*param
));
2572 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
2573 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
2574 * detailed explanation of these parameters.
2576 param
->swizzling
[0] = 0xff;
2577 param
->swizzling
[1] = 0xff;
2581 fill_buffer_image_param(struct brw_image_param
*param
,
2582 enum pipe_format pfmt
,
2585 const unsigned cpp
= util_format_get_blocksize(pfmt
);
2587 fill_default_image_param(param
);
2588 param
->size
[0] = size
/ cpp
;
2589 param
->stride
[0] = cpp
;
2592 #define isl_surf_fill_image_param(x, ...)
2593 #define fill_default_image_param(x, ...)
2594 #define fill_buffer_image_param(x, ...)
2598 * The pipe->set_shader_images() driver hook.
2601 iris_set_shader_images(struct pipe_context
*ctx
,
2602 enum pipe_shader_type p_stage
,
2603 unsigned start_slot
, unsigned count
,
2604 const struct pipe_image_view
*p_images
)
2606 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2607 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2608 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2609 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2610 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2612 struct iris_genx_state
*genx
= ice
->state
.genx
;
2613 struct brw_image_param
*image_params
= genx
->shaders
[stage
].image_param
;
2616 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
2618 for (unsigned i
= 0; i
< count
; i
++) {
2619 struct iris_image_view
*iv
= &shs
->image
[start_slot
+ i
];
2621 if (p_images
&& p_images
[i
].resource
) {
2622 const struct pipe_image_view
*img
= &p_images
[i
];
2623 struct iris_resource
*res
= (void *) img
->resource
;
2626 alloc_surface_states(ice
->state
.surface_uploader
,
2627 &iv
->surface_state
, 1 << ISL_AUX_USAGE_NONE
);
2631 util_copy_image_view(&iv
->base
, img
);
2633 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
2635 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
2636 res
->bind_stages
|= 1 << stage
;
2638 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
2639 enum isl_format isl_fmt
=
2640 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
2642 bool untyped_fallback
= false;
2644 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
2645 /* On Gen8, try to use typed surfaces reads (which support a
2646 * limited number of formats), and if not possible, fall back
2649 untyped_fallback
= GEN_GEN
== 8 &&
2650 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
);
2652 if (untyped_fallback
)
2653 isl_fmt
= ISL_FORMAT_RAW
;
2655 isl_fmt
= isl_lower_storage_image_format(devinfo
, isl_fmt
);
2658 if (res
->base
.target
!= PIPE_BUFFER
) {
2659 struct isl_view view
= {
2661 .base_level
= img
->u
.tex
.level
,
2663 .base_array_layer
= img
->u
.tex
.first_layer
,
2664 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
2665 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2669 if (untyped_fallback
) {
2670 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2671 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2674 /* Images don't support compression */
2675 unsigned aux_modes
= 1 << ISL_AUX_USAGE_NONE
;
2677 enum isl_aux_usage usage
= u_bit_scan(&aux_modes
);
2679 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2680 &view
, usage
, 0, 0);
2682 map
+= SURFACE_STATE_ALIGNMENT
;
2686 isl_surf_fill_image_param(&screen
->isl_dev
,
2687 &image_params
[start_slot
+ i
],
2690 util_range_add(&res
->base
, &res
->valid_buffer_range
, img
->u
.buf
.offset
,
2691 img
->u
.buf
.offset
+ img
->u
.buf
.size
);
2693 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2694 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2695 img
->u
.buf
.offset
, img
->u
.buf
.size
);
2696 fill_buffer_image_param(&image_params
[start_slot
+ i
],
2697 img
->format
, img
->u
.buf
.size
);
2700 pipe_resource_reference(&iv
->base
.resource
, NULL
);
2701 pipe_resource_reference(&iv
->surface_state
.res
, NULL
);
2702 fill_default_image_param(&image_params
[start_slot
+ i
]);
2706 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2708 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2709 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2711 /* Broadwell also needs brw_image_params re-uploaded */
2713 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2714 shs
->sysvals_need_upload
= true;
2720 * The pipe->set_sampler_views() driver hook.
2723 iris_set_sampler_views(struct pipe_context
*ctx
,
2724 enum pipe_shader_type p_stage
,
2725 unsigned start
, unsigned count
,
2726 struct pipe_sampler_view
**views
)
2728 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2729 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2730 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2732 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
2734 for (unsigned i
= 0; i
< count
; i
++) {
2735 struct pipe_sampler_view
*pview
= views
? views
[i
] : NULL
;
2736 pipe_sampler_view_reference((struct pipe_sampler_view
**)
2737 &shs
->textures
[start
+ i
], pview
);
2738 struct iris_sampler_view
*view
= (void *) pview
;
2740 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
2741 view
->res
->bind_stages
|= 1 << stage
;
2743 shs
->bound_sampler_views
|= 1 << (start
+ i
);
2747 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
2749 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2750 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2754 * The pipe->set_tess_state() driver hook.
2757 iris_set_tess_state(struct pipe_context
*ctx
,
2758 const float default_outer_level
[4],
2759 const float default_inner_level
[2])
2761 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2762 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
2764 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
2765 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
2767 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
2768 shs
->sysvals_need_upload
= true;
2772 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
2774 struct iris_surface
*surf
= (void *) p_surf
;
2775 pipe_resource_reference(&p_surf
->texture
, NULL
);
2776 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2777 pipe_resource_reference(&surf
->surface_state_read
.res
, NULL
);
2782 iris_set_clip_state(struct pipe_context
*ctx
,
2783 const struct pipe_clip_state
*state
)
2785 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2786 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
2787 struct iris_shader_state
*gshs
= &ice
->state
.shaders
[MESA_SHADER_GEOMETRY
];
2788 struct iris_shader_state
*tshs
= &ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
];
2790 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
2792 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
| IRIS_DIRTY_CONSTANTS_GS
|
2793 IRIS_DIRTY_CONSTANTS_TES
;
2794 shs
->sysvals_need_upload
= true;
2795 gshs
->sysvals_need_upload
= true;
2796 tshs
->sysvals_need_upload
= true;
2800 * The pipe->set_polygon_stipple() driver hook.
2803 iris_set_polygon_stipple(struct pipe_context
*ctx
,
2804 const struct pipe_poly_stipple
*state
)
2806 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2807 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
2808 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
2812 * The pipe->set_sample_mask() driver hook.
2815 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2817 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2819 /* We only support 16x MSAA, so we have 16 bits of sample maks.
2820 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
2822 ice
->state
.sample_mask
= sample_mask
& 0xffff;
2823 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
2827 * The pipe->set_scissor_states() driver hook.
2829 * This corresponds to our SCISSOR_RECT state structures. It's an
2830 * exact match, so we just store them, and memcpy them out later.
2833 iris_set_scissor_states(struct pipe_context
*ctx
,
2834 unsigned start_slot
,
2835 unsigned num_scissors
,
2836 const struct pipe_scissor_state
*rects
)
2838 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2840 for (unsigned i
= 0; i
< num_scissors
; i
++) {
2841 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
2842 /* If the scissor was out of bounds and got clamped to 0 width/height
2843 * at the bounds, the subtraction of 1 from maximums could produce a
2844 * negative number and thus not clip anything. Instead, just provide
2845 * a min > max scissor inside the bounds, which produces the expected
2848 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2849 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
2852 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2853 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
2854 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
2859 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
2863 * The pipe->set_stencil_ref() driver hook.
2865 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
2868 iris_set_stencil_ref(struct pipe_context
*ctx
,
2869 const struct pipe_stencil_ref
*state
)
2871 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2872 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2874 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2876 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2880 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2882 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2886 * The pipe->set_viewport_states() driver hook.
2888 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2889 * the guardband yet, as we need the framebuffer dimensions, but we can
2890 * at least fill out the rest.
2893 iris_set_viewport_states(struct pipe_context
*ctx
,
2894 unsigned start_slot
,
2896 const struct pipe_viewport_state
*states
)
2898 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2900 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2902 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2904 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2905 !ice
->state
.cso_rast
->depth_clip_far
))
2906 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2910 * The pipe->set_framebuffer_state() driver hook.
2912 * Sets the current draw FBO, including color render targets, depth,
2913 * and stencil buffers.
2916 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2917 const struct pipe_framebuffer_state
*state
)
2919 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2920 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2921 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2922 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2923 struct iris_resource
*zres
;
2924 struct iris_resource
*stencil_res
;
2926 unsigned samples
= util_framebuffer_get_num_samples(state
);
2927 unsigned layers
= util_framebuffer_get_num_layers(state
);
2929 if (cso
->samples
!= samples
) {
2930 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2932 /* We need to toggle 3DSTATE_PS::32 Pixel Dispatch Enable */
2933 if (GEN_GEN
>= 9 && (cso
->samples
== 16 || samples
== 16))
2934 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
2937 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2938 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2941 if ((cso
->layers
== 0) != (layers
== 0)) {
2942 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2945 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2946 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2949 if (cso
->zsbuf
|| state
->zsbuf
) {
2950 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2953 util_copy_framebuffer_state(cso
, state
);
2954 cso
->samples
= samples
;
2955 cso
->layers
= layers
;
2957 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2959 struct isl_view view
= {
2962 .base_array_layer
= 0,
2964 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2967 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
2970 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2973 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2974 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2976 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2979 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2981 info
.depth_surf
= &zres
->surf
;
2982 info
.depth_address
= zres
->bo
->gtt_offset
+ zres
->offset
;
2983 info
.mocs
= mocs(zres
->bo
);
2985 view
.format
= zres
->surf
.format
;
2987 if (iris_resource_level_has_hiz(zres
, view
.base_level
)) {
2988 info
.hiz_usage
= zres
->aux
.usage
;
2989 info
.hiz_surf
= &zres
->aux
.surf
;
2990 info
.hiz_address
= zres
->aux
.bo
->gtt_offset
+ zres
->aux
.offset
;
2995 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2996 info
.stencil_surf
= &stencil_res
->surf
;
2997 info
.stencil_address
= stencil_res
->bo
->gtt_offset
+ stencil_res
->offset
;
2999 view
.format
= stencil_res
->surf
.format
;
3000 info
.mocs
= mocs(stencil_res
->bo
);
3005 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
3007 /* Make a null surface for unbound buffers */
3008 void *null_surf_map
=
3009 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
3010 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
3011 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
3012 isl_extent3d(MAX2(cso
->width
, 1),
3013 MAX2(cso
->height
, 1),
3014 cso
->layers
? cso
->layers
: 1));
3015 ice
->state
.null_fb
.offset
+=
3016 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
3018 /* Render target change */
3019 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
3021 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
3023 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
3026 ice
->state
.dirty
|= IRIS_DIRTY_PMA_FIX
;
3029 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
3030 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
3032 /* The PIPE_CONTROL command description says:
3034 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
3035 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
3036 * Target Cache Flush by enabling this bit. When render target flush
3037 * is set due to new association of BTI, PS Scoreboard Stall bit must
3038 * be set in this packet."
3040 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
3041 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
3042 "workaround: RT BTI change [draw]",
3043 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
3044 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
3049 * The pipe->set_constant_buffer() driver hook.
3051 * This uploads any constant data in user buffers, and references
3052 * any UBO resources containing constant data.
3055 iris_set_constant_buffer(struct pipe_context
*ctx
,
3056 enum pipe_shader_type p_stage
, unsigned index
,
3057 const struct pipe_constant_buffer
*input
)
3059 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3060 gl_shader_stage stage
= stage_from_pipe(p_stage
);
3061 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3062 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[index
];
3064 /* TODO: Only do this if the buffer changes? */
3065 pipe_resource_reference(&shs
->constbuf_surf_state
[index
].res
, NULL
);
3067 if (input
&& input
->buffer_size
&& (input
->buffer
|| input
->user_buffer
)) {
3068 shs
->bound_cbufs
|= 1u << index
;
3070 if (input
->user_buffer
) {
3072 pipe_resource_reference(&cbuf
->buffer
, NULL
);
3073 u_upload_alloc(ice
->ctx
.const_uploader
, 0, input
->buffer_size
, 64,
3074 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
3076 if (!cbuf
->buffer
) {
3077 /* Allocation was unsuccessful - just unbind */
3078 iris_set_constant_buffer(ctx
, p_stage
, index
, NULL
);
3083 memcpy(map
, input
->user_buffer
, input
->buffer_size
);
3084 } else if (input
->buffer
) {
3085 pipe_resource_reference(&cbuf
->buffer
, input
->buffer
);
3087 cbuf
->buffer_offset
= input
->buffer_offset
;
3091 MIN2(input
->buffer_size
,
3092 iris_resource_bo(cbuf
->buffer
)->size
- cbuf
->buffer_offset
);
3094 struct iris_resource
*res
= (void *) cbuf
->buffer
;
3095 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
3096 res
->bind_stages
|= 1 << stage
;
3098 shs
->bound_cbufs
&= ~(1u << index
);
3099 pipe_resource_reference(&cbuf
->buffer
, NULL
);
3102 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
3106 upload_sysvals(struct iris_context
*ice
,
3107 gl_shader_stage stage
)
3109 UNUSED
struct iris_genx_state
*genx
= ice
->state
.genx
;
3110 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3112 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3113 if (!shader
|| shader
->num_system_values
== 0)
3116 assert(shader
->num_cbufs
> 0);
3118 unsigned sysval_cbuf_index
= shader
->num_cbufs
- 1;
3119 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[sysval_cbuf_index
];
3120 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t);
3121 uint32_t *map
= NULL
;
3123 assert(sysval_cbuf_index
< PIPE_MAX_CONSTANT_BUFFERS
);
3124 u_upload_alloc(ice
->ctx
.const_uploader
, 0, upload_size
, 64,
3125 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
3127 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
3128 uint32_t sysval
= shader
->system_values
[i
];
3131 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
3133 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
3134 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
3135 struct brw_image_param
*param
=
3136 &genx
->shaders
[stage
].image_param
[img
];
3138 assert(offset
< sizeof(struct brw_image_param
));
3139 value
= ((uint32_t *) param
)[offset
];
3141 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
3143 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
3144 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
3145 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
3146 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
3147 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
3148 if (stage
== MESA_SHADER_TESS_CTRL
) {
3149 value
= ice
->state
.vertices_per_patch
;
3151 assert(stage
== MESA_SHADER_TESS_EVAL
);
3152 const struct shader_info
*tcs_info
=
3153 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
3155 value
= tcs_info
->tess
.tcs_vertices_out
;
3157 value
= ice
->state
.vertices_per_patch
;
3159 } else if (sysval
>= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
&&
3160 sysval
<= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
) {
3161 unsigned i
= sysval
- BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
3162 value
= fui(ice
->state
.default_outer_level
[i
]);
3163 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
) {
3164 value
= fui(ice
->state
.default_inner_level
[0]);
3165 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
) {
3166 value
= fui(ice
->state
.default_inner_level
[1]);
3168 assert(!"unhandled system value");
3174 cbuf
->buffer_size
= upload_size
;
3175 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
3176 &shs
->constbuf_surf_state
[sysval_cbuf_index
], false);
3178 shs
->sysvals_need_upload
= false;
3182 * The pipe->set_shader_buffers() driver hook.
3184 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
3185 * SURFACE_STATE here, as the buffer offset may change each time.
3188 iris_set_shader_buffers(struct pipe_context
*ctx
,
3189 enum pipe_shader_type p_stage
,
3190 unsigned start_slot
, unsigned count
,
3191 const struct pipe_shader_buffer
*buffers
,
3192 unsigned writable_bitmask
)
3194 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3195 gl_shader_stage stage
= stage_from_pipe(p_stage
);
3196 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3198 unsigned modified_bits
= u_bit_consecutive(start_slot
, count
);
3200 shs
->bound_ssbos
&= ~modified_bits
;
3201 shs
->writable_ssbos
&= ~modified_bits
;
3202 shs
->writable_ssbos
|= writable_bitmask
<< start_slot
;
3204 for (unsigned i
= 0; i
< count
; i
++) {
3205 if (buffers
&& buffers
[i
].buffer
) {
3206 struct iris_resource
*res
= (void *) buffers
[i
].buffer
;
3207 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[start_slot
+ i
];
3208 struct iris_state_ref
*surf_state
=
3209 &shs
->ssbo_surf_state
[start_slot
+ i
];
3210 pipe_resource_reference(&ssbo
->buffer
, &res
->base
);
3211 ssbo
->buffer_offset
= buffers
[i
].buffer_offset
;
3213 MIN2(buffers
[i
].buffer_size
, res
->bo
->size
- ssbo
->buffer_offset
);
3215 shs
->bound_ssbos
|= 1 << (start_slot
+ i
);
3217 iris_upload_ubo_ssbo_surf_state(ice
, ssbo
, surf_state
, true);
3219 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
3220 res
->bind_stages
|= 1 << stage
;
3222 util_range_add(&res
->base
, &res
->valid_buffer_range
, ssbo
->buffer_offset
,
3223 ssbo
->buffer_offset
+ ssbo
->buffer_size
);
3225 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
].buffer
, NULL
);
3226 pipe_resource_reference(&shs
->ssbo_surf_state
[start_slot
+ i
].res
,
3231 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
3235 iris_delete_state(struct pipe_context
*ctx
, void *state
)
3241 * The pipe->set_vertex_buffers() driver hook.
3243 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
3246 iris_set_vertex_buffers(struct pipe_context
*ctx
,
3247 unsigned start_slot
, unsigned count
,
3248 const struct pipe_vertex_buffer
*buffers
)
3250 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3251 struct iris_genx_state
*genx
= ice
->state
.genx
;
3253 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
3255 for (unsigned i
= 0; i
< count
; i
++) {
3256 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
3257 struct iris_vertex_buffer_state
*state
=
3258 &genx
->vertex_buffers
[start_slot
+ i
];
3261 pipe_resource_reference(&state
->resource
, NULL
);
3265 /* We may see user buffers that are NULL bindings. */
3266 assert(!(buffer
->is_user_buffer
&& buffer
->buffer
.user
!= NULL
));
3268 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
3269 struct iris_resource
*res
= (void *) state
->resource
;
3271 state
->offset
= (int) buffer
->buffer_offset
;
3274 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
3275 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
3278 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
3279 vb
.VertexBufferIndex
= start_slot
+ i
;
3280 vb
.AddressModifyEnable
= true;
3281 vb
.BufferPitch
= buffer
->stride
;
3283 vb
.BufferSize
= res
->bo
->size
- (int) buffer
->buffer_offset
;
3284 vb
.BufferStartingAddress
=
3285 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
3286 vb
.MOCS
= mocs(res
->bo
);
3288 vb
.NullVertexBuffer
= true;
3293 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
3297 * Gallium CSO for vertex elements.
3299 struct iris_vertex_element_state
{
3300 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
3301 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
3302 uint32_t edgeflag_ve
[GENX(VERTEX_ELEMENT_STATE_length
)];
3303 uint32_t edgeflag_vfi
[GENX(3DSTATE_VF_INSTANCING_length
)];
3308 * The pipe->create_vertex_elements() driver hook.
3310 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
3311 * and 3DSTATE_VF_INSTANCING commands. The vertex_elements and vf_instancing
3312 * arrays are ready to be emitted at draw time if no EdgeFlag or SGVs are
3313 * needed. In these cases we will need information available at draw time.
3314 * We setup edgeflag_ve and edgeflag_vfi as alternatives last
3315 * 3DSTATE_VERTEX_ELEMENT and 3DSTATE_VF_INSTANCING that can be used at
3316 * draw time if we detect that EdgeFlag is needed by the Vertex Shader.
3319 iris_create_vertex_elements(struct pipe_context
*ctx
,
3321 const struct pipe_vertex_element
*state
)
3323 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
3324 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3325 struct iris_vertex_element_state
*cso
=
3326 malloc(sizeof(struct iris_vertex_element_state
));
3330 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
3332 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
3335 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
3336 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
3339 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
3341 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
3342 ve
.Component0Control
= VFCOMP_STORE_0
;
3343 ve
.Component1Control
= VFCOMP_STORE_0
;
3344 ve
.Component2Control
= VFCOMP_STORE_0
;
3345 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
3348 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
3352 for (int i
= 0; i
< count
; i
++) {
3353 const struct iris_format_info fmt
=
3354 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
3355 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
3356 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
3358 switch (isl_format_get_num_channels(fmt
.fmt
)) {
3359 case 0: comp
[0] = VFCOMP_STORE_0
; /* fallthrough */
3360 case 1: comp
[1] = VFCOMP_STORE_0
; /* fallthrough */
3361 case 2: comp
[2] = VFCOMP_STORE_0
; /* fallthrough */
3363 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
3364 : VFCOMP_STORE_1_FP
;
3367 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
3368 ve
.EdgeFlagEnable
= false;
3369 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
3371 ve
.SourceElementOffset
= state
[i
].src_offset
;
3372 ve
.SourceElementFormat
= fmt
.fmt
;
3373 ve
.Component0Control
= comp
[0];
3374 ve
.Component1Control
= comp
[1];
3375 ve
.Component2Control
= comp
[2];
3376 ve
.Component3Control
= comp
[3];
3379 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
3380 vi
.VertexElementIndex
= i
;
3381 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
3382 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
3385 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
3386 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
3389 /* An alternative version of the last VE and VFI is stored so it
3390 * can be used at draw time in case Vertex Shader uses EdgeFlag
3393 const unsigned edgeflag_index
= count
- 1;
3394 const struct iris_format_info fmt
=
3395 iris_format_for_usage(devinfo
, state
[edgeflag_index
].src_format
, 0);
3396 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), cso
->edgeflag_ve
, ve
) {
3397 ve
.EdgeFlagEnable
= true ;
3398 ve
.VertexBufferIndex
= state
[edgeflag_index
].vertex_buffer_index
;
3400 ve
.SourceElementOffset
= state
[edgeflag_index
].src_offset
;
3401 ve
.SourceElementFormat
= fmt
.fmt
;
3402 ve
.Component0Control
= VFCOMP_STORE_SRC
;
3403 ve
.Component1Control
= VFCOMP_STORE_0
;
3404 ve
.Component2Control
= VFCOMP_STORE_0
;
3405 ve
.Component3Control
= VFCOMP_STORE_0
;
3407 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->edgeflag_vfi
, vi
) {
3408 /* The vi.VertexElementIndex of the EdgeFlag Vertex Element is filled
3409 * at draw time, as it should change if SGVs are emitted.
3411 vi
.InstancingEnable
= state
[edgeflag_index
].instance_divisor
> 0;
3412 vi
.InstanceDataStepRate
= state
[edgeflag_index
].instance_divisor
;
3420 * The pipe->bind_vertex_elements_state() driver hook.
3423 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
3425 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3426 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
3427 struct iris_vertex_element_state
*new_cso
= state
;
3429 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
3430 * we need to re-emit it to ensure we're overriding the right one.
3432 if (new_cso
&& cso_changed(count
))
3433 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
3435 ice
->state
.cso_vertex_elements
= state
;
3436 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
3440 * The pipe->create_stream_output_target() driver hook.
3442 * "Target" here refers to a destination buffer. We translate this into
3443 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
3444 * know which buffer this represents, or whether we ought to zero the
3445 * write-offsets, or append. Those are handled in the set() hook.
3447 static struct pipe_stream_output_target
*
3448 iris_create_stream_output_target(struct pipe_context
*ctx
,
3449 struct pipe_resource
*p_res
,
3450 unsigned buffer_offset
,
3451 unsigned buffer_size
)
3453 struct iris_resource
*res
= (void *) p_res
;
3454 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
3458 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
3460 pipe_reference_init(&cso
->base
.reference
, 1);
3461 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
3462 cso
->base
.buffer_offset
= buffer_offset
;
3463 cso
->base
.buffer_size
= buffer_size
;
3464 cso
->base
.context
= ctx
;
3466 util_range_add(&res
->base
, &res
->valid_buffer_range
, buffer_offset
,
3467 buffer_offset
+ buffer_size
);
3469 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
3475 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
3476 struct pipe_stream_output_target
*state
)
3478 struct iris_stream_output_target
*cso
= (void *) state
;
3480 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
3481 pipe_resource_reference(&cso
->offset
.res
, NULL
);
3487 * The pipe->set_stream_output_targets() driver hook.
3489 * At this point, we know which targets are bound to a particular index,
3490 * and also whether we want to append or start over. We can finish the
3491 * 3DSTATE_SO_BUFFER packets we started earlier.
3494 iris_set_stream_output_targets(struct pipe_context
*ctx
,
3495 unsigned num_targets
,
3496 struct pipe_stream_output_target
**targets
,
3497 const unsigned *offsets
)
3499 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3500 struct iris_genx_state
*genx
= ice
->state
.genx
;
3501 uint32_t *so_buffers
= genx
->so_buffers
;
3503 const bool active
= num_targets
> 0;
3504 if (ice
->state
.streamout_active
!= active
) {
3505 ice
->state
.streamout_active
= active
;
3506 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
3508 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
3509 * it's a non-pipelined command. If we're switching streamout on, we
3510 * may have missed emitting it earlier, so do so now. (We're already
3511 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
3514 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
3517 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3518 struct iris_stream_output_target
*tgt
=
3519 (void *) ice
->state
.so_target
[i
];
3521 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3523 flush
|= iris_flush_bits_for_history(res
);
3524 iris_dirty_for_history(ice
, res
);
3527 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
3528 "make streamout results visible", flush
);
3532 for (int i
= 0; i
< 4; i
++) {
3533 pipe_so_target_reference(&ice
->state
.so_target
[i
],
3534 i
< num_targets
? targets
[i
] : NULL
);
3537 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
3541 for (unsigned i
= 0; i
< 4; i
++,
3542 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
3544 struct iris_stream_output_target
*tgt
= (void *) ice
->state
.so_target
[i
];
3545 unsigned offset
= offsets
[i
];
3548 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
3549 sob
.SOBufferIndex
= i
;
3553 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3555 /* Note that offsets[i] will either be 0, causing us to zero
3556 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
3557 * "continue appending at the existing offset."
3559 assert(offset
== 0 || offset
== 0xFFFFFFFF);
3561 /* We might be called by Begin (offset = 0), Pause, then Resume
3562 * (offset = 0xFFFFFFFF) before ever drawing (where these commands
3563 * will actually be sent to the GPU). In this case, we don't want
3564 * to append - we still want to do our initial zeroing.
3569 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
3570 sob
.SurfaceBaseAddress
=
3571 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
3572 sob
.SOBufferEnable
= true;
3573 sob
.StreamOffsetWriteEnable
= true;
3574 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3575 sob
.MOCS
= mocs(res
->bo
);
3577 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
3579 sob
.SOBufferIndex
= i
;
3580 sob
.StreamOffset
= offset
;
3581 sob
.StreamOutputBufferOffsetAddress
=
3582 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
3583 tgt
->offset
.offset
);
3587 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
3591 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
3592 * 3DSTATE_STREAMOUT packets.
3594 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
3595 * hardware to record. We can create it entirely based on the shader, with
3596 * no dynamic state dependencies.
3598 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
3599 * state-based settings. We capture the shader-related ones here, and merge
3600 * the rest in at draw time.
3603 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
3604 const struct brw_vue_map
*vue_map
)
3606 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3607 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3608 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3609 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3611 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3613 memset(so_decl
, 0, sizeof(so_decl
));
3615 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3616 * command feels strange -- each dword pair contains a SO_DECL per stream.
3618 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
3619 const struct pipe_stream_output
*output
= &info
->output
[i
];
3620 const int buffer
= output
->output_buffer
;
3621 const int varying
= output
->register_index
;
3622 const unsigned stream_id
= output
->stream
;
3623 assert(stream_id
< MAX_VERTEX_STREAMS
);
3625 buffer_mask
[stream_id
] |= 1 << buffer
;
3627 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3629 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3630 * array. Instead, it simply increments DstOffset for the following
3631 * input by the number of components that should be skipped.
3633 * Our hardware is unusual in that it requires us to program SO_DECLs
3634 * for fake "hole" components, rather than simply taking the offset
3635 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3636 * program as many size = 4 holes as we can, then a final hole to
3637 * accommodate the final 1, 2, or 3 remaining.
3639 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
3641 while (skip_components
> 0) {
3642 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3644 .OutputBufferSlot
= output
->output_buffer
,
3645 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3647 skip_components
-= 4;
3650 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
3652 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3653 .OutputBufferSlot
= output
->output_buffer
,
3654 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3656 ((1 << output
->num_components
) - 1) << output
->start_component
,
3659 if (decls
[stream_id
] > max_decls
)
3660 max_decls
= decls
[stream_id
];
3663 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
3664 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
3665 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
3667 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
3668 int urb_entry_read_offset
= 0;
3669 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3670 urb_entry_read_offset
;
3672 /* We always read the whole vertex. This could be reduced at some
3673 * point by reading less and offsetting the register index in the
3676 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3677 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3678 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3679 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3680 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3681 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3682 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3683 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3685 /* Set buffer pitches; 0 means unbound. */
3686 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
3687 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
3688 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
3689 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
3692 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
3693 list
.DWordLength
= 3 + 2 * max_decls
- 2;
3694 list
.StreamtoBufferSelects0
= buffer_mask
[0];
3695 list
.StreamtoBufferSelects1
= buffer_mask
[1];
3696 list
.StreamtoBufferSelects2
= buffer_mask
[2];
3697 list
.StreamtoBufferSelects3
= buffer_mask
[3];
3698 list
.NumEntries0
= decls
[0];
3699 list
.NumEntries1
= decls
[1];
3700 list
.NumEntries2
= decls
[2];
3701 list
.NumEntries3
= decls
[3];
3704 for (int i
= 0; i
< max_decls
; i
++) {
3705 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
3706 entry
.Stream0Decl
= so_decl
[0][i
];
3707 entry
.Stream1Decl
= so_decl
[1][i
];
3708 entry
.Stream2Decl
= so_decl
[2][i
];
3709 entry
.Stream3Decl
= so_decl
[3][i
];
3717 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
3718 const struct brw_vue_map
*last_vue_map
,
3719 bool two_sided_color
,
3720 unsigned *out_offset
,
3721 unsigned *out_length
)
3723 /* The compiler computes the first URB slot without considering COL/BFC
3724 * swizzling (because it doesn't know whether it's enabled), so we need
3725 * to do that here too. This may result in a smaller offset, which
3728 const unsigned first_slot
=
3729 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
3731 /* This becomes the URB read offset (counted in pairs of slots). */
3732 assert(first_slot
% 2 == 0);
3733 *out_offset
= first_slot
/ 2;
3735 /* We need to adjust the inputs read to account for front/back color
3736 * swizzling, as it can make the URB length longer.
3738 for (int c
= 0; c
<= 1; c
++) {
3739 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
3740 /* If two sided color is enabled, the fragment shader's gl_Color
3741 * (COL0) input comes from either the gl_FrontColor (COL0) or
3742 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
3744 if (two_sided_color
)
3745 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3747 /* If front color isn't written, we opt to give them back color
3748 * instead of an undefined value. Switch from COL to BFC.
3750 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
3751 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
3752 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3757 /* Compute the minimum URB Read Length necessary for the FS inputs.
3759 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
3760 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
3762 * "This field should be set to the minimum length required to read the
3763 * maximum source attribute. The maximum source attribute is indicated
3764 * by the maximum value of the enabled Attribute # Source Attribute if
3765 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
3766 * enable is not set.
3767 * read_length = ceiling((max_source_attr + 1) / 2)
3769 * [errata] Corruption/Hang possible if length programmed larger than
3772 * Similar text exists for Ivy Bridge.
3774 * We find the last URB slot that's actually read by the FS.
3776 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
3777 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
3778 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
3781 /* The URB read length is the difference of the two, counted in pairs. */
3782 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
3786 iris_emit_sbe_swiz(struct iris_batch
*batch
,
3787 const struct iris_context
*ice
,
3788 unsigned urb_read_offset
,
3789 unsigned sprite_coord_enables
)
3791 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
3792 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3793 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3794 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
3795 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3797 /* XXX: this should be generated when putting programs in place */
3799 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
3800 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
3801 if (input_index
< 0 || input_index
>= 16)
3804 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
3805 &attr_overrides
[input_index
];
3806 int slot
= vue_map
->varying_to_slot
[fs_attr
];
3808 /* Viewport and Layer are stored in the VUE header. We need to override
3809 * them to zero if earlier stages didn't write them, as GL requires that
3810 * they read back as zero when not explicitly set.
3813 case VARYING_SLOT_VIEWPORT
:
3814 case VARYING_SLOT_LAYER
:
3815 attr
->ComponentOverrideX
= true;
3816 attr
->ComponentOverrideW
= true;
3817 attr
->ConstantSource
= CONST_0000
;
3819 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
3820 attr
->ComponentOverrideY
= true;
3821 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
3822 attr
->ComponentOverrideZ
= true;
3825 case VARYING_SLOT_PRIMITIVE_ID
:
3826 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
3828 attr
->ComponentOverrideX
= true;
3829 attr
->ComponentOverrideY
= true;
3830 attr
->ComponentOverrideZ
= true;
3831 attr
->ComponentOverrideW
= true;
3832 attr
->ConstantSource
= PRIM_ID
;
3840 if (sprite_coord_enables
& (1 << input_index
))
3843 /* If there was only a back color written but not front, use back
3844 * as the color instead of undefined.
3846 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
3847 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
3848 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
3849 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
3851 /* Not written by the previous stage - undefined. */
3853 attr
->ComponentOverrideX
= true;
3854 attr
->ComponentOverrideY
= true;
3855 attr
->ComponentOverrideZ
= true;
3856 attr
->ComponentOverrideW
= true;
3857 attr
->ConstantSource
= CONST_0001_FLOAT
;
3861 /* Compute the location of the attribute relative to the read offset,
3862 * which is counted in 256-bit increments (two 128-bit VUE slots).
3864 const int source_attr
= slot
- 2 * urb_read_offset
;
3865 assert(source_attr
>= 0 && source_attr
<= 32);
3866 attr
->SourceAttribute
= source_attr
;
3868 /* If we are doing two-sided color, and the VUE slot following this one
3869 * represents a back-facing color, then we need to instruct the SF unit
3870 * to do back-facing swizzling.
3872 if (cso_rast
->light_twoside
&&
3873 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3874 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3875 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3876 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3877 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3880 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3881 for (int i
= 0; i
< 16; i
++)
3882 sbes
.Attribute
[i
] = attr_overrides
[i
];
3887 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3888 const struct iris_rasterizer_state
*cso
)
3890 unsigned overrides
= 0;
3892 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
3893 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
3895 for (int i
= 0; i
< 8; i
++) {
3896 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
3897 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
3898 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
3905 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
3907 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3908 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3909 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3910 const struct shader_info
*fs_info
=
3911 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
3913 unsigned urb_read_offset
, urb_read_length
;
3914 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
3915 ice
->shaders
.last_vue_map
,
3916 cso_rast
->light_twoside
,
3917 &urb_read_offset
, &urb_read_length
);
3919 unsigned sprite_coord_overrides
=
3920 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3922 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
3923 sbe
.AttributeSwizzleEnable
= true;
3924 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3925 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3926 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3927 sbe
.VertexURBEntryReadLength
= urb_read_length
;
3928 sbe
.ForceVertexURBEntryReadOffset
= true;
3929 sbe
.ForceVertexURBEntryReadLength
= true;
3930 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3931 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
3933 for (int i
= 0; i
< 32; i
++) {
3934 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3939 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
3942 /* ------------------------------------------------------------------- */
3945 * Populate VS program key fields based on the current state.
3948 iris_populate_vs_key(const struct iris_context
*ice
,
3949 const struct shader_info
*info
,
3950 gl_shader_stage last_stage
,
3951 struct brw_vs_prog_key
*key
)
3953 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3955 if (info
->clip_distance_array_size
== 0 &&
3956 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
3957 last_stage
== MESA_SHADER_VERTEX
)
3958 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3962 * Populate TCS program key fields based on the current state.
3965 iris_populate_tcs_key(const struct iris_context
*ice
,
3966 struct brw_tcs_prog_key
*key
)
3971 * Populate TES program key fields based on the current state.
3974 iris_populate_tes_key(const struct iris_context
*ice
,
3975 const struct shader_info
*info
,
3976 gl_shader_stage last_stage
,
3977 struct brw_tes_prog_key
*key
)
3979 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3981 if (info
->clip_distance_array_size
== 0 &&
3982 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
3983 last_stage
== MESA_SHADER_TESS_EVAL
)
3984 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3988 * Populate GS program key fields based on the current state.
3991 iris_populate_gs_key(const struct iris_context
*ice
,
3992 const struct shader_info
*info
,
3993 gl_shader_stage last_stage
,
3994 struct brw_gs_prog_key
*key
)
3996 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3998 if (info
->clip_distance_array_size
== 0 &&
3999 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
4000 last_stage
== MESA_SHADER_GEOMETRY
)
4001 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
4005 * Populate FS program key fields based on the current state.
4008 iris_populate_fs_key(const struct iris_context
*ice
,
4009 const struct shader_info
*info
,
4010 struct brw_wm_prog_key
*key
)
4012 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
4013 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
4014 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
4015 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
4016 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
4018 key
->nr_color_regions
= fb
->nr_cbufs
;
4020 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
4022 key
->alpha_to_coverage
= blend
->alpha_to_coverage
;
4024 key
->alpha_test_replicate_alpha
= fb
->nr_cbufs
> 1 && zsa
->alpha
.enabled
;
4026 key
->flat_shade
= rast
->flatshade
&&
4027 (info
->inputs_read
& (VARYING_BIT_COL0
| VARYING_BIT_COL1
));
4029 key
->persample_interp
= rast
->force_persample_interp
;
4030 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
4032 key
->coherent_fb_fetch
= GEN_GEN
>= 9;
4034 key
->force_dual_color_blend
=
4035 screen
->driconf
.dual_color_blend_by_location
&&
4036 (blend
->blend_enables
& 1) && blend
->dual_color_blending
;
4038 /* TODO: Respect glHint for key->high_quality_derivatives */
4042 iris_populate_cs_key(const struct iris_context
*ice
,
4043 struct brw_cs_prog_key
*key
)
4048 KSP(const struct iris_compiled_shader
*shader
)
4050 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
4051 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
4054 /* Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
4055 * prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
4056 * this WA on C0 stepping.
4058 * TODO: Fill out SamplerCount for prefetching?
4061 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
4062 pkt.KernelStartPointer = KSP(shader); \
4063 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
4064 shader->bt.size_bytes / 4; \
4065 pkt.FloatingPointMode = prog_data->use_alt_mode; \
4067 pkt.DispatchGRFStartRegisterForURBData = \
4068 prog_data->dispatch_grf_start_reg; \
4069 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
4070 pkt.prefix##URBEntryReadOffset = 0; \
4072 pkt.StatisticsEnable = true; \
4073 pkt.Enable = true; \
4075 if (prog_data->total_scratch) { \
4076 struct iris_bo *bo = \
4077 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
4078 uint32_t scratch_addr = bo->gtt_offset; \
4079 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
4080 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
4084 * Encode most of 3DSTATE_VS based on the compiled shader.
4087 iris_store_vs_state(struct iris_context
*ice
,
4088 const struct gen_device_info
*devinfo
,
4089 struct iris_compiled_shader
*shader
)
4091 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4092 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4094 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
4095 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
4096 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
4097 vs
.SIMD8DispatchEnable
= true;
4098 vs
.UserClipDistanceCullTestEnableBitmask
=
4099 vue_prog_data
->cull_distance_mask
;
4104 * Encode most of 3DSTATE_HS based on the compiled shader.
4107 iris_store_tcs_state(struct iris_context
*ice
,
4108 const struct gen_device_info
*devinfo
,
4109 struct iris_compiled_shader
*shader
)
4111 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4112 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4113 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
4115 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
4116 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
4118 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
4119 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
4120 hs
.IncludeVertexHandles
= true;
4123 hs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
4124 hs
.IncludePrimitiveID
= tcs_prog_data
->include_primitive_id
;
4130 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
4133 iris_store_tes_state(struct iris_context
*ice
,
4134 const struct gen_device_info
*devinfo
,
4135 struct iris_compiled_shader
*shader
)
4137 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4138 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4139 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
4141 uint32_t *te_state
= (void *) shader
->derived_data
;
4142 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
4144 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
4145 te
.Partitioning
= tes_prog_data
->partitioning
;
4146 te
.OutputTopology
= tes_prog_data
->output_topology
;
4147 te
.TEDomain
= tes_prog_data
->domain
;
4149 te
.MaximumTessellationFactorOdd
= 63.0;
4150 te
.MaximumTessellationFactorNotOdd
= 64.0;
4153 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
4154 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
4156 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
4157 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
4158 ds
.ComputeWCoordinateEnable
=
4159 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
4161 ds
.UserClipDistanceCullTestEnableBitmask
=
4162 vue_prog_data
->cull_distance_mask
;
4168 * Encode most of 3DSTATE_GS based on the compiled shader.
4171 iris_store_gs_state(struct iris_context
*ice
,
4172 const struct gen_device_info
*devinfo
,
4173 struct iris_compiled_shader
*shader
)
4175 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4176 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4177 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
4179 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
4180 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
4182 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
4183 gs
.OutputTopology
= gs_prog_data
->output_topology
;
4184 gs
.ControlDataHeaderSize
=
4185 gs_prog_data
->control_data_header_size_hwords
;
4186 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
4187 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
4188 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
4189 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
4190 gs
.ReorderMode
= TRAILING
;
4191 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
4192 gs
.MaximumNumberofThreads
=
4193 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
4194 : (devinfo
->max_gs_threads
- 1);
4196 if (gs_prog_data
->static_vertex_count
!= -1) {
4197 gs
.StaticOutput
= true;
4198 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
4200 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
4202 gs
.UserClipDistanceCullTestEnableBitmask
=
4203 vue_prog_data
->cull_distance_mask
;
4205 const int urb_entry_write_offset
= 1;
4206 const uint32_t urb_entry_output_length
=
4207 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
4208 urb_entry_write_offset
;
4210 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
4211 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
4216 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
4219 iris_store_fs_state(struct iris_context
*ice
,
4220 const struct gen_device_info
*devinfo
,
4221 struct iris_compiled_shader
*shader
)
4223 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4224 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
4226 uint32_t *ps_state
= (void *) shader
->derived_data
;
4227 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
4229 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
4230 ps
.VectorMaskEnable
= true;
4231 // XXX: WABTPPrefetchDisable, see above, drop at C0
4232 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
4233 shader
->bt
.size_bytes
/ 4;
4234 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
4235 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
4237 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
4239 /* From the documentation for this packet:
4240 * "If the PS kernel does not need the Position XY Offsets to
4241 * compute a Position Value, then this field should be programmed
4242 * to POSOFFSET_NONE."
4244 * "SW Recommendation: If the PS kernel needs the Position Offsets
4245 * to compute a Position XY value, this field should match Position
4246 * ZW Interpolation Mode to ensure a consistent position.xyzw
4249 * We only require XY sample offsets. So, this recommendation doesn't
4250 * look useful at the moment. We might need this in future.
4252 ps
.PositionXYOffsetSelect
=
4253 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
4255 if (prog_data
->total_scratch
) {
4256 struct iris_bo
*bo
=
4257 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
4258 MESA_SHADER_FRAGMENT
);
4259 uint32_t scratch_addr
= bo
->gtt_offset
;
4260 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
4261 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
4265 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
4266 psx
.PixelShaderValid
= true;
4267 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
4268 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
4269 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
4270 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
4271 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
4272 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
4273 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
4276 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
4277 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
4283 * Compute the size of the derived data (shader command packets).
4285 * This must match the data written by the iris_store_xs_state() functions.
4288 iris_store_cs_state(struct iris_context
*ice
,
4289 const struct gen_device_info
*devinfo
,
4290 struct iris_compiled_shader
*shader
)
4292 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4293 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
4294 void *map
= shader
->derived_data
;
4296 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
4297 desc
.KernelStartPointer
= KSP(shader
);
4298 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
4299 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
4300 desc
.SharedLocalMemorySize
=
4301 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
4302 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
4303 desc
.CrossThreadConstantDataReadLength
=
4304 cs_prog_data
->push
.cross_thread
.regs
;
4309 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
4311 assert(cache_id
<= IRIS_CACHE_BLORP
);
4313 static const unsigned dwords
[] = {
4314 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
4315 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
4316 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
4317 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
4319 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
4320 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
4321 [IRIS_CACHE_BLORP
] = 0,
4324 return sizeof(uint32_t) * dwords
[cache_id
];
4328 * Create any state packets corresponding to the given shader stage
4329 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
4330 * This means that we can look up a program in the in-memory cache and
4331 * get most of the state packet without having to reconstruct it.
4334 iris_store_derived_program_state(struct iris_context
*ice
,
4335 enum iris_program_cache_id cache_id
,
4336 struct iris_compiled_shader
*shader
)
4338 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
4339 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
4343 iris_store_vs_state(ice
, devinfo
, shader
);
4345 case IRIS_CACHE_TCS
:
4346 iris_store_tcs_state(ice
, devinfo
, shader
);
4348 case IRIS_CACHE_TES
:
4349 iris_store_tes_state(ice
, devinfo
, shader
);
4352 iris_store_gs_state(ice
, devinfo
, shader
);
4355 iris_store_fs_state(ice
, devinfo
, shader
);
4358 iris_store_cs_state(ice
, devinfo
, shader
);
4359 case IRIS_CACHE_BLORP
:
4366 /* ------------------------------------------------------------------- */
4368 static const uint32_t push_constant_opcodes
[] = {
4369 [MESA_SHADER_VERTEX
] = 21,
4370 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
4371 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
4372 [MESA_SHADER_GEOMETRY
] = 22,
4373 [MESA_SHADER_FRAGMENT
] = 23,
4374 [MESA_SHADER_COMPUTE
] = 0,
4378 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
4380 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
4382 iris_use_pinned_bo(batch
, state_bo
, false);
4384 return ice
->state
.unbound_tex
.offset
;
4388 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
4390 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
4391 if (!ice
->state
.null_fb
.res
)
4392 return use_null_surface(batch
, ice
);
4394 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
4396 iris_use_pinned_bo(batch
, state_bo
, false);
4398 return ice
->state
.null_fb
.offset
;
4402 surf_state_offset_for_aux(struct iris_resource
*res
,
4404 enum isl_aux_usage aux_usage
)
4406 return SURFACE_STATE_ALIGNMENT
*
4407 util_bitcount(aux_modes
& ((1 << aux_usage
) - 1));
4412 surf_state_update_clear_value(struct iris_batch
*batch
,
4413 struct iris_resource
*res
,
4414 struct iris_state_ref
*state
,
4416 enum isl_aux_usage aux_usage
)
4418 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
4419 struct iris_bo
*state_bo
= iris_resource_bo(state
->res
);
4420 uint64_t real_offset
= state
->offset
+ IRIS_MEMZONE_BINDER_START
;
4421 uint32_t offset_into_bo
= real_offset
- state_bo
->gtt_offset
;
4422 uint32_t clear_offset
= offset_into_bo
+
4423 isl_dev
->ss
.clear_value_offset
+
4424 surf_state_offset_for_aux(res
, aux_modes
, aux_usage
);
4425 uint32_t *color
= res
->aux
.clear_color
.u32
;
4427 assert(isl_dev
->ss
.clear_value_size
== 16);
4429 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
4430 iris_emit_pipe_control_write(batch
, "update fast clear value (Z)",
4431 PIPE_CONTROL_WRITE_IMMEDIATE
,
4432 state_bo
, clear_offset
, color
[0]);
4434 iris_emit_pipe_control_write(batch
, "update fast clear color (RG__)",
4435 PIPE_CONTROL_WRITE_IMMEDIATE
,
4436 state_bo
, clear_offset
,
4437 (uint64_t) color
[0] |
4438 (uint64_t) color
[1] << 32);
4439 iris_emit_pipe_control_write(batch
, "update fast clear color (__BA)",
4440 PIPE_CONTROL_WRITE_IMMEDIATE
,
4441 state_bo
, clear_offset
+ 8,
4442 (uint64_t) color
[2] |
4443 (uint64_t) color
[3] << 32);
4446 iris_emit_pipe_control_flush(batch
,
4447 "update fast clear: state cache invalidate",
4448 PIPE_CONTROL_FLUSH_ENABLE
|
4449 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
4454 update_clear_value(struct iris_context
*ice
,
4455 struct iris_batch
*batch
,
4456 struct iris_resource
*res
,
4457 struct iris_state_ref
*state
,
4458 unsigned all_aux_modes
,
4459 struct isl_view
*view
)
4461 UNUSED
struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
4462 UNUSED
unsigned aux_modes
= all_aux_modes
;
4464 /* We only need to update the clear color in the surface state for gen8 and
4465 * gen9. Newer gens can read it directly from the clear color state buffer.
4468 /* Skip updating the ISL_AUX_USAGE_NONE surface state */
4469 aux_modes
&= ~(1 << ISL_AUX_USAGE_NONE
);
4472 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4474 surf_state_update_clear_value(batch
, res
, state
, all_aux_modes
,
4478 pipe_resource_reference(&state
->res
, NULL
);
4480 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
4481 state
, all_aux_modes
);
4483 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4484 fill_surface_state(isl_dev
, map
, res
, &res
->surf
, view
, aux_usage
, 0, 0);
4485 map
+= SURFACE_STATE_ALIGNMENT
;
4491 * Add a surface to the validation list, as well as the buffer containing
4492 * the corresponding SURFACE_STATE.
4494 * Returns the binding table entry (offset to SURFACE_STATE).
4497 use_surface(struct iris_context
*ice
,
4498 struct iris_batch
*batch
,
4499 struct pipe_surface
*p_surf
,
4501 enum isl_aux_usage aux_usage
,
4502 bool is_read_surface
)
4504 struct iris_surface
*surf
= (void *) p_surf
;
4505 struct iris_resource
*res
= (void *) p_surf
->texture
;
4506 uint32_t offset
= 0;
4508 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
4509 if (GEN_GEN
== 8 && is_read_surface
) {
4510 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state_read
.res
), false);
4512 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
4516 iris_use_pinned_bo(batch
, res
->aux
.bo
, writeable
);
4517 if (res
->aux
.clear_color_bo
)
4518 iris_use_pinned_bo(batch
, res
->aux
.clear_color_bo
, false);
4520 if (memcmp(&res
->aux
.clear_color
, &surf
->clear_color
,
4521 sizeof(surf
->clear_color
)) != 0) {
4522 update_clear_value(ice
, batch
, res
, &surf
->surface_state
,
4523 res
->aux
.possible_usages
, &surf
->view
);
4525 update_clear_value(ice
, batch
, res
, &surf
->surface_state_read
,
4526 res
->aux
.possible_usages
, &surf
->read_view
);
4528 surf
->clear_color
= res
->aux
.clear_color
;
4532 offset
= (GEN_GEN
== 8 && is_read_surface
) ? surf
->surface_state_read
.offset
4533 : surf
->surface_state
.offset
;
4536 surf_state_offset_for_aux(res
, res
->aux
.possible_usages
, aux_usage
);
4540 use_sampler_view(struct iris_context
*ice
,
4541 struct iris_batch
*batch
,
4542 struct iris_sampler_view
*isv
)
4545 enum isl_aux_usage aux_usage
=
4546 iris_resource_texture_aux_usage(ice
, isv
->res
, isv
->view
.format
, 0);
4548 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
4549 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
4551 if (isv
->res
->aux
.bo
) {
4552 iris_use_pinned_bo(batch
, isv
->res
->aux
.bo
, false);
4553 if (isv
->res
->aux
.clear_color_bo
)
4554 iris_use_pinned_bo(batch
, isv
->res
->aux
.clear_color_bo
, false);
4555 if (memcmp(&isv
->res
->aux
.clear_color
, &isv
->clear_color
,
4556 sizeof(isv
->clear_color
)) != 0) {
4557 update_clear_value(ice
, batch
, isv
->res
, &isv
->surface_state
,
4558 isv
->res
->aux
.sampler_usages
, &isv
->view
);
4559 isv
->clear_color
= isv
->res
->aux
.clear_color
;
4563 return isv
->surface_state
.offset
+
4564 surf_state_offset_for_aux(isv
->res
, isv
->res
->aux
.sampler_usages
,
4569 use_ubo_ssbo(struct iris_batch
*batch
,
4570 struct iris_context
*ice
,
4571 struct pipe_shader_buffer
*buf
,
4572 struct iris_state_ref
*surf_state
,
4575 if (!buf
->buffer
|| !surf_state
->res
)
4576 return use_null_surface(batch
, ice
);
4578 iris_use_pinned_bo(batch
, iris_resource_bo(buf
->buffer
), writable
);
4579 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
4581 return surf_state
->offset
;
4585 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
4586 struct iris_shader_state
*shs
, int i
)
4588 struct iris_image_view
*iv
= &shs
->image
[i
];
4589 struct iris_resource
*res
= (void *) iv
->base
.resource
;
4592 return use_null_surface(batch
, ice
);
4594 bool write
= iv
->base
.shader_access
& PIPE_IMAGE_ACCESS_WRITE
;
4596 iris_use_pinned_bo(batch
, res
->bo
, write
);
4597 iris_use_pinned_bo(batch
, iris_resource_bo(iv
->surface_state
.res
), false);
4600 iris_use_pinned_bo(batch
, res
->aux
.bo
, write
);
4602 return iv
->surface_state
.offset
;
4605 #define push_bt_entry(addr) \
4606 assert(addr >= binder_addr); \
4607 assert(s < shader->bt.size_bytes / sizeof(uint32_t)); \
4608 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
4610 #define bt_assert(section) \
4611 if (!pin_only && shader->bt.used_mask[section] != 0) \
4612 assert(shader->bt.offsets[section] == s);
4615 * Populate the binding table for a given shader stage.
4617 * This fills out the table of pointers to surfaces required by the shader,
4618 * and also adds those buffers to the validation list so the kernel can make
4619 * resident before running our batch.
4622 iris_populate_binding_table(struct iris_context
*ice
,
4623 struct iris_batch
*batch
,
4624 gl_shader_stage stage
,
4627 const struct iris_binder
*binder
= &ice
->state
.binder
;
4628 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
4629 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4633 struct iris_binding_table
*bt
= &shader
->bt
;
4634 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4635 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4636 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
4638 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
4641 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
4643 /* TCS passthrough doesn't need a binding table. */
4644 assert(stage
== MESA_SHADER_TESS_CTRL
);
4648 if (stage
== MESA_SHADER_COMPUTE
&&
4649 shader
->bt
.used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
]) {
4650 /* surface for gl_NumWorkGroups */
4651 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
4652 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
4653 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
4654 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
4655 push_bt_entry(grid_state
->offset
);
4658 if (stage
== MESA_SHADER_FRAGMENT
) {
4659 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4660 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
4661 if (cso_fb
->nr_cbufs
) {
4662 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
4664 if (cso_fb
->cbufs
[i
]) {
4665 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
], true,
4666 ice
->state
.draw_aux_usage
[i
], false);
4668 addr
= use_null_fb_surface(batch
, ice
);
4670 push_bt_entry(addr
);
4672 } else if (GEN_GEN
< 11) {
4673 uint32_t addr
= use_null_fb_surface(batch
, ice
);
4674 push_bt_entry(addr
);
4678 #define foreach_surface_used(index, group) \
4680 for (int index = 0; index < bt->sizes[group]; index++) \
4681 if (iris_group_index_to_bti(bt, group, index) != \
4682 IRIS_SURFACE_NOT_USED)
4684 foreach_surface_used(i
, IRIS_SURFACE_GROUP_RENDER_TARGET_READ
) {
4685 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4687 if (cso_fb
->cbufs
[i
]) {
4688 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
],
4689 true, ice
->state
.draw_aux_usage
[i
], true);
4690 push_bt_entry(addr
);
4694 foreach_surface_used(i
, IRIS_SURFACE_GROUP_TEXTURE
) {
4695 struct iris_sampler_view
*view
= shs
->textures
[i
];
4696 uint32_t addr
= view
? use_sampler_view(ice
, batch
, view
)
4697 : use_null_surface(batch
, ice
);
4698 push_bt_entry(addr
);
4701 foreach_surface_used(i
, IRIS_SURFACE_GROUP_IMAGE
) {
4702 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
4703 push_bt_entry(addr
);
4706 foreach_surface_used(i
, IRIS_SURFACE_GROUP_UBO
) {
4709 if (i
== bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] - 1) {
4710 if (ish
->const_data
) {
4711 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data
), false);
4712 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data_state
.res
),
4714 addr
= ish
->const_data_state
.offset
;
4716 /* This can only happen with INTEL_DISABLE_COMPACT_BINDING_TABLE=1. */
4717 addr
= use_null_surface(batch
, ice
);
4720 addr
= use_ubo_ssbo(batch
, ice
, &shs
->constbuf
[i
],
4721 &shs
->constbuf_surf_state
[i
], false);
4724 push_bt_entry(addr
);
4727 foreach_surface_used(i
, IRIS_SURFACE_GROUP_SSBO
) {
4729 use_ubo_ssbo(batch
, ice
, &shs
->ssbo
[i
], &shs
->ssbo_surf_state
[i
],
4730 shs
->writable_ssbos
& (1u << i
));
4731 push_bt_entry(addr
);
4735 /* XXX: YUV surfaces not implemented yet */
4736 bt_assert(plane_start
[1], ...);
4737 bt_assert(plane_start
[2], ...);
4742 iris_use_optional_res(struct iris_batch
*batch
,
4743 struct pipe_resource
*res
,
4747 struct iris_bo
*bo
= iris_resource_bo(res
);
4748 iris_use_pinned_bo(batch
, bo
, writeable
);
4753 pin_depth_and_stencil_buffers(struct iris_batch
*batch
,
4754 struct pipe_surface
*zsbuf
,
4755 struct iris_depth_stencil_alpha_state
*cso_zsa
)
4760 struct iris_resource
*zres
, *sres
;
4761 iris_get_depth_stencil_resources(zsbuf
->texture
, &zres
, &sres
);
4764 iris_use_pinned_bo(batch
, zres
->bo
, cso_zsa
->depth_writes_enabled
);
4766 iris_use_pinned_bo(batch
, zres
->aux
.bo
,
4767 cso_zsa
->depth_writes_enabled
);
4772 iris_use_pinned_bo(batch
, sres
->bo
, cso_zsa
->stencil_writes_enabled
);
4776 /* ------------------------------------------------------------------- */
4779 * Pin any BOs which were installed by a previous batch, and restored
4780 * via the hardware logical context mechanism.
4782 * We don't need to re-emit all state every batch - the hardware context
4783 * mechanism will save and restore it for us. This includes pointers to
4784 * various BOs...which won't exist unless we ask the kernel to pin them
4785 * by adding them to the validation list.
4787 * We can skip buffers if we've re-emitted those packets, as we're
4788 * overwriting those stale pointers with new ones, and don't actually
4789 * refer to the old BOs.
4792 iris_restore_render_saved_bos(struct iris_context
*ice
,
4793 struct iris_batch
*batch
,
4794 const struct pipe_draw_info
*draw
)
4796 struct iris_genx_state
*genx
= ice
->state
.genx
;
4798 const uint64_t clean
= ~ice
->state
.dirty
;
4800 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
4801 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
4804 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4805 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
4808 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
4809 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
4812 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4813 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
4816 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
4817 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
4820 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
4821 for (int i
= 0; i
< 4; i
++) {
4822 struct iris_stream_output_target
*tgt
=
4823 (void *) ice
->state
.so_target
[i
];
4825 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4827 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4833 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4834 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4837 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4838 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4843 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4845 for (int i
= 0; i
< 4; i
++) {
4846 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4848 if (range
->length
== 0)
4851 /* Range block is a binding table index, map back to UBO index. */
4852 unsigned block_index
= iris_bti_to_group_index(
4853 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
4854 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
4856 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4857 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4860 iris_use_pinned_bo(batch
, res
->bo
, false);
4862 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4866 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4867 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4868 /* Re-pin any buffers referred to by the binding table. */
4869 iris_populate_binding_table(ice
, batch
, stage
, true);
4873 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4874 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4875 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4877 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4880 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4881 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
4882 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4885 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4886 iris_use_pinned_bo(batch
, bo
, false);
4888 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4890 if (prog_data
->total_scratch
> 0) {
4891 struct iris_bo
*bo
=
4892 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4893 iris_use_pinned_bo(batch
, bo
, true);
4899 if ((clean
& IRIS_DIRTY_DEPTH_BUFFER
) &&
4900 (clean
& IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
4901 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4902 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
4905 iris_use_optional_res(batch
, ice
->state
.last_res
.index_buffer
, false);
4907 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4908 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4910 const int i
= u_bit_scan64(&bound
);
4911 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
4912 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4918 iris_restore_compute_saved_bos(struct iris_context
*ice
,
4919 struct iris_batch
*batch
,
4920 const struct pipe_grid_info
*grid
)
4922 const uint64_t clean
= ~ice
->state
.dirty
;
4924 const int stage
= MESA_SHADER_COMPUTE
;
4925 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4927 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
4928 /* Re-pin any buffers referred to by the binding table. */
4929 iris_populate_binding_table(ice
, batch
, stage
, true);
4932 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
4934 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
4936 if ((clean
& IRIS_DIRTY_SAMPLER_STATES_CS
) &&
4937 (clean
& IRIS_DIRTY_BINDINGS_CS
) &&
4938 (clean
& IRIS_DIRTY_CONSTANTS_CS
) &&
4939 (clean
& IRIS_DIRTY_CS
)) {
4940 iris_use_optional_res(batch
, ice
->state
.last_res
.cs_desc
, false);
4943 if (clean
& IRIS_DIRTY_CS
) {
4944 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4947 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4948 iris_use_pinned_bo(batch
, bo
, false);
4950 struct iris_bo
*curbe_bo
=
4951 iris_resource_bo(ice
->state
.last_res
.cs_thread_ids
);
4952 iris_use_pinned_bo(batch
, curbe_bo
, false);
4954 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4956 if (prog_data
->total_scratch
> 0) {
4957 struct iris_bo
*bo
=
4958 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4959 iris_use_pinned_bo(batch
, bo
, true);
4966 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
4969 iris_update_surface_base_address(struct iris_batch
*batch
,
4970 struct iris_binder
*binder
)
4972 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
4975 flush_before_state_base_change(batch
);
4977 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
4978 sba
.SurfaceStateBaseAddressModifyEnable
= true;
4979 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
4981 /* The hardware appears to pay attention to the MOCS fields even
4982 * if you don't set the "Address Modify Enable" bit for the base.
4984 sba
.GeneralStateMOCS
= MOCS_WB
;
4985 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
4986 sba
.DynamicStateMOCS
= MOCS_WB
;
4987 sba
.IndirectObjectMOCS
= MOCS_WB
;
4988 sba
.InstructionMOCS
= MOCS_WB
;
4989 sba
.SurfaceStateMOCS
= MOCS_WB
;
4991 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
4995 flush_after_state_base_change(batch
);
4997 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
5001 iris_viewport_zmin_zmax(const struct pipe_viewport_state
*vp
, bool halfz
,
5002 bool window_space_position
, float *zmin
, float *zmax
)
5004 if (window_space_position
) {
5009 util_viewport_zmin_zmax(vp
, halfz
, zmin
, zmax
);
5014 genX(emit_aux_map_state
)(struct iris_batch
*batch
)
5016 struct iris_screen
*screen
= batch
->screen
;
5017 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
5020 uint32_t aux_map_state_num
= gen_aux_map_get_state_num(aux_map_ctx
);
5021 if (batch
->last_aux_map_state
!= aux_map_state_num
) {
5022 /* If the aux-map state number increased, then we need to rewrite the
5023 * register. Rewriting the register is used to both set the aux-map
5024 * translation table address, and also to invalidate any previously
5025 * cached translations.
5027 uint64_t base_addr
= gen_aux_map_get_base(aux_map_ctx
);
5028 assert(base_addr
!= 0 && ALIGN(base_addr
, 32 * 1024) == base_addr
);
5029 iris_load_register_imm64(batch
, GENX(GFX_AUX_TABLE_BASE_ADDR_num
),
5031 batch
->last_aux_map_state
= aux_map_state_num
;
5037 iris_upload_dirty_render_state(struct iris_context
*ice
,
5038 struct iris_batch
*batch
,
5039 const struct pipe_draw_info
*draw
)
5041 const uint64_t dirty
= ice
->state
.dirty
;
5043 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
5046 struct iris_genx_state
*genx
= ice
->state
.genx
;
5047 struct iris_binder
*binder
= &ice
->state
.binder
;
5048 struct brw_wm_prog_data
*wm_prog_data
= (void *)
5049 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
5051 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
5052 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5053 uint32_t cc_vp_address
;
5055 /* XXX: could avoid streaming for depth_clip [0,1] case. */
5056 uint32_t *cc_vp_map
=
5057 stream_state(batch
, ice
->state
.dynamic_uploader
,
5058 &ice
->state
.last_res
.cc_vp
,
5059 4 * ice
->state
.num_viewports
*
5060 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
5061 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
5063 iris_viewport_zmin_zmax(&ice
->state
.viewports
[i
], cso_rast
->clip_halfz
,
5064 ice
->state
.window_space_position
,
5066 if (cso_rast
->depth_clip_near
)
5068 if (cso_rast
->depth_clip_far
)
5071 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
5072 ccv
.MinimumDepth
= zmin
;
5073 ccv
.MaximumDepth
= zmax
;
5076 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
5079 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
5080 ptr
.CCViewportPointer
= cc_vp_address
;
5084 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
5085 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5086 uint32_t sf_cl_vp_address
;
5088 stream_state(batch
, ice
->state
.dynamic_uploader
,
5089 &ice
->state
.last_res
.sf_cl_vp
,
5090 4 * ice
->state
.num_viewports
*
5091 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
5093 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
5094 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
5095 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
5097 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
5098 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
5099 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
5100 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
5102 gen_calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
5103 state
->scale
[0], state
->scale
[1],
5104 state
->translate
[0], state
->translate
[1],
5105 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
5107 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
5108 vp
.ViewportMatrixElementm00
= state
->scale
[0];
5109 vp
.ViewportMatrixElementm11
= state
->scale
[1];
5110 vp
.ViewportMatrixElementm22
= state
->scale
[2];
5111 vp
.ViewportMatrixElementm30
= state
->translate
[0];
5112 vp
.ViewportMatrixElementm31
= state
->translate
[1];
5113 vp
.ViewportMatrixElementm32
= state
->translate
[2];
5114 vp
.XMinClipGuardband
= gb_xmin
;
5115 vp
.XMaxClipGuardband
= gb_xmax
;
5116 vp
.YMinClipGuardband
= gb_ymin
;
5117 vp
.YMaxClipGuardband
= gb_ymax
;
5118 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
5119 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
5120 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
5121 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
5124 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
5127 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
5128 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
5132 if (dirty
& IRIS_DIRTY_URB
) {
5135 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
5136 if (!ice
->shaders
.prog
[i
]) {
5139 struct brw_vue_prog_data
*vue_prog_data
=
5140 (void *) ice
->shaders
.prog
[i
]->prog_data
;
5141 size
[i
] = vue_prog_data
->urb_entry_size
;
5143 assert(size
[i
] != 0);
5146 genX(emit_urb_setup
)(ice
, batch
, size
,
5147 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
5148 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
);
5151 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
5152 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
5153 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5154 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
5155 const int header_dwords
= GENX(BLEND_STATE_length
);
5157 /* Always write at least one BLEND_STATE - the final RT message will
5158 * reference BLEND_STATE[0] even if there aren't color writes. There
5159 * may still be alpha testing, computed depth, and so on.
5161 const int rt_dwords
=
5162 MAX2(cso_fb
->nr_cbufs
, 1) * GENX(BLEND_STATE_ENTRY_length
);
5164 uint32_t blend_offset
;
5165 uint32_t *blend_map
=
5166 stream_state(batch
, ice
->state
.dynamic_uploader
,
5167 &ice
->state
.last_res
.blend
,
5168 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
5170 uint32_t blend_state_header
;
5171 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
5172 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
5173 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
5176 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
5177 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
5179 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
5180 ptr
.BlendStatePointer
= blend_offset
;
5181 ptr
.BlendStatePointerValid
= true;
5185 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
5186 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
5188 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
5192 stream_state(batch
, ice
->state
.dynamic_uploader
,
5193 &ice
->state
.last_res
.color_calc
,
5194 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
5196 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
5197 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
5198 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
5199 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
5200 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
5201 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
5202 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
5204 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
5205 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
5208 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
5209 ptr
.ColorCalcStatePointer
= cc_offset
;
5210 ptr
.ColorCalcStatePointerValid
= true;
5214 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5215 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
5218 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5219 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5224 if (shs
->sysvals_need_upload
)
5225 upload_sysvals(ice
, stage
);
5227 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
5229 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
5230 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
5232 /* The Skylake PRM contains the following restriction:
5234 * "The driver must ensure The following case does not occur
5235 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
5236 * buffer 3 read length equal to zero committed followed by a
5237 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
5240 * To avoid this, we program the buffers in the highest slots.
5241 * This way, slot 0 is only used if slot 3 is also used.
5245 for (int i
= 3; i
>= 0; i
--) {
5246 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
5248 if (range
->length
== 0)
5251 /* Range block is a binding table index, map back to UBO index. */
5252 unsigned block_index
= iris_bti_to_group_index(
5253 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
5254 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
5256 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
5257 struct iris_resource
*res
= (void *) cbuf
->buffer
;
5259 assert(cbuf
->buffer_offset
% 32 == 0);
5261 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
5262 pkt
.ConstantBody
.Buffer
[n
] =
5263 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->buffer_offset
)
5264 : ro_bo(batch
->screen
->workaround_bo
, 0);
5271 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5272 /* Gen9 requires 3DSTATE_BINDING_TABLE_POINTERS_XS to be re-emitted
5273 * in order to commit constants. TODO: Investigate "Disable Gather
5274 * at Set Shader" to go back to legacy mode...
5276 if (dirty
& ((IRIS_DIRTY_BINDINGS_VS
|
5277 (GEN_GEN
== 9 ? IRIS_DIRTY_CONSTANTS_VS
: 0)) << stage
)) {
5278 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
5279 ptr
._3DCommandSubOpcode
= 38 + stage
;
5280 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
5285 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5286 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
5287 iris_populate_binding_table(ice
, batch
, stage
, false);
5291 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5292 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
5293 !ice
->shaders
.prog
[stage
])
5296 iris_upload_sampler_states(ice
, stage
);
5298 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5299 struct pipe_resource
*res
= shs
->sampler_table
.res
;
5301 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
5303 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
5304 ptr
._3DCommandSubOpcode
= 43 + stage
;
5305 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
5309 if (ice
->state
.need_border_colors
)
5310 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
5312 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
5313 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
5315 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
5316 if (ice
->state
.framebuffer
.samples
> 0)
5317 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
5321 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
5322 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
5323 ms
.SampleMask
= ice
->state
.sample_mask
;
5327 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5328 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
5331 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5334 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5335 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
5336 iris_use_pinned_bo(batch
, cache
->bo
, false);
5338 if (prog_data
->total_scratch
> 0) {
5339 struct iris_bo
*bo
=
5340 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
5341 iris_use_pinned_bo(batch
, bo
, true);
5344 if (stage
== MESA_SHADER_FRAGMENT
) {
5345 UNUSED
struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5346 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5348 uint32_t ps_state
[GENX(3DSTATE_PS_length
)] = {0};
5349 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
5350 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
5351 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
5352 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
5354 /* The docs for 3DSTATE_PS::32 Pixel Dispatch Enable say:
5356 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16,
5357 * SIMD32 Dispatch must not be enabled for PER_PIXEL dispatch
5360 * 16x MSAA only exists on Gen9+, so we can skip this on Gen8.
5362 if (GEN_GEN
>= 9 && cso_fb
->samples
== 16 &&
5363 !wm_prog_data
->persample_dispatch
) {
5364 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
5365 ps
._32PixelDispatchEnable
= false;
5368 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
5369 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
5370 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
5371 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
5372 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
5373 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
5375 ps
.KernelStartPointer0
= KSP(shader
) +
5376 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
5377 ps
.KernelStartPointer1
= KSP(shader
) +
5378 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
5379 ps
.KernelStartPointer2
= KSP(shader
) +
5380 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
5383 uint32_t psx_state
[GENX(3DSTATE_PS_EXTRA_length
)] = {0};
5384 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
5386 if (!wm_prog_data
->uses_sample_mask
)
5387 psx
.InputCoverageMaskState
= ICMS_NONE
;
5388 else if (wm_prog_data
->post_depth_coverage
)
5389 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
5390 else if (wm_prog_data
->inner_coverage
&&
5391 cso
->conservative_rasterization
)
5392 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
5394 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
5396 psx
.PixelShaderUsesInputCoverageMask
=
5397 wm_prog_data
->uses_sample_mask
;
5401 uint32_t *shader_ps
= (uint32_t *) shader
->derived_data
;
5402 uint32_t *shader_psx
= shader_ps
+ GENX(3DSTATE_PS_length
);
5403 iris_emit_merge(batch
, shader_ps
, ps_state
,
5404 GENX(3DSTATE_PS_length
));
5405 iris_emit_merge(batch
, shader_psx
, psx_state
,
5406 GENX(3DSTATE_PS_EXTRA_length
));
5408 iris_batch_emit(batch
, shader
->derived_data
,
5409 iris_derived_program_state_size(stage
));
5412 if (stage
== MESA_SHADER_TESS_EVAL
) {
5413 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
5414 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
5415 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
5416 } else if (stage
== MESA_SHADER_GEOMETRY
) {
5417 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
5422 if (ice
->state
.streamout_active
) {
5423 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
5424 iris_batch_emit(batch
, genx
->so_buffers
,
5425 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
5426 for (int i
= 0; i
< 4; i
++) {
5427 struct iris_stream_output_target
*tgt
=
5428 (void *) ice
->state
.so_target
[i
];
5431 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
5433 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
5439 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
5440 uint32_t *decl_list
=
5441 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
5442 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
5445 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
5446 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5448 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
5449 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
5450 sol
.SOFunctionEnable
= true;
5451 sol
.SOStatisticsEnable
= true;
5453 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
5454 !ice
->state
.prims_generated_query_active
;
5455 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
5458 assert(ice
->state
.streamout
);
5460 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
5461 GENX(3DSTATE_STREAMOUT_length
));
5464 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
5465 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
5469 if (dirty
& IRIS_DIRTY_CLIP
) {
5470 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5471 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5473 bool gs_or_tes
= ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] ||
5474 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
5475 bool points_or_lines
= cso_rast
->fill_mode_point_or_line
||
5476 (gs_or_tes
? ice
->shaders
.output_topology_is_points_or_lines
5477 : ice
->state
.prim_is_points_or_lines
);
5479 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
5480 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
5481 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5482 if (cso_rast
->rasterizer_discard
)
5483 cl
.ClipMode
= CLIPMODE_REJECT_ALL
;
5484 else if (ice
->state
.window_space_position
)
5485 cl
.ClipMode
= CLIPMODE_ACCEPT_ALL
;
5487 cl
.ClipMode
= CLIPMODE_NORMAL
;
5489 cl
.PerspectiveDivideDisable
= ice
->state
.window_space_position
;
5490 cl
.ViewportXYClipTestEnable
= !points_or_lines
;
5492 if (wm_prog_data
->barycentric_interp_modes
&
5493 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
5494 cl
.NonPerspectiveBarycentricEnable
= true;
5496 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
5497 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
5499 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
5500 ARRAY_SIZE(cso_rast
->clip
));
5503 if (dirty
& IRIS_DIRTY_RASTER
) {
5504 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5505 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
5507 uint32_t dynamic_sf
[GENX(3DSTATE_SF_length
)];
5508 iris_pack_command(GENX(3DSTATE_SF
), &dynamic_sf
, sf
) {
5509 sf
.ViewportTransformEnable
= !ice
->state
.window_space_position
;
5511 iris_emit_merge(batch
, cso
->sf
, dynamic_sf
,
5512 ARRAY_SIZE(dynamic_sf
));
5515 if (dirty
& IRIS_DIRTY_WM
) {
5516 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5517 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
5519 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
5520 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5522 wm
.BarycentricInterpolationMode
=
5523 wm_prog_data
->barycentric_interp_modes
;
5525 if (wm_prog_data
->early_fragment_tests
)
5526 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
5527 else if (wm_prog_data
->has_side_effects
)
5528 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
5530 /* We could skip this bit if color writes are enabled. */
5531 if (wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
)
5532 wm
.ForceThreadDispatchEnable
= ForceON
;
5534 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
5537 if (dirty
& IRIS_DIRTY_SBE
) {
5538 iris_emit_sbe(batch
, ice
);
5541 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
5542 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
5543 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
5544 const struct shader_info
*fs_info
=
5545 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
5547 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
5548 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
5549 pb
.HasWriteableRT
= has_writeable_rt(cso_blend
, fs_info
);
5550 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
5552 /* The dual source blending docs caution against using SRC1 factors
5553 * when the shader doesn't use a dual source render target write.
5554 * Empirically, this can lead to GPU hangs, and the results are
5555 * undefined anyway, so simply disable blending to avoid the hang.
5557 pb
.ColorBufferBlendEnable
= (cso_blend
->blend_enables
& 1) &&
5558 (!cso_blend
->dual_color_blending
|| wm_prog_data
->dual_src_blend
);
5561 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
5562 ARRAY_SIZE(cso_blend
->ps_blend
));
5565 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
5566 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
5568 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
5569 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
5570 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
5571 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
5572 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
5574 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
5576 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
5580 iris_batch_emit(batch
, cso
->depth_bounds
, sizeof(cso
->depth_bounds
));
5584 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
5585 uint32_t scissor_offset
=
5586 emit_state(batch
, ice
->state
.dynamic_uploader
,
5587 &ice
->state
.last_res
.scissor
,
5588 ice
->state
.scissors
,
5589 sizeof(struct pipe_scissor_state
) *
5590 ice
->state
.num_viewports
, 32);
5592 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
5593 ptr
.ScissorRectPointer
= scissor_offset
;
5597 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
5598 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
5600 /* Do not emit the clear params yets. We need to update the clear value
5603 uint32_t clear_length
= GENX(3DSTATE_CLEAR_PARAMS_length
) * 4;
5604 uint32_t cso_z_size
= sizeof(cso_z
->packets
) - clear_length
;
5605 iris_batch_emit(batch
, cso_z
->packets
, cso_z_size
);
5607 union isl_color_value clear_value
= { .f32
= { 0, } };
5609 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5610 if (cso_fb
->zsbuf
) {
5611 struct iris_resource
*zres
, *sres
;
5612 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
5614 if (zres
&& zres
->aux
.bo
)
5615 clear_value
= iris_resource_get_clear_color(zres
, NULL
, NULL
);
5618 uint32_t clear_params
[GENX(3DSTATE_CLEAR_PARAMS_length
)];
5619 iris_pack_command(GENX(3DSTATE_CLEAR_PARAMS
), clear_params
, clear
) {
5620 clear
.DepthClearValueValid
= true;
5621 clear
.DepthClearValue
= clear_value
.f32
[0];
5623 iris_batch_emit(batch
, clear_params
, clear_length
);
5626 if (dirty
& (IRIS_DIRTY_DEPTH_BUFFER
| IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
5627 /* Listen for buffer changes, and also write enable changes. */
5628 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5629 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
5632 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
5633 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
5634 for (int i
= 0; i
< 32; i
++) {
5635 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
5640 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
5641 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5642 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
5645 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
5646 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
5647 topo
.PrimitiveTopologyType
=
5648 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
5652 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
5653 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
5654 int dynamic_bound
= ice
->state
.bound_vertex_buffers
;
5656 if (ice
->state
.vs_uses_draw_params
) {
5657 assert(ice
->draw
.draw_params
.res
);
5659 struct iris_vertex_buffer_state
*state
=
5660 &(ice
->state
.genx
->vertex_buffers
[count
]);
5661 pipe_resource_reference(&state
->resource
, ice
->draw
.draw_params
.res
);
5662 struct iris_resource
*res
= (void *) state
->resource
;
5664 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
5665 vb
.VertexBufferIndex
= count
;
5666 vb
.AddressModifyEnable
= true;
5668 vb
.BufferSize
= res
->bo
->size
- ice
->draw
.draw_params
.offset
;
5669 vb
.BufferStartingAddress
=
5670 ro_bo(NULL
, res
->bo
->gtt_offset
+
5671 (int) ice
->draw
.draw_params
.offset
);
5672 vb
.MOCS
= mocs(res
->bo
);
5674 dynamic_bound
|= 1ull << count
;
5678 if (ice
->state
.vs_uses_derived_draw_params
) {
5679 struct iris_vertex_buffer_state
*state
=
5680 &(ice
->state
.genx
->vertex_buffers
[count
]);
5681 pipe_resource_reference(&state
->resource
,
5682 ice
->draw
.derived_draw_params
.res
);
5683 struct iris_resource
*res
= (void *) ice
->draw
.derived_draw_params
.res
;
5685 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
5686 vb
.VertexBufferIndex
= count
;
5687 vb
.AddressModifyEnable
= true;
5690 res
->bo
->size
- ice
->draw
.derived_draw_params
.offset
;
5691 vb
.BufferStartingAddress
=
5692 ro_bo(NULL
, res
->bo
->gtt_offset
+
5693 (int) ice
->draw
.derived_draw_params
.offset
);
5694 vb
.MOCS
= mocs(res
->bo
);
5696 dynamic_bound
|= 1ull << count
;
5701 /* The VF cache designers cut corners, and made the cache key's
5702 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
5703 * 32 bits of the address. If you have two vertex buffers which get
5704 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
5705 * you can get collisions (even within a single batch).
5707 * So, we need to do a VF cache invalidate if the buffer for a VB
5708 * slot slot changes [48:32] address bits from the previous time.
5710 unsigned flush_flags
= 0;
5712 uint64_t bound
= dynamic_bound
;
5714 const int i
= u_bit_scan64(&bound
);
5715 uint16_t high_bits
= 0;
5717 struct iris_resource
*res
=
5718 (void *) genx
->vertex_buffers
[i
].resource
;
5720 iris_use_pinned_bo(batch
, res
->bo
, false);
5722 high_bits
= res
->bo
->gtt_offset
>> 32ull;
5723 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
5724 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5725 PIPE_CONTROL_CS_STALL
;
5726 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
5732 iris_emit_pipe_control_flush(batch
,
5733 "workaround: VF cache 32-bit key [VB]",
5737 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
5740 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
5741 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
5742 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
5746 bound
= dynamic_bound
;
5748 const int i
= u_bit_scan64(&bound
);
5749 memcpy(map
, genx
->vertex_buffers
[i
].state
,
5750 sizeof(uint32_t) * vb_dwords
);
5756 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
5757 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5758 const unsigned entries
= MAX2(cso
->count
, 1);
5759 if (!(ice
->state
.vs_needs_sgvs_element
||
5760 ice
->state
.vs_uses_derived_draw_params
||
5761 ice
->state
.vs_needs_edge_flag
)) {
5762 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
5763 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
5765 uint32_t dynamic_ves
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
5766 const unsigned dyn_count
= cso
->count
+
5767 ice
->state
.vs_needs_sgvs_element
+
5768 ice
->state
.vs_uses_derived_draw_params
;
5770 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
),
5773 1 + GENX(VERTEX_ELEMENT_STATE_length
) * dyn_count
- 2;
5775 memcpy(&dynamic_ves
[1], &cso
->vertex_elements
[1],
5776 (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5777 GENX(VERTEX_ELEMENT_STATE_length
) * sizeof(uint32_t));
5778 uint32_t *ve_pack_dest
=
5779 &dynamic_ves
[1 + (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5780 GENX(VERTEX_ELEMENT_STATE_length
)];
5782 if (ice
->state
.vs_needs_sgvs_element
) {
5783 uint32_t base_ctrl
= ice
->state
.vs_uses_draw_params
?
5784 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
5785 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5787 ve
.VertexBufferIndex
=
5788 util_bitcount64(ice
->state
.bound_vertex_buffers
);
5789 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5790 ve
.Component0Control
= base_ctrl
;
5791 ve
.Component1Control
= base_ctrl
;
5792 ve
.Component2Control
= VFCOMP_STORE_0
;
5793 ve
.Component3Control
= VFCOMP_STORE_0
;
5795 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5797 if (ice
->state
.vs_uses_derived_draw_params
) {
5798 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5800 ve
.VertexBufferIndex
=
5801 util_bitcount64(ice
->state
.bound_vertex_buffers
) +
5802 ice
->state
.vs_uses_draw_params
;
5803 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5804 ve
.Component0Control
= VFCOMP_STORE_SRC
;
5805 ve
.Component1Control
= VFCOMP_STORE_SRC
;
5806 ve
.Component2Control
= VFCOMP_STORE_0
;
5807 ve
.Component3Control
= VFCOMP_STORE_0
;
5809 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5811 if (ice
->state
.vs_needs_edge_flag
) {
5812 for (int i
= 0; i
< GENX(VERTEX_ELEMENT_STATE_length
); i
++)
5813 ve_pack_dest
[i
] = cso
->edgeflag_ve
[i
];
5816 iris_batch_emit(batch
, &dynamic_ves
, sizeof(uint32_t) *
5817 (1 + dyn_count
* GENX(VERTEX_ELEMENT_STATE_length
)));
5820 if (!ice
->state
.vs_needs_edge_flag
) {
5821 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
5822 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5824 assert(cso
->count
> 0);
5825 const unsigned edgeflag_index
= cso
->count
- 1;
5826 uint32_t dynamic_vfi
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
5827 memcpy(&dynamic_vfi
[0], cso
->vf_instancing
, edgeflag_index
*
5828 GENX(3DSTATE_VF_INSTANCING_length
) * sizeof(uint32_t));
5830 uint32_t *vfi_pack_dest
= &dynamic_vfi
[0] +
5831 edgeflag_index
* GENX(3DSTATE_VF_INSTANCING_length
);
5832 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
5833 vi
.VertexElementIndex
= edgeflag_index
+
5834 ice
->state
.vs_needs_sgvs_element
+
5835 ice
->state
.vs_uses_derived_draw_params
;
5837 for (int i
= 0; i
< GENX(3DSTATE_VF_INSTANCING_length
); i
++)
5838 vfi_pack_dest
[i
] |= cso
->edgeflag_vfi
[i
];
5840 iris_batch_emit(batch
, &dynamic_vfi
[0], sizeof(uint32_t) *
5841 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5845 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
5846 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
5847 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
5848 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5850 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
5851 if (vs_prog_data
->uses_vertexid
) {
5852 sgv
.VertexIDEnable
= true;
5853 sgv
.VertexIDComponentNumber
= 2;
5854 sgv
.VertexIDElementOffset
=
5855 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5858 if (vs_prog_data
->uses_instanceid
) {
5859 sgv
.InstanceIDEnable
= true;
5860 sgv
.InstanceIDComponentNumber
= 3;
5861 sgv
.InstanceIDElementOffset
=
5862 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5867 if (dirty
& IRIS_DIRTY_VF
) {
5868 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
5869 if (draw
->primitive_restart
) {
5870 vf
.IndexedDrawCutIndexEnable
= true;
5871 vf
.CutIndex
= draw
->restart_index
;
5876 if (dirty
& IRIS_DIRTY_VF_STATISTICS
) {
5877 iris_emit_cmd(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
5878 vf
.StatisticsEnable
= true;
5883 if (dirty
& IRIS_DIRTY_PMA_FIX
) {
5884 bool enable
= want_pma_fix(ice
);
5885 genX(update_pma_fix
)(ice
, batch
, enable
);
5889 if (ice
->state
.current_hash_scale
!= 1)
5890 genX(emit_hashing_mode
)(ice
, batch
, UINT_MAX
, UINT_MAX
, 1);
5893 genX(emit_aux_map_state
)(batch
);
5898 iris_upload_render_state(struct iris_context
*ice
,
5899 struct iris_batch
*batch
,
5900 const struct pipe_draw_info
*draw
)
5902 bool use_predicate
= ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
5904 /* Always pin the binder. If we're emitting new binding table pointers,
5905 * we need it. If not, we're probably inheriting old tables via the
5906 * context, and need it anyway. Since true zero-bindings cases are
5907 * practically non-existent, just pin it and avoid last_res tracking.
5909 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5911 if (!batch
->contains_draw
) {
5912 iris_restore_render_saved_bos(ice
, batch
, draw
);
5913 batch
->contains_draw
= true;
5916 iris_upload_dirty_render_state(ice
, batch
, draw
);
5918 if (draw
->index_size
> 0) {
5921 if (draw
->has_user_indices
) {
5922 u_upload_data(ice
->ctx
.stream_uploader
, 0,
5923 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
5924 &offset
, &ice
->state
.last_res
.index_buffer
);
5926 struct iris_resource
*res
= (void *) draw
->index
.resource
;
5927 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
5929 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
5930 draw
->index
.resource
);
5934 struct iris_genx_state
*genx
= ice
->state
.genx
;
5935 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
5937 uint32_t ib_packet
[GENX(3DSTATE_INDEX_BUFFER_length
)];
5938 iris_pack_command(GENX(3DSTATE_INDEX_BUFFER
), ib_packet
, ib
) {
5939 ib
.IndexFormat
= draw
->index_size
>> 1;
5941 ib
.BufferSize
= bo
->size
- offset
;
5942 ib
.BufferStartingAddress
= ro_bo(NULL
, bo
->gtt_offset
+ offset
);
5945 if (memcmp(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
)) != 0) {
5946 memcpy(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
));
5947 iris_batch_emit(batch
, ib_packet
, sizeof(ib_packet
));
5948 iris_use_pinned_bo(batch
, bo
, false);
5951 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
5952 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
5953 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
5954 iris_emit_pipe_control_flush(batch
,
5955 "workaround: VF cache 32-bit key [IB]",
5956 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5957 PIPE_CONTROL_CS_STALL
);
5958 ice
->state
.last_index_bo_high_bits
= high_bits
;
5962 #define _3DPRIM_END_OFFSET 0x2420
5963 #define _3DPRIM_START_VERTEX 0x2430
5964 #define _3DPRIM_VERTEX_COUNT 0x2434
5965 #define _3DPRIM_INSTANCE_COUNT 0x2438
5966 #define _3DPRIM_START_INSTANCE 0x243C
5967 #define _3DPRIM_BASE_VERTEX 0x2440
5969 if (draw
->indirect
) {
5970 if (draw
->indirect
->indirect_draw_count
) {
5971 use_predicate
= true;
5973 struct iris_bo
*draw_count_bo
=
5974 iris_resource_bo(draw
->indirect
->indirect_draw_count
);
5975 unsigned draw_count_offset
=
5976 draw
->indirect
->indirect_draw_count_offset
;
5978 iris_emit_pipe_control_flush(batch
,
5979 "ensure indirect draw buffer is flushed",
5980 PIPE_CONTROL_FLUSH_ENABLE
);
5982 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
) {
5983 struct gen_mi_builder b
;
5984 gen_mi_builder_init(&b
, batch
);
5986 /* comparison = draw id < draw count */
5987 struct gen_mi_value comparison
=
5988 gen_mi_ult(&b
, gen_mi_imm(draw
->drawid
),
5989 gen_mi_mem32(ro_bo(draw_count_bo
,
5990 draw_count_offset
)));
5992 /* predicate = comparison & conditional rendering predicate */
5993 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_RESULT
),
5994 gen_mi_iand(&b
, comparison
,
5995 gen_mi_reg32(CS_GPR(15))));
5997 uint32_t mi_predicate
;
5999 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
6000 iris_load_register_imm64(batch
, MI_PREDICATE_SRC1
, draw
->drawid
);
6001 /* Upload the current draw count from the draw parameters buffer
6002 * to MI_PREDICATE_SRC0.
6004 iris_load_register_mem32(batch
, MI_PREDICATE_SRC0
,
6005 draw_count_bo
, draw_count_offset
);
6006 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
6007 iris_load_register_imm32(batch
, MI_PREDICATE_SRC0
+ 4, 0);
6009 if (draw
->drawid
== 0) {
6010 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
6011 MI_PREDICATE_COMBINEOP_SET
|
6012 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
6014 /* While draw_index < draw_count the predicate's result will be
6015 * (draw_index == draw_count) ^ TRUE = TRUE
6016 * When draw_index == draw_count the result is
6017 * (TRUE) ^ TRUE = FALSE
6018 * After this all results will be:
6019 * (FALSE) ^ FALSE = FALSE
6021 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOAD
|
6022 MI_PREDICATE_COMBINEOP_XOR
|
6023 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
6025 iris_batch_emit(batch
, &mi_predicate
, sizeof(uint32_t));
6028 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
6031 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6032 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
6033 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
6035 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6036 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
6037 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
6039 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6040 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
6041 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
6043 if (draw
->index_size
) {
6044 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6045 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
6046 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
6048 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6049 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
6050 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
6053 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6054 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
6055 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
6057 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
6058 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
6062 } else if (draw
->count_from_stream_output
) {
6063 struct iris_stream_output_target
*so
=
6064 (void *) draw
->count_from_stream_output
;
6066 /* XXX: Replace with actual cache tracking */
6067 iris_emit_pipe_control_flush(batch
,
6068 "draw count from stream output stall",
6069 PIPE_CONTROL_CS_STALL
);
6071 struct gen_mi_builder b
;
6072 gen_mi_builder_init(&b
, batch
);
6074 struct iris_address addr
=
6075 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
6076 struct gen_mi_value offset
=
6077 gen_mi_iadd_imm(&b
, gen_mi_mem32(addr
), -so
->base
.buffer_offset
);
6079 gen_mi_store(&b
, gen_mi_reg32(_3DPRIM_VERTEX_COUNT
),
6080 gen_mi_udiv32_imm(&b
, offset
, so
->stride
));
6082 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
6083 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
6084 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
6085 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
6088 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
6089 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
6090 prim
.PredicateEnable
= use_predicate
;
6092 if (draw
->indirect
|| draw
->count_from_stream_output
) {
6093 prim
.IndirectParameterEnable
= true;
6095 prim
.StartInstanceLocation
= draw
->start_instance
;
6096 prim
.InstanceCount
= draw
->instance_count
;
6097 prim
.VertexCountPerInstance
= draw
->count
;
6099 prim
.StartVertexLocation
= draw
->start
;
6101 if (draw
->index_size
) {
6102 prim
.BaseVertexLocation
+= draw
->index_bias
;
6104 prim
.StartVertexLocation
+= draw
->index_bias
;
6111 iris_upload_compute_state(struct iris_context
*ice
,
6112 struct iris_batch
*batch
,
6113 const struct pipe_grid_info
*grid
)
6115 const uint64_t dirty
= ice
->state
.dirty
;
6116 struct iris_screen
*screen
= batch
->screen
;
6117 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
6118 struct iris_binder
*binder
= &ice
->state
.binder
;
6119 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
6120 struct iris_compiled_shader
*shader
=
6121 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
6122 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
6123 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
6125 /* Always pin the binder. If we're emitting new binding table pointers,
6126 * we need it. If not, we're probably inheriting old tables via the
6127 * context, and need it anyway. Since true zero-bindings cases are
6128 * practically non-existent, just pin it and avoid last_res tracking.
6130 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
6132 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->sysvals_need_upload
)
6133 upload_sysvals(ice
, MESA_SHADER_COMPUTE
);
6135 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
6136 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
6138 if (dirty
& IRIS_DIRTY_SAMPLER_STATES_CS
)
6139 iris_upload_sampler_states(ice
, MESA_SHADER_COMPUTE
);
6141 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
6142 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
6144 if (ice
->state
.need_border_colors
)
6145 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
6148 genX(emit_aux_map_state
)(batch
);
6151 if (dirty
& IRIS_DIRTY_CS
) {
6152 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
6154 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
6155 * the only bits that are changed are scoreboard related: Scoreboard
6156 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
6157 * these scoreboard related states, a MEDIA_STATE_FLUSH is
6160 iris_emit_pipe_control_flush(batch
,
6161 "workaround: stall before MEDIA_VFE_STATE",
6162 PIPE_CONTROL_CS_STALL
);
6164 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
6165 if (prog_data
->total_scratch
) {
6166 struct iris_bo
*bo
=
6167 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
6168 MESA_SHADER_COMPUTE
);
6169 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
6170 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
6173 vfe
.MaximumNumberofThreads
=
6174 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
6176 vfe
.ResetGatewayTimer
=
6177 Resettingrelativetimerandlatchingtheglobaltimestamp
;
6180 vfe
.BypassGatewayControl
= true;
6182 vfe
.NumberofURBEntries
= 2;
6183 vfe
.URBEntryAllocationSize
= 2;
6185 vfe
.CURBEAllocationSize
=
6186 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
6187 cs_prog_data
->push
.cross_thread
.regs
, 2);
6191 /* TODO: Combine subgroup-id with cbuf0 so we can push regular uniforms */
6192 if (dirty
& IRIS_DIRTY_CS
) {
6193 uint32_t curbe_data_offset
= 0;
6194 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
6195 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
6196 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
6197 uint32_t *curbe_data_map
=
6198 stream_state(batch
, ice
->state
.dynamic_uploader
,
6199 &ice
->state
.last_res
.cs_thread_ids
,
6200 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
6201 &curbe_data_offset
);
6202 assert(curbe_data_map
);
6203 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
6204 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
6206 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
6207 curbe
.CURBETotalDataLength
=
6208 ALIGN(cs_prog_data
->push
.total
.size
, 64);
6209 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
6213 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
6214 IRIS_DIRTY_BINDINGS_CS
|
6215 IRIS_DIRTY_CONSTANTS_CS
|
6217 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
6219 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
6220 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
6221 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
6224 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
6225 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
6227 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
6228 load
.InterfaceDescriptorTotalLength
=
6229 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
6230 load
.InterfaceDescriptorDataStartAddress
=
6231 emit_state(batch
, ice
->state
.dynamic_uploader
,
6232 &ice
->state
.last_res
.cs_desc
, desc
, sizeof(desc
), 64);
6236 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
6237 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
6238 uint32_t right_mask
;
6241 right_mask
= ~0u >> (32 - remainder
);
6243 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
6245 #define GPGPU_DISPATCHDIMX 0x2500
6246 #define GPGPU_DISPATCHDIMY 0x2504
6247 #define GPGPU_DISPATCHDIMZ 0x2508
6249 if (grid
->indirect
) {
6250 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
6251 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
6252 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6253 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
6254 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
6256 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6257 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
6258 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
6260 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6261 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
6262 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
6266 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
6267 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
6268 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
6269 ggw
.ThreadDepthCounterMaximum
= 0;
6270 ggw
.ThreadHeightCounterMaximum
= 0;
6271 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
6272 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
6273 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
6274 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
6275 ggw
.RightExecutionMask
= right_mask
;
6276 ggw
.BottomExecutionMask
= 0xffffffff;
6279 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
6281 if (!batch
->contains_draw
) {
6282 iris_restore_compute_saved_bos(ice
, batch
, grid
);
6283 batch
->contains_draw
= true;
6288 * State module teardown.
6291 iris_destroy_state(struct iris_context
*ice
)
6293 struct iris_genx_state
*genx
= ice
->state
.genx
;
6295 pipe_resource_reference(&ice
->draw
.draw_params
.res
, NULL
);
6296 pipe_resource_reference(&ice
->draw
.derived_draw_params
.res
, NULL
);
6298 /* Loop over all VBOs, including ones for draw parameters */
6299 for (unsigned i
= 0; i
< ARRAY_SIZE(genx
->vertex_buffers
); i
++) {
6300 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
6303 free(ice
->state
.genx
);
6305 for (int i
= 0; i
< 4; i
++) {
6306 pipe_so_target_reference(&ice
->state
.so_target
[i
], NULL
);
6309 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
6310 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
6312 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
6314 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
6315 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
6316 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
6317 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
6318 pipe_resource_reference(&shs
->constbuf
[i
].buffer
, NULL
);
6319 pipe_resource_reference(&shs
->constbuf_surf_state
[i
].res
, NULL
);
6321 for (int i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
6322 pipe_resource_reference(&shs
->image
[i
].base
.resource
, NULL
);
6323 pipe_resource_reference(&shs
->image
[i
].surface_state
.res
, NULL
);
6325 for (int i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
6326 pipe_resource_reference(&shs
->ssbo
[i
].buffer
, NULL
);
6327 pipe_resource_reference(&shs
->ssbo_surf_state
[i
].res
, NULL
);
6329 for (int i
= 0; i
< IRIS_MAX_TEXTURE_SAMPLERS
; i
++) {
6330 pipe_sampler_view_reference((struct pipe_sampler_view
**)
6331 &shs
->textures
[i
], NULL
);
6335 pipe_resource_reference(&ice
->state
.grid_size
.res
, NULL
);
6336 pipe_resource_reference(&ice
->state
.grid_surf_state
.res
, NULL
);
6338 pipe_resource_reference(&ice
->state
.null_fb
.res
, NULL
);
6339 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
6341 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
6342 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
6343 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
6344 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
6345 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
6346 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
6347 pipe_resource_reference(&ice
->state
.last_res
.cs_thread_ids
, NULL
);
6348 pipe_resource_reference(&ice
->state
.last_res
.cs_desc
, NULL
);
6351 /* ------------------------------------------------------------------- */
6354 iris_rebind_buffer(struct iris_context
*ice
,
6355 struct iris_resource
*res
,
6356 uint64_t old_address
)
6358 struct pipe_context
*ctx
= &ice
->ctx
;
6359 struct iris_screen
*screen
= (void *) ctx
->screen
;
6360 struct iris_genx_state
*genx
= ice
->state
.genx
;
6362 assert(res
->base
.target
== PIPE_BUFFER
);
6364 /* Buffers can't be framebuffer attachments, nor display related,
6365 * and we don't have upstream Clover support.
6367 assert(!(res
->bind_history
& (PIPE_BIND_DEPTH_STENCIL
|
6368 PIPE_BIND_RENDER_TARGET
|
6369 PIPE_BIND_BLENDABLE
|
6370 PIPE_BIND_DISPLAY_TARGET
|
6372 PIPE_BIND_COMPUTE_RESOURCE
|
6373 PIPE_BIND_GLOBAL
)));
6375 if (res
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
6376 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
6378 const int i
= u_bit_scan64(&bound_vbs
);
6379 struct iris_vertex_buffer_state
*state
= &genx
->vertex_buffers
[i
];
6381 /* Update the CPU struct */
6382 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_start
) == 32);
6383 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) == 64);
6384 uint64_t *addr
= (uint64_t *) &state
->state
[1];
6386 if (*addr
== old_address
+ state
->offset
) {
6387 *addr
= res
->bo
->gtt_offset
+ state
->offset
;
6388 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
6393 /* We don't need to handle PIPE_BIND_INDEX_BUFFER here: we re-emit
6394 * the 3DSTATE_INDEX_BUFFER packet whenever the address changes.
6396 * There is also no need to handle these:
6397 * - PIPE_BIND_COMMAND_ARGS_BUFFER (emitted for every indirect draw)
6398 * - PIPE_BIND_QUERY_BUFFER (no persistent state references)
6401 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
6402 /* XXX: be careful about resetting vs appending... */
6406 for (int s
= MESA_SHADER_VERTEX
; s
< MESA_SHADER_STAGES
; s
++) {
6407 struct iris_shader_state
*shs
= &ice
->state
.shaders
[s
];
6408 enum pipe_shader_type p_stage
= stage_to_pipe(s
);
6410 if (!(res
->bind_stages
& (1 << s
)))
6413 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
6414 /* Skip constant buffer 0, it's for regular uniforms, not UBOs */
6415 uint32_t bound_cbufs
= shs
->bound_cbufs
& ~1u;
6416 while (bound_cbufs
) {
6417 const int i
= u_bit_scan(&bound_cbufs
);
6418 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[i
];
6419 struct iris_state_ref
*surf_state
= &shs
->constbuf_surf_state
[i
];
6421 if (res
->bo
== iris_resource_bo(cbuf
->buffer
)) {
6422 pipe_resource_reference(&surf_state
->res
, NULL
);
6423 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< s
;
6428 if (res
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
6429 uint32_t bound_ssbos
= shs
->bound_ssbos
;
6430 while (bound_ssbos
) {
6431 const int i
= u_bit_scan(&bound_ssbos
);
6432 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[i
];
6434 if (res
->bo
== iris_resource_bo(ssbo
->buffer
)) {
6435 struct pipe_shader_buffer buf
= {
6436 .buffer
= &res
->base
,
6437 .buffer_offset
= ssbo
->buffer_offset
,
6438 .buffer_size
= ssbo
->buffer_size
,
6440 iris_set_shader_buffers(ctx
, p_stage
, i
, 1, &buf
,
6441 (shs
->writable_ssbos
>> i
) & 1);
6446 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
6447 uint32_t bound_sampler_views
= shs
->bound_sampler_views
;
6448 while (bound_sampler_views
) {
6449 const int i
= u_bit_scan(&bound_sampler_views
);
6450 struct iris_sampler_view
*isv
= shs
->textures
[i
];
6452 if (res
->bo
== iris_resource_bo(isv
->base
.texture
)) {
6453 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
6454 &isv
->surface_state
,
6455 isv
->res
->aux
.sampler_usages
);
6457 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
6458 isv
->view
.format
, isv
->view
.swizzle
,
6459 isv
->base
.u
.buf
.offset
,
6460 isv
->base
.u
.buf
.size
);
6461 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< s
;
6466 if (res
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
6467 uint32_t bound_image_views
= shs
->bound_image_views
;
6468 while (bound_image_views
) {
6469 const int i
= u_bit_scan(&bound_image_views
);
6470 struct iris_image_view
*iv
= &shs
->image
[i
];
6472 if (res
->bo
== iris_resource_bo(iv
->base
.resource
)) {
6473 iris_set_shader_images(ctx
, p_stage
, i
, 1, &iv
->base
);
6480 /* ------------------------------------------------------------------- */
6483 flags_to_post_sync_op(uint32_t flags
)
6485 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
6486 return WriteImmediateData
;
6488 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
6489 return WritePSDepthCount
;
6491 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
6492 return WriteTimestamp
;
6498 * Do the given flags have a Post Sync or LRI Post Sync operation?
6500 static enum pipe_control_flags
6501 get_post_sync_flags(enum pipe_control_flags flags
)
6503 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
6504 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6505 PIPE_CONTROL_WRITE_TIMESTAMP
|
6506 PIPE_CONTROL_LRI_POST_SYNC_OP
;
6508 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
6509 * "LRI Post Sync Operation". So more than one bit set would be illegal.
6511 assert(util_bitcount(flags
) <= 1);
6516 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
6519 * Emit a series of PIPE_CONTROL commands, taking into account any
6520 * workarounds necessary to actually accomplish the caller's request.
6522 * Unless otherwise noted, spec quotations in this function come from:
6524 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
6525 * Restrictions for PIPE_CONTROL.
6527 * You should not use this function directly. Use the helpers in
6528 * iris_pipe_control.c instead, which may split the pipe control further.
6531 iris_emit_raw_pipe_control(struct iris_batch
*batch
,
6538 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6539 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
6540 enum pipe_control_flags non_lri_post_sync_flags
=
6541 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
6543 /* Recursive PIPE_CONTROL workarounds --------------------------------
6544 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
6546 * We do these first because we want to look at the original operation,
6547 * rather than any workarounds we set.
6549 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
6550 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
6551 * lists several workarounds:
6553 * "Project: SKL, KBL, BXT
6555 * If the VF Cache Invalidation Enable is set to a 1 in a
6556 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
6557 * sets to 0, with the VF Cache Invalidation Enable set to 0
6558 * needs to be sent prior to the PIPE_CONTROL with VF Cache
6559 * Invalidation Enable set to a 1."
6561 iris_emit_raw_pipe_control(batch
,
6562 "workaround: recursive VF cache invalidate",
6566 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
6567 /* Project: SKL / Argument: LRI Post Sync Operation [23]
6569 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6570 * programmed prior to programming a PIPECONTROL command with "LRI
6571 * Post Sync Operation" in GPGPU mode of operation (i.e when
6572 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
6574 * The same text exists a few rows below for Post Sync Op.
6576 iris_emit_raw_pipe_control(batch
,
6577 "workaround: CS stall before gpgpu post-sync",
6578 PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
6581 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
6583 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
6584 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
6585 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
6587 iris_emit_raw_pipe_control(batch
,
6588 "workaround: PC flush before RT flush",
6589 PIPE_CONTROL_FLUSH_ENABLE
, bo
, offset
, imm
);
6592 /* "Flush Types" workarounds ---------------------------------------------
6593 * We do these now because they may add post-sync operations or CS stalls.
6596 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
6597 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
6599 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
6600 * 'Write PS Depth Count' or 'Write Timestamp'."
6603 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6604 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6605 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6606 bo
= batch
->screen
->workaround_bo
;
6610 /* #1130 from Gen10 workarounds page:
6612 * "Enable Depth Stall on every Post Sync Op if Render target Cache
6613 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
6614 * board stall if Render target cache flush is enabled."
6616 * Applicable to CNL B0 and C0 steppings only.
6618 * The wording here is unclear, and this workaround doesn't look anything
6619 * like the internal bug report recommendations, but leave it be for now...
6621 if (GEN_GEN
== 10) {
6622 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
6623 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6624 } else if (flags
& non_lri_post_sync_flags
) {
6625 flags
|= PIPE_CONTROL_DEPTH_STALL
;
6629 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
6630 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
6632 * "This bit must be DISABLED for operations other than writing
6635 * This seems like nonsense. An Ivybridge workaround requires us to
6636 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
6637 * operation. Gen8+ requires us to emit depth stalls and depth cache
6638 * flushes together. So, it's hard to imagine this means anything other
6639 * than "we originally intended this to be used for PS_DEPTH_COUNT".
6641 * We ignore the supposed restriction and do nothing.
6645 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6646 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6647 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
6649 * "This bit must be DISABLED for End-of-pipe (Read) fences,
6650 * PS_DEPTH_COUNT or TIMESTAMP queries."
6652 * TODO: Implement end-of-pipe checking.
6654 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6655 PIPE_CONTROL_WRITE_TIMESTAMP
)));
6658 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6659 /* From the PIPE_CONTROL instruction table, bit 1:
6661 * "This bit is ignored if Depth Stall Enable is set.
6662 * Further, the render cache is not flushed even if Write Cache
6663 * Flush Enable bit is set."
6665 * We assert that the caller doesn't do this combination, to try and
6666 * prevent mistakes. It shouldn't hurt the GPU, though.
6668 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
6669 * and "Render Target Flush" combo is explicitly required for BTI
6670 * update workarounds.
6672 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
6673 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
6676 /* PIPE_CONTROL page workarounds ------------------------------------- */
6678 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
6679 /* From the PIPE_CONTROL page itself:
6682 * Restriction: Pipe_control with CS-stall bit set must be issued
6683 * before a pipe-control command that has the State Cache
6684 * Invalidate bit set."
6686 flags
|= PIPE_CONTROL_CS_STALL
;
6689 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
6690 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
6693 * SW must always program Post-Sync Operation to "Write Immediate
6694 * Data" when Flush LLC is set."
6696 * For now, we just require the caller to do it.
6698 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
6701 /* "Post-Sync Operation" workarounds -------------------------------- */
6703 /* Project: All / Argument: Global Snapshot Count Reset [19]
6705 * "This bit must not be exercised on any product.
6706 * Requires stall bit ([20] of DW1) set."
6708 * We don't use this, so we just assert that it isn't used. The
6709 * PIPE_CONTROL instruction page indicates that they intended this
6710 * as a debug feature and don't think it is useful in production,
6711 * but it may actually be usable, should we ever want to.
6713 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
6715 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
6716 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
6717 /* Project: All / Arguments:
6719 * - Generic Media State Clear [16]
6720 * - Indirect State Pointers Disable [16]
6722 * "Requires stall bit ([20] of DW1) set."
6724 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
6725 * State Clear) says:
6727 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6728 * programmed prior to programming a PIPECONTROL command with "Media
6729 * State Clear" set in GPGPU mode of operation"
6731 * This is a subset of the earlier rule, so there's nothing to do.
6733 flags
|= PIPE_CONTROL_CS_STALL
;
6736 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
6737 /* Project: All / Argument: Store Data Index
6739 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6742 * For now, we just assert that the caller does this. We might want to
6743 * automatically add a write to the workaround BO...
6745 assert(non_lri_post_sync_flags
!= 0);
6748 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
6749 /* Project: All / Argument: Sync GFDT
6751 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6752 * than '0' or 0x2520[13] must be set."
6754 * For now, we just assert that the caller does this.
6756 assert(non_lri_post_sync_flags
!= 0);
6759 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
6760 /* Project: IVB+ / Argument: TLB inv
6762 * "Requires stall bit ([20] of DW1) set."
6764 * Also, from the PIPE_CONTROL instruction table:
6767 * Post Sync Operation or CS stall must be set to ensure a TLB
6768 * invalidation occurs. Otherwise no cycle will occur to the TLB
6769 * cache to invalidate."
6771 * This is not a subset of the earlier rule, so there's nothing to do.
6773 flags
|= PIPE_CONTROL_CS_STALL
;
6776 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
6777 /* TODO: The big Skylake GT4 post sync op workaround */
6780 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
6782 if (IS_COMPUTE_PIPELINE(batch
)) {
6783 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
6784 /* Project: SKL+ / Argument: Tex Invalidate
6785 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
6787 flags
|= PIPE_CONTROL_CS_STALL
;
6790 if (GEN_GEN
== 8 && (post_sync_flags
||
6791 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
6792 PIPE_CONTROL_DEPTH_STALL
|
6793 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6794 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6795 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
6796 /* Project: BDW / Arguments:
6798 * - LRI Post Sync Operation [23]
6799 * - Post Sync Op [15:14]
6801 * - Depth Stall [13]
6802 * - Render Target Cache Flush [12]
6803 * - Depth Cache Flush [0]
6804 * - DC Flush Enable [5]
6806 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
6809 flags
|= PIPE_CONTROL_CS_STALL
;
6811 /* Also, from the PIPE_CONTROL instruction table, bit 20:
6814 * This bit must be always set when PIPE_CONTROL command is
6815 * programmed by GPGPU and MEDIA workloads, except for the cases
6816 * when only Read Only Cache Invalidation bits are set (State
6817 * Cache Invalidation Enable, Instruction cache Invalidation
6818 * Enable, Texture Cache Invalidation Enable, Constant Cache
6819 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
6820 * need not implemented when FF_DOP_CG is disable via "Fixed
6821 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
6823 * It sounds like we could avoid CS stalls in some cases, but we
6824 * don't currently bother. This list isn't exactly the list above,
6830 /* "Stall" workarounds ----------------------------------------------
6831 * These have to come after the earlier ones because we may have added
6832 * some additional CS stalls above.
6835 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
6836 /* Project: PRE-SKL, VLV, CHV
6838 * "[All Stepping][All SKUs]:
6840 * One of the following must also be set:
6842 * - Render Target Cache Flush Enable ([12] of DW1)
6843 * - Depth Cache Flush Enable ([0] of DW1)
6844 * - Stall at Pixel Scoreboard ([1] of DW1)
6845 * - Depth Stall ([13] of DW1)
6846 * - Post-Sync Operation ([13] of DW1)
6847 * - DC Flush Enable ([5] of DW1)"
6849 * If we don't already have one of those bits set, we choose to add
6850 * "Stall at Pixel Scoreboard". Some of the other bits require a
6851 * CS stall as a workaround (see above), which would send us into
6852 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
6853 * appears to be safe, so we choose that.
6855 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6856 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6857 PIPE_CONTROL_WRITE_IMMEDIATE
|
6858 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6859 PIPE_CONTROL_WRITE_TIMESTAMP
|
6860 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
6861 PIPE_CONTROL_DEPTH_STALL
|
6862 PIPE_CONTROL_DATA_CACHE_FLUSH
;
6863 if (!(flags
& wa_bits
))
6864 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6867 /* Emit --------------------------------------------------------------- */
6869 if (INTEL_DEBUG
& DEBUG_PIPE_CONTROL
) {
6871 " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64
"]: %s\n",
6872 (flags
& PIPE_CONTROL_FLUSH_ENABLE
) ? "PipeCon " : "",
6873 (flags
& PIPE_CONTROL_CS_STALL
) ? "CS " : "",
6874 (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) ? "Scoreboard " : "",
6875 (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) ? "VF " : "",
6876 (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) ? "RT " : "",
6877 (flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
) ? "Const " : "",
6878 (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
) ? "TC " : "",
6879 (flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
) ? "DC " : "",
6880 (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
) ? "ZFlush " : "",
6881 (flags
& PIPE_CONTROL_DEPTH_STALL
) ? "ZStall " : "",
6882 (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
) ? "State " : "",
6883 (flags
& PIPE_CONTROL_TLB_INVALIDATE
) ? "TLB " : "",
6884 (flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
) ? "Inst " : "",
6885 (flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
) ? "MediaClear " : "",
6886 (flags
& PIPE_CONTROL_NOTIFY_ENABLE
) ? "Notify " : "",
6887 (flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) ?
6889 (flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
) ?
6891 (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
) ? "WriteImm " : "",
6892 (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
) ? "WriteZCount " : "",
6893 (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
) ? "WriteTimestamp " : "",
6897 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
6898 pc
.LRIPostSyncOperation
= NoLRIOperation
;
6899 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
6900 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
6901 pc
.StoreDataIndex
= 0;
6902 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
6903 pc
.GlobalSnapshotCountReset
=
6904 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
6905 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
6906 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
6907 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6908 pc
.RenderTargetCacheFlushEnable
=
6909 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
6910 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
6911 pc
.StateCacheInvalidationEnable
=
6912 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
6913 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
6914 pc
.ConstantCacheInvalidationEnable
=
6915 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
6916 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
6917 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
6918 pc
.InstructionCacheInvalidateEnable
=
6919 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
6920 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
6921 pc
.IndirectStatePointersDisable
=
6922 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
6923 pc
.TextureCacheInvalidationEnable
=
6924 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
6925 pc
.Address
= rw_bo(bo
, offset
);
6926 pc
.ImmediateData
= imm
;
6931 genX(emit_urb_setup
)(struct iris_context
*ice
,
6932 struct iris_batch
*batch
,
6933 const unsigned size
[4],
6934 bool tess_present
, bool gs_present
)
6936 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6937 const unsigned push_size_kB
= 32;
6938 unsigned entries
[4];
6941 ice
->shaders
.last_vs_entry_size
= size
[MESA_SHADER_VERTEX
];
6943 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
6944 1024 * ice
->shaders
.urb_size
,
6945 tess_present
, gs_present
,
6946 size
, entries
, start
);
6948 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
6949 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
6950 urb
._3DCommandSubOpcode
+= i
;
6951 urb
.VSURBStartingAddress
= start
[i
];
6952 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
6953 urb
.VSNumberofURBEntries
= entries
[i
];
6960 * Preemption on Gen9 has to be enabled or disabled in various cases.
6962 * See these workarounds for preemption:
6963 * - WaDisableMidObjectPreemptionForGSLineStripAdj
6964 * - WaDisableMidObjectPreemptionForTrifanOrPolygon
6965 * - WaDisableMidObjectPreemptionForLineLoop
6968 * We don't put this in the vtable because it's only used on Gen9.
6971 gen9_toggle_preemption(struct iris_context
*ice
,
6972 struct iris_batch
*batch
,
6973 const struct pipe_draw_info
*draw
)
6975 struct iris_genx_state
*genx
= ice
->state
.genx
;
6976 bool object_preemption
= true;
6978 /* WaDisableMidObjectPreemptionForGSLineStripAdj
6980 * "WA: Disable mid-draw preemption when draw-call is a linestrip_adj
6981 * and GS is enabled."
6983 if (draw
->mode
== PIPE_PRIM_LINE_STRIP_ADJACENCY
&&
6984 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
6985 object_preemption
= false;
6987 /* WaDisableMidObjectPreemptionForTrifanOrPolygon
6989 * "TriFan miscompare in Execlist Preemption test. Cut index that is
6990 * on a previous context. End the previous, the resume another context
6991 * with a tri-fan or polygon, and the vertex count is corrupted. If we
6992 * prempt again we will cause corruption.
6994 * WA: Disable mid-draw preemption when draw-call has a tri-fan."
6996 if (draw
->mode
== PIPE_PRIM_TRIANGLE_FAN
)
6997 object_preemption
= false;
6999 /* WaDisableMidObjectPreemptionForLineLoop
7001 * "VF Stats Counters Missing a vertex when preemption enabled.
7003 * WA: Disable mid-draw preemption when the draw uses a lineloop
7006 if (draw
->mode
== PIPE_PRIM_LINE_LOOP
)
7007 object_preemption
= false;
7011 * "VF is corrupting GAFS data when preempted on an instance boundary
7012 * and replayed with instancing enabled.
7014 * WA: Disable preemption when using instanceing."
7016 if (draw
->instance_count
> 1)
7017 object_preemption
= false;
7019 if (genx
->object_preemption
!= object_preemption
) {
7020 iris_enable_obj_preemption(batch
, object_preemption
);
7021 genx
->object_preemption
= object_preemption
;
7027 iris_lost_genx_state(struct iris_context
*ice
, struct iris_batch
*batch
)
7029 struct iris_genx_state
*genx
= ice
->state
.genx
;
7031 memset(genx
->last_index_buffer
, 0, sizeof(genx
->last_index_buffer
));
7035 iris_emit_mi_report_perf_count(struct iris_batch
*batch
,
7037 uint32_t offset_in_bytes
,
7040 iris_emit_cmd(batch
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
7041 mi_rpc
.MemoryAddress
= rw_bo(bo
, offset_in_bytes
);
7042 mi_rpc
.ReportID
= report_id
;
7047 * Update the pixel hashing modes that determine the balancing of PS threads
7048 * across subslices and slices.
7050 * \param width Width bound of the rendering area (already scaled down if \p
7051 * scale is greater than 1).
7052 * \param height Height bound of the rendering area (already scaled down if \p
7053 * scale is greater than 1).
7054 * \param scale The number of framebuffer samples that could potentially be
7055 * affected by an individual channel of the PS thread. This is
7056 * typically one for single-sampled rendering, but for operations
7057 * like CCS resolves and fast clears a single PS invocation may
7058 * update a huge number of pixels, in which case a finer
7059 * balancing is desirable in order to maximally utilize the
7060 * bandwidth available. UINT_MAX can be used as shorthand for
7061 * "finest hashing mode available".
7064 genX(emit_hashing_mode
)(struct iris_context
*ice
, struct iris_batch
*batch
,
7065 unsigned width
, unsigned height
, unsigned scale
)
7068 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
7069 const unsigned slice_hashing
[] = {
7070 /* Because all Gen9 platforms with more than one slice require
7071 * three-way subslice hashing, a single "normal" 16x16 slice hashing
7072 * block is guaranteed to suffer from substantial imbalance, with one
7073 * subslice receiving twice as much work as the other two in the
7076 * The performance impact of that would be particularly severe when
7077 * three-way hashing is also in use for slice balancing (which is the
7078 * case for all Gen9 GT4 platforms), because one of the slices
7079 * receives one every three 16x16 blocks in either direction, which
7080 * is roughly the periodicity of the underlying subslice imbalance
7081 * pattern ("roughly" because in reality the hardware's
7082 * implementation of three-way hashing doesn't do exact modulo 3
7083 * arithmetic, which somewhat decreases the magnitude of this effect
7084 * in practice). This leads to a systematic subslice imbalance
7085 * within that slice regardless of the size of the primitive. The
7086 * 32x32 hashing mode guarantees that the subslice imbalance within a
7087 * single slice hashing block is minimal, largely eliminating this
7091 /* Finest slice hashing mode available. */
7094 const unsigned subslice_hashing
[] = {
7095 /* 16x16 would provide a slight cache locality benefit especially
7096 * visible in the sampler L1 cache efficiency of low-bandwidth
7097 * non-LLC platforms, but it comes at the cost of greater subslice
7098 * imbalance for primitives of dimensions approximately intermediate
7099 * between 16x4 and 16x16.
7102 /* Finest subslice hashing mode available. */
7105 /* Dimensions of the smallest hashing block of a given hashing mode. If
7106 * the rendering area is smaller than this there can't possibly be any
7107 * benefit from switching to this mode, so we optimize out the
7110 const unsigned min_size
[][2] = {
7114 const unsigned idx
= scale
> 1;
7116 if (width
> min_size
[idx
][0] || height
> min_size
[idx
][1]) {
7119 iris_pack_state(GENX(GT_MODE
), >_mode
, reg
) {
7120 reg
.SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0);
7121 reg
.SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0);
7122 reg
.SubsliceHashing
= subslice_hashing
[idx
];
7123 reg
.SubsliceHashingMask
= -1;
7126 iris_emit_raw_pipe_control(batch
,
7127 "workaround: CS stall before GT_MODE LRI",
7128 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
7129 PIPE_CONTROL_CS_STALL
,
7132 iris_emit_lri(batch
, GT_MODE
, gt_mode
);
7134 ice
->state
.current_hash_scale
= scale
;
7140 genX(init_state
)(struct iris_context
*ice
)
7142 struct pipe_context
*ctx
= &ice
->ctx
;
7143 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
7145 ctx
->create_blend_state
= iris_create_blend_state
;
7146 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
7147 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
7148 ctx
->create_sampler_state
= iris_create_sampler_state
;
7149 ctx
->create_sampler_view
= iris_create_sampler_view
;
7150 ctx
->create_surface
= iris_create_surface
;
7151 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
7152 ctx
->bind_blend_state
= iris_bind_blend_state
;
7153 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
7154 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
7155 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
7156 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
7157 ctx
->delete_blend_state
= iris_delete_state
;
7158 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
7159 ctx
->delete_rasterizer_state
= iris_delete_state
;
7160 ctx
->delete_sampler_state
= iris_delete_state
;
7161 ctx
->delete_vertex_elements_state
= iris_delete_state
;
7162 ctx
->set_blend_color
= iris_set_blend_color
;
7163 ctx
->set_clip_state
= iris_set_clip_state
;
7164 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
7165 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
7166 ctx
->set_shader_images
= iris_set_shader_images
;
7167 ctx
->set_sampler_views
= iris_set_sampler_views
;
7168 ctx
->set_tess_state
= iris_set_tess_state
;
7169 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
7170 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
7171 ctx
->set_sample_mask
= iris_set_sample_mask
;
7172 ctx
->set_scissor_states
= iris_set_scissor_states
;
7173 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
7174 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
7175 ctx
->set_viewport_states
= iris_set_viewport_states
;
7176 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
7177 ctx
->surface_destroy
= iris_surface_destroy
;
7178 ctx
->draw_vbo
= iris_draw_vbo
;
7179 ctx
->launch_grid
= iris_launch_grid
;
7180 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
7181 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
7182 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
7184 ice
->vtbl
.destroy_state
= iris_destroy_state
;
7185 ice
->vtbl
.init_render_context
= iris_init_render_context
;
7186 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
7187 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
7188 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
7189 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
7190 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
7191 ice
->vtbl
.emit_mi_report_perf_count
= iris_emit_mi_report_perf_count
;
7192 ice
->vtbl
.rebind_buffer
= iris_rebind_buffer
;
7193 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
7194 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
7195 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
7196 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
7197 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
7198 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
7199 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
7200 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
7201 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
7202 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
7203 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
7204 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
7205 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
7206 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
7207 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
7208 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
7209 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
7210 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
7211 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
7212 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
7213 ice
->vtbl
.mocs
= mocs
;
7214 ice
->vtbl
.lost_genx_state
= iris_lost_genx_state
;
7216 ice
->state
.dirty
= ~0ull;
7218 ice
->state
.statistics_counters_enabled
= true;
7220 ice
->state
.sample_mask
= 0xffff;
7221 ice
->state
.num_viewports
= 1;
7222 ice
->state
.prim_mode
= PIPE_PRIM_MAX
;
7223 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
7224 ice
->draw
.derived_params
.drawid
= -1;
7226 /* Make a 1x1x1 null surface for unbound textures */
7227 void *null_surf_map
=
7228 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
7229 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
7230 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
7231 ice
->state
.unbound_tex
.offset
+=
7232 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
7234 /* Default all scissor rectangles to be empty regions. */
7235 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
7236 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
7237 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,