2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "util/u_upload_mgr.h"
44 #include "intel/compiler/brw_compiler.h"
45 #include "intel/common/gen_l3_config.h"
46 #include "intel/common/gen_sample_positions.h"
47 #include "iris_batch.h"
48 #include "iris_context.h"
49 #include "iris_pipe.h"
50 #include "iris_resource.h"
52 #define __gen_address_type struct iris_address
53 #define __gen_user_data struct iris_batch
55 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
58 __gen_combine_address(struct iris_batch
*batch
, void *location
,
59 struct iris_address addr
, uint32_t delta
)
61 uint64_t result
= addr
.offset
+ delta
;
64 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
65 /* Assume this is a general address, not relative to a base. */
66 result
+= addr
.bo
->gtt_offset
;
72 #define __genxml_cmd_length(cmd) cmd ## _length
73 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
74 #define __genxml_cmd_header(cmd) cmd ## _header
75 #define __genxml_cmd_pack(cmd) cmd ## _pack
77 #define _iris_pack_command(batch, cmd, dst, name) \
78 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
79 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
80 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
84 #define iris_pack_command(cmd, dst, name) \
85 _iris_pack_command(NULL, cmd, dst, name)
87 #define iris_pack_state(cmd, dst, name) \
88 for (struct cmd name = {}, \
89 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
90 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
93 #define iris_emit_cmd(batch, cmd, name) \
94 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
96 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
98 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
99 for (uint32_t i = 0; i < num_dwords; i++) \
100 dw[i] = (dwords0)[i] | (dwords1)[i]; \
101 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
104 #include "genxml/genX_pack.h"
105 #include "genxml/gen_macros.h"
106 #include "genxml/genX_bits.h"
108 #define MOCS_WB (2 << 1)
110 UNUSED
static void pipe_asserts()
112 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
114 /* pipe_logicop happens to match the hardware. */
115 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
116 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
117 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
118 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
119 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
120 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
121 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
122 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
123 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
124 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
125 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
126 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
127 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
128 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
129 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
130 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
132 /* pipe_blend_func happens to match the hardware. */
133 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
134 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
135 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
136 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
137 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
138 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
139 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
140 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
141 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
142 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
143 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
144 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
145 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
146 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
147 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
148 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
149 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
150 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
151 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
153 /* pipe_blend_func happens to match the hardware. */
154 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
155 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
156 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
157 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
158 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
160 /* pipe_stencil_op happens to match the hardware. */
161 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
162 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
163 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
164 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
165 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
166 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
167 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
168 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
170 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
171 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
172 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
177 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
179 static const unsigned map
[] = {
180 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
181 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
182 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
183 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
184 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
185 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
186 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
187 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
188 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
189 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
190 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
191 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
192 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
193 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
194 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
197 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
201 translate_compare_func(enum pipe_compare_func pipe_func
)
203 static const unsigned map
[] = {
204 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
205 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
206 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
207 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
208 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
209 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
210 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
211 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
213 return map
[pipe_func
];
217 translate_shadow_func(enum pipe_compare_func pipe_func
)
219 /* Gallium specifies the result of shadow comparisons as:
221 * 1 if ref <op> texel,
226 * 0 if texel <op> ref,
229 * So we need to flip the operator and also negate.
231 static const unsigned map
[] = {
232 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
233 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
234 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
235 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
236 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
237 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
238 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
239 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
241 return map
[pipe_func
];
245 translate_cull_mode(unsigned pipe_face
)
247 static const unsigned map
[4] = {
248 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
249 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
250 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
251 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
253 return map
[pipe_face
];
257 translate_fill_mode(unsigned pipe_polymode
)
259 static const unsigned map
[4] = {
260 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
261 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
262 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
263 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
265 return map
[pipe_polymode
];
268 static struct iris_address
269 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
272 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
276 * Returns the BO's address relative to the appropriate base address.
278 * All of our base addresses are programmed to the start of a 4GB region,
279 * so simply returning the bottom 32 bits of the BO address will give us
280 * the offset from whatever base address corresponds to that memory region.
283 bo_offset_from_base_address(struct pipe_resource
*res
)
285 struct iris_bo
*bo
= ((struct iris_resource
*) res
)->bo
;
287 /* This only works for buffers in the memory zones corresponding to a
288 * base address - the top, unbounded memory zone doesn't have a base.
290 assert(bo
->gtt_offset
< 3 * (1ull << 32));
291 return bo
->gtt_offset
;
295 stream_state(struct iris_batch
*batch
,
296 struct u_upload_mgr
*uploader
,
299 uint32_t *out_offset
)
301 struct pipe_resource
*res
= NULL
;
304 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, &res
, &ptr
);
306 struct iris_bo
*bo
= ((struct iris_resource
*) res
)->bo
;
307 iris_use_pinned_bo(batch
, bo
, false);
309 *out_offset
+= bo_offset_from_base_address(res
);
311 pipe_resource_reference(&res
, NULL
);
317 emit_state(struct iris_batch
*batch
,
318 struct u_upload_mgr
*uploader
,
324 uint32_t *map
= stream_state(batch
, uploader
, size
, alignment
, &offset
);
327 memcpy(map
, data
, size
);
333 iris_init_render_context(struct iris_screen
*screen
,
334 struct iris_batch
*batch
,
335 struct iris_vtable
*vtbl
,
336 struct pipe_debug_callback
*dbg
)
338 iris_init_batch(batch
, screen
, vtbl
, dbg
, I915_EXEC_RENDER
);
340 /* XXX: PIPE_CONTROLs */
342 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
344 // XXX: MOCS is stupid for this.
345 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
346 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
347 sba
.SurfaceStateMemoryObjectControlState
= MOCS_WB
;
348 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
349 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
350 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
351 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
354 sba
.GeneralStateBaseAddressModifyEnable
= true;
355 sba
.SurfaceStateBaseAddressModifyEnable
= true;
356 sba
.DynamicStateBaseAddressModifyEnable
= true;
357 sba
.IndirectObjectBaseAddressModifyEnable
= true;
358 sba
.InstructionBaseAddressModifyEnable
= true;
359 sba
.GeneralStateBufferSizeModifyEnable
= true;
360 sba
.DynamicStateBufferSizeModifyEnable
= true;
361 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
362 sba
.IndirectObjectBufferSizeModifyEnable
= true;
363 sba
.InstructionBuffersizeModifyEnable
= true;
365 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
366 sba
.SurfaceStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SURFACE_START
);
367 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
369 sba
.GeneralStateBufferSize
= 0xfffff;
370 sba
.IndirectObjectBufferSize
= 0xfffff;
371 sba
.InstructionBufferSize
= 0xfffff;
372 sba
.DynamicStateBufferSize
= 0xfffff;
375 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
376 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
377 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
379 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
380 GEN_SAMPLE_POS_1X(pat
._1xSample
);
381 GEN_SAMPLE_POS_2X(pat
._2xSample
);
382 GEN_SAMPLE_POS_4X(pat
._4xSample
);
383 GEN_SAMPLE_POS_8X(pat
._8xSample
);
384 GEN_SAMPLE_POS_16X(pat
._16xSample
);
386 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
387 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
388 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
389 /* XXX: may need to set an offset for origin-UL framebuffers */
390 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
392 /* Just assign a static partitioning. */
393 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
394 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
395 alloc
._3DCommandSubOpcode
= 18 + i
;
396 alloc
.ConstantBufferOffset
= 6 * i
;
397 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
403 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
408 iris_set_blend_color(struct pipe_context
*ctx
,
409 const struct pipe_blend_color
*state
)
411 struct iris_context
*ice
= (struct iris_context
*) ctx
;
413 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
414 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
417 struct iris_blend_state
{
418 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
419 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
420 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
422 bool alpha_to_coverage
; /* for shader key */
426 iris_create_blend_state(struct pipe_context
*ctx
,
427 const struct pipe_blend_state
*state
)
429 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
430 uint32_t *blend_state
= cso
->blend_state
;
432 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
434 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
435 /* pb.HasWriteableRT is filled in at draw time. */
436 /* pb.AlphaTestEnable is filled in at draw time. */
437 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
438 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
440 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
442 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
443 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
444 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
445 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
448 iris_pack_state(GENX(BLEND_STATE
), blend_state
, bs
) {
449 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
450 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
451 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
452 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
453 bs
.ColorDitherEnable
= state
->dither
;
454 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
457 blend_state
+= GENX(BLEND_STATE_length
);
459 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
460 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_state
, be
) {
461 be
.LogicOpEnable
= state
->logicop_enable
;
462 be
.LogicOpFunction
= state
->logicop_func
;
464 be
.PreBlendSourceOnlyClampEnable
= false;
465 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
466 be
.PreBlendColorClampEnable
= true;
467 be
.PostBlendColorClampEnable
= true;
469 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
471 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
472 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
473 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
474 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
475 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
476 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
478 be
.WriteDisableRed
= !(state
->rt
[i
].colormask
& PIPE_MASK_R
);
479 be
.WriteDisableGreen
= !(state
->rt
[i
].colormask
& PIPE_MASK_G
);
480 be
.WriteDisableBlue
= !(state
->rt
[i
].colormask
& PIPE_MASK_B
);
481 be
.WriteDisableAlpha
= !(state
->rt
[i
].colormask
& PIPE_MASK_A
);
483 blend_state
+= GENX(BLEND_STATE_ENTRY_length
);
490 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
492 struct iris_context
*ice
= (struct iris_context
*) ctx
;
493 ice
->state
.cso_blend
= state
;
494 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
495 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
498 struct iris_depth_stencil_alpha_state
{
499 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
500 uint32_t cc_vp
[GENX(CC_VIEWPORT_length
)];
502 struct pipe_alpha_state alpha
; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
506 iris_create_zsa_state(struct pipe_context
*ctx
,
507 const struct pipe_depth_stencil_alpha_state
*state
)
509 struct iris_depth_stencil_alpha_state
*cso
=
510 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
512 cso
->alpha
= state
->alpha
;
514 bool two_sided_stencil
= state
->stencil
[1].enabled
;
516 /* The state tracker needs to optimize away EQUAL writes for us. */
517 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
519 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
520 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
521 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
522 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
523 wmds
.StencilTestFunction
=
524 translate_compare_func(state
->stencil
[0].func
);
525 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
526 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
527 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
528 wmds
.BackfaceStencilTestFunction
=
529 translate_compare_func(state
->stencil
[1].func
);
530 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
531 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
532 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
533 wmds
.StencilBufferWriteEnable
=
534 state
->stencil
[0].writemask
!= 0 ||
535 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
536 wmds
.DepthTestEnable
= state
->depth
.enabled
;
537 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
538 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
539 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
540 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
541 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
542 /* wmds.[Backface]StencilReferenceValue are merged later */
545 iris_pack_state(GENX(CC_VIEWPORT
), cso
->cc_vp
, ccvp
) {
546 ccvp
.MinimumDepth
= state
->depth
.bounds_min
;
547 ccvp
.MaximumDepth
= state
->depth
.bounds_max
;
554 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
556 struct iris_context
*ice
= (struct iris_context
*) ctx
;
557 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
558 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
561 if (!old_cso
|| old_cso
->alpha
.ref_value
!= new_cso
->alpha
.ref_value
) {
562 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
566 ice
->state
.cso_zsa
= new_cso
;
567 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
568 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
571 struct iris_rasterizer_state
{
572 uint32_t sf
[GENX(3DSTATE_SF_length
)];
573 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
574 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
575 uint32_t wm
[GENX(3DSTATE_WM_length
)];
576 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
578 bool flatshade
; /* for shader state */
579 bool clamp_fragment_color
; /* for shader state */
580 bool light_twoside
; /* for shader state */
581 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
582 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
583 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
584 uint16_t sprite_coord_enable
;
588 iris_create_rasterizer_state(struct pipe_context
*ctx
,
589 const struct pipe_rasterizer_state
*state
)
591 struct iris_rasterizer_state
*cso
=
592 malloc(sizeof(struct iris_rasterizer_state
));
595 point_quad_rasterization
-> SBE
?
600 force_persample_interp
- ?
603 offset_units_unscaled
- cap
not exposed
607 cso
->flatshade
= state
->flatshade
;
608 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
609 cso
->light_twoside
= state
->light_twoside
;
610 cso
->rasterizer_discard
= state
->rasterizer_discard
;
611 cso
->half_pixel_center
= state
->half_pixel_center
;
612 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
613 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
615 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
616 sf
.StatisticsEnable
= true;
617 sf
.ViewportTransformEnable
= true;
618 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
619 sf
.LineEndCapAntialiasingRegionWidth
=
620 state
->line_smooth
? _10pixels
: _05pixels
;
621 sf
.LastPixelEnable
= state
->line_last_pixel
;
622 sf
.LineWidth
= state
->line_width
;
623 sf
.SmoothPointEnable
= state
->point_smooth
;
624 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
625 sf
.PointWidth
= state
->point_size
;
627 if (state
->flatshade_first
) {
628 sf
.TriangleStripListProvokingVertexSelect
= 2;
629 sf
.TriangleFanProvokingVertexSelect
= 2;
630 sf
.LineStripListProvokingVertexSelect
= 1;
632 sf
.TriangleFanProvokingVertexSelect
= 1;
637 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
638 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
639 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
640 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
641 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
642 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
643 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
644 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
645 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
646 rr
.GlobalDepthOffsetConstant
= state
->offset_units
;
647 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
648 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
649 rr
.SmoothPointEnable
= state
->point_smooth
;
650 rr
.AntialiasingEnable
= state
->line_smooth
;
651 rr
.ScissorRectangleEnable
= state
->scissor
;
652 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
653 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
654 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
657 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
658 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
659 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
661 cl
.StatisticsEnable
= true;
662 cl
.EarlyCullEnable
= true;
663 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
664 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
665 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
666 cl
.GuardbandClipTestEnable
= true;
667 cl
.ClipMode
= CLIPMODE_NORMAL
;
668 cl
.ClipEnable
= true;
669 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
670 cl
.MinimumPointWidth
= 0.125;
671 cl
.MaximumPointWidth
= 255.875;
673 if (state
->flatshade_first
) {
674 cl
.TriangleStripListProvokingVertexSelect
= 2;
675 cl
.TriangleFanProvokingVertexSelect
= 2;
676 cl
.LineStripListProvokingVertexSelect
= 1;
678 cl
.TriangleFanProvokingVertexSelect
= 1;
682 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
683 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
684 * filled in at draw time from the FS program.
686 wm
.LineAntialiasingRegionWidth
= _10pixels
;
687 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
688 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
689 wm
.StatisticsEnable
= true;
690 wm
.LineStippleEnable
= state
->line_stipple_enable
;
691 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
694 /* Remap from 0..255 back to 1..256 */
695 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
697 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
698 line
.LineStipplePattern
= state
->line_stipple_pattern
;
699 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
700 line
.LineStippleRepeatCount
= line_stipple_factor
;
707 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
709 struct iris_context
*ice
= (struct iris_context
*) ctx
;
710 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
711 struct iris_rasterizer_state
*new_cso
= state
;
714 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
715 if (!old_cso
|| memcmp(old_cso
->line_stipple
, new_cso
->line_stipple
,
716 sizeof(old_cso
->line_stipple
)) != 0) {
717 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
721 old_cso
->half_pixel_center
!= new_cso
->half_pixel_center
) {
722 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
726 ice
->state
.cso_rast
= new_cso
;
727 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
731 translate_wrap(unsigned pipe_wrap
)
733 static const unsigned map
[] = {
734 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
735 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
736 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
737 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
738 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
739 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
740 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1, // XXX: ???
741 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1, // XXX: ???
743 return map
[pipe_wrap
];
747 * Return true if the given wrap mode requires the border color to exist.
750 wrap_mode_needs_border_color(unsigned wrap_mode
)
752 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
756 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
758 static const unsigned map
[] = {
759 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
760 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
761 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
763 return map
[pipe_mip
];
766 struct iris_sampler_state
{
767 struct pipe_sampler_state base
;
769 bool needs_border_color
;
771 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
775 iris_create_sampler_state(struct pipe_context
*pctx
,
776 const struct pipe_sampler_state
*state
)
778 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
783 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
784 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
786 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
787 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
788 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
790 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
791 wrap_mode_needs_border_color(wrap_t
) ||
792 wrap_mode_needs_border_color(wrap_r
);
794 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
795 samp
.TCXAddressControlMode
= wrap_s
;
796 samp
.TCYAddressControlMode
= wrap_t
;
797 samp
.TCZAddressControlMode
= wrap_r
;
798 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
799 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
800 samp
.MinModeFilter
= state
->min_img_filter
;
801 samp
.MagModeFilter
= state
->mag_img_filter
;
802 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
803 samp
.MaximumAnisotropy
= RATIO21
;
805 if (state
->max_anisotropy
>= 2) {
806 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
807 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
808 samp
.AnisotropicAlgorithm
= EWAApproximation
;
811 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
812 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
814 samp
.MaximumAnisotropy
=
815 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
818 /* Set address rounding bits if not using nearest filtering. */
819 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
820 samp
.UAddressMinFilterRoundingEnable
= true;
821 samp
.VAddressMinFilterRoundingEnable
= true;
822 samp
.RAddressMinFilterRoundingEnable
= true;
825 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
826 samp
.UAddressMagFilterRoundingEnable
= true;
827 samp
.VAddressMagFilterRoundingEnable
= true;
828 samp
.RAddressMagFilterRoundingEnable
= true;
831 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
832 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
834 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
836 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
837 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
838 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
839 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
841 //samp.BorderColorPointer = <<comes from elsewhere>>
848 iris_bind_sampler_states(struct pipe_context
*ctx
,
849 enum pipe_shader_type p_stage
,
850 unsigned start
, unsigned count
,
853 struct iris_context
*ice
= (struct iris_context
*) ctx
;
854 gl_shader_stage stage
= stage_from_pipe(p_stage
);
856 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
858 /* Assemble the SAMPLER_STATEs into a contiguous chunk of memory
859 * relative to Dynamic State Base Address.
862 u_upload_alloc(ice
->state
.dynamic_uploader
, 0,
863 count
* 4 * GENX(SAMPLER_STATE_length
), 32,
864 &ice
->state
.sampler_table_offset
[stage
],
865 &ice
->state
.sampler_table_resource
[stage
],
870 ice
->state
.sampler_table_offset
[stage
] +=
871 bo_offset_from_base_address(ice
->state
.sampler_table_resource
[stage
]);
873 for (int i
= 0; i
< count
; i
++) {
874 struct iris_sampler_state
*state
= states
[i
];
876 /* Save a pointer to the iris_sampler_state, a few fields need
877 * to inform draw-time decisions.
879 ice
->state
.samplers
[stage
][start
+ i
] = state
;
882 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
884 map
+= GENX(SAMPLER_STATE_length
);
887 ice
->state
.num_samplers
[stage
] = count
;
889 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
892 struct iris_sampler_view
{
893 struct pipe_sampler_view pipe
;
894 struct isl_view view
;
896 /** The resource (BO) holding our SURFACE_STATE. */
897 struct pipe_resource
*surface_state_resource
;
898 unsigned surface_state_offset
;
900 //uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
904 * Convert an swizzle enumeration (i.e. PIPE_SWIZZLE_X) to one of the Gen7.5+
905 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
907 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
910 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
912 * which is simply adding 4 then modding by 8 (or anding with 7).
914 * We then may need to apply workarounds for textureGather hardware bugs.
916 static enum isl_channel_select
917 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
919 return (swizzle
+ 4) & 7;
922 static struct pipe_sampler_view
*
923 iris_create_sampler_view(struct pipe_context
*ctx
,
924 struct pipe_resource
*tex
,
925 const struct pipe_sampler_view
*tmpl
)
927 struct iris_context
*ice
= (struct iris_context
*) ctx
;
928 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
929 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
930 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
935 /* initialize base object */
937 isv
->pipe
.context
= ctx
;
938 isv
->pipe
.texture
= NULL
;
939 pipe_reference_init(&isv
->pipe
.reference
, 1);
940 pipe_resource_reference(&isv
->pipe
.texture
, tex
);
942 /* XXX: do we need brw_get_texture_swizzle hacks here? */
944 isv
->view
= (struct isl_view
) {
945 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
946 .base_level
= tmpl
->u
.tex
.first_level
,
947 .levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1,
948 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
949 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
950 .swizzle
= (struct isl_swizzle
) {
951 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
952 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
953 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
954 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
956 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
960 u_upload_alloc(ice
->state
.surface_uploader
, 0,
961 4 * GENX(RENDER_SURFACE_STATE_length
), 64,
962 &isv
->surface_state_offset
,
963 &isv
->surface_state_resource
,
968 isv
->surface_state_offset
+=
969 bo_offset_from_base_address(isv
->surface_state_resource
);
971 isl_surf_fill_state(&screen
->isl_dev
, map
,
972 .surf
= &itex
->surf
, .view
= &isv
->view
,
974 .address
= itex
->bo
->gtt_offset
);
976 // .clear_color = clear_color,
981 struct iris_surface
{
982 struct pipe_surface pipe
;
983 struct isl_view view
;
985 /** The resource (BO) holding our SURFACE_STATE. */
986 struct pipe_resource
*surface_state_resource
;
987 unsigned surface_state_offset
;
989 // uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
992 static struct pipe_surface
*
993 iris_create_surface(struct pipe_context
*ctx
,
994 struct pipe_resource
*tex
,
995 const struct pipe_surface
*tmpl
)
997 struct iris_context
*ice
= (struct iris_context
*) ctx
;
998 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
999 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1000 struct pipe_surface
*psurf
= &surf
->pipe
;
1001 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
1006 pipe_reference_init(&psurf
->reference
, 1);
1007 pipe_resource_reference(&psurf
->texture
, tex
);
1008 psurf
->context
= ctx
;
1009 psurf
->format
= tmpl
->format
;
1010 psurf
->width
= tex
->width0
;
1011 psurf
->height
= tex
->height0
;
1012 psurf
->texture
= tex
;
1013 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1014 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1015 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1017 surf
->view
= (struct isl_view
) {
1018 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
1019 .base_level
= tmpl
->u
.tex
.level
,
1021 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1022 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1023 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1024 // XXX: DEPTH_BIt, STENCIL_BIT...CUBE_BIT? Other bits?!
1025 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1029 u_upload_alloc(ice
->state
.surface_uploader
, 0,
1030 4 * GENX(RENDER_SURFACE_STATE_length
), 64,
1031 &surf
->surface_state_offset
,
1032 &surf
->surface_state_resource
,
1037 surf
->surface_state_offset
+=
1038 bo_offset_from_base_address(surf
->surface_state_resource
);
1040 isl_surf_fill_state(&screen
->isl_dev
, map
,
1041 .surf
= &itex
->surf
, .view
= &surf
->view
,
1043 .address
= itex
->bo
->gtt_offset
);
1045 // .clear_color = clear_color,
1051 iris_set_sampler_views(struct pipe_context
*ctx
,
1052 enum pipe_shader_type p_stage
,
1053 unsigned start
, unsigned count
,
1054 struct pipe_sampler_view
**views
)
1056 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1057 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1060 for (i
= 0; i
< count
; i
++) {
1061 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1062 &ice
->state
.textures
[stage
][i
], views
[i
]);
1064 for (; i
< ice
->state
.num_textures
[stage
]; i
++) {
1065 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1066 &ice
->state
.textures
[stage
][i
], NULL
);
1069 ice
->state
.num_textures
[stage
] = count
;
1071 // XXX: ice->state.dirty |= (IRIS_DIRTY_BINDING_TABLE_VS << stage);
1075 iris_set_clip_state(struct pipe_context
*ctx
,
1076 const struct pipe_clip_state
*state
)
1081 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1082 const struct pipe_poly_stipple
*state
)
1084 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1085 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1086 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1090 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1092 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1094 ice
->state
.sample_mask
= sample_mask
;
1095 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1099 iris_set_scissor_states(struct pipe_context
*ctx
,
1100 unsigned start_slot
,
1101 unsigned num_scissors
,
1102 const struct pipe_scissor_state
*states
)
1104 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1106 ice
->state
.num_scissors
= num_scissors
;
1108 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1109 ice
->state
.scissors
[start_slot
+ i
] = states
[i
];
1112 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1116 iris_set_stencil_ref(struct pipe_context
*ctx
,
1117 const struct pipe_stencil_ref
*state
)
1119 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1120 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1121 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1125 struct iris_viewport_state
{
1126 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
) * IRIS_MAX_VIEWPORTS
];
1130 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1132 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1137 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1138 float m00
, float m11
, float m30
, float m31
,
1139 float *xmin
, float *xmax
,
1140 float *ymin
, float *ymax
)
1142 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1143 * Strips and Fans documentation:
1145 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1146 * fixed-point "guardband" range supported by the rasterization hardware"
1150 * "In almost all circumstances, if an object’s vertices are actually
1151 * modified by this clamping (i.e., had X or Y coordinates outside of
1152 * the guardband extent the rendered object will not match the intended
1153 * result. Therefore software should take steps to ensure that this does
1154 * not happen - e.g., by clipping objects such that they do not exceed
1155 * these limits after the Drawing Rectangle is applied."
1157 * I believe the fundamental restriction is that the rasterizer (in
1158 * the SF/WM stages) have a limit on the number of pixels that can be
1159 * rasterized. We need to ensure any coordinates beyond the rasterizer
1160 * limit are handled by the clipper. So effectively that limit becomes
1161 * the clipper's guardband size.
1163 * It goes on to say:
1165 * "In addition, in order to be correctly rendered, objects must have a
1166 * screenspace bounding box not exceeding 8K in the X or Y direction.
1167 * This additional restriction must also be comprehended by software,
1168 * i.e., enforced by use of clipping."
1170 * This makes no sense. Gen7+ hardware supports 16K render targets,
1171 * and you definitely need to be able to draw polygons that fill the
1172 * surface. Our assumption is that the rasterizer was limited to 8K
1173 * on Sandybridge, which only supports 8K surfaces, and it was actually
1174 * increased to 16K on Ivybridge and later.
1176 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1178 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1180 if (m00
!= 0 && m11
!= 0) {
1181 /* First, we compute the screen-space render area */
1182 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1183 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1184 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1185 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1187 /* We want the guardband to be centered on that */
1188 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1189 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1190 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1191 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1193 /* Now we need it in native device coordinates */
1194 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1195 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1196 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1197 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1199 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1200 * flipped upside-down. X should be fine though.
1202 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1203 *xmin
= ndc_gb_xmin
;
1204 *xmax
= ndc_gb_xmax
;
1205 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1206 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1208 /* The viewport scales to 0, so nothing will be rendered. */
1218 iris_set_viewport_states(struct pipe_context
*ctx
,
1219 unsigned start_slot
,
1220 unsigned num_viewports
,
1221 const struct pipe_viewport_state
*state
)
1223 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1224 struct iris_viewport_state
*cso
=
1225 malloc(sizeof(struct iris_viewport_state
));
1226 uint32_t *vp_map
= &cso
->sf_cl_vp
[start_slot
];
1228 // XXX: sf_cl_vp is only big enough for one slot, we don't iterate right
1229 for (unsigned i
= 0; i
< num_viewports
; i
++) {
1230 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
1231 vp
.ViewportMatrixElementm00
= state
[i
].scale
[0];
1232 vp
.ViewportMatrixElementm11
= state
[i
].scale
[1];
1233 vp
.ViewportMatrixElementm22
= state
[i
].scale
[2];
1234 vp
.ViewportMatrixElementm30
= state
[i
].translate
[0];
1235 vp
.ViewportMatrixElementm31
= state
[i
].translate
[1];
1236 vp
.ViewportMatrixElementm32
= state
[i
].translate
[2];
1237 /* XXX: in i965 this is computed based on the drawbuffer size,
1238 * but we don't have that here...
1240 vp
.XMinClipGuardband
= -1.0;
1241 vp
.XMaxClipGuardband
= 1.0;
1242 vp
.YMinClipGuardband
= -1.0;
1243 vp
.YMaxClipGuardband
= 1.0;
1244 vp
.XMinViewPort
= viewport_extent(&state
[i
], 0, -1.0f
);
1245 vp
.XMaxViewPort
= viewport_extent(&state
[i
], 0, 1.0f
) - 1;
1246 vp
.YMinViewPort
= viewport_extent(&state
[i
], 1, -1.0f
);
1247 vp
.YMaxViewPort
= viewport_extent(&state
[i
], 1, 1.0f
) - 1;
1250 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
1253 ice
->state
.cso_vp
= cso
;
1254 ice
->state
.num_viewports
= num_viewports
;
1255 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1258 struct iris_depth_state
1260 uint32_t depth_buffer
[GENX(3DSTATE_DEPTH_BUFFER_length
)];
1261 uint32_t hier_depth_buffer
[GENX(3DSTATE_HIER_DEPTH_BUFFER_length
)];
1262 uint32_t stencil_buffer
[GENX(3DSTATE_STENCIL_BUFFER_length
)];
1266 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1267 const struct pipe_framebuffer_state
*state
)
1269 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1270 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1272 if (cso
->samples
!= state
->samples
) {
1273 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1276 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
1277 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1280 cso
->width
= state
->width
;
1281 cso
->height
= state
->height
;
1282 cso
->layers
= state
->layers
;
1283 cso
->samples
= state
->samples
;
1286 for (i
= 0; i
< state
->nr_cbufs
; i
++)
1287 pipe_surface_reference(&cso
->cbufs
[i
], state
->cbufs
[i
]);
1288 for (; i
< cso
->nr_cbufs
; i
++)
1289 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
1291 cso
->nr_cbufs
= state
->nr_cbufs
;
1293 pipe_surface_reference(&cso
->zsbuf
, state
->zsbuf
);
1295 //struct isl_depth_stencil_hiz_emit_info info = {
1299 // XXX: depth buffers
1303 iris_set_constant_buffer(struct pipe_context
*ctx
,
1304 enum pipe_shader_type p_stage
, unsigned index
,
1305 const struct pipe_constant_buffer
*cb
)
1307 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1308 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1310 util_copy_constant_buffer(&ice
->shaders
.state
[stage
].constbuf
[index
], cb
);
1314 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1315 struct pipe_sampler_view
*state
)
1317 struct iris_surface
*isv
= (void *) state
;
1318 pipe_resource_reference(&state
->texture
, NULL
);
1319 pipe_resource_reference(&isv
->surface_state_resource
, NULL
);
1325 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1327 struct iris_surface
*surf
= (void *) p_surf
;
1328 pipe_resource_reference(&p_surf
->texture
, NULL
);
1329 pipe_resource_reference(&surf
->surface_state_resource
, NULL
);
1334 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1339 struct iris_vertex_buffer_state
{
1340 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
1341 struct iris_bo
*bos
[33];
1342 unsigned num_buffers
;
1346 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
1349 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
1350 iris_bo_unreference(cso
->bos
[i
]);
1356 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1357 unsigned start_slot
, unsigned count
,
1358 const struct pipe_vertex_buffer
*buffers
)
1360 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1361 struct iris_vertex_buffer_state
*cso
=
1362 malloc(sizeof(struct iris_vertex_buffer_state
));
1364 /* If there are no buffers, do nothing. We can leave the stale
1365 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1366 * elements that point to them, it should be fine.
1371 iris_free_vertex_buffers(ice
->state
.cso_vertex_buffers
);
1373 cso
->num_buffers
= count
;
1375 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1376 vb
.DWordLength
= 4 * cso
->num_buffers
- 1;
1379 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1381 for (unsigned i
= 0; i
< count
; i
++) {
1382 assert(!buffers
[i
].is_user_buffer
);
1384 struct iris_resource
*res
= (void *) buffers
[i
].buffer
.resource
;
1385 iris_bo_reference(res
->bo
);
1386 cso
->bos
[i
] = res
->bo
;
1388 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1389 vb
.VertexBufferIndex
= start_slot
+ i
;
1391 vb
.AddressModifyEnable
= true;
1392 vb
.BufferPitch
= buffers
[i
].stride
;
1393 vb
.BufferSize
= res
->bo
->size
;
1394 vb
.BufferStartingAddress
=
1395 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffers
[i
].buffer_offset
);
1398 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1401 ice
->state
.cso_vertex_buffers
= cso
;
1402 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1405 struct iris_vertex_element_state
{
1406 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1407 uint32_t vf_instancing
[GENX(3DSTATE_VF_INSTANCING_length
)][33];
1412 iris_create_vertex_elements(struct pipe_context
*ctx
,
1414 const struct pipe_vertex_element
*state
)
1416 struct iris_vertex_element_state
*cso
=
1417 malloc(sizeof(struct iris_vertex_element_state
));
1422 * - create edge flag one
1424 * - if those are necessary, use count + 1/2/3... OR in the length
1426 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
);
1428 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1430 for (int i
= 0; i
< count
; i
++) {
1431 enum isl_format isl_format
=
1432 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1433 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
1434 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
1436 switch (isl_format_get_num_channels(isl_format
)) {
1437 case 0: comp
[0] = VFCOMP_STORE_0
;
1438 case 1: comp
[1] = VFCOMP_STORE_0
;
1439 case 2: comp
[2] = VFCOMP_STORE_0
;
1441 comp
[3] = isl_format_has_int_channel(isl_format
) ? VFCOMP_STORE_1_INT
1442 : VFCOMP_STORE_1_FP
;
1445 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1446 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1448 ve
.SourceElementOffset
= state
[i
].src_offset
;
1449 ve
.SourceElementFormat
= isl_format
;
1450 ve
.Component0Control
= comp
[0];
1451 ve
.Component1Control
= comp
[1];
1452 ve
.Component2Control
= comp
[2];
1453 ve
.Component3Control
= comp
[3];
1456 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->vf_instancing
[i
], vi
) {
1457 vi
.VertexElementIndex
= i
;
1458 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1459 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1462 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1469 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
1471 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1473 ice
->state
.cso_vertex_elements
= state
;
1474 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
1478 iris_create_compute_state(struct pipe_context
*ctx
,
1479 const struct pipe_compute_state
*state
)
1484 static struct pipe_stream_output_target
*
1485 iris_create_stream_output_target(struct pipe_context
*ctx
,
1486 struct pipe_resource
*res
,
1487 unsigned buffer_offset
,
1488 unsigned buffer_size
)
1490 struct pipe_stream_output_target
*t
=
1491 CALLOC_STRUCT(pipe_stream_output_target
);
1495 pipe_reference_init(&t
->reference
, 1);
1496 pipe_resource_reference(&t
->buffer
, res
);
1497 t
->buffer_offset
= buffer_offset
;
1498 t
->buffer_size
= buffer_size
;
1503 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
1504 struct pipe_stream_output_target
*t
)
1506 pipe_resource_reference(&t
->buffer
, NULL
);
1511 iris_set_stream_output_targets(struct pipe_context
*ctx
,
1512 unsigned num_targets
,
1513 struct pipe_stream_output_target
**targets
,
1514 const unsigned *offsets
)
1519 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
1520 const struct brw_vue_map
*last_vue_map
,
1521 bool two_sided_color
,
1522 unsigned *out_offset
,
1523 unsigned *out_length
)
1525 /* The compiler computes the first URB slot without considering COL/BFC
1526 * swizzling (because it doesn't know whether it's enabled), so we need
1527 * to do that here too. This may result in a smaller offset, which
1530 const unsigned first_slot
=
1531 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
1533 /* This becomes the URB read offset (counted in pairs of slots). */
1534 assert(first_slot
% 2 == 0);
1535 *out_offset
= first_slot
/ 2;
1537 /* We need to adjust the inputs read to account for front/back color
1538 * swizzling, as it can make the URB length longer.
1540 for (int c
= 0; c
<= 1; c
++) {
1541 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
1542 /* If two sided color is enabled, the fragment shader's gl_Color
1543 * (COL0) input comes from either the gl_FrontColor (COL0) or
1544 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
1546 if (two_sided_color
)
1547 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1549 /* If front color isn't written, we opt to give them back color
1550 * instead of an undefined value. Switch from COL to BFC.
1552 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
1553 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
1554 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1559 /* Compute the minimum URB Read Length necessary for the FS inputs.
1561 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1562 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1564 * "This field should be set to the minimum length required to read the
1565 * maximum source attribute. The maximum source attribute is indicated
1566 * by the maximum value of the enabled Attribute # Source Attribute if
1567 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1568 * enable is not set.
1569 * read_length = ceiling((max_source_attr + 1) / 2)
1571 * [errata] Corruption/Hang possible if length programmed larger than
1574 * Similar text exists for Ivy Bridge.
1576 * We find the last URB slot that's actually read by the FS.
1578 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
1579 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
1580 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
1583 /* The URB read length is the difference of the two, counted in pairs. */
1584 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
1588 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
1590 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
1591 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
1592 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
1593 struct pipe_shader_state
*p_fs
=
1594 (void *) ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1595 assert(p_fs
->type
== PIPE_SHADER_IR_NIR
);
1596 nir_shader
*fs_nir
= p_fs
->ir
.nir
;
1598 unsigned urb_read_offset
, urb_read_length
;
1599 iris_compute_sbe_urb_read_interval(fs_nir
->info
.inputs_read
,
1600 ice
->shaders
.last_vue_map
,
1601 cso_rast
->light_twoside
,
1602 &urb_read_offset
, &urb_read_length
);
1604 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
1605 sbe
.AttributeSwizzleEnable
= true;
1606 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1607 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
1608 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
1609 sbe
.VertexURBEntryReadLength
= urb_read_length
;
1610 sbe
.ForceVertexURBEntryReadOffset
= true;
1611 sbe
.ForceVertexURBEntryReadLength
= true;
1612 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1614 for (int i
= 0; i
< 32; i
++) {
1615 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
1621 iris_bind_compute_state(struct pipe_context
*ctx
, void *state
)
1626 iris_populate_sampler_key(const struct iris_context
*ice
,
1627 struct brw_sampler_prog_key_data
*key
)
1629 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
1630 key
->swizzles
[i
] = 0x688; /* XYZW */
1635 iris_populate_vs_key(const struct iris_context
*ice
,
1636 struct brw_vs_prog_key
*key
)
1638 memset(key
, 0, sizeof(*key
));
1639 iris_populate_sampler_key(ice
, &key
->tex
);
1643 iris_populate_tcs_key(const struct iris_context
*ice
,
1644 struct brw_tcs_prog_key
*key
)
1646 memset(key
, 0, sizeof(*key
));
1647 iris_populate_sampler_key(ice
, &key
->tex
);
1651 iris_populate_tes_key(const struct iris_context
*ice
,
1652 struct brw_tes_prog_key
*key
)
1654 memset(key
, 0, sizeof(*key
));
1655 iris_populate_sampler_key(ice
, &key
->tex
);
1659 iris_populate_gs_key(const struct iris_context
*ice
,
1660 struct brw_gs_prog_key
*key
)
1662 memset(key
, 0, sizeof(*key
));
1663 iris_populate_sampler_key(ice
, &key
->tex
);
1667 iris_populate_fs_key(const struct iris_context
*ice
,
1668 struct brw_wm_prog_key
*key
)
1670 memset(key
, 0, sizeof(*key
));
1671 iris_populate_sampler_key(ice
, &key
->tex
);
1673 /* XXX: dirty flags? */
1674 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
1675 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
1676 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
1677 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
1679 key
->nr_color_regions
= fb
->nr_cbufs
;
1681 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
1683 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
1684 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
1686 // key->force_dual_color_blend for unigine
1688 if (cso_rast
->multisample
) {
1689 key
->persample_interp
=
1690 ctx
->Multisample
.SampleShading
&&
1691 (ctx
->Multisample
.MinSampleShadingValue
*
1692 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1);
1694 key
->multisample_fbo
= fb
->samples
> 1;
1698 key
->coherent_fb_fetch
= true;
1701 //pkt.SamplerCount = \
1702 //DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1703 //pkt.PerThreadScratchSpace = prog_data->total_scratch == 0 ? 0 : \
1704 //ffs(stage_state->per_thread_scratch) - 11; \
1707 KSP(const struct iris_compiled_shader
*shader
)
1709 struct iris_resource
*res
= (void *) shader
->buffer
;
1710 return res
->bo
->gtt_offset
+ shader
->offset
;
1713 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1714 pkt.KernelStartPointer = KSP(shader); \
1715 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
1716 pkt.FloatingPointMode = prog_data->use_alt_mode; \
1718 pkt.DispatchGRFStartRegisterForURBData = \
1719 prog_data->dispatch_grf_start_reg; \
1720 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1721 pkt.prefix##URBEntryReadOffset = 0; \
1723 pkt.StatisticsEnable = true; \
1727 iris_set_vs_state(const struct gen_device_info
*devinfo
,
1728 struct iris_compiled_shader
*shader
)
1730 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1731 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1733 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
1734 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1735 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1736 vs
.SIMD8DispatchEnable
= true;
1737 vs
.UserClipDistanceCullTestEnableBitmask
=
1738 vue_prog_data
->cull_distance_mask
;
1743 iris_set_tcs_state(const struct gen_device_info
*devinfo
,
1744 struct iris_compiled_shader
*shader
)
1746 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1747 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1748 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
1750 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
1751 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
1753 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
1754 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
1755 hs
.IncludeVertexHandles
= true;
1760 iris_set_tes_state(const struct gen_device_info
*devinfo
,
1761 struct iris_compiled_shader
*shader
)
1763 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1764 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1765 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
1767 uint32_t *te_state
= (void *) shader
->derived_data
;
1768 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
1770 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
1771 te
.Partitioning
= tes_prog_data
->partitioning
;
1772 te
.OutputTopology
= tes_prog_data
->output_topology
;
1773 te
.TEDomain
= tes_prog_data
->domain
;
1775 te
.MaximumTessellationFactorOdd
= 63.0;
1776 te
.MaximumTessellationFactorNotOdd
= 64.0;
1779 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
1780 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
1782 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
1783 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
1784 ds
.ComputeWCoordinateEnable
=
1785 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
1787 ds
.UserClipDistanceCullTestEnableBitmask
=
1788 vue_prog_data
->cull_distance_mask
;
1794 iris_set_gs_state(const struct gen_device_info
*devinfo
,
1795 struct iris_compiled_shader
*shader
)
1797 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1798 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1799 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
1801 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
1802 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
1804 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
1805 gs
.OutputTopology
= gs_prog_data
->output_topology
;
1806 gs
.ControlDataHeaderSize
=
1807 gs_prog_data
->control_data_header_size_hwords
;
1808 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
1809 gs
.DispatchMode
= SIMD8
;
1810 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
1811 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
1812 gs
.ReorderMode
= TRAILING
;
1813 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
1814 gs
.MaximumNumberofThreads
=
1815 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
1816 : (devinfo
->max_gs_threads
- 1);
1818 if (gs_prog_data
->static_vertex_count
!= -1) {
1819 gs
.StaticOutput
= true;
1820 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
1822 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
1824 gs
.UserClipDistanceCullTestEnableBitmask
=
1825 vue_prog_data
->cull_distance_mask
;
1827 const int urb_entry_write_offset
= 1;
1828 const uint32_t urb_entry_output_length
=
1829 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
1830 urb_entry_write_offset
;
1832 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
1833 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
1838 iris_set_fs_state(const struct gen_device_info
*devinfo
,
1839 struct iris_compiled_shader
*shader
)
1841 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1842 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
1844 uint32_t *ps_state
= (void *) shader
->derived_data
;
1845 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
1847 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
1848 ps
.VectorMaskEnable
= true;
1849 //ps.SamplerCount = ...
1850 ps
.BindingTableEntryCount
= prog_data
->binding_table
.size_bytes
/ 4;
1851 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
1852 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
1854 ps
.PushConstantEnable
= prog_data
->nr_params
> 0 ||
1855 prog_data
->ubo_ranges
[0].length
> 0;
1857 /* From the documentation for this packet:
1858 * "If the PS kernel does not need the Position XY Offsets to
1859 * compute a Position Value, then this field should be programmed
1860 * to POSOFFSET_NONE."
1862 * "SW Recommendation: If the PS kernel needs the Position Offsets
1863 * to compute a Position XY value, this field should match Position
1864 * ZW Interpolation Mode to ensure a consistent position.xyzw
1867 * We only require XY sample offsets. So, this recommendation doesn't
1868 * look useful at the moment. We might need this in future.
1870 ps
.PositionXYOffsetSelect
=
1871 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
1872 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1873 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1874 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
1876 // XXX: Disable SIMD32 with 16x MSAA
1878 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
1879 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
1880 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
1881 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
1882 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
1883 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
1885 ps
.KernelStartPointer0
=
1886 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
1887 ps
.KernelStartPointer1
=
1888 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
1889 ps
.KernelStartPointer2
=
1890 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
1893 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
1894 psx
.PixelShaderValid
= true;
1895 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1896 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
1897 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
1898 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1899 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1900 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
1902 if (wm_prog_data
->uses_sample_mask
) {
1903 /* TODO: conservative rasterization */
1904 if (wm_prog_data
->post_depth_coverage
)
1905 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
1907 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
1910 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1911 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
1912 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
1919 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
1921 assert(cache_id
<= IRIS_CACHE_CS
);
1923 static const unsigned dwords
[] = {
1924 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
1925 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
1926 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
1927 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
1929 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
1930 [IRIS_CACHE_CS
] = 0,
1931 [IRIS_CACHE_BLORP_BLIT
] = 0,
1934 return sizeof(uint32_t) * dwords
[cache_id
];
1938 iris_set_derived_program_state(const struct gen_device_info
*devinfo
,
1939 enum iris_program_cache_id cache_id
,
1940 struct iris_compiled_shader
*shader
)
1944 iris_set_vs_state(devinfo
, shader
);
1946 case IRIS_CACHE_TCS
:
1947 iris_set_tcs_state(devinfo
, shader
);
1949 case IRIS_CACHE_TES
:
1950 iris_set_tes_state(devinfo
, shader
);
1953 iris_set_gs_state(devinfo
, shader
);
1956 iris_set_fs_state(devinfo
, shader
);
1966 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
1968 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
1969 const unsigned push_size_kB
= 32;
1970 unsigned entries
[4];
1974 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1975 if (!ice
->shaders
.prog
[i
]) {
1978 struct brw_vue_prog_data
*vue_prog_data
=
1979 (void *) ice
->shaders
.prog
[i
]->prog_data
;
1980 size
[i
] = vue_prog_data
->urb_entry_size
;
1982 assert(size
[i
] != 0);
1985 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
1986 1024 * ice
->shaders
.urb_size
,
1987 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
1988 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
1989 size
, entries
, start
);
1991 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1992 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
1993 urb
._3DCommandSubOpcode
+= i
;
1994 urb
.VSURBStartingAddress
= start
[i
];
1995 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
1996 urb
.VSNumberofURBEntries
= entries
[i
];
2001 static const uint32_t push_constant_opcodes
[] = {
2002 [MESA_SHADER_VERTEX
] = 21,
2003 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2004 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2005 [MESA_SHADER_GEOMETRY
] = 22,
2006 [MESA_SHADER_FRAGMENT
] = 23,
2007 [MESA_SHADER_COMPUTE
] = 0,
2011 * Add a surface to the validation list, as well as the buffer containing
2012 * the corresponding SURFACE_STATE.
2014 * Returns the binding table entry (offset to SURFACE_STATE).
2017 use_surface(struct iris_batch
*batch
,
2018 struct pipe_surface
*p_surf
,
2021 struct iris_surface
*surf
= (void *) p_surf
;
2022 struct iris_resource
*res
= (void *) p_surf
->texture
;
2023 struct iris_resource
*state_res
= (void *) surf
->surface_state_resource
;
2024 iris_use_pinned_bo(batch
, res
->bo
, writeable
);
2025 iris_use_pinned_bo(batch
, state_res
->bo
, false);
2027 return surf
->surface_state_offset
;
2031 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
2033 struct iris_resource
*res
= (void *) isv
->pipe
.texture
;
2034 struct iris_resource
*state_res
= (void *) isv
->surface_state_resource
;
2035 iris_use_pinned_bo(batch
, res
->bo
, false);
2036 iris_use_pinned_bo(batch
, state_res
->bo
, false);
2038 return isv
->surface_state_offset
;
2042 iris_upload_render_state(struct iris_context
*ice
,
2043 struct iris_batch
*batch
,
2044 const struct pipe_draw_info
*draw
)
2046 const uint64_t dirty
= ice
->state
.dirty
;
2048 struct brw_wm_prog_data
*wm_prog_data
= (void *)
2049 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2051 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
2052 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2053 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2054 ptr
.CCViewportPointer
=
2055 emit_state(batch
, ice
->state
.dynamic_uploader
,
2056 cso
->cc_vp
, sizeof(cso
->cc_vp
), 32);
2060 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
2061 struct iris_viewport_state
*cso
= ice
->state
.cso_vp
;
2062 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2063 ptr
.SFClipViewportPointer
=
2064 emit_state(batch
, ice
->state
.dynamic_uploader
, cso
->sf_cl_vp
,
2065 4 * GENX(SF_CLIP_VIEWPORT_length
) *
2066 ice
->state
.num_viewports
, 64);
2072 if (dirty
& IRIS_DIRTY_URB
) {
2073 iris_upload_urb_config(ice
, batch
);
2076 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
2077 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2078 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2079 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2080 const int num_dwords
= 4 * (GENX(BLEND_STATE_length
) +
2081 cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
));
2082 uint32_t blend_offset
;
2083 uint32_t *blend_map
=
2084 stream_state(batch
, ice
->state
.dynamic_uploader
, 4 * num_dwords
, 64,
2087 uint32_t blend_state_header
;
2088 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
2089 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2090 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
2093 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
2094 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1],
2095 sizeof(cso_blend
->blend_state
) - sizeof(uint32_t));
2097 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2098 ptr
.BlendStatePointer
= blend_offset
;
2099 ptr
.BlendStatePointerValid
= true;
2103 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
2104 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2107 stream_state(batch
, ice
->state
.dynamic_uploader
,
2108 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
2110 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
2111 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
2112 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
2113 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
2114 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
2115 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
2116 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
2118 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2119 ptr
.ColorCalcStatePointer
= cc_offset
;
2120 ptr
.ColorCalcStatePointerValid
= true;
2124 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2125 // XXX: wrong dirty tracking...
2126 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
2129 struct pipe_constant_buffer
*cbuf0
=
2130 &ice
->shaders
.state
[stage
].constbuf
[0];
2132 if (!ice
->shaders
.prog
[stage
] || cbuf0
->buffer
|| !cbuf0
->buffer_size
)
2135 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2136 shs
->const_size
= cbuf0
->buffer_size
;
2137 u_upload_data(ice
->ctx
.const_uploader
, 0, shs
->const_size
, 32,
2138 cbuf0
->user_buffer
, &shs
->const_offset
,
2139 &shs
->push_resource
);
2142 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2143 // XXX: wrong dirty tracking...
2144 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
2147 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2148 struct iris_resource
*res
= (void *) shs
->push_resource
;
2150 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2151 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2153 pkt
.ConstantBody
.ReadLength
[3] = shs
->const_size
;
2154 pkt
.ConstantBody
.Buffer
[3] = ro_bo(res
->bo
, shs
->const_offset
);
2161 // - ubos/ssbos/abos
2164 // - render targets - write and read
2165 // XXX: 3DSTATE_BINDING_TABLE_POINTERS_XS
2167 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2168 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2169 if (!shader
) // XXX: dirty bits...also, emit a disable maybe?
2172 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
2173 uint32_t bt_offset
= 0;
2174 uint32_t *bt_map
= NULL
;
2177 if (prog_data
->binding_table
.size_bytes
!= 0) {
2178 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
2179 bt_map
= iris_binder_reserve(&ice
->state
.binder
,
2180 prog_data
->binding_table
.size_bytes
,
2184 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
2185 ptr
._3DCommandSubOpcode
= 38 + stage
;
2186 ptr
.PointertoVSBindingTable
= bt_offset
;
2189 if (stage
== MESA_SHADER_FRAGMENT
) {
2190 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2191 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
2192 bt_map
[s
++] = use_surface(batch
, cso_fb
->cbufs
[i
], true);
2196 assert(prog_data
->binding_table
.texture_start
==
2197 (ice
->state
.num_textures
[stage
] ? s
: 0xd0d0d0d0));
2199 for (int i
= 0; i
< ice
->state
.num_textures
[stage
]; i
++) {
2200 struct iris_sampler_view
*view
= ice
->state
.textures
[stage
][i
];
2201 bt_map
[s
++] = use_sampler_view(batch
, view
);
2205 // XXX: not implemented yet
2206 assert(prog_data
->binding_table
.pull_constants_start
== 0xd0d0d0d0);
2207 assert(prog_data
->binding_table
.ubo_start
== 0xd0d0d0d0);
2208 assert(prog_data
->binding_table
.ssbo_start
== 0xd0d0d0d0);
2209 assert(prog_data
->binding_table
.image_start
== 0xd0d0d0d0);
2210 assert(prog_data
->binding_table
.shader_time_start
== 0xd0d0d0d0);
2211 //assert(prog_data->binding_table.plane_start[1] == 0xd0d0d0d0);
2212 //assert(prog_data->binding_table.plane_start[2] == 0xd0d0d0d0);
2216 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2217 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
2218 !ice
->shaders
.prog
[stage
])
2221 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
2222 ptr
._3DCommandSubOpcode
= 43 + stage
;
2223 ptr
.PointertoVSSamplerState
= ice
->state
.sampler_table_offset
[stage
];
2227 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
2228 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
2230 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
2231 if (ice
->state
.framebuffer
.samples
> 0)
2232 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
2236 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
2237 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
2238 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
2242 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2243 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
2246 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2249 struct iris_resource
*cache
= (void *) shader
->buffer
;
2250 iris_use_pinned_bo(batch
, cache
->bo
, false);
2251 iris_batch_emit(batch
, shader
->derived_data
,
2252 iris_derived_program_state_size(stage
));
2254 if (stage
== MESA_SHADER_TESS_EVAL
) {
2255 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
2256 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
2257 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
2258 } else if (stage
== MESA_SHADER_GEOMETRY
) {
2259 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
2265 // 3DSTATE_STREAMOUT
2266 // 3DSTATE_SO_BUFFER
2267 // 3DSTATE_SO_DECL_LIST
2269 if (dirty
& IRIS_DIRTY_CLIP
) {
2270 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2271 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2273 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
2274 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
2275 if (wm_prog_data
->barycentric_interp_modes
&
2276 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
2277 cl
.NonPerspectiveBarycentricEnable
= true;
2279 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
2281 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
2282 ARRAY_SIZE(cso_rast
->clip
));
2285 if (dirty
& IRIS_DIRTY_RASTER
) {
2286 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2287 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
2288 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
2292 if (dirty
& (IRIS_DIRTY_RASTER
| IRIS_DIRTY_FS
)) {
2293 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2294 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
2296 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
2297 wm
.BarycentricInterpolationMode
=
2298 wm_prog_data
->barycentric_interp_modes
;
2300 if (wm_prog_data
->early_fragment_tests
)
2301 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
2302 else if (wm_prog_data
->has_side_effects
)
2303 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
2305 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
2309 // XXX: 3DSTATE_SBE, 3DSTATE_SBE_SWIZ
2310 // -> iris_raster_state (point sprite texture coordinate origin)
2311 // -> bunch of shader state...
2312 iris_emit_sbe(batch
, ice
);
2313 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbe
) {
2317 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
2318 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2319 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2320 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
2321 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
2322 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
2323 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2326 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
2327 ARRAY_SIZE(cso_blend
->ps_blend
));
2330 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
2331 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2332 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
2334 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
2335 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
2336 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
2337 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
2339 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
2342 if (dirty
& IRIS_DIRTY_SCISSOR
) {
2343 // XXX: allocate at set_scissor time?
2344 uint32_t scissor_offset
= ice
->state
.num_scissors
== 0 ? 0 :
2345 emit_state(batch
, ice
->state
.dynamic_uploader
, ice
->state
.scissors
,
2346 sizeof(struct pipe_scissor_state
) *
2347 ice
->state
.num_scissors
, 32);
2349 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2350 ptr
.ScissorRectPointer
= scissor_offset
;
2354 // XXX: 3DSTATE_DEPTH_BUFFER
2355 // XXX: 3DSTATE_HIER_DEPTH_BUFFER
2356 // XXX: 3DSTATE_STENCIL_BUFFER
2357 // XXX: 3DSTATE_CLEAR_PARAMS
2359 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
2360 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
2361 for (int i
= 0; i
< 32; i
++) {
2362 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
2367 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
2368 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2369 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
2373 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
2374 topo
.PrimitiveTopologyType
=
2375 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
2379 if (draw
->index_size
> 0) {
2380 struct iris_resource
*res
= (struct iris_resource
*)draw
->index
.resource
;
2382 assert(!draw
->has_user_indices
);
2384 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
2385 ib
.IndexFormat
= draw
->index_size
;
2387 ib
.BufferSize
= res
->bo
->size
;
2388 ib
.BufferStartingAddress
= ro_bo(res
->bo
, 0);
2392 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
2393 struct iris_vertex_buffer_state
*cso
= ice
->state
.cso_vertex_buffers
;
2395 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_length
) == 4);
2396 STATIC_ASSERT((GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) % 32) == 0);
2398 iris_batch_emit(batch
, cso
->vertex_buffers
,
2399 sizeof(uint32_t) * (1 + 4 * cso
->num_buffers
));
2401 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
2402 iris_use_pinned_bo(batch
, cso
->bos
[i
], false);
2406 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
2407 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
2408 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
2409 (1 + cso
->count
* GENX(VERTEX_ELEMENT_STATE_length
)));
2410 for (int i
= 0; i
< cso
->count
; i
++) {
2411 iris_batch_emit(batch
, cso
->vf_instancing
[i
], sizeof(uint32_t) *
2412 (cso
->count
* GENX(3DSTATE_VF_INSTANCING_length
)));
2414 for (int i
= 0; i
< cso
->count
; i
++) {
2415 /* TODO: vertexid, instanceid support */
2416 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
);
2421 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
2422 if (draw
->primitive_restart
) {
2423 vf
.IndexedDrawCutIndexEnable
= true;
2424 vf
.CutIndex
= draw
->restart_index
;
2429 // XXX: Gen8 - PMA fix
2431 assert(!draw
->indirect
); // XXX: indirect support
2433 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
2434 prim
.StartInstanceLocation
= draw
->start_instance
;
2435 prim
.InstanceCount
= draw
->instance_count
;
2436 prim
.VertexCountPerInstance
= draw
->count
;
2437 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
2439 // XXX: this is probably bonkers.
2440 prim
.StartVertexLocation
= draw
->start
;
2442 if (draw
->index_size
) {
2443 prim
.BaseVertexLocation
+= draw
->index_bias
;
2445 prim
.StartVertexLocation
+= draw
->index_bias
;
2448 //prim.BaseVertexLocation = ...;
2453 iris_destroy_state(struct iris_context
*ice
)
2455 // XXX: unreference resources/surfaces.
2456 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
2457 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
2459 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
2463 flags_to_post_sync_op(uint32_t flags
)
2465 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
2466 return WriteImmediateData
;
2468 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
2469 return WritePSDepthCount
;
2471 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
2472 return WriteTimestamp
;
2478 * Do the given flags have a Post Sync or LRI Post Sync operation?
2480 static enum pipe_control_flags
2481 get_post_sync_flags(enum pipe_control_flags flags
)
2483 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
2484 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2485 PIPE_CONTROL_WRITE_TIMESTAMP
|
2486 PIPE_CONTROL_LRI_POST_SYNC_OP
;
2488 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
2489 * "LRI Post Sync Operation". So more than one bit set would be illegal.
2491 assert(util_bitcount(flags
) <= 1);
2496 // XXX: compute support
2497 #define IS_COMPUTE_PIPELINE(batch) (batch->ring != I915_EXEC_RENDER)
2500 * Emit a series of PIPE_CONTROL commands, taking into account any
2501 * workarounds necessary to actually accomplish the caller's request.
2503 * Unless otherwise noted, spec quotations in this function come from:
2505 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
2506 * Restrictions for PIPE_CONTROL.
2509 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
2510 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
2512 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
2513 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
2514 enum pipe_control_flags non_lri_post_sync_flags
=
2515 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
2517 /* Recursive PIPE_CONTROL workarounds --------------------------------
2518 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
2520 * We do these first because we want to look at the original operation,
2521 * rather than any workarounds we set.
2523 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
2524 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
2525 * lists several workarounds:
2527 * "Project: SKL, KBL, BXT
2529 * If the VF Cache Invalidation Enable is set to a 1 in a
2530 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
2531 * sets to 0, with the VF Cache Invalidation Enable set to 0
2532 * needs to be sent prior to the PIPE_CONTROL with VF Cache
2533 * Invalidation Enable set to a 1."
2535 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
2538 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
2539 /* Project: SKL / Argument: LRI Post Sync Operation [23]
2541 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2542 * programmed prior to programming a PIPECONTROL command with "LRI
2543 * Post Sync Operation" in GPGPU mode of operation (i.e when
2544 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2546 * The same text exists a few rows below for Post Sync Op.
2548 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
2551 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
2553 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
2554 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
2555 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
2557 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
2561 /* "Flush Types" workarounds ---------------------------------------------
2562 * We do these now because they may add post-sync operations or CS stalls.
2565 if (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
2566 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
2568 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
2569 * 'Write PS Depth Count' or 'Write Timestamp'."
2572 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
2573 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
2574 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
2575 bo
= batch
->screen
->workaround_bo
;
2579 /* #1130 from Gen10 workarounds page:
2581 * "Enable Depth Stall on every Post Sync Op if Render target Cache
2582 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
2583 * board stall if Render target cache flush is enabled."
2585 * Applicable to CNL B0 and C0 steppings only.
2587 * The wording here is unclear, and this workaround doesn't look anything
2588 * like the internal bug report recommendations, but leave it be for now...
2590 if (GEN_GEN
== 10) {
2591 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
2592 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
2593 } else if (flags
& non_lri_post_sync_flags
) {
2594 flags
|= PIPE_CONTROL_DEPTH_STALL
;
2598 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
2599 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
2601 * "This bit must be DISABLED for operations other than writing
2604 * This seems like nonsense. An Ivybridge workaround requires us to
2605 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
2606 * operation. Gen8+ requires us to emit depth stalls and depth cache
2607 * flushes together. So, it's hard to imagine this means anything other
2608 * than "we originally intended this to be used for PS_DEPTH_COUNT".
2610 * We ignore the supposed restriction and do nothing.
2614 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2615 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
2616 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
2618 * "This bit must be DISABLED for End-of-pipe (Read) fences,
2619 * PS_DEPTH_COUNT or TIMESTAMP queries."
2621 * TODO: Implement end-of-pipe checking.
2623 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2624 PIPE_CONTROL_WRITE_TIMESTAMP
)));
2627 if (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) {
2628 /* From the PIPE_CONTROL instruction table, bit 1:
2630 * "This bit is ignored if Depth Stall Enable is set.
2631 * Further, the render cache is not flushed even if Write Cache
2632 * Flush Enable bit is set."
2634 * We assert that the caller doesn't do this combination, to try and
2635 * prevent mistakes. It shouldn't hurt the GPU, though.
2637 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
2638 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
2641 /* PIPE_CONTROL page workarounds ------------------------------------- */
2643 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
2644 /* From the PIPE_CONTROL page itself:
2647 * Restriction: Pipe_control with CS-stall bit set must be issued
2648 * before a pipe-control command that has the State Cache
2649 * Invalidate bit set."
2651 flags
|= PIPE_CONTROL_CS_STALL
;
2654 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
2655 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
2658 * SW must always program Post-Sync Operation to "Write Immediate
2659 * Data" when Flush LLC is set."
2661 * For now, we just require the caller to do it.
2663 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
2666 /* "Post-Sync Operation" workarounds -------------------------------- */
2668 /* Project: All / Argument: Global Snapshot Count Reset [19]
2670 * "This bit must not be exercised on any product.
2671 * Requires stall bit ([20] of DW1) set."
2673 * We don't use this, so we just assert that it isn't used. The
2674 * PIPE_CONTROL instruction page indicates that they intended this
2675 * as a debug feature and don't think it is useful in production,
2676 * but it may actually be usable, should we ever want to.
2678 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
2680 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
2681 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
2682 /* Project: All / Arguments:
2684 * - Generic Media State Clear [16]
2685 * - Indirect State Pointers Disable [16]
2687 * "Requires stall bit ([20] of DW1) set."
2689 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
2690 * State Clear) says:
2692 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2693 * programmed prior to programming a PIPECONTROL command with "Media
2694 * State Clear" set in GPGPU mode of operation"
2696 * This is a subset of the earlier rule, so there's nothing to do.
2698 flags
|= PIPE_CONTROL_CS_STALL
;
2701 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
2702 /* Project: All / Argument: Store Data Index
2704 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
2707 * For now, we just assert that the caller does this. We might want to
2708 * automatically add a write to the workaround BO...
2710 assert(non_lri_post_sync_flags
!= 0);
2713 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
2714 /* Project: All / Argument: Sync GFDT
2716 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
2717 * than '0' or 0x2520[13] must be set."
2719 * For now, we just assert that the caller does this.
2721 assert(non_lri_post_sync_flags
!= 0);
2724 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
2725 /* Project: IVB+ / Argument: TLB inv
2727 * "Requires stall bit ([20] of DW1) set."
2729 * Also, from the PIPE_CONTROL instruction table:
2732 * Post Sync Operation or CS stall must be set to ensure a TLB
2733 * invalidation occurs. Otherwise no cycle will occur to the TLB
2734 * cache to invalidate."
2736 * This is not a subset of the earlier rule, so there's nothing to do.
2738 flags
|= PIPE_CONTROL_CS_STALL
;
2741 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
2742 /* TODO: The big Skylake GT4 post sync op workaround */
2745 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
2747 if (IS_COMPUTE_PIPELINE(batch
)) {
2748 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
2749 /* Project: SKL+ / Argument: Tex Invalidate
2750 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
2752 flags
|= PIPE_CONTROL_CS_STALL
;
2755 if (GEN_GEN
== 8 && (post_sync_flags
||
2756 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
2757 PIPE_CONTROL_DEPTH_STALL
|
2758 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2759 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
2760 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
2761 /* Project: BDW / Arguments:
2763 * - LRI Post Sync Operation [23]
2764 * - Post Sync Op [15:14]
2766 * - Depth Stall [13]
2767 * - Render Target Cache Flush [12]
2768 * - Depth Cache Flush [0]
2769 * - DC Flush Enable [5]
2771 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
2774 flags
|= PIPE_CONTROL_CS_STALL
;
2776 /* Also, from the PIPE_CONTROL instruction table, bit 20:
2779 * This bit must be always set when PIPE_CONTROL command is
2780 * programmed by GPGPU and MEDIA workloads, except for the cases
2781 * when only Read Only Cache Invalidation bits are set (State
2782 * Cache Invalidation Enable, Instruction cache Invalidation
2783 * Enable, Texture Cache Invalidation Enable, Constant Cache
2784 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
2785 * need not implemented when FF_DOP_CG is disable via "Fixed
2786 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
2788 * It sounds like we could avoid CS stalls in some cases, but we
2789 * don't currently bother. This list isn't exactly the list above,
2795 /* "Stall" workarounds ----------------------------------------------
2796 * These have to come after the earlier ones because we may have added
2797 * some additional CS stalls above.
2800 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
2801 /* Project: PRE-SKL, VLV, CHV
2803 * "[All Stepping][All SKUs]:
2805 * One of the following must also be set:
2807 * - Render Target Cache Flush Enable ([12] of DW1)
2808 * - Depth Cache Flush Enable ([0] of DW1)
2809 * - Stall at Pixel Scoreboard ([1] of DW1)
2810 * - Depth Stall ([13] of DW1)
2811 * - Post-Sync Operation ([13] of DW1)
2812 * - DC Flush Enable ([5] of DW1)"
2814 * If we don't already have one of those bits set, we choose to add
2815 * "Stall at Pixel Scoreboard". Some of the other bits require a
2816 * CS stall as a workaround (see above), which would send us into
2817 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
2818 * appears to be safe, so we choose that.
2820 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2821 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
2822 PIPE_CONTROL_WRITE_IMMEDIATE
|
2823 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2824 PIPE_CONTROL_WRITE_TIMESTAMP
|
2825 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
2826 PIPE_CONTROL_DEPTH_STALL
|
2827 PIPE_CONTROL_DATA_CACHE_FLUSH
;
2828 if (!(flags
& wa_bits
))
2829 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
2832 /* Emit --------------------------------------------------------------- */
2834 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
2835 pc
.LRIPostSyncOperation
= NoLRIOperation
;
2836 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
2837 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
2838 pc
.StoreDataIndex
= 0;
2839 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
2840 pc
.GlobalSnapshotCountReset
=
2841 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
2842 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
2843 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
2844 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
2845 pc
.RenderTargetCacheFlushEnable
=
2846 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
2847 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
2848 pc
.StateCacheInvalidationEnable
=
2849 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
2850 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
2851 pc
.ConstantCacheInvalidationEnable
=
2852 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
2853 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
2854 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
2855 pc
.InstructionCacheInvalidateEnable
=
2856 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
2857 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
2858 pc
.IndirectStatePointersDisable
=
2859 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
2860 pc
.TextureCacheInvalidationEnable
=
2861 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2862 pc
.Address
= ro_bo(bo
, offset
);
2863 pc
.ImmediateData
= imm
;
2868 genX(init_state
)(struct iris_context
*ice
)
2870 struct pipe_context
*ctx
= &ice
->ctx
;
2872 ctx
->create_blend_state
= iris_create_blend_state
;
2873 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
2874 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
2875 ctx
->create_sampler_state
= iris_create_sampler_state
;
2876 ctx
->create_sampler_view
= iris_create_sampler_view
;
2877 ctx
->create_surface
= iris_create_surface
;
2878 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
2879 ctx
->create_compute_state
= iris_create_compute_state
;
2880 ctx
->bind_blend_state
= iris_bind_blend_state
;
2881 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
2882 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
2883 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
2884 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
2885 ctx
->bind_compute_state
= iris_bind_compute_state
;
2886 ctx
->delete_blend_state
= iris_delete_state
;
2887 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
2888 ctx
->delete_fs_state
= iris_delete_state
;
2889 ctx
->delete_rasterizer_state
= iris_delete_state
;
2890 ctx
->delete_sampler_state
= iris_delete_state
;
2891 ctx
->delete_vertex_elements_state
= iris_delete_state
;
2892 ctx
->delete_compute_state
= iris_delete_state
;
2893 ctx
->delete_tcs_state
= iris_delete_state
;
2894 ctx
->delete_tes_state
= iris_delete_state
;
2895 ctx
->delete_gs_state
= iris_delete_state
;
2896 ctx
->delete_vs_state
= iris_delete_state
;
2897 ctx
->set_blend_color
= iris_set_blend_color
;
2898 ctx
->set_clip_state
= iris_set_clip_state
;
2899 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
2900 ctx
->set_sampler_views
= iris_set_sampler_views
;
2901 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
2902 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
2903 ctx
->set_sample_mask
= iris_set_sample_mask
;
2904 ctx
->set_scissor_states
= iris_set_scissor_states
;
2905 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
2906 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
2907 ctx
->set_viewport_states
= iris_set_viewport_states
;
2908 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
2909 ctx
->surface_destroy
= iris_surface_destroy
;
2910 ctx
->draw_vbo
= iris_draw_vbo
;
2911 ctx
->launch_grid
= iris_launch_grid
;
2912 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
2913 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
2914 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
2916 ice
->vtbl
.destroy_state
= iris_destroy_state
;
2917 ice
->vtbl
.init_render_context
= iris_init_render_context
;
2918 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
2919 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
2920 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
2921 ice
->vtbl
.set_derived_program_state
= iris_set_derived_program_state
;
2922 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
2923 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
2924 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
2925 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
2926 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
2928 ice
->state
.dirty
= ~0ull;