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iris: bits of WM key
[mesa.git] / src / gallium / drivers / iris / iris_state.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25
26 #ifdef HAVE_VALGRIND
27 #include <valgrind.h>
28 #include <memcheck.h>
29 #define VG(x) x
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
31 #else
32 #define VG(x)
33 #endif
34
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "i915_drm.h"
42 #include "intel/compiler/brw_compiler.h"
43 #include "intel/common/gen_sample_positions.h"
44 #include "iris_batch.h"
45 #include "iris_context.h"
46 #include "iris_pipe.h"
47 #include "iris_resource.h"
48
49 #define __gen_address_type struct iris_address
50 #define __gen_user_data struct iris_batch
51
52 static uint64_t
53 __gen_combine_address(struct iris_batch *batch, void *location,
54 struct iris_address addr, uint32_t delta)
55 {
56 if (addr.bo == NULL)
57 return addr.offset + delta;
58
59 return iris_batch_reloc(batch, location - batch->cmdbuf.map, addr.bo,
60 addr.offset + delta, addr.reloc_flags);
61 }
62
63 #define __genxml_cmd_length(cmd) cmd ## _length
64 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
65 #define __genxml_cmd_header(cmd) cmd ## _header
66 #define __genxml_cmd_pack(cmd) cmd ## _pack
67
68 static void *
69 get_command_space(struct iris_batch *batch, unsigned bytes)
70 {
71 iris_require_command_space(batch, bytes);
72 void *map = batch->cmdbuf.map_next;
73 batch->cmdbuf.map_next += bytes;
74 return map;
75 }
76
77 #define _iris_pack_command(batch, cmd, dst, name) \
78 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
79 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
80 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
81 _dst = NULL; \
82 }))
83
84 #define iris_pack_command(cmd, dst, name) \
85 _iris_pack_command(NULL, cmd, dst, name)
86
87 #define iris_pack_state(cmd, dst, name) \
88 for (struct cmd name = {}, \
89 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
90 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
91 _dst = NULL)
92
93 #define iris_emit_cmd(batch, cmd, name) \
94 _iris_pack_command(batch, cmd, get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
95
96 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
97 do { \
98 uint32_t *dw = get_command_space(batch, 4 * num_dwords); \
99 for (uint32_t i = 0; i < num_dwords; i++) \
100 dw[i] = (dwords0)[i] | (dwords1)[i]; \
101 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
102 } while (0)
103
104 #define iris_emit_with_addr(batch, dwords, num_dw, addr_field, addr) \
105 do { \
106 STATIC_ASSERT((GENX(addr_field) % 64) == 0); \
107 assert(num_dw <= ARRAY_SIZE(dwords)); \
108 int addr_idx = GENX(addr_field) / 32; \
109 uint32_t *dw = get_command_space(batch, 4 * num_dw); \
110 for (uint32_t i = 0; i < addr_idx; i++) { \
111 dw[i] = (dwords)[i]; \
112 } \
113 uint64_t *qw = (uint64_t *) &dw[addr_idx]; \
114 qw = iris_batch_reloc(batch, qw - batch->cmdbuf.map, addr.bo, \
115 addr.offset + (dwords)[addr_idx + 1], \
116 addr.reloc_flags); \
117 for (uint32_t i = addr_idx + 1; i < num_dw; i++) { \
118 dw[i] = (dwords)[i]; \
119 } \
120 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dw * 4)); \
121 } while (0)
122
123 #include "genxml/genX_pack.h"
124 #include "genxml/gen_macros.h"
125 #include "genxml/genX_bits.h"
126
127 #define MOCS_WB (2 << 1)
128
129 UNUSED static void pipe_asserts()
130 {
131 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
132
133 /* pipe_logicop happens to match the hardware. */
134 PIPE_ASSERT(PIPE_LOGICOP_CLEAR == LOGICOP_CLEAR);
135 PIPE_ASSERT(PIPE_LOGICOP_NOR == LOGICOP_NOR);
136 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED == LOGICOP_AND_INVERTED);
137 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED == LOGICOP_COPY_INVERTED);
138 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE == LOGICOP_AND_REVERSE);
139 PIPE_ASSERT(PIPE_LOGICOP_INVERT == LOGICOP_INVERT);
140 PIPE_ASSERT(PIPE_LOGICOP_XOR == LOGICOP_XOR);
141 PIPE_ASSERT(PIPE_LOGICOP_NAND == LOGICOP_NAND);
142 PIPE_ASSERT(PIPE_LOGICOP_AND == LOGICOP_AND);
143 PIPE_ASSERT(PIPE_LOGICOP_EQUIV == LOGICOP_EQUIV);
144 PIPE_ASSERT(PIPE_LOGICOP_NOOP == LOGICOP_NOOP);
145 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED == LOGICOP_OR_INVERTED);
146 PIPE_ASSERT(PIPE_LOGICOP_COPY == LOGICOP_COPY);
147 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE == LOGICOP_OR_REVERSE);
148 PIPE_ASSERT(PIPE_LOGICOP_OR == LOGICOP_OR);
149 PIPE_ASSERT(PIPE_LOGICOP_SET == LOGICOP_SET);
150
151 /* pipe_blend_func happens to match the hardware. */
152 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE == BLENDFACTOR_ONE);
153 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR == BLENDFACTOR_SRC_COLOR);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA == BLENDFACTOR_SRC_ALPHA);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA == BLENDFACTOR_DST_ALPHA);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR == BLENDFACTOR_DST_COLOR);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE == BLENDFACTOR_SRC_ALPHA_SATURATE);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR == BLENDFACTOR_CONST_COLOR);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA == BLENDFACTOR_CONST_ALPHA);
160 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR == BLENDFACTOR_SRC1_COLOR);
161 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA == BLENDFACTOR_SRC1_ALPHA);
162 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO == BLENDFACTOR_ZERO);
163 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR == BLENDFACTOR_INV_SRC_COLOR);
164 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA == BLENDFACTOR_INV_SRC_ALPHA);
165 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA == BLENDFACTOR_INV_DST_ALPHA);
166 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR == BLENDFACTOR_INV_DST_COLOR);
167 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR == BLENDFACTOR_INV_CONST_COLOR);
168 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA == BLENDFACTOR_INV_CONST_ALPHA);
169 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR == BLENDFACTOR_INV_SRC1_COLOR);
170 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA == BLENDFACTOR_INV_SRC1_ALPHA);
171
172 /* pipe_blend_func happens to match the hardware. */
173 PIPE_ASSERT(PIPE_BLEND_ADD == BLENDFUNCTION_ADD);
174 PIPE_ASSERT(PIPE_BLEND_SUBTRACT == BLENDFUNCTION_SUBTRACT);
175 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT == BLENDFUNCTION_REVERSE_SUBTRACT);
176 PIPE_ASSERT(PIPE_BLEND_MIN == BLENDFUNCTION_MIN);
177 PIPE_ASSERT(PIPE_BLEND_MAX == BLENDFUNCTION_MAX);
178
179 /* pipe_stencil_op happens to match the hardware. */
180 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP == STENCILOP_KEEP);
181 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO == STENCILOP_ZERO);
182 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE == STENCILOP_REPLACE);
183 PIPE_ASSERT(PIPE_STENCIL_OP_INCR == STENCILOP_INCRSAT);
184 PIPE_ASSERT(PIPE_STENCIL_OP_DECR == STENCILOP_DECRSAT);
185 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP == STENCILOP_INCR);
186 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP == STENCILOP_DECR);
187 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT == STENCILOP_INVERT);
188 #undef PIPE_ASSERT
189 }
190
191 static unsigned
192 translate_prim_type(enum pipe_prim_type prim, uint8_t verts_per_patch)
193 {
194 static const unsigned map[] = {
195 [PIPE_PRIM_POINTS] = _3DPRIM_POINTLIST,
196 [PIPE_PRIM_LINES] = _3DPRIM_LINELIST,
197 [PIPE_PRIM_LINE_LOOP] = _3DPRIM_LINELOOP,
198 [PIPE_PRIM_LINE_STRIP] = _3DPRIM_LINESTRIP,
199 [PIPE_PRIM_TRIANGLES] = _3DPRIM_TRILIST,
200 [PIPE_PRIM_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
201 [PIPE_PRIM_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
202 [PIPE_PRIM_QUADS] = _3DPRIM_QUADLIST,
203 [PIPE_PRIM_QUAD_STRIP] = _3DPRIM_QUADSTRIP,
204 [PIPE_PRIM_POLYGON] = _3DPRIM_POLYGON,
205 [PIPE_PRIM_LINES_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
206 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
207 [PIPE_PRIM_TRIANGLES_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
208 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
209 [PIPE_PRIM_PATCHES] = _3DPRIM_PATCHLIST_1 - 1,
210 };
211
212 return map[prim] + (prim == PIPE_PRIM_PATCHES ? verts_per_patch : 0);
213 }
214
215 static unsigned
216 translate_compare_func(enum pipe_compare_func pipe_func)
217 {
218 static const unsigned map[] = {
219 [PIPE_FUNC_NEVER] = COMPAREFUNCTION_NEVER,
220 [PIPE_FUNC_LESS] = COMPAREFUNCTION_LESS,
221 [PIPE_FUNC_EQUAL] = COMPAREFUNCTION_EQUAL,
222 [PIPE_FUNC_LEQUAL] = COMPAREFUNCTION_LEQUAL,
223 [PIPE_FUNC_GREATER] = COMPAREFUNCTION_GREATER,
224 [PIPE_FUNC_NOTEQUAL] = COMPAREFUNCTION_NOTEQUAL,
225 [PIPE_FUNC_GEQUAL] = COMPAREFUNCTION_GEQUAL,
226 [PIPE_FUNC_ALWAYS] = COMPAREFUNCTION_ALWAYS,
227 };
228 return map[pipe_func];
229 }
230
231 static unsigned
232 translate_shadow_func(enum pipe_compare_func pipe_func)
233 {
234 /* Gallium specifies the result of shadow comparisons as:
235 *
236 * 1 if ref <op> texel,
237 * 0 otherwise.
238 *
239 * The hardware does:
240 *
241 * 0 if texel <op> ref,
242 * 1 otherwise.
243 *
244 * So we need to flip the operator and also negate.
245 */
246 static const unsigned map[] = {
247 [PIPE_FUNC_NEVER] = PREFILTEROPALWAYS,
248 [PIPE_FUNC_LESS] = PREFILTEROPLEQUAL,
249 [PIPE_FUNC_EQUAL] = PREFILTEROPNOTEQUAL,
250 [PIPE_FUNC_LEQUAL] = PREFILTEROPLESS,
251 [PIPE_FUNC_GREATER] = PREFILTEROPGEQUAL,
252 [PIPE_FUNC_NOTEQUAL] = PREFILTEROPEQUAL,
253 [PIPE_FUNC_GEQUAL] = PREFILTEROPGREATER,
254 [PIPE_FUNC_ALWAYS] = PREFILTEROPNEVER,
255 };
256 return map[pipe_func];
257 }
258
259 static unsigned
260 translate_cull_mode(unsigned pipe_face)
261 {
262 static const unsigned map[4] = {
263 [PIPE_FACE_NONE] = CULLMODE_NONE,
264 [PIPE_FACE_FRONT] = CULLMODE_FRONT,
265 [PIPE_FACE_BACK] = CULLMODE_BACK,
266 [PIPE_FACE_FRONT_AND_BACK] = CULLMODE_BOTH,
267 };
268 return map[pipe_face];
269 }
270
271 static unsigned
272 translate_fill_mode(unsigned pipe_polymode)
273 {
274 static const unsigned map[4] = {
275 [PIPE_POLYGON_MODE_FILL] = FILL_MODE_SOLID,
276 [PIPE_POLYGON_MODE_LINE] = FILL_MODE_WIREFRAME,
277 [PIPE_POLYGON_MODE_POINT] = FILL_MODE_POINT,
278 [PIPE_POLYGON_MODE_FILL_RECTANGLE] = FILL_MODE_SOLID,
279 };
280 return map[pipe_polymode];
281 }
282
283 static struct iris_address
284 ro_bo(struct iris_bo *bo, uint32_t offset)
285 {
286 return (struct iris_address) { .bo = bo, .offset = offset };
287 }
288
289 static void
290 iris_emit_state_base_address(struct iris_batch *batch)
291 {
292 /* XXX: PIPE_CONTROLs */
293
294 iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
295 #if 0
296 // XXX: MOCS is stupid for this.
297 sba.GeneralStateMemoryObjectControlState = MOCS_WB;
298 sba.StatelessDataPortAccessMemoryObjectControlState = MOCS_WB;
299 sba.SurfaceStateMemoryObjectControlState = MOCS_WB;
300 sba.DynamicStateMemoryObjectControlState = MOCS_WB;
301 sba.IndirectObjectMemoryObjectControlState = MOCS_WB;
302 sba.InstructionMemoryObjectControlState = MOCS_WB;
303 sba.BindlessSurfaceStateMemoryObjectControlState = MOCS_WB;
304 #endif
305
306 sba.GeneralStateBaseAddressModifyEnable = true;
307 sba.SurfaceStateBaseAddressModifyEnable = true;
308 sba.DynamicStateBaseAddressModifyEnable = true;
309 sba.IndirectObjectBaseAddressModifyEnable = true;
310 sba.InstructionBaseAddressModifyEnable = true;
311 sba.GeneralStateBufferSizeModifyEnable = true;
312 sba.DynamicStateBufferSizeModifyEnable = true;
313 sba.BindlessSurfaceStateBaseAddressModifyEnable = true;
314 sba.IndirectObjectBufferSizeModifyEnable = true;
315 sba.InstructionBuffersizeModifyEnable = true;
316
317 sba.SurfaceStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
318 sba.DynamicStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
319
320 sba.GeneralStateBufferSize = 0xfffff;
321 sba.IndirectObjectBufferSize = 0xfffff;
322 sba.InstructionBufferSize = 0xfffff;
323 sba.DynamicStateBufferSize = ALIGN(MAX_STATE_SIZE, 4096);
324 }
325 }
326
327 static void
328 iris_init_render_context(struct iris_screen *screen,
329 struct iris_batch *batch,
330 struct pipe_debug_callback *dbg)
331 {
332 batch->emit_state_base_address = iris_emit_state_base_address;
333 iris_init_batch(batch, screen, dbg, I915_EXEC_RENDER);
334
335 iris_emit_cmd(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
336 rect.ClippedDrawingRectangleXMax = UINT16_MAX;
337 rect.ClippedDrawingRectangleYMax = UINT16_MAX;
338 }
339 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_PATTERN), pat) {
340 GEN_SAMPLE_POS_1X(pat._1xSample);
341 GEN_SAMPLE_POS_2X(pat._2xSample);
342 GEN_SAMPLE_POS_4X(pat._4xSample);
343 GEN_SAMPLE_POS_8X(pat._8xSample);
344 GEN_SAMPLE_POS_16X(pat._16xSample);
345 }
346 iris_emit_cmd(batch, GENX(3DSTATE_AA_LINE_PARAMETERS), foo);
347 iris_emit_cmd(batch, GENX(3DSTATE_WM_CHROMAKEY), foo);
348 iris_emit_cmd(batch, GENX(3DSTATE_WM_HZ_OP), foo);
349 /* XXX: may need to set an offset for origin-UL framebuffers */
350 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_OFFSET), foo);
351
352 /* Just assign a static partitioning. */
353 for (int i = 0; i <= MESA_SHADER_FRAGMENT; i++) {
354 iris_emit_cmd(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) {
355 alloc._3DCommandSubOpcode = 18 + i;
356 alloc.ConstantBufferOffset = 6 * i;
357 alloc.ConstantBufferSize = i == MESA_SHADER_FRAGMENT ? 8 : 6;
358 }
359 }
360 }
361
362 static void
363 iris_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *info)
364 {
365 }
366
367 static void
368 iris_set_blend_color(struct pipe_context *ctx,
369 const struct pipe_blend_color *state)
370 {
371 struct iris_context *ice = (struct iris_context *) ctx;
372
373 memcpy(&ice->state.blend_color, state, sizeof(struct pipe_blend_color));
374 ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE;
375 }
376
377 struct iris_blend_state {
378 uint32_t ps_blend[GENX(3DSTATE_PS_BLEND_length)];
379 uint32_t blend_state[GENX(BLEND_STATE_length)];
380 uint32_t blend_entries[BRW_MAX_DRAW_BUFFERS *
381 GENX(BLEND_STATE_ENTRY_length)];
382
383 bool alpha_to_coverage; /* for shader key */
384 };
385
386 static void *
387 iris_create_blend_state(struct pipe_context *ctx,
388 const struct pipe_blend_state *state)
389 {
390 struct iris_blend_state *cso = malloc(sizeof(struct iris_blend_state));
391
392 cso->alpha_to_coverage = state->alpha_to_coverage;
393
394 iris_pack_state(GENX(BLEND_STATE), cso->blend_state, bs) {
395 bs.AlphaToCoverageEnable = state->alpha_to_coverage;
396 bs.IndependentAlphaBlendEnable = state->independent_blend_enable;
397 bs.AlphaToOneEnable = state->alpha_to_one;
398 bs.AlphaToCoverageDitherEnable = state->alpha_to_coverage;
399 bs.ColorDitherEnable = state->dither;
400 //bs.AlphaTestEnable = <comes from alpha state> :(
401 //bs.AlphaTestFunction = <comes from alpha state> :(
402 }
403
404 iris_pack_command(GENX(3DSTATE_PS_BLEND), cso->ps_blend, pb) {
405 //pb.HasWriteableRT = <comes from somewhere> :(
406 //pb.AlphaTestEnable = <comes from alpha state> :(
407 pb.AlphaToCoverageEnable = state->alpha_to_coverage;
408 pb.IndependentAlphaBlendEnable = state->independent_blend_enable;
409
410 pb.ColorBufferBlendEnable = state->rt[0].blend_enable;
411
412 pb.SourceBlendFactor = state->rt[0].rgb_src_factor;
413 pb.SourceAlphaBlendFactor = state->rt[0].alpha_func;
414 pb.DestinationBlendFactor = state->rt[0].rgb_dst_factor;
415 pb.DestinationAlphaBlendFactor = state->rt[0].alpha_dst_factor;
416 }
417
418 for (int i = 0; i < BRW_MAX_DRAW_BUFFERS; i++) {
419 iris_pack_state(GENX(BLEND_STATE_ENTRY), &cso->blend_entries[i], be) {
420 be.LogicOpEnable = state->logicop_enable;
421 be.LogicOpFunction = state->logicop_func;
422
423 be.PreBlendSourceOnlyClampEnable = false;
424 be.ColorClampRange = COLORCLAMP_RTFORMAT;
425 be.PreBlendColorClampEnable = true;
426 be.PostBlendColorClampEnable = true;
427
428 be.ColorBufferBlendEnable = state->rt[i].blend_enable;
429
430 be.ColorBlendFunction = state->rt[i].rgb_func;
431 be.AlphaBlendFunction = state->rt[i].alpha_func;
432 be.SourceBlendFactor = state->rt[i].rgb_src_factor;
433 be.SourceAlphaBlendFactor = state->rt[i].alpha_func;
434 be.DestinationBlendFactor = state->rt[i].rgb_dst_factor;
435 be.DestinationAlphaBlendFactor = state->rt[i].alpha_dst_factor;
436
437 be.WriteDisableRed = state->rt[i].colormask & PIPE_MASK_R;
438 be.WriteDisableGreen = state->rt[i].colormask & PIPE_MASK_G;
439 be.WriteDisableBlue = state->rt[i].colormask & PIPE_MASK_B;
440 be.WriteDisableAlpha = state->rt[i].colormask & PIPE_MASK_A;
441 }
442 }
443
444 return cso;
445 }
446
447 static void
448 iris_bind_blend_state(struct pipe_context *ctx, void *state)
449 {
450 struct iris_context *ice = (struct iris_context *) ctx;
451 ice->state.cso_blend = state;
452 ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
453 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
454 }
455
456 struct iris_depth_stencil_alpha_state {
457 uint32_t wmds[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
458 uint32_t cc_vp[GENX(CC_VIEWPORT_length)];
459
460 struct pipe_alpha_state alpha; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
461 };
462
463 static void *
464 iris_create_zsa_state(struct pipe_context *ctx,
465 const struct pipe_depth_stencil_alpha_state *state)
466 {
467 struct iris_depth_stencil_alpha_state *cso =
468 malloc(sizeof(struct iris_depth_stencil_alpha_state));
469
470 cso->alpha = state->alpha;
471
472 bool two_sided_stencil = state->stencil[1].enabled;
473
474 /* The state tracker needs to optimize away EQUAL writes for us. */
475 assert(!(state->depth.func == PIPE_FUNC_EQUAL && state->depth.writemask));
476
477 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), cso->wmds, wmds) {
478 wmds.StencilFailOp = state->stencil[0].fail_op;
479 wmds.StencilPassDepthFailOp = state->stencil[0].zfail_op;
480 wmds.StencilPassDepthPassOp = state->stencil[0].zpass_op;
481 wmds.StencilTestFunction =
482 translate_compare_func(state->stencil[0].func);
483 wmds.BackfaceStencilFailOp = state->stencil[1].fail_op;
484 wmds.BackfaceStencilPassDepthFailOp = state->stencil[1].zfail_op;
485 wmds.BackfaceStencilPassDepthPassOp = state->stencil[1].zpass_op;
486 wmds.BackfaceStencilTestFunction =
487 translate_compare_func(state->stencil[1].func);
488 wmds.DepthTestFunction = translate_compare_func(state->depth.func);
489 wmds.DoubleSidedStencilEnable = two_sided_stencil;
490 wmds.StencilTestEnable = state->stencil[0].enabled;
491 wmds.StencilBufferWriteEnable =
492 state->stencil[0].writemask != 0 ||
493 (two_sided_stencil && state->stencil[1].writemask != 0);
494 wmds.DepthTestEnable = state->depth.enabled;
495 wmds.DepthBufferWriteEnable = state->depth.writemask;
496 wmds.StencilTestMask = state->stencil[0].valuemask;
497 wmds.StencilWriteMask = state->stencil[0].writemask;
498 wmds.BackfaceStencilTestMask = state->stencil[1].valuemask;
499 wmds.BackfaceStencilWriteMask = state->stencil[1].writemask;
500 /* wmds.[Backface]StencilReferenceValue are merged later */
501 }
502
503 iris_pack_state(GENX(CC_VIEWPORT), cso->cc_vp, ccvp) {
504 ccvp.MinimumDepth = state->depth.bounds_min;
505 ccvp.MaximumDepth = state->depth.bounds_max;
506 }
507
508 return cso;
509 }
510
511 static void
512 iris_bind_zsa_state(struct pipe_context *ctx, void *state)
513 {
514 struct iris_context *ice = (struct iris_context *) ctx;
515 struct iris_depth_stencil_alpha_state *old_cso = ice->state.cso_zsa;
516 struct iris_depth_stencil_alpha_state *new_cso = state;
517
518 if (new_cso) {
519 if (!old_cso || old_cso->alpha.ref_value != new_cso->alpha.ref_value) {
520 ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE;
521 }
522 }
523
524 ice->state.cso_zsa = new_cso;
525 ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
526 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
527 }
528
529 struct iris_rasterizer_state {
530 uint32_t sf[GENX(3DSTATE_SF_length)];
531 uint32_t clip[GENX(3DSTATE_CLIP_length)];
532 uint32_t raster[GENX(3DSTATE_RASTER_length)];
533 uint32_t wm[GENX(3DSTATE_WM_length)];
534 uint32_t line_stipple[GENX(3DSTATE_LINE_STIPPLE_length)];
535
536 bool flatshade; /* for shader state */
537 bool clamp_fragment_color; /* for shader state */
538 bool light_twoside; /* for shader state */
539 bool rasterizer_discard; /* for 3DSTATE_STREAMOUT */
540 bool half_pixel_center; /* for 3DSTATE_MULTISAMPLE */
541 enum pipe_sprite_coord_mode sprite_coord_mode; /* PIPE_SPRITE_* */
542 };
543
544 static void *
545 iris_create_rasterizer_state(struct pipe_context *ctx,
546 const struct pipe_rasterizer_state *state)
547 {
548 struct iris_rasterizer_state *cso =
549 malloc(sizeof(struct iris_rasterizer_state));
550
551 #if 0
552 sprite_coord_mode -> SBE PointSpriteTextureCoordinateOrigin
553 sprite_coord_enable -> SBE PointSpriteTextureCoordinateEnable
554 point_quad_rasterization -> SBE?
555
556 not necessary?
557 {
558 poly_smooth
559 force_persample_interp - ?
560 bottom_edge_rule
561
562 offset_units_unscaled - cap not exposed
563 }
564 #endif
565
566 cso->flatshade = state->flatshade;
567 cso->clamp_fragment_color = state->clamp_fragment_color;
568 cso->light_twoside = state->light_twoside;
569 cso->rasterizer_discard = state->rasterizer_discard;
570 cso->half_pixel_center = state->half_pixel_center;
571
572 iris_pack_command(GENX(3DSTATE_SF), cso->sf, sf) {
573 sf.StatisticsEnable = true;
574 sf.ViewportTransformEnable = true;
575 sf.AALineDistanceMode = AALINEDISTANCE_TRUE;
576 sf.LineEndCapAntialiasingRegionWidth =
577 state->line_smooth ? _10pixels : _05pixels;
578 sf.LastPixelEnable = state->line_last_pixel;
579 sf.LineWidth = state->line_width;
580 sf.SmoothPointEnable = state->point_smooth;
581 sf.PointWidthSource = state->point_size_per_vertex ? Vertex : State;
582 sf.PointWidth = state->point_size;
583
584 if (state->flatshade_first) {
585 sf.TriangleStripListProvokingVertexSelect = 2;
586 sf.TriangleFanProvokingVertexSelect = 2;
587 sf.LineStripListProvokingVertexSelect = 1;
588 } else {
589 sf.TriangleFanProvokingVertexSelect = 1;
590 }
591 }
592
593 /* COMPLETE! */
594 iris_pack_command(GENX(3DSTATE_RASTER), cso->raster, rr) {
595 rr.FrontWinding = state->front_ccw ? CounterClockwise : Clockwise;
596 rr.CullMode = translate_cull_mode(state->cull_face);
597 rr.FrontFaceFillMode = translate_fill_mode(state->fill_front);
598 rr.BackFaceFillMode = translate_fill_mode(state->fill_back);
599 rr.DXMultisampleRasterizationEnable = state->multisample;
600 rr.GlobalDepthOffsetEnableSolid = state->offset_tri;
601 rr.GlobalDepthOffsetEnableWireframe = state->offset_line;
602 rr.GlobalDepthOffsetEnablePoint = state->offset_point;
603 rr.GlobalDepthOffsetConstant = state->offset_units;
604 rr.GlobalDepthOffsetScale = state->offset_scale;
605 rr.GlobalDepthOffsetClamp = state->offset_clamp;
606 rr.SmoothPointEnable = state->point_smooth;
607 rr.AntialiasingEnable = state->line_smooth;
608 rr.ScissorRectangleEnable = state->scissor;
609 rr.ViewportZNearClipTestEnable = state->depth_clip_near;
610 rr.ViewportZFarClipTestEnable = state->depth_clip_far;
611 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
612 }
613
614 iris_pack_command(GENX(3DSTATE_CLIP), cso->clip, cl) {
615 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
616 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
617 */
618 cl.StatisticsEnable = true;
619 cl.EarlyCullEnable = true;
620 cl.UserClipDistanceClipTestEnableBitmask = state->clip_plane_enable;
621 cl.ForceUserClipDistanceClipTestEnableBitmask = true;
622 cl.APIMode = state->clip_halfz ? APIMODE_D3D : APIMODE_OGL;
623 cl.GuardbandClipTestEnable = true;
624 cl.ClipMode = CLIPMODE_NORMAL;
625 cl.ClipEnable = true;
626 cl.ViewportXYClipTestEnable = state->point_tri_clip;
627 cl.MinimumPointWidth = 0.125;
628 cl.MaximumPointWidth = 255.875;
629
630 if (state->flatshade_first) {
631 cl.TriangleStripListProvokingVertexSelect = 2;
632 cl.TriangleFanProvokingVertexSelect = 2;
633 cl.LineStripListProvokingVertexSelect = 1;
634 } else {
635 cl.TriangleFanProvokingVertexSelect = 1;
636 }
637 }
638
639 iris_pack_command(GENX(3DSTATE_WM), cso->wm, wm) {
640 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
641 * filled in at draw time from the FS program.
642 */
643 wm.LineAntialiasingRegionWidth = _10pixels;
644 wm.LineEndCapAntialiasingRegionWidth = _05pixels;
645 wm.PointRasterizationRule = RASTRULE_UPPER_RIGHT;
646 wm.StatisticsEnable = true;
647 wm.LineStippleEnable = state->line_stipple_enable;
648 wm.PolygonStippleEnable = state->poly_stipple_enable;
649 }
650
651 /* Remap from 0..255 back to 1..256 */
652 const unsigned line_stipple_factor = state->line_stipple_factor + 1;
653
654 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE), cso->line_stipple, line) {
655 line.LineStipplePattern = state->line_stipple_pattern;
656 line.LineStippleInverseRepeatCount = 1.0f / line_stipple_factor;
657 line.LineStippleRepeatCount = line_stipple_factor;
658 }
659
660 return cso;
661 }
662
663 static void
664 iris_bind_rasterizer_state(struct pipe_context *ctx, void *state)
665 {
666 struct iris_context *ice = (struct iris_context *) ctx;
667 struct iris_rasterizer_state *old_cso = ice->state.cso_rast;
668 struct iris_rasterizer_state *new_cso = state;
669
670 if (new_cso) {
671 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
672 if (!old_cso || memcmp(old_cso->line_stipple, new_cso->line_stipple,
673 sizeof(old_cso->line_stipple)) != 0) {
674 ice->state.dirty |= IRIS_DIRTY_LINE_STIPPLE;
675 }
676
677 if (!old_cso ||
678 old_cso->half_pixel_center != new_cso->half_pixel_center) {
679 ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
680 }
681 }
682
683 ice->state.cso_rast = new_cso;
684 ice->state.dirty |= IRIS_DIRTY_RASTER;
685 }
686
687 static uint32_t
688 translate_wrap(unsigned pipe_wrap)
689 {
690 static const unsigned map[] = {
691 [PIPE_TEX_WRAP_REPEAT] = TCM_WRAP,
692 [PIPE_TEX_WRAP_CLAMP] = TCM_HALF_BORDER,
693 [PIPE_TEX_WRAP_CLAMP_TO_EDGE] = TCM_CLAMP,
694 [PIPE_TEX_WRAP_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
695 [PIPE_TEX_WRAP_MIRROR_REPEAT] = TCM_MIRROR,
696 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
697 [PIPE_TEX_WRAP_MIRROR_CLAMP] = -1, // XXX: ???
698 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER] = -1, // XXX: ???
699 };
700 return map[pipe_wrap];
701 }
702
703 /**
704 * Return true if the given wrap mode requires the border color to exist.
705 */
706 static bool
707 wrap_mode_needs_border_color(unsigned wrap_mode)
708 {
709 return wrap_mode == TCM_CLAMP_BORDER || wrap_mode == TCM_HALF_BORDER;
710 }
711
712 static unsigned
713 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip)
714 {
715 static const unsigned map[] = {
716 [PIPE_TEX_MIPFILTER_NEAREST] = MIPFILTER_NEAREST,
717 [PIPE_TEX_MIPFILTER_LINEAR] = MIPFILTER_LINEAR,
718 [PIPE_TEX_MIPFILTER_NONE] = MIPFILTER_NONE,
719 };
720 return map[pipe_mip];
721 }
722
723 struct iris_sampler_state {
724 struct pipe_sampler_state base;
725
726 bool needs_border_color;
727
728 uint32_t sampler_state[GENX(SAMPLER_STATE_length)];
729 };
730
731 static void *
732 iris_create_sampler_state(struct pipe_context *pctx,
733 const struct pipe_sampler_state *state)
734 {
735 struct iris_sampler_state *cso = CALLOC_STRUCT(iris_sampler_state);
736
737 if (!cso)
738 return NULL;
739
740 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST == MAPFILTER_NEAREST);
741 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR == MAPFILTER_LINEAR);
742
743 unsigned wrap_s = translate_wrap(state->wrap_s);
744 unsigned wrap_t = translate_wrap(state->wrap_t);
745 unsigned wrap_r = translate_wrap(state->wrap_r);
746
747 cso->needs_border_color = wrap_mode_needs_border_color(wrap_s) ||
748 wrap_mode_needs_border_color(wrap_t) ||
749 wrap_mode_needs_border_color(wrap_r);
750
751 iris_pack_state(GENX(SAMPLER_STATE), cso->sampler_state, samp) {
752 samp.TCXAddressControlMode = wrap_s;
753 samp.TCYAddressControlMode = wrap_t;
754 samp.TCZAddressControlMode = wrap_r;
755 samp.CubeSurfaceControlMode = state->seamless_cube_map;
756 samp.NonnormalizedCoordinateEnable = !state->normalized_coords;
757 samp.MinModeFilter = state->min_img_filter;
758 samp.MagModeFilter = state->mag_img_filter;
759 samp.MipModeFilter = translate_mip_filter(state->min_mip_filter);
760 samp.MaximumAnisotropy = RATIO21;
761
762 if (state->max_anisotropy >= 2) {
763 if (state->min_img_filter == PIPE_TEX_FILTER_LINEAR) {
764 samp.MinModeFilter = MAPFILTER_ANISOTROPIC;
765 samp.AnisotropicAlgorithm = EWAApproximation;
766 }
767
768 if (state->mag_img_filter == PIPE_TEX_FILTER_LINEAR)
769 samp.MagModeFilter = MAPFILTER_ANISOTROPIC;
770
771 samp.MaximumAnisotropy =
772 MIN2((state->max_anisotropy - 2) / 2, RATIO161);
773 }
774
775 /* Set address rounding bits if not using nearest filtering. */
776 if (state->min_img_filter != PIPE_TEX_FILTER_NEAREST) {
777 samp.UAddressMinFilterRoundingEnable = true;
778 samp.VAddressMinFilterRoundingEnable = true;
779 samp.RAddressMinFilterRoundingEnable = true;
780 }
781
782 if (state->mag_img_filter != PIPE_TEX_FILTER_NEAREST) {
783 samp.UAddressMagFilterRoundingEnable = true;
784 samp.VAddressMagFilterRoundingEnable = true;
785 samp.RAddressMagFilterRoundingEnable = true;
786 }
787
788 if (state->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
789 samp.ShadowFunction = translate_shadow_func(state->compare_func);
790
791 const float hw_max_lod = GEN_GEN >= 7 ? 14 : 13;
792
793 samp.LODPreClampMode = CLAMP_MODE_OGL;
794 samp.MinLOD = CLAMP(state->min_lod, 0, hw_max_lod);
795 samp.MaxLOD = CLAMP(state->max_lod, 0, hw_max_lod);
796 samp.TextureLODBias = CLAMP(state->lod_bias, -16, 15);
797
798 //samp.BorderColorPointer = <<comes from elsewhere>>
799 }
800
801 return cso;
802 }
803
804 static void
805 iris_bind_sampler_states(struct pipe_context *ctx,
806 enum pipe_shader_type p_stage,
807 unsigned start, unsigned count,
808 void **states)
809 {
810 struct iris_context *ice = (struct iris_context *) ctx;
811 gl_shader_stage stage = stage_from_pipe(p_stage);
812
813 assert(start + count <= IRIS_MAX_TEXTURE_SAMPLERS);
814
815 for (int i = 0; i < count; i++) {
816 ice->state.samplers[stage][start + i] = states[i];
817 }
818
819 ice->state.dirty |= IRIS_DIRTY_SAMPLER_STATES_VS << stage;
820 }
821
822 struct iris_sampler_view {
823 struct pipe_sampler_view pipe;
824 struct isl_view view;
825 uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
826 };
827
828 /**
829 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
830 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
831 *
832 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
833 * 0 1 2 3 4 5
834 * 4 5 6 7 0 1
835 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
836 *
837 * which is simply adding 4 then modding by 8 (or anding with 7).
838 *
839 * We then may need to apply workarounds for textureGather hardware bugs.
840 */
841 static enum isl_channel_select
842 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle)
843 {
844 return (swizzle + 4) & 7;
845 }
846
847 static struct pipe_sampler_view *
848 iris_create_sampler_view(struct pipe_context *ctx,
849 struct pipe_resource *tex,
850 const struct pipe_sampler_view *tmpl)
851 {
852 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
853 struct iris_resource *itex = (struct iris_resource *) tex;
854 struct iris_sampler_view *isv = calloc(1, sizeof(struct iris_sampler_view));
855
856 if (!isv)
857 return NULL;
858
859 /* initialize base object */
860 isv->pipe = *tmpl;
861 isv->pipe.context = ctx;
862 isv->pipe.texture = NULL;
863 pipe_reference_init(&isv->pipe.reference, 1);
864 pipe_resource_reference(&isv->pipe.texture, tex);
865
866 /* XXX: do we need brw_get_texture_swizzle hacks here? */
867
868 isv->view = (struct isl_view) {
869 .format = iris_isl_format_for_pipe_format(tmpl->format),
870 .base_level = tmpl->u.tex.first_level,
871 .levels = tmpl->u.tex.last_level - tmpl->u.tex.first_level + 1,
872 .base_array_layer = tmpl->u.tex.first_layer,
873 .array_len = tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1,
874 .swizzle = (struct isl_swizzle) {
875 .r = pipe_swizzle_to_isl_channel(tmpl->swizzle_r),
876 .g = pipe_swizzle_to_isl_channel(tmpl->swizzle_g),
877 .b = pipe_swizzle_to_isl_channel(tmpl->swizzle_b),
878 .a = pipe_swizzle_to_isl_channel(tmpl->swizzle_a),
879 },
880 .usage = ISL_SURF_USAGE_TEXTURE_BIT,
881 };
882
883 isl_surf_fill_state(&screen->isl_dev, isv->surface_state,
884 .surf = &itex->surf, .view = &isv->view,
885 .mocs = MOCS_WB);
886 // .address = ...
887 // .aux_surf =
888 // .clear_color = clear_color,
889
890 return &isv->pipe;
891 }
892
893 struct iris_surface {
894 struct pipe_surface pipe;
895 struct isl_view view;
896 uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
897 };
898
899 static struct pipe_surface *
900 iris_create_surface(struct pipe_context *ctx,
901 struct pipe_resource *tex,
902 const struct pipe_surface *tmpl)
903 {
904 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
905 struct iris_surface *surf = calloc(1, sizeof(struct iris_surface));
906 struct pipe_surface *psurf = &surf->pipe;
907 struct iris_resource *itex = (struct iris_resource *) tex;
908
909 if (!surf)
910 return NULL;
911
912 pipe_reference_init(&psurf->reference, 1);
913 pipe_resource_reference(&psurf->texture, tex);
914 psurf->context = ctx;
915 psurf->format = tmpl->format;
916 psurf->width = tex->width0;
917 psurf->height = tex->height0;
918 psurf->texture = tex;
919 psurf->u.tex.first_layer = tmpl->u.tex.first_layer;
920 psurf->u.tex.last_layer = tmpl->u.tex.last_layer;
921 psurf->u.tex.level = tmpl->u.tex.level;
922
923 surf->view = (struct isl_view) {
924 .format = iris_isl_format_for_pipe_format(tmpl->format),
925 .base_level = tmpl->u.tex.level,
926 .levels = 1,
927 .base_array_layer = tmpl->u.tex.first_layer,
928 .array_len = tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1,
929 .swizzle = ISL_SWIZZLE_IDENTITY,
930 // XXX: DEPTH_BIt, STENCIL_BIT...CUBE_BIT? Other bits?!
931 .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT,
932 };
933
934 isl_surf_fill_state(&screen->isl_dev, surf->surface_state,
935 .surf = &itex->surf, .view = &surf->view,
936 .mocs = MOCS_WB);
937 // .address = ...
938 // .aux_surf =
939 // .clear_color = clear_color,
940
941 return psurf;
942 }
943
944 static void
945 iris_set_sampler_views(struct pipe_context *ctx,
946 enum pipe_shader_type shader,
947 unsigned start, unsigned count,
948 struct pipe_sampler_view **views)
949 {
950 }
951
952 static void
953 iris_set_clip_state(struct pipe_context *ctx,
954 const struct pipe_clip_state *state)
955 {
956 }
957
958 static void
959 iris_set_polygon_stipple(struct pipe_context *ctx,
960 const struct pipe_poly_stipple *state)
961 {
962 struct iris_context *ice = (struct iris_context *) ctx;
963 memcpy(&ice->state.poly_stipple, state, sizeof(*state));
964 ice->state.dirty |= IRIS_DIRTY_POLYGON_STIPPLE;
965 }
966
967 static void
968 iris_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
969 {
970 struct iris_context *ice = (struct iris_context *) ctx;
971
972 ice->state.sample_mask = sample_mask;
973 ice->state.dirty |= IRIS_DIRTY_SAMPLE_MASK;
974 }
975
976 static void
977 iris_set_scissor_states(struct pipe_context *ctx,
978 unsigned start_slot,
979 unsigned num_scissors,
980 const struct pipe_scissor_state *states)
981 {
982 struct iris_context *ice = (struct iris_context *) ctx;
983
984 ice->state.num_scissors = num_scissors;
985
986 for (unsigned i = 0; i < num_scissors; i++) {
987 ice->state.scissors[start_slot + i] = states[i];
988 }
989
990 ice->state.dirty |= IRIS_DIRTY_SCISSOR_RECT;
991 }
992
993 static void
994 iris_set_stencil_ref(struct pipe_context *ctx,
995 const struct pipe_stencil_ref *state)
996 {
997 struct iris_context *ice = (struct iris_context *) ctx;
998 memcpy(&ice->state.stencil_ref, state, sizeof(*state));
999 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
1000 }
1001
1002
1003 struct iris_viewport_state {
1004 uint32_t sf_cl_vp[GENX(SF_CLIP_VIEWPORT_length)];
1005 };
1006
1007 static float
1008 extent_from_matrix(const struct pipe_viewport_state *state, int axis)
1009 {
1010 return fabsf(state->scale[axis]) * state->translate[axis];
1011 }
1012
1013 #if 0
1014 static void
1015 calculate_guardband_size(uint32_t fb_width, uint32_t fb_height,
1016 float m00, float m11, float m30, float m31,
1017 float *xmin, float *xmax,
1018 float *ymin, float *ymax)
1019 {
1020 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1021 * Strips and Fans documentation:
1022 *
1023 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1024 * fixed-point "guardband" range supported by the rasterization hardware"
1025 *
1026 * and
1027 *
1028 * "In almost all circumstances, if an object’s vertices are actually
1029 * modified by this clamping (i.e., had X or Y coordinates outside of
1030 * the guardband extent the rendered object will not match the intended
1031 * result. Therefore software should take steps to ensure that this does
1032 * not happen - e.g., by clipping objects such that they do not exceed
1033 * these limits after the Drawing Rectangle is applied."
1034 *
1035 * I believe the fundamental restriction is that the rasterizer (in
1036 * the SF/WM stages) have a limit on the number of pixels that can be
1037 * rasterized. We need to ensure any coordinates beyond the rasterizer
1038 * limit are handled by the clipper. So effectively that limit becomes
1039 * the clipper's guardband size.
1040 *
1041 * It goes on to say:
1042 *
1043 * "In addition, in order to be correctly rendered, objects must have a
1044 * screenspace bounding box not exceeding 8K in the X or Y direction.
1045 * This additional restriction must also be comprehended by software,
1046 * i.e., enforced by use of clipping."
1047 *
1048 * This makes no sense. Gen7+ hardware supports 16K render targets,
1049 * and you definitely need to be able to draw polygons that fill the
1050 * surface. Our assumption is that the rasterizer was limited to 8K
1051 * on Sandybridge, which only supports 8K surfaces, and it was actually
1052 * increased to 16K on Ivybridge and later.
1053 *
1054 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1055 */
1056 const float gb_size = GEN_GEN >= 7 ? 16384.0f : 8192.0f;
1057
1058 if (m00 != 0 && m11 != 0) {
1059 /* First, we compute the screen-space render area */
1060 const float ss_ra_xmin = MIN3( 0, m30 + m00, m30 - m00);
1061 const float ss_ra_xmax = MAX3( fb_width, m30 + m00, m30 - m00);
1062 const float ss_ra_ymin = MIN3( 0, m31 + m11, m31 - m11);
1063 const float ss_ra_ymax = MAX3(fb_height, m31 + m11, m31 - m11);
1064
1065 /* We want the guardband to be centered on that */
1066 const float ss_gb_xmin = (ss_ra_xmin + ss_ra_xmax) / 2 - gb_size;
1067 const float ss_gb_xmax = (ss_ra_xmin + ss_ra_xmax) / 2 + gb_size;
1068 const float ss_gb_ymin = (ss_ra_ymin + ss_ra_ymax) / 2 - gb_size;
1069 const float ss_gb_ymax = (ss_ra_ymin + ss_ra_ymax) / 2 + gb_size;
1070
1071 /* Now we need it in native device coordinates */
1072 const float ndc_gb_xmin = (ss_gb_xmin - m30) / m00;
1073 const float ndc_gb_xmax = (ss_gb_xmax - m30) / m00;
1074 const float ndc_gb_ymin = (ss_gb_ymin - m31) / m11;
1075 const float ndc_gb_ymax = (ss_gb_ymax - m31) / m11;
1076
1077 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1078 * flipped upside-down. X should be fine though.
1079 */
1080 assert(ndc_gb_xmin <= ndc_gb_xmax);
1081 *xmin = ndc_gb_xmin;
1082 *xmax = ndc_gb_xmax;
1083 *ymin = MIN2(ndc_gb_ymin, ndc_gb_ymax);
1084 *ymax = MAX2(ndc_gb_ymin, ndc_gb_ymax);
1085 } else {
1086 /* The viewport scales to 0, so nothing will be rendered. */
1087 *xmin = 0.0f;
1088 *xmax = 0.0f;
1089 *ymin = 0.0f;
1090 *ymax = 0.0f;
1091 }
1092 }
1093 #endif
1094
1095 static void
1096 iris_set_viewport_states(struct pipe_context *ctx,
1097 unsigned start_slot,
1098 unsigned num_viewports,
1099 const struct pipe_viewport_state *state)
1100 {
1101 struct iris_context *ice = (struct iris_context *) ctx;
1102 struct iris_viewport_state *cso =
1103 malloc(sizeof(struct iris_viewport_state));
1104
1105 // XXX: sf_cl_vp is only big enough for one slot, we don't iterate right
1106 for (unsigned i = start_slot; i < start_slot + num_viewports; i++) {
1107 float x_extent = extent_from_matrix(&state[i], 0);
1108 float y_extent = extent_from_matrix(&state[i], 1);
1109
1110 iris_pack_state(GENX(SF_CLIP_VIEWPORT), cso->sf_cl_vp, vp) {
1111 vp.ViewportMatrixElementm00 = state[i].scale[0];
1112 vp.ViewportMatrixElementm11 = state[i].scale[1];
1113 vp.ViewportMatrixElementm22 = state[i].scale[2];
1114 vp.ViewportMatrixElementm30 = state[i].translate[0];
1115 vp.ViewportMatrixElementm31 = state[i].translate[1];
1116 vp.ViewportMatrixElementm32 = state[i].translate[2];
1117 /* XXX: in i965 this is computed based on the drawbuffer size,
1118 * but we don't have that here...
1119 */
1120 vp.XMinClipGuardband = -1.0;
1121 vp.XMaxClipGuardband = 1.0;
1122 vp.YMinClipGuardband = -1.0;
1123 vp.YMaxClipGuardband = 1.0;
1124 vp.XMinViewPort = -x_extent;
1125 vp.XMaxViewPort = x_extent;
1126 vp.YMinViewPort = -y_extent;
1127 vp.YMaxViewPort = y_extent;
1128 }
1129 }
1130
1131 ice->state.cso_vp = cso;
1132 // XXX: start_slot
1133 ice->state.num_viewports = num_viewports;
1134 ice->state.dirty |= IRIS_DIRTY_SF_CL_VIEWPORT;
1135 }
1136
1137 struct iris_depth_state
1138 {
1139 uint32_t depth_buffer[GENX(3DSTATE_DEPTH_BUFFER_length)];
1140 uint32_t hier_depth_buffer[GENX(3DSTATE_HIER_DEPTH_BUFFER_length)];
1141 uint32_t stencil_buffer[GENX(3DSTATE_STENCIL_BUFFER_length)];
1142 };
1143
1144 static void
1145 iris_set_framebuffer_state(struct pipe_context *ctx,
1146 const struct pipe_framebuffer_state *state)
1147 {
1148 struct iris_context *ice = (struct iris_context *) ctx;
1149 struct pipe_framebuffer_state *cso = &ice->state.framebuffer;
1150
1151 if (cso->samples != state->samples) {
1152 ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
1153 }
1154
1155 cso->width = state->width;
1156 cso->height = state->height;
1157 cso->layers = state->layers;
1158 cso->samples = state->samples;
1159
1160 unsigned i;
1161 for (i = 0; i < state->nr_cbufs; i++)
1162 pipe_surface_reference(&cso->cbufs[i], state->cbufs[i]);
1163 for (; i < cso->nr_cbufs; i++)
1164 pipe_surface_reference(&cso->cbufs[i], NULL);
1165
1166 cso->nr_cbufs = state->nr_cbufs;
1167
1168 pipe_surface_reference(&cso->zsbuf, state->zsbuf);
1169
1170 struct isl_depth_stencil_hiz_emit_info info = {
1171 .mocs = MOCS_WB,
1172 };
1173
1174 // XXX: depth buffers
1175 }
1176
1177 static void
1178 iris_set_constant_buffer(struct pipe_context *ctx,
1179 enum pipe_shader_type shader, uint index,
1180 const struct pipe_constant_buffer *cb)
1181 {
1182 }
1183
1184
1185 static void
1186 iris_sampler_view_destroy(struct pipe_context *ctx,
1187 struct pipe_sampler_view *state)
1188 {
1189 pipe_resource_reference(&state->texture, NULL);
1190 free(state);
1191 }
1192
1193
1194 static void
1195 iris_surface_destroy(struct pipe_context *ctx, struct pipe_surface *surface)
1196 {
1197 pipe_resource_reference(&surface->texture, NULL);
1198 free(surface);
1199 }
1200
1201 static void
1202 iris_delete_state(struct pipe_context *ctx, void *state)
1203 {
1204 free(state);
1205 }
1206
1207 struct iris_vertex_buffer_state {
1208 uint32_t vertex_buffers[1 + 33 * GENX(VERTEX_BUFFER_STATE_length)];
1209 struct iris_address bos[33];
1210 unsigned num_buffers;
1211 };
1212
1213 static void
1214 iris_free_vertex_buffers(struct iris_vertex_buffer_state *cso)
1215 {
1216 if (cso) {
1217 for (unsigned i = 0; i < cso->num_buffers; i++)
1218 iris_bo_unreference(cso->bos[i].bo);
1219 free(cso);
1220 }
1221 }
1222
1223 static void
1224 iris_set_vertex_buffers(struct pipe_context *ctx,
1225 unsigned start_slot, unsigned count,
1226 const struct pipe_vertex_buffer *buffers)
1227 {
1228 struct iris_context *ice = (struct iris_context *) ctx;
1229 struct iris_vertex_buffer_state *cso =
1230 malloc(sizeof(struct iris_vertex_buffer_state));
1231
1232 /* If there are no buffers, do nothing. We can leave the stale
1233 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1234 * elements that point to them, it should be fine.
1235 */
1236 if (!buffers)
1237 return;
1238
1239 iris_free_vertex_buffers(ice->state.cso_vertex_buffers);
1240
1241 cso->num_buffers = count;
1242
1243 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS), cso->vertex_buffers, vb) {
1244 vb.DWordLength = 4 * cso->num_buffers - 1;
1245 }
1246
1247 uint32_t *vb_pack_dest = &cso->vertex_buffers[1];
1248
1249 for (unsigned i = 0; i < count; i++) {
1250 assert(!buffers[i].is_user_buffer);
1251
1252 struct iris_resource *res = (void *) buffers[i].buffer.resource;
1253 iris_bo_reference(res->bo);
1254 cso->bos[i] = ro_bo(res->bo, buffers[i].buffer_offset);
1255
1256 iris_pack_state(GENX(VERTEX_BUFFER_STATE), vb_pack_dest, vb) {
1257 vb.VertexBufferIndex = start_slot + i;
1258 vb.MOCS = MOCS_WB;
1259 vb.AddressModifyEnable = true;
1260 vb.BufferPitch = buffers[i].stride;
1261 vb.BufferSize = res->bo->size;
1262 /* vb.BufferStartingAddress is filled in at draw time */
1263 }
1264
1265 vb_pack_dest += GENX(VERTEX_BUFFER_STATE_length);
1266 }
1267
1268 ice->state.cso_vertex_buffers = cso;
1269 ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS;
1270 }
1271
1272 struct iris_vertex_element_state {
1273 uint32_t vertex_elements[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length)];
1274 uint32_t vf_instancing[GENX(3DSTATE_VF_INSTANCING_length)][33];
1275 unsigned count;
1276 };
1277
1278 static void *
1279 iris_create_vertex_elements(struct pipe_context *ctx,
1280 unsigned count,
1281 const struct pipe_vertex_element *state)
1282 {
1283 struct iris_vertex_element_state *cso =
1284 malloc(sizeof(struct iris_vertex_element_state));
1285
1286 cso->count = count;
1287
1288 /* TODO:
1289 * - create edge flag one
1290 * - create SGV ones
1291 * - if those are necessary, use count + 1/2/3... OR in the length
1292 */
1293 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS), cso->vertex_elements, ve);
1294
1295 uint32_t *ve_pack_dest = &cso->vertex_elements[1];
1296
1297 for (int i = 0; i < count; i++) {
1298 iris_pack_state(GENX(VERTEX_ELEMENT_STATE), ve_pack_dest, ve) {
1299 ve.VertexBufferIndex = state[i].vertex_buffer_index;
1300 ve.Valid = true;
1301 ve.SourceElementOffset = state[i].src_offset;
1302 ve.SourceElementFormat =
1303 iris_isl_format_for_pipe_format(state[i].src_format);
1304 }
1305
1306 iris_pack_command(GENX(3DSTATE_VF_INSTANCING), cso->vf_instancing[i], vi) {
1307 vi.VertexElementIndex = i;
1308 vi.InstancingEnable = state[i].instance_divisor > 0;
1309 vi.InstanceDataStepRate = state[i].instance_divisor;
1310 }
1311
1312 ve_pack_dest += GENX(VERTEX_ELEMENT_STATE_length);
1313 }
1314
1315 return cso;
1316 }
1317
1318 static void
1319 iris_bind_vertex_elements_state(struct pipe_context *ctx, void *state)
1320 {
1321 struct iris_context *ice = (struct iris_context *) ctx;
1322
1323 ice->state.cso_vertex_elements = state;
1324 ice->state.dirty |= IRIS_DIRTY_VERTEX_ELEMENTS;
1325 }
1326
1327 static void *
1328 iris_create_compute_state(struct pipe_context *ctx,
1329 const struct pipe_compute_state *state)
1330 {
1331 return malloc(1);
1332 }
1333
1334 static struct pipe_stream_output_target *
1335 iris_create_stream_output_target(struct pipe_context *ctx,
1336 struct pipe_resource *res,
1337 unsigned buffer_offset,
1338 unsigned buffer_size)
1339 {
1340 struct pipe_stream_output_target *t =
1341 CALLOC_STRUCT(pipe_stream_output_target);
1342 if (!t)
1343 return NULL;
1344
1345 pipe_reference_init(&t->reference, 1);
1346 pipe_resource_reference(&t->buffer, res);
1347 t->buffer_offset = buffer_offset;
1348 t->buffer_size = buffer_size;
1349 return t;
1350 }
1351
1352 static void
1353 iris_stream_output_target_destroy(struct pipe_context *ctx,
1354 struct pipe_stream_output_target *t)
1355 {
1356 pipe_resource_reference(&t->buffer, NULL);
1357 free(t);
1358 }
1359
1360 static void
1361 iris_set_stream_output_targets(struct pipe_context *ctx,
1362 unsigned num_targets,
1363 struct pipe_stream_output_target **targets,
1364 const unsigned *offsets)
1365 {
1366 }
1367
1368 static void
1369 iris_bind_compute_state(struct pipe_context *ctx, void *state)
1370 {
1371 }
1372
1373 static void
1374 iris_populate_vs_key(const struct iris_context *ice,
1375 struct brw_vs_prog_key *key)
1376 {
1377 memset(key, 0, sizeof(*key));
1378 }
1379
1380 static void
1381 iris_populate_tcs_key(const struct iris_context *ice,
1382 struct brw_tcs_prog_key *key)
1383 {
1384 memset(key, 0, sizeof(*key));
1385 }
1386
1387 static void
1388 iris_populate_tes_key(const struct iris_context *ice,
1389 struct brw_tes_prog_key *key)
1390 {
1391 memset(key, 0, sizeof(*key));
1392 }
1393
1394 static void
1395 iris_populate_gs_key(const struct iris_context *ice,
1396 struct brw_gs_prog_key *key)
1397 {
1398 memset(key, 0, sizeof(*key));
1399 }
1400
1401 static void
1402 iris_populate_fs_key(const struct iris_context *ice,
1403 struct brw_wm_prog_key *key)
1404 {
1405 memset(key, 0, sizeof(*key));
1406
1407 /* XXX: dirty flags? */
1408 struct pipe_framebuffer_state *fb = &ice->state.framebuffer;
1409 struct iris_depth_stencil_alpha_state *zsa = ice->state.cso_zsa;
1410 struct iris_rasterizer_state *rast = ice->state.cso_rast;
1411 struct iris_blend_state *blend = ice->state.cso_blend;
1412
1413 key->nr_color_regions = fb->nr_cbufs;
1414
1415 key->clamp_fragment_color = rast->clamp_fragment_color;
1416
1417 key->replicate_alpha = fb->nr_cbufs > 1 &&
1418 (zsa->alpha.enabled || blend->alpha_to_coverage);
1419
1420 // key->force_dual_color_blend for unigine
1421 #if 0
1422 if (cso_rast->multisample) {
1423 key->persample_interp =
1424 ctx->Multisample.SampleShading &&
1425 (ctx->Multisample.MinSampleShadingValue *
1426 _mesa_geometric_samples(ctx->DrawBuffer) > 1);
1427
1428 key->multisample_fbo = fb->samples > 1;
1429 }
1430 #endif
1431
1432 key->coherent_fb_fetch = true;
1433 }
1434
1435 //pkt.SamplerCount = \
1436 //DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1437 //pkt.PerThreadScratchSpace = prog_data->total_scratch == 0 ? 0 : \
1438 //ffs(stage_state->per_thread_scratch) - 11; \
1439
1440 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1441 pkt.KernelStartPointer = shader->prog_offset; \
1442 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
1443 pkt.FloatingPointMode = prog_data->use_alt_mode; \
1444 \
1445 pkt.DispatchGRFStartRegisterForURBData = \
1446 prog_data->dispatch_grf_start_reg; \
1447 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1448 pkt.prefix##URBEntryReadOffset = 0; \
1449 \
1450 pkt.StatisticsEnable = true; \
1451 pkt.Enable = true;
1452
1453 static void
1454 iris_set_vs_state(const struct gen_device_info *devinfo,
1455 struct iris_compiled_shader *shader)
1456 {
1457 struct brw_stage_prog_data *prog_data = shader->prog_data;
1458 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1459
1460 iris_pack_command(GENX(3DSTATE_VS), shader->derived_data, vs) {
1461 INIT_THREAD_DISPATCH_FIELDS(vs, Vertex);
1462 vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
1463 vs.SIMD8DispatchEnable = true;
1464 vs.UserClipDistanceCullTestEnableBitmask =
1465 vue_prog_data->cull_distance_mask;
1466 }
1467 }
1468
1469 static void
1470 iris_set_tcs_state(const struct gen_device_info *devinfo,
1471 struct iris_compiled_shader *shader)
1472 {
1473 struct brw_stage_prog_data *prog_data = shader->prog_data;
1474 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1475 struct brw_tcs_prog_data *tcs_prog_data = (void *) prog_data;
1476
1477 iris_pack_command(GENX(3DSTATE_HS), shader->derived_data, hs) {
1478 INIT_THREAD_DISPATCH_FIELDS(hs, Vertex);
1479
1480 hs.InstanceCount = tcs_prog_data->instances - 1;
1481 hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
1482 hs.IncludeVertexHandles = true;
1483 }
1484 }
1485
1486 static void
1487 iris_set_tes_state(const struct gen_device_info *devinfo,
1488 struct iris_compiled_shader *shader)
1489 {
1490 struct brw_stage_prog_data *prog_data = shader->prog_data;
1491 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1492 struct brw_tes_prog_data *tes_prog_data = (void *) prog_data;
1493
1494 uint32_t *te_state = (void *) shader->derived_data;
1495 uint32_t *ds_state = te_state + GENX(3DSTATE_TE_length);
1496
1497 iris_pack_command(GENX(3DSTATE_TE), te_state, te) {
1498 te.Partitioning = tes_prog_data->partitioning;
1499 te.OutputTopology = tes_prog_data->output_topology;
1500 te.TEDomain = tes_prog_data->domain;
1501 te.TEEnable = true;
1502 te.MaximumTessellationFactorOdd = 63.0;
1503 te.MaximumTessellationFactorNotOdd = 64.0;
1504 }
1505
1506 iris_pack_command(GENX(3DSTATE_DS), ds_state, ds) {
1507 INIT_THREAD_DISPATCH_FIELDS(ds, Patch);
1508
1509 ds.DispatchMode = DISPATCH_MODE_SIMD8_SINGLE_PATCH;
1510 ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
1511 ds.ComputeWCoordinateEnable =
1512 tes_prog_data->domain == BRW_TESS_DOMAIN_TRI;
1513
1514 ds.UserClipDistanceCullTestEnableBitmask =
1515 vue_prog_data->cull_distance_mask;
1516 }
1517
1518 }
1519
1520 static void
1521 iris_set_gs_state(const struct gen_device_info *devinfo,
1522 struct iris_compiled_shader *shader)
1523 {
1524 struct brw_stage_prog_data *prog_data = shader->prog_data;
1525 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1526 struct brw_gs_prog_data *gs_prog_data = (void *) prog_data;
1527
1528 iris_pack_command(GENX(3DSTATE_GS), shader->derived_data, gs) {
1529 INIT_THREAD_DISPATCH_FIELDS(gs, Vertex);
1530
1531 gs.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1;
1532 gs.OutputTopology = gs_prog_data->output_topology;
1533 gs.ControlDataHeaderSize =
1534 gs_prog_data->control_data_header_size_hwords;
1535 gs.InstanceControl = gs_prog_data->invocations - 1;
1536 gs.DispatchMode = SIMD8;
1537 gs.IncludePrimitiveID = gs_prog_data->include_primitive_id;
1538 gs.ControlDataFormat = gs_prog_data->control_data_format;
1539 gs.ReorderMode = TRAILING;
1540 gs.ExpectedVertexCount = gs_prog_data->vertices_in;
1541 gs.MaximumNumberofThreads =
1542 GEN_GEN == 8 ? (devinfo->max_gs_threads / 2 - 1)
1543 : (devinfo->max_gs_threads - 1);
1544
1545 if (gs_prog_data->static_vertex_count != -1) {
1546 gs.StaticOutput = true;
1547 gs.StaticOutputVertexCount = gs_prog_data->static_vertex_count;
1548 }
1549 gs.IncludeVertexHandles = vue_prog_data->include_vue_handles;
1550
1551 gs.UserClipDistanceCullTestEnableBitmask =
1552 vue_prog_data->cull_distance_mask;
1553
1554 const int urb_entry_write_offset = 1;
1555 const uint32_t urb_entry_output_length =
1556 DIV_ROUND_UP(vue_prog_data->vue_map.num_slots, 2) -
1557 urb_entry_write_offset;
1558
1559 gs.VertexURBEntryOutputReadOffset = urb_entry_write_offset;
1560 gs.VertexURBEntryOutputLength = MAX2(urb_entry_output_length, 1);
1561 }
1562 }
1563
1564 static void
1565 iris_set_fs_state(const struct gen_device_info *devinfo,
1566 struct iris_compiled_shader *shader)
1567 {
1568 struct brw_stage_prog_data *prog_data = shader->prog_data;
1569 struct brw_wm_prog_data *wm_prog_data = (void *) shader->prog_data;
1570
1571 uint32_t *ps_state = (void *) shader->derived_data;
1572 uint32_t *psx_state = ps_state + GENX(3DSTATE_PS_length);
1573
1574 iris_pack_command(GENX(3DSTATE_PS), ps_state, ps) {
1575 ps.VectorMaskEnable = true;
1576 //ps.SamplerCount = ...
1577 ps.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4;
1578 ps.FloatingPointMode = prog_data->use_alt_mode;
1579 ps.MaximumNumberofThreadsPerPSD = 64 - (GEN_GEN == 8 ? 2 : 1);
1580
1581 ps.PushConstantEnable = prog_data->nr_params > 0 ||
1582 prog_data->ubo_ranges[0].length > 0;
1583
1584 /* From the documentation for this packet:
1585 * "If the PS kernel does not need the Position XY Offsets to
1586 * compute a Position Value, then this field should be programmed
1587 * to POSOFFSET_NONE."
1588 *
1589 * "SW Recommendation: If the PS kernel needs the Position Offsets
1590 * to compute a Position XY value, this field should match Position
1591 * ZW Interpolation Mode to ensure a consistent position.xyzw
1592 * computation."
1593 *
1594 * We only require XY sample offsets. So, this recommendation doesn't
1595 * look useful at the moment. We might need this in future.
1596 */
1597 ps.PositionXYOffsetSelect =
1598 wm_prog_data->uses_pos_offset ? POSOFFSET_SAMPLE : POSOFFSET_NONE;
1599 ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
1600 ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
1601 ps._32PixelDispatchEnable = wm_prog_data->dispatch_32;
1602
1603 // XXX: Disable SIMD32 with 16x MSAA
1604
1605 ps.DispatchGRFStartRegisterForConstantSetupData0 =
1606 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 0);
1607 ps.DispatchGRFStartRegisterForConstantSetupData1 =
1608 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 1);
1609 ps.DispatchGRFStartRegisterForConstantSetupData2 =
1610 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 2);
1611
1612 ps.KernelStartPointer0 =
1613 shader->prog_offset + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 0);
1614 ps.KernelStartPointer1 =
1615 shader->prog_offset + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 1);
1616 ps.KernelStartPointer2 =
1617 shader->prog_offset + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 2);
1618 }
1619
1620 iris_pack_command(GENX(3DSTATE_PS_EXTRA), psx_state, psx) {
1621 psx.PixelShaderValid = true;
1622 psx.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode;
1623 psx.PixelShaderKillsPixel = wm_prog_data->uses_kill;
1624 psx.AttributeEnable = wm_prog_data->num_varying_inputs != 0;
1625 psx.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth;
1626 psx.PixelShaderUsesSourceW = wm_prog_data->uses_src_w;
1627 psx.PixelShaderIsPerSample = wm_prog_data->persample_dispatch;
1628
1629 if (wm_prog_data->uses_sample_mask) {
1630 /* TODO: conservative rasterization */
1631 if (wm_prog_data->post_depth_coverage)
1632 psx.InputCoverageMaskState = ICMS_DEPTH_COVERAGE;
1633 else
1634 psx.InputCoverageMaskState = ICMS_NORMAL;
1635 }
1636
1637 psx.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask;
1638 psx.PixelShaderPullsBary = wm_prog_data->pulls_bary;
1639 psx.PixelShaderComputesStencil = wm_prog_data->computed_stencil;
1640
1641 // XXX: UAV bit
1642 }
1643 }
1644
1645 static unsigned
1646 iris_derived_program_state_size(enum iris_program_cache_id cache_id)
1647 {
1648 assert(cache_id <= IRIS_CACHE_CS);
1649
1650 static const unsigned dwords[] = {
1651 [IRIS_CACHE_VS] = GENX(3DSTATE_VS_length),
1652 [IRIS_CACHE_TCS] = GENX(3DSTATE_HS_length),
1653 [IRIS_CACHE_TES] = GENX(3DSTATE_TE_length) + GENX(3DSTATE_DS_length),
1654 [IRIS_CACHE_GS] = GENX(3DSTATE_GS_length),
1655 [IRIS_CACHE_FS] =
1656 GENX(3DSTATE_PS_length) + GENX(3DSTATE_PS_EXTRA_length),
1657 [IRIS_CACHE_CS] = 0,
1658 [IRIS_CACHE_BLORP_BLIT] = 0,
1659 };
1660
1661 return sizeof(uint32_t) * dwords[cache_id];
1662 }
1663
1664 static void
1665 iris_set_derived_program_state(const struct gen_device_info *devinfo,
1666 enum iris_program_cache_id cache_id,
1667 struct iris_compiled_shader *shader)
1668 {
1669 switch (cache_id) {
1670 case IRIS_CACHE_VS:
1671 iris_set_vs_state(devinfo, shader);
1672 break;
1673 case IRIS_CACHE_TCS:
1674 iris_set_tcs_state(devinfo, shader);
1675 break;
1676 case IRIS_CACHE_TES:
1677 iris_set_tes_state(devinfo, shader);
1678 break;
1679 case IRIS_CACHE_GS:
1680 iris_set_gs_state(devinfo, shader);
1681 break;
1682 case IRIS_CACHE_FS:
1683 iris_set_fs_state(devinfo, shader);
1684 break;
1685 case IRIS_CACHE_CS:
1686 break;
1687 default:
1688 break;
1689 }
1690 }
1691
1692 static void
1693 iris_upload_render_state(struct iris_context *ice,
1694 struct iris_batch *batch,
1695 const struct pipe_draw_info *draw)
1696 {
1697 const uint64_t dirty = ice->state.dirty;
1698
1699 struct brw_wm_prog_data *wm_prog_data = (void *)
1700 ice->shaders.prog[MESA_SHADER_FRAGMENT]->prog_data;
1701
1702 if (dirty & IRIS_DIRTY_CC_VIEWPORT) {
1703 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1704 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), ptr) {
1705 ptr.CCViewportPointer =
1706 iris_emit_state(batch, cso->cc_vp, sizeof(cso->cc_vp), 32);
1707 }
1708 }
1709
1710 if (dirty & IRIS_DIRTY_SF_CL_VIEWPORT) {
1711 struct iris_viewport_state *cso = ice->state.cso_vp;
1712 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), ptr) {
1713 ptr.SFClipViewportPointer =
1714 iris_emit_state(batch, cso->sf_cl_vp, sizeof(cso->sf_cl_vp), 64);
1715 }
1716 }
1717
1718 /* XXX: L3 State */
1719
1720 if (dirty & IRIS_DIRTY_URB) {
1721 /* XXX: URB */
1722 }
1723
1724 if (dirty & IRIS_DIRTY_BLEND_STATE) {
1725 struct iris_blend_state *cso = ice->state.cso_blend;
1726 // XXX: 3DSTATE_BLEND_STATE_POINTERS - BLEND_STATE
1727 // -> from iris_blend_state (most) + iris_depth_stencil_alpha_state
1728 // (alpha test function/enable) + has writeable RT from ???????
1729 }
1730
1731 if (dirty & IRIS_DIRTY_COLOR_CALC_STATE) {
1732 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1733 uint32_t cc_offset;
1734 void *cc_map =
1735 iris_alloc_state(batch,
1736 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length),
1737 64, &cc_offset);
1738 iris_pack_state(GENX(COLOR_CALC_STATE), cc_map, cc) {
1739 cc.AlphaTestFormat = ALPHATEST_FLOAT32;
1740 cc.AlphaReferenceValueAsFLOAT32 = cso->alpha.ref_value;
1741 cc.BlendConstantColorRed = ice->state.blend_color.color[0];
1742 cc.BlendConstantColorGreen = ice->state.blend_color.color[1];
1743 cc.BlendConstantColorBlue = ice->state.blend_color.color[2];
1744 cc.BlendConstantColorAlpha = ice->state.blend_color.color[3];
1745 }
1746 iris_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
1747 ptr.ColorCalcStatePointer = cc_offset;
1748 ptr.ColorCalcStatePointerValid = true;
1749 }
1750 }
1751
1752 // XXX: 3DSTATE_CONSTANT_XS
1753 // XXX: 3DSTATE_BINDING_TABLE_POINTERS_XS
1754
1755 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
1756 if (!(dirty & (IRIS_DIRTY_SAMPLER_STATES_VS << stage)))
1757 continue;
1758
1759 // XXX: get sampler count from shader; don't emit them all...
1760 const int count = IRIS_MAX_TEXTURE_SAMPLERS;
1761
1762 uint32_t offset;
1763 uint32_t *map = iris_alloc_state(batch,
1764 count * 4 * GENX(SAMPLER_STATE_length),
1765 32, &offset);
1766
1767 for (int i = 0; i < count; i++) {
1768 // XXX: when we have a correct count, these better be bound
1769 if (!ice->state.samplers[stage][i])
1770 continue;
1771 memcpy(map, ice->state.samplers[stage][i]->sampler_state,
1772 4 * GENX(SAMPLER_STATE_length));
1773 map += GENX(SAMPLER_STATE_length);
1774 }
1775
1776 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ptr) {
1777 ptr._3DCommandSubOpcode = 43 + stage;
1778 ptr.PointertoVSSamplerState = offset;
1779 }
1780 }
1781
1782 if (dirty & IRIS_DIRTY_MULTISAMPLE) {
1783 iris_emit_cmd(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
1784 ms.PixelLocation =
1785 ice->state.cso_rast->half_pixel_center ? CENTER : UL_CORNER;
1786 if (ice->state.framebuffer.samples > 0)
1787 ms.NumberofMultisamples = ffs(ice->state.framebuffer.samples) - 1;
1788 }
1789 }
1790
1791 if (dirty & IRIS_DIRTY_SAMPLE_MASK) {
1792 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_MASK), ms) {
1793 ms.SampleMask = ice->state.sample_mask;
1794 }
1795 }
1796
1797 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
1798 if (!(dirty & (IRIS_DIRTY_VS << stage)))
1799 continue;
1800
1801 if (ice->shaders.prog[stage]) {
1802 iris_batch_emit(batch, ice->shaders.prog[stage]->derived_data,
1803 iris_derived_program_state_size(stage));
1804 } else {
1805 if (stage == MESA_SHADER_TESS_EVAL) {
1806 iris_emit_cmd(batch, GENX(3DSTATE_HS), hs);
1807 iris_emit_cmd(batch, GENX(3DSTATE_TE), te);
1808 iris_emit_cmd(batch, GENX(3DSTATE_DS), ds);
1809 } else if (stage == MESA_SHADER_GEOMETRY) {
1810 iris_emit_cmd(batch, GENX(3DSTATE_GS), gs);
1811 }
1812 }
1813 }
1814
1815 // XXX: SOL and so on
1816
1817 if (dirty & IRIS_DIRTY_CLIP) {
1818 struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
1819 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
1820
1821 uint32_t dynamic_clip[GENX(3DSTATE_CLIP_length)];
1822 iris_pack_command(GENX(3DSTATE_CLIP), &dynamic_clip, cl) {
1823 if (wm_prog_data->barycentric_interp_modes &
1824 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS)
1825 cl.NonPerspectiveBarycentricEnable = true;
1826
1827 cl.ForceZeroRTAIndexEnable = cso_fb->layers == 0;
1828 }
1829 iris_emit_merge(batch, cso_rast->clip, dynamic_clip,
1830 ARRAY_SIZE(cso_rast->clip));
1831 }
1832
1833 if (dirty & IRIS_DIRTY_RASTER) {
1834 struct iris_rasterizer_state *cso = ice->state.cso_rast;
1835 iris_batch_emit(batch, cso->raster, sizeof(cso->raster));
1836 iris_batch_emit(batch, cso->sf, sizeof(cso->sf));
1837
1838 }
1839
1840 if (dirty & (IRIS_DIRTY_RASTER | IRIS_DIRTY_FS)) {
1841 struct iris_rasterizer_state *cso = ice->state.cso_rast;
1842 uint32_t dynamic_wm[GENX(3DSTATE_WM_length)];
1843
1844 iris_pack_command(GENX(3DSTATE_WM), &dynamic_wm, wm) {
1845 wm.BarycentricInterpolationMode =
1846 wm_prog_data->barycentric_interp_modes;
1847
1848 if (wm_prog_data->early_fragment_tests)
1849 wm.EarlyDepthStencilControl = EDSC_PREPS;
1850 else if (wm_prog_data->has_side_effects)
1851 wm.EarlyDepthStencilControl = EDSC_PSEXEC;
1852 }
1853 iris_emit_merge(batch, cso->wm, dynamic_wm, ARRAY_SIZE(cso->wm));
1854 }
1855
1856 // XXX: SBE, SBE_SWIZ
1857
1858 if (dirty & IRIS_DIRTY_PS_BLEND) {
1859 struct iris_blend_state *cso = ice->state.cso_blend;
1860 iris_batch_emit(batch, cso->ps_blend, sizeof(cso->ps_blend));
1861 }
1862
1863 if (dirty & IRIS_DIRTY_WM_DEPTH_STENCIL) {
1864 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1865 struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref;
1866
1867 uint32_t stencil_refs[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
1868 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), &stencil_refs, wmds) {
1869 wmds.StencilReferenceValue = p_stencil_refs->ref_value[0];
1870 wmds.BackfaceStencilReferenceValue = p_stencil_refs->ref_value[1];
1871 }
1872 iris_emit_merge(batch, cso->wmds, stencil_refs, ARRAY_SIZE(cso->wmds));
1873 }
1874
1875 if (dirty & IRIS_DIRTY_SCISSOR) {
1876 uint32_t scissor_offset =
1877 iris_emit_state(batch, ice->state.scissors,
1878 sizeof(struct pipe_scissor_state) *
1879 ice->state.num_scissors, 32);
1880
1881 iris_emit_cmd(batch, GENX(3DSTATE_SCISSOR_STATE_POINTERS), ptr) {
1882 ptr.ScissorRectPointer = scissor_offset;
1883 }
1884 }
1885
1886 // XXX: 3DSTATE_DEPTH_BUFFER and friends
1887
1888 if (dirty & IRIS_DIRTY_POLYGON_STIPPLE) {
1889 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
1890 for (int i = 0; i < 32; i++) {
1891 poly.PatternRow[i] = ice->state.poly_stipple.stipple[i];
1892 }
1893 }
1894 }
1895
1896 if (dirty & IRIS_DIRTY_LINE_STIPPLE) {
1897 struct iris_rasterizer_state *cso = ice->state.cso_rast;
1898 iris_batch_emit(batch, cso->line_stipple, sizeof(cso->line_stipple));
1899 }
1900
1901 if (1) {
1902 iris_emit_cmd(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
1903 topo.PrimitiveTopologyType =
1904 translate_prim_type(draw->mode, draw->vertices_per_patch);
1905 }
1906 }
1907
1908 if (draw->index_size > 0) {
1909 struct iris_resource *res = (struct iris_resource *)draw->index.resource;
1910
1911 assert(!draw->has_user_indices);
1912
1913 iris_emit_cmd(batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
1914 ib.IndexFormat = draw->index_size;
1915 ib.MOCS = MOCS_WB;
1916 ib.BufferSize = res->bo->size;
1917 ib.BufferStartingAddress = ro_bo(res->bo, 0);
1918 }
1919 }
1920
1921 if (dirty & IRIS_DIRTY_VERTEX_BUFFERS) {
1922 struct iris_vertex_buffer_state *cso = ice->state.cso_vertex_buffers;
1923
1924 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_length) == 4);
1925 STATIC_ASSERT((GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) % 32) == 0);
1926
1927 uint64_t *addr = batch->cmdbuf.map_next + sizeof(uint32_t) *
1928 (GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) / 32);
1929 uint32_t *delta = cso->vertex_buffers +
1930 (1 + GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) / 32);
1931
1932 iris_batch_emit(batch, cso->vertex_buffers,
1933 sizeof(uint32_t) * (1 + 4 * cso->num_buffers));
1934
1935 for (unsigned i = 0; i < cso->num_buffers; i++) {
1936 *addr = iris_batch_reloc(batch, (void *) addr - batch->cmdbuf.map,
1937 cso->bos[i].bo, cso->bos[i].offset +
1938 *delta, cso->bos[i].reloc_flags);
1939 addr = (void *) addr + 16;
1940 delta = (void *) delta + 16;
1941 }
1942 }
1943
1944 if (dirty & IRIS_DIRTY_VERTEX_ELEMENTS) {
1945 struct iris_vertex_element_state *cso = ice->state.cso_vertex_elements;
1946 iris_batch_emit(batch, cso->vertex_elements, sizeof(uint32_t) *
1947 (1 + cso->count * GENX(VERTEX_ELEMENT_STATE_length)));
1948 for (int i = 0; i < cso->count; i++) {
1949 iris_batch_emit(batch, cso->vf_instancing[i], sizeof(uint32_t) *
1950 (cso->count * GENX(3DSTATE_VF_INSTANCING_length)));
1951 }
1952 for (int i = 0; i < cso->count; i++) {
1953 /* TODO: vertexid, instanceid support */
1954 iris_emit_cmd(batch, GENX(3DSTATE_VF_SGVS), sgvs);
1955 }
1956 }
1957
1958 if (1) {
1959 iris_emit_cmd(batch, GENX(3DSTATE_VF), vf) {
1960 if (draw->primitive_restart) {
1961 vf.IndexedDrawCutIndexEnable = true;
1962 vf.CutIndex = draw->restart_index;
1963 }
1964 }
1965 }
1966
1967 // XXX: Gen8 - PMA fix
1968
1969 assert(!draw->indirect); // XXX: indirect support
1970
1971 iris_emit_cmd(batch, GENX(3DPRIMITIVE), prim) {
1972 prim.StartInstanceLocation = draw->start_instance;
1973 prim.InstanceCount = draw->instance_count;
1974 prim.VertexCountPerInstance = draw->count;
1975 prim.VertexAccessType = draw->index_size > 0 ? RANDOM : SEQUENTIAL;
1976
1977 // XXX: this is probably bonkers.
1978 prim.StartVertexLocation = draw->start;
1979
1980 if (draw->index_size) {
1981 prim.BaseVertexLocation += draw->index_bias;
1982 } else {
1983 prim.StartVertexLocation += draw->index_bias;
1984 }
1985
1986 //prim.BaseVertexLocation = ...;
1987 }
1988 #if 0
1989 l3 configuration
1990
1991 3DSTATE_URB_*
1992 -> TODO
1993
1994 3DSTATE_CONSTANT_* - push constants
1995 -> TODO
1996
1997 Surfaces:
1998 - pull constants
1999 - ubos/ssbos/abos
2000 - images
2001 - textures
2002 - render targets - write and read
2003 3DSTATE_BINDING_TABLE_POINTERS_*
2004 -> TODO
2005
2006 3DSTATE_STREAMOUT
2007 3DSTATE_SO_BUFFER
2008 3DSTATE_SO_DECL_LIST
2009
2010 3DSTATE_SBE
2011 -> iris_raster_state (point sprite texture coordinate origin)
2012 -> bunch of shader state...
2013 3DSTATE_SBE_SWIZ
2014 -> FS state
2015
2016 3DSTATE_DEPTH_BUFFER
2017 3DSTATE_HIER_DEPTH_BUFFER
2018 3DSTATE_STENCIL_BUFFER
2019 3DSTATE_CLEAR_PARAMS
2020 -> iris_framebuffer_state?
2021 #endif
2022 }
2023
2024
2025
2026 static void
2027 iris_destroy_state(struct iris_context *ice)
2028 {
2029 // XXX: unreference resources/surfaces.
2030 for (unsigned i = 0; i < ice->state.framebuffer.nr_cbufs; i++) {
2031 pipe_surface_reference(&ice->state.framebuffer.cbufs[i], NULL);
2032 }
2033 pipe_surface_reference(&ice->state.framebuffer.zsbuf, NULL);
2034 }
2035
2036 void
2037 genX(init_state)(struct iris_context *ice)
2038 {
2039 struct pipe_context *ctx = &ice->ctx;
2040
2041 ctx->create_blend_state = iris_create_blend_state;
2042 ctx->create_depth_stencil_alpha_state = iris_create_zsa_state;
2043 ctx->create_rasterizer_state = iris_create_rasterizer_state;
2044 ctx->create_sampler_state = iris_create_sampler_state;
2045 ctx->create_sampler_view = iris_create_sampler_view;
2046 ctx->create_surface = iris_create_surface;
2047 ctx->create_vertex_elements_state = iris_create_vertex_elements;
2048 ctx->create_compute_state = iris_create_compute_state;
2049 ctx->bind_blend_state = iris_bind_blend_state;
2050 ctx->bind_depth_stencil_alpha_state = iris_bind_zsa_state;
2051 ctx->bind_sampler_states = iris_bind_sampler_states;
2052 ctx->bind_rasterizer_state = iris_bind_rasterizer_state;
2053 ctx->bind_vertex_elements_state = iris_bind_vertex_elements_state;
2054 ctx->bind_compute_state = iris_bind_compute_state;
2055 ctx->delete_blend_state = iris_delete_state;
2056 ctx->delete_depth_stencil_alpha_state = iris_delete_state;
2057 ctx->delete_fs_state = iris_delete_state;
2058 ctx->delete_rasterizer_state = iris_delete_state;
2059 ctx->delete_sampler_state = iris_delete_state;
2060 ctx->delete_vertex_elements_state = iris_delete_state;
2061 ctx->delete_compute_state = iris_delete_state;
2062 ctx->delete_tcs_state = iris_delete_state;
2063 ctx->delete_tes_state = iris_delete_state;
2064 ctx->delete_gs_state = iris_delete_state;
2065 ctx->delete_vs_state = iris_delete_state;
2066 ctx->set_blend_color = iris_set_blend_color;
2067 ctx->set_clip_state = iris_set_clip_state;
2068 ctx->set_constant_buffer = iris_set_constant_buffer;
2069 ctx->set_sampler_views = iris_set_sampler_views;
2070 ctx->set_framebuffer_state = iris_set_framebuffer_state;
2071 ctx->set_polygon_stipple = iris_set_polygon_stipple;
2072 ctx->set_sample_mask = iris_set_sample_mask;
2073 ctx->set_scissor_states = iris_set_scissor_states;
2074 ctx->set_stencil_ref = iris_set_stencil_ref;
2075 ctx->set_vertex_buffers = iris_set_vertex_buffers;
2076 ctx->set_viewport_states = iris_set_viewport_states;
2077 ctx->sampler_view_destroy = iris_sampler_view_destroy;
2078 ctx->surface_destroy = iris_surface_destroy;
2079 ctx->draw_vbo = iris_draw_vbo;
2080 ctx->launch_grid = iris_launch_grid;
2081 ctx->create_stream_output_target = iris_create_stream_output_target;
2082 ctx->stream_output_target_destroy = iris_stream_output_target_destroy;
2083 ctx->set_stream_output_targets = iris_set_stream_output_targets;
2084
2085 ice->state.destroy_state = iris_destroy_state;
2086 ice->state.init_render_context = iris_init_render_context;
2087 ice->state.upload_render_state = iris_upload_render_state;
2088 ice->state.derived_program_state_size = iris_derived_program_state_size;
2089 ice->state.set_derived_program_state = iris_set_derived_program_state;
2090 ice->state.populate_vs_key = iris_populate_vs_key;
2091 ice->state.populate_tcs_key = iris_populate_tcs_key;
2092 ice->state.populate_tes_key = iris_populate_tes_key;
2093 ice->state.populate_gs_key = iris_populate_gs_key;
2094 ice->state.populate_fs_key = iris_populate_fs_key;
2095
2096
2097 ice->state.dirty = ~0ull;
2098 }