2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "intel/common/gen_sample_positions.h"
43 #include "iris_batch.h"
44 #include "iris_context.h"
45 #include "iris_pipe.h"
46 #include "iris_resource.h"
48 #define __gen_address_type unsigned
49 #define __gen_user_data void
52 __gen_combine_address(void *user_data
, void *location
,
53 unsigned address
, uint32_t delta
)
58 #define __genxml_cmd_length(cmd) cmd ## _length
59 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
60 #define __genxml_cmd_header(cmd) cmd ## _header
61 #define __genxml_cmd_pack(cmd) cmd ## _pack
63 #define iris_pack_command(cmd, dst, name) \
64 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
65 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
66 ({ __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name); \
67 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __genxml_cmd_length(cmd) * 4)); \
71 #define iris_pack_state(cmd, dst, name) \
72 for (struct cmd name = {}, \
73 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
74 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
77 #define iris_emit_cmd(batch, cmd, name) \
78 iris_require_command_space(batch, 4 * __genxml_cmd_length(cmd)); \
79 iris_pack_command(cmd, batch->cmdbuf.map_next, name)
81 #define iris_emit_merge(batch, dwords0, dwords1) \
83 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
85 iris_require_command_space(batch, ARRAY_SIZE(dwords0)); \
86 uint32_t *dw = batch->cmdbuf.map_next; \
87 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
88 dw[i] = (dwords0)[i] | (dwords1)[i]; \
89 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4)); \
92 #include "genxml/genX_pack.h"
93 #include "genxml/gen_macros.h"
95 #define MOCS_WB (2 << 1)
97 UNUSED
static void pipe_asserts()
99 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
101 /* pipe_logicop happens to match the hardware. */
102 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
103 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
104 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
105 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
106 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
107 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
108 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
109 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
110 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
111 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
112 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
113 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
114 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
115 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
116 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
117 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
119 /* pipe_blend_func happens to match the hardware. */
120 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
121 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
122 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
123 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
124 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
125 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
126 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
127 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
128 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
129 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
130 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
131 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
132 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
133 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
134 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
135 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
136 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
137 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
138 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
140 /* pipe_blend_func happens to match the hardware. */
141 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
142 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
143 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
144 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
145 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
147 /* pipe_stencil_op happens to match the hardware. */
148 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
149 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
150 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
151 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
152 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
153 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
154 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
155 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
160 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
162 assert(prim
== PIPE_PRIM_PATCHES
|| verts_per_patch
== 0);
164 static const unsigned map
[] = {
165 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
166 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
167 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
168 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
169 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
170 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
171 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
172 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
173 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
174 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
175 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
176 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
177 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
178 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
179 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
182 return map
[prim
] + verts_per_patch
;
186 translate_compare_func(enum pipe_compare_func pipe_func
)
188 static const unsigned map
[] = {
189 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
190 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
191 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
192 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
193 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
194 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
195 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
196 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
198 return map
[pipe_func
];
202 translate_shadow_func(enum pipe_compare_func pipe_func
)
204 /* Gallium specifies the result of shadow comparisons as:
206 * 1 if ref <op> texel,
211 * 0 if texel <op> ref,
214 * So we need to flip the operator and also negate.
216 static const unsigned map
[] = {
217 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
218 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
219 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
220 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
221 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
222 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
223 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
224 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
226 return map
[pipe_func
];
230 translate_cull_mode(unsigned pipe_face
)
232 static const unsigned map
[4] = {
233 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
234 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
235 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
236 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
238 return map
[pipe_face
];
242 translate_fill_mode(unsigned pipe_polymode
)
244 static const unsigned map
[4] = {
245 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
246 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
247 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
248 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
250 return map
[pipe_polymode
];
254 iris_upload_initial_gpu_state(struct iris_context
*ice
,
255 struct iris_batch
*batch
)
257 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
258 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
259 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
261 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
262 GEN_SAMPLE_POS_1X(pat
._1xSample
);
263 GEN_SAMPLE_POS_2X(pat
._2xSample
);
264 GEN_SAMPLE_POS_4X(pat
._4xSample
);
265 GEN_SAMPLE_POS_8X(pat
._8xSample
);
266 GEN_SAMPLE_POS_16X(pat
._16xSample
);
268 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
269 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
270 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
271 /* XXX: may need to set an offset for origin-UL framebuffers */
272 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
274 /* Just assign a static partitioning. */
275 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
276 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
277 alloc
._3DCommandSubOpcode
= 18 + i
;
278 alloc
.ConstantBufferOffset
= 6 * i
;
279 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
285 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
290 iris_set_blend_color(struct pipe_context
*ctx
,
291 const struct pipe_blend_color
*state
)
293 struct iris_context
*ice
= (struct iris_context
*) ctx
;
295 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
296 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
299 struct iris_blend_state
{
300 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
301 uint32_t blend_state
[GENX(BLEND_STATE_length
)];
302 uint32_t blend_entries
[BRW_MAX_DRAW_BUFFERS
*
303 GENX(BLEND_STATE_ENTRY_length
)];
307 iris_create_blend_state(struct pipe_context
*ctx
,
308 const struct pipe_blend_state
*state
)
310 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
312 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
313 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
314 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
315 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
316 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
317 bs
.ColorDitherEnable
= state
->dither
;
318 //bs.AlphaTestEnable = <comes from alpha state> :(
319 //bs.AlphaTestFunction = <comes from alpha state> :(
322 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
323 //pb.HasWriteableRT = <comes from somewhere> :(
324 //pb.AlphaTestEnable = <comes from alpha state> :(
325 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
326 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
328 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
330 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
331 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
332 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
333 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
336 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
337 iris_pack_state(GENX(BLEND_STATE_ENTRY
), &cso
->blend_entries
[i
], be
) {
338 be
.LogicOpEnable
= state
->logicop_enable
;
339 be
.LogicOpFunction
= state
->logicop_func
;
341 be
.PreBlendSourceOnlyClampEnable
= false;
342 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
343 be
.PreBlendColorClampEnable
= true;
344 be
.PostBlendColorClampEnable
= true;
346 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
348 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
349 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
350 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
351 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
352 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
353 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
355 be
.WriteDisableRed
= state
->rt
[i
].colormask
& PIPE_MASK_R
;
356 be
.WriteDisableGreen
= state
->rt
[i
].colormask
& PIPE_MASK_G
;
357 be
.WriteDisableBlue
= state
->rt
[i
].colormask
& PIPE_MASK_B
;
358 be
.WriteDisableAlpha
= state
->rt
[i
].colormask
& PIPE_MASK_A
;
366 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
368 struct iris_context
*ice
= (struct iris_context
*) ctx
;
369 ice
->state
.cso_blend
= state
;
370 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
371 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
374 struct iris_depth_stencil_alpha_state
{
375 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
376 uint32_t cc_vp
[GENX(CC_VIEWPORT_length
)];
378 struct pipe_alpha_state alpha
; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
382 iris_create_zsa_state(struct pipe_context
*ctx
,
383 const struct pipe_depth_stencil_alpha_state
*state
)
385 struct iris_depth_stencil_alpha_state
*cso
=
386 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
388 cso
->alpha
= state
->alpha
;
390 bool two_sided_stencil
= state
->stencil
[1].enabled
;
392 /* The state tracker needs to optimize away EQUAL writes for us. */
393 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
395 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
396 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
397 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
398 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
399 wmds
.StencilTestFunction
=
400 translate_compare_func(state
->stencil
[0].func
);
401 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
402 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
403 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
404 wmds
.BackfaceStencilTestFunction
=
405 translate_compare_func(state
->stencil
[1].func
);
406 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
407 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
408 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
409 wmds
.StencilBufferWriteEnable
=
410 state
->stencil
[0].writemask
!= 0 ||
411 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
412 wmds
.DepthTestEnable
= state
->depth
.enabled
;
413 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
414 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
415 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
416 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
417 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
418 /* wmds.[Backface]StencilReferenceValue are merged later */
421 iris_pack_state(GENX(CC_VIEWPORT
), cso
->cc_vp
, ccvp
) {
422 ccvp
.MinimumDepth
= state
->depth
.bounds_min
;
423 ccvp
.MaximumDepth
= state
->depth
.bounds_max
;
430 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
432 struct iris_context
*ice
= (struct iris_context
*) ctx
;
433 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
434 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
437 if (!old_cso
|| old_cso
->alpha
.ref_value
!= new_cso
->alpha
.ref_value
) {
438 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
442 ice
->state
.cso_zsa
= new_cso
;
443 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
444 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
447 struct iris_rasterizer_state
{
448 uint32_t sf
[GENX(3DSTATE_SF_length
)];
449 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
450 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
451 uint32_t wm
[GENX(3DSTATE_WM_length
)];
452 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
454 bool flatshade
; /* for shader state */
455 bool light_twoside
; /* for shader state */
456 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
457 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
458 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
462 iris_create_rasterizer_state(struct pipe_context
*ctx
,
463 const struct pipe_rasterizer_state
*state
)
465 struct iris_rasterizer_state
*cso
=
466 malloc(sizeof(struct iris_rasterizer_state
));
469 sprite_coord_mode
-> SBE PointSpriteTextureCoordinateOrigin
470 sprite_coord_enable
-> SBE PointSpriteTextureCoordinateEnable
471 point_quad_rasterization
-> SBE
?
476 force_persample_interp
- ?
479 offset_units_unscaled
- cap
not exposed
483 cso
->flatshade
= state
->flatshade
;
484 cso
->light_twoside
= state
->light_twoside
;
485 cso
->rasterizer_discard
= state
->rasterizer_discard
;
486 cso
->half_pixel_center
= state
->half_pixel_center
;
488 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
489 sf
.StatisticsEnable
= true;
490 sf
.ViewportTransformEnable
= true;
491 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
492 sf
.LineEndCapAntialiasingRegionWidth
=
493 state
->line_smooth
? _10pixels
: _05pixels
;
494 sf
.LastPixelEnable
= state
->line_last_pixel
;
495 sf
.LineWidth
= state
->line_width
;
496 sf
.SmoothPointEnable
= state
->point_smooth
;
497 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
498 sf
.PointWidth
= state
->point_size
;
500 if (state
->flatshade_first
) {
501 sf
.TriangleStripListProvokingVertexSelect
= 2;
502 sf
.TriangleFanProvokingVertexSelect
= 2;
503 sf
.LineStripListProvokingVertexSelect
= 1;
505 sf
.TriangleFanProvokingVertexSelect
= 1;
510 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
511 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
512 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
513 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
514 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
515 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
516 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
517 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
518 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
519 rr
.GlobalDepthOffsetConstant
= state
->offset_units
;
520 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
521 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
522 rr
.SmoothPointEnable
= state
->point_smooth
;
523 rr
.AntialiasingEnable
= state
->line_smooth
;
524 rr
.ScissorRectangleEnable
= state
->scissor
;
525 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
526 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
527 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
530 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
531 cl
.StatisticsEnable
= true;
532 cl
.EarlyCullEnable
= true;
533 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
534 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
535 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
536 cl
.GuardbandClipTestEnable
= true;
537 cl
.ClipMode
= CLIPMODE_NORMAL
;
538 cl
.ClipEnable
= true;
539 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
540 cl
.MinimumPointWidth
= 0.125;
541 cl
.MaximumPointWidth
= 255.875;
542 //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
543 //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
545 if (state
->flatshade_first
) {
546 cl
.TriangleStripListProvokingVertexSelect
= 2;
547 cl
.TriangleFanProvokingVertexSelect
= 2;
548 cl
.LineStripListProvokingVertexSelect
= 1;
550 cl
.TriangleFanProvokingVertexSelect
= 1;
554 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
555 wm
.LineAntialiasingRegionWidth
= _10pixels
;
556 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
557 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
558 wm
.StatisticsEnable
= true;
559 wm
.LineStippleEnable
= state
->line_stipple_enable
;
560 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
561 // wm.BarycentricInterpolationMode = <comes from FS program> :(
562 // wm.EarlyDepthStencilControl = <comes from FS program> :(
565 /* Remap from 0..255 back to 1..256 */
566 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
568 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
569 line
.LineStipplePattern
= state
->line_stipple_pattern
;
570 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
571 line
.LineStippleRepeatCount
= line_stipple_factor
;
578 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
580 struct iris_context
*ice
= (struct iris_context
*) ctx
;
581 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
582 struct iris_rasterizer_state
*new_cso
= state
;
585 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
586 if (!old_cso
|| memcmp(old_cso
->line_stipple
, new_cso
->line_stipple
,
587 sizeof(old_cso
->line_stipple
)) != 0) {
588 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
592 old_cso
->half_pixel_center
!= new_cso
->half_pixel_center
) {
593 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
597 ice
->state
.cso_rast
= new_cso
;
598 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
602 translate_wrap(unsigned pipe_wrap
)
604 static const unsigned map
[] = {
605 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
606 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
607 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
608 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
609 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
610 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
611 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1, // XXX: ???
612 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1, // XXX: ???
614 return map
[pipe_wrap
];
618 * Return true if the given wrap mode requires the border color to exist.
621 wrap_mode_needs_border_color(unsigned wrap_mode
)
623 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
627 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
629 static const unsigned map
[] = {
630 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
631 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
632 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
634 return map
[pipe_mip
];
637 struct iris_sampler_state
{
638 struct pipe_sampler_state base
;
640 bool needs_border_color
;
642 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
646 iris_create_sampler_state(struct pipe_context
*pctx
,
647 const struct pipe_sampler_state
*state
)
649 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
654 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
655 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
657 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
658 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
659 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
661 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
662 wrap_mode_needs_border_color(wrap_t
) ||
663 wrap_mode_needs_border_color(wrap_r
);
665 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
666 samp
.TCXAddressControlMode
= wrap_s
;
667 samp
.TCYAddressControlMode
= wrap_t
;
668 samp
.TCZAddressControlMode
= wrap_r
;
669 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
670 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
671 samp
.MinModeFilter
= state
->min_img_filter
;
672 samp
.MagModeFilter
= state
->mag_img_filter
;
673 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
674 samp
.MaximumAnisotropy
= RATIO21
;
676 if (state
->max_anisotropy
>= 2) {
677 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
678 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
679 samp
.AnisotropicAlgorithm
= EWAApproximation
;
682 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
683 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
685 samp
.MaximumAnisotropy
=
686 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
689 /* Set address rounding bits if not using nearest filtering. */
690 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
691 samp
.UAddressMinFilterRoundingEnable
= true;
692 samp
.VAddressMinFilterRoundingEnable
= true;
693 samp
.RAddressMinFilterRoundingEnable
= true;
696 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
697 samp
.UAddressMagFilterRoundingEnable
= true;
698 samp
.VAddressMagFilterRoundingEnable
= true;
699 samp
.RAddressMagFilterRoundingEnable
= true;
702 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
703 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
705 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
707 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
708 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
709 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
710 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
712 //samp.BorderColorPointer = <<comes from elsewhere>>
719 iris_bind_sampler_states(struct pipe_context
*ctx
,
720 enum pipe_shader_type p_stage
,
721 unsigned start
, unsigned count
,
724 struct iris_context
*ice
= (struct iris_context
*) ctx
;
725 gl_shader_stage stage
= stage_from_pipe(p_stage
);
727 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
729 for (int i
= 0; i
< count
; i
++) {
730 ice
->state
.samplers
[stage
][start
+ i
] = states
[i
];
733 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
736 struct iris_sampler_view
{
737 struct pipe_sampler_view pipe
;
738 struct isl_view view
;
739 uint32_t surface_state
[GENX(RENDER_SURFACE_STATE_length
)];
743 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
744 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
746 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
749 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
751 * which is simply adding 4 then modding by 8 (or anding with 7).
753 * We then may need to apply workarounds for textureGather hardware bugs.
755 static enum isl_channel_select
756 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
758 return (swizzle
+ 4) & 7;
761 static struct pipe_sampler_view
*
762 iris_create_sampler_view(struct pipe_context
*ctx
,
763 struct pipe_resource
*tex
,
764 const struct pipe_sampler_view
*tmpl
)
766 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
767 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
768 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
773 /* initialize base object */
775 isv
->pipe
.context
= ctx
;
776 isv
->pipe
.texture
= NULL
;
777 pipe_reference_init(&isv
->pipe
.reference
, 1);
778 pipe_resource_reference(&isv
->pipe
.texture
, tex
);
780 /* XXX: do we need brw_get_texture_swizzle hacks here? */
782 isv
->view
= (struct isl_view
) {
783 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
784 .base_level
= tmpl
->u
.tex
.first_level
,
785 .levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1,
786 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
787 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
788 .swizzle
= (struct isl_swizzle
) {
789 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
790 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
791 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
792 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
794 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
797 isl_surf_fill_state(&screen
->isl_dev
, isv
->surface_state
,
798 .surf
= &itex
->surf
, .view
= &isv
->view
,
802 // .clear_color = clear_color,
807 struct iris_surface
{
808 struct pipe_surface pipe
;
809 struct isl_view view
;
810 uint32_t surface_state
[GENX(RENDER_SURFACE_STATE_length
)];
813 static struct pipe_surface
*
814 iris_create_surface(struct pipe_context
*ctx
,
815 struct pipe_resource
*tex
,
816 const struct pipe_surface
*tmpl
)
818 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
819 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
820 struct pipe_surface
*psurf
= &surf
->pipe
;
821 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
826 pipe_reference_init(&psurf
->reference
, 1);
827 pipe_resource_reference(&psurf
->texture
, tex
);
828 psurf
->context
= ctx
;
829 psurf
->format
= tmpl
->format
;
830 psurf
->width
= tex
->width0
;
831 psurf
->height
= tex
->height0
;
832 psurf
->texture
= tex
;
833 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
834 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
835 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
837 surf
->view
= (struct isl_view
) {
838 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
839 .base_level
= tmpl
->u
.tex
.level
,
841 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
842 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
843 .swizzle
= ISL_SWIZZLE_IDENTITY
,
844 // XXX: DEPTH_BIt, STENCIL_BIT...CUBE_BIT? Other bits?!
845 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
848 isl_surf_fill_state(&screen
->isl_dev
, surf
->surface_state
,
849 .surf
= &itex
->surf
, .view
= &surf
->view
,
853 // .clear_color = clear_color,
859 iris_set_sampler_views(struct pipe_context
*ctx
,
860 enum pipe_shader_type shader
,
861 unsigned start
, unsigned count
,
862 struct pipe_sampler_view
**views
)
867 iris_set_clip_state(struct pipe_context
*ctx
,
868 const struct pipe_clip_state
*state
)
873 iris_set_polygon_stipple(struct pipe_context
*ctx
,
874 const struct pipe_poly_stipple
*state
)
876 struct iris_context
*ice
= (struct iris_context
*) ctx
;
877 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
878 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
882 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
884 struct iris_context
*ice
= (struct iris_context
*) ctx
;
886 ice
->state
.sample_mask
= sample_mask
;
887 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
891 iris_set_scissor_states(struct pipe_context
*ctx
,
893 unsigned num_scissors
,
894 const struct pipe_scissor_state
*state
)
896 struct iris_context
*ice
= (struct iris_context
*) ctx
;
899 ice
->state
.num_scissors
= num_scissors
;
901 for (unsigned i
= start_slot
; i
< start_slot
+ num_scissors
; i
++) {
902 ice
->state
.scissors
[i
] = *state
;
905 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
909 iris_set_stencil_ref(struct pipe_context
*ctx
,
910 const struct pipe_stencil_ref
*state
)
912 struct iris_context
*ice
= (struct iris_context
*) ctx
;
913 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
914 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
918 struct iris_viewport_state
{
919 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
)];
923 extent_from_matrix(const struct pipe_viewport_state
*state
, int axis
)
925 return fabsf(state
->scale
[axis
]) * state
->translate
[axis
];
930 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
931 float m00
, float m11
, float m30
, float m31
,
932 float *xmin
, float *xmax
,
933 float *ymin
, float *ymax
)
935 /* According to the "Vertex X,Y Clamping and Quantization" section of the
936 * Strips and Fans documentation:
938 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
939 * fixed-point "guardband" range supported by the rasterization hardware"
943 * "In almost all circumstances, if an object’s vertices are actually
944 * modified by this clamping (i.e., had X or Y coordinates outside of
945 * the guardband extent the rendered object will not match the intended
946 * result. Therefore software should take steps to ensure that this does
947 * not happen - e.g., by clipping objects such that they do not exceed
948 * these limits after the Drawing Rectangle is applied."
950 * I believe the fundamental restriction is that the rasterizer (in
951 * the SF/WM stages) have a limit on the number of pixels that can be
952 * rasterized. We need to ensure any coordinates beyond the rasterizer
953 * limit are handled by the clipper. So effectively that limit becomes
954 * the clipper's guardband size.
958 * "In addition, in order to be correctly rendered, objects must have a
959 * screenspace bounding box not exceeding 8K in the X or Y direction.
960 * This additional restriction must also be comprehended by software,
961 * i.e., enforced by use of clipping."
963 * This makes no sense. Gen7+ hardware supports 16K render targets,
964 * and you definitely need to be able to draw polygons that fill the
965 * surface. Our assumption is that the rasterizer was limited to 8K
966 * on Sandybridge, which only supports 8K surfaces, and it was actually
967 * increased to 16K on Ivybridge and later.
969 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
971 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
973 if (m00
!= 0 && m11
!= 0) {
974 /* First, we compute the screen-space render area */
975 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
976 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
977 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
978 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
980 /* We want the guardband to be centered on that */
981 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
982 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
983 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
984 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
986 /* Now we need it in native device coordinates */
987 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
988 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
989 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
990 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
992 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
993 * flipped upside-down. X should be fine though.
995 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
998 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
999 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1001 /* The viewport scales to 0, so nothing will be rendered. */
1011 iris_set_viewport_states(struct pipe_context
*ctx
,
1012 unsigned start_slot
,
1013 unsigned num_viewports
,
1014 const struct pipe_viewport_state
*state
)
1016 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1017 struct iris_viewport_state
*cso
=
1018 malloc(sizeof(struct iris_viewport_state
));
1020 for (unsigned i
= start_slot
; i
< start_slot
+ num_viewports
; i
++) {
1021 float x_extent
= extent_from_matrix(&state
[i
], 0);
1022 float y_extent
= extent_from_matrix(&state
[i
], 1);
1024 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), cso
->sf_cl_vp
, vp
) {
1025 vp
.ViewportMatrixElementm00
= state
[i
].scale
[0];
1026 vp
.ViewportMatrixElementm11
= state
[i
].scale
[1];
1027 vp
.ViewportMatrixElementm22
= state
[i
].scale
[2];
1028 vp
.ViewportMatrixElementm30
= state
[i
].translate
[0];
1029 vp
.ViewportMatrixElementm31
= state
[i
].translate
[1];
1030 vp
.ViewportMatrixElementm32
= state
[i
].translate
[2];
1031 /* XXX: in i965 this is computed based on the drawbuffer size,
1032 * but we don't have that here...
1034 vp
.XMinClipGuardband
= -1.0;
1035 vp
.XMaxClipGuardband
= 1.0;
1036 vp
.YMinClipGuardband
= -1.0;
1037 vp
.YMaxClipGuardband
= 1.0;
1038 vp
.XMinViewPort
= -x_extent
;
1039 vp
.XMaxViewPort
= x_extent
;
1040 vp
.YMinViewPort
= -y_extent
;
1041 vp
.YMaxViewPort
= y_extent
;
1045 ice
->state
.cso_vp
= cso
;
1047 ice
->state
.num_viewports
= num_viewports
;
1048 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1051 struct iris_depth_state
1053 uint32_t depth_buffer
[GENX(3DSTATE_DEPTH_BUFFER_length
)];
1054 uint32_t hier_depth_buffer
[GENX(3DSTATE_HIER_DEPTH_BUFFER_length
)];
1055 uint32_t stencil_buffer
[GENX(3DSTATE_STENCIL_BUFFER_length
)];
1059 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1060 const struct pipe_framebuffer_state
*state
)
1062 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1063 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1065 if (cso
->samples
!= state
->samples
) {
1066 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1069 cso
->width
= state
->width
;
1070 cso
->height
= state
->height
;
1071 cso
->layers
= state
->layers
;
1072 cso
->samples
= state
->samples
;
1075 for (i
= 0; i
< state
->nr_cbufs
; i
++)
1076 pipe_surface_reference(&cso
->cbufs
[i
], state
->cbufs
[i
]);
1077 for (; i
< cso
->nr_cbufs
; i
++)
1078 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
1080 cso
->nr_cbufs
= state
->nr_cbufs
;
1082 pipe_surface_reference(&cso
->zsbuf
, state
->zsbuf
);
1084 struct isl_depth_stencil_hiz_emit_info info
= {
1088 // XXX: depth buffers
1092 iris_set_constant_buffer(struct pipe_context
*ctx
,
1093 enum pipe_shader_type shader
, uint index
,
1094 const struct pipe_constant_buffer
*cb
)
1100 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1101 struct pipe_sampler_view
*state
)
1103 pipe_resource_reference(&state
->texture
, NULL
);
1109 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*surface
)
1111 pipe_resource_reference(&surface
->texture
, NULL
);
1116 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1121 struct iris_vertex_buffer_state
{
1122 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
1123 unsigned length
; /* length of 3DSTATE_VERTEX_BUFFERS in DWords */
1127 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1128 unsigned start_slot
, unsigned count
,
1129 const struct pipe_vertex_buffer
*buffers
)
1131 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1132 struct iris_vertex_buffer_state
*cso
=
1133 malloc(sizeof(struct iris_vertex_buffer_state
));
1135 cso
->length
= 4 * count
- 1;
1137 iris_pack_state(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1138 vb
.DWordLength
= cso
->length
;
1141 /* If there are no buffers, do nothing. We can leave the stale
1142 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1143 * elements that point to them, it should be fine.
1148 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1150 for (unsigned i
= 0; i
< count
; i
++) {
1151 assert(!buffers
[i
].is_user_buffer
);
1153 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1154 vb
.VertexBufferIndex
= start_slot
+ i
;
1156 vb
.AddressModifyEnable
= true;
1157 vb
.BufferPitch
= buffers
[i
].stride
;
1158 //vb.BufferStartingAddress = ro_bo(bo, buffers[i].buffer_offset);
1159 //vb.BufferSize = bo->size;
1162 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1165 ice
->state
.cso_vertex_buffers
= cso
;
1166 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1169 struct iris_vertex_element_state
{
1170 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1171 uint32_t vf_instancing
[GENX(3DSTATE_VF_INSTANCING_length
)][33];
1176 iris_create_vertex_elements(struct pipe_context
*ctx
,
1178 const struct pipe_vertex_element
*state
)
1180 struct iris_vertex_element_state
*cso
=
1181 malloc(sizeof(struct iris_vertex_element_state
));
1186 * - create edge flag one
1188 * - if those are necessary, use count + 1/2/3... OR in the length
1190 iris_pack_state(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
);
1192 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1194 for (int i
= 0; i
< count
; i
++) {
1195 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1196 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1198 ve
.SourceElementOffset
= state
[i
].src_offset
;
1199 ve
.SourceElementFormat
=
1200 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1203 iris_pack_state(GENX(3DSTATE_VF_INSTANCING
), cso
->vf_instancing
[i
], vi
) {
1204 vi
.VertexElementIndex
= i
;
1205 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1206 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1209 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1216 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
1218 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1220 ice
->state
.cso_vertex_elements
= state
;
1221 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
1225 iris_create_compute_state(struct pipe_context
*ctx
,
1226 const struct pipe_compute_state
*state
)
1231 static struct pipe_stream_output_target
*
1232 iris_create_stream_output_target(struct pipe_context
*ctx
,
1233 struct pipe_resource
*res
,
1234 unsigned buffer_offset
,
1235 unsigned buffer_size
)
1237 struct pipe_stream_output_target
*t
=
1238 CALLOC_STRUCT(pipe_stream_output_target
);
1242 pipe_reference_init(&t
->reference
, 1);
1243 pipe_resource_reference(&t
->buffer
, res
);
1244 t
->buffer_offset
= buffer_offset
;
1245 t
->buffer_size
= buffer_size
;
1250 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
1251 struct pipe_stream_output_target
*t
)
1253 pipe_resource_reference(&t
->buffer
, NULL
);
1258 iris_set_stream_output_targets(struct pipe_context
*ctx
,
1259 unsigned num_targets
,
1260 struct pipe_stream_output_target
**targets
,
1261 const unsigned *offsets
)
1266 iris_upload_render_state(struct iris_context
*ice
,
1267 struct iris_batch
*batch
,
1268 const struct pipe_draw_info
*draw
)
1270 const uint64_t dirty
= ice
->state
.dirty
;
1272 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
1273 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1274 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
1276 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1277 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
1278 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
1279 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
1281 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
);
1284 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
1285 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1286 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
1287 ptr
.CCViewportPointer
=
1288 iris_emit_state(batch
, cso
->cc_vp
, sizeof(cso
->cc_vp
), 32);
1292 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
1293 struct iris_blend_state
*cso
= ice
->state
.cso_blend
;
1294 iris_batch_emit(batch
, cso
->ps_blend
, sizeof(cso
->ps_blend
));
1297 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
1298 //struct iris_blend_state *cso = ice->state.cso_blend;
1299 // XXX: 3DSTATE_BLEND_STATE_POINTERS - BLEND_STATE
1300 // -> from iris_blend_state (most) + iris_depth_stencil_alpha_state
1301 // (alpha test function/enable) + has writeable RT from ???????
1304 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
1305 struct iris_viewport_state
*cso
= ice
->state
.cso_vp
;
1306 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
1307 ptr
.SFClipViewportPointer
=
1308 iris_emit_state(batch
, cso
->sf_cl_vp
, sizeof(cso
->sf_cl_vp
), 64);
1312 if (dirty
& IRIS_DIRTY_CLIP
) {
1313 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
1315 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
1316 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
1317 //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
1318 //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
1319 // also userclip stuffs...
1321 iris_emit_merge(batch
, cso
->clip
, dynamic_clip
);
1324 if (dirty
& IRIS_DIRTY_RASTER
) {
1325 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
1326 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
1327 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
1330 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
1331 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
1332 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
1335 if (dirty
& IRIS_DIRTY_SCISSOR
) {
1336 uint32_t scissor_offset
=
1337 iris_emit_state(batch
, ice
->state
.scissors
,
1338 sizeof(struct pipe_scissor_state
) *
1339 ice
->state
.num_scissors
, 32);
1341 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
1342 ptr
.ScissorRectPointer
= scissor_offset
;
1346 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
1347 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
1348 for (int i
= 0; i
< 32; i
++) {
1349 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
1354 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
1355 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1358 iris_alloc_state(batch
,
1359 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
1361 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
1362 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
1363 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
1364 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
1365 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
1366 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
1367 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
1369 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
1370 ptr
.ColorCalcStatePointer
= cc_offset
;
1371 ptr
.ColorCalcStatePointerValid
= true;
1375 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
1376 struct iris_vertex_buffer_state
*cso
= ice
->state
.cso_vertex_buffers
;
1378 iris_batch_emit(batch
, cso
->vertex_buffers
,
1379 sizeof(uint32_t) * cso
->length
);
1382 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
1383 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
1384 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
1385 (1 + cso
->count
* GENX(VERTEX_ELEMENT_STATE_length
)));
1386 for (int i
= 0; i
< cso
->count
; i
++) {
1387 iris_batch_emit(batch
, cso
->vf_instancing
[i
],
1388 sizeof(cso
->vf_instancing
[0]));
1390 for (int i
= 0; i
< cso
->count
; i
++) {
1391 /* TODO: vertexid, instanceid support */
1392 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
);
1396 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
1397 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1399 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
1400 if (ice
->state
.framebuffer
.samples
> 0)
1401 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
1405 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
1406 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
1407 ms
.SampleMask
= ice
->state
.sample_mask
;
1411 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
1412 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)))
1415 // XXX: get sampler count from shader; don't emit them all...
1416 const int count
= IRIS_MAX_TEXTURE_SAMPLERS
;
1419 uint32_t *map
= iris_alloc_state(batch
,
1420 count
* 4 * GENX(SAMPLER_STATE_length
),
1423 for (int i
= 0; i
< count
; i
++) {
1424 memcpy(map
, ice
->state
.samplers
[stage
][i
]->sampler_state
,
1425 4 * GENX(SAMPLER_STATE_length
));
1426 map
+= GENX(SAMPLER_STATE_length
);
1429 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
1430 ptr
._3DCommandSubOpcode
= 43 + stage
;
1431 ptr
.PointertoVSSamplerState
= offset
;
1436 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
1437 topo
.PrimitiveTopologyType
=
1438 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
1443 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
1444 vf
.IndexedDrawCutIndexEnable
= draw
->primitive_restart
;
1445 vf
.CutIndex
= draw
->restart_index
;
1449 // draw->index_size > 0
1451 struct iris_resource
*res
= (struct iris_resource
*)draw
->index
.resource
;
1453 assert(!draw
->has_user_indices
);
1455 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
1456 ib
.IndexFormat
= draw
->index_size
;
1458 ib
.BufferSize
= res
->bo
->size
;
1459 // XXX: gah, addresses :( need two different combine address funcs
1460 // ib.BufferStartingAddress = res->bo;
1463 assert(!draw
->indirect
); // XXX: indirect support
1465 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
1466 prim
.StartInstanceLocation
= draw
->start_instance
;
1467 prim
.InstanceCount
= draw
->instance_count
;
1469 // XXX: this is probably bonkers.
1470 prim
.StartVertexLocation
= draw
->start
;
1472 if (draw
->index_size
) {
1473 prim
.BaseVertexLocation
+= draw
->index_bias
;
1475 prim
.StartVertexLocation
+= draw
->index_bias
;
1478 //prim.BaseVertexLocation = ...;
1487 3DSTATE_CONSTANT_
* - push constants
1495 - render targets
- write
and read
1496 3DSTATE_BINDING_TABLE_POINTERS_
*
1508 3DSTATE_SO_DECL_LIST
1511 -> iris_raster_state
+ FS
state (barycentric
, EDSC
)
1513 -> iris_raster_state (point sprite texture coordinate origin
)
1514 -> bunch of shader state
...
1518 3DSTATE_DEPTH_BUFFER
1519 3DSTATE_HIER_DEPTH_BUFFER
1520 3DSTATE_STENCIL_BUFFER
1521 3DSTATE_CLEAR_PARAMS
1522 -> iris_framebuffer_state
?
1527 iris_bind_state(struct pipe_context
*ctx
, void *state
)
1532 iris_destroy_state(struct iris_context
*ice
)
1534 // XXX: unreference resources/surfaces.
1535 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
1536 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
1538 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
1542 iris_init_state_functions(struct pipe_context
*ctx
)
1544 ctx
->create_blend_state
= iris_create_blend_state
;
1545 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
1546 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
1547 ctx
->create_sampler_state
= iris_create_sampler_state
;
1548 ctx
->create_sampler_view
= iris_create_sampler_view
;
1549 ctx
->create_surface
= iris_create_surface
;
1550 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
1551 ctx
->create_compute_state
= iris_create_compute_state
;
1552 ctx
->bind_blend_state
= iris_bind_blend_state
;
1553 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
1554 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
1555 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
1556 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
1557 ctx
->bind_compute_state
= iris_bind_state
;
1558 ctx
->delete_blend_state
= iris_delete_state
;
1559 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
1560 ctx
->delete_fs_state
= iris_delete_state
;
1561 ctx
->delete_rasterizer_state
= iris_delete_state
;
1562 ctx
->delete_sampler_state
= iris_delete_state
;
1563 ctx
->delete_vertex_elements_state
= iris_delete_state
;
1564 ctx
->delete_compute_state
= iris_delete_state
;
1565 ctx
->delete_tcs_state
= iris_delete_state
;
1566 ctx
->delete_tes_state
= iris_delete_state
;
1567 ctx
->delete_gs_state
= iris_delete_state
;
1568 ctx
->delete_vs_state
= iris_delete_state
;
1569 ctx
->set_blend_color
= iris_set_blend_color
;
1570 ctx
->set_clip_state
= iris_set_clip_state
;
1571 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
1572 ctx
->set_sampler_views
= iris_set_sampler_views
;
1573 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
1574 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
1575 ctx
->set_sample_mask
= iris_set_sample_mask
;
1576 ctx
->set_scissor_states
= iris_set_scissor_states
;
1577 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
1578 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
1579 ctx
->set_viewport_states
= iris_set_viewport_states
;
1580 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
1581 ctx
->surface_destroy
= iris_surface_destroy
;
1582 ctx
->draw_vbo
= iris_draw_vbo
;
1583 ctx
->launch_grid
= iris_launch_grid
;
1584 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
1585 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
1586 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;