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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_inlines.h"
92 #include "util/u_format.h"
93 #include "util/u_framebuffer.h"
94 #include "util/u_transfer.h"
95 #include "util/u_upload_mgr.h"
96 #include "util/u_viewport.h"
99 #include "intel/compiler/brw_compiler.h"
100 #include "intel/common/gen_l3_config.h"
101 #include "intel/common/gen_sample_positions.h"
102 #include "iris_batch.h"
103 #include "iris_context.h"
104 #include "iris_pipe.h"
105 #include "iris_resource.h"
107 #define __gen_address_type struct iris_address
108 #define __gen_user_data struct iris_batch
110 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
113 __gen_combine_address(struct iris_batch
*batch
, void *location
,
114 struct iris_address addr
, uint32_t delta
)
116 uint64_t result
= addr
.offset
+ delta
;
119 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
120 /* Assume this is a general address, not relative to a base. */
121 result
+= addr
.bo
->gtt_offset
;
127 #define __genxml_cmd_length(cmd) cmd ## _length
128 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
129 #define __genxml_cmd_header(cmd) cmd ## _header
130 #define __genxml_cmd_pack(cmd) cmd ## _pack
132 #define _iris_pack_command(batch, cmd, dst, name) \
133 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
134 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
135 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
139 #define iris_pack_command(cmd, dst, name) \
140 _iris_pack_command(NULL, cmd, dst, name)
142 #define iris_pack_state(cmd, dst, name) \
143 for (struct cmd name = {}, \
144 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
145 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
148 #define iris_emit_cmd(batch, cmd, name) \
149 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
151 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
153 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
154 for (uint32_t i = 0; i < num_dwords; i++) \
155 dw[i] = (dwords0)[i] | (dwords1)[i]; \
156 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
159 #include "genxml/genX_pack.h"
160 #include "genxml/gen_macros.h"
161 #include "genxml/genX_bits.h"
163 #define MOCS_WB (2 << 1)
166 * Statically assert that PIPE_* enums match the hardware packets.
167 * (As long as they match, we don't need to translate them.)
169 UNUSED
static void pipe_asserts()
171 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
173 /* pipe_logicop happens to match the hardware. */
174 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
175 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
176 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
177 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
178 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
179 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
180 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
181 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
182 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
183 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
184 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
185 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
186 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
187 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
188 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
189 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
191 /* pipe_blend_func happens to match the hardware. */
192 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
193 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
194 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
195 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
196 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
197 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
198 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
199 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
200 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
201 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
202 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
203 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
204 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
205 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
206 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
207 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
212 /* pipe_blend_func happens to match the hardware. */
213 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
214 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
215 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
216 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
217 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
219 /* pipe_stencil_op happens to match the hardware. */
220 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
221 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
222 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
223 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
224 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
225 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
226 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
227 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
229 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
230 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
231 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
236 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
238 static const unsigned map
[] = {
239 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
240 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
241 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
242 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
243 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
244 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
245 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
246 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
247 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
248 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
249 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
250 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
251 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
252 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
253 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
256 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
260 translate_compare_func(enum pipe_compare_func pipe_func
)
262 static const unsigned map
[] = {
263 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
264 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
265 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
266 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
267 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
268 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
269 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
270 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
272 return map
[pipe_func
];
276 translate_shadow_func(enum pipe_compare_func pipe_func
)
278 /* Gallium specifies the result of shadow comparisons as:
280 * 1 if ref <op> texel,
285 * 0 if texel <op> ref,
288 * So we need to flip the operator and also negate.
290 static const unsigned map
[] = {
291 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
292 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
293 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
294 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
295 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
296 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
297 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
298 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
300 return map
[pipe_func
];
304 translate_cull_mode(unsigned pipe_face
)
306 static const unsigned map
[4] = {
307 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
308 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
309 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
310 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
312 return map
[pipe_face
];
316 translate_fill_mode(unsigned pipe_polymode
)
318 static const unsigned map
[4] = {
319 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
320 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
321 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
322 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
324 return map
[pipe_polymode
];
328 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
330 static const unsigned map
[] = {
331 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
332 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
333 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
335 return map
[pipe_mip
];
339 translate_wrap(unsigned pipe_wrap
)
341 static const unsigned map
[] = {
342 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
343 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
344 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
345 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
346 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
347 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
349 /* These are unsupported. */
350 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
351 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
353 return map
[pipe_wrap
];
356 static struct iris_address
357 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
359 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
360 * validation list at CSO creation time, instead of draw time.
362 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
365 static struct iris_address
366 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
368 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
369 * validation list at CSO creation time, instead of draw time.
371 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
375 * Allocate space for some indirect state.
377 * Return a pointer to the map (to fill it out) and a state ref (for
378 * referring to the state in GPU commands).
381 upload_state(struct u_upload_mgr
*uploader
,
382 struct iris_state_ref
*ref
,
387 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
392 * Stream out temporary/short-lived state.
394 * This allocates space, pins the BO, and includes the BO address in the
395 * returned offset (which works because all state lives in 32-bit memory
399 stream_state(struct iris_batch
*batch
,
400 struct u_upload_mgr
*uploader
,
401 struct pipe_resource
**out_res
,
404 uint32_t *out_offset
)
408 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
410 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
411 iris_use_pinned_bo(batch
, bo
, false);
413 *out_offset
+= iris_bo_offset_from_base_address(bo
);
419 * stream_state() + memcpy.
422 emit_state(struct iris_batch
*batch
,
423 struct u_upload_mgr
*uploader
,
424 struct pipe_resource
**out_res
,
431 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
434 memcpy(map
, data
, size
);
440 * Did field 'x' change between 'old_cso' and 'new_cso'?
442 * (If so, we may want to set some dirty flags.)
444 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
445 #define cso_changed_memcmp(x) \
446 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
449 flush_for_state_base_change(struct iris_batch
*batch
)
451 /* Flush before emitting STATE_BASE_ADDRESS.
453 * This isn't documented anywhere in the PRM. However, it seems to be
454 * necessary prior to changing the surface state base adress. We've
455 * seen issues in Vulkan where we get GPU hangs when using multi-level
456 * command buffers which clear depth, reset state base address, and then
459 * Normally, in GL, we would trust the kernel to do sufficient stalls
460 * and flushes prior to executing our batch. However, it doesn't seem
461 * as if the kernel's flushing is always sufficient and we don't want to
464 * We make this an end-of-pipe sync instead of a normal flush because we
465 * do not know the current status of the GPU. On Haswell at least,
466 * having a fast-clear operation in flight at the same time as a normal
467 * rendering operation can cause hangs. Since the kernel's flushing is
468 * insufficient, we need to ensure that any rendering operations from
469 * other processes are definitely complete before we try to do our own
470 * rendering. It's a bit of a big hammer but it appears to work.
472 iris_emit_end_of_pipe_sync(batch
,
473 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
474 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
475 PIPE_CONTROL_DATA_CACHE_FLUSH
);
479 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
481 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
482 lri
.RegisterOffset
= reg
;
486 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
489 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t src
, uint32_t dst
)
491 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
492 lrr
.SourceRegisterAddress
= src
;
493 lrr
.DestinationRegisterAddress
= dst
;
498 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
500 #if GEN_GEN >= 8 && GEN_GEN < 10
501 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
503 * Software must clear the COLOR_CALC_STATE Valid field in
504 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
505 * with Pipeline Select set to GPGPU.
507 * The internal hardware docs recommend the same workaround for Gen9
510 if (pipeline
== GPGPU
)
511 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
515 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
516 * PIPELINE_SELECT [DevBWR+]":
520 * Software must ensure all the write caches are flushed through a
521 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
522 * command to invalidate read only caches prior to programming
523 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
525 iris_emit_pipe_control_flush(batch
,
526 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
527 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
528 PIPE_CONTROL_DATA_CACHE_FLUSH
|
529 PIPE_CONTROL_CS_STALL
);
531 iris_emit_pipe_control_flush(batch
,
532 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
533 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
534 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
535 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
537 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
541 sel
.PipelineSelection
= pipeline
;
546 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
551 * "This chicken bit works around a hardware issue with barrier
552 * logic encountered when switching between GPGPU and 3D pipelines.
553 * To workaround the issue, this mode bit should be set after a
554 * pipeline is selected."
557 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
558 reg
.GLKBarrierMode
= value
;
559 reg
.GLKBarrierModeMask
= 1;
561 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
566 init_state_base_address(struct iris_batch
*batch
)
568 flush_for_state_base_change(batch
);
570 /* We program most base addresses once at context initialization time.
571 * Each base address points at a 4GB memory zone, and never needs to
572 * change. See iris_bufmgr.h for a description of the memory zones.
574 * The one exception is Surface State Base Address, which needs to be
575 * updated occasionally. See iris_binder.c for the details there.
577 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
579 // XXX: MOCS is stupid for this.
580 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
581 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
582 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
583 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
584 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
585 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
588 sba
.GeneralStateBaseAddressModifyEnable
= true;
589 sba
.DynamicStateBaseAddressModifyEnable
= true;
590 sba
.IndirectObjectBaseAddressModifyEnable
= true;
591 sba
.InstructionBaseAddressModifyEnable
= true;
592 sba
.GeneralStateBufferSizeModifyEnable
= true;
593 sba
.DynamicStateBufferSizeModifyEnable
= true;
594 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
595 sba
.IndirectObjectBufferSizeModifyEnable
= true;
596 sba
.InstructionBuffersizeModifyEnable
= true;
598 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
599 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
601 sba
.GeneralStateBufferSize
= 0xfffff;
602 sba
.IndirectObjectBufferSize
= 0xfffff;
603 sba
.InstructionBufferSize
= 0xfffff;
604 sba
.DynamicStateBufferSize
= 0xfffff;
609 * Upload the initial GPU state for a render context.
611 * This sets some invariant state that needs to be programmed a particular
612 * way, but we never actually change.
615 iris_init_render_context(struct iris_screen
*screen
,
616 struct iris_batch
*batch
,
617 struct iris_vtable
*vtbl
,
618 struct pipe_debug_callback
*dbg
)
620 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
623 emit_pipeline_select(batch
, _3D
);
625 init_state_base_address(batch
);
627 // XXX: INSTPM on Gen8
628 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
629 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
630 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
632 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
635 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
636 reg
.FloatBlendOptimizationEnable
= true;
637 reg
.FloatBlendOptimizationEnableMask
= true;
638 reg
.PartialResolveDisableInVC
= true;
639 reg
.PartialResolveDisableInVCMask
= true;
641 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
643 if (devinfo
->is_geminilake
)
644 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
648 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
649 reg
.HeaderlessMessageforPreemptableContexts
= 1;
650 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
652 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
657 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
658 * changing it dynamically. We set it to the maximum size here, and
659 * instead include the render target dimensions in the viewport, so
660 * viewport extents clipping takes care of pruning stray geometry.
662 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
663 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
664 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
667 /* Set the initial MSAA sample positions. */
668 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
669 GEN_SAMPLE_POS_1X(pat
._1xSample
);
670 GEN_SAMPLE_POS_2X(pat
._2xSample
);
671 GEN_SAMPLE_POS_4X(pat
._4xSample
);
672 GEN_SAMPLE_POS_8X(pat
._8xSample
);
673 GEN_SAMPLE_POS_16X(pat
._16xSample
);
676 /* Use the legacy AA line coverage computation. */
677 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
679 /* Disable chromakeying (it's for media) */
680 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
682 /* We want regular rendering, not special HiZ operations. */
683 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
685 /* No polygon stippling offsets are necessary. */
686 // XXX: may need to set an offset for origin-UL framebuffers
687 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
689 /* Set a static partitioning of the push constant area. */
690 // XXX: this may be a bad idea...could starve the push ringbuffers...
691 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
692 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
693 alloc
._3DCommandSubOpcode
= 18 + i
;
694 alloc
.ConstantBufferOffset
= 6 * i
;
695 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
701 iris_init_compute_context(struct iris_screen
*screen
,
702 struct iris_batch
*batch
,
703 struct iris_vtable
*vtbl
,
704 struct pipe_debug_callback
*dbg
)
706 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
708 emit_pipeline_select(batch
, GPGPU
);
710 const bool has_slm
= true;
711 const bool wants_dc_cache
= true;
713 const struct gen_l3_weights w
=
714 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
715 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
718 iris_pack_state(GENX(L3CNTLREG
), ®_val
, reg
) {
719 reg
.SLMEnable
= has_slm
;
721 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
722 * in L3CNTLREG register. The default setting of the bit is not the
723 * desirable behavior.
725 reg
.ErrorDetectionBehaviorControl
= true;
727 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
728 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
729 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
730 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
732 iris_emit_lri(batch
, L3CNTLREG
, reg_val
);
734 init_state_base_address(batch
);
737 if (devinfo
->is_geminilake
)
738 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
742 struct iris_vertex_buffer_state
{
743 /** The 3DSTATE_VERTEX_BUFFERS hardware packet. */
744 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
746 /** The resource to source vertex data from. */
747 struct pipe_resource
*resources
[33];
749 /** The number of bound vertex buffers. */
750 unsigned num_buffers
;
753 struct iris_depth_buffer_state
{
754 /* Depth/HiZ/Stencil related hardware packets. */
755 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
756 GENX(3DSTATE_STENCIL_BUFFER_length
) +
757 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
758 GENX(3DSTATE_CLEAR_PARAMS_length
)];
762 * Generation-specific context state (ice->state.genx->...).
764 * Most state can go in iris_context directly, but these encode hardware
765 * packets which vary by generation.
767 struct iris_genx_state
{
768 /** SF_CLIP_VIEWPORT */
769 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
) * IRIS_MAX_VIEWPORTS
];
771 struct iris_vertex_buffer_state vertex_buffers
;
772 struct iris_depth_buffer_state depth_buffer
;
774 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
775 uint32_t streamout
[4 * GENX(3DSTATE_STREAMOUT_length
)];
779 * The pipe->set_blend_color() driver hook.
781 * This corresponds to our COLOR_CALC_STATE.
784 iris_set_blend_color(struct pipe_context
*ctx
,
785 const struct pipe_blend_color
*state
)
787 struct iris_context
*ice
= (struct iris_context
*) ctx
;
789 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
790 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
791 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
795 * Gallium CSO for blend state (see pipe_blend_state).
797 struct iris_blend_state
{
798 /** Partial 3DSTATE_PS_BLEND */
799 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
801 /** Partial BLEND_STATE */
802 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
803 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
805 bool alpha_to_coverage
; /* for shader key */
809 * The pipe->create_blend_state() driver hook.
811 * Translates a pipe_blend_state into iris_blend_state.
814 iris_create_blend_state(struct pipe_context
*ctx
,
815 const struct pipe_blend_state
*state
)
817 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
818 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
820 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
822 bool indep_alpha_blend
= false;
824 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
825 const struct pipe_rt_blend_state
*rt
=
826 &state
->rt
[state
->independent_blend_enable
? i
: 0];
828 if (rt
->rgb_func
!= rt
->alpha_func
||
829 rt
->rgb_src_factor
!= rt
->alpha_src_factor
||
830 rt
->rgb_dst_factor
!= rt
->alpha_dst_factor
)
831 indep_alpha_blend
= true;
833 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
834 be
.LogicOpEnable
= state
->logicop_enable
;
835 be
.LogicOpFunction
= state
->logicop_func
;
837 be
.PreBlendSourceOnlyClampEnable
= false;
838 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
839 be
.PreBlendColorClampEnable
= true;
840 be
.PostBlendColorClampEnable
= true;
842 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
844 be
.ColorBlendFunction
= rt
->rgb_func
;
845 be
.AlphaBlendFunction
= rt
->alpha_func
;
846 be
.SourceBlendFactor
= rt
->rgb_src_factor
;
847 be
.SourceAlphaBlendFactor
= rt
->alpha_src_factor
;
848 be
.DestinationBlendFactor
= rt
->rgb_dst_factor
;
849 be
.DestinationAlphaBlendFactor
= rt
->alpha_dst_factor
;
851 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
852 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
853 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
854 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
856 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
859 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
860 /* pb.HasWriteableRT is filled in at draw time. */
861 /* pb.AlphaTestEnable is filled in at draw time. */
862 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
863 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
865 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
867 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
868 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_src_factor
;
869 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
870 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
873 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
874 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
875 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
876 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
877 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
878 bs
.ColorDitherEnable
= state
->dither
;
879 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
887 * The pipe->bind_blend_state() driver hook.
889 * Bind a blending CSO and flag related dirty bits.
892 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
894 struct iris_context
*ice
= (struct iris_context
*) ctx
;
895 ice
->state
.cso_blend
= state
;
896 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
897 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
898 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
902 * Gallium CSO for depth, stencil, and alpha testing state.
904 struct iris_depth_stencil_alpha_state
{
905 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
906 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
908 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
909 struct pipe_alpha_state alpha
;
911 /** Outbound to resolve and cache set tracking. */
912 bool depth_writes_enabled
;
913 bool stencil_writes_enabled
;
917 * The pipe->create_depth_stencil_alpha_state() driver hook.
919 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
920 * testing state since we need pieces of it in a variety of places.
923 iris_create_zsa_state(struct pipe_context
*ctx
,
924 const struct pipe_depth_stencil_alpha_state
*state
)
926 struct iris_depth_stencil_alpha_state
*cso
=
927 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
929 bool two_sided_stencil
= state
->stencil
[1].enabled
;
931 cso
->alpha
= state
->alpha
;
932 cso
->depth_writes_enabled
= state
->depth
.writemask
;
933 cso
->stencil_writes_enabled
=
934 state
->stencil
[0].writemask
!= 0 ||
935 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 1);
937 /* The state tracker needs to optimize away EQUAL writes for us. */
938 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
940 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
941 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
942 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
943 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
944 wmds
.StencilTestFunction
=
945 translate_compare_func(state
->stencil
[0].func
);
946 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
947 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
948 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
949 wmds
.BackfaceStencilTestFunction
=
950 translate_compare_func(state
->stencil
[1].func
);
951 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
952 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
953 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
954 wmds
.StencilBufferWriteEnable
=
955 state
->stencil
[0].writemask
!= 0 ||
956 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
957 wmds
.DepthTestEnable
= state
->depth
.enabled
;
958 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
959 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
960 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
961 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
962 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
963 /* wmds.[Backface]StencilReferenceValue are merged later */
970 * The pipe->bind_depth_stencil_alpha_state() driver hook.
972 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
975 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
977 struct iris_context
*ice
= (struct iris_context
*) ctx
;
978 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
979 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
982 if (cso_changed(alpha
.ref_value
))
983 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
985 if (cso_changed(alpha
.enabled
))
986 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
988 if (cso_changed(alpha
.func
))
989 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
991 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
992 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
995 ice
->state
.cso_zsa
= new_cso
;
996 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
997 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
998 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1002 * Gallium CSO for rasterizer state.
1004 struct iris_rasterizer_state
{
1005 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1006 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1007 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1008 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1009 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1011 uint8_t num_clip_plane_consts
;
1012 bool clip_halfz
; /* for CC_VIEWPORT */
1013 bool depth_clip_near
; /* for CC_VIEWPORT */
1014 bool depth_clip_far
; /* for CC_VIEWPORT */
1015 bool flatshade
; /* for shader state */
1016 bool flatshade_first
; /* for stream output */
1017 bool clamp_fragment_color
; /* for shader state */
1018 bool light_twoside
; /* for shader state */
1019 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
1020 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1021 bool line_stipple_enable
;
1022 bool poly_stipple_enable
;
1024 bool force_persample_interp
;
1025 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1026 uint16_t sprite_coord_enable
;
1030 get_line_width(const struct pipe_rasterizer_state
*state
)
1032 float line_width
= state
->line_width
;
1034 /* From the OpenGL 4.4 spec:
1036 * "The actual width of non-antialiased lines is determined by rounding
1037 * the supplied width to the nearest integer, then clamping it to the
1038 * implementation-dependent maximum non-antialiased line width."
1040 if (!state
->multisample
&& !state
->line_smooth
)
1041 line_width
= roundf(state
->line_width
);
1043 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1044 /* For 1 pixel line thickness or less, the general anti-aliasing
1045 * algorithm gives up, and a garbage line is generated. Setting a
1046 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1047 * (one-pixel-wide), non-antialiased lines.
1049 * Lines rendered with zero Line Width are rasterized using the
1050 * "Grid Intersection Quantization" rules as specified by the
1051 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1060 * The pipe->create_rasterizer_state() driver hook.
1063 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1064 const struct pipe_rasterizer_state
*state
)
1066 struct iris_rasterizer_state
*cso
=
1067 malloc(sizeof(struct iris_rasterizer_state
));
1070 point_quad_rasterization
-> SBE
?
1075 force_persample_interp
- ?
1078 offset_units_unscaled
- cap
not exposed
1082 // XXX: it may make more sense just to store the pipe_rasterizer_state,
1083 // we're copying a lot of booleans here. But we don't need all of them...
1085 cso
->multisample
= state
->multisample
;
1086 cso
->force_persample_interp
= state
->force_persample_interp
;
1087 cso
->clip_halfz
= state
->clip_halfz
;
1088 cso
->depth_clip_near
= state
->depth_clip_near
;
1089 cso
->depth_clip_far
= state
->depth_clip_far
;
1090 cso
->flatshade
= state
->flatshade
;
1091 cso
->flatshade_first
= state
->flatshade_first
;
1092 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1093 cso
->light_twoside
= state
->light_twoside
;
1094 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1095 cso
->half_pixel_center
= state
->half_pixel_center
;
1096 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1097 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1098 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1099 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1101 if (state
->clip_plane_enable
!= 0)
1102 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1104 cso
->num_clip_plane_consts
= 0;
1106 float line_width
= get_line_width(state
);
1108 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1109 sf
.StatisticsEnable
= true;
1110 sf
.ViewportTransformEnable
= true;
1111 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1112 sf
.LineEndCapAntialiasingRegionWidth
=
1113 state
->line_smooth
? _10pixels
: _05pixels
;
1114 sf
.LastPixelEnable
= state
->line_last_pixel
;
1115 sf
.LineWidth
= line_width
;
1116 sf
.SmoothPointEnable
= state
->point_smooth
|| state
->multisample
;
1117 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1118 sf
.PointWidth
= state
->point_size
;
1120 if (state
->flatshade_first
) {
1121 sf
.TriangleFanProvokingVertexSelect
= 1;
1123 sf
.TriangleStripListProvokingVertexSelect
= 2;
1124 sf
.TriangleFanProvokingVertexSelect
= 2;
1125 sf
.LineStripListProvokingVertexSelect
= 1;
1129 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1130 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1131 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1132 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1133 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1134 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1135 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1136 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1137 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1138 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1139 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1140 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1141 rr
.SmoothPointEnable
= state
->point_smooth
|| state
->multisample
;
1142 rr
.AntialiasingEnable
= state
->line_smooth
;
1143 rr
.ScissorRectangleEnable
= state
->scissor
;
1144 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1145 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1146 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
1149 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1150 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1151 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1153 cl
.StatisticsEnable
= true;
1154 cl
.EarlyCullEnable
= true;
1155 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1156 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1157 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1158 cl
.GuardbandClipTestEnable
= true;
1159 cl
.ClipMode
= CLIPMODE_NORMAL
;
1160 cl
.ClipEnable
= true;
1161 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
1162 cl
.MinimumPointWidth
= 0.125;
1163 cl
.MaximumPointWidth
= 255.875;
1165 if (state
->flatshade_first
) {
1166 cl
.TriangleFanProvokingVertexSelect
= 1;
1168 cl
.TriangleStripListProvokingVertexSelect
= 2;
1169 cl
.TriangleFanProvokingVertexSelect
= 2;
1170 cl
.LineStripListProvokingVertexSelect
= 1;
1174 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1175 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1176 * filled in at draw time from the FS program.
1178 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1179 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1180 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1181 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1182 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1185 /* Remap from 0..255 back to 1..256 */
1186 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1188 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1189 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1190 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1191 line
.LineStippleRepeatCount
= line_stipple_factor
;
1198 * The pipe->bind_rasterizer_state() driver hook.
1200 * Bind a rasterizer CSO and flag related dirty bits.
1203 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1205 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1206 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1207 struct iris_rasterizer_state
*new_cso
= state
;
1210 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1211 if (cso_changed_memcmp(line_stipple
))
1212 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1214 if (cso_changed(half_pixel_center
))
1215 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1217 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1218 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1220 if (cso_changed(rasterizer_discard
) || cso_changed(flatshade_first
))
1221 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1223 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1224 cso_changed(clip_halfz
))
1225 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1227 if (cso_changed(sprite_coord_enable
) || cso_changed(light_twoside
))
1228 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1231 ice
->state
.cso_rast
= new_cso
;
1232 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1233 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1234 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1238 * Return true if the given wrap mode requires the border color to exist.
1240 * (We can skip uploading it if the sampler isn't going to use it.)
1243 wrap_mode_needs_border_color(unsigned wrap_mode
)
1245 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1249 * Gallium CSO for sampler state.
1251 struct iris_sampler_state
{
1252 union pipe_color_union border_color
;
1253 bool needs_border_color
;
1255 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1259 * The pipe->create_sampler_state() driver hook.
1261 * We fill out SAMPLER_STATE (except for the border color pointer), and
1262 * store that on the CPU. It doesn't make sense to upload it to a GPU
1263 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1264 * all bound sampler states to be in contiguous memor.
1267 iris_create_sampler_state(struct pipe_context
*ctx
,
1268 const struct pipe_sampler_state
*state
)
1270 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1275 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1276 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1278 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1279 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1280 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1282 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1284 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1285 wrap_mode_needs_border_color(wrap_t
) ||
1286 wrap_mode_needs_border_color(wrap_r
);
1288 float min_lod
= state
->min_lod
;
1289 unsigned mag_img_filter
= state
->mag_img_filter
;
1291 // XXX: explain this code ported from ilo...I don't get it at all...
1292 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1293 state
->min_lod
> 0.0f
) {
1295 mag_img_filter
= state
->min_img_filter
;
1298 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1299 samp
.TCXAddressControlMode
= wrap_s
;
1300 samp
.TCYAddressControlMode
= wrap_t
;
1301 samp
.TCZAddressControlMode
= wrap_r
;
1302 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1303 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1304 samp
.MinModeFilter
= state
->min_img_filter
;
1305 samp
.MagModeFilter
= mag_img_filter
;
1306 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1307 samp
.MaximumAnisotropy
= RATIO21
;
1309 if (state
->max_anisotropy
>= 2) {
1310 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1311 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1312 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1315 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1316 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1318 samp
.MaximumAnisotropy
=
1319 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1322 /* Set address rounding bits if not using nearest filtering. */
1323 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1324 samp
.UAddressMinFilterRoundingEnable
= true;
1325 samp
.VAddressMinFilterRoundingEnable
= true;
1326 samp
.RAddressMinFilterRoundingEnable
= true;
1329 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1330 samp
.UAddressMagFilterRoundingEnable
= true;
1331 samp
.VAddressMagFilterRoundingEnable
= true;
1332 samp
.RAddressMagFilterRoundingEnable
= true;
1335 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1336 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1338 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1340 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1341 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1342 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1343 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1345 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1352 * The pipe->bind_sampler_states() driver hook.
1354 * Now that we know all the sampler states, we upload them all into a
1355 * contiguous area of GPU memory, for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1356 * We also fill out the border color state pointers at this point.
1358 * We could defer this work to draw time, but we assume that binding
1359 * will be less frequent than drawing.
1361 // XXX: this may be a bad idea, need to make sure that st/mesa calls us
1362 // XXX: with the complete set of shaders. If it makes multiple calls to
1363 // XXX: things one at a time, we could waste a lot of time assembling things.
1364 // XXX: it doesn't even BUY us anything to do it here, because we only flag
1365 // XXX: IRIS_DIRTY_SAMPLER_STATE when this is called...
1367 iris_bind_sampler_states(struct pipe_context
*ctx
,
1368 enum pipe_shader_type p_stage
,
1369 unsigned start
, unsigned count
,
1372 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1373 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1374 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1376 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1377 shs
->num_samplers
= MAX2(shs
->num_samplers
, start
+ count
);
1379 for (int i
= 0; i
< count
; i
++) {
1380 shs
->samplers
[start
+ i
] = states
[i
];
1383 // XXX: count may include NULLs
1385 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1386 * in the dynamic state memory zone, so we can point to it via the
1387 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1390 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
,
1391 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
1395 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1396 shs
->sampler_table
.offset
+=
1397 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1399 /* Make sure all land in the same BO */
1400 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1402 for (int i
= 0; i
< count
; i
++) {
1403 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1406 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1407 } else if (!state
->needs_border_color
) {
1408 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1410 ice
->state
.need_border_colors
= true;
1412 /* Stream out the border color and merge the pointer. */
1414 iris_upload_border_color(ice
, &state
->border_color
);
1416 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1417 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1418 dyns
.BorderColorPointer
= offset
;
1421 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1422 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1425 map
+= GENX(SAMPLER_STATE_length
);
1428 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1431 static enum isl_channel_select
1432 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1435 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1436 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1437 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1438 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1439 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1440 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1441 default: unreachable("invalid swizzle");
1446 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1449 enum isl_format format
,
1453 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1454 const unsigned cpp
= fmtl
->bpb
/ 8;
1456 /* The ARB_texture_buffer_specification says:
1458 * "The number of texels in the buffer texture's texel array is given by
1460 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1462 * where <buffer_size> is the size of the buffer object, in basic
1463 * machine units and <components> and <base_type> are the element count
1464 * and base data type for elements, as specified in Table X.1. The
1465 * number of texels in the texel array is then clamped to the
1466 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1468 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1469 * so that when ISL divides by stride to obtain the number of texels, that
1470 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1472 unsigned final_size
=
1473 MIN3(size
, bo
->size
- offset
, IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1475 isl_buffer_fill_state(isl_dev
, map
,
1476 .address
= bo
->gtt_offset
+ offset
,
1477 .size_B
= final_size
,
1484 * The pipe->create_sampler_view() driver hook.
1486 static struct pipe_sampler_view
*
1487 iris_create_sampler_view(struct pipe_context
*ctx
,
1488 struct pipe_resource
*tex
,
1489 const struct pipe_sampler_view
*tmpl
)
1491 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1492 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1493 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1494 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1499 /* initialize base object */
1501 isv
->base
.context
= ctx
;
1502 isv
->base
.texture
= NULL
;
1503 pipe_reference_init(&isv
->base
.reference
, 1);
1504 pipe_resource_reference(&isv
->base
.texture
, tex
);
1506 void *map
= upload_state(ice
->state
.surface_uploader
, &isv
->surface_state
,
1507 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1511 struct iris_bo
*state_bo
= iris_resource_bo(isv
->surface_state
.res
);
1512 isv
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1514 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1515 struct iris_resource
*zres
, *sres
;
1516 const struct util_format_description
*desc
=
1517 util_format_description(tmpl
->format
);
1519 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1521 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1524 isv
->res
= (struct iris_resource
*) tex
;
1526 isl_surf_usage_flags_t usage
=
1527 ISL_SURF_USAGE_TEXTURE_BIT
|
1528 (isv
->res
->surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
);
1530 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1531 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1532 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1534 const struct iris_format_info fmt
=
1535 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1537 isv
->view
= (struct isl_view
) {
1539 .swizzle
= (struct isl_swizzle
) {
1540 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1541 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1542 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1543 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1548 /* Fill out SURFACE_STATE for this view. */
1549 if (tmpl
->target
!= PIPE_BUFFER
) {
1550 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1551 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1552 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1553 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1554 isv
->view
.array_len
=
1555 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1557 isl_surf_fill_state(&screen
->isl_dev
, map
,
1558 .surf
= &isv
->res
->surf
, .view
= &isv
->view
,
1560 .address
= isv
->res
->bo
->gtt_offset
);
1562 // .clear_color = clear_color,
1564 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
->bo
, map
,
1565 isv
->view
.format
, tmpl
->u
.buf
.offset
,
1573 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1574 struct pipe_sampler_view
*state
)
1576 struct iris_sampler_view
*isv
= (void *) state
;
1577 pipe_resource_reference(&state
->texture
, NULL
);
1578 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1583 * The pipe->create_surface() driver hook.
1585 * In Gallium nomenclature, "surfaces" are a view of a resource that
1586 * can be bound as a render target or depth/stencil buffer.
1588 static struct pipe_surface
*
1589 iris_create_surface(struct pipe_context
*ctx
,
1590 struct pipe_resource
*tex
,
1591 const struct pipe_surface
*tmpl
)
1593 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1594 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1595 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1596 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1597 struct pipe_surface
*psurf
= &surf
->base
;
1598 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1603 pipe_reference_init(&psurf
->reference
, 1);
1604 pipe_resource_reference(&psurf
->texture
, tex
);
1605 psurf
->context
= ctx
;
1606 psurf
->format
= tmpl
->format
;
1607 psurf
->width
= tex
->width0
;
1608 psurf
->height
= tex
->height0
;
1609 psurf
->texture
= tex
;
1610 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1611 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1612 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1614 isl_surf_usage_flags_t usage
= 0;
1616 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1617 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1618 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1620 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1622 const struct iris_format_info fmt
=
1623 iris_format_for_usage(devinfo
, psurf
->format
, usage
);
1625 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1626 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1627 /* Framebuffer validation will reject this invalid case, but it
1628 * hasn't had the opportunity yet. In the meantime, we need to
1629 * avoid hitting ISL asserts about unsupported formats below.
1635 surf
->view
= (struct isl_view
) {
1637 .base_level
= tmpl
->u
.tex
.level
,
1639 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1640 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1641 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1645 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1646 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1647 ISL_SURF_USAGE_STENCIL_BIT
))
1651 void *map
= upload_state(ice
->state
.surface_uploader
, &surf
->surface_state
,
1652 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1656 struct iris_bo
*state_bo
= iris_resource_bo(surf
->surface_state
.res
);
1657 surf
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1659 isl_surf_fill_state(&screen
->isl_dev
, map
,
1660 .surf
= &res
->surf
, .view
= &surf
->view
,
1662 .address
= res
->bo
->gtt_offset
);
1664 // .clear_color = clear_color,
1670 * The pipe->set_shader_images() driver hook.
1673 iris_set_shader_images(struct pipe_context
*ctx
,
1674 enum pipe_shader_type p_stage
,
1675 unsigned start_slot
, unsigned count
,
1676 const struct pipe_image_view
*p_images
)
1678 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1679 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1680 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1681 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1682 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1684 shs
->num_images
= MAX2(shs
->num_images
, start_slot
+ count
);
1686 for (unsigned i
= 0; i
< count
; i
++) {
1687 if (p_images
&& p_images
[i
].resource
) {
1688 const struct pipe_image_view
*img
= &p_images
[i
];
1689 struct iris_resource
*res
= (void *) img
->resource
;
1690 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, &res
->base
);
1692 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
1694 // XXX: these are not retained forever, use a separate uploader?
1696 upload_state(ice
->state
.surface_uploader
,
1697 &shs
->image
[start_slot
+ i
].surface_state
,
1698 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1699 if (!unlikely(map
)) {
1700 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1704 struct iris_bo
*surf_state_bo
=
1705 iris_resource_bo(shs
->image
[start_slot
+ i
].surface_state
.res
);
1706 shs
->image
[start_slot
+ i
].surface_state
.offset
+=
1707 iris_bo_offset_from_base_address(surf_state_bo
);
1709 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1710 enum isl_format isl_format
=
1711 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
1713 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
)
1714 isl_format
= isl_lower_storage_image_format(devinfo
, isl_format
);
1716 shs
->image
[start_slot
+ i
].access
= img
->shader_access
;
1718 if (res
->base
.target
!= PIPE_BUFFER
) {
1719 struct isl_view view
= {
1720 .format
= isl_format
,
1721 .base_level
= img
->u
.tex
.level
,
1723 .base_array_layer
= img
->u
.tex
.first_layer
,
1724 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
1725 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1729 isl_surf_fill_state(&screen
->isl_dev
, map
,
1730 .surf
= &res
->surf
, .view
= &view
,
1732 .address
= res
->bo
->gtt_offset
);
1734 // .clear_color = clear_color,
1736 fill_buffer_surface_state(&screen
->isl_dev
, res
->bo
, map
,
1737 isl_format
, img
->u
.buf
.offset
,
1741 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1742 pipe_resource_reference(&shs
->image
[start_slot
+ i
].surface_state
.res
,
1747 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1752 * The pipe->set_sampler_views() driver hook.
1755 iris_set_sampler_views(struct pipe_context
*ctx
,
1756 enum pipe_shader_type p_stage
,
1757 unsigned start
, unsigned count
,
1758 struct pipe_sampler_view
**views
)
1760 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1761 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1762 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1765 for (i
= 0; i
< count
; i
++) {
1766 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1767 &shs
->textures
[i
], views
[i
]);
1768 struct iris_sampler_view
*view
= (void *) views
[i
];
1770 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
1772 for (; i
< shs
->num_textures
; i
++) {
1773 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1774 &shs
->textures
[i
], NULL
);
1777 shs
->num_textures
= count
;
1779 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
1783 * The pipe->set_tess_state() driver hook.
1786 iris_set_tess_state(struct pipe_context
*ctx
,
1787 const float default_outer_level
[4],
1788 const float default_inner_level
[2])
1790 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1792 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
1793 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
1795 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
1799 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1801 struct iris_surface
*surf
= (void *) p_surf
;
1802 pipe_resource_reference(&p_surf
->texture
, NULL
);
1803 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
1808 iris_set_clip_state(struct pipe_context
*ctx
,
1809 const struct pipe_clip_state
*state
)
1811 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1812 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
1814 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
1816 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
;
1817 shs
->cbuf0_needs_upload
= true;
1821 * The pipe->set_polygon_stipple() driver hook.
1824 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1825 const struct pipe_poly_stipple
*state
)
1827 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1828 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1829 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1833 * The pipe->set_sample_mask() driver hook.
1836 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1838 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1840 /* We only support 16x MSAA, so we have 16 bits of sample maks.
1841 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
1843 ice
->state
.sample_mask
= sample_mask
& 0xffff;
1844 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1848 * The pipe->set_scissor_states() driver hook.
1850 * This corresponds to our SCISSOR_RECT state structures. It's an
1851 * exact match, so we just store them, and memcpy them out later.
1854 iris_set_scissor_states(struct pipe_context
*ctx
,
1855 unsigned start_slot
,
1856 unsigned num_scissors
,
1857 const struct pipe_scissor_state
*rects
)
1859 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1861 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1862 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
1863 /* If the scissor was out of bounds and got clamped to 0 width/height
1864 * at the bounds, the subtraction of 1 from maximums could produce a
1865 * negative number and thus not clip anything. Instead, just provide
1866 * a min > max scissor inside the bounds, which produces the expected
1869 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
1870 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
1873 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
1874 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
1875 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
1880 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1884 * The pipe->set_stencil_ref() driver hook.
1886 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
1889 iris_set_stencil_ref(struct pipe_context
*ctx
,
1890 const struct pipe_stencil_ref
*state
)
1892 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1893 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1894 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1898 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1900 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1905 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1906 float m00
, float m11
, float m30
, float m31
,
1907 float *xmin
, float *xmax
,
1908 float *ymin
, float *ymax
)
1910 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1911 * Strips and Fans documentation:
1913 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1914 * fixed-point "guardband" range supported by the rasterization hardware"
1918 * "In almost all circumstances, if an object’s vertices are actually
1919 * modified by this clamping (i.e., had X or Y coordinates outside of
1920 * the guardband extent the rendered object will not match the intended
1921 * result. Therefore software should take steps to ensure that this does
1922 * not happen - e.g., by clipping objects such that they do not exceed
1923 * these limits after the Drawing Rectangle is applied."
1925 * I believe the fundamental restriction is that the rasterizer (in
1926 * the SF/WM stages) have a limit on the number of pixels that can be
1927 * rasterized. We need to ensure any coordinates beyond the rasterizer
1928 * limit are handled by the clipper. So effectively that limit becomes
1929 * the clipper's guardband size.
1931 * It goes on to say:
1933 * "In addition, in order to be correctly rendered, objects must have a
1934 * screenspace bounding box not exceeding 8K in the X or Y direction.
1935 * This additional restriction must also be comprehended by software,
1936 * i.e., enforced by use of clipping."
1938 * This makes no sense. Gen7+ hardware supports 16K render targets,
1939 * and you definitely need to be able to draw polygons that fill the
1940 * surface. Our assumption is that the rasterizer was limited to 8K
1941 * on Sandybridge, which only supports 8K surfaces, and it was actually
1942 * increased to 16K on Ivybridge and later.
1944 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1946 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1948 if (m00
!= 0 && m11
!= 0) {
1949 /* First, we compute the screen-space render area */
1950 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1951 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1952 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1953 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1955 /* We want the guardband to be centered on that */
1956 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1957 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1958 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1959 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1961 /* Now we need it in native device coordinates */
1962 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1963 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1964 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1965 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1967 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1968 * flipped upside-down. X should be fine though.
1970 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1971 *xmin
= ndc_gb_xmin
;
1972 *xmax
= ndc_gb_xmax
;
1973 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1974 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1976 /* The viewport scales to 0, so nothing will be rendered. */
1986 * The pipe->set_viewport_states() driver hook.
1988 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
1989 * the guardband yet, as we need the framebuffer dimensions, but we can
1990 * at least fill out the rest.
1993 iris_set_viewport_states(struct pipe_context
*ctx
,
1994 unsigned start_slot
,
1996 const struct pipe_viewport_state
*states
)
1998 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1999 struct iris_genx_state
*genx
= ice
->state
.genx
;
2001 &genx
->sf_cl_vp
[start_slot
* GENX(SF_CLIP_VIEWPORT_length
)];
2003 for (unsigned i
= 0; i
< count
; i
++) {
2004 const struct pipe_viewport_state
*state
= &states
[i
];
2006 memcpy(&ice
->state
.viewports
[start_slot
+ i
], state
, sizeof(*state
));
2008 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
2009 vp
.ViewportMatrixElementm00
= state
->scale
[0];
2010 vp
.ViewportMatrixElementm11
= state
->scale
[1];
2011 vp
.ViewportMatrixElementm22
= state
->scale
[2];
2012 vp
.ViewportMatrixElementm30
= state
->translate
[0];
2013 vp
.ViewportMatrixElementm31
= state
->translate
[1];
2014 vp
.ViewportMatrixElementm32
= state
->translate
[2];
2015 /* XXX: in i965 this is computed based on the drawbuffer size,
2016 * but we don't have that here...
2018 vp
.XMinClipGuardband
= -1.0;
2019 vp
.XMaxClipGuardband
= 1.0;
2020 vp
.YMinClipGuardband
= -1.0;
2021 vp
.YMaxClipGuardband
= 1.0;
2022 vp
.XMinViewPort
= viewport_extent(state
, 0, -1.0f
);
2023 vp
.XMaxViewPort
= viewport_extent(state
, 0, 1.0f
) - 1;
2024 vp
.YMinViewPort
= viewport_extent(state
, 1, -1.0f
);
2025 vp
.YMaxViewPort
= viewport_extent(state
, 1, 1.0f
) - 1;
2028 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
2031 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2033 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2034 !ice
->state
.cso_rast
->depth_clip_far
))
2035 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2039 * The pipe->set_framebuffer_state() driver hook.
2041 * Sets the current draw FBO, including color render targets, depth,
2042 * and stencil buffers.
2045 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2046 const struct pipe_framebuffer_state
*state
)
2048 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2049 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2050 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2051 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2052 struct iris_resource
*zres
;
2053 struct iris_resource
*stencil_res
;
2055 unsigned samples
= util_framebuffer_get_num_samples(state
);
2057 if (cso
->samples
!= samples
) {
2058 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2061 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2062 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2065 if ((cso
->layers
== 0) != (state
->layers
== 0)) {
2066 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2069 util_copy_framebuffer_state(cso
, state
);
2070 cso
->samples
= samples
;
2072 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2074 struct isl_view view
= {
2077 .base_array_layer
= 0,
2079 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2082 struct isl_depth_stencil_hiz_emit_info info
= {
2088 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2091 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2092 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2094 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2097 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2099 info
.depth_surf
= &zres
->surf
;
2100 info
.depth_address
= zres
->bo
->gtt_offset
;
2101 info
.hiz_usage
= ISL_AUX_USAGE_NONE
;
2103 view
.format
= zres
->surf
.format
;
2107 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2108 info
.stencil_surf
= &stencil_res
->surf
;
2109 info
.stencil_address
= stencil_res
->bo
->gtt_offset
;
2111 view
.format
= stencil_res
->surf
.format
;
2115 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2117 /* Make a null surface for unbound buffers */
2118 void *null_surf_map
=
2119 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2120 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2121 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2122 isl_extent3d(MAX2(cso
->width
, 1),
2123 MAX2(cso
->height
, 1),
2124 cso
->layers
? cso
->layers
: 1));
2125 ice
->state
.null_fb
.offset
+=
2126 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2128 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2130 /* Render target change */
2131 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2133 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2136 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2137 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2139 /* The PIPE_CONTROL command description says:
2141 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2142 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2143 * Target Cache Flush by enabling this bit. When render target flush
2144 * is set due to new association of BTI, PS Scoreboard Stall bit must
2145 * be set in this packet."
2147 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2148 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2149 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2150 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2155 upload_ubo_surf_state(struct iris_context
*ice
,
2156 struct iris_const_buffer
*cbuf
,
2157 unsigned buffer_size
)
2159 struct pipe_context
*ctx
= &ice
->ctx
;
2160 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
2162 // XXX: these are not retained forever, use a separate uploader?
2164 upload_state(ice
->state
.surface_uploader
, &cbuf
->surface_state
,
2165 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2166 if (!unlikely(map
)) {
2167 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2171 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2172 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state
.res
);
2173 cbuf
->surface_state
.offset
+= iris_bo_offset_from_base_address(surf_bo
);
2175 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2176 .address
= res
->bo
->gtt_offset
+ cbuf
->data
.offset
,
2177 .size_B
= MIN2(buffer_size
,
2178 res
->bo
->size
- cbuf
->data
.offset
),
2179 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
2185 * The pipe->set_constant_buffer() driver hook.
2187 * This uploads any constant data in user buffers, and references
2188 * any UBO resources containing constant data.
2191 iris_set_constant_buffer(struct pipe_context
*ctx
,
2192 enum pipe_shader_type p_stage
, unsigned index
,
2193 const struct pipe_constant_buffer
*input
)
2195 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2196 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2197 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2198 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
2200 if (input
&& input
->buffer
) {
2203 pipe_resource_reference(&cbuf
->data
.res
, input
->buffer
);
2204 cbuf
->data
.offset
= input
->buffer_offset
;
2206 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2207 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2209 upload_ubo_surf_state(ice
, cbuf
, input
->buffer_size
);
2211 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2212 pipe_resource_reference(&cbuf
->surface_state
.res
, NULL
);
2217 memcpy(&shs
->cbuf0
, input
, sizeof(shs
->cbuf0
));
2219 memset(&shs
->cbuf0
, 0, sizeof(shs
->cbuf0
));
2221 shs
->cbuf0_needs_upload
= true;
2224 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2225 // XXX: maybe not necessary all the time...?
2226 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2227 // XXX: pull model we may need actual new bindings...
2228 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2232 upload_uniforms(struct iris_context
*ice
,
2233 gl_shader_stage stage
)
2235 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2236 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
2237 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2239 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t) +
2240 shs
->cbuf0
.buffer_size
;
2242 if (upload_size
== 0)
2246 upload_state(ice
->ctx
.const_uploader
, &cbuf
->data
, upload_size
, 64);
2248 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2249 uint32_t sysval
= shader
->system_values
[i
];
2252 if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2253 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2254 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2255 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2257 assert(!"unhandled system value");
2263 if (shs
->cbuf0
.user_buffer
) {
2264 memcpy(map
, shs
->cbuf0
.user_buffer
, shs
->cbuf0
.buffer_size
);
2267 upload_ubo_surf_state(ice
, cbuf
, upload_size
);
2271 * The pipe->set_shader_buffers() driver hook.
2273 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2274 * SURFACE_STATE here, as the buffer offset may change each time.
2277 iris_set_shader_buffers(struct pipe_context
*ctx
,
2278 enum pipe_shader_type p_stage
,
2279 unsigned start_slot
, unsigned count
,
2280 const struct pipe_shader_buffer
*buffers
)
2282 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2283 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2284 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2285 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2287 for (unsigned i
= 0; i
< count
; i
++) {
2288 if (buffers
&& buffers
[i
].buffer
) {
2289 const struct pipe_shader_buffer
*buffer
= &buffers
[i
];
2290 struct iris_resource
*res
= (void *) buffer
->buffer
;
2291 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], &res
->base
);
2293 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2295 // XXX: these are not retained forever, use a separate uploader?
2297 upload_state(ice
->state
.surface_uploader
,
2298 &shs
->ssbo_surface_state
[start_slot
+ i
],
2299 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2300 if (!unlikely(map
)) {
2301 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2305 struct iris_bo
*surf_state_bo
=
2306 iris_resource_bo(shs
->ssbo_surface_state
[start_slot
+ i
].res
);
2307 shs
->ssbo_surface_state
[start_slot
+ i
].offset
+=
2308 iris_bo_offset_from_base_address(surf_state_bo
);
2310 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2312 res
->bo
->gtt_offset
+ buffer
->buffer_offset
,
2314 MIN2(buffer
->buffer_size
,
2315 res
->bo
->size
- buffer
->buffer_offset
),
2316 .format
= ISL_FORMAT_RAW
,
2320 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2321 pipe_resource_reference(&shs
->ssbo_surface_state
[start_slot
+ i
].res
,
2326 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2330 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2336 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
2338 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
2339 pipe_resource_reference(&cso
->resources
[i
], NULL
);
2343 * The pipe->set_vertex_buffers() driver hook.
2345 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2348 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2349 unsigned start_slot
, unsigned count
,
2350 const struct pipe_vertex_buffer
*buffers
)
2352 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2353 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
2355 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
2360 cso
->num_buffers
= count
;
2362 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
2363 vb
.DWordLength
= 4 * MAX2(cso
->num_buffers
, 1) - 1;
2366 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
2369 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
2370 vb
.VertexBufferIndex
= start_slot
;
2371 vb
.NullVertexBuffer
= true;
2372 vb
.AddressModifyEnable
= true;
2376 for (unsigned i
= 0; i
< count
; i
++) {
2377 assert(!buffers
[i
].is_user_buffer
);
2379 pipe_resource_reference(&cso
->resources
[i
], buffers
[i
].buffer
.resource
);
2380 struct iris_resource
*res
= (void *) cso
->resources
[i
];
2383 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2385 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
2386 vb
.VertexBufferIndex
= start_slot
+ i
;
2388 vb
.AddressModifyEnable
= true;
2389 vb
.BufferPitch
= buffers
[i
].stride
;
2391 vb
.BufferSize
= res
->bo
->size
;
2392 vb
.BufferStartingAddress
=
2393 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffers
[i
].buffer_offset
);
2395 vb
.NullVertexBuffer
= true;
2399 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
2402 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2406 * Gallium CSO for vertex elements.
2408 struct iris_vertex_element_state
{
2409 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2410 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2415 * The pipe->create_vertex_elements() driver hook.
2417 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2418 * and 3DSTATE_VF_INSTANCING commands. SGVs are handled at draw time.
2421 iris_create_vertex_elements(struct pipe_context
*ctx
,
2423 const struct pipe_vertex_element
*state
)
2425 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2426 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2427 struct iris_vertex_element_state
*cso
=
2428 malloc(sizeof(struct iris_vertex_element_state
));
2433 * - create edge flag one
2435 * - if those are necessary, use count + 1/2/3... OR in the length
2437 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2439 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2442 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2443 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2446 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2448 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2449 ve
.Component0Control
= VFCOMP_STORE_0
;
2450 ve
.Component1Control
= VFCOMP_STORE_0
;
2451 ve
.Component2Control
= VFCOMP_STORE_0
;
2452 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2455 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2459 for (int i
= 0; i
< count
; i
++) {
2460 const struct iris_format_info fmt
=
2461 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2462 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2463 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2465 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2466 case 0: comp
[0] = VFCOMP_STORE_0
;
2467 case 1: comp
[1] = VFCOMP_STORE_0
;
2468 case 2: comp
[2] = VFCOMP_STORE_0
;
2470 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2471 : VFCOMP_STORE_1_FP
;
2474 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2475 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2477 ve
.SourceElementOffset
= state
[i
].src_offset
;
2478 ve
.SourceElementFormat
= fmt
.fmt
;
2479 ve
.Component0Control
= comp
[0];
2480 ve
.Component1Control
= comp
[1];
2481 ve
.Component2Control
= comp
[2];
2482 ve
.Component3Control
= comp
[3];
2485 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2486 vi
.VertexElementIndex
= i
;
2487 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2488 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2491 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2492 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2499 * The pipe->bind_vertex_elements_state() driver hook.
2502 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2504 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2505 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2506 struct iris_vertex_element_state
*new_cso
= state
;
2508 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2509 * we need to re-emit it to ensure we're overriding the right one.
2511 if (new_cso
&& cso_changed(count
))
2512 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2514 ice
->state
.cso_vertex_elements
= state
;
2515 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2519 * Gallium CSO for stream output (transform feedback) targets.
2521 struct iris_stream_output_target
{
2522 struct pipe_stream_output_target base
;
2524 uint32_t so_buffer
[GENX(3DSTATE_SO_BUFFER_length
)];
2526 /** Storage holding the offset where we're writing in the buffer */
2527 struct iris_state_ref offset
;
2531 * The pipe->create_stream_output_target() driver hook.
2533 * "Target" here refers to a destination buffer. We translate this into
2534 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2535 * know which buffer this represents, or whether we ought to zero the
2536 * write-offsets, or append. Those are handled in the set() hook.
2538 static struct pipe_stream_output_target
*
2539 iris_create_stream_output_target(struct pipe_context
*ctx
,
2540 struct pipe_resource
*p_res
,
2541 unsigned buffer_offset
,
2542 unsigned buffer_size
)
2544 struct iris_resource
*res
= (void *) p_res
;
2545 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2549 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
2551 pipe_reference_init(&cso
->base
.reference
, 1);
2552 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
2553 cso
->base
.buffer_offset
= buffer_offset
;
2554 cso
->base
.buffer_size
= buffer_size
;
2555 cso
->base
.context
= ctx
;
2557 upload_state(ctx
->stream_uploader
, &cso
->offset
, 4 * sizeof(uint32_t), 4);
2559 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), cso
->so_buffer
, sob
) {
2560 sob
.SurfaceBaseAddress
=
2561 rw_bo(NULL
, res
->bo
->gtt_offset
+ buffer_offset
);
2562 sob
.SOBufferEnable
= true;
2563 sob
.StreamOffsetWriteEnable
= true;
2564 sob
.StreamOutputBufferOffsetAddressEnable
= true;
2565 sob
.MOCS
= MOCS_WB
; // XXX: MOCS
2567 sob
.SurfaceSize
= MAX2(buffer_size
/ 4, 1) - 1;
2569 /* .SOBufferIndex, .StreamOffset, and .StreamOutputBufferOffsetAddress
2570 * are filled in later when we have stream IDs.
2578 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2579 struct pipe_stream_output_target
*state
)
2581 struct iris_stream_output_target
*cso
= (void *) state
;
2583 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2584 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2590 * The pipe->set_stream_output_targets() driver hook.
2592 * At this point, we know which targets are bound to a particular index,
2593 * and also whether we want to append or start over. We can finish the
2594 * 3DSTATE_SO_BUFFER packets we started earlier.
2597 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2598 unsigned num_targets
,
2599 struct pipe_stream_output_target
**targets
,
2600 const unsigned *offsets
)
2602 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2603 struct iris_genx_state
*genx
= ice
->state
.genx
;
2604 uint32_t *so_buffers
= genx
->so_buffers
;
2606 const bool active
= num_targets
> 0;
2607 if (ice
->state
.streamout_active
!= active
) {
2608 ice
->state
.streamout_active
= active
;
2609 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2611 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
2612 * it's a non-pipelined command. If we're switching streamout on, we
2613 * may have missed emitting it earlier, so do so now. (We're already
2614 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
2617 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
2620 for (int i
= 0; i
< 4; i
++) {
2621 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2622 i
< num_targets
? targets
[i
] : NULL
);
2625 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2629 for (unsigned i
= 0; i
< 4; i
++,
2630 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2632 if (i
>= num_targets
|| !targets
[i
]) {
2633 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
2634 sob
.SOBufferIndex
= i
;
2638 struct iris_stream_output_target
*tgt
= (void *) targets
[i
];
2640 /* Note that offsets[i] will either be 0, causing us to zero
2641 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
2642 * "continue appending at the existing offset."
2644 assert(offsets
[i
] == 0 || offsets
[i
] == 0xFFFFFFFF);
2646 uint32_t dynamic
[GENX(3DSTATE_SO_BUFFER_length
)];
2647 iris_pack_state(GENX(3DSTATE_SO_BUFFER
), dynamic
, dyns
) {
2648 dyns
.SOBufferIndex
= i
;
2649 dyns
.StreamOffset
= offsets
[i
];
2650 dyns
.StreamOutputBufferOffsetAddress
=
2651 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+ tgt
->offset
.offset
+ i
* sizeof(uint32_t));
2654 for (uint32_t j
= 0; j
< GENX(3DSTATE_SO_BUFFER_length
); j
++) {
2655 so_buffers
[j
] = tgt
->so_buffer
[j
] | dynamic
[j
];
2659 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
2663 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
2664 * 3DSTATE_STREAMOUT packets.
2666 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
2667 * hardware to record. We can create it entirely based on the shader, with
2668 * no dynamic state dependencies.
2670 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
2671 * state-based settings. We capture the shader-related ones here, and merge
2672 * the rest in at draw time.
2675 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
2676 const struct brw_vue_map
*vue_map
)
2678 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2679 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2680 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2681 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2683 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2685 memset(so_decl
, 0, sizeof(so_decl
));
2687 /* Construct the list of SO_DECLs to be emitted. The formatting of the
2688 * command feels strange -- each dword pair contains a SO_DECL per stream.
2690 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
2691 const struct pipe_stream_output
*output
= &info
->output
[i
];
2692 const int buffer
= output
->output_buffer
;
2693 const int varying
= output
->register_index
;
2694 const unsigned stream_id
= output
->stream
;
2695 assert(stream_id
< MAX_VERTEX_STREAMS
);
2697 buffer_mask
[stream_id
] |= 1 << buffer
;
2699 assert(vue_map
->varying_to_slot
[varying
] >= 0);
2701 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
2702 * array. Instead, it simply increments DstOffset for the following
2703 * input by the number of components that should be skipped.
2705 * Our hardware is unusual in that it requires us to program SO_DECLs
2706 * for fake "hole" components, rather than simply taking the offset
2707 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
2708 * program as many size = 4 holes as we can, then a final hole to
2709 * accommodate the final 1, 2, or 3 remaining.
2711 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
2713 while (skip_components
> 0) {
2714 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2716 .OutputBufferSlot
= output
->output_buffer
,
2717 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
2719 skip_components
-= 4;
2722 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
2724 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2725 .OutputBufferSlot
= output
->output_buffer
,
2726 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
2728 ((1 << output
->num_components
) - 1) << output
->start_component
,
2731 if (decls
[stream_id
] > max_decls
)
2732 max_decls
= decls
[stream_id
];
2735 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
2736 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
2737 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
2739 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
2740 int urb_entry_read_offset
= 0;
2741 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
2742 urb_entry_read_offset
;
2744 /* We always read the whole vertex. This could be reduced at some
2745 * point by reading less and offsetting the register index in the
2748 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
2749 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
2750 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
2751 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
2752 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
2753 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
2754 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
2755 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
2757 /* Set buffer pitches; 0 means unbound. */
2758 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
2759 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
2760 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
2761 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
2764 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
2765 list
.DWordLength
= 3 + 2 * max_decls
- 2;
2766 list
.StreamtoBufferSelects0
= buffer_mask
[0];
2767 list
.StreamtoBufferSelects1
= buffer_mask
[1];
2768 list
.StreamtoBufferSelects2
= buffer_mask
[2];
2769 list
.StreamtoBufferSelects3
= buffer_mask
[3];
2770 list
.NumEntries0
= decls
[0];
2771 list
.NumEntries1
= decls
[1];
2772 list
.NumEntries2
= decls
[2];
2773 list
.NumEntries3
= decls
[3];
2776 for (int i
= 0; i
< max_decls
; i
++) {
2777 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
2778 entry
.Stream0Decl
= so_decl
[0][i
];
2779 entry
.Stream1Decl
= so_decl
[1][i
];
2780 entry
.Stream2Decl
= so_decl
[2][i
];
2781 entry
.Stream3Decl
= so_decl
[3][i
];
2789 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
2790 const struct brw_vue_map
*last_vue_map
,
2791 bool two_sided_color
,
2792 unsigned *out_offset
,
2793 unsigned *out_length
)
2795 /* The compiler computes the first URB slot without considering COL/BFC
2796 * swizzling (because it doesn't know whether it's enabled), so we need
2797 * to do that here too. This may result in a smaller offset, which
2800 const unsigned first_slot
=
2801 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
2803 /* This becomes the URB read offset (counted in pairs of slots). */
2804 assert(first_slot
% 2 == 0);
2805 *out_offset
= first_slot
/ 2;
2807 /* We need to adjust the inputs read to account for front/back color
2808 * swizzling, as it can make the URB length longer.
2810 for (int c
= 0; c
<= 1; c
++) {
2811 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
2812 /* If two sided color is enabled, the fragment shader's gl_Color
2813 * (COL0) input comes from either the gl_FrontColor (COL0) or
2814 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
2816 if (two_sided_color
)
2817 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2819 /* If front color isn't written, we opt to give them back color
2820 * instead of an undefined value. Switch from COL to BFC.
2822 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
2823 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
2824 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2829 /* Compute the minimum URB Read Length necessary for the FS inputs.
2831 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
2832 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
2834 * "This field should be set to the minimum length required to read the
2835 * maximum source attribute. The maximum source attribute is indicated
2836 * by the maximum value of the enabled Attribute # Source Attribute if
2837 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
2838 * enable is not set.
2839 * read_length = ceiling((max_source_attr + 1) / 2)
2841 * [errata] Corruption/Hang possible if length programmed larger than
2844 * Similar text exists for Ivy Bridge.
2846 * We find the last URB slot that's actually read by the FS.
2848 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
2849 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
2850 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
2853 /* The URB read length is the difference of the two, counted in pairs. */
2854 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
2858 iris_emit_sbe_swiz(struct iris_batch
*batch
,
2859 const struct iris_context
*ice
,
2860 unsigned urb_read_offset
,
2861 unsigned sprite_coord_enables
)
2863 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
2864 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2865 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2866 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
2867 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2869 /* XXX: this should be generated when putting programs in place */
2871 // XXX: raster->sprite_coord_enable
2873 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
2874 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
2875 if (input_index
< 0 || input_index
>= 16)
2878 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
2879 &attr_overrides
[input_index
];
2880 int slot
= vue_map
->varying_to_slot
[fs_attr
];
2882 /* Viewport and Layer are stored in the VUE header. We need to override
2883 * them to zero if earlier stages didn't write them, as GL requires that
2884 * they read back as zero when not explicitly set.
2887 case VARYING_SLOT_VIEWPORT
:
2888 case VARYING_SLOT_LAYER
:
2889 attr
->ComponentOverrideX
= true;
2890 attr
->ComponentOverrideW
= true;
2891 attr
->ConstantSource
= CONST_0000
;
2893 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
2894 attr
->ComponentOverrideY
= true;
2895 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
2896 attr
->ComponentOverrideZ
= true;
2899 case VARYING_SLOT_PRIMITIVE_ID
:
2900 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
2902 attr
->ComponentOverrideX
= true;
2903 attr
->ComponentOverrideY
= true;
2904 attr
->ComponentOverrideZ
= true;
2905 attr
->ComponentOverrideW
= true;
2906 attr
->ConstantSource
= PRIM_ID
;
2914 if (sprite_coord_enables
& (1 << input_index
))
2917 /* If there was only a back color written but not front, use back
2918 * as the color instead of undefined.
2920 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
2921 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
2922 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
2923 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
2925 /* Not written by the previous stage - undefined. */
2927 attr
->ComponentOverrideX
= true;
2928 attr
->ComponentOverrideY
= true;
2929 attr
->ComponentOverrideZ
= true;
2930 attr
->ComponentOverrideW
= true;
2931 attr
->ConstantSource
= CONST_0001_FLOAT
;
2935 /* Compute the location of the attribute relative to the read offset,
2936 * which is counted in 256-bit increments (two 128-bit VUE slots).
2938 const int source_attr
= slot
- 2 * urb_read_offset
;
2939 assert(source_attr
>= 0 && source_attr
<= 32);
2940 attr
->SourceAttribute
= source_attr
;
2942 /* If we are doing two-sided color, and the VUE slot following this one
2943 * represents a back-facing color, then we need to instruct the SF unit
2944 * to do back-facing swizzling.
2946 if (cso_rast
->light_twoside
&&
2947 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
2948 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
2949 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
2950 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
2951 attr
->SwizzleSelect
= INPUTATTR_FACING
;
2954 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
2955 for (int i
= 0; i
< 16; i
++)
2956 sbes
.Attribute
[i
] = attr_overrides
[i
];
2961 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
2962 const struct iris_rasterizer_state
*cso
)
2964 unsigned overrides
= 0;
2966 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
2967 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
2969 for (int i
= 0; i
< 8; i
++) {
2970 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
2971 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
2972 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
2979 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
2981 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2982 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2983 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2984 const struct shader_info
*fs_info
=
2985 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
2987 unsigned urb_read_offset
, urb_read_length
;
2988 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
2989 ice
->shaders
.last_vue_map
,
2990 cso_rast
->light_twoside
,
2991 &urb_read_offset
, &urb_read_length
);
2993 unsigned sprite_coord_overrides
=
2994 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
2996 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
2997 sbe
.AttributeSwizzleEnable
= true;
2998 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2999 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3000 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3001 sbe
.VertexURBEntryReadLength
= urb_read_length
;
3002 sbe
.ForceVertexURBEntryReadOffset
= true;
3003 sbe
.ForceVertexURBEntryReadLength
= true;
3004 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3005 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
3007 for (int i
= 0; i
< 32; i
++) {
3008 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3012 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
3015 /* ------------------------------------------------------------------- */
3018 * Populate VS program key fields based on the current state.
3021 iris_populate_vs_key(const struct iris_context
*ice
,
3022 const struct shader_info
*info
,
3023 struct brw_vs_prog_key
*key
)
3025 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3027 if (info
->clip_distance_array_size
== 0 &&
3028 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)))
3029 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3033 * Populate TCS program key fields based on the current state.
3036 iris_populate_tcs_key(const struct iris_context
*ice
,
3037 struct brw_tcs_prog_key
*key
)
3042 * Populate TES program key fields based on the current state.
3045 iris_populate_tes_key(const struct iris_context
*ice
,
3046 struct brw_tes_prog_key
*key
)
3051 * Populate GS program key fields based on the current state.
3054 iris_populate_gs_key(const struct iris_context
*ice
,
3055 struct brw_gs_prog_key
*key
)
3060 * Populate FS program key fields based on the current state.
3063 iris_populate_fs_key(const struct iris_context
*ice
,
3064 struct brw_wm_prog_key
*key
)
3066 /* XXX: dirty flags? */
3067 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3068 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3069 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3070 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3072 key
->nr_color_regions
= fb
->nr_cbufs
;
3074 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3076 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
3077 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
3079 /* XXX: only bother if COL0/1 are read */
3080 key
->flat_shade
= rast
->flatshade
;
3082 key
->persample_interp
= rast
->force_persample_interp
;
3083 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3085 key
->coherent_fb_fetch
= true;
3087 // XXX: uint64_t input_slots_valid; - for >16 inputs
3089 // XXX: key->force_dual_color_blend for unigine
3090 // XXX: respect hint for high_quality_derivatives:1;
3094 iris_populate_cs_key(const struct iris_context
*ice
,
3095 struct brw_cs_prog_key
*key
)
3100 // XXX: these need to go in INIT_THREAD_DISPATCH_FIELDS
3101 pkt
.SamplerCount
= \
3102 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4); \
3107 KSP(const struct iris_compiled_shader
*shader
)
3109 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3110 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3113 // Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3114 // prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3115 // this WA on C0 stepping.
3117 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3118 pkt.KernelStartPointer = KSP(shader); \
3119 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3120 prog_data->binding_table.size_bytes / 4; \
3121 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3123 pkt.DispatchGRFStartRegisterForURBData = \
3124 prog_data->dispatch_grf_start_reg; \
3125 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3126 pkt.prefix##URBEntryReadOffset = 0; \
3128 pkt.StatisticsEnable = true; \
3129 pkt.Enable = true; \
3131 if (prog_data->total_scratch) { \
3132 uint32_t scratch_addr = \
3133 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3134 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3135 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3139 * Encode most of 3DSTATE_VS based on the compiled shader.
3142 iris_store_vs_state(struct iris_context
*ice
,
3143 const struct gen_device_info
*devinfo
,
3144 struct iris_compiled_shader
*shader
)
3146 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3147 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3149 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3150 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3151 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3152 vs
.SIMD8DispatchEnable
= true;
3153 vs
.UserClipDistanceCullTestEnableBitmask
=
3154 vue_prog_data
->cull_distance_mask
;
3159 * Encode most of 3DSTATE_HS based on the compiled shader.
3162 iris_store_tcs_state(struct iris_context
*ice
,
3163 const struct gen_device_info
*devinfo
,
3164 struct iris_compiled_shader
*shader
)
3166 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3167 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3168 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3170 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3171 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3173 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3174 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3175 hs
.IncludeVertexHandles
= true;
3180 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3183 iris_store_tes_state(struct iris_context
*ice
,
3184 const struct gen_device_info
*devinfo
,
3185 struct iris_compiled_shader
*shader
)
3187 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3188 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3189 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3191 uint32_t *te_state
= (void *) shader
->derived_data
;
3192 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3194 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3195 te
.Partitioning
= tes_prog_data
->partitioning
;
3196 te
.OutputTopology
= tes_prog_data
->output_topology
;
3197 te
.TEDomain
= tes_prog_data
->domain
;
3199 te
.MaximumTessellationFactorOdd
= 63.0;
3200 te
.MaximumTessellationFactorNotOdd
= 64.0;
3203 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3204 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3206 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3207 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3208 ds
.ComputeWCoordinateEnable
=
3209 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3211 ds
.UserClipDistanceCullTestEnableBitmask
=
3212 vue_prog_data
->cull_distance_mask
;
3218 * Encode most of 3DSTATE_GS based on the compiled shader.
3221 iris_store_gs_state(struct iris_context
*ice
,
3222 const struct gen_device_info
*devinfo
,
3223 struct iris_compiled_shader
*shader
)
3225 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3226 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3227 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3229 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3230 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3232 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3233 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3234 gs
.ControlDataHeaderSize
=
3235 gs_prog_data
->control_data_header_size_hwords
;
3236 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3237 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3238 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3239 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3240 gs
.ReorderMode
= TRAILING
;
3241 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3242 gs
.MaximumNumberofThreads
=
3243 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3244 : (devinfo
->max_gs_threads
- 1);
3246 if (gs_prog_data
->static_vertex_count
!= -1) {
3247 gs
.StaticOutput
= true;
3248 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3250 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3252 gs
.UserClipDistanceCullTestEnableBitmask
=
3253 vue_prog_data
->cull_distance_mask
;
3255 const int urb_entry_write_offset
= 1;
3256 const uint32_t urb_entry_output_length
=
3257 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3258 urb_entry_write_offset
;
3260 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3261 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3266 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3269 iris_store_fs_state(struct iris_context
*ice
,
3270 const struct gen_device_info
*devinfo
,
3271 struct iris_compiled_shader
*shader
)
3273 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3274 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3276 uint32_t *ps_state
= (void *) shader
->derived_data
;
3277 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3279 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3280 ps
.VectorMaskEnable
= true;
3281 //ps.SamplerCount = ...
3282 // XXX: WABTPPrefetchDisable, see above, drop at C0
3283 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3284 prog_data
->binding_table
.size_bytes
/ 4;
3285 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3286 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3288 ps
.PushConstantEnable
= shader
->num_system_values
> 0 ||
3289 prog_data
->ubo_ranges
[0].length
> 0;
3291 /* From the documentation for this packet:
3292 * "If the PS kernel does not need the Position XY Offsets to
3293 * compute a Position Value, then this field should be programmed
3294 * to POSOFFSET_NONE."
3296 * "SW Recommendation: If the PS kernel needs the Position Offsets
3297 * to compute a Position XY value, this field should match Position
3298 * ZW Interpolation Mode to ensure a consistent position.xyzw
3301 * We only require XY sample offsets. So, this recommendation doesn't
3302 * look useful at the moment. We might need this in future.
3304 ps
.PositionXYOffsetSelect
=
3305 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3306 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
3307 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
3308 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
3310 // XXX: Disable SIMD32 with 16x MSAA
3312 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3313 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
3314 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
3315 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
3316 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3317 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
3319 ps
.KernelStartPointer0
=
3320 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
3321 ps
.KernelStartPointer1
=
3322 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
3323 ps
.KernelStartPointer2
=
3324 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
3326 if (prog_data
->total_scratch
) {
3327 uint32_t scratch_addr
=
3328 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3329 MESA_SHADER_FRAGMENT
);
3330 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3331 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3335 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3336 psx
.PixelShaderValid
= true;
3337 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3338 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
3339 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3340 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3341 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3342 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3344 if (wm_prog_data
->uses_sample_mask
) {
3345 /* TODO: conservative rasterization */
3346 if (wm_prog_data
->post_depth_coverage
)
3347 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
3349 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
3352 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3353 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3354 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3361 * Compute the size of the derived data (shader command packets).
3363 * This must match the data written by the iris_store_xs_state() functions.
3366 iris_store_cs_state(struct iris_context
*ice
,
3367 const struct gen_device_info
*devinfo
,
3368 struct iris_compiled_shader
*shader
)
3370 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3371 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3372 void *map
= shader
->derived_data
;
3374 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3375 desc
.KernelStartPointer
= KSP(shader
);
3376 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3377 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3378 desc
.SharedLocalMemorySize
=
3379 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3380 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3381 desc
.CrossThreadConstantDataReadLength
=
3382 cs_prog_data
->push
.cross_thread
.regs
;
3387 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3389 assert(cache_id
<= IRIS_CACHE_BLORP
);
3391 static const unsigned dwords
[] = {
3392 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3393 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3394 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3395 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3397 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3398 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3399 [IRIS_CACHE_BLORP
] = 0,
3402 return sizeof(uint32_t) * dwords
[cache_id
];
3406 * Create any state packets corresponding to the given shader stage
3407 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3408 * This means that we can look up a program in the in-memory cache and
3409 * get most of the state packet without having to reconstruct it.
3412 iris_store_derived_program_state(struct iris_context
*ice
,
3413 enum iris_program_cache_id cache_id
,
3414 struct iris_compiled_shader
*shader
)
3416 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3417 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3421 iris_store_vs_state(ice
, devinfo
, shader
);
3423 case IRIS_CACHE_TCS
:
3424 iris_store_tcs_state(ice
, devinfo
, shader
);
3426 case IRIS_CACHE_TES
:
3427 iris_store_tes_state(ice
, devinfo
, shader
);
3430 iris_store_gs_state(ice
, devinfo
, shader
);
3433 iris_store_fs_state(ice
, devinfo
, shader
);
3436 iris_store_cs_state(ice
, devinfo
, shader
);
3437 case IRIS_CACHE_BLORP
:
3444 /* ------------------------------------------------------------------- */
3447 * Configure the URB.
3449 * XXX: write a real comment.
3452 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
3454 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
3455 const unsigned push_size_kB
= 32;
3456 unsigned entries
[4];
3460 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3461 if (!ice
->shaders
.prog
[i
]) {
3464 struct brw_vue_prog_data
*vue_prog_data
=
3465 (void *) ice
->shaders
.prog
[i
]->prog_data
;
3466 size
[i
] = vue_prog_data
->urb_entry_size
;
3468 assert(size
[i
] != 0);
3471 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
3472 1024 * ice
->shaders
.urb_size
,
3473 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
3474 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
3475 size
, entries
, start
);
3477 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3478 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
3479 urb
._3DCommandSubOpcode
+= i
;
3480 urb
.VSURBStartingAddress
= start
[i
];
3481 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
3482 urb
.VSNumberofURBEntries
= entries
[i
];
3487 static const uint32_t push_constant_opcodes
[] = {
3488 [MESA_SHADER_VERTEX
] = 21,
3489 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3490 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3491 [MESA_SHADER_GEOMETRY
] = 22,
3492 [MESA_SHADER_FRAGMENT
] = 23,
3493 [MESA_SHADER_COMPUTE
] = 0,
3497 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3499 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3501 iris_use_pinned_bo(batch
, state_bo
, false);
3503 return ice
->state
.unbound_tex
.offset
;
3507 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3509 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3510 if (!ice
->state
.null_fb
.res
)
3511 return use_null_surface(batch
, ice
);
3513 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3515 iris_use_pinned_bo(batch
, state_bo
, false);
3517 return ice
->state
.null_fb
.offset
;
3521 * Add a surface to the validation list, as well as the buffer containing
3522 * the corresponding SURFACE_STATE.
3524 * Returns the binding table entry (offset to SURFACE_STATE).
3527 use_surface(struct iris_batch
*batch
,
3528 struct pipe_surface
*p_surf
,
3531 struct iris_surface
*surf
= (void *) p_surf
;
3533 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
3534 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
3536 return surf
->surface_state
.offset
;
3540 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
3542 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
3543 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
3545 return isv
->surface_state
.offset
;
3549 use_const_buffer(struct iris_batch
*batch
,
3550 struct iris_context
*ice
,
3551 struct iris_const_buffer
*cbuf
)
3553 if (!cbuf
->surface_state
.res
)
3554 return use_null_surface(batch
, ice
);
3556 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->data
.res
), false);
3557 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->surface_state
.res
), false);
3559 return cbuf
->surface_state
.offset
;
3563 use_ssbo(struct iris_batch
*batch
, struct iris_context
*ice
,
3564 struct iris_shader_state
*shs
, int i
)
3567 return use_null_surface(batch
, ice
);
3569 struct iris_state_ref
*surf_state
= &shs
->ssbo_surface_state
[i
];
3571 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->ssbo
[i
]), true);
3572 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3574 return surf_state
->offset
;
3578 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
3579 struct iris_shader_state
*shs
, int i
)
3581 if (!shs
->image
[i
].res
)
3582 return use_null_surface(batch
, ice
);
3584 struct iris_state_ref
*surf_state
= &shs
->image
[i
].surface_state
;
3586 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->image
[i
].res
),
3587 shs
->image
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
);
3588 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3590 return surf_state
->offset
;
3593 #define push_bt_entry(addr) \
3594 assert(addr >= binder_addr); \
3595 assert(s < prog_data->binding_table.size_bytes / sizeof(uint32_t)); \
3596 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
3598 #define bt_assert(section, exists) \
3599 if (!pin_only) assert(prog_data->binding_table.section == \
3600 (exists) ? s : 0xd0d0d0d0)
3603 * Populate the binding table for a given shader stage.
3605 * This fills out the table of pointers to surfaces required by the shader,
3606 * and also adds those buffers to the validation list so the kernel can make
3607 * resident before running our batch.
3610 iris_populate_binding_table(struct iris_context
*ice
,
3611 struct iris_batch
*batch
,
3612 gl_shader_stage stage
,
3615 const struct iris_binder
*binder
= &ice
->state
.binder
;
3616 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3620 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3621 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3622 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
3624 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
3625 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
3628 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
3630 /* TCS passthrough doesn't need a binding table. */
3631 assert(stage
== MESA_SHADER_TESS_CTRL
);
3635 if (stage
== MESA_SHADER_COMPUTE
) {
3636 /* surface for gl_NumWorkGroups */
3637 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
3638 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
3639 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
3640 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
3641 push_bt_entry(grid_state
->offset
);
3644 if (stage
== MESA_SHADER_FRAGMENT
) {
3645 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3646 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
3647 if (cso_fb
->nr_cbufs
) {
3648 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
3650 cso_fb
->cbufs
[i
] ? use_surface(batch
, cso_fb
->cbufs
[i
], true)
3651 : use_null_fb_surface(batch
, ice
);
3652 push_bt_entry(addr
);
3655 uint32_t addr
= use_null_fb_surface(batch
, ice
);
3656 push_bt_entry(addr
);
3660 bt_assert(texture_start
, info
->num_textures
> 0);
3662 for (int i
= 0; i
< info
->num_textures
; i
++) {
3663 struct iris_sampler_view
*view
= shs
->textures
[i
];
3664 uint32_t addr
= view
? use_sampler_view(batch
, view
)
3665 : use_null_surface(batch
, ice
);
3666 push_bt_entry(addr
);
3669 bt_assert(image_start
, info
->num_images
> 0);
3671 for (int i
= 0; i
< info
->num_images
; i
++) {
3672 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
3673 push_bt_entry(addr
);
3676 const int num_ubos
= iris_get_shader_num_ubos(ice
, stage
);
3678 bt_assert(ubo_start
, num_ubos
> 0);
3680 for (int i
= 0; i
< num_ubos
; i
++) {
3681 uint32_t addr
= use_const_buffer(batch
, ice
, &shs
->constbuf
[i
]);
3682 push_bt_entry(addr
);
3685 bt_assert(ssbo_start
, info
->num_abos
+ info
->num_ssbos
> 0);
3687 /* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
3688 * for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
3689 * in st_atom_storagebuf.c so it'll compact them into one range, with
3690 * SSBOs starting at info->num_abos. Ideally it'd reset num_abos to 0 too
3692 if (info
->num_abos
+ info
->num_ssbos
> 0) {
3693 for (int i
= 0; i
< IRIS_MAX_ABOS
+ info
->num_ssbos
; i
++) {
3694 uint32_t addr
= use_ssbo(batch
, ice
, shs
, i
);
3695 push_bt_entry(addr
);
3700 // XXX: not implemented yet
3701 bt_assert(plane_start
[1], ...);
3702 bt_assert(plane_start
[2], ...);
3707 iris_use_optional_res(struct iris_batch
*batch
,
3708 struct pipe_resource
*res
,
3712 struct iris_bo
*bo
= iris_resource_bo(res
);
3713 iris_use_pinned_bo(batch
, bo
, writeable
);
3717 /* ------------------------------------------------------------------- */
3720 * Pin any BOs which were installed by a previous batch, and restored
3721 * via the hardware logical context mechanism.
3723 * We don't need to re-emit all state every batch - the hardware context
3724 * mechanism will save and restore it for us. This includes pointers to
3725 * various BOs...which won't exist unless we ask the kernel to pin them
3726 * by adding them to the validation list.
3728 * We can skip buffers if we've re-emitted those packets, as we're
3729 * overwriting those stale pointers with new ones, and don't actually
3730 * refer to the old BOs.
3733 iris_restore_render_saved_bos(struct iris_context
*ice
,
3734 struct iris_batch
*batch
,
3735 const struct pipe_draw_info
*draw
)
3737 // XXX: whack IRIS_SHADER_DIRTY_BINDING_TABLE on new batch
3739 const uint64_t clean
= ~ice
->state
.dirty
;
3741 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
3742 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
3745 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3746 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
3749 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
3750 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
3753 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3754 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
3757 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
3758 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
3761 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3762 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
3765 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3766 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3771 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3773 for (int i
= 0; i
< 4; i
++) {
3774 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3776 if (range
->length
== 0)
3779 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3780 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3783 iris_use_pinned_bo(batch
, res
->bo
, false);
3785 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3789 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3790 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
3791 /* Re-pin any buffers referred to by the binding table. */
3792 iris_populate_binding_table(ice
, batch
, stage
, true);
3796 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3797 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3798 struct pipe_resource
*res
= shs
->sampler_table
.res
;
3800 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3803 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3804 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
3805 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3807 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3808 iris_use_pinned_bo(batch
, bo
, false);
3811 // XXX: scratch buffer
3815 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
3816 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3818 if (cso_fb
->zsbuf
) {
3819 struct iris_resource
*zres
, *sres
;
3820 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
3822 // XXX: might not be writable...
3824 iris_use_pinned_bo(batch
, zres
->bo
, true);
3826 iris_use_pinned_bo(batch
, sres
->bo
, true);
3830 if (draw
->index_size
== 0 && ice
->state
.last_res
.index_buffer
) {
3831 /* This draw didn't emit a new index buffer, so we are inheriting the
3832 * older index buffer. This draw didn't need it, but future ones may.
3834 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
3835 iris_use_pinned_bo(batch
, bo
, false);
3838 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
3839 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
3840 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
3841 struct iris_resource
*res
= (void *) cso
->resources
[i
];
3842 iris_use_pinned_bo(batch
, res
->bo
, false);
3848 iris_restore_compute_saved_bos(struct iris_context
*ice
,
3849 struct iris_batch
*batch
,
3850 const struct pipe_grid_info
*grid
)
3852 const uint64_t clean
= ~ice
->state
.dirty
;
3854 const int stage
= MESA_SHADER_COMPUTE
;
3855 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3857 if (clean
& IRIS_DIRTY_CONSTANTS_CS
) {
3858 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3861 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3862 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[0];
3864 if (range
->length
> 0) {
3865 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3866 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3869 iris_use_pinned_bo(batch
, res
->bo
, false);
3871 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3876 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
3877 /* Re-pin any buffers referred to by the binding table. */
3878 iris_populate_binding_table(ice
, batch
, stage
, true);
3881 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
3883 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
3885 if (clean
& IRIS_DIRTY_CS
) {
3886 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3888 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3889 iris_use_pinned_bo(batch
, bo
, false);
3892 // XXX: scratch buffer
3897 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
3900 iris_update_surface_base_address(struct iris_batch
*batch
,
3901 struct iris_binder
*binder
)
3903 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
3906 flush_for_state_base_change(batch
);
3908 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
3909 // XXX: sba.SurfaceStateMemoryObjectControlState = MOCS_WB;
3910 sba
.SurfaceStateBaseAddressModifyEnable
= true;
3911 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
3914 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
3918 iris_upload_dirty_render_state(struct iris_context
*ice
,
3919 struct iris_batch
*batch
,
3920 const struct pipe_draw_info
*draw
)
3922 const uint64_t dirty
= ice
->state
.dirty
;
3924 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
3927 struct iris_genx_state
*genx
= ice
->state
.genx
;
3928 struct iris_binder
*binder
= &ice
->state
.binder
;
3929 struct brw_wm_prog_data
*wm_prog_data
= (void *)
3930 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3932 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
3933 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3934 uint32_t cc_vp_address
;
3936 /* XXX: could avoid streaming for depth_clip [0,1] case. */
3937 uint32_t *cc_vp_map
=
3938 stream_state(batch
, ice
->state
.dynamic_uploader
,
3939 &ice
->state
.last_res
.cc_vp
,
3940 4 * ice
->state
.num_viewports
*
3941 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
3942 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
3944 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
3945 cso_rast
->clip_halfz
, &zmin
, &zmax
);
3946 if (cso_rast
->depth_clip_near
)
3948 if (cso_rast
->depth_clip_far
)
3951 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
3952 ccv
.MinimumDepth
= zmin
;
3953 ccv
.MaximumDepth
= zmax
;
3956 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
3959 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
3960 ptr
.CCViewportPointer
= cc_vp_address
;
3964 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3965 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
3966 ptr
.SFClipViewportPointer
=
3967 emit_state(batch
, ice
->state
.dynamic_uploader
,
3968 &ice
->state
.last_res
.sf_cl_vp
,
3969 genx
->sf_cl_vp
, 4 * GENX(SF_CLIP_VIEWPORT_length
) *
3970 ice
->state
.num_viewports
, 64);
3976 // XXX: this is only flagged at setup, we assume a static configuration
3977 if (dirty
& IRIS_DIRTY_URB
) {
3978 iris_upload_urb_config(ice
, batch
);
3981 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
3982 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
3983 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3984 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
3985 const int header_dwords
= GENX(BLEND_STATE_length
);
3986 const int rt_dwords
= cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
);
3987 uint32_t blend_offset
;
3988 uint32_t *blend_map
=
3989 stream_state(batch
, ice
->state
.dynamic_uploader
,
3990 &ice
->state
.last_res
.blend
,
3991 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
3993 uint32_t blend_state_header
;
3994 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
3995 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
3996 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
3999 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4000 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4002 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4003 ptr
.BlendStatePointer
= blend_offset
;
4004 ptr
.BlendStatePointerValid
= true;
4008 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4009 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4012 stream_state(batch
, ice
->state
.dynamic_uploader
,
4013 &ice
->state
.last_res
.color_calc
,
4014 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4016 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4017 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4018 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4019 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4020 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4021 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4022 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4024 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4025 ptr
.ColorCalcStatePointer
= cc_offset
;
4026 ptr
.ColorCalcStatePointerValid
= true;
4030 /* Upload constants for TCS passthrough. */
4031 if ((dirty
& IRIS_DIRTY_CONSTANTS_TCS
) &&
4032 ice
->shaders
.prog
[MESA_SHADER_TESS_CTRL
] &&
4033 !ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
]) {
4034 struct iris_compiled_shader
*tes_shader
= ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
4037 /* Passthrough always copies 2 vec4s, so when uploading data we ensure
4038 * it is in the right layout for TES.
4041 struct brw_tes_prog_data
*tes_prog_data
= (void *) tes_shader
->prog_data
;
4042 switch (tes_prog_data
->domain
) {
4043 case BRW_TESS_DOMAIN_QUAD
:
4044 for (int i
= 0; i
< 4; i
++)
4045 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4046 hdr
[3] = ice
->state
.default_inner_level
[0];
4047 hdr
[2] = ice
->state
.default_inner_level
[1];
4049 case BRW_TESS_DOMAIN_TRI
:
4050 for (int i
= 0; i
< 3; i
++)
4051 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4052 hdr
[4] = ice
->state
.default_inner_level
[0];
4054 case BRW_TESS_DOMAIN_ISOLINE
:
4055 hdr
[7] = ice
->state
.default_outer_level
[1];
4056 hdr
[6] = ice
->state
.default_outer_level
[0];
4060 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
4061 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
4062 u_upload_data(ice
->ctx
.const_uploader
, 0, sizeof(hdr
), 32,
4063 &hdr
[0], &cbuf
->data
.offset
,
4067 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4068 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4071 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4072 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4077 if (shs
->cbuf0_needs_upload
)
4078 upload_uniforms(ice
, stage
);
4080 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4082 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4083 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4085 /* The Skylake PRM contains the following restriction:
4087 * "The driver must ensure The following case does not occur
4088 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4089 * buffer 3 read length equal to zero committed followed by a
4090 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4093 * To avoid this, we program the buffers in the highest slots.
4094 * This way, slot 0 is only used if slot 3 is also used.
4098 for (int i
= 3; i
>= 0; i
--) {
4099 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4101 if (range
->length
== 0)
4104 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4105 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
4107 assert(cbuf
->data
.offset
% 32 == 0);
4109 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4110 pkt
.ConstantBody
.Buffer
[n
] =
4111 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->data
.offset
)
4112 : ro_bo(batch
->screen
->workaround_bo
, 0);
4119 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4120 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4121 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4122 ptr
._3DCommandSubOpcode
= 38 + stage
;
4123 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4128 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4129 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4130 iris_populate_binding_table(ice
, batch
, stage
, false);
4134 if (ice
->state
.need_border_colors
)
4135 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4137 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4138 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4139 !ice
->shaders
.prog
[stage
])
4142 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4143 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4145 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4147 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4148 ptr
._3DCommandSubOpcode
= 43 + stage
;
4149 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4153 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4154 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4156 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4157 if (ice
->state
.framebuffer
.samples
> 0)
4158 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4162 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4163 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4164 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
4168 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4169 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4172 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4175 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4176 iris_use_pinned_bo(batch
, cache
->bo
, false);
4177 iris_batch_emit(batch
, shader
->derived_data
,
4178 iris_derived_program_state_size(stage
));
4180 if (stage
== MESA_SHADER_TESS_EVAL
) {
4181 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4182 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4183 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4184 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4185 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4190 if (ice
->state
.streamout_active
) {
4191 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4192 iris_batch_emit(batch
, genx
->so_buffers
,
4193 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4194 for (int i
= 0; i
< 4; i
++) {
4195 struct iris_stream_output_target
*tgt
=
4196 (void *) ice
->state
.so_target
[i
];
4198 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4200 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4206 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
4207 uint32_t *decl_list
=
4208 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
4209 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
4212 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4213 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4215 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
4216 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
4217 sol
.SOFunctionEnable
= true;
4218 sol
.SOStatisticsEnable
= true;
4220 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
4221 !ice
->state
.prims_generated_query_active
;
4222 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
4225 assert(ice
->state
.streamout
);
4227 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
4228 GENX(3DSTATE_STREAMOUT_length
));
4231 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4232 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
4236 if (dirty
& IRIS_DIRTY_CLIP
) {
4237 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4238 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4240 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
4241 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
4242 if (wm_prog_data
->barycentric_interp_modes
&
4243 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
4244 cl
.NonPerspectiveBarycentricEnable
= true;
4246 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
4247 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
4249 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
4250 ARRAY_SIZE(cso_rast
->clip
));
4253 if (dirty
& IRIS_DIRTY_RASTER
) {
4254 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4255 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
4256 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
4260 /* XXX: FS program updates needs to flag IRIS_DIRTY_WM */
4261 if (dirty
& IRIS_DIRTY_WM
) {
4262 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4263 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
4265 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
4266 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4268 wm
.BarycentricInterpolationMode
=
4269 wm_prog_data
->barycentric_interp_modes
;
4271 if (wm_prog_data
->early_fragment_tests
)
4272 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
4273 else if (wm_prog_data
->has_side_effects
)
4274 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
4276 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
4279 if (dirty
& IRIS_DIRTY_SBE
) {
4280 iris_emit_sbe(batch
, ice
);
4283 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
4284 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4285 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4286 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
4287 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
4288 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
4289 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4292 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
4293 ARRAY_SIZE(cso_blend
->ps_blend
));
4296 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
4297 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4298 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4300 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
4301 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
4302 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4303 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4305 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
4308 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
4309 uint32_t scissor_offset
=
4310 emit_state(batch
, ice
->state
.dynamic_uploader
,
4311 &ice
->state
.last_res
.scissor
,
4312 ice
->state
.scissors
,
4313 sizeof(struct pipe_scissor_state
) *
4314 ice
->state
.num_viewports
, 32);
4316 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
4317 ptr
.ScissorRectPointer
= scissor_offset
;
4321 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
4322 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4323 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
4325 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
4327 if (cso_fb
->zsbuf
) {
4328 struct iris_resource
*zres
, *sres
;
4329 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
4331 // XXX: might not be writable...
4333 iris_use_pinned_bo(batch
, zres
->bo
, true);
4335 iris_use_pinned_bo(batch
, sres
->bo
, true);
4339 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
4340 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
4341 for (int i
= 0; i
< 32; i
++) {
4342 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
4347 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
4348 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4349 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
4352 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
4353 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
4354 topo
.PrimitiveTopologyType
=
4355 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
4359 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4360 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
4361 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
4363 if (cso
->num_buffers
> 0) {
4364 /* The VF cache designers cut corners, and made the cache key's
4365 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
4366 * 32 bits of the address. If you have two vertex buffers which get
4367 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
4368 * you can get collisions (even within a single batch).
4370 * So, we need to do a VF cache invalidate if the buffer for a VB
4371 * slot slot changes [48:32] address bits from the previous time.
4373 bool need_invalidate
= false;
4375 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
4376 uint16_t high_bits
= 0;
4378 struct iris_resource
*res
= (void *) cso
->resources
[i
];
4380 iris_use_pinned_bo(batch
, res
->bo
, false);
4382 high_bits
= res
->bo
->gtt_offset
>> 32ull;
4383 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
4384 need_invalidate
= true;
4385 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
4390 if (need_invalidate
) {
4391 iris_emit_pipe_control_flush(batch
,
4392 PIPE_CONTROL_VF_CACHE_INVALIDATE
);
4395 iris_batch_emit(batch
, cso
->vertex_buffers
, sizeof(uint32_t) *
4396 (1 + vb_dwords
* cso
->num_buffers
));
4400 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
4401 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4402 const unsigned entries
= MAX2(cso
->count
, 1);
4403 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
4404 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
4405 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
4406 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
4409 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
4410 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
4411 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
4412 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4414 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
4415 if (vs_prog_data
->uses_vertexid
) {
4416 sgv
.VertexIDEnable
= true;
4417 sgv
.VertexIDComponentNumber
= 2;
4418 sgv
.VertexIDElementOffset
= cso
->count
;
4421 if (vs_prog_data
->uses_instanceid
) {
4422 sgv
.InstanceIDEnable
= true;
4423 sgv
.InstanceIDComponentNumber
= 3;
4424 sgv
.InstanceIDElementOffset
= cso
->count
;
4429 if (dirty
& IRIS_DIRTY_VF
) {
4430 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
4431 if (draw
->primitive_restart
) {
4432 vf
.IndexedDrawCutIndexEnable
= true;
4433 vf
.CutIndex
= draw
->restart_index
;
4438 // XXX: Gen8 - PMA fix
4442 iris_upload_render_state(struct iris_context
*ice
,
4443 struct iris_batch
*batch
,
4444 const struct pipe_draw_info
*draw
)
4446 /* Always pin the binder. If we're emitting new binding table pointers,
4447 * we need it. If not, we're probably inheriting old tables via the
4448 * context, and need it anyway. Since true zero-bindings cases are
4449 * practically non-existent, just pin it and avoid last_res tracking.
4451 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
4453 if (!batch
->contains_draw
) {
4454 iris_restore_render_saved_bos(ice
, batch
, draw
);
4455 batch
->contains_draw
= true;
4458 iris_upload_dirty_render_state(ice
, batch
, draw
);
4460 if (draw
->index_size
> 0) {
4463 if (draw
->has_user_indices
) {
4464 u_upload_data(ice
->ctx
.stream_uploader
, 0,
4465 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
4466 &offset
, &ice
->state
.last_res
.index_buffer
);
4468 struct iris_resource
*res
= (void *) draw
->index
.resource
;
4469 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
4471 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
4472 draw
->index
.resource
);
4476 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4478 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
4479 ib
.IndexFormat
= draw
->index_size
>> 1;
4481 ib
.BufferSize
= bo
->size
;
4482 ib
.BufferStartingAddress
= ro_bo(bo
, offset
);
4485 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
4486 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
4487 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
4488 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_VF_CACHE_INVALIDATE
);
4489 ice
->state
.last_index_bo_high_bits
= high_bits
;
4493 #define _3DPRIM_END_OFFSET 0x2420
4494 #define _3DPRIM_START_VERTEX 0x2430
4495 #define _3DPRIM_VERTEX_COUNT 0x2434
4496 #define _3DPRIM_INSTANCE_COUNT 0x2438
4497 #define _3DPRIM_START_INSTANCE 0x243C
4498 #define _3DPRIM_BASE_VERTEX 0x2440
4500 if (draw
->indirect
) {
4501 /* We don't support this MultidrawIndirect. */
4502 assert(!draw
->indirect
->indirect_draw_count
);
4504 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
4507 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4508 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
4509 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
4511 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4512 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
4513 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
4515 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4516 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
4517 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
4519 if (draw
->index_size
) {
4520 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4521 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
4522 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4524 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4525 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4526 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
4529 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4530 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4531 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4533 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
4534 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
4540 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
4541 prim
.StartInstanceLocation
= draw
->start_instance
;
4542 prim
.InstanceCount
= draw
->instance_count
;
4543 prim
.VertexCountPerInstance
= draw
->count
;
4544 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
4545 prim
.PredicateEnable
= ice
->predicate
== IRIS_PREDICATE_STATE_USE_BIT
? 1 : 0;
4546 // XXX: this is probably bonkers.
4547 prim
.StartVertexLocation
= draw
->start
;
4549 prim
.IndirectParameterEnable
= draw
->indirect
!= NULL
;
4551 if (draw
->index_size
) {
4552 prim
.BaseVertexLocation
+= draw
->index_bias
;
4554 prim
.StartVertexLocation
+= draw
->index_bias
;
4557 //prim.BaseVertexLocation = ...;
4562 iris_upload_compute_state(struct iris_context
*ice
,
4563 struct iris_batch
*batch
,
4564 const struct pipe_grid_info
*grid
)
4566 const uint64_t dirty
= ice
->state
.dirty
;
4567 struct iris_screen
*screen
= batch
->screen
;
4568 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
4569 struct iris_binder
*binder
= &ice
->state
.binder
;
4570 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
4571 struct iris_compiled_shader
*shader
=
4572 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
4573 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4574 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
4576 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->cbuf0_needs_upload
)
4577 upload_uniforms(ice
, MESA_SHADER_COMPUTE
);
4579 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
4580 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
4582 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
4583 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
4585 if (ice
->state
.need_border_colors
)
4586 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4588 if (dirty
& IRIS_DIRTY_CS
) {
4589 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4591 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4592 * the only bits that are changed are scoreboard related: Scoreboard
4593 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
4594 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4597 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
4599 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4600 if (prog_data
->total_scratch
) {
4601 uint32_t scratch_addr
=
4602 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
4603 MESA_SHADER_COMPUTE
);
4604 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
4605 vfe
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
4608 vfe
.MaximumNumberofThreads
=
4609 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
4611 vfe
.ResetGatewayTimer
=
4612 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4615 vfe
.NumberofURBEntries
= 2;
4616 vfe
.URBEntryAllocationSize
= 2;
4618 // XXX: Use Indirect Payload Storage?
4619 vfe
.CURBEAllocationSize
=
4620 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4621 cs_prog_data
->push
.cross_thread
.regs
, 2);
4625 // XXX: hack iris_set_constant_buffers to upload these thread counts
4626 // XXX: along with regular uniforms for compute shaders, somehow.
4628 uint32_t curbe_data_offset
= 0;
4629 // TODO: Move subgroup-id into uniforms ubo so we can push uniforms
4630 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
4631 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
4632 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
4633 struct pipe_resource
*curbe_data_res
= NULL
;
4634 uint32_t *curbe_data_map
=
4635 stream_state(batch
, ice
->state
.dynamic_uploader
, &curbe_data_res
,
4636 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
4637 &curbe_data_offset
);
4638 assert(curbe_data_map
);
4639 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
4640 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
4642 if (dirty
& IRIS_DIRTY_CONSTANTS_CS
) {
4643 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4644 curbe
.CURBETotalDataLength
=
4645 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4646 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
4650 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
4651 IRIS_DIRTY_BINDINGS_CS
|
4652 IRIS_DIRTY_CONSTANTS_CS
|
4654 struct pipe_resource
*desc_res
= NULL
;
4655 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4657 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
4658 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
4659 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
4662 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
4663 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
4665 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4666 load
.InterfaceDescriptorTotalLength
=
4667 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4668 load
.InterfaceDescriptorDataStartAddress
=
4669 emit_state(batch
, ice
->state
.dynamic_uploader
,
4670 &desc_res
, desc
, sizeof(desc
), 32);
4673 pipe_resource_reference(&desc_res
, NULL
);
4676 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
4677 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
4678 uint32_t right_mask
;
4681 right_mask
= ~0u >> (32 - remainder
);
4683 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
4685 #define GPGPU_DISPATCHDIMX 0x2500
4686 #define GPGPU_DISPATCHDIMY 0x2504
4687 #define GPGPU_DISPATCHDIMZ 0x2508
4689 if (grid
->indirect
) {
4690 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
4691 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
4692 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4693 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
4694 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
4696 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4697 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
4698 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
4700 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4701 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
4702 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
4706 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
4707 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
4708 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
4709 ggw
.ThreadDepthCounterMaximum
= 0;
4710 ggw
.ThreadHeightCounterMaximum
= 0;
4711 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
4712 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
4713 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
4714 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
4715 ggw
.RightExecutionMask
= right_mask
;
4716 ggw
.BottomExecutionMask
= 0xffffffff;
4719 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4721 if (!batch
->contains_draw
) {
4722 iris_restore_compute_saved_bos(ice
, batch
, grid
);
4723 batch
->contains_draw
= true;
4728 * State module teardown.
4731 iris_destroy_state(struct iris_context
*ice
)
4733 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
4735 // XXX: unreference resources/surfaces.
4736 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
4737 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
4739 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
4741 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
4742 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4743 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
4745 free(ice
->state
.genx
);
4747 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
4748 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
4749 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
4750 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
4751 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
4752 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
4755 /* ------------------------------------------------------------------- */
4758 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t src
,
4761 _iris_emit_lrr(batch
, src
, dst
);
4765 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t src
,
4768 _iris_emit_lrr(batch
, src
, dst
);
4769 _iris_emit_lrr(batch
, src
+ 4, dst
+ 4);
4773 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
4776 _iris_emit_lri(batch
, reg
, val
);
4780 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
4783 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
4784 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
4788 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
4791 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
4792 struct iris_bo
*bo
, uint32_t offset
)
4794 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4795 lrm
.RegisterAddress
= reg
;
4796 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
4801 * Load a 64-bit value from a buffer into a MMIO register via
4802 * two MI_LOAD_REGISTER_MEM commands.
4805 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
4806 struct iris_bo
*bo
, uint32_t offset
)
4808 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
4809 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
4813 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
4814 struct iris_bo
*bo
, uint32_t offset
,
4817 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
4818 srm
.RegisterAddress
= reg
;
4819 srm
.MemoryAddress
= rw_bo(bo
, offset
);
4820 srm
.PredicateEnable
= predicated
;
4825 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
4826 struct iris_bo
*bo
, uint32_t offset
,
4829 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
4830 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
4834 iris_store_data_imm32(struct iris_batch
*batch
,
4835 struct iris_bo
*bo
, uint32_t offset
,
4838 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
4839 sdi
.Address
= rw_bo(bo
, offset
);
4840 sdi
.ImmediateData
= imm
;
4845 iris_store_data_imm64(struct iris_batch
*batch
,
4846 struct iris_bo
*bo
, uint32_t offset
,
4849 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
4850 * 2 in genxml but it's actually variable length and we need 5 DWords.
4852 void *map
= iris_get_command_space(batch
, 4 * 5);
4853 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
4854 sdi
.DWordLength
= 5 - 2;
4855 sdi
.Address
= rw_bo(bo
, offset
);
4856 sdi
.ImmediateData
= imm
;
4861 iris_copy_mem_mem(struct iris_batch
*batch
,
4862 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
4863 struct iris_bo
*src_bo
, uint32_t src_offset
,
4866 /* MI_COPY_MEM_MEM operates on DWords. */
4867 assert(bytes
% 4 == 0);
4868 assert(dst_offset
% 4 == 0);
4869 assert(src_offset
% 4 == 0);
4871 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
4872 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
4873 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
4874 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
4879 /* ------------------------------------------------------------------- */
4882 flags_to_post_sync_op(uint32_t flags
)
4884 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
4885 return WriteImmediateData
;
4887 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
4888 return WritePSDepthCount
;
4890 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
4891 return WriteTimestamp
;
4897 * Do the given flags have a Post Sync or LRI Post Sync operation?
4899 static enum pipe_control_flags
4900 get_post_sync_flags(enum pipe_control_flags flags
)
4902 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
4903 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
4904 PIPE_CONTROL_WRITE_TIMESTAMP
|
4905 PIPE_CONTROL_LRI_POST_SYNC_OP
;
4907 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
4908 * "LRI Post Sync Operation". So more than one bit set would be illegal.
4910 assert(util_bitcount(flags
) <= 1);
4915 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
4918 * Emit a series of PIPE_CONTROL commands, taking into account any
4919 * workarounds necessary to actually accomplish the caller's request.
4921 * Unless otherwise noted, spec quotations in this function come from:
4923 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
4924 * Restrictions for PIPE_CONTROL.
4926 * You should not use this function directly. Use the helpers in
4927 * iris_pipe_control.c instead, which may split the pipe control further.
4930 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
4931 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
4933 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
4934 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
4935 enum pipe_control_flags non_lri_post_sync_flags
=
4936 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
4938 /* Recursive PIPE_CONTROL workarounds --------------------------------
4939 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
4941 * We do these first because we want to look at the original operation,
4942 * rather than any workarounds we set.
4944 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
4945 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
4946 * lists several workarounds:
4948 * "Project: SKL, KBL, BXT
4950 * If the VF Cache Invalidation Enable is set to a 1 in a
4951 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
4952 * sets to 0, with the VF Cache Invalidation Enable set to 0
4953 * needs to be sent prior to the PIPE_CONTROL with VF Cache
4954 * Invalidation Enable set to a 1."
4956 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
4959 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
4960 /* Project: SKL / Argument: LRI Post Sync Operation [23]
4962 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
4963 * programmed prior to programming a PIPECONTROL command with "LRI
4964 * Post Sync Operation" in GPGPU mode of operation (i.e when
4965 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
4967 * The same text exists a few rows below for Post Sync Op.
4969 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
4972 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
4974 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
4975 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
4976 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
4978 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
4982 /* "Flush Types" workarounds ---------------------------------------------
4983 * We do these now because they may add post-sync operations or CS stalls.
4986 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
4987 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
4989 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
4990 * 'Write PS Depth Count' or 'Write Timestamp'."
4993 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
4994 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
4995 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
4996 bo
= batch
->screen
->workaround_bo
;
5000 /* #1130 from Gen10 workarounds page:
5002 * "Enable Depth Stall on every Post Sync Op if Render target Cache
5003 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
5004 * board stall if Render target cache flush is enabled."
5006 * Applicable to CNL B0 and C0 steppings only.
5008 * The wording here is unclear, and this workaround doesn't look anything
5009 * like the internal bug report recommendations, but leave it be for now...
5011 if (GEN_GEN
== 10) {
5012 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
5013 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5014 } else if (flags
& non_lri_post_sync_flags
) {
5015 flags
|= PIPE_CONTROL_DEPTH_STALL
;
5019 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
5020 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
5022 * "This bit must be DISABLED for operations other than writing
5025 * This seems like nonsense. An Ivybridge workaround requires us to
5026 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
5027 * operation. Gen8+ requires us to emit depth stalls and depth cache
5028 * flushes together. So, it's hard to imagine this means anything other
5029 * than "we originally intended this to be used for PS_DEPTH_COUNT".
5031 * We ignore the supposed restriction and do nothing.
5035 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5036 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5037 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
5039 * "This bit must be DISABLED for End-of-pipe (Read) fences,
5040 * PS_DEPTH_COUNT or TIMESTAMP queries."
5042 * TODO: Implement end-of-pipe checking.
5044 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5045 PIPE_CONTROL_WRITE_TIMESTAMP
)));
5048 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5049 /* From the PIPE_CONTROL instruction table, bit 1:
5051 * "This bit is ignored if Depth Stall Enable is set.
5052 * Further, the render cache is not flushed even if Write Cache
5053 * Flush Enable bit is set."
5055 * We assert that the caller doesn't do this combination, to try and
5056 * prevent mistakes. It shouldn't hurt the GPU, though.
5058 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
5059 * and "Render Target Flush" combo is explicitly required for BTI
5060 * update workarounds.
5062 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
5063 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
5066 /* PIPE_CONTROL page workarounds ------------------------------------- */
5068 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
5069 /* From the PIPE_CONTROL page itself:
5072 * Restriction: Pipe_control with CS-stall bit set must be issued
5073 * before a pipe-control command that has the State Cache
5074 * Invalidate bit set."
5076 flags
|= PIPE_CONTROL_CS_STALL
;
5079 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
5080 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
5083 * SW must always program Post-Sync Operation to "Write Immediate
5084 * Data" when Flush LLC is set."
5086 * For now, we just require the caller to do it.
5088 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
5091 /* "Post-Sync Operation" workarounds -------------------------------- */
5093 /* Project: All / Argument: Global Snapshot Count Reset [19]
5095 * "This bit must not be exercised on any product.
5096 * Requires stall bit ([20] of DW1) set."
5098 * We don't use this, so we just assert that it isn't used. The
5099 * PIPE_CONTROL instruction page indicates that they intended this
5100 * as a debug feature and don't think it is useful in production,
5101 * but it may actually be usable, should we ever want to.
5103 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
5105 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
5106 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
5107 /* Project: All / Arguments:
5109 * - Generic Media State Clear [16]
5110 * - Indirect State Pointers Disable [16]
5112 * "Requires stall bit ([20] of DW1) set."
5114 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
5115 * State Clear) says:
5117 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5118 * programmed prior to programming a PIPECONTROL command with "Media
5119 * State Clear" set in GPGPU mode of operation"
5121 * This is a subset of the earlier rule, so there's nothing to do.
5123 flags
|= PIPE_CONTROL_CS_STALL
;
5126 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
5127 /* Project: All / Argument: Store Data Index
5129 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5132 * For now, we just assert that the caller does this. We might want to
5133 * automatically add a write to the workaround BO...
5135 assert(non_lri_post_sync_flags
!= 0);
5138 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
5139 /* Project: All / Argument: Sync GFDT
5141 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5142 * than '0' or 0x2520[13] must be set."
5144 * For now, we just assert that the caller does this.
5146 assert(non_lri_post_sync_flags
!= 0);
5149 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
5150 /* Project: IVB+ / Argument: TLB inv
5152 * "Requires stall bit ([20] of DW1) set."
5154 * Also, from the PIPE_CONTROL instruction table:
5157 * Post Sync Operation or CS stall must be set to ensure a TLB
5158 * invalidation occurs. Otherwise no cycle will occur to the TLB
5159 * cache to invalidate."
5161 * This is not a subset of the earlier rule, so there's nothing to do.
5163 flags
|= PIPE_CONTROL_CS_STALL
;
5166 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
5167 /* TODO: The big Skylake GT4 post sync op workaround */
5170 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
5172 if (IS_COMPUTE_PIPELINE(batch
)) {
5173 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
5174 /* Project: SKL+ / Argument: Tex Invalidate
5175 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
5177 flags
|= PIPE_CONTROL_CS_STALL
;
5180 if (GEN_GEN
== 8 && (post_sync_flags
||
5181 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
5182 PIPE_CONTROL_DEPTH_STALL
|
5183 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5184 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5185 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
5186 /* Project: BDW / Arguments:
5188 * - LRI Post Sync Operation [23]
5189 * - Post Sync Op [15:14]
5191 * - Depth Stall [13]
5192 * - Render Target Cache Flush [12]
5193 * - Depth Cache Flush [0]
5194 * - DC Flush Enable [5]
5196 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
5199 flags
|= PIPE_CONTROL_CS_STALL
;
5201 /* Also, from the PIPE_CONTROL instruction table, bit 20:
5204 * This bit must be always set when PIPE_CONTROL command is
5205 * programmed by GPGPU and MEDIA workloads, except for the cases
5206 * when only Read Only Cache Invalidation bits are set (State
5207 * Cache Invalidation Enable, Instruction cache Invalidation
5208 * Enable, Texture Cache Invalidation Enable, Constant Cache
5209 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
5210 * need not implemented when FF_DOP_CG is disable via "Fixed
5211 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
5213 * It sounds like we could avoid CS stalls in some cases, but we
5214 * don't currently bother. This list isn't exactly the list above,
5220 /* "Stall" workarounds ----------------------------------------------
5221 * These have to come after the earlier ones because we may have added
5222 * some additional CS stalls above.
5225 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
5226 /* Project: PRE-SKL, VLV, CHV
5228 * "[All Stepping][All SKUs]:
5230 * One of the following must also be set:
5232 * - Render Target Cache Flush Enable ([12] of DW1)
5233 * - Depth Cache Flush Enable ([0] of DW1)
5234 * - Stall at Pixel Scoreboard ([1] of DW1)
5235 * - Depth Stall ([13] of DW1)
5236 * - Post-Sync Operation ([13] of DW1)
5237 * - DC Flush Enable ([5] of DW1)"
5239 * If we don't already have one of those bits set, we choose to add
5240 * "Stall at Pixel Scoreboard". Some of the other bits require a
5241 * CS stall as a workaround (see above), which would send us into
5242 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
5243 * appears to be safe, so we choose that.
5245 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5246 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5247 PIPE_CONTROL_WRITE_IMMEDIATE
|
5248 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5249 PIPE_CONTROL_WRITE_TIMESTAMP
|
5250 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
5251 PIPE_CONTROL_DEPTH_STALL
|
5252 PIPE_CONTROL_DATA_CACHE_FLUSH
;
5253 if (!(flags
& wa_bits
))
5254 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5257 /* Emit --------------------------------------------------------------- */
5259 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
5260 pc
.LRIPostSyncOperation
= NoLRIOperation
;
5261 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
5262 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
5263 pc
.StoreDataIndex
= 0;
5264 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
5265 pc
.GlobalSnapshotCountReset
=
5266 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
5267 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
5268 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
5269 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5270 pc
.RenderTargetCacheFlushEnable
=
5271 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
5272 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
5273 pc
.StateCacheInvalidationEnable
=
5274 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
5275 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
5276 pc
.ConstantCacheInvalidationEnable
=
5277 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
5278 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
5279 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
5280 pc
.InstructionCacheInvalidateEnable
=
5281 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
5282 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
5283 pc
.IndirectStatePointersDisable
=
5284 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
5285 pc
.TextureCacheInvalidationEnable
=
5286 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
5287 pc
.Address
= rw_bo(bo
, offset
);
5288 pc
.ImmediateData
= imm
;
5293 genX(init_state
)(struct iris_context
*ice
)
5295 struct pipe_context
*ctx
= &ice
->ctx
;
5296 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
5298 ctx
->create_blend_state
= iris_create_blend_state
;
5299 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
5300 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
5301 ctx
->create_sampler_state
= iris_create_sampler_state
;
5302 ctx
->create_sampler_view
= iris_create_sampler_view
;
5303 ctx
->create_surface
= iris_create_surface
;
5304 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
5305 ctx
->bind_blend_state
= iris_bind_blend_state
;
5306 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
5307 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
5308 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
5309 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
5310 ctx
->delete_blend_state
= iris_delete_state
;
5311 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
5312 ctx
->delete_fs_state
= iris_delete_state
;
5313 ctx
->delete_rasterizer_state
= iris_delete_state
;
5314 ctx
->delete_sampler_state
= iris_delete_state
;
5315 ctx
->delete_vertex_elements_state
= iris_delete_state
;
5316 ctx
->delete_tcs_state
= iris_delete_state
;
5317 ctx
->delete_tes_state
= iris_delete_state
;
5318 ctx
->delete_gs_state
= iris_delete_state
;
5319 ctx
->delete_vs_state
= iris_delete_state
;
5320 ctx
->set_blend_color
= iris_set_blend_color
;
5321 ctx
->set_clip_state
= iris_set_clip_state
;
5322 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
5323 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
5324 ctx
->set_shader_images
= iris_set_shader_images
;
5325 ctx
->set_sampler_views
= iris_set_sampler_views
;
5326 ctx
->set_tess_state
= iris_set_tess_state
;
5327 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
5328 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
5329 ctx
->set_sample_mask
= iris_set_sample_mask
;
5330 ctx
->set_scissor_states
= iris_set_scissor_states
;
5331 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
5332 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
5333 ctx
->set_viewport_states
= iris_set_viewport_states
;
5334 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
5335 ctx
->surface_destroy
= iris_surface_destroy
;
5336 ctx
->draw_vbo
= iris_draw_vbo
;
5337 ctx
->launch_grid
= iris_launch_grid
;
5338 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
5339 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
5340 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
5342 ice
->vtbl
.destroy_state
= iris_destroy_state
;
5343 ice
->vtbl
.init_render_context
= iris_init_render_context
;
5344 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
5345 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
5346 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
5347 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
5348 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
5349 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
5350 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
5351 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
5352 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
5353 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
5354 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
5355 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
5356 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
5357 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
5358 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
5359 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
5360 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
5361 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
5362 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
5363 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
5364 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
5365 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
5366 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
5367 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
5368 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
5370 ice
->state
.dirty
= ~0ull;
5372 ice
->state
.statistics_counters_enabled
= true;
5374 ice
->state
.sample_mask
= 0xffff;
5375 ice
->state
.num_viewports
= 1;
5376 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
5378 /* Make a 1x1x1 null surface for unbound textures */
5379 void *null_surf_map
=
5380 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
5381 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
5382 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
5383 ice
->state
.unbound_tex
.offset
+=
5384 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
5386 /* Default all scissor rectangles to be empty regions. */
5387 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
5388 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
5389 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,